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-rw-r--r--arch/powerpc/platforms/pasemi/setup.c27
-rw-r--r--include/asm-powerpc/reg.h6
2 files changed, 31 insertions, 2 deletions
diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c
index cabf7017c05e..2d9652b6acb3 100644
--- a/arch/powerpc/platforms/pasemi/setup.c
+++ b/arch/powerpc/platforms/pasemi/setup.c
@@ -48,13 +48,36 @@ static void pas_restart(char *cmd)
48} 48}
49 49
50#ifdef CONFIG_SMP 50#ifdef CONFIG_SMP
51static DEFINE_SPINLOCK(timebase_lock);
52
53static void __devinit pas_give_timebase(void)
54{
55 unsigned long tb;
56
57 spin_lock(&timebase_lock);
58 mtspr(SPRN_TBCTL, TBCTL_FREEZE);
59 tb = mftb();
60 mtspr(SPRN_TBCTL, TBCTL_UPDATE_LOWER | (tb & 0xffffffff));
61 mtspr(SPRN_TBCTL, TBCTL_UPDATE_UPPER | (tb >> 32));
62 mtspr(SPRN_TBCTL, TBCTL_RESTART);
63 spin_unlock(&timebase_lock);
64 pr_debug("pas_give_timebase: cpu %d gave tb %lx\n",
65 smp_processor_id(), tb);
66}
67
68static void __devinit pas_take_timebase(void)
69{
70 pr_debug("pas_take_timebase: cpu %d has tb %lx\n",
71 smp_processor_id(), mftb());
72}
73
51struct smp_ops_t pas_smp_ops = { 74struct smp_ops_t pas_smp_ops = {
52 .probe = smp_mpic_probe, 75 .probe = smp_mpic_probe,
53 .message_pass = smp_mpic_message_pass, 76 .message_pass = smp_mpic_message_pass,
54 .kick_cpu = smp_generic_kick_cpu, 77 .kick_cpu = smp_generic_kick_cpu,
55 .setup_cpu = smp_mpic_setup_cpu, 78 .setup_cpu = smp_mpic_setup_cpu,
56 .give_timebase = smp_generic_give_timebase, 79 .give_timebase = pas_give_timebase,
57 .take_timebase = smp_generic_take_timebase, 80 .take_timebase = pas_take_timebase,
58}; 81};
59#endif /* CONFIG_SMP */ 82#endif /* CONFIG_SMP */
60 83
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index 923df6ceaa5c..0d7f0164ed81 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -392,6 +392,12 @@
392#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ 392#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */
393#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ 393#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */
394 394
395#define SPRN_TBCTL 0x35f /* PA6T Timebase control register */
396#define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */
397#define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */
398#define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */
399#define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */
400
395#ifndef SPRN_SVR 401#ifndef SPRN_SVR
396#define SPRN_SVR 0x11E /* System Version Register */ 402#define SPRN_SVR 0x11E /* System Version Register */
397#endif 403#endif