diff options
-rw-r--r-- | arch/mips/alchemy/common/dbdma.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 3ab6d80d150d..19c1c82849ff 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c | |||
@@ -175,7 +175,7 @@ static dbdev_tab_t dbdev_tab[] = { | |||
175 | #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) | 175 | #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) |
176 | 176 | ||
177 | #ifdef CONFIG_PM | 177 | #ifdef CONFIG_PM |
178 | static u32 au1xxx_dbdma_pm_regs[NUM_DBDMA_CHANS + 1][8]; | 178 | static u32 au1xxx_dbdma_pm_regs[NUM_DBDMA_CHANS + 1][6]; |
179 | #endif | 179 | #endif |
180 | 180 | ||
181 | 181 | ||
@@ -993,14 +993,13 @@ void au1xxx_dbdma_suspend(void) | |||
993 | au1xxx_dbdma_pm_regs[0][3] = au_readl(addr + 0x0c); | 993 | au1xxx_dbdma_pm_regs[0][3] = au_readl(addr + 0x0c); |
994 | 994 | ||
995 | /* save channel configurations */ | 995 | /* save channel configurations */ |
996 | for (i = 1, addr = DDMA_CHANNEL_BASE; i < NUM_DBDMA_CHANS; i++) { | 996 | for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) { |
997 | au1xxx_dbdma_pm_regs[i][0] = au_readl(addr + 0x00); | 997 | au1xxx_dbdma_pm_regs[i][0] = au_readl(addr + 0x00); |
998 | au1xxx_dbdma_pm_regs[i][1] = au_readl(addr + 0x04); | 998 | au1xxx_dbdma_pm_regs[i][1] = au_readl(addr + 0x04); |
999 | au1xxx_dbdma_pm_regs[i][2] = au_readl(addr + 0x08); | 999 | au1xxx_dbdma_pm_regs[i][2] = au_readl(addr + 0x08); |
1000 | au1xxx_dbdma_pm_regs[i][3] = au_readl(addr + 0x0c); | 1000 | au1xxx_dbdma_pm_regs[i][3] = au_readl(addr + 0x0c); |
1001 | au1xxx_dbdma_pm_regs[i][4] = au_readl(addr + 0x10); | 1001 | au1xxx_dbdma_pm_regs[i][4] = au_readl(addr + 0x10); |
1002 | au1xxx_dbdma_pm_regs[i][5] = au_readl(addr + 0x14); | 1002 | au1xxx_dbdma_pm_regs[i][5] = au_readl(addr + 0x14); |
1003 | au1xxx_dbdma_pm_regs[i][6] = au_readl(addr + 0x18); | ||
1004 | 1003 | ||
1005 | /* halt channel */ | 1004 | /* halt channel */ |
1006 | au_writel(au1xxx_dbdma_pm_regs[i][0] & ~1, addr + 0x00); | 1005 | au_writel(au1xxx_dbdma_pm_regs[i][0] & ~1, addr + 0x00); |
@@ -1027,14 +1026,13 @@ void au1xxx_dbdma_resume(void) | |||
1027 | au_writel(au1xxx_dbdma_pm_regs[0][3], addr + 0x0c); | 1026 | au_writel(au1xxx_dbdma_pm_regs[0][3], addr + 0x0c); |
1028 | 1027 | ||
1029 | /* restore channel configurations */ | 1028 | /* restore channel configurations */ |
1030 | for (i = 1, addr = DDMA_CHANNEL_BASE; i < NUM_DBDMA_CHANS; i++) { | 1029 | for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) { |
1031 | au_writel(au1xxx_dbdma_pm_regs[i][0], addr + 0x00); | 1030 | au_writel(au1xxx_dbdma_pm_regs[i][0], addr + 0x00); |
1032 | au_writel(au1xxx_dbdma_pm_regs[i][1], addr + 0x04); | 1031 | au_writel(au1xxx_dbdma_pm_regs[i][1], addr + 0x04); |
1033 | au_writel(au1xxx_dbdma_pm_regs[i][2], addr + 0x08); | 1032 | au_writel(au1xxx_dbdma_pm_regs[i][2], addr + 0x08); |
1034 | au_writel(au1xxx_dbdma_pm_regs[i][3], addr + 0x0c); | 1033 | au_writel(au1xxx_dbdma_pm_regs[i][3], addr + 0x0c); |
1035 | au_writel(au1xxx_dbdma_pm_regs[i][4], addr + 0x10); | 1034 | au_writel(au1xxx_dbdma_pm_regs[i][4], addr + 0x10); |
1036 | au_writel(au1xxx_dbdma_pm_regs[i][5], addr + 0x14); | 1035 | au_writel(au1xxx_dbdma_pm_regs[i][5], addr + 0x14); |
1037 | au_writel(au1xxx_dbdma_pm_regs[i][6], addr + 0x18); | ||
1038 | au_sync(); | 1036 | au_sync(); |
1039 | addr += 0x100; /* next channel base */ | 1037 | addr += 0x100; /* next channel base */ |
1040 | } | 1038 | } |