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-rw-r--r--arch/mips/sni/pcimt.c105
-rw-r--r--arch/mips/sni/pcit.c122
2 files changed, 32 insertions, 195 deletions
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 8e8593b64f6a..9ee208daa8b1 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -91,7 +91,7 @@ static struct platform_device pcimt_serial8250_device = {
91}; 91};
92 92
93static struct resource sni_io_resource = { 93static struct resource sni_io_resource = {
94 .start = 0x00001000UL, 94 .start = 0x00000000UL,
95 .end = 0x03bfffffUL, 95 .end = 0x03bfffffUL,
96 .name = "PCIMT IO MEM", 96 .name = "PCIMT IO MEM",
97 .flags = IORESOURCE_IO, 97 .flags = IORESOURCE_IO,
@@ -132,107 +132,19 @@ static struct resource pcimt_io_resources[] = {
132}; 132};
133 133
134static struct resource sni_mem_resource = { 134static struct resource sni_mem_resource = {
135 .start = 0x10000000UL, 135 .start = 0x18000000UL,
136 .end = 0xffffffffUL, 136 .end = 0x1fbfffffUL,
137 .name = "PCIMT PCI MEM", 137 .name = "PCIMT PCI MEM",
138 .flags = IORESOURCE_MEM 138 .flags = IORESOURCE_MEM
139}; 139};
140 140
141/*
142 * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used
143 * for other purposes. Be paranoid and allocate all of the before the PCI
144 * code gets a chance to to map anything else there ...
145 *
146 * This leaves the following areas available:
147 *
148 * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory
149 * 0x10100000 - 0x13ffffff ( 15MB) PCI/EISA/ISA Bus Memory
150 * 0x18000000 - 0x1fbfffff (124MB) PCI/EISA Bus Memory
151 * 0x1ff08000 - 0x1ffeffff (816kB) PCI/EISA Bus Memory
152 * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory
153 */
154static struct resource pcimt_mem_resources[] = {
155 {
156 .start = 0x100a0000,
157 .end = 0x100bffff,
158 .name = "Video RAM area",
159 .flags = IORESOURCE_BUSY
160 }, {
161 .start = 0x100c0000,
162 .end = 0x100fffff,
163 .name = "ISA Reserved",
164 .flags = IORESOURCE_BUSY
165 }, {
166 .start = 0x14000000,
167 .end = 0x17bfffff,
168 .name = "PCI IO",
169 .flags = IORESOURCE_BUSY
170 }, {
171 .start = 0x17c00000,
172 .end = 0x17ffffff,
173 .name = "Cache Replacement Area",
174 .flags = IORESOURCE_BUSY
175 }, {
176 .start = 0x1a000000,
177 .end = 0x1a000003,
178 .name = "PCI INT Acknowledge",
179 .flags = IORESOURCE_BUSY
180 }, {
181 .start = 0x1fc00000,
182 .end = 0x1fc7ffff,
183 .name = "Boot PROM",
184 .flags = IORESOURCE_BUSY
185 }, {
186 .start = 0x1fc80000,
187 .end = 0x1fcfffff,
188 .name = "Diag PROM",
189 .flags = IORESOURCE_BUSY
190 }, {
191 .start = 0x1fd00000,
192 .end = 0x1fdfffff,
193 .name = "X-Bus",
194 .flags = IORESOURCE_BUSY
195 }, {
196 .start = 0x1fe00000,
197 .end = 0x1fefffff,
198 .name = "BIOS map",
199 .flags = IORESOURCE_BUSY
200 }, {
201 .start = 0x1ff00000,
202 .end = 0x1ff7ffff,
203 .name = "NVRAM / EEPROM",
204 .flags = IORESOURCE_BUSY
205 }, {
206 .start = 0x1fff0000,
207 .end = 0x1fffefff,
208 .name = "ASIC PCI",
209 .flags = IORESOURCE_BUSY
210 }, {
211 .start = 0x1ffff000,
212 .end = 0x1fffffff,
213 .name = "MP Agent",
214 .flags = IORESOURCE_BUSY
215 }, {
216 .start = 0x20000000,
217 .end = 0x9fffffff,
218 .name = "Main Memory",
219 .flags = IORESOURCE_BUSY
220 }
221};
222
223static void __init sni_pcimt_resource_init(void) 141static void __init sni_pcimt_resource_init(void)
224{ 142{
225 int i; 143 int i;
226 144
227 /* request I/O space for devices used on all i[345]86 PCs */ 145 /* request I/O space for devices used on all i[345]86 PCs */
228 for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++) 146 for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++)
229 request_resource(&ioport_resource, pcimt_io_resources + i); 147 request_resource(&sni_io_resource, pcimt_io_resources + i);
230
231 /* request mem space for pcimt-specific devices */
232 for (i = 0; i < ARRAY_SIZE(pcimt_mem_resources); i++)
233 request_resource(&sni_mem_resource, pcimt_mem_resources + i);
234
235 ioport_resource.end = sni_io_resource.end;
236} 148}
237 149
238extern struct pci_ops sni_pcimt_ops; 150extern struct pci_ops sni_pcimt_ops;
@@ -240,9 +152,10 @@ extern struct pci_ops sni_pcimt_ops;
240static struct pci_controller sni_controller = { 152static struct pci_controller sni_controller = {
241 .pci_ops = &sni_pcimt_ops, 153 .pci_ops = &sni_pcimt_ops,
242 .mem_resource = &sni_mem_resource, 154 .mem_resource = &sni_mem_resource,
243 .mem_offset = 0x10000000UL, 155 .mem_offset = 0x00000000UL,
244 .io_resource = &sni_io_resource, 156 .io_resource = &sni_io_resource,
245 .io_offset = 0x00000000UL 157 .io_offset = 0x00000000UL,
158 .io_map_base = SNI_PORT_BASE
246}; 159};
247 160
248static void enable_pcimt_irq(unsigned int irq) 161static void enable_pcimt_irq(unsigned int irq)
@@ -363,15 +276,17 @@ void __init sni_pcimt_irq_init(void)
363 276
364void sni_pcimt_init(void) 277void sni_pcimt_init(void)
365{ 278{
366 sni_pcimt_resource_init();
367 sni_pcimt_detect(); 279 sni_pcimt_detect();
368 sni_pcimt_sc_init(); 280 sni_pcimt_sc_init();
369 rtc_mips_get_time = mc146818_get_cmos_time; 281 rtc_mips_get_time = mc146818_get_cmos_time;
370 rtc_mips_set_time = mc146818_set_rtc_mmss; 282 rtc_mips_set_time = mc146818_set_rtc_mmss;
371 board_time_init = sni_cpu_time_init; 283 board_time_init = sni_cpu_time_init;
284 ioport_resource.end = sni_io_resource.end;
372#ifdef CONFIG_PCI 285#ifdef CONFIG_PCI
286 PCIBIOS_MIN_IO = 0x9000;
373 register_pci_controller(&sni_controller); 287 register_pci_controller(&sni_controller);
374#endif 288#endif
289 sni_pcimt_resource_init();
375} 290}
376 291
377static int __init snirm_pcimt_setup_devinit(void) 292static int __init snirm_pcimt_setup_devinit(void)
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 1dfc3f00bbd3..00d151f4d121 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -43,7 +43,7 @@ static struct platform_device pcit_serial8250_device = {
43}; 43};
44 44
45static struct plat_serial8250_port pcit_cplus_data[] = { 45static struct plat_serial8250_port pcit_cplus_data[] = {
46 PORT(0x3f8, 4), 46 PORT(0x3f8, 0),
47 PORT(0x2f8, 3), 47 PORT(0x2f8, 3),
48 PORT(0x3e8, 4), 48 PORT(0x3e8, 4),
49 PORT(0x2e8, 3), 49 PORT(0x2e8, 3),
@@ -59,9 +59,9 @@ static struct platform_device pcit_cplus_serial8250_device = {
59}; 59};
60 60
61static struct resource sni_io_resource = { 61static struct resource sni_io_resource = {
62 .start = 0x00001000UL, 62 .start = 0x00000000UL,
63 .end = 0x03bfffffUL, 63 .end = 0x03bfffffUL,
64 .name = "PCIT IO MEM", 64 .name = "PCIT IO",
65 .flags = IORESOURCE_IO, 65 .flags = IORESOURCE_IO,
66}; 66};
67 67
@@ -92,6 +92,11 @@ static struct resource pcit_io_resources[] = {
92 .name = "dma2", 92 .name = "dma2",
93 .flags = IORESOURCE_BUSY 93 .flags = IORESOURCE_BUSY
94 }, { 94 }, {
95 .start = 0xcf8,
96 .end = 0xcfb,
97 .name = "PCI config addr",
98 .flags = IORESOURCE_BUSY
99 }, {
95 .start = 0xcfc, 100 .start = 0xcfc,
96 .end = 0xcff, 101 .end = 0xcff,
97 .name = "PCI config data", 102 .name = "PCI config data",
@@ -100,107 +105,19 @@ static struct resource pcit_io_resources[] = {
100}; 105};
101 106
102static struct resource sni_mem_resource = { 107static struct resource sni_mem_resource = {
103 .start = 0x10000000UL, 108 .start = 0x18000000UL,
104 .end = 0xffffffffUL, 109 .end = 0x1fbfffffUL,
105 .name = "PCIT PCI MEM", 110 .name = "PCIT PCI MEM",
106 .flags = IORESOURCE_MEM 111 .flags = IORESOURCE_MEM
107}; 112};
108 113
109/*
110 * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used
111 * for other purposes. Be paranoid and allocate all of the before the PCI
112 * code gets a chance to to map anything else there ...
113 *
114 * This leaves the following areas available:
115 *
116 * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory
117 * 0x10100000 - 0x13ffffff ( 15MB) PCI/EISA/ISA Bus Memory
118 * 0x18000000 - 0x1fbfffff (124MB) PCI/EISA Bus Memory
119 * 0x1ff08000 - 0x1ffeffff (816kB) PCI/EISA Bus Memory
120 * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory
121 */
122static struct resource pcit_mem_resources[] = {
123 {
124 .start = 0x14000000,
125 .end = 0x17bfffff,
126 .name = "PCI IO",
127 .flags = IORESOURCE_BUSY
128 }, {
129 .start = 0x17c00000,
130 .end = 0x17ffffff,
131 .name = "Cache Replacement Area",
132 .flags = IORESOURCE_BUSY
133 }, {
134 .start = 0x180a0000,
135 .end = 0x180bffff,
136 .name = "Video RAM area",
137 .flags = IORESOURCE_BUSY
138 }, {
139 .start = 0x180c0000,
140 .end = 0x180fffff,
141 .name = "ISA Reserved",
142 .flags = IORESOURCE_BUSY
143 }, {
144 .start = 0x19000000,
145 .end = 0x1fbfffff,
146 .name = "PCI MEM",
147 .flags = IORESOURCE_BUSY
148 }, {
149 .start = 0x1fc00000,
150 .end = 0x1fc7ffff,
151 .name = "Boot PROM",
152 .flags = IORESOURCE_BUSY
153 }, {
154 .start = 0x1fc80000,
155 .end = 0x1fcfffff,
156 .name = "Diag PROM",
157 .flags = IORESOURCE_BUSY
158 }, {
159 .start = 0x1fd00000,
160 .end = 0x1fdfffff,
161 .name = "X-Bus",
162 .flags = IORESOURCE_BUSY
163 }, {
164 .start = 0x1fe00000,
165 .end = 0x1fefffff,
166 .name = "BIOS map",
167 .flags = IORESOURCE_BUSY
168 }, {
169 .start = 0x1ff00000,
170 .end = 0x1ff7ffff,
171 .name = "NVRAM / EEPROM",
172 .flags = IORESOURCE_BUSY
173 }, {
174 .start = 0x1fff0000,
175 .end = 0x1fffefff,
176 .name = "MAUI ASIC",
177 .flags = IORESOURCE_BUSY
178 }, {
179 .start = 0x1ffff000,
180 .end = 0x1fffffff,
181 .name = "MP Agent",
182 .flags = IORESOURCE_BUSY
183 }, {
184 .start = 0x20000000,
185 .end = 0x9fffffff,
186 .name = "Main Memory",
187 .flags = IORESOURCE_BUSY
188 }
189};
190
191static void __init sni_pcit_resource_init(void) 114static void __init sni_pcit_resource_init(void)
192{ 115{
193 int i; 116 int i;
194 117
195 /* request I/O space for devices used on all i[345]86 PCs */ 118 /* request I/O space for devices used on all i[345]86 PCs */
196 for (i = 0; i < ARRAY_SIZE(pcit_io_resources); i++) 119 for (i = 0; i < ARRAY_SIZE(pcit_io_resources); i++)
197 request_resource(&ioport_resource, pcit_io_resources + i); 120 request_resource(&sni_io_resource, pcit_io_resources + i);
198
199 /* request mem space for pcimt-specific devices */
200 for (i = 0; i < ARRAY_SIZE(pcit_mem_resources); i++)
201 request_resource(&sni_mem_resource, pcit_mem_resources + i);
202
203 ioport_resource.end = sni_io_resource.end;
204} 121}
205 122
206 123
@@ -209,9 +126,10 @@ extern struct pci_ops sni_pcit_ops;
209static struct pci_controller sni_pcit_controller = { 126static struct pci_controller sni_pcit_controller = {
210 .pci_ops = &sni_pcit_ops, 127 .pci_ops = &sni_pcit_ops,
211 .mem_resource = &sni_mem_resource, 128 .mem_resource = &sni_mem_resource,
212 .mem_offset = 0x10000000UL, 129 .mem_offset = 0x00000000UL,
213 .io_resource = &sni_io_resource, 130 .io_resource = &sni_io_resource,
214 .io_offset = 0x00000000UL 131 .io_offset = 0x00000000UL,
132 .io_map_base = SNI_PORT_BASE
215}; 133};
216 134
217static void enable_pcit_irq(unsigned int irq) 135static void enable_pcit_irq(unsigned int irq)
@@ -262,7 +180,7 @@ static void pcit_hwint0(void)
262 int irq; 180 int irq;
263 181
264 clear_c0_status(IE_IRQ0); 182 clear_c0_status(IE_IRQ0);
265 irq = ffs((pending >> 16) & 0x7f); 183 irq = ffs((pending >> 16) & 0x3f);
266 184
267 if (likely(irq > 0)) 185 if (likely(irq > 0))
268 do_IRQ (irq + SNI_PCIT_INT_START - 1); 186 do_IRQ (irq + SNI_PCIT_INT_START - 1);
@@ -289,6 +207,8 @@ static void sni_pcit_hwint_cplus(void)
289 207
290 if (pending & C_IRQ0) 208 if (pending & C_IRQ0)
291 pcit_hwint0(); 209 pcit_hwint0();
210 else if (pending & C_IRQ1)
211 do_IRQ (MIPS_CPU_IRQ_BASE + 3);
292 else if (pending & C_IRQ2) 212 else if (pending & C_IRQ2)
293 do_IRQ (MIPS_CPU_IRQ_BASE + 4); 213 do_IRQ (MIPS_CPU_IRQ_BASE + 4);
294 else if (pending & C_IRQ3) 214 else if (pending & C_IRQ3)
@@ -317,21 +237,23 @@ void __init sni_pcit_cplus_irq_init(void)
317 mips_cpu_irq_init(); 237 mips_cpu_irq_init();
318 for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) 238 for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
319 set_irq_chip(i, &pcit_irq_type); 239 set_irq_chip(i, &pcit_irq_type);
320 *(volatile u32 *)SNI_PCIT_INT_REG = 0; 240 *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
321 sni_hwint = sni_pcit_hwint_cplus; 241 sni_hwint = sni_pcit_hwint_cplus;
322 change_c0_status(ST0_IM, IE_IRQ0); 242 change_c0_status(ST0_IM, IE_IRQ0);
323 setup_irq (SNI_PCIT_INT_START + 6, &sni_isa_irq); 243 setup_irq (MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq);
324} 244}
325 245
326void sni_pcit_init(void) 246void sni_pcit_init(void)
327{ 247{
328 sni_pcit_resource_init();
329 rtc_mips_get_time = mc146818_get_cmos_time; 248 rtc_mips_get_time = mc146818_get_cmos_time;
330 rtc_mips_set_time = mc146818_set_rtc_mmss; 249 rtc_mips_set_time = mc146818_set_rtc_mmss;
331 board_time_init = sni_cpu_time_init; 250 board_time_init = sni_cpu_time_init;
251 ioport_resource.end = sni_io_resource.end;
332#ifdef CONFIG_PCI 252#ifdef CONFIG_PCI
253 PCIBIOS_MIN_IO = 0x9000;
333 register_pci_controller(&sni_pcit_controller); 254 register_pci_controller(&sni_pcit_controller);
334#endif 255#endif
256 sni_pcit_resource_init();
335} 257}
336 258
337static int __init snirm_pcit_setup_devinit(void) 259static int __init snirm_pcit_setup_devinit(void)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 16:46:30 -0500