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-rw-r--r--drivers/ata/sata_mv.c35
1 files changed, 18 insertions, 17 deletions
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index d689fb9ceb96..55d3ce087304 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -272,17 +272,17 @@ enum {
272 SATA_FIS_IRQ_CAUSE_OFS = 0x364, 272 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
273 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */ 273 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
274 274
275 LTMODE_OFS = 0x30c, 275 LTMODE_OFS = 0x30c, /* requires read-after-write */
276 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 276 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
277 277
278 PHY_MODE3 = 0x310, 278 PHY_MODE2_OFS = 0x330,
279 PHY_MODE4 = 0x314, 279 PHY_MODE3_OFS = 0x310,
280 PHY_MODE4_OFS = 0x314, /* requires read-after-write */
280 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ 281 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
281 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ 282 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
282 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ 283 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
283 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ 284 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
284 285
285 PHY_MODE2 = 0x330,
286 SATA_IFCTL_OFS = 0x344, 286 SATA_IFCTL_OFS = 0x344,
287 SATA_TESTCTL_OFS = 0x348, 287 SATA_TESTCTL_OFS = 0x348,
288 SATA_IFSTAT_OFS = 0x34c, 288 SATA_IFSTAT_OFS = 0x34c,
@@ -3168,7 +3168,7 @@ static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3168 } 3168 }
3169 3169
3170 port_mmio = mv_port_base(mmio, idx); 3170 port_mmio = mv_port_base(mmio, idx);
3171 tmp = readl(port_mmio + PHY_MODE2); 3171 tmp = readl(port_mmio + PHY_MODE2_OFS);
3172 3172
3173 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3173 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3174 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3174 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
@@ -3192,25 +3192,25 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3192 u32 m2, m3; 3192 u32 m2, m3;
3193 3193
3194 if (fix_phy_mode2) { 3194 if (fix_phy_mode2) {
3195 m2 = readl(port_mmio + PHY_MODE2); 3195 m2 = readl(port_mmio + PHY_MODE2_OFS);
3196 m2 &= ~(1 << 16); 3196 m2 &= ~(1 << 16);
3197 m2 |= (1 << 31); 3197 m2 |= (1 << 31);
3198 writel(m2, port_mmio + PHY_MODE2); 3198 writel(m2, port_mmio + PHY_MODE2_OFS);
3199 3199
3200 udelay(200); 3200 udelay(200);
3201 3201
3202 m2 = readl(port_mmio + PHY_MODE2); 3202 m2 = readl(port_mmio + PHY_MODE2_OFS);
3203 m2 &= ~((1 << 16) | (1 << 31)); 3203 m2 &= ~((1 << 16) | (1 << 31));
3204 writel(m2, port_mmio + PHY_MODE2); 3204 writel(m2, port_mmio + PHY_MODE2_OFS);
3205 3205
3206 udelay(200); 3206 udelay(200);
3207 } 3207 }
3208 3208
3209 /* 3209 /*
3210 * Gen-II/IIe PHY_MODE3 errata RM#2: 3210 * Gen-II/IIe PHY_MODE3_OFS errata RM#2:
3211 * Achieves better receiver noise performance than the h/w default: 3211 * Achieves better receiver noise performance than the h/w default:
3212 */ 3212 */
3213 m3 = readl(port_mmio + PHY_MODE3); 3213 m3 = readl(port_mmio + PHY_MODE3_OFS);
3214 m3 = (m3 & 0x1f) | (0x5555601 << 5); 3214 m3 = (m3 & 0x1f) | (0x5555601 << 5);
3215 3215
3216 /* Guideline 88F5182 (GL# SATA-S11) */ 3216 /* Guideline 88F5182 (GL# SATA-S11) */
@@ -3218,7 +3218,7 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3218 m3 &= ~0x1c; 3218 m3 &= ~0x1c;
3219 3219
3220 if (fix_phy_mode4) { 3220 if (fix_phy_mode4) {
3221 u32 m4 = readl(port_mmio + PHY_MODE4); 3221 u32 m4 = readl(port_mmio + PHY_MODE4_OFS);
3222 /* 3222 /*
3223 * Enforce reserved-bit restrictions on GenIIe devices only. 3223 * Enforce reserved-bit restrictions on GenIIe devices only.
3224 * For earlier chipsets, force only the internal config field 3224 * For earlier chipsets, force only the internal config field
@@ -3228,17 +3228,18 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3228 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; 3228 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3229 else 3229 else
3230 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; 3230 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
3231 writel(m4, port_mmio + PHY_MODE4); 3231 writel(m4, port_mmio + PHY_MODE4_OFS);
3232 } 3232 }
3233 /* 3233 /*
3234 * Workaround for 60x1-B2 errata SATA#13: 3234 * Workaround for 60x1-B2 errata SATA#13:
3235 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, 3235 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3236 * so we must always rewrite PHY_MODE3 after PHY_MODE4. 3236 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3237 * Or ensure we use writelfl() when writing PHY_MODE4.
3237 */ 3238 */
3238 writel(m3, port_mmio + PHY_MODE3); 3239 writel(m3, port_mmio + PHY_MODE3_OFS);
3239 3240
3240 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3241 /* Revert values of pre-emphasis and signal amps to the saved ones */
3241 m2 = readl(port_mmio + PHY_MODE2); 3242 m2 = readl(port_mmio + PHY_MODE2_OFS);
3242 3243
3243 m2 &= ~MV_M2_PREAMP_MASK; 3244 m2 &= ~MV_M2_PREAMP_MASK;
3244 m2 |= hpriv->signal[port].amps; 3245 m2 |= hpriv->signal[port].amps;
@@ -3251,7 +3252,7 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3251 m2 |= 0x0000900F; 3252 m2 |= 0x0000900F;
3252 } 3253 }
3253 3254
3254 writel(m2, port_mmio + PHY_MODE2); 3255 writel(m2, port_mmio + PHY_MODE2_OFS);
3255} 3256}
3256 3257
3257/* TODO: use the generic LED interface to configure the SATA Presence */ 3258/* TODO: use the generic LED interface to configure the SATA Presence */
@@ -3269,7 +3270,7 @@ static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3269 u32 tmp; 3270 u32 tmp;
3270 3271
3271 port_mmio = mv_port_base(mmio, idx); 3272 port_mmio = mv_port_base(mmio, idx);
3272 tmp = readl(port_mmio + PHY_MODE2); 3273 tmp = readl(port_mmio + PHY_MODE2_OFS);
3273 3274
3274 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3275 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3275 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3276 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */