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-rw-r--r--arch/mips/Makefile8
-rw-r--r--arch/mips/txx9/Kconfig8
-rw-r--r--arch/mips/txx9/generic/setup.c5
-rw-r--r--arch/mips/txx9/rbtx4939/Makefile3
-rw-r--r--arch/mips/txx9/rbtx4939/irq.c96
-rw-r--r--arch/mips/txx9/rbtx4939/prom.c17
-rw-r--r--arch/mips/txx9/rbtx4939/setup.c306
-rw-r--r--include/asm-mips/txx9/boards.h3
-rw-r--r--include/asm-mips/txx9/rbtx4939.h133
9 files changed, 573 insertions, 6 deletions
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 9aab51caf16a..87f67228e309 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -567,15 +567,11 @@ cflags-$(CONFIG_MIKROTIK_RB532) += -Iinclude/asm-mips/mach-rc32434
567load-$(CONFIG_MIKROTIK_RB532) += 0xffffffff80101000 567load-$(CONFIG_MIKROTIK_RB532) += 0xffffffff80101000
568 568
569# 569#
570# Toshiba RBTX4927 board or 570# Toshiba RBTX49XX boards
571# Toshiba RBTX4937 board
572# 571#
573core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/ 572core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/
574
575#
576# Toshiba RBTX4938 board
577#
578core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/ 573core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/
574core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/
579 575
580cflags-y += -Iinclude/asm-mips/mach-generic 576cflags-y += -Iinclude/asm-mips/mach-generic
581drivers-$(CONFIG_PCI) += arch/mips/pci/ 577drivers-$(CONFIG_PCI) += arch/mips/pci/
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 58691a1fe779..17052db4161d 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -45,6 +45,14 @@ config TOSHIBA_RBTX4938
45 This Toshiba board is based on the TX4938 processor. Say Y here to 45 This Toshiba board is based on the TX4938 processor. Say Y here to
46 support this machine type 46 support this machine type
47 47
48config TOSHIBA_RBTX4939
49 bool "Toshiba RBTX4939 bobard"
50 depends on MACH_TX49XX
51 select SOC_TX4939
52 help
53 This Toshiba board is based on the TX4939 processor. Say Y here to
54 support this machine type
55
48config SOC_TX3927 56config SOC_TX3927
49 bool 57 bool
50 select CEVT_TXX9 58 select CEVT_TXX9
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 1ea06553a1e1..7a05c34c1dec 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -372,6 +372,11 @@ static void __init select_board(void)
372 txx9_board_vec = &rbtx4938_vec; 372 txx9_board_vec = &rbtx4938_vec;
373 break; 373 break;
374#endif 374#endif
375#ifdef CONFIG_TOSHIBA_RBTX4939
376 case 0x4939:
377 txx9_board_vec = &rbtx4939_vec;
378 break;
379#endif
375 } 380 }
376#endif 381#endif
377} 382}
diff --git a/arch/mips/txx9/rbtx4939/Makefile b/arch/mips/txx9/rbtx4939/Makefile
new file mode 100644
index 000000000000..3232cd03a7d6
--- /dev/null
+++ b/arch/mips/txx9/rbtx4939/Makefile
@@ -0,0 +1,3 @@
1obj-y += irq.o setup.o prom.o
2
3EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/rbtx4939/irq.c b/arch/mips/txx9/rbtx4939/irq.c
new file mode 100644
index 000000000000..500cc0a908e6
--- /dev/null
+++ b/arch/mips/txx9/rbtx4939/irq.c
@@ -0,0 +1,96 @@
1/*
2 * Toshiba RBTX4939 interrupt routines
3 * Based on linux/arch/mips/txx9/rbtx4938/irq.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <asm/mipsregs.h>
15#include <asm/txx9/rbtx4939.h>
16
17/*
18 * RBTX4939 IOC controller definition
19 */
20
21static void rbtx4939_ioc_irq_unmask(unsigned int irq)
22{
23 int ioc_nr = irq - RBTX4939_IRQ_IOC;
24
25 writeb(readb(rbtx4939_ien_addr) | (1 << ioc_nr), rbtx4939_ien_addr);
26}
27
28static void rbtx4939_ioc_irq_mask(unsigned int irq)
29{
30 int ioc_nr = irq - RBTX4939_IRQ_IOC;
31
32 writeb(readb(rbtx4939_ien_addr) & ~(1 << ioc_nr), rbtx4939_ien_addr);
33 mmiowb();
34}
35
36static struct irq_chip rbtx4939_ioc_irq_chip = {
37 .name = "IOC",
38 .ack = rbtx4939_ioc_irq_mask,
39 .mask = rbtx4939_ioc_irq_mask,
40 .mask_ack = rbtx4939_ioc_irq_mask,
41 .unmask = rbtx4939_ioc_irq_unmask,
42};
43
44
45static inline int rbtx4939_ioc_irqroute(void)
46{
47 unsigned char istat = readb(rbtx4939_ifac2_addr);
48
49 if (unlikely(istat == 0))
50 return -1;
51 return RBTX4939_IRQ_IOC + __fls8(istat);
52}
53
54static int rbtx4939_irq_dispatch(int pending)
55{
56 int irq;
57
58 if (pending & CAUSEF_IP7)
59 return MIPS_CPU_IRQ_BASE + 7;
60 irq = tx4939_irq();
61 if (likely(irq >= 0)) {
62 /* redirect IOC interrupts */
63 switch (irq) {
64 case RBTX4939_IRQ_IOCINT:
65 irq = rbtx4939_ioc_irqroute();
66 break;
67 }
68 } else if (pending & CAUSEF_IP0)
69 irq = MIPS_CPU_IRQ_BASE + 0;
70 else if (pending & CAUSEF_IP1)
71 irq = MIPS_CPU_IRQ_BASE + 1;
72 else
73 irq = -1;
74 return irq;
75}
76
77void __init rbtx4939_irq_setup(void)
78{
79 int i;
80
81 /* mask all IOC interrupts */
82 writeb(0, rbtx4939_ien_addr);
83
84 /* clear SoftInt interrupts */
85 writeb(0, rbtx4939_softint_addr);
86
87 txx9_irq_dispatch = rbtx4939_irq_dispatch;
88
89 tx4939_irq_init();
90 for (i = RBTX4939_IRQ_IOC;
91 i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++)
92 set_irq_chip_and_handler(i, &rbtx4939_ioc_irq_chip,
93 handle_level_irq);
94
95 set_irq_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq);
96}
diff --git a/arch/mips/txx9/rbtx4939/prom.c b/arch/mips/txx9/rbtx4939/prom.c
new file mode 100644
index 000000000000..bd277ecb4ad6
--- /dev/null
+++ b/arch/mips/txx9/rbtx4939/prom.c
@@ -0,0 +1,17 @@
1/*
2 * rbtx4939 specific prom routines
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 */
8
9#include <linux/init.h>
10#include <asm/txx9/generic.h>
11#include <asm/txx9/rbtx4939.h>
12
13void __init rbtx4939_prom_init(void)
14{
15 tx4939_add_memory_regions();
16 txx9_sio_putchar_init(TX4939_SIO_REG(0) & 0xfffffffffULL);
17}
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
new file mode 100644
index 000000000000..277864d5e779
--- /dev/null
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -0,0 +1,306 @@
1/*
2 * Toshiba RBTX4939 setup routines.
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/platform_device.h>
16#include <linux/leds.h>
17#include <asm/reboot.h>
18#include <asm/txx9/generic.h>
19#include <asm/txx9/pci.h>
20#include <asm/txx9/rbtx4939.h>
21
22static void rbtx4939_machine_restart(char *command)
23{
24 local_irq_disable();
25 writeb(1, rbtx4939_reseten_addr);
26 writeb(1, rbtx4939_softreset_addr);
27 while (1)
28 ;
29}
30
31static void __init rbtx4939_time_init(void)
32{
33 tx4939_time_init(0);
34}
35
36static void __init rbtx4939_pci_setup(void)
37{
38#ifdef CONFIG_PCI
39 int extarb = !(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB);
40 struct pci_controller *c = &txx9_primary_pcic;
41
42 register_pci_controller(c);
43
44 tx4939_report_pciclk();
45 tx4927_pcic_setup(tx4939_pcicptr, c, extarb);
46 if (!(__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_ATA1MODE) &&
47 (__raw_readq(&tx4939_ccfgptr->pcfg) &
48 (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE))) {
49 tx4939_report_pci1clk();
50
51 /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
52 c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
53 register_pci_controller(c);
54 tx4927_pcic_setup(tx4939_pcic1ptr, c, 0);
55 }
56
57 tx4939_setup_pcierr_irq();
58#endif /* CONFIG_PCI */
59}
60
61static unsigned long long default_ebccr[] __initdata = {
62 0x01c0000000007608ULL, /* 64M ROM */
63 0x017f000000007049ULL, /* 1M IOC */
64 0x0180000000408608ULL, /* ISA */
65 0,
66};
67
68static void __init rbtx4939_ebusc_setup(void)
69{
70 int i;
71 unsigned int sp;
72
73 /* use user-configured speed */
74 sp = TX4939_EBUSC_CR(0) & 0x30;
75 default_ebccr[0] |= sp;
76 default_ebccr[1] |= sp;
77 default_ebccr[2] |= sp;
78 /* initialise by myself */
79 for (i = 0; i < ARRAY_SIZE(default_ebccr); i++) {
80 if (default_ebccr[i])
81 ____raw_writeq(default_ebccr[i],
82 &tx4939_ebuscptr->cr[i]);
83 else
84 ____raw_writeq(____raw_readq(&tx4939_ebuscptr->cr[i])
85 & ~8,
86 &tx4939_ebuscptr->cr[i]);
87 }
88}
89
90static void __init rbtx4939_update_ioc_pen(void)
91{
92 __u64 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
93 __u64 ccfg = ____raw_readq(&tx4939_ccfgptr->ccfg);
94 __u8 pe1 = readb(rbtx4939_pe1_addr);
95 __u8 pe2 = readb(rbtx4939_pe2_addr);
96 __u8 pe3 = readb(rbtx4939_pe3_addr);
97 if (pcfg & TX4939_PCFG_ATA0MODE)
98 pe1 |= RBTX4939_PE1_ATA(0);
99 else
100 pe1 &= ~RBTX4939_PE1_ATA(0);
101 if (pcfg & TX4939_PCFG_ATA1MODE) {
102 pe1 |= RBTX4939_PE1_ATA(1);
103 pe1 &= ~(RBTX4939_PE1_RMII(0) | RBTX4939_PE1_RMII(1));
104 } else {
105 pe1 &= ~RBTX4939_PE1_ATA(1);
106 if (pcfg & TX4939_PCFG_ET0MODE)
107 pe1 |= RBTX4939_PE1_RMII(0);
108 else
109 pe1 &= ~RBTX4939_PE1_RMII(0);
110 if (pcfg & TX4939_PCFG_ET1MODE)
111 pe1 |= RBTX4939_PE1_RMII(1);
112 else
113 pe1 &= ~RBTX4939_PE1_RMII(1);
114 }
115 if (ccfg & TX4939_CCFG_PTSEL)
116 pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
117 RBTX4939_PE3_VP_S);
118 else {
119 __u64 vmode = pcfg &
120 (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE);
121 if (vmode == 0)
122 pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
123 RBTX4939_PE3_VP_S);
124 else if (vmode == TX4939_PCFG_VPSMODE) {
125 pe3 |= RBTX4939_PE3_VP_P;
126 pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_S);
127 } else if (vmode == TX4939_PCFG_VSSMODE) {
128 pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_S;
129 pe3 &= ~RBTX4939_PE3_VP_P;
130 } else {
131 pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_P;
132 pe3 &= ~RBTX4939_PE3_VP_S;
133 }
134 }
135 if (pcfg & TX4939_PCFG_SPIMODE) {
136 if (pcfg & TX4939_PCFG_SIO2MODE_GPIO)
137 pe2 &= ~(RBTX4939_PE2_SIO2 | RBTX4939_PE2_SIO0);
138 else {
139 if (pcfg & TX4939_PCFG_SIO2MODE_SIO2) {
140 pe2 |= RBTX4939_PE2_SIO2;
141 pe2 &= ~RBTX4939_PE2_SIO0;
142 } else {
143 pe2 |= RBTX4939_PE2_SIO0;
144 pe2 &= ~RBTX4939_PE2_SIO2;
145 }
146 }
147 if (pcfg & TX4939_PCFG_SIO3MODE)
148 pe2 |= RBTX4939_PE2_SIO3;
149 else
150 pe2 &= ~RBTX4939_PE2_SIO3;
151 pe2 &= ~RBTX4939_PE2_SPI;
152 } else {
153 pe2 |= RBTX4939_PE2_SPI;
154 pe2 &= ~(RBTX4939_PE2_SIO3 | RBTX4939_PE2_SIO2 |
155 RBTX4939_PE2_SIO0);
156 }
157 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_GPIO)
158 pe2 |= RBTX4939_PE2_GPIO;
159 else
160 pe2 &= ~RBTX4939_PE2_GPIO;
161 writeb(pe1, rbtx4939_pe1_addr);
162 writeb(pe2, rbtx4939_pe2_addr);
163 writeb(pe3, rbtx4939_pe3_addr);
164}
165
166#define RBTX4939_MAX_7SEGLEDS 8
167
168#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
169static u8 led_val[RBTX4939_MAX_7SEGLEDS];
170struct rbtx4939_led_data {
171 struct led_classdev cdev;
172 char name[32];
173 unsigned int num;
174};
175
176/* Use "dot" in 7seg LEDs */
177static void rbtx4939_led_brightness_set(struct led_classdev *led_cdev,
178 enum led_brightness value)
179{
180 struct rbtx4939_led_data *led_dat =
181 container_of(led_cdev, struct rbtx4939_led_data, cdev);
182 unsigned int num = led_dat->num;
183 unsigned long flags;
184
185 local_irq_save(flags);
186 led_val[num] = (led_val[num] & 0x7f) | (value ? 0x80 : 0);
187 writeb(led_val[num], rbtx4939_7seg_addr(num / 4, num % 4));
188 local_irq_restore(flags);
189}
190
191static int __init rbtx4939_led_probe(struct platform_device *pdev)
192{
193 struct rbtx4939_led_data *leds_data;
194 int i;
195 static char *default_triggers[] __initdata = {
196 "heartbeat",
197 "ide-disk",
198 "nand-disk",
199 };
200
201 leds_data = kzalloc(sizeof(*leds_data) * RBTX4939_MAX_7SEGLEDS,
202 GFP_KERNEL);
203 if (!leds_data)
204 return -ENOMEM;
205 for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++) {
206 int rc;
207 struct rbtx4939_led_data *led_dat = &leds_data[i];
208
209 led_dat->num = i;
210 led_dat->cdev.brightness_set = rbtx4939_led_brightness_set;
211 sprintf(led_dat->name, "rbtx4939:amber:%u", i);
212 led_dat->cdev.name = led_dat->name;
213 if (i < ARRAY_SIZE(default_triggers))
214 led_dat->cdev.default_trigger = default_triggers[i];
215 rc = led_classdev_register(&pdev->dev, &led_dat->cdev);
216 if (rc < 0)
217 return rc;
218 led_dat->cdev.brightness_set(&led_dat->cdev, 0);
219 }
220 return 0;
221
222}
223
224static struct platform_driver rbtx4939_led_driver = {
225 .driver = {
226 .name = "rbtx4939-led",
227 .owner = THIS_MODULE,
228 },
229};
230
231static void __init rbtx4939_led_setup(void)
232{
233 platform_device_register_simple("rbtx4939-led", -1, NULL, 0);
234 platform_driver_probe(&rbtx4939_led_driver, rbtx4939_led_probe);
235}
236#else
237static inline void rbtx4939_led_setup(void)
238{
239}
240#endif
241
242static void __init rbtx4939_arch_init(void)
243{
244 rbtx4939_pci_setup();
245}
246
247static void __init rbtx4939_device_init(void)
248{
249#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
250 int i, j;
251 unsigned char ethaddr[2][6];
252 for (i = 0; i < 2; i++) {
253 unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10);
254 if (readb(rbtx4939_bdipsw_addr) & 8) {
255 u16 buf[3];
256 area -= 0x03000000;
257 for (j = 0; j < 3; j++)
258 buf[j] = le16_to_cpup((u16 *)(area + j * 2));
259 memcpy(ethaddr[i], buf, 6);
260 } else
261 memcpy(ethaddr[i], (void *)area, 6);
262 }
263 tx4939_ethaddr_init(ethaddr[0], ethaddr[1]);
264#endif
265 rbtx4939_led_setup();
266 tx4939_wdt_init();
267}
268
269static void __init rbtx4939_setup(void)
270{
271 rbtx4939_ebusc_setup();
272 /* always enable ATA0 */
273 txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE);
274 rbtx4939_update_ioc_pen();
275 if (txx9_master_clock == 0)
276 txx9_master_clock = 20000000;
277 tx4939_setup();
278
279 _machine_restart = rbtx4939_machine_restart;
280
281 pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
282 readb(rbtx4939_board_rev_addr), readb(rbtx4939_ioc_rev_addr),
283 readb(rbtx4939_udipsw_addr), readb(rbtx4939_bdipsw_addr));
284
285#ifdef CONFIG_PCI
286 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
287 txx9_board_pcibios_setup = tx4927_pcibios_setup;
288#else
289 set_io_port_base(RBTX4939_ETHER_BASE);
290#endif
291
292 tx4939_sio_init(TX4939_SCLK0(txx9_master_clock), 0);
293}
294
295struct txx9_board_vec rbtx4939_vec __initdata = {
296 .system = "Tothiba RBTX4939",
297 .prom_init = rbtx4939_prom_init,
298 .mem_setup = rbtx4939_setup,
299 .irq_setup = rbtx4939_irq_setup,
300 .time_init = rbtx4939_time_init,
301 .device_init = rbtx4939_device_init,
302 .arch_init = rbtx4939_arch_init,
303#ifdef CONFIG_PCI
304 .pci_map_irq = tx4939_pci_map_irq,
305#endif
306};
diff --git a/include/asm-mips/txx9/boards.h b/include/asm-mips/txx9/boards.h
index 4abc8142fbb7..cbe9476d963e 100644
--- a/include/asm-mips/txx9/boards.h
+++ b/include/asm-mips/txx9/boards.h
@@ -8,3 +8,6 @@ BOARD_VEC(rbtx4937_vec)
8#ifdef CONFIG_TOSHIBA_RBTX4938 8#ifdef CONFIG_TOSHIBA_RBTX4938
9BOARD_VEC(rbtx4938_vec) 9BOARD_VEC(rbtx4938_vec)
10#endif 10#endif
11#ifdef CONFIG_TOSHIBA_RBTX4939
12BOARD_VEC(rbtx4939_vec)
13#endif
diff --git a/include/asm-mips/txx9/rbtx4939.h b/include/asm-mips/txx9/rbtx4939.h
new file mode 100644
index 000000000000..1acf428c0b4f
--- /dev/null
+++ b/include/asm-mips/txx9/rbtx4939.h
@@ -0,0 +1,133 @@
1/*
2 * Definitions for RBTX4939
3 *
4 * (C) Copyright TOSHIBA CORPORATION 2005-2006
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 */
10#ifndef __ASM_TXX9_RBTX4939_H
11#define __ASM_TXX9_RBTX4939_H
12
13#include <asm/addrspace.h>
14#include <asm/txx9irq.h>
15#include <asm/txx9/generic.h>
16#include <asm/txx9/tx4939.h>
17
18/* Address map */
19#define RBTX4939_IOC_REG_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
20#define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
21#define RBTX4939_IOC_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000002)
22#define RBTX4939_CONFIG1_ADDR (IO_BASE + TXX9_CE(1) + 0x00000004)
23#define RBTX4939_CONFIG2_ADDR (IO_BASE + TXX9_CE(1) + 0x00000006)
24#define RBTX4939_CONFIG3_ADDR (IO_BASE + TXX9_CE(1) + 0x00000008)
25#define RBTX4939_CONFIG4_ADDR (IO_BASE + TXX9_CE(1) + 0x0000000a)
26#define RBTX4939_USTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00001000)
27#define RBTX4939_UDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001002)
28#define RBTX4939_BDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001004)
29#define RBTX4939_IEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00002000)
30#define RBTX4939_IPOL_ADDR (IO_BASE + TXX9_CE(1) + 0x00002002)
31#define RBTX4939_IFAC1_ADDR (IO_BASE + TXX9_CE(1) + 0x00002004)
32#define RBTX4939_IFAC2_ADDR (IO_BASE + TXX9_CE(1) + 0x00002006)
33#define RBTX4939_SOFTINT_ADDR (IO_BASE + TXX9_CE(1) + 0x00003000)
34#define RBTX4939_ISASTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004000)
35#define RBTX4939_PCISTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004002)
36#define RBTX4939_ROME_ADDR (IO_BASE + TXX9_CE(1) + 0x00004004)
37#define RBTX4939_SPICS_ADDR (IO_BASE + TXX9_CE(1) + 0x00004006)
38#define RBTX4939_AUDI_ADDR (IO_BASE + TXX9_CE(1) + 0x00004008)
39#define RBTX4939_ISAGPIO_ADDR (IO_BASE + TXX9_CE(1) + 0x0000400a)
40#define RBTX4939_PE1_ADDR (IO_BASE + TXX9_CE(1) + 0x00005000)
41#define RBTX4939_PE2_ADDR (IO_BASE + TXX9_CE(1) + 0x00005002)
42#define RBTX4939_PE3_ADDR (IO_BASE + TXX9_CE(1) + 0x00005004)
43#define RBTX4939_VP_ADDR (IO_BASE + TXX9_CE(1) + 0x00005006)
44#define RBTX4939_VPRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00005008)
45#define RBTX4939_VPSOUT_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500a)
46#define RBTX4939_VPSIN_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500c)
47#define RBTX4939_7SEG_ADDR(s, ch) \
48 (IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2)
49#define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000)
50#define RBTX4939_RESETEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00007002)
51#define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004)
52#define RBTX4939_ETHER_BASE (IO_BASE + TXX9_CE(1) + 0x00020000)
53
54/* Ethernet port address */
55#define RBTX4939_ETHER_ADDR (RBTX4939_ETHER_BASE + 0x300)
56
57/* bits for IEN/IPOL/IFAC */
58#define RBTX4938_INTB_ISA0 0
59#define RBTX4938_INTB_ISA11 1
60#define RBTX4938_INTB_ISA12 2
61#define RBTX4938_INTB_ISA15 3
62#define RBTX4938_INTB_I2S 4
63#define RBTX4938_INTB_SW 5
64#define RBTX4938_INTF_ISA0 (1 << RBTX4938_INTB_ISA0)
65#define RBTX4938_INTF_ISA11 (1 << RBTX4938_INTB_ISA11)
66#define RBTX4938_INTF_ISA12 (1 << RBTX4938_INTB_ISA12)
67#define RBTX4938_INTF_ISA15 (1 << RBTX4938_INTB_ISA15)
68#define RBTX4938_INTF_I2S (1 << RBTX4938_INTB_I2S)
69#define RBTX4938_INTF_SW (1 << RBTX4938_INTB_SW)
70
71/* bits for PE1,PE2,PE3 */
72#define RBTX4939_PE1_ATA(ch) (0x01 << (ch))
73#define RBTX4939_PE1_RMII(ch) (0x04 << (ch))
74#define RBTX4939_PE2_SIO0 0x01
75#define RBTX4939_PE2_SIO2 0x02
76#define RBTX4939_PE2_SIO3 0x04
77#define RBTX4939_PE2_CIR 0x08
78#define RBTX4939_PE2_SPI 0x10
79#define RBTX4939_PE2_GPIO 0x20
80#define RBTX4939_PE3_VP 0x01
81#define RBTX4939_PE3_VP_P 0x02
82#define RBTX4939_PE3_VP_S 0x04
83
84#define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR)
85#define rbtx4939_ioc_rev_addr ((u8 __iomem *)RBTX4939_IOC_REV_ADDR)
86#define rbtx4939_config1_addr ((u8 __iomem *)RBTX4939_CONFIG1_ADDR)
87#define rbtx4939_config2_addr ((u8 __iomem *)RBTX4939_CONFIG2_ADDR)
88#define rbtx4939_config3_addr ((u8 __iomem *)RBTX4939_CONFIG3_ADDR)
89#define rbtx4939_config4_addr ((u8 __iomem *)RBTX4939_CONFIG4_ADDR)
90#define rbtx4939_ustat_addr ((u8 __iomem *)RBTX4939_USTAT_ADDR)
91#define rbtx4939_udipsw_addr ((u8 __iomem *)RBTX4939_UDIPSW_ADDR)
92#define rbtx4939_bdipsw_addr ((u8 __iomem *)RBTX4939_BDIPSW_ADDR)
93#define rbtx4939_ien_addr ((u8 __iomem *)RBTX4939_IEN_ADDR)
94#define rbtx4939_ipol_addr ((u8 __iomem *)RBTX4939_IPOL_ADDR)
95#define rbtx4939_ifac1_addr ((u8 __iomem *)RBTX4939_IFAC1_ADDR)
96#define rbtx4939_ifac2_addr ((u8 __iomem *)RBTX4939_IFAC2_ADDR)
97#define rbtx4939_softint_addr ((u8 __iomem *)RBTX4939_SOFTINT_ADDR)
98#define rbtx4939_isastat_addr ((u8 __iomem *)RBTX4939_ISASTAT_ADDR)
99#define rbtx4939_pcistat_addr ((u8 __iomem *)RBTX4939_PCISTAT_ADDR)
100#define rbtx4939_rome_addr ((u8 __iomem *)RBTX4939_ROME_ADDR)
101#define rbtx4939_spics_addr ((u8 __iomem *)RBTX4939_SPICS_ADDR)
102#define rbtx4939_audi_addr ((u8 __iomem *)RBTX4939_AUDI_ADDR)
103#define rbtx4939_isagpio_addr ((u8 __iomem *)RBTX4939_ISAGPIO_ADDR)
104#define rbtx4939_pe1_addr ((u8 __iomem *)RBTX4939_PE1_ADDR)
105#define rbtx4939_pe2_addr ((u8 __iomem *)RBTX4939_PE2_ADDR)
106#define rbtx4939_pe3_addr ((u8 __iomem *)RBTX4939_PE3_ADDR)
107#define rbtx4939_vp_addr ((u8 __iomem *)RBTX4939_VP_ADDR)
108#define rbtx4939_vpreset_addr ((u8 __iomem *)RBTX4939_VPRESET_ADDR)
109#define rbtx4939_vpsout_addr ((u8 __iomem *)RBTX4939_VPSOUT_ADDR)
110#define rbtx4939_vpsin_addr ((u8 __iomem *)RBTX4939_VPSIN_ADDR)
111#define rbtx4939_7seg_addr(s, ch) \
112 ((u8 __iomem *)RBTX4939_7SEG_ADDR(s, ch))
113#define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR)
114#define rbtx4939_reseten_addr ((u8 __iomem *)RBTX4939_RESETEN_ADDR)
115#define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR)
116
117/*
118 * IRQ mappings
119 */
120#define RBTX4939_NR_IRQ_IOC 8
121
122#define RBTX4939_IRQ_IOC (TXX9_IRQ_BASE + TX4939_NUM_IR)
123#define RBTX4939_IRQ_END (RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC)
124
125/* IOC (ISA, etc) */
126#define RBTX4939_IRQ_IOCINT (TXX9_IRQ_BASE + TX4939_IR_INT(0))
127/* Onboard 10M Ether */
128#define RBTX4939_IRQ_ETHER (TXX9_IRQ_BASE + TX4939_IR_INT(1))
129
130void rbtx4939_prom_init(void);
131void rbtx4939_irq_setup(void);
132
133#endif /* __ASM_TXX9_RBTX4939_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 23:41:29 -0500