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-rw-r--r--drivers/net/Kconfig7
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/niu.c7939
-rw-r--r--drivers/net/niu.h3222
4 files changed, 11169 insertions, 0 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 0e48b294200e..9c635a237a9d 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2594,6 +2594,13 @@ config NETXEN_NIC
2594 help 2594 help
2595 This enables the support for NetXen's Gigabit Ethernet card. 2595 This enables the support for NetXen's Gigabit Ethernet card.
2596 2596
2597config NIU
2598 tristate "Sun Neptune 10Gbit Ethernet support"
2599 depends on PCI
2600 help
2601 This enables support for cards based upon Sun's
2602 Neptune chipset.
2603
2597config PASEMI_MAC 2604config PASEMI_MAC
2598 tristate "PA Semi 1/10Gbit MAC" 2605 tristate "PA Semi 1/10Gbit MAC"
2599 depends on PPC64 && PCI 2606 depends on PPC64 && PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index eb5c655e26d5..d2e0f35da42e 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -241,3 +241,4 @@ obj-$(CONFIG_NETCONSOLE) += netconsole.o
241obj-$(CONFIG_FS_ENET) += fs_enet/ 241obj-$(CONFIG_FS_ENET) += fs_enet/
242 242
243obj-$(CONFIG_NETXEN_NIC) += netxen/ 243obj-$(CONFIG_NETXEN_NIC) += netxen/
244obj-$(CONFIG_NIU) += niu.o
diff --git a/drivers/net/niu.c b/drivers/net/niu.c
new file mode 100644
index 000000000000..43bfe7e6b6f5
--- /dev/null
+++ b/drivers/net/niu.c
@@ -0,0 +1,7939 @@
1/* niu.c: Neptune ethernet driver.
2 *
3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/module.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/dma-mapping.h>
10#include <linux/netdevice.h>
11#include <linux/ethtool.h>
12#include <linux/etherdevice.h>
13#include <linux/platform_device.h>
14#include <linux/delay.h>
15#include <linux/bitops.h>
16#include <linux/mii.h>
17#include <linux/if_ether.h>
18#include <linux/if_vlan.h>
19#include <linux/ip.h>
20#include <linux/in.h>
21#include <linux/ipv6.h>
22#include <linux/log2.h>
23#include <linux/jiffies.h>
24#include <linux/crc32.h>
25
26#include <linux/io.h>
27
28#ifdef CONFIG_SPARC64
29#include <linux/of_device.h>
30#endif
31
32#include "niu.h"
33
34#define DRV_MODULE_NAME "niu"
35#define PFX DRV_MODULE_NAME ": "
36#define DRV_MODULE_VERSION "0.5"
37#define DRV_MODULE_RELDATE "October 5, 2007"
38
39static char version[] __devinitdata =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43MODULE_DESCRIPTION("NIU ethernet driver");
44MODULE_LICENSE("GPL");
45MODULE_VERSION(DRV_MODULE_VERSION);
46
47#ifndef DMA_44BIT_MASK
48#define DMA_44BIT_MASK 0x00000fffffffffffULL
49#endif
50
51#ifndef readq
52static u64 readq(void __iomem *reg)
53{
54 return (((u64)readl(reg + 0x4UL) << 32) |
55 (u64)readl(reg));
56}
57
58static void writeq(u64 val, void __iomem *reg)
59{
60 writel(val & 0xffffffff, reg);
61 writel(val >> 32, reg + 0x4UL);
62}
63#endif
64
65static struct pci_device_id niu_pci_tbl[] = {
66 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
67 {}
68};
69
70MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
71
72#define NIU_TX_TIMEOUT (5 * HZ)
73
74#define nr64(reg) readq(np->regs + (reg))
75#define nw64(reg, val) writeq((val), np->regs + (reg))
76
77#define nr64_mac(reg) readq(np->mac_regs + (reg))
78#define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
79
80#define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
81#define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
82
83#define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
84#define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
85
86#define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
87#define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
88
89#define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
90
91static int niu_debug;
92static int debug = -1;
93module_param(debug, int, 0);
94MODULE_PARM_DESC(debug, "NIU debug level");
95
96#define niudbg(TYPE, f, a...) \
97do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
98 printk(KERN_DEBUG PFX f, ## a); \
99} while (0)
100
101#define niuinfo(TYPE, f, a...) \
102do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
103 printk(KERN_INFO PFX f, ## a); \
104} while (0)
105
106#define niuwarn(TYPE, f, a...) \
107do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
108 printk(KERN_WARNING PFX f, ## a); \
109} while (0)
110
111#define niu_lock_parent(np, flags) \
112 spin_lock_irqsave(&np->parent->lock, flags)
113#define niu_unlock_parent(np, flags) \
114 spin_unlock_irqrestore(&np->parent->lock, flags)
115
116static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
117 u64 bits, int limit, int delay)
118{
119 while (--limit >= 0) {
120 u64 val = nr64_mac(reg);
121
122 if (!(val & bits))
123 break;
124 udelay(delay);
125 }
126 if (limit < 0)
127 return -ENODEV;
128 return 0;
129}
130
131static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
132 u64 bits, int limit, int delay,
133 const char *reg_name)
134{
135 int err;
136
137 nw64_mac(reg, bits);
138 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
139 if (err)
140 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
141 "would not clear, val[%llx]\n",
142 np->dev->name, (unsigned long long) bits, reg_name,
143 (unsigned long long) nr64_mac(reg));
144 return err;
145}
146
147#define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
148({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
149 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
150})
151
152static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
153 u64 bits, int limit, int delay)
154{
155 while (--limit >= 0) {
156 u64 val = nr64_ipp(reg);
157
158 if (!(val & bits))
159 break;
160 udelay(delay);
161 }
162 if (limit < 0)
163 return -ENODEV;
164 return 0;
165}
166
167static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
168 u64 bits, int limit, int delay,
169 const char *reg_name)
170{
171 int err;
172 u64 val;
173
174 val = nr64_ipp(reg);
175 val |= bits;
176 nw64_ipp(reg, val);
177
178 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
179 if (err)
180 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
181 "would not clear, val[%llx]\n",
182 np->dev->name, (unsigned long long) bits, reg_name,
183 (unsigned long long) nr64_ipp(reg));
184 return err;
185}
186
187#define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
188({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
189 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
190})
191
192static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
193 u64 bits, int limit, int delay)
194{
195 while (--limit >= 0) {
196 u64 val = nr64(reg);
197
198 if (!(val & bits))
199 break;
200 udelay(delay);
201 }
202 if (limit < 0)
203 return -ENODEV;
204 return 0;
205}
206
207#define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
208({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
209 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
210})
211
212static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
213 u64 bits, int limit, int delay,
214 const char *reg_name)
215{
216 int err;
217
218 nw64(reg, bits);
219 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
220 if (err)
221 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
222 "would not clear, val[%llx]\n",
223 np->dev->name, (unsigned long long) bits, reg_name,
224 (unsigned long long) nr64(reg));
225 return err;
226}
227
228#define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
229({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
230 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
231})
232
233static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
234{
235 u64 val = (u64) lp->timer;
236
237 if (on)
238 val |= LDG_IMGMT_ARM;
239
240 nw64(LDG_IMGMT(lp->ldg_num), val);
241}
242
243static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
244{
245 unsigned long mask_reg, bits;
246 u64 val;
247
248 if (ldn < 0 || ldn > LDN_MAX)
249 return -EINVAL;
250
251 if (ldn < 64) {
252 mask_reg = LD_IM0(ldn);
253 bits = LD_IM0_MASK;
254 } else {
255 mask_reg = LD_IM1(ldn - 64);
256 bits = LD_IM1_MASK;
257 }
258
259 val = nr64(mask_reg);
260 if (on)
261 val &= ~bits;
262 else
263 val |= bits;
264 nw64(mask_reg, val);
265
266 return 0;
267}
268
269static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
270{
271 struct niu_parent *parent = np->parent;
272 int i;
273
274 for (i = 0; i <= LDN_MAX; i++) {
275 int err;
276
277 if (parent->ldg_map[i] != lp->ldg_num)
278 continue;
279
280 err = niu_ldn_irq_enable(np, i, on);
281 if (err)
282 return err;
283 }
284 return 0;
285}
286
287static int niu_enable_interrupts(struct niu *np, int on)
288{
289 int i;
290
291 for (i = 0; i < np->num_ldg; i++) {
292 struct niu_ldg *lp = &np->ldg[i];
293 int err;
294
295 err = niu_enable_ldn_in_ldg(np, lp, on);
296 if (err)
297 return err;
298 }
299 for (i = 0; i < np->num_ldg; i++)
300 niu_ldg_rearm(np, &np->ldg[i], on);
301
302 return 0;
303}
304
305static u32 phy_encode(u32 type, int port)
306{
307 return (type << (port * 2));
308}
309
310static u32 phy_decode(u32 val, int port)
311{
312 return (val >> (port * 2)) & PORT_TYPE_MASK;
313}
314
315static int mdio_wait(struct niu *np)
316{
317 int limit = 1000;
318 u64 val;
319
320 while (--limit > 0) {
321 val = nr64(MIF_FRAME_OUTPUT);
322 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
323 return val & MIF_FRAME_OUTPUT_DATA;
324
325 udelay(10);
326 }
327
328 return -ENODEV;
329}
330
331static int mdio_read(struct niu *np, int port, int dev, int reg)
332{
333 int err;
334
335 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
336 err = mdio_wait(np);
337 if (err < 0)
338 return err;
339
340 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
341 return mdio_wait(np);
342}
343
344static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
345{
346 int err;
347
348 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
349 err = mdio_wait(np);
350 if (err < 0)
351 return err;
352
353 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
354 err = mdio_wait(np);
355 if (err < 0)
356 return err;
357
358 return 0;
359}
360
361static int mii_read(struct niu *np, int port, int reg)
362{
363 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
364 return mdio_wait(np);
365}
366
367static int mii_write(struct niu *np, int port, int reg, int data)
368{
369 int err;
370
371 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
372 err = mdio_wait(np);
373 if (err < 0)
374 return err;
375
376 return 0;
377}
378
379static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
380{
381 int err;
382
383 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
384 ESR2_TI_PLL_TX_CFG_L(channel),
385 val & 0xffff);
386 if (!err)
387 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
388 ESR2_TI_PLL_TX_CFG_H(channel),
389 val >> 16);
390 return err;
391}
392
393static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
394{
395 int err;
396
397 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
398 ESR2_TI_PLL_RX_CFG_L(channel),
399 val & 0xffff);
400 if (!err)
401 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
402 ESR2_TI_PLL_RX_CFG_H(channel),
403 val >> 16);
404 return err;
405}
406
407/* Mode is always 10G fiber. */
408static int serdes_init_niu(struct niu *np)
409{
410 struct niu_link_config *lp = &np->link_config;
411 u32 tx_cfg, rx_cfg;
412 unsigned long i;
413
414 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
415 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
416 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
417 PLL_RX_CFG_EQ_LP_ADAPTIVE);
418
419 if (lp->loopback_mode == LOOPBACK_PHY) {
420 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
421
422 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
423 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
424
425 tx_cfg |= PLL_TX_CFG_ENTEST;
426 rx_cfg |= PLL_RX_CFG_ENTEST;
427 }
428
429 /* Initialize all 4 lanes of the SERDES. */
430 for (i = 0; i < 4; i++) {
431 int err = esr2_set_tx_cfg(np, i, tx_cfg);
432 if (err)
433 return err;
434 }
435
436 for (i = 0; i < 4; i++) {
437 int err = esr2_set_rx_cfg(np, i, rx_cfg);
438 if (err)
439 return err;
440 }
441
442 return 0;
443}
444
445static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
446{
447 int err;
448
449 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
450 if (err >= 0) {
451 *val = (err & 0xffff);
452 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
453 ESR_RXTX_CTRL_H(chan));
454 if (err >= 0)
455 *val |= ((err & 0xffff) << 16);
456 err = 0;
457 }
458 return err;
459}
460
461static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
462{
463 int err;
464
465 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
466 ESR_GLUE_CTRL0_L(chan));
467 if (err >= 0) {
468 *val = (err & 0xffff);
469 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
470 ESR_GLUE_CTRL0_H(chan));
471 if (err >= 0) {
472 *val |= ((err & 0xffff) << 16);
473 err = 0;
474 }
475 }
476 return err;
477}
478
479static int esr_read_reset(struct niu *np, u32 *val)
480{
481 int err;
482
483 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
484 ESR_RXTX_RESET_CTRL_L);
485 if (err >= 0) {
486 *val = (err & 0xffff);
487 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
488 ESR_RXTX_RESET_CTRL_H);
489 if (err >= 0) {
490 *val |= ((err & 0xffff) << 16);
491 err = 0;
492 }
493 }
494 return err;
495}
496
497static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
498{
499 int err;
500
501 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
502 ESR_RXTX_CTRL_L(chan), val & 0xffff);
503 if (!err)
504 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
505 ESR_RXTX_CTRL_H(chan), (val >> 16));
506 return err;
507}
508
509static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
510{
511 int err;
512
513 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
514 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
515 if (!err)
516 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
517 ESR_GLUE_CTRL0_H(chan), (val >> 16));
518 return err;
519}
520
521static int esr_reset(struct niu *np)
522{
523 u32 reset;
524 int err;
525
526 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
527 ESR_RXTX_RESET_CTRL_L, 0x0000);
528 if (err)
529 return err;
530 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
531 ESR_RXTX_RESET_CTRL_H, 0xffff);
532 if (err)
533 return err;
534 udelay(200);
535
536 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
537 ESR_RXTX_RESET_CTRL_L, 0xffff);
538 if (err)
539 return err;
540 udelay(200);
541
542 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
543 ESR_RXTX_RESET_CTRL_H, 0x0000);
544 if (err)
545 return err;
546 udelay(200);
547
548 err = esr_read_reset(np, &reset);
549 if (err)
550 return err;
551 if (reset != 0) {
552 dev_err(np->device, PFX "Port %u ESR_RESET "
553 "did not clear [%08x]\n",
554 np->port, reset);
555 return -ENODEV;
556 }
557
558 return 0;
559}
560
561static int serdes_init_10g(struct niu *np)
562{
563 struct niu_link_config *lp = &np->link_config;
564 unsigned long ctrl_reg, test_cfg_reg, i;
565 u64 ctrl_val, test_cfg_val, sig, mask, val;
566 int err;
567
568 switch (np->port) {
569 case 0:
570 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
571 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
572 break;
573 case 1:
574 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
575 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
576 break;
577
578 default:
579 return -EINVAL;
580 }
581 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
582 ENET_SERDES_CTRL_SDET_1 |
583 ENET_SERDES_CTRL_SDET_2 |
584 ENET_SERDES_CTRL_SDET_3 |
585 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
586 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
587 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
588 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
589 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
590 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
591 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
592 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
593 test_cfg_val = 0;
594
595 if (lp->loopback_mode == LOOPBACK_PHY) {
596 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
597 ENET_SERDES_TEST_MD_0_SHIFT) |
598 (ENET_TEST_MD_PAD_LOOPBACK <<
599 ENET_SERDES_TEST_MD_1_SHIFT) |
600 (ENET_TEST_MD_PAD_LOOPBACK <<
601 ENET_SERDES_TEST_MD_2_SHIFT) |
602 (ENET_TEST_MD_PAD_LOOPBACK <<
603 ENET_SERDES_TEST_MD_3_SHIFT));
604 }
605
606 nw64(ctrl_reg, ctrl_val);
607 nw64(test_cfg_reg, test_cfg_val);
608
609 /* Initialize all 4 lanes of the SERDES. */
610 for (i = 0; i < 4; i++) {
611 u32 rxtx_ctrl, glue0;
612
613 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
614 if (err)
615 return err;
616 err = esr_read_glue0(np, i, &glue0);
617 if (err)
618 return err;
619
620 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
621 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
622 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
623
624 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
625 ESR_GLUE_CTRL0_THCNT |
626 ESR_GLUE_CTRL0_BLTIME);
627 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
628 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
629 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
630 (BLTIME_300_CYCLES <<
631 ESR_GLUE_CTRL0_BLTIME_SHIFT));
632
633 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
634 if (err)
635 return err;
636 err = esr_write_glue0(np, i, glue0);
637 if (err)
638 return err;
639 }
640
641 err = esr_reset(np);
642 if (err)
643 return err;
644
645 sig = nr64(ESR_INT_SIGNALS);
646 switch (np->port) {
647 case 0:
648 mask = ESR_INT_SIGNALS_P0_BITS;
649 val = (ESR_INT_SRDY0_P0 |
650 ESR_INT_DET0_P0 |
651 ESR_INT_XSRDY_P0 |
652 ESR_INT_XDP_P0_CH3 |
653 ESR_INT_XDP_P0_CH2 |
654 ESR_INT_XDP_P0_CH1 |
655 ESR_INT_XDP_P0_CH0);
656 break;
657
658 case 1:
659 mask = ESR_INT_SIGNALS_P1_BITS;
660 val = (ESR_INT_SRDY0_P1 |
661 ESR_INT_DET0_P1 |
662 ESR_INT_XSRDY_P1 |
663 ESR_INT_XDP_P1_CH3 |
664 ESR_INT_XDP_P1_CH2 |
665 ESR_INT_XDP_P1_CH1 |
666 ESR_INT_XDP_P1_CH0);
667 break;
668
669 default:
670 return -EINVAL;
671 }
672
673 if ((sig & mask) != val) {
674 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
675 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
676 return -ENODEV;
677 }
678
679 return 0;
680}
681
682static int serdes_init_1g(struct niu *np)
683{
684 u64 val;
685
686 val = nr64(ENET_SERDES_1_PLL_CFG);
687 val &= ~ENET_SERDES_PLL_FBDIV2;
688 switch (np->port) {
689 case 0:
690 val |= ENET_SERDES_PLL_HRATE0;
691 break;
692 case 1:
693 val |= ENET_SERDES_PLL_HRATE1;
694 break;
695 case 2:
696 val |= ENET_SERDES_PLL_HRATE2;
697 break;
698 case 3:
699 val |= ENET_SERDES_PLL_HRATE3;
700 break;
701 default:
702 return -EINVAL;
703 }
704 nw64(ENET_SERDES_1_PLL_CFG, val);
705
706 return 0;
707}
708
709static int bcm8704_reset(struct niu *np)
710{
711 int err, limit;
712
713 err = mdio_read(np, np->phy_addr,
714 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
715 if (err < 0)
716 return err;
717 err |= BMCR_RESET;
718 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
719 MII_BMCR, err);
720 if (err)
721 return err;
722
723 limit = 1000;
724 while (--limit >= 0) {
725 err = mdio_read(np, np->phy_addr,
726 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
727 if (err < 0)
728 return err;
729 if (!(err & BMCR_RESET))
730 break;
731 }
732 if (limit < 0) {
733 dev_err(np->device, PFX "Port %u PHY will not reset "
734 "(bmcr=%04x)\n", np->port, (err & 0xffff));
735 return -ENODEV;
736 }
737 return 0;
738}
739
740/* When written, certain PHY registers need to be read back twice
741 * in order for the bits to settle properly.
742 */
743static int bcm8704_user_dev3_readback(struct niu *np, int reg)
744{
745 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
746 if (err < 0)
747 return err;
748 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
749 if (err < 0)
750 return err;
751 return 0;
752}
753
754static int bcm8704_init_user_dev3(struct niu *np)
755{
756 int err;
757
758 err = mdio_write(np, np->phy_addr,
759 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
760 (USER_CONTROL_OPTXRST_LVL |
761 USER_CONTROL_OPBIASFLT_LVL |
762 USER_CONTROL_OBTMPFLT_LVL |
763 USER_CONTROL_OPPRFLT_LVL |
764 USER_CONTROL_OPTXFLT_LVL |
765 USER_CONTROL_OPRXLOS_LVL |
766 USER_CONTROL_OPRXFLT_LVL |
767 USER_CONTROL_OPTXON_LVL |
768 (0x3f << USER_CONTROL_RES1_SHIFT)));
769 if (err)
770 return err;
771
772 err = mdio_write(np, np->phy_addr,
773 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
774 (USER_PMD_TX_CTL_XFP_CLKEN |
775 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
776 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
777 USER_PMD_TX_CTL_TSCK_LPWREN));
778 if (err)
779 return err;
780
781 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
782 if (err)
783 return err;
784 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
785 if (err)
786 return err;
787
788 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
789 BCM8704_USER_OPT_DIGITAL_CTRL);
790 if (err < 0)
791 return err;
792 err &= ~USER_ODIG_CTRL_GPIOS;
793 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
794 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
795 BCM8704_USER_OPT_DIGITAL_CTRL, err);
796 if (err)
797 return err;
798
799 mdelay(1000);
800
801 return 0;
802}
803
804static int xcvr_init_10g(struct niu *np)
805{
806 struct niu_link_config *lp = &np->link_config;
807 u16 analog_stat0, tx_alarm_status;
808 int err;
809 u64 val;
810
811 val = nr64_mac(XMAC_CONFIG);
812 val &= ~XMAC_CONFIG_LED_POLARITY;
813 val |= XMAC_CONFIG_FORCE_LED_ON;
814 nw64_mac(XMAC_CONFIG, val);
815
816 /* XXX shared resource, lock parent XXX */
817 val = nr64(MIF_CONFIG);
818 val |= MIF_CONFIG_INDIRECT_MODE;
819 nw64(MIF_CONFIG, val);
820
821 err = bcm8704_reset(np);
822 if (err)
823 return err;
824
825 err = bcm8704_init_user_dev3(np);
826 if (err)
827 return err;
828
829 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
830 MII_BMCR);
831 if (err < 0)
832 return err;
833 err &= ~BMCR_LOOPBACK;
834
835 if (lp->loopback_mode == LOOPBACK_MAC)
836 err |= BMCR_LOOPBACK;
837
838 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
839 MII_BMCR, err);
840 if (err)
841 return err;
842
843#if 1
844 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
845 MII_STAT1000);
846 if (err < 0)
847 return err;
848 pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
849 np->port, err);
850
851 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
852 if (err < 0)
853 return err;
854 pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
855 np->port, err);
856
857 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
858 MII_NWAYTEST);
859 if (err < 0)
860 return err;
861 pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
862 np->port, err);
863#endif
864
865 /* XXX dig this out it might not be so useful XXX */
866 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
867 BCM8704_USER_ANALOG_STATUS0);
868 if (err < 0)
869 return err;
870 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
871 BCM8704_USER_ANALOG_STATUS0);
872 if (err < 0)
873 return err;
874 analog_stat0 = err;
875
876 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
877 BCM8704_USER_TX_ALARM_STATUS);
878 if (err < 0)
879 return err;
880 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
881 BCM8704_USER_TX_ALARM_STATUS);
882 if (err < 0)
883 return err;
884 tx_alarm_status = err;
885
886 if (analog_stat0 != 0x03fc) {
887 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
888 pr_info(PFX "Port %u cable not connected "
889 "or bad cable.\n", np->port);
890 } else if (analog_stat0 == 0x639c) {
891 pr_info(PFX "Port %u optical module is bad "
892 "or missing.\n", np->port);
893 }
894 }
895
896 return 0;
897}
898
899static int mii_reset(struct niu *np)
900{
901 int limit, err;
902
903 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
904 if (err)
905 return err;
906
907 limit = 1000;
908 while (--limit >= 0) {
909 udelay(500);
910 err = mii_read(np, np->phy_addr, MII_BMCR);
911 if (err < 0)
912 return err;
913 if (!(err & BMCR_RESET))
914 break;
915 }
916 if (limit < 0) {
917 dev_err(np->device, PFX "Port %u MII would not reset, "
918 "bmcr[%04x]\n", np->port, err);
919 return -ENODEV;
920 }
921
922 return 0;
923}
924
925static int mii_init_common(struct niu *np)
926{
927 struct niu_link_config *lp = &np->link_config;
928 u16 bmcr, bmsr, adv, estat;
929 int err;
930
931 err = mii_reset(np);
932 if (err)
933 return err;
934
935 err = mii_read(np, np->phy_addr, MII_BMSR);
936 if (err < 0)
937 return err;
938 bmsr = err;
939
940 estat = 0;
941 if (bmsr & BMSR_ESTATEN) {
942 err = mii_read(np, np->phy_addr, MII_ESTATUS);
943 if (err < 0)
944 return err;
945 estat = err;
946 }
947
948 bmcr = 0;
949 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
950 if (err)
951 return err;
952
953 if (lp->loopback_mode == LOOPBACK_MAC) {
954 bmcr |= BMCR_LOOPBACK;
955 if (lp->active_speed == SPEED_1000)
956 bmcr |= BMCR_SPEED1000;
957 if (lp->active_duplex == DUPLEX_FULL)
958 bmcr |= BMCR_FULLDPLX;
959 }
960
961 if (lp->loopback_mode == LOOPBACK_PHY) {
962 u16 aux;
963
964 aux = (BCM5464R_AUX_CTL_EXT_LB |
965 BCM5464R_AUX_CTL_WRITE_1);
966 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
967 if (err)
968 return err;
969 }
970
971 /* XXX configurable XXX */
972 /* XXX for now don't advertise half-duplex or asym pause... XXX */
973 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
974 if (bmsr & BMSR_10FULL)
975 adv |= ADVERTISE_10FULL;
976 if (bmsr & BMSR_100FULL)
977 adv |= ADVERTISE_100FULL;
978 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
979 if (err)
980 return err;
981
982 if (bmsr & BMSR_ESTATEN) {
983 u16 ctrl1000 = 0;
984
985 if (estat & ESTATUS_1000_TFULL)
986 ctrl1000 |= ADVERTISE_1000FULL;
987 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
988 if (err)
989 return err;
990 }
991 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
992
993 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
994 if (err)
995 return err;
996
997 err = mii_read(np, np->phy_addr, MII_BMCR);
998 if (err < 0)
999 return err;
1000 err = mii_read(np, np->phy_addr, MII_BMSR);
1001 if (err < 0)
1002 return err;
1003#if 0
1004 pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1005 np->port, bmcr, bmsr);
1006#endif
1007
1008 return 0;
1009}
1010
1011static int xcvr_init_1g(struct niu *np)
1012{
1013 u64 val;
1014
1015 /* XXX shared resource, lock parent XXX */
1016 val = nr64(MIF_CONFIG);
1017 val &= ~MIF_CONFIG_INDIRECT_MODE;
1018 nw64(MIF_CONFIG, val);
1019
1020 return mii_init_common(np);
1021}
1022
1023static int niu_xcvr_init(struct niu *np)
1024{
1025 const struct niu_phy_ops *ops = np->phy_ops;
1026 int err;
1027
1028 err = 0;
1029 if (ops->xcvr_init)
1030 err = ops->xcvr_init(np);
1031
1032 return err;
1033}
1034
1035static int niu_serdes_init(struct niu *np)
1036{
1037 const struct niu_phy_ops *ops = np->phy_ops;
1038 int err;
1039
1040 err = 0;
1041 if (ops->serdes_init)
1042 err = ops->serdes_init(np);
1043
1044 return err;
1045}
1046
1047static void niu_init_xif(struct niu *);
1048
1049static int niu_link_status_common(struct niu *np, int link_up)
1050{
1051 struct niu_link_config *lp = &np->link_config;
1052 struct net_device *dev = np->dev;
1053 unsigned long flags;
1054
1055 if (!netif_carrier_ok(dev) && link_up) {
1056 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1057 dev->name,
1058 (lp->active_speed == SPEED_10000 ?
1059 "10Gb/sec" :
1060 (lp->active_speed == SPEED_1000 ?
1061 "1Gb/sec" :
1062 (lp->active_speed == SPEED_100 ?
1063 "100Mbit/sec" : "10Mbit/sec"))),
1064 (lp->active_duplex == DUPLEX_FULL ?
1065 "full" : "half"));
1066
1067 spin_lock_irqsave(&np->lock, flags);
1068 niu_init_xif(np);
1069 spin_unlock_irqrestore(&np->lock, flags);
1070
1071 netif_carrier_on(dev);
1072 } else if (netif_carrier_ok(dev) && !link_up) {
1073 niuwarn(LINK, "%s: Link is down\n", dev->name);
1074 netif_carrier_off(dev);
1075 }
1076
1077 return 0;
1078}
1079
1080static int link_status_10g(struct niu *np, int *link_up_p)
1081{
1082 unsigned long flags;
1083 int err, link_up;
1084
1085 link_up = 0;
1086
1087 spin_lock_irqsave(&np->lock, flags);
1088
1089 err = -EINVAL;
1090 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
1091 goto out;
1092
1093 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1094 BCM8704_PMD_RCV_SIGDET);
1095 if (err < 0)
1096 goto out;
1097 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1098 err = 0;
1099 goto out;
1100 }
1101
1102 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1103 BCM8704_PCS_10G_R_STATUS);
1104 if (err < 0)
1105 goto out;
1106 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1107 err = 0;
1108 goto out;
1109 }
1110
1111 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1112 BCM8704_PHYXS_XGXS_LANE_STAT);
1113 if (err < 0)
1114 goto out;
1115
1116 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1117 PHYXS_XGXS_LANE_STAT_MAGIC |
1118 PHYXS_XGXS_LANE_STAT_LANE3 |
1119 PHYXS_XGXS_LANE_STAT_LANE2 |
1120 PHYXS_XGXS_LANE_STAT_LANE1 |
1121 PHYXS_XGXS_LANE_STAT_LANE0)) {
1122 err = 0;
1123 goto out;
1124 }
1125
1126 link_up = 1;
1127 np->link_config.active_speed = SPEED_10000;
1128 np->link_config.active_duplex = DUPLEX_FULL;
1129 err = 0;
1130
1131out:
1132 spin_unlock_irqrestore(&np->lock, flags);
1133
1134 *link_up_p = link_up;
1135 return err;
1136}
1137
1138static int link_status_1g(struct niu *np, int *link_up_p)
1139{
1140 u16 current_speed, bmsr;
1141 unsigned long flags;
1142 u8 current_duplex;
1143 int err, link_up;
1144
1145 link_up = 0;
1146 current_speed = SPEED_INVALID;
1147 current_duplex = DUPLEX_INVALID;
1148
1149 spin_lock_irqsave(&np->lock, flags);
1150
1151 err = -EINVAL;
1152 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
1153 goto out;
1154
1155 err = mii_read(np, np->phy_addr, MII_BMSR);
1156 if (err < 0)
1157 goto out;
1158
1159 bmsr = err;
1160 if (bmsr & BMSR_LSTATUS) {
1161 u16 adv, lpa, common, estat;
1162
1163 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1164 if (err < 0)
1165 goto out;
1166 adv = err;
1167
1168 err = mii_read(np, np->phy_addr, MII_LPA);
1169 if (err < 0)
1170 goto out;
1171 lpa = err;
1172
1173 common = adv & lpa;
1174
1175 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1176 if (err < 0)
1177 goto out;
1178 estat = err;
1179
1180 link_up = 1;
1181 if (estat & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
1182 current_speed = SPEED_1000;
1183 if (estat & ESTATUS_1000_TFULL)
1184 current_duplex = DUPLEX_FULL;
1185 else
1186 current_duplex = DUPLEX_HALF;
1187 } else {
1188 if (common & ADVERTISE_100BASE4) {
1189 current_speed = SPEED_100;
1190 current_duplex = DUPLEX_HALF;
1191 } else if (common & ADVERTISE_100FULL) {
1192 current_speed = SPEED_100;
1193 current_duplex = DUPLEX_FULL;
1194 } else if (common & ADVERTISE_100HALF) {
1195 current_speed = SPEED_100;
1196 current_duplex = DUPLEX_HALF;
1197 } else if (common & ADVERTISE_10FULL) {
1198 current_speed = SPEED_10;
1199 current_duplex = DUPLEX_FULL;
1200 } else if (common & ADVERTISE_10HALF) {
1201 current_speed = SPEED_10;
1202 current_duplex = DUPLEX_HALF;
1203 } else
1204 link_up = 0;
1205 }
1206 }
1207 err = 0;
1208
1209out:
1210 spin_unlock_irqrestore(&np->lock, flags);
1211
1212 *link_up_p = link_up;
1213 return err;
1214}
1215
1216static int niu_link_status(struct niu *np, int *link_up_p)
1217{
1218 const struct niu_phy_ops *ops = np->phy_ops;
1219 int err;
1220
1221 err = 0;
1222 if (ops->link_status)
1223 err = ops->link_status(np, link_up_p);
1224
1225 return err;
1226}
1227
1228static void niu_timer(unsigned long __opaque)
1229{
1230 struct niu *np = (struct niu *) __opaque;
1231 unsigned long off;
1232 int err, link_up;
1233
1234 err = niu_link_status(np, &link_up);
1235 if (!err)
1236 niu_link_status_common(np, link_up);
1237
1238 if (netif_carrier_ok(np->dev))
1239 off = 5 * HZ;
1240 else
1241 off = 1 * HZ;
1242 np->timer.expires = jiffies + off;
1243
1244 add_timer(&np->timer);
1245}
1246
1247static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
1248 .serdes_init = serdes_init_niu,
1249 .xcvr_init = xcvr_init_10g,
1250 .link_status = link_status_10g,
1251};
1252
1253static const struct niu_phy_ops phy_ops_10g_fiber = {
1254 .serdes_init = serdes_init_10g,
1255 .xcvr_init = xcvr_init_10g,
1256 .link_status = link_status_10g,
1257};
1258
1259static const struct niu_phy_ops phy_ops_10g_copper = {
1260 .serdes_init = serdes_init_10g,
1261 .link_status = link_status_10g, /* XXX */
1262};
1263
1264static const struct niu_phy_ops phy_ops_1g_fiber = {
1265 .serdes_init = serdes_init_1g,
1266 .xcvr_init = xcvr_init_1g,
1267 .link_status = link_status_1g,
1268};
1269
1270static const struct niu_phy_ops phy_ops_1g_copper = {
1271 .xcvr_init = xcvr_init_1g,
1272 .link_status = link_status_1g,
1273};
1274
1275struct niu_phy_template {
1276 const struct niu_phy_ops *ops;
1277 u32 phy_addr_base;
1278};
1279
1280static const struct niu_phy_template phy_template_niu = {
1281 .ops = &phy_ops_10g_fiber_niu,
1282 .phy_addr_base = 16,
1283};
1284
1285static const struct niu_phy_template phy_template_10g_fiber = {
1286 .ops = &phy_ops_10g_fiber,
1287 .phy_addr_base = 8,
1288};
1289
1290static const struct niu_phy_template phy_template_10g_copper = {
1291 .ops = &phy_ops_10g_copper,
1292 .phy_addr_base = 10,
1293};
1294
1295static const struct niu_phy_template phy_template_1g_fiber = {
1296 .ops = &phy_ops_1g_fiber,
1297 .phy_addr_base = 0,
1298};
1299
1300static const struct niu_phy_template phy_template_1g_copper = {
1301 .ops = &phy_ops_1g_copper,
1302 .phy_addr_base = 0,
1303};
1304
1305static int niu_determine_phy_disposition(struct niu *np)
1306{
1307 struct niu_parent *parent = np->parent;
1308 u8 plat_type = parent->plat_type;
1309 const struct niu_phy_template *tp;
1310 u32 phy_addr_off = 0;
1311
1312 if (plat_type == PLAT_TYPE_NIU) {
1313 tp = &phy_template_niu;
1314 phy_addr_off += np->port;
1315 } else {
1316 switch (np->flags & (NIU_FLAGS_10G | NIU_FLAGS_FIBER)) {
1317 case 0:
1318 /* 1G copper */
1319 tp = &phy_template_1g_copper;
1320 if (plat_type == PLAT_TYPE_VF_P0)
1321 phy_addr_off = 10;
1322 else if (plat_type == PLAT_TYPE_VF_P1)
1323 phy_addr_off = 26;
1324
1325 phy_addr_off += (np->port ^ 0x3);
1326 break;
1327
1328 case NIU_FLAGS_10G:
1329 /* 10G copper */
1330 tp = &phy_template_1g_copper;
1331 break;
1332
1333 case NIU_FLAGS_FIBER:
1334 /* 1G fiber */
1335 tp = &phy_template_1g_fiber;
1336 break;
1337
1338 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
1339 /* 10G fiber */
1340 tp = &phy_template_10g_fiber;
1341 if (plat_type == PLAT_TYPE_VF_P0 ||
1342 plat_type == PLAT_TYPE_VF_P1)
1343 phy_addr_off = 8;
1344 phy_addr_off += np->port;
1345 break;
1346
1347 default:
1348 return -EINVAL;
1349 }
1350 }
1351
1352 np->phy_ops = tp->ops;
1353 np->phy_addr = tp->phy_addr_base + phy_addr_off;
1354
1355 return 0;
1356}
1357
1358static int niu_init_link(struct niu *np)
1359{
1360 struct niu_parent *parent = np->parent;
1361 int err, ignore;
1362
1363 if (parent->plat_type == PLAT_TYPE_NIU) {
1364 err = niu_xcvr_init(np);
1365 if (err)
1366 return err;
1367 msleep(200);
1368 }
1369 err = niu_serdes_init(np);
1370 if (err)
1371 return err;
1372 msleep(200);
1373 err = niu_xcvr_init(np);
1374 if (!err)
1375 niu_link_status(np, &ignore);
1376 return 0;
1377}
1378
1379static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
1380{
1381 u16 reg0 = addr[4] << 8 | addr[5];
1382 u16 reg1 = addr[2] << 8 | addr[3];
1383 u16 reg2 = addr[0] << 8 | addr[1];
1384
1385 if (np->flags & NIU_FLAGS_XMAC) {
1386 nw64_mac(XMAC_ADDR0, reg0);
1387 nw64_mac(XMAC_ADDR1, reg1);
1388 nw64_mac(XMAC_ADDR2, reg2);
1389 } else {
1390 nw64_mac(BMAC_ADDR0, reg0);
1391 nw64_mac(BMAC_ADDR1, reg1);
1392 nw64_mac(BMAC_ADDR2, reg2);
1393 }
1394}
1395
1396static int niu_num_alt_addr(struct niu *np)
1397{
1398 if (np->flags & NIU_FLAGS_XMAC)
1399 return XMAC_NUM_ALT_ADDR;
1400 else
1401 return BMAC_NUM_ALT_ADDR;
1402}
1403
1404static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
1405{
1406 u16 reg0 = addr[4] << 8 | addr[5];
1407 u16 reg1 = addr[2] << 8 | addr[3];
1408 u16 reg2 = addr[0] << 8 | addr[1];
1409
1410 if (index >= niu_num_alt_addr(np))
1411 return -EINVAL;
1412
1413 if (np->flags & NIU_FLAGS_XMAC) {
1414 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
1415 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
1416 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
1417 } else {
1418 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
1419 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
1420 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
1421 }
1422
1423 return 0;
1424}
1425
1426static int niu_enable_alt_mac(struct niu *np, int index, int on)
1427{
1428 unsigned long reg;
1429 u64 val, mask;
1430
1431 if (index >= niu_num_alt_addr(np))
1432 return -EINVAL;
1433
1434 if (np->flags & NIU_FLAGS_XMAC)
1435 reg = XMAC_ADDR_CMPEN;
1436 else
1437 reg = BMAC_ADDR_CMPEN;
1438
1439 mask = 1 << index;
1440
1441 val = nr64_mac(reg);
1442 if (on)
1443 val |= mask;
1444 else
1445 val &= ~mask;
1446 nw64_mac(reg, val);
1447
1448 return 0;
1449}
1450
1451static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
1452 int num, int mac_pref)
1453{
1454 u64 val = nr64_mac(reg);
1455 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
1456 val |= num;
1457 if (mac_pref)
1458 val |= HOST_INFO_MPR;
1459 nw64_mac(reg, val);
1460}
1461
1462static int __set_rdc_table_num(struct niu *np,
1463 int xmac_index, int bmac_index,
1464 int rdc_table_num, int mac_pref)
1465{
1466 unsigned long reg;
1467
1468 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
1469 return -EINVAL;
1470 if (np->flags & NIU_FLAGS_XMAC)
1471 reg = XMAC_HOST_INFO(xmac_index);
1472 else
1473 reg = BMAC_HOST_INFO(bmac_index);
1474 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
1475 return 0;
1476}
1477
1478static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
1479 int mac_pref)
1480{
1481 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
1482}
1483
1484static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
1485 int mac_pref)
1486{
1487 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
1488}
1489
1490static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
1491 int table_num, int mac_pref)
1492{
1493 if (idx >= niu_num_alt_addr(np))
1494 return -EINVAL;
1495 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
1496}
1497
1498static u64 vlan_entry_set_parity(u64 reg_val)
1499{
1500 u64 port01_mask;
1501 u64 port23_mask;
1502
1503 port01_mask = 0x00ff;
1504 port23_mask = 0xff00;
1505
1506 if (hweight64(reg_val & port01_mask) & 1)
1507 reg_val |= ENET_VLAN_TBL_PARITY0;
1508 else
1509 reg_val &= ~ENET_VLAN_TBL_PARITY0;
1510
1511 if (hweight64(reg_val & port23_mask) & 1)
1512 reg_val |= ENET_VLAN_TBL_PARITY1;
1513 else
1514 reg_val &= ~ENET_VLAN_TBL_PARITY1;
1515
1516 return reg_val;
1517}
1518
1519static void vlan_tbl_write(struct niu *np, unsigned long index,
1520 int port, int vpr, int rdc_table)
1521{
1522 u64 reg_val = nr64(ENET_VLAN_TBL(index));
1523
1524 reg_val &= ~((ENET_VLAN_TBL_VPR |
1525 ENET_VLAN_TBL_VLANRDCTBLN) <<
1526 ENET_VLAN_TBL_SHIFT(port));
1527 if (vpr)
1528 reg_val |= (ENET_VLAN_TBL_VPR <<
1529 ENET_VLAN_TBL_SHIFT(port));
1530 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
1531
1532 reg_val = vlan_entry_set_parity(reg_val);
1533
1534 nw64(ENET_VLAN_TBL(index), reg_val);
1535}
1536
1537static void vlan_tbl_clear(struct niu *np)
1538{
1539 int i;
1540
1541 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
1542 nw64(ENET_VLAN_TBL(i), 0);
1543}
1544
1545static int tcam_wait_bit(struct niu *np, u64 bit)
1546{
1547 int limit = 1000;
1548
1549 while (--limit > 0) {
1550 if (nr64(TCAM_CTL) & bit)
1551 break;
1552 udelay(1);
1553 }
1554 if (limit < 0)
1555 return -ENODEV;
1556
1557 return 0;
1558}
1559
1560static int tcam_flush(struct niu *np, int index)
1561{
1562 nw64(TCAM_KEY_0, 0x00);
1563 nw64(TCAM_KEY_MASK_0, 0xff);
1564 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
1565
1566 return tcam_wait_bit(np, TCAM_CTL_STAT);
1567}
1568
1569#if 0
1570static int tcam_read(struct niu *np, int index,
1571 u64 *key, u64 *mask)
1572{
1573 int err;
1574
1575 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
1576 err = tcam_wait_bit(np, TCAM_CTL_STAT);
1577 if (!err) {
1578 key[0] = nr64(TCAM_KEY_0);
1579 key[1] = nr64(TCAM_KEY_1);
1580 key[2] = nr64(TCAM_KEY_2);
1581 key[3] = nr64(TCAM_KEY_3);
1582 mask[0] = nr64(TCAM_KEY_MASK_0);
1583 mask[1] = nr64(TCAM_KEY_MASK_1);
1584 mask[2] = nr64(TCAM_KEY_MASK_2);
1585 mask[3] = nr64(TCAM_KEY_MASK_3);
1586 }
1587 return err;
1588}
1589#endif
1590
1591static int tcam_write(struct niu *np, int index,
1592 u64 *key, u64 *mask)
1593{
1594 nw64(TCAM_KEY_0, key[0]);
1595 nw64(TCAM_KEY_1, key[1]);
1596 nw64(TCAM_KEY_2, key[2]);
1597 nw64(TCAM_KEY_3, key[3]);
1598 nw64(TCAM_KEY_MASK_0, mask[0]);
1599 nw64(TCAM_KEY_MASK_1, mask[1]);
1600 nw64(TCAM_KEY_MASK_2, mask[2]);
1601 nw64(TCAM_KEY_MASK_3, mask[3]);
1602 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
1603
1604 return tcam_wait_bit(np, TCAM_CTL_STAT);
1605}
1606
1607#if 0
1608static int tcam_assoc_read(struct niu *np, int index, u64 *data)
1609{
1610 int err;
1611
1612 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
1613 err = tcam_wait_bit(np, TCAM_CTL_STAT);
1614 if (!err)
1615 *data = nr64(TCAM_KEY_1);
1616
1617 return err;
1618}
1619#endif
1620
1621static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
1622{
1623 nw64(TCAM_KEY_1, assoc_data);
1624 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
1625
1626 return tcam_wait_bit(np, TCAM_CTL_STAT);
1627}
1628
1629static void tcam_enable(struct niu *np, int on)
1630{
1631 u64 val = nr64(FFLP_CFG_1);
1632
1633 if (on)
1634 val &= ~FFLP_CFG_1_TCAM_DIS;
1635 else
1636 val |= FFLP_CFG_1_TCAM_DIS;
1637 nw64(FFLP_CFG_1, val);
1638}
1639
1640static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
1641{
1642 u64 val = nr64(FFLP_CFG_1);
1643
1644 val &= ~(FFLP_CFG_1_FFLPINITDONE |
1645 FFLP_CFG_1_CAMLAT |
1646 FFLP_CFG_1_CAMRATIO);
1647 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
1648 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
1649 nw64(FFLP_CFG_1, val);
1650
1651 val = nr64(FFLP_CFG_1);
1652 val |= FFLP_CFG_1_FFLPINITDONE;
1653 nw64(FFLP_CFG_1, val);
1654}
1655
1656static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
1657 int on)
1658{
1659 unsigned long reg;
1660 u64 val;
1661
1662 if (class < CLASS_CODE_ETHERTYPE1 ||
1663 class > CLASS_CODE_ETHERTYPE2)
1664 return -EINVAL;
1665
1666 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
1667 val = nr64(reg);
1668 if (on)
1669 val |= L2_CLS_VLD;
1670 else
1671 val &= ~L2_CLS_VLD;
1672 nw64(reg, val);
1673
1674 return 0;
1675}
1676
1677#if 0
1678static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
1679 u64 ether_type)
1680{
1681 unsigned long reg;
1682 u64 val;
1683
1684 if (class < CLASS_CODE_ETHERTYPE1 ||
1685 class > CLASS_CODE_ETHERTYPE2 ||
1686 (ether_type & ~(u64)0xffff) != 0)
1687 return -EINVAL;
1688
1689 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
1690 val = nr64(reg);
1691 val &= ~L2_CLS_ETYPE;
1692 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
1693 nw64(reg, val);
1694
1695 return 0;
1696}
1697#endif
1698
1699static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
1700 int on)
1701{
1702 unsigned long reg;
1703 u64 val;
1704
1705 if (class < CLASS_CODE_USER_PROG1 ||
1706 class > CLASS_CODE_USER_PROG4)
1707 return -EINVAL;
1708
1709 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
1710 val = nr64(reg);
1711 if (on)
1712 val |= L3_CLS_VALID;
1713 else
1714 val &= ~L3_CLS_VALID;
1715 nw64(reg, val);
1716
1717 return 0;
1718}
1719
1720#if 0
1721static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
1722 int ipv6, u64 protocol_id,
1723 u64 tos_mask, u64 tos_val)
1724{
1725 unsigned long reg;
1726 u64 val;
1727
1728 if (class < CLASS_CODE_USER_PROG1 ||
1729 class > CLASS_CODE_USER_PROG4 ||
1730 (protocol_id & ~(u64)0xff) != 0 ||
1731 (tos_mask & ~(u64)0xff) != 0 ||
1732 (tos_val & ~(u64)0xff) != 0)
1733 return -EINVAL;
1734
1735 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
1736 val = nr64(reg);
1737 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
1738 L3_CLS_TOSMASK | L3_CLS_TOS);
1739 if (ipv6)
1740 val |= L3_CLS_IPVER;
1741 val |= (protocol_id << L3_CLS_PID_SHIFT);
1742 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
1743 val |= (tos_val << L3_CLS_TOS_SHIFT);
1744 nw64(reg, val);
1745
1746 return 0;
1747}
1748#endif
1749
1750static int tcam_early_init(struct niu *np)
1751{
1752 unsigned long i;
1753 int err;
1754
1755 tcam_enable(np, 0);
1756 tcam_set_lat_and_ratio(np,
1757 DEFAULT_TCAM_LATENCY,
1758 DEFAULT_TCAM_ACCESS_RATIO);
1759 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
1760 err = tcam_user_eth_class_enable(np, i, 0);
1761 if (err)
1762 return err;
1763 }
1764 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
1765 err = tcam_user_ip_class_enable(np, i, 0);
1766 if (err)
1767 return err;
1768 }
1769
1770 return 0;
1771}
1772
1773static int tcam_flush_all(struct niu *np)
1774{
1775 unsigned long i;
1776
1777 for (i = 0; i < np->parent->tcam_num_entries; i++) {
1778 int err = tcam_flush(np, i);
1779 if (err)
1780 return err;
1781 }
1782 return 0;
1783}
1784
1785static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
1786{
1787 return ((u64)index | (num_entries == 1 ?
1788 HASH_TBL_ADDR_AUTOINC : 0));
1789}
1790
1791#if 0
1792static int hash_read(struct niu *np, unsigned long partition,
1793 unsigned long index, unsigned long num_entries,
1794 u64 *data)
1795{
1796 u64 val = hash_addr_regval(index, num_entries);
1797 unsigned long i;
1798
1799 if (partition >= FCRAM_NUM_PARTITIONS ||
1800 index + num_entries > FCRAM_SIZE)
1801 return -EINVAL;
1802
1803 nw64(HASH_TBL_ADDR(partition), val);
1804 for (i = 0; i < num_entries; i++)
1805 data[i] = nr64(HASH_TBL_DATA(partition));
1806
1807 return 0;
1808}
1809#endif
1810
1811static int hash_write(struct niu *np, unsigned long partition,
1812 unsigned long index, unsigned long num_entries,
1813 u64 *data)
1814{
1815 u64 val = hash_addr_regval(index, num_entries);
1816 unsigned long i;
1817
1818 if (partition >= FCRAM_NUM_PARTITIONS ||
1819 index + (num_entries * 8) > FCRAM_SIZE)
1820 return -EINVAL;
1821
1822 nw64(HASH_TBL_ADDR(partition), val);
1823 for (i = 0; i < num_entries; i++)
1824 nw64(HASH_TBL_DATA(partition), data[i]);
1825
1826 return 0;
1827}
1828
1829static void fflp_reset(struct niu *np)
1830{
1831 u64 val;
1832
1833 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
1834 udelay(10);
1835 nw64(FFLP_CFG_1, 0);
1836
1837 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
1838 nw64(FFLP_CFG_1, val);
1839}
1840
1841static void fflp_set_timings(struct niu *np)
1842{
1843 u64 val = nr64(FFLP_CFG_1);
1844
1845 val &= ~FFLP_CFG_1_FFLPINITDONE;
1846 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
1847 nw64(FFLP_CFG_1, val);
1848
1849 val = nr64(FFLP_CFG_1);
1850 val |= FFLP_CFG_1_FFLPINITDONE;
1851 nw64(FFLP_CFG_1, val);
1852
1853 val = nr64(FCRAM_REF_TMR);
1854 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
1855 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
1856 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
1857 nw64(FCRAM_REF_TMR, val);
1858}
1859
1860static int fflp_set_partition(struct niu *np, u64 partition,
1861 u64 mask, u64 base, int enable)
1862{
1863 unsigned long reg;
1864 u64 val;
1865
1866 if (partition >= FCRAM_NUM_PARTITIONS ||
1867 (mask & ~(u64)0x1f) != 0 ||
1868 (base & ~(u64)0x1f) != 0)
1869 return -EINVAL;
1870
1871 reg = FLW_PRT_SEL(partition);
1872
1873 val = nr64(reg);
1874 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
1875 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
1876 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
1877 if (enable)
1878 val |= FLW_PRT_SEL_EXT;
1879 nw64(reg, val);
1880
1881 return 0;
1882}
1883
1884static int fflp_disable_all_partitions(struct niu *np)
1885{
1886 unsigned long i;
1887
1888 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
1889 int err = fflp_set_partition(np, 0, 0, 0, 0);
1890 if (err)
1891 return err;
1892 }
1893 return 0;
1894}
1895
1896static void fflp_llcsnap_enable(struct niu *np, int on)
1897{
1898 u64 val = nr64(FFLP_CFG_1);
1899
1900 if (on)
1901 val |= FFLP_CFG_1_LLCSNAP;
1902 else
1903 val &= ~FFLP_CFG_1_LLCSNAP;
1904 nw64(FFLP_CFG_1, val);
1905}
1906
1907static void fflp_errors_enable(struct niu *np, int on)
1908{
1909 u64 val = nr64(FFLP_CFG_1);
1910
1911 if (on)
1912 val &= ~FFLP_CFG_1_ERRORDIS;
1913 else
1914 val |= FFLP_CFG_1_ERRORDIS;
1915 nw64(FFLP_CFG_1, val);
1916}
1917
1918static int fflp_hash_clear(struct niu *np)
1919{
1920 struct fcram_hash_ipv4 ent;
1921 unsigned long i;
1922
1923 /* IPV4 hash entry with valid bit clear, rest is don't care. */
1924 memset(&ent, 0, sizeof(ent));
1925 ent.header = HASH_HEADER_EXT;
1926
1927 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
1928 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
1929 if (err)
1930 return err;
1931 }
1932 return 0;
1933}
1934
1935static int fflp_early_init(struct niu *np)
1936{
1937 struct niu_parent *parent;
1938 unsigned long flags;
1939 int err;
1940
1941 niu_lock_parent(np, flags);
1942
1943 parent = np->parent;
1944 err = 0;
1945 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
1946 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
1947 np->port);
1948 if (np->parent->plat_type != PLAT_TYPE_NIU) {
1949 fflp_reset(np);
1950 fflp_set_timings(np);
1951 err = fflp_disable_all_partitions(np);
1952 if (err) {
1953 niudbg(PROBE, "fflp_disable_all_partitions "
1954 "failed, err=%d\n", err);
1955 goto out;
1956 }
1957 }
1958
1959 err = tcam_early_init(np);
1960 if (err) {
1961 niudbg(PROBE, "tcam_early_init failed, err=%d\n",
1962 err);
1963 goto out;
1964 }
1965 fflp_llcsnap_enable(np, 1);
1966 fflp_errors_enable(np, 0);
1967 nw64(H1POLY, 0);
1968 nw64(H2POLY, 0);
1969
1970 err = tcam_flush_all(np);
1971 if (err) {
1972 niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
1973 err);
1974 goto out;
1975 }
1976 if (np->parent->plat_type != PLAT_TYPE_NIU) {
1977 err = fflp_hash_clear(np);
1978 if (err) {
1979 niudbg(PROBE, "fflp_hash_clear failed, "
1980 "err=%d\n", err);
1981 goto out;
1982 }
1983 }
1984
1985 vlan_tbl_clear(np);
1986
1987 niudbg(PROBE, "fflp_early_init: Success\n");
1988 parent->flags |= PARENT_FLGS_CLS_HWINIT;
1989 }
1990out:
1991 niu_unlock_parent(np, flags);
1992 return err;
1993}
1994
1995static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
1996{
1997 if (class_code < CLASS_CODE_USER_PROG1 ||
1998 class_code > CLASS_CODE_SCTP_IPV6)
1999 return -EINVAL;
2000
2001 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2002 return 0;
2003}
2004
2005static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
2006{
2007 if (class_code < CLASS_CODE_USER_PROG1 ||
2008 class_code > CLASS_CODE_SCTP_IPV6)
2009 return -EINVAL;
2010
2011 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2012 return 0;
2013}
2014
2015static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
2016 u32 offset, u32 size)
2017{
2018 int i = skb_shinfo(skb)->nr_frags;
2019 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2020
2021 frag->page = page;
2022 frag->page_offset = offset;
2023 frag->size = size;
2024
2025 skb->len += size;
2026 skb->data_len += size;
2027 skb->truesize += size;
2028
2029 skb_shinfo(skb)->nr_frags = i + 1;
2030}
2031
2032static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
2033{
2034 a >>= PAGE_SHIFT;
2035 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
2036
2037 return (a & (MAX_RBR_RING_SIZE - 1));
2038}
2039
2040static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
2041 struct page ***link)
2042{
2043 unsigned int h = niu_hash_rxaddr(rp, addr);
2044 struct page *p, **pp;
2045
2046 addr &= PAGE_MASK;
2047 pp = &rp->rxhash[h];
2048 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
2049 if (p->index == addr) {
2050 *link = pp;
2051 break;
2052 }
2053 }
2054
2055 return p;
2056}
2057
2058static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
2059{
2060 unsigned int h = niu_hash_rxaddr(rp, base);
2061
2062 page->index = base;
2063 page->mapping = (struct address_space *) rp->rxhash[h];
2064 rp->rxhash[h] = page;
2065}
2066
2067static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
2068 gfp_t mask, int start_index)
2069{
2070 struct page *page;
2071 u64 addr;
2072 int i;
2073
2074 page = alloc_page(mask);
2075 if (!page)
2076 return -ENOMEM;
2077
2078 addr = np->ops->map_page(np->device, page, 0,
2079 PAGE_SIZE, DMA_FROM_DEVICE);
2080
2081 niu_hash_page(rp, page, addr);
2082 if (rp->rbr_blocks_per_page > 1)
2083 atomic_add(rp->rbr_blocks_per_page - 1,
2084 &compound_head(page)->_count);
2085
2086 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
2087 __le32 *rbr = &rp->rbr[start_index + i];
2088
2089 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
2090 addr += rp->rbr_block_size;
2091 }
2092
2093 return 0;
2094}
2095
2096static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
2097{
2098 int index = rp->rbr_index;
2099
2100 rp->rbr_pending++;
2101 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
2102 int err = niu_rbr_add_page(np, rp, mask, index);
2103
2104 if (unlikely(err)) {
2105 rp->rbr_pending--;
2106 return;
2107 }
2108
2109 rp->rbr_index += rp->rbr_blocks_per_page;
2110 BUG_ON(rp->rbr_index > rp->rbr_table_size);
2111 if (rp->rbr_index == rp->rbr_table_size)
2112 rp->rbr_index = 0;
2113
2114 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
2115 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
2116 rp->rbr_pending = 0;
2117 }
2118 }
2119}
2120
2121static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
2122{
2123 unsigned int index = rp->rcr_index;
2124 int num_rcr = 0;
2125
2126 rp->rx_dropped++;
2127 while (1) {
2128 struct page *page, **link;
2129 u64 addr, val;
2130 u32 rcr_size;
2131
2132 num_rcr++;
2133
2134 val = le64_to_cpup(&rp->rcr[index]);
2135 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
2136 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
2137 page = niu_find_rxpage(rp, addr, &link);
2138
2139 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
2140 RCR_ENTRY_PKTBUFSZ_SHIFT];
2141 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
2142 *link = (struct page *) page->mapping;
2143 np->ops->unmap_page(np->device, page->index,
2144 PAGE_SIZE, DMA_FROM_DEVICE);
2145 page->index = 0;
2146 page->mapping = NULL;
2147 __free_page(page);
2148 rp->rbr_refill_pending++;
2149 }
2150
2151 index = NEXT_RCR(rp, index);
2152 if (!(val & RCR_ENTRY_MULTI))
2153 break;
2154
2155 }
2156 rp->rcr_index = index;
2157
2158 return num_rcr;
2159}
2160
2161static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
2162{
2163 unsigned int index = rp->rcr_index;
2164 struct sk_buff *skb;
2165 int len, num_rcr;
2166
2167 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
2168 if (unlikely(!skb))
2169 return niu_rx_pkt_ignore(np, rp);
2170
2171 num_rcr = 0;
2172 while (1) {
2173 struct page *page, **link;
2174 u32 rcr_size, append_size;
2175 u64 addr, val, off;
2176
2177 num_rcr++;
2178
2179 val = le64_to_cpup(&rp->rcr[index]);
2180
2181 len = (val & RCR_ENTRY_L2_LEN) >>
2182 RCR_ENTRY_L2_LEN_SHIFT;
2183 len -= ETH_FCS_LEN;
2184
2185 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
2186 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
2187 page = niu_find_rxpage(rp, addr, &link);
2188
2189 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
2190 RCR_ENTRY_PKTBUFSZ_SHIFT];
2191
2192 off = addr & ~PAGE_MASK;
2193 append_size = rcr_size;
2194 if (num_rcr == 1) {
2195 int ptype;
2196
2197 off += 2;
2198 append_size -= 2;
2199
2200 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
2201 if ((ptype == RCR_PKT_TYPE_TCP ||
2202 ptype == RCR_PKT_TYPE_UDP) &&
2203 !(val & (RCR_ENTRY_NOPORT |
2204 RCR_ENTRY_ERROR)))
2205 skb->ip_summed = CHECKSUM_UNNECESSARY;
2206 else
2207 skb->ip_summed = CHECKSUM_NONE;
2208 }
2209 if (!(val & RCR_ENTRY_MULTI))
2210 append_size = len - skb->len;
2211
2212 niu_rx_skb_append(skb, page, off, append_size);
2213 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
2214 *link = (struct page *) page->mapping;
2215 np->ops->unmap_page(np->device, page->index,
2216 PAGE_SIZE, DMA_FROM_DEVICE);
2217 page->index = 0;
2218 page->mapping = NULL;
2219 rp->rbr_refill_pending++;
2220 } else
2221 get_page(page);
2222
2223 index = NEXT_RCR(rp, index);
2224 if (!(val & RCR_ENTRY_MULTI))
2225 break;
2226
2227 }
2228 rp->rcr_index = index;
2229
2230 skb_reserve(skb, NET_IP_ALIGN);
2231 __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
2232
2233 rp->rx_packets++;
2234 rp->rx_bytes += skb->len;
2235
2236 skb->protocol = eth_type_trans(skb, np->dev);
2237 netif_receive_skb(skb);
2238
2239 return num_rcr;
2240}
2241
2242static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
2243{
2244 int blocks_per_page = rp->rbr_blocks_per_page;
2245 int err, index = rp->rbr_index;
2246
2247 err = 0;
2248 while (index < (rp->rbr_table_size - blocks_per_page)) {
2249 err = niu_rbr_add_page(np, rp, mask, index);
2250 if (err)
2251 break;
2252
2253 index += blocks_per_page;
2254 }
2255
2256 rp->rbr_index = index;
2257 return err;
2258}
2259
2260static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
2261{
2262 int i;
2263
2264 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
2265 struct page *page;
2266
2267 page = rp->rxhash[i];
2268 while (page) {
2269 struct page *next = (struct page *) page->mapping;
2270 u64 base = page->index;
2271
2272 np->ops->unmap_page(np->device, base, PAGE_SIZE,
2273 DMA_FROM_DEVICE);
2274 page->index = 0;
2275 page->mapping = NULL;
2276
2277 __free_page(page);
2278
2279 page = next;
2280 }
2281 }
2282
2283 for (i = 0; i < rp->rbr_table_size; i++)
2284 rp->rbr[i] = cpu_to_le32(0);
2285 rp->rbr_index = 0;
2286}
2287
2288static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
2289{
2290 struct tx_buff_info *tb = &rp->tx_buffs[idx];
2291 struct sk_buff *skb = tb->skb;
2292 struct tx_pkt_hdr *tp;
2293 u64 tx_flags;
2294 int i, len;
2295
2296 tp = (struct tx_pkt_hdr *) skb->data;
2297 tx_flags = le64_to_cpup(&tp->flags);
2298
2299 rp->tx_packets++;
2300 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
2301 ((tx_flags & TXHDR_PAD) / 2));
2302
2303 len = skb_headlen(skb);
2304 np->ops->unmap_single(np->device, tb->mapping,
2305 len, DMA_TO_DEVICE);
2306
2307 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
2308 rp->mark_pending--;
2309
2310 tb->skb = NULL;
2311 do {
2312 idx = NEXT_TX(rp, idx);
2313 len -= MAX_TX_DESC_LEN;
2314 } while (len > 0);
2315
2316 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2317 tb = &rp->tx_buffs[idx];
2318 BUG_ON(tb->skb != NULL);
2319 np->ops->unmap_page(np->device, tb->mapping,
2320 skb_shinfo(skb)->frags[i].size,
2321 DMA_TO_DEVICE);
2322 idx = NEXT_TX(rp, idx);
2323 }
2324
2325 dev_kfree_skb(skb);
2326
2327 return idx;
2328}
2329
2330#define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
2331
2332static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
2333{
2334 u16 pkt_cnt, tmp;
2335 int cons;
2336 u64 cs;
2337
2338 cs = rp->tx_cs;
2339 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
2340 goto out;
2341
2342 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
2343 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
2344 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
2345
2346 rp->last_pkt_cnt = tmp;
2347
2348 cons = rp->cons;
2349
2350 niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
2351 np->dev->name, pkt_cnt, cons);
2352
2353 while (pkt_cnt--)
2354 cons = release_tx_packet(np, rp, cons);
2355
2356 rp->cons = cons;
2357 smp_mb();
2358
2359out:
2360 if (unlikely(netif_queue_stopped(np->dev) &&
2361 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
2362 netif_tx_lock(np->dev);
2363 if (netif_queue_stopped(np->dev) &&
2364 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
2365 netif_wake_queue(np->dev);
2366 netif_tx_unlock(np->dev);
2367 }
2368}
2369
2370static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
2371{
2372 int qlen, rcr_done = 0, work_done = 0;
2373 struct rxdma_mailbox *mbox = rp->mbox;
2374 u64 stat;
2375
2376#if 1
2377 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
2378 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
2379#else
2380 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
2381 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
2382#endif
2383 mbox->rx_dma_ctl_stat = 0;
2384 mbox->rcrstat_a = 0;
2385
2386 niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
2387 np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
2388
2389 rcr_done = work_done = 0;
2390 qlen = min(qlen, budget);
2391 while (work_done < qlen) {
2392 rcr_done += niu_process_rx_pkt(np, rp);
2393 work_done++;
2394 }
2395
2396 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
2397 unsigned int i;
2398
2399 for (i = 0; i < rp->rbr_refill_pending; i++)
2400 niu_rbr_refill(np, rp, GFP_ATOMIC);
2401 rp->rbr_refill_pending = 0;
2402 }
2403
2404 stat = (RX_DMA_CTL_STAT_MEX |
2405 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
2406 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
2407
2408 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
2409
2410 return work_done;
2411}
2412
2413static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
2414{
2415 u64 v0 = lp->v0;
2416 u32 tx_vec = (v0 >> 32);
2417 u32 rx_vec = (v0 & 0xffffffff);
2418 int i, work_done = 0;
2419
2420 niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
2421 np->dev->name, (unsigned long long) v0);
2422
2423 for (i = 0; i < np->num_tx_rings; i++) {
2424 struct tx_ring_info *rp = &np->tx_rings[i];
2425 if (tx_vec & (1 << rp->tx_channel))
2426 niu_tx_work(np, rp);
2427 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
2428 }
2429
2430 for (i = 0; i < np->num_rx_rings; i++) {
2431 struct rx_ring_info *rp = &np->rx_rings[i];
2432
2433 if (rx_vec & (1 << rp->rx_channel)) {
2434 int this_work_done;
2435
2436 this_work_done = niu_rx_work(np, rp,
2437 budget);
2438
2439 budget -= this_work_done;
2440 work_done += this_work_done;
2441 }
2442 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
2443 }
2444
2445 return work_done;
2446}
2447
2448static int niu_poll(struct napi_struct *napi, int budget)
2449{
2450 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
2451 struct niu *np = lp->np;
2452 int work_done;
2453
2454 work_done = niu_poll_core(np, lp, budget);
2455
2456 if (work_done < budget) {
2457 netif_rx_complete(np->dev, napi);
2458 niu_ldg_rearm(np, lp, 1);
2459 }
2460 return work_done;
2461}
2462
2463static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
2464 u64 stat)
2465{
2466 dev_err(np->device, PFX "%s: RX channel %u errors ( ",
2467 np->dev->name, rp->rx_channel);
2468
2469 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
2470 printk("RBR_TMOUT ");
2471 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
2472 printk("RSP_CNT ");
2473 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
2474 printk("BYTE_EN_BUS ");
2475 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
2476 printk("RSP_DAT ");
2477 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
2478 printk("RCR_ACK ");
2479 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
2480 printk("RCR_SHA_PAR ");
2481 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
2482 printk("RBR_PRE_PAR ");
2483 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
2484 printk("CONFIG ");
2485 if (stat & RX_DMA_CTL_STAT_RCRINCON)
2486 printk("RCRINCON ");
2487 if (stat & RX_DMA_CTL_STAT_RCRFULL)
2488 printk("RCRFULL ");
2489 if (stat & RX_DMA_CTL_STAT_RBRFULL)
2490 printk("RBRFULL ");
2491 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
2492 printk("RBRLOGPAGE ");
2493 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
2494 printk("CFIGLOGPAGE ");
2495 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
2496 printk("DC_FIDO ");
2497
2498 printk(")\n");
2499}
2500
2501static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
2502{
2503 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
2504 int err = 0;
2505
2506 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
2507 np->dev->name, rp->rx_channel, (unsigned long long) stat);
2508
2509 niu_log_rxchan_errors(np, rp, stat);
2510
2511 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
2512 RX_DMA_CTL_STAT_PORT_FATAL))
2513 err = -EINVAL;
2514
2515 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
2516 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
2517
2518 return err;
2519}
2520
2521static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
2522 u64 cs)
2523{
2524 dev_err(np->device, PFX "%s: TX channel %u errors ( ",
2525 np->dev->name, rp->tx_channel);
2526
2527 if (cs & TX_CS_MBOX_ERR)
2528 printk("MBOX ");
2529 if (cs & TX_CS_PKT_SIZE_ERR)
2530 printk("PKT_SIZE ");
2531 if (cs & TX_CS_TX_RING_OFLOW)
2532 printk("TX_RING_OFLOW ");
2533 if (cs & TX_CS_PREF_BUF_PAR_ERR)
2534 printk("PREF_BUF_PAR ");
2535 if (cs & TX_CS_NACK_PREF)
2536 printk("NACK_PREF ");
2537 if (cs & TX_CS_NACK_PKT_RD)
2538 printk("NACK_PKT_RD ");
2539 if (cs & TX_CS_CONF_PART_ERR)
2540 printk("CONF_PART ");
2541 if (cs & TX_CS_PKT_PRT_ERR)
2542 printk("PKT_PTR ");
2543
2544 printk(")\n");
2545}
2546
2547static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
2548{
2549 u64 cs, logh, logl;
2550
2551 cs = nr64(TX_CS(rp->tx_channel));
2552 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
2553 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
2554
2555 dev_err(np->device, PFX "%s: TX channel %u error, "
2556 "cs[%llx] logh[%llx] logl[%llx]\n",
2557 np->dev->name, rp->tx_channel,
2558 (unsigned long long) cs,
2559 (unsigned long long) logh,
2560 (unsigned long long) logl);
2561
2562 niu_log_txchan_errors(np, rp, cs);
2563
2564 return -ENODEV;
2565}
2566
2567static int niu_mif_interrupt(struct niu *np)
2568{
2569 u64 mif_status = nr64(MIF_STATUS);
2570 int phy_mdint = 0;
2571
2572 if (np->flags & NIU_FLAGS_XMAC) {
2573 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
2574
2575 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
2576 phy_mdint = 1;
2577 }
2578
2579 dev_err(np->device, PFX "%s: MIF interrupt, "
2580 "stat[%llx] phy_mdint(%d)\n",
2581 np->dev->name, (unsigned long long) mif_status, phy_mdint);
2582
2583 return -ENODEV;
2584}
2585
2586static void niu_xmac_interrupt(struct niu *np)
2587{
2588 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
2589 u64 val;
2590
2591 val = nr64_mac(XTXMAC_STATUS);
2592 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
2593 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
2594 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
2595 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
2596 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
2597 mp->tx_fifo_errors++;
2598 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
2599 mp->tx_overflow_errors++;
2600 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
2601 mp->tx_max_pkt_size_errors++;
2602 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
2603 mp->tx_underflow_errors++;
2604
2605 val = nr64_mac(XRXMAC_STATUS);
2606 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
2607 mp->rx_local_faults++;
2608 if (val & XRXMAC_STATUS_RFLT_DET)
2609 mp->rx_remote_faults++;
2610 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
2611 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
2612 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
2613 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
2614 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
2615 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
2616 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
2617 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
2618 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
2619 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
2620 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
2621 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
2622 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
2623 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
2624 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
2625 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
2626 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
2627 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
2628 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
2629 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
2630 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
2631 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
2632 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
2633 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
2634 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
2635 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
2636 if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
2637 mp->rx_octets += RXMAC_BT_CNT_COUNT;
2638 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
2639 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
2640 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
2641 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
2642 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
2643 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
2644 if (val & XRXMAC_STATUS_RXUFLOW)
2645 mp->rx_underflows++;
2646 if (val & XRXMAC_STATUS_RXOFLOW)
2647 mp->rx_overflows++;
2648
2649 val = nr64_mac(XMAC_FC_STAT);
2650 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
2651 mp->pause_off_state++;
2652 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
2653 mp->pause_on_state++;
2654 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
2655 mp->pause_received++;
2656}
2657
2658static void niu_bmac_interrupt(struct niu *np)
2659{
2660 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
2661 u64 val;
2662
2663 val = nr64_mac(BTXMAC_STATUS);
2664 if (val & BTXMAC_STATUS_UNDERRUN)
2665 mp->tx_underflow_errors++;
2666 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
2667 mp->tx_max_pkt_size_errors++;
2668 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
2669 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
2670 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
2671 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
2672
2673 val = nr64_mac(BRXMAC_STATUS);
2674 if (val & BRXMAC_STATUS_OVERFLOW)
2675 mp->rx_overflows++;
2676 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
2677 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
2678 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
2679 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
2680 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
2681 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
2682 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
2683 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
2684
2685 val = nr64_mac(BMAC_CTRL_STATUS);
2686 if (val & BMAC_CTRL_STATUS_NOPAUSE)
2687 mp->pause_off_state++;
2688 if (val & BMAC_CTRL_STATUS_PAUSE)
2689 mp->pause_on_state++;
2690 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
2691 mp->pause_received++;
2692}
2693
2694static int niu_mac_interrupt(struct niu *np)
2695{
2696 if (np->flags & NIU_FLAGS_XMAC)
2697 niu_xmac_interrupt(np);
2698 else
2699 niu_bmac_interrupt(np);
2700
2701 return 0;
2702}
2703
2704static void niu_log_device_error(struct niu *np, u64 stat)
2705{
2706 dev_err(np->device, PFX "%s: Core device errors ( ",
2707 np->dev->name);
2708
2709 if (stat & SYS_ERR_MASK_META2)
2710 printk("META2 ");
2711 if (stat & SYS_ERR_MASK_META1)
2712 printk("META1 ");
2713 if (stat & SYS_ERR_MASK_PEU)
2714 printk("PEU ");
2715 if (stat & SYS_ERR_MASK_TXC)
2716 printk("TXC ");
2717 if (stat & SYS_ERR_MASK_RDMC)
2718 printk("RDMC ");
2719 if (stat & SYS_ERR_MASK_TDMC)
2720 printk("TDMC ");
2721 if (stat & SYS_ERR_MASK_ZCP)
2722 printk("ZCP ");
2723 if (stat & SYS_ERR_MASK_FFLP)
2724 printk("FFLP ");
2725 if (stat & SYS_ERR_MASK_IPP)
2726 printk("IPP ");
2727 if (stat & SYS_ERR_MASK_MAC)
2728 printk("MAC ");
2729 if (stat & SYS_ERR_MASK_SMX)
2730 printk("SMX ");
2731
2732 printk(")\n");
2733}
2734
2735static int niu_device_error(struct niu *np)
2736{
2737 u64 stat = nr64(SYS_ERR_STAT);
2738
2739 dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
2740 np->dev->name, (unsigned long long) stat);
2741
2742 niu_log_device_error(np, stat);
2743
2744 return -ENODEV;
2745}
2746
2747static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp)
2748{
2749 u64 v0 = lp->v0;
2750 u64 v1 = lp->v1;
2751 u64 v2 = lp->v2;
2752 int i, err = 0;
2753
2754 if (v1 & 0x00000000ffffffffULL) {
2755 u32 rx_vec = (v1 & 0xffffffff);
2756
2757 for (i = 0; i < np->num_rx_rings; i++) {
2758 struct rx_ring_info *rp = &np->rx_rings[i];
2759
2760 if (rx_vec & (1 << rp->rx_channel)) {
2761 int r = niu_rx_error(np, rp);
2762 if (r)
2763 err = r;
2764 }
2765 }
2766 }
2767 if (v1 & 0x7fffffff00000000ULL) {
2768 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
2769
2770 for (i = 0; i < np->num_tx_rings; i++) {
2771 struct tx_ring_info *rp = &np->tx_rings[i];
2772
2773 if (tx_vec & (1 << rp->tx_channel)) {
2774 int r = niu_tx_error(np, rp);
2775 if (r)
2776 err = r;
2777 }
2778 }
2779 }
2780 if ((v0 | v1) & 0x8000000000000000ULL) {
2781 int r = niu_mif_interrupt(np);
2782 if (r)
2783 err = r;
2784 }
2785 if (v2) {
2786 if (v2 & 0x01ef) {
2787 int r = niu_mac_interrupt(np);
2788 if (r)
2789 err = r;
2790 }
2791 if (v2 & 0x0210) {
2792 int r = niu_device_error(np);
2793 if (r)
2794 err = r;
2795 }
2796 }
2797
2798 if (err)
2799 niu_enable_interrupts(np, 0);
2800
2801 return -EINVAL;
2802}
2803
2804static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
2805 int ldn)
2806{
2807 struct rxdma_mailbox *mbox = rp->mbox;
2808 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
2809
2810 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
2811 RX_DMA_CTL_STAT_RCRTO);
2812 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
2813
2814 niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
2815 np->dev->name, (unsigned long long) stat);
2816}
2817
2818static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
2819 int ldn)
2820{
2821 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
2822
2823 niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
2824 np->dev->name, (unsigned long long) rp->tx_cs);
2825}
2826
2827static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
2828{
2829 struct niu_parent *parent = np->parent;
2830 u32 rx_vec, tx_vec;
2831 int i;
2832
2833 tx_vec = (v0 >> 32);
2834 rx_vec = (v0 & 0xffffffff);
2835
2836 for (i = 0; i < np->num_rx_rings; i++) {
2837 struct rx_ring_info *rp = &np->rx_rings[i];
2838 int ldn = LDN_RXDMA(rp->rx_channel);
2839
2840 if (parent->ldg_map[ldn] != ldg)
2841 continue;
2842
2843 nw64(LD_IM0(ldn), LD_IM0_MASK);
2844 if (rx_vec & (1 << rp->rx_channel))
2845 niu_rxchan_intr(np, rp, ldn);
2846 }
2847
2848 for (i = 0; i < np->num_tx_rings; i++) {
2849 struct tx_ring_info *rp = &np->tx_rings[i];
2850 int ldn = LDN_TXDMA(rp->tx_channel);
2851
2852 if (parent->ldg_map[ldn] != ldg)
2853 continue;
2854
2855 nw64(LD_IM0(ldn), LD_IM0_MASK);
2856 if (tx_vec & (1 << rp->tx_channel))
2857 niu_txchan_intr(np, rp, ldn);
2858 }
2859}
2860
2861static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
2862 u64 v0, u64 v1, u64 v2)
2863{
2864 if (likely(netif_rx_schedule_prep(np->dev, &lp->napi))) {
2865 lp->v0 = v0;
2866 lp->v1 = v1;
2867 lp->v2 = v2;
2868 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
2869 __netif_rx_schedule(np->dev, &lp->napi);
2870 }
2871}
2872
2873static irqreturn_t niu_interrupt(int irq, void *dev_id)
2874{
2875 struct niu_ldg *lp = dev_id;
2876 struct niu *np = lp->np;
2877 int ldg = lp->ldg_num;
2878 unsigned long flags;
2879 u64 v0, v1, v2;
2880
2881 if (netif_msg_intr(np))
2882 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
2883 lp, ldg);
2884
2885 spin_lock_irqsave(&np->lock, flags);
2886
2887 v0 = nr64(LDSV0(ldg));
2888 v1 = nr64(LDSV1(ldg));
2889 v2 = nr64(LDSV2(ldg));
2890
2891 if (netif_msg_intr(np))
2892 printk("v0[%llx] v1[%llx] v2[%llx]\n",
2893 (unsigned long long) v0,
2894 (unsigned long long) v1,
2895 (unsigned long long) v2);
2896
2897 if (unlikely(!v0 && !v1 && !v2)) {
2898 spin_unlock_irqrestore(&np->lock, flags);
2899 return IRQ_NONE;
2900 }
2901
2902 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
2903 int err = niu_slowpath_interrupt(np, lp);
2904 if (err)
2905 goto out;
2906 }
2907 if (likely(v0 & ~((u64)1 << LDN_MIF)))
2908 niu_schedule_napi(np, lp, v0, v1, v2);
2909 else
2910 niu_ldg_rearm(np, lp, 1);
2911out:
2912 spin_unlock_irqrestore(&np->lock, flags);
2913
2914 return IRQ_HANDLED;
2915}
2916
2917static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
2918{
2919 if (rp->mbox) {
2920 np->ops->free_coherent(np->device,
2921 sizeof(struct rxdma_mailbox),
2922 rp->mbox, rp->mbox_dma);
2923 rp->mbox = NULL;
2924 }
2925 if (rp->rcr) {
2926 np->ops->free_coherent(np->device,
2927 MAX_RCR_RING_SIZE * sizeof(__le64),
2928 rp->rcr, rp->rcr_dma);
2929 rp->rcr = NULL;
2930 rp->rcr_table_size = 0;
2931 rp->rcr_index = 0;
2932 }
2933 if (rp->rbr) {
2934 niu_rbr_free(np, rp);
2935
2936 np->ops->free_coherent(np->device,
2937 MAX_RBR_RING_SIZE * sizeof(__le32),
2938 rp->rbr, rp->rbr_dma);
2939 rp->rbr = NULL;
2940 rp->rbr_table_size = 0;
2941 rp->rbr_index = 0;
2942 }
2943 kfree(rp->rxhash);
2944 rp->rxhash = NULL;
2945}
2946
2947static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
2948{
2949 if (rp->mbox) {
2950 np->ops->free_coherent(np->device,
2951 sizeof(struct txdma_mailbox),
2952 rp->mbox, rp->mbox_dma);
2953 rp->mbox = NULL;
2954 }
2955 if (rp->descr) {
2956 int i;
2957
2958 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
2959 if (rp->tx_buffs[i].skb)
2960 (void) release_tx_packet(np, rp, i);
2961 }
2962
2963 np->ops->free_coherent(np->device,
2964 MAX_TX_RING_SIZE * sizeof(__le64),
2965 rp->descr, rp->descr_dma);
2966 rp->descr = NULL;
2967 rp->pending = 0;
2968 rp->prod = 0;
2969 rp->cons = 0;
2970 rp->wrap_bit = 0;
2971 }
2972}
2973
2974static void niu_free_channels(struct niu *np)
2975{
2976 int i;
2977
2978 if (np->rx_rings) {
2979 for (i = 0; i < np->num_rx_rings; i++) {
2980 struct rx_ring_info *rp = &np->rx_rings[i];
2981
2982 niu_free_rx_ring_info(np, rp);
2983 }
2984 kfree(np->rx_rings);
2985 np->rx_rings = NULL;
2986 np->num_rx_rings = 0;
2987 }
2988
2989 if (np->tx_rings) {
2990 for (i = 0; i < np->num_tx_rings; i++) {
2991 struct tx_ring_info *rp = &np->tx_rings[i];
2992
2993 niu_free_tx_ring_info(np, rp);
2994 }
2995 kfree(np->tx_rings);
2996 np->tx_rings = NULL;
2997 np->num_tx_rings = 0;
2998 }
2999}
3000
3001static int niu_alloc_rx_ring_info(struct niu *np,
3002 struct rx_ring_info *rp)
3003{
3004 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
3005
3006 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
3007 GFP_KERNEL);
3008 if (!rp->rxhash)
3009 return -ENOMEM;
3010
3011 rp->mbox = np->ops->alloc_coherent(np->device,
3012 sizeof(struct rxdma_mailbox),
3013 &rp->mbox_dma, GFP_KERNEL);
3014 if (!rp->mbox)
3015 return -ENOMEM;
3016 if ((unsigned long)rp->mbox & (64UL - 1)) {
3017 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3018 "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
3019 return -EINVAL;
3020 }
3021
3022 rp->rcr = np->ops->alloc_coherent(np->device,
3023 MAX_RCR_RING_SIZE * sizeof(__le64),
3024 &rp->rcr_dma, GFP_KERNEL);
3025 if (!rp->rcr)
3026 return -ENOMEM;
3027 if ((unsigned long)rp->rcr & (64UL - 1)) {
3028 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3029 "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
3030 return -EINVAL;
3031 }
3032 rp->rcr_table_size = MAX_RCR_RING_SIZE;
3033 rp->rcr_index = 0;
3034
3035 rp->rbr = np->ops->alloc_coherent(np->device,
3036 MAX_RBR_RING_SIZE * sizeof(__le32),
3037 &rp->rbr_dma, GFP_KERNEL);
3038 if (!rp->rbr)
3039 return -ENOMEM;
3040 if ((unsigned long)rp->rbr & (64UL - 1)) {
3041 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3042 "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
3043 return -EINVAL;
3044 }
3045 rp->rbr_table_size = MAX_RBR_RING_SIZE;
3046 rp->rbr_index = 0;
3047 rp->rbr_pending = 0;
3048
3049 return 0;
3050}
3051
3052static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
3053{
3054 int mtu = np->dev->mtu;
3055
3056 /* These values are recommended by the HW designers for fair
3057 * utilization of DRR amongst the rings.
3058 */
3059 rp->max_burst = mtu + 32;
3060 if (rp->max_burst > 4096)
3061 rp->max_burst = 4096;
3062}
3063
3064static int niu_alloc_tx_ring_info(struct niu *np,
3065 struct tx_ring_info *rp)
3066{
3067 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
3068
3069 rp->mbox = np->ops->alloc_coherent(np->device,
3070 sizeof(struct txdma_mailbox),
3071 &rp->mbox_dma, GFP_KERNEL);
3072 if (!rp->mbox)
3073 return -ENOMEM;
3074 if ((unsigned long)rp->mbox & (64UL - 1)) {
3075 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3076 "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
3077 return -EINVAL;
3078 }
3079
3080 rp->descr = np->ops->alloc_coherent(np->device,
3081 MAX_TX_RING_SIZE * sizeof(__le64),
3082 &rp->descr_dma, GFP_KERNEL);
3083 if (!rp->descr)
3084 return -ENOMEM;
3085 if ((unsigned long)rp->descr & (64UL - 1)) {
3086 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3087 "TXDMA descr table %p\n", np->dev->name, rp->descr);
3088 return -EINVAL;
3089 }
3090
3091 rp->pending = MAX_TX_RING_SIZE;
3092 rp->prod = 0;
3093 rp->cons = 0;
3094 rp->wrap_bit = 0;
3095
3096 /* XXX make these configurable... XXX */
3097 rp->mark_freq = rp->pending / 4;
3098
3099 niu_set_max_burst(np, rp);
3100
3101 return 0;
3102}
3103
3104static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
3105{
3106 u16 bs;
3107
3108 switch (PAGE_SIZE) {
3109 case 4 * 1024:
3110 case 8 * 1024:
3111 case 16 * 1024:
3112 case 32 * 1024:
3113 rp->rbr_block_size = PAGE_SIZE;
3114 rp->rbr_blocks_per_page = 1;
3115 break;
3116
3117 default:
3118 if (PAGE_SIZE % (32 * 1024) == 0)
3119 bs = 32 * 1024;
3120 else if (PAGE_SIZE % (16 * 1024) == 0)
3121 bs = 16 * 1024;
3122 else if (PAGE_SIZE % (8 * 1024) == 0)
3123 bs = 8 * 1024;
3124 else if (PAGE_SIZE % (4 * 1024) == 0)
3125 bs = 4 * 1024;
3126 else
3127 BUG();
3128 rp->rbr_block_size = bs;
3129 rp->rbr_blocks_per_page = PAGE_SIZE / bs;
3130 }
3131
3132 rp->rbr_sizes[0] = 256;
3133 rp->rbr_sizes[1] = 1024;
3134 if (np->dev->mtu > ETH_DATA_LEN) {
3135 switch (PAGE_SIZE) {
3136 case 4 * 1024:
3137 rp->rbr_sizes[2] = 4096;
3138 break;
3139
3140 default:
3141 rp->rbr_sizes[2] = 8192;
3142 break;
3143 }
3144 } else {
3145 rp->rbr_sizes[2] = 2048;
3146 }
3147 rp->rbr_sizes[3] = rp->rbr_block_size;
3148}
3149
3150static int niu_alloc_channels(struct niu *np)
3151{
3152 struct niu_parent *parent = np->parent;
3153 int first_rx_channel, first_tx_channel;
3154 int i, port, err;
3155
3156 port = np->port;
3157 first_rx_channel = first_tx_channel = 0;
3158 for (i = 0; i < port; i++) {
3159 first_rx_channel += parent->rxchan_per_port[i];
3160 first_tx_channel += parent->txchan_per_port[i];
3161 }
3162
3163 np->num_rx_rings = parent->rxchan_per_port[port];
3164 np->num_tx_rings = parent->txchan_per_port[port];
3165
3166 np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
3167 GFP_KERNEL);
3168 err = -ENOMEM;
3169 if (!np->rx_rings)
3170 goto out_err;
3171
3172 for (i = 0; i < np->num_rx_rings; i++) {
3173 struct rx_ring_info *rp = &np->rx_rings[i];
3174
3175 rp->np = np;
3176 rp->rx_channel = first_rx_channel + i;
3177
3178 err = niu_alloc_rx_ring_info(np, rp);
3179 if (err)
3180 goto out_err;
3181
3182 niu_size_rbr(np, rp);
3183
3184 /* XXX better defaults, configurable, etc... XXX */
3185 rp->nonsyn_window = 64;
3186 rp->nonsyn_threshold = rp->rcr_table_size - 64;
3187 rp->syn_window = 64;
3188 rp->syn_threshold = rp->rcr_table_size - 64;
3189 rp->rcr_pkt_threshold = 16;
3190 rp->rcr_timeout = 8;
3191 rp->rbr_kick_thresh = RBR_REFILL_MIN;
3192 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
3193 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
3194
3195 err = niu_rbr_fill(np, rp, GFP_KERNEL);
3196 if (err)
3197 return err;
3198 }
3199
3200 np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
3201 GFP_KERNEL);
3202 err = -ENOMEM;
3203 if (!np->tx_rings)
3204 goto out_err;
3205
3206 for (i = 0; i < np->num_tx_rings; i++) {
3207 struct tx_ring_info *rp = &np->tx_rings[i];
3208
3209 rp->np = np;
3210 rp->tx_channel = first_tx_channel + i;
3211
3212 err = niu_alloc_tx_ring_info(np, rp);
3213 if (err)
3214 goto out_err;
3215 }
3216
3217 return 0;
3218
3219out_err:
3220 niu_free_channels(np);
3221 return err;
3222}
3223
3224static int niu_tx_cs_sng_poll(struct niu *np, int channel)
3225{
3226 int limit = 1000;
3227
3228 while (--limit > 0) {
3229 u64 val = nr64(TX_CS(channel));
3230 if (val & TX_CS_SNG_STATE)
3231 return 0;
3232 }
3233 return -ENODEV;
3234}
3235
3236static int niu_tx_channel_stop(struct niu *np, int channel)
3237{
3238 u64 val = nr64(TX_CS(channel));
3239
3240 val |= TX_CS_STOP_N_GO;
3241 nw64(TX_CS(channel), val);
3242
3243 return niu_tx_cs_sng_poll(np, channel);
3244}
3245
3246static int niu_tx_cs_reset_poll(struct niu *np, int channel)
3247{
3248 int limit = 1000;
3249
3250 while (--limit > 0) {
3251 u64 val = nr64(TX_CS(channel));
3252 if (!(val & TX_CS_RST))
3253 return 0;
3254 }
3255 return -ENODEV;
3256}
3257
3258static int niu_tx_channel_reset(struct niu *np, int channel)
3259{
3260 u64 val = nr64(TX_CS(channel));
3261 int err;
3262
3263 val |= TX_CS_RST;
3264 nw64(TX_CS(channel), val);
3265
3266 err = niu_tx_cs_reset_poll(np, channel);
3267 if (!err)
3268 nw64(TX_RING_KICK(channel), 0);
3269
3270 return err;
3271}
3272
3273static int niu_tx_channel_lpage_init(struct niu *np, int channel)
3274{
3275 u64 val;
3276
3277 nw64(TX_LOG_MASK1(channel), 0);
3278 nw64(TX_LOG_VAL1(channel), 0);
3279 nw64(TX_LOG_MASK2(channel), 0);
3280 nw64(TX_LOG_VAL2(channel), 0);
3281 nw64(TX_LOG_PAGE_RELO1(channel), 0);
3282 nw64(TX_LOG_PAGE_RELO2(channel), 0);
3283 nw64(TX_LOG_PAGE_HDL(channel), 0);
3284
3285 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
3286 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
3287 nw64(TX_LOG_PAGE_VLD(channel), val);
3288
3289 /* XXX TXDMA 32bit mode? XXX */
3290
3291 return 0;
3292}
3293
3294static void niu_txc_enable_port(struct niu *np, int on)
3295{
3296 unsigned long flags;
3297 u64 val, mask;
3298
3299 niu_lock_parent(np, flags);
3300 val = nr64(TXC_CONTROL);
3301 mask = (u64)1 << np->port;
3302 if (on) {
3303 val |= TXC_CONTROL_ENABLE | mask;
3304 } else {
3305 val &= ~mask;
3306 if ((val & ~TXC_CONTROL_ENABLE) == 0)
3307 val &= ~TXC_CONTROL_ENABLE;
3308 }
3309 nw64(TXC_CONTROL, val);
3310 niu_unlock_parent(np, flags);
3311}
3312
3313static void niu_txc_set_imask(struct niu *np, u64 imask)
3314{
3315 unsigned long flags;
3316 u64 val;
3317
3318 niu_lock_parent(np, flags);
3319 val = nr64(TXC_INT_MASK);
3320 val &= ~TXC_INT_MASK_VAL(np->port);
3321 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
3322 niu_unlock_parent(np, flags);
3323}
3324
3325static void niu_txc_port_dma_enable(struct niu *np, int on)
3326{
3327 u64 val = 0;
3328
3329 if (on) {
3330 int i;
3331
3332 for (i = 0; i < np->num_tx_rings; i++)
3333 val |= (1 << np->tx_rings[i].tx_channel);
3334 }
3335 nw64(TXC_PORT_DMA(np->port), val);
3336}
3337
3338static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
3339{
3340 int err, channel = rp->tx_channel;
3341 u64 val, ring_len;
3342
3343 err = niu_tx_channel_stop(np, channel);
3344 if (err)
3345 return err;
3346
3347 err = niu_tx_channel_reset(np, channel);
3348 if (err)
3349 return err;
3350
3351 err = niu_tx_channel_lpage_init(np, channel);
3352 if (err)
3353 return err;
3354
3355 nw64(TXC_DMA_MAX(channel), rp->max_burst);
3356 nw64(TX_ENT_MSK(channel), 0);
3357
3358 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
3359 TX_RNG_CFIG_STADDR)) {
3360 dev_err(np->device, PFX "%s: TX ring channel %d "
3361 "DMA addr (%llx) is not aligned.\n",
3362 np->dev->name, channel,
3363 (unsigned long long) rp->descr_dma);
3364 return -EINVAL;
3365 }
3366
3367 /* The length field in TX_RNG_CFIG is measured in 64-byte
3368 * blocks. rp->pending is the number of TX descriptors in
3369 * our ring, 8 bytes each, thus we divide by 8 bytes more
3370 * to get the proper value the chip wants.
3371 */
3372 ring_len = (rp->pending / 8);
3373
3374 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
3375 rp->descr_dma);
3376 nw64(TX_RNG_CFIG(channel), val);
3377
3378 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
3379 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
3380 dev_err(np->device, PFX "%s: TX ring channel %d "
3381 "MBOX addr (%llx) is has illegal bits.\n",
3382 np->dev->name, channel,
3383 (unsigned long long) rp->mbox_dma);
3384 return -EINVAL;
3385 }
3386 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
3387 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
3388
3389 nw64(TX_CS(channel), 0);
3390
3391 rp->last_pkt_cnt = 0;
3392
3393 return 0;
3394}
3395
3396static void niu_init_rdc_groups(struct niu *np)
3397{
3398 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
3399 int i, first_table_num = tp->first_table_num;
3400
3401 for (i = 0; i < tp->num_tables; i++) {
3402 struct rdc_table *tbl = &tp->tables[i];
3403 int this_table = first_table_num + i;
3404 int slot;
3405
3406 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
3407 nw64(RDC_TBL(this_table, slot),
3408 tbl->rxdma_channel[slot]);
3409 }
3410
3411 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
3412}
3413
3414static void niu_init_drr_weight(struct niu *np)
3415{
3416 int type = phy_decode(np->parent->port_phy, np->port);
3417 u64 val;
3418
3419 switch (type) {
3420 case PORT_TYPE_10G:
3421 val = PT_DRR_WEIGHT_DEFAULT_10G;
3422 break;
3423
3424 case PORT_TYPE_1G:
3425 default:
3426 val = PT_DRR_WEIGHT_DEFAULT_1G;
3427 break;
3428 }
3429 nw64(PT_DRR_WT(np->port), val);
3430}
3431
3432static int niu_init_hostinfo(struct niu *np)
3433{
3434 struct niu_parent *parent = np->parent;
3435 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
3436 int i, err, num_alt = niu_num_alt_addr(np);
3437 int first_rdc_table = tp->first_table_num;
3438
3439 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
3440 if (err)
3441 return err;
3442
3443 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
3444 if (err)
3445 return err;
3446
3447 for (i = 0; i < num_alt; i++) {
3448 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
3449 if (err)
3450 return err;
3451 }
3452
3453 return 0;
3454}
3455
3456static int niu_rx_channel_reset(struct niu *np, int channel)
3457{
3458 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
3459 RXDMA_CFIG1_RST, 1000, 10,
3460 "RXDMA_CFIG1");
3461}
3462
3463static int niu_rx_channel_lpage_init(struct niu *np, int channel)
3464{
3465 u64 val;
3466
3467 nw64(RX_LOG_MASK1(channel), 0);
3468 nw64(RX_LOG_VAL1(channel), 0);
3469 nw64(RX_LOG_MASK2(channel), 0);
3470 nw64(RX_LOG_VAL2(channel), 0);
3471 nw64(RX_LOG_PAGE_RELO1(channel), 0);
3472 nw64(RX_LOG_PAGE_RELO2(channel), 0);
3473 nw64(RX_LOG_PAGE_HDL(channel), 0);
3474
3475 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
3476 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
3477 nw64(RX_LOG_PAGE_VLD(channel), val);
3478
3479 return 0;
3480}
3481
3482static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
3483{
3484 u64 val;
3485
3486 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
3487 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
3488 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
3489 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
3490 nw64(RDC_RED_PARA(rp->rx_channel), val);
3491}
3492
3493static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
3494{
3495 u64 val = 0;
3496
3497 switch (rp->rbr_block_size) {
3498 case 4 * 1024:
3499 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
3500 break;
3501 case 8 * 1024:
3502 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
3503 break;
3504 case 16 * 1024:
3505 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
3506 break;
3507 case 32 * 1024:
3508 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
3509 break;
3510 default:
3511 return -EINVAL;
3512 }
3513 val |= RBR_CFIG_B_VLD2;
3514 switch (rp->rbr_sizes[2]) {
3515 case 2 * 1024:
3516 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
3517 break;
3518 case 4 * 1024:
3519 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
3520 break;
3521 case 8 * 1024:
3522 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
3523 break;
3524 case 16 * 1024:
3525 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
3526 break;
3527
3528 default:
3529 return -EINVAL;
3530 }
3531 val |= RBR_CFIG_B_VLD1;
3532 switch (rp->rbr_sizes[1]) {
3533 case 1 * 1024:
3534 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
3535 break;
3536 case 2 * 1024:
3537 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
3538 break;
3539 case 4 * 1024:
3540 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
3541 break;
3542 case 8 * 1024:
3543 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
3544 break;
3545
3546 default:
3547 return -EINVAL;
3548 }
3549 val |= RBR_CFIG_B_VLD0;
3550 switch (rp->rbr_sizes[0]) {
3551 case 256:
3552 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
3553 break;
3554 case 512:
3555 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
3556 break;
3557 case 1 * 1024:
3558 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
3559 break;
3560 case 2 * 1024:
3561 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
3562 break;
3563
3564 default:
3565 return -EINVAL;
3566 }
3567
3568 *ret = val;
3569 return 0;
3570}
3571
3572static int niu_enable_rx_channel(struct niu *np, int channel, int on)
3573{
3574 u64 val = nr64(RXDMA_CFIG1(channel));
3575 int limit;
3576
3577 if (on)
3578 val |= RXDMA_CFIG1_EN;
3579 else
3580 val &= ~RXDMA_CFIG1_EN;
3581 nw64(RXDMA_CFIG1(channel), val);
3582
3583 limit = 1000;
3584 while (--limit > 0) {
3585 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
3586 break;
3587 udelay(10);
3588 }
3589 if (limit <= 0)
3590 return -ENODEV;
3591 return 0;
3592}
3593
3594static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
3595{
3596 int err, channel = rp->rx_channel;
3597 u64 val;
3598
3599 err = niu_rx_channel_reset(np, channel);
3600 if (err)
3601 return err;
3602
3603 err = niu_rx_channel_lpage_init(np, channel);
3604 if (err)
3605 return err;
3606
3607 niu_rx_channel_wred_init(np, rp);
3608
3609 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
3610 nw64(RX_DMA_CTL_STAT(channel),
3611 (RX_DMA_CTL_STAT_MEX |
3612 RX_DMA_CTL_STAT_RCRTHRES |
3613 RX_DMA_CTL_STAT_RCRTO |
3614 RX_DMA_CTL_STAT_RBR_EMPTY));
3615 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
3616 nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
3617 nw64(RBR_CFIG_A(channel),
3618 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
3619 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
3620 err = niu_compute_rbr_cfig_b(rp, &val);
3621 if (err)
3622 return err;
3623 nw64(RBR_CFIG_B(channel), val);
3624 nw64(RCRCFIG_A(channel),
3625 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
3626 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
3627 nw64(RCRCFIG_B(channel),
3628 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
3629 RCRCFIG_B_ENTOUT |
3630 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
3631
3632 err = niu_enable_rx_channel(np, channel, 1);
3633 if (err)
3634 return err;
3635
3636 nw64(RBR_KICK(channel), rp->rbr_index);
3637
3638 val = nr64(RX_DMA_CTL_STAT(channel));
3639 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
3640 nw64(RX_DMA_CTL_STAT(channel), val);
3641
3642 return 0;
3643}
3644
3645static int niu_init_rx_channels(struct niu *np)
3646{
3647 unsigned long flags;
3648 u64 seed = jiffies_64;
3649 int err, i;
3650
3651 niu_lock_parent(np, flags);
3652 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
3653 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
3654 niu_unlock_parent(np, flags);
3655
3656 /* XXX RXDMA 32bit mode? XXX */
3657
3658 niu_init_rdc_groups(np);
3659 niu_init_drr_weight(np);
3660
3661 err = niu_init_hostinfo(np);
3662 if (err)
3663 return err;
3664
3665 for (i = 0; i < np->num_rx_rings; i++) {
3666 struct rx_ring_info *rp = &np->rx_rings[i];
3667
3668 err = niu_init_one_rx_channel(np, rp);
3669 if (err)
3670 return err;
3671 }
3672
3673 return 0;
3674}
3675
3676static int niu_set_ip_frag_rule(struct niu *np)
3677{
3678 struct niu_parent *parent = np->parent;
3679 struct niu_classifier *cp = &np->clas;
3680 struct niu_tcam_entry *tp;
3681 int index, err;
3682
3683 /* XXX fix this allocation scheme XXX */
3684 index = cp->tcam_index;
3685 tp = &parent->tcam[index];
3686
3687 /* Note that the noport bit is the same in both ipv4 and
3688 * ipv6 format TCAM entries.
3689 */
3690 memset(tp, 0, sizeof(*tp));
3691 tp->key[1] = TCAM_V4KEY1_NOPORT;
3692 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
3693 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
3694 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
3695 err = tcam_write(np, index, tp->key, tp->key_mask);
3696 if (err)
3697 return err;
3698 err = tcam_assoc_write(np, index, tp->assoc_data);
3699 if (err)
3700 return err;
3701
3702 return 0;
3703}
3704
3705static int niu_init_classifier_hw(struct niu *np)
3706{
3707 struct niu_parent *parent = np->parent;
3708 struct niu_classifier *cp = &np->clas;
3709 int i, err;
3710
3711 nw64(H1POLY, cp->h1_init);
3712 nw64(H2POLY, cp->h2_init);
3713
3714 err = niu_init_hostinfo(np);
3715 if (err)
3716 return err;
3717
3718 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
3719 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
3720
3721 vlan_tbl_write(np, i, np->port,
3722 vp->vlan_pref, vp->rdc_num);
3723 }
3724
3725 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
3726 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
3727
3728 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
3729 ap->rdc_num, ap->mac_pref);
3730 if (err)
3731 return err;
3732 }
3733
3734 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
3735 int index = i - CLASS_CODE_USER_PROG1;
3736
3737 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
3738 if (err)
3739 return err;
3740 err = niu_set_flow_key(np, i, parent->flow_key[index]);
3741 if (err)
3742 return err;
3743 }
3744
3745 err = niu_set_ip_frag_rule(np);
3746 if (err)
3747 return err;
3748
3749 tcam_enable(np, 1);
3750
3751 return 0;
3752}
3753
3754static int niu_zcp_write(struct niu *np, int index, u64 *data)
3755{
3756 nw64(ZCP_RAM_DATA0, data[0]);
3757 nw64(ZCP_RAM_DATA1, data[1]);
3758 nw64(ZCP_RAM_DATA2, data[2]);
3759 nw64(ZCP_RAM_DATA3, data[3]);
3760 nw64(ZCP_RAM_DATA4, data[4]);
3761 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
3762 nw64(ZCP_RAM_ACC,
3763 (ZCP_RAM_ACC_WRITE |
3764 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
3765 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
3766
3767 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
3768 1000, 100);
3769}
3770
3771static int niu_zcp_read(struct niu *np, int index, u64 *data)
3772{
3773 int err;
3774
3775 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
3776 1000, 100);
3777 if (err) {
3778 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
3779 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
3780 (unsigned long long) nr64(ZCP_RAM_ACC));
3781 return err;
3782 }
3783
3784 nw64(ZCP_RAM_ACC,
3785 (ZCP_RAM_ACC_READ |
3786 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
3787 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
3788
3789 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
3790 1000, 100);
3791 if (err) {
3792 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
3793 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
3794 (unsigned long long) nr64(ZCP_RAM_ACC));
3795 return err;
3796 }
3797
3798 data[0] = nr64(ZCP_RAM_DATA0);
3799 data[1] = nr64(ZCP_RAM_DATA1);
3800 data[2] = nr64(ZCP_RAM_DATA2);
3801 data[3] = nr64(ZCP_RAM_DATA3);
3802 data[4] = nr64(ZCP_RAM_DATA4);
3803
3804 return 0;
3805}
3806
3807static void niu_zcp_cfifo_reset(struct niu *np)
3808{
3809 u64 val = nr64(RESET_CFIFO);
3810
3811 val |= RESET_CFIFO_RST(np->port);
3812 nw64(RESET_CFIFO, val);
3813 udelay(10);
3814
3815 val &= ~RESET_CFIFO_RST(np->port);
3816 nw64(RESET_CFIFO, val);
3817}
3818
3819static int niu_init_zcp(struct niu *np)
3820{
3821 u64 data[5], rbuf[5];
3822 int i, max, err;
3823
3824 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3825 if (np->port == 0 || np->port == 1)
3826 max = ATLAS_P0_P1_CFIFO_ENTRIES;
3827 else
3828 max = ATLAS_P2_P3_CFIFO_ENTRIES;
3829 } else
3830 max = NIU_CFIFO_ENTRIES;
3831
3832 data[0] = 0;
3833 data[1] = 0;
3834 data[2] = 0;
3835 data[3] = 0;
3836 data[4] = 0;
3837
3838 for (i = 0; i < max; i++) {
3839 err = niu_zcp_write(np, i, data);
3840 if (err)
3841 return err;
3842 err = niu_zcp_read(np, i, rbuf);
3843 if (err)
3844 return err;
3845 }
3846
3847 niu_zcp_cfifo_reset(np);
3848 nw64(CFIFO_ECC(np->port), 0);
3849 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
3850 (void) nr64(ZCP_INT_STAT);
3851 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
3852
3853 return 0;
3854}
3855
3856static void niu_ipp_write(struct niu *np, int index, u64 *data)
3857{
3858 u64 val = nr64_ipp(IPP_CFIG);
3859
3860 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
3861 nw64_ipp(IPP_DFIFO_WR_PTR, index);
3862 nw64_ipp(IPP_DFIFO_WR0, data[0]);
3863 nw64_ipp(IPP_DFIFO_WR1, data[1]);
3864 nw64_ipp(IPP_DFIFO_WR2, data[2]);
3865 nw64_ipp(IPP_DFIFO_WR3, data[3]);
3866 nw64_ipp(IPP_DFIFO_WR4, data[4]);
3867 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
3868}
3869
3870static void niu_ipp_read(struct niu *np, int index, u64 *data)
3871{
3872 nw64_ipp(IPP_DFIFO_RD_PTR, index);
3873 data[0] = nr64_ipp(IPP_DFIFO_RD0);
3874 data[1] = nr64_ipp(IPP_DFIFO_RD1);
3875 data[2] = nr64_ipp(IPP_DFIFO_RD2);
3876 data[3] = nr64_ipp(IPP_DFIFO_RD3);
3877 data[4] = nr64_ipp(IPP_DFIFO_RD4);
3878}
3879
3880static int niu_ipp_reset(struct niu *np)
3881{
3882 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
3883 1000, 100, "IPP_CFIG");
3884}
3885
3886static int niu_init_ipp(struct niu *np)
3887{
3888 u64 data[5], rbuf[5], val;
3889 int i, max, err;
3890
3891 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3892 if (np->port == 0 || np->port == 1)
3893 max = ATLAS_P0_P1_DFIFO_ENTRIES;
3894 else
3895 max = ATLAS_P2_P3_DFIFO_ENTRIES;
3896 } else
3897 max = NIU_DFIFO_ENTRIES;
3898
3899 data[0] = 0;
3900 data[1] = 0;
3901 data[2] = 0;
3902 data[3] = 0;
3903 data[4] = 0;
3904
3905 for (i = 0; i < max; i++) {
3906 niu_ipp_write(np, i, data);
3907 niu_ipp_read(np, i, rbuf);
3908 }
3909
3910 (void) nr64_ipp(IPP_INT_STAT);
3911 (void) nr64_ipp(IPP_INT_STAT);
3912
3913 err = niu_ipp_reset(np);
3914 if (err)
3915 return err;
3916
3917 (void) nr64_ipp(IPP_PKT_DIS);
3918 (void) nr64_ipp(IPP_BAD_CS_CNT);
3919 (void) nr64_ipp(IPP_ECC);
3920
3921 (void) nr64_ipp(IPP_INT_STAT);
3922
3923 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
3924
3925 val = nr64_ipp(IPP_CFIG);
3926 val &= ~IPP_CFIG_IP_MAX_PKT;
3927 val |= (IPP_CFIG_IPP_ENABLE |
3928 IPP_CFIG_DFIFO_ECC_EN |
3929 IPP_CFIG_DROP_BAD_CRC |
3930 IPP_CFIG_CKSUM_EN |
3931 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
3932 nw64_ipp(IPP_CFIG, val);
3933
3934 return 0;
3935}
3936
3937static void niu_init_xif_xmac(struct niu *np)
3938{
3939 struct niu_link_config *lp = &np->link_config;
3940 u64 val;
3941
3942 val = nr64_mac(XMAC_CONFIG);
3943
3944 if ((np->flags & NIU_FLAGS_10G) != 0 &&
3945 (np->flags & NIU_FLAGS_FIBER) != 0) {
3946 if (netif_carrier_ok(np->dev)) {
3947 val |= XMAC_CONFIG_LED_POLARITY;
3948 val &= ~XMAC_CONFIG_FORCE_LED_ON;
3949 } else {
3950 val |= XMAC_CONFIG_FORCE_LED_ON;
3951 val &= ~XMAC_CONFIG_LED_POLARITY;
3952 }
3953 }
3954
3955 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
3956
3957 val |= XMAC_CONFIG_TX_OUTPUT_EN;
3958
3959 if (lp->loopback_mode == LOOPBACK_MAC) {
3960 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
3961 val |= XMAC_CONFIG_LOOPBACK;
3962 } else {
3963 val &= ~XMAC_CONFIG_LOOPBACK;
3964 }
3965
3966 if (np->flags & NIU_FLAGS_10G) {
3967 val &= ~XMAC_CONFIG_LFS_DISABLE;
3968 } else {
3969 val |= XMAC_CONFIG_LFS_DISABLE;
3970 if (!(np->flags & NIU_FLAGS_FIBER))
3971 val |= XMAC_CONFIG_1G_PCS_BYPASS;
3972 else
3973 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
3974 }
3975
3976 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
3977
3978 if (lp->active_speed == SPEED_100)
3979 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
3980 else
3981 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
3982
3983 nw64_mac(XMAC_CONFIG, val);
3984
3985 val = nr64_mac(XMAC_CONFIG);
3986 val &= ~XMAC_CONFIG_MODE_MASK;
3987 if (np->flags & NIU_FLAGS_10G) {
3988 val |= XMAC_CONFIG_MODE_XGMII;
3989 } else {
3990 if (lp->active_speed == SPEED_100)
3991 val |= XMAC_CONFIG_MODE_MII;
3992 else
3993 val |= XMAC_CONFIG_MODE_GMII;
3994 }
3995
3996 nw64_mac(XMAC_CONFIG, val);
3997}
3998
3999static void niu_init_xif_bmac(struct niu *np)
4000{
4001 struct niu_link_config *lp = &np->link_config;
4002 u64 val;
4003
4004 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
4005
4006 if (lp->loopback_mode == LOOPBACK_MAC)
4007 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
4008 else
4009 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
4010
4011 if (lp->active_speed == SPEED_1000)
4012 val |= BMAC_XIF_CONFIG_GMII_MODE;
4013 else
4014 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
4015
4016 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
4017 BMAC_XIF_CONFIG_LED_POLARITY);
4018
4019 if (!(np->flags & NIU_FLAGS_10G) &&
4020 !(np->flags & NIU_FLAGS_FIBER) &&
4021 lp->active_speed == SPEED_100)
4022 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
4023 else
4024 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
4025
4026 nw64_mac(BMAC_XIF_CONFIG, val);
4027}
4028
4029static void niu_init_xif(struct niu *np)
4030{
4031 if (np->flags & NIU_FLAGS_XMAC)
4032 niu_init_xif_xmac(np);
4033 else
4034 niu_init_xif_bmac(np);
4035}
4036
4037static void niu_pcs_mii_reset(struct niu *np)
4038{
4039 u64 val = nr64_pcs(PCS_MII_CTL);
4040 val |= PCS_MII_CTL_RST;
4041 nw64_pcs(PCS_MII_CTL, val);
4042}
4043
4044static void niu_xpcs_reset(struct niu *np)
4045{
4046 u64 val = nr64_xpcs(XPCS_CONTROL1);
4047 val |= XPCS_CONTROL1_RESET;
4048 nw64_xpcs(XPCS_CONTROL1, val);
4049}
4050
4051static int niu_init_pcs(struct niu *np)
4052{
4053 struct niu_link_config *lp = &np->link_config;
4054 u64 val;
4055
4056 switch (np->flags & (NIU_FLAGS_10G | NIU_FLAGS_FIBER)) {
4057 case NIU_FLAGS_FIBER:
4058 /* 1G fiber */
4059 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
4060 nw64_pcs(PCS_DPATH_MODE, 0);
4061 niu_pcs_mii_reset(np);
4062 break;
4063
4064 case NIU_FLAGS_10G:
4065 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
4066 if (!(np->flags & NIU_FLAGS_XMAC))
4067 return -EINVAL;
4068
4069 /* 10G copper or fiber */
4070 val = nr64_mac(XMAC_CONFIG);
4071 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
4072 nw64_mac(XMAC_CONFIG, val);
4073
4074 niu_xpcs_reset(np);
4075
4076 val = nr64_xpcs(XPCS_CONTROL1);
4077 if (lp->loopback_mode == LOOPBACK_PHY)
4078 val |= XPCS_CONTROL1_LOOPBACK;
4079 else
4080 val &= ~XPCS_CONTROL1_LOOPBACK;
4081 nw64_xpcs(XPCS_CONTROL1, val);
4082
4083 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
4084 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
4085 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
4086 break;
4087
4088 case 0:
4089 /* 1G copper */
4090 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
4091 niu_pcs_mii_reset(np);
4092 break;
4093
4094 default:
4095 return -EINVAL;
4096 }
4097
4098 return 0;
4099}
4100
4101static int niu_reset_tx_xmac(struct niu *np)
4102{
4103 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
4104 (XTXMAC_SW_RST_REG_RS |
4105 XTXMAC_SW_RST_SOFT_RST),
4106 1000, 100, "XTXMAC_SW_RST");
4107}
4108
4109static int niu_reset_tx_bmac(struct niu *np)
4110{
4111 int limit;
4112
4113 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
4114 limit = 1000;
4115 while (--limit >= 0) {
4116 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
4117 break;
4118 udelay(100);
4119 }
4120 if (limit < 0) {
4121 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
4122 "BTXMAC_SW_RST[%llx]\n",
4123 np->port,
4124 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
4125 return -ENODEV;
4126 }
4127
4128 return 0;
4129}
4130
4131static int niu_reset_tx_mac(struct niu *np)
4132{
4133 if (np->flags & NIU_FLAGS_XMAC)
4134 return niu_reset_tx_xmac(np);
4135 else
4136 return niu_reset_tx_bmac(np);
4137}
4138
4139static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
4140{
4141 u64 val;
4142
4143 val = nr64_mac(XMAC_MIN);
4144 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
4145 XMAC_MIN_RX_MIN_PKT_SIZE);
4146 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
4147 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
4148 nw64_mac(XMAC_MIN, val);
4149
4150 nw64_mac(XMAC_MAX, max);
4151
4152 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
4153
4154 val = nr64_mac(XMAC_IPG);
4155 if (np->flags & NIU_FLAGS_10G) {
4156 val &= ~XMAC_IPG_IPG_XGMII;
4157 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
4158 } else {
4159 val &= ~XMAC_IPG_IPG_MII_GMII;
4160 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
4161 }
4162 nw64_mac(XMAC_IPG, val);
4163
4164 val = nr64_mac(XMAC_CONFIG);
4165 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
4166 XMAC_CONFIG_STRETCH_MODE |
4167 XMAC_CONFIG_VAR_MIN_IPG_EN |
4168 XMAC_CONFIG_TX_ENABLE);
4169 nw64_mac(XMAC_CONFIG, val);
4170
4171 nw64_mac(TXMAC_FRM_CNT, 0);
4172 nw64_mac(TXMAC_BYTE_CNT, 0);
4173}
4174
4175static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
4176{
4177 u64 val;
4178
4179 nw64_mac(BMAC_MIN_FRAME, min);
4180 nw64_mac(BMAC_MAX_FRAME, max);
4181
4182 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
4183 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
4184 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
4185
4186 val = nr64_mac(BTXMAC_CONFIG);
4187 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
4188 BTXMAC_CONFIG_ENABLE);
4189 nw64_mac(BTXMAC_CONFIG, val);
4190}
4191
4192static void niu_init_tx_mac(struct niu *np)
4193{
4194 u64 min, max;
4195
4196 min = 64;
4197 if (np->dev->mtu > ETH_DATA_LEN)
4198 max = 9216;
4199 else
4200 max = 1522;
4201
4202 /* The XMAC_MIN register only accepts values for TX min which
4203 * have the low 3 bits cleared.
4204 */
4205 BUILD_BUG_ON(min & 0x7);
4206
4207 if (np->flags & NIU_FLAGS_XMAC)
4208 niu_init_tx_xmac(np, min, max);
4209 else
4210 niu_init_tx_bmac(np, min, max);
4211}
4212
4213static int niu_reset_rx_xmac(struct niu *np)
4214{
4215 int limit;
4216
4217 nw64_mac(XRXMAC_SW_RST,
4218 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
4219 limit = 1000;
4220 while (--limit >= 0) {
4221 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
4222 XRXMAC_SW_RST_SOFT_RST)))
4223 break;
4224 udelay(100);
4225 }
4226 if (limit < 0) {
4227 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
4228 "XRXMAC_SW_RST[%llx]\n",
4229 np->port,
4230 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
4231 return -ENODEV;
4232 }
4233
4234 return 0;
4235}
4236
4237static int niu_reset_rx_bmac(struct niu *np)
4238{
4239 int limit;
4240
4241 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
4242 limit = 1000;
4243 while (--limit >= 0) {
4244 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
4245 break;
4246 udelay(100);
4247 }
4248 if (limit < 0) {
4249 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
4250 "BRXMAC_SW_RST[%llx]\n",
4251 np->port,
4252 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
4253 return -ENODEV;
4254 }
4255
4256 return 0;
4257}
4258
4259static int niu_reset_rx_mac(struct niu *np)
4260{
4261 if (np->flags & NIU_FLAGS_XMAC)
4262 return niu_reset_rx_xmac(np);
4263 else
4264 return niu_reset_rx_bmac(np);
4265}
4266
4267static void niu_init_rx_xmac(struct niu *np)
4268{
4269 struct niu_parent *parent = np->parent;
4270 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4271 int first_rdc_table = tp->first_table_num;
4272 unsigned long i;
4273 u64 val;
4274
4275 nw64_mac(XMAC_ADD_FILT0, 0);
4276 nw64_mac(XMAC_ADD_FILT1, 0);
4277 nw64_mac(XMAC_ADD_FILT2, 0);
4278 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
4279 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
4280 for (i = 0; i < MAC_NUM_HASH; i++)
4281 nw64_mac(XMAC_HASH_TBL(i), 0);
4282 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
4283 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4284 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4285
4286 val = nr64_mac(XMAC_CONFIG);
4287 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
4288 XMAC_CONFIG_PROMISCUOUS |
4289 XMAC_CONFIG_PROMISC_GROUP |
4290 XMAC_CONFIG_ERR_CHK_DIS |
4291 XMAC_CONFIG_RX_CRC_CHK_DIS |
4292 XMAC_CONFIG_RESERVED_MULTICAST |
4293 XMAC_CONFIG_RX_CODEV_CHK_DIS |
4294 XMAC_CONFIG_ADDR_FILTER_EN |
4295 XMAC_CONFIG_RCV_PAUSE_ENABLE |
4296 XMAC_CONFIG_STRIP_CRC |
4297 XMAC_CONFIG_PASS_FLOW_CTRL |
4298 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
4299 val |= (XMAC_CONFIG_HASH_FILTER_EN);
4300 nw64_mac(XMAC_CONFIG, val);
4301
4302 nw64_mac(RXMAC_BT_CNT, 0);
4303 nw64_mac(RXMAC_BC_FRM_CNT, 0);
4304 nw64_mac(RXMAC_MC_FRM_CNT, 0);
4305 nw64_mac(RXMAC_FRAG_CNT, 0);
4306 nw64_mac(RXMAC_HIST_CNT1, 0);
4307 nw64_mac(RXMAC_HIST_CNT2, 0);
4308 nw64_mac(RXMAC_HIST_CNT3, 0);
4309 nw64_mac(RXMAC_HIST_CNT4, 0);
4310 nw64_mac(RXMAC_HIST_CNT5, 0);
4311 nw64_mac(RXMAC_HIST_CNT6, 0);
4312 nw64_mac(RXMAC_HIST_CNT7, 0);
4313 nw64_mac(RXMAC_MPSZER_CNT, 0);
4314 nw64_mac(RXMAC_CRC_ER_CNT, 0);
4315 nw64_mac(RXMAC_CD_VIO_CNT, 0);
4316 nw64_mac(LINK_FAULT_CNT, 0);
4317}
4318
4319static void niu_init_rx_bmac(struct niu *np)
4320{
4321 struct niu_parent *parent = np->parent;
4322 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4323 int first_rdc_table = tp->first_table_num;
4324 unsigned long i;
4325 u64 val;
4326
4327 nw64_mac(BMAC_ADD_FILT0, 0);
4328 nw64_mac(BMAC_ADD_FILT1, 0);
4329 nw64_mac(BMAC_ADD_FILT2, 0);
4330 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
4331 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
4332 for (i = 0; i < MAC_NUM_HASH; i++)
4333 nw64_mac(BMAC_HASH_TBL(i), 0);
4334 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4335 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4336 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
4337
4338 val = nr64_mac(BRXMAC_CONFIG);
4339 val &= ~(BRXMAC_CONFIG_ENABLE |
4340 BRXMAC_CONFIG_STRIP_PAD |
4341 BRXMAC_CONFIG_STRIP_FCS |
4342 BRXMAC_CONFIG_PROMISC |
4343 BRXMAC_CONFIG_PROMISC_GRP |
4344 BRXMAC_CONFIG_ADDR_FILT_EN |
4345 BRXMAC_CONFIG_DISCARD_DIS);
4346 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
4347 nw64_mac(BRXMAC_CONFIG, val);
4348
4349 val = nr64_mac(BMAC_ADDR_CMPEN);
4350 val |= BMAC_ADDR_CMPEN_EN0;
4351 nw64_mac(BMAC_ADDR_CMPEN, val);
4352}
4353
4354static void niu_init_rx_mac(struct niu *np)
4355{
4356 niu_set_primary_mac(np, np->dev->dev_addr);
4357
4358 if (np->flags & NIU_FLAGS_XMAC)
4359 niu_init_rx_xmac(np);
4360 else
4361 niu_init_rx_bmac(np);
4362}
4363
4364static void niu_enable_tx_xmac(struct niu *np, int on)
4365{
4366 u64 val = nr64_mac(XMAC_CONFIG);
4367
4368 if (on)
4369 val |= XMAC_CONFIG_TX_ENABLE;
4370 else
4371 val &= ~XMAC_CONFIG_TX_ENABLE;
4372 nw64_mac(XMAC_CONFIG, val);
4373}
4374
4375static void niu_enable_tx_bmac(struct niu *np, int on)
4376{
4377 u64 val = nr64_mac(BTXMAC_CONFIG);
4378
4379 if (on)
4380 val |= BTXMAC_CONFIG_ENABLE;
4381 else
4382 val &= ~BTXMAC_CONFIG_ENABLE;
4383 nw64_mac(BTXMAC_CONFIG, val);
4384}
4385
4386static void niu_enable_tx_mac(struct niu *np, int on)
4387{
4388 if (np->flags & NIU_FLAGS_XMAC)
4389 niu_enable_tx_xmac(np, on);
4390 else
4391 niu_enable_tx_bmac(np, on);
4392}
4393
4394static void niu_enable_rx_xmac(struct niu *np, int on)
4395{
4396 u64 val = nr64_mac(XMAC_CONFIG);
4397
4398 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
4399 XMAC_CONFIG_PROMISCUOUS);
4400
4401 if (np->flags & NIU_FLAGS_MCAST)
4402 val |= XMAC_CONFIG_HASH_FILTER_EN;
4403 if (np->flags & NIU_FLAGS_PROMISC)
4404 val |= XMAC_CONFIG_PROMISCUOUS;
4405
4406 if (on)
4407 val |= XMAC_CONFIG_RX_MAC_ENABLE;
4408 else
4409 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
4410 nw64_mac(XMAC_CONFIG, val);
4411}
4412
4413static void niu_enable_rx_bmac(struct niu *np, int on)
4414{
4415 u64 val = nr64_mac(BRXMAC_CONFIG);
4416
4417 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
4418 BRXMAC_CONFIG_PROMISC);
4419
4420 if (np->flags & NIU_FLAGS_MCAST)
4421 val |= BRXMAC_CONFIG_HASH_FILT_EN;
4422 if (np->flags & NIU_FLAGS_PROMISC)
4423 val |= BRXMAC_CONFIG_PROMISC;
4424
4425 if (on)
4426 val |= BRXMAC_CONFIG_ENABLE;
4427 else
4428 val &= ~BRXMAC_CONFIG_ENABLE;
4429 nw64_mac(BRXMAC_CONFIG, val);
4430}
4431
4432static void niu_enable_rx_mac(struct niu *np, int on)
4433{
4434 if (np->flags & NIU_FLAGS_XMAC)
4435 niu_enable_rx_xmac(np, on);
4436 else
4437 niu_enable_rx_bmac(np, on);
4438}
4439
4440static int niu_init_mac(struct niu *np)
4441{
4442 int err;
4443
4444 niu_init_xif(np);
4445 err = niu_init_pcs(np);
4446 if (err)
4447 return err;
4448
4449 err = niu_reset_tx_mac(np);
4450 if (err)
4451 return err;
4452 niu_init_tx_mac(np);
4453 err = niu_reset_rx_mac(np);
4454 if (err)
4455 return err;
4456 niu_init_rx_mac(np);
4457
4458 /* This looks hookey but the RX MAC reset we just did will
4459 * undo some of the state we setup in niu_init_tx_mac() so we
4460 * have to call it again. In particular, the RX MAC reset will
4461 * set the XMAC_MAX register back to it's default value.
4462 */
4463 niu_init_tx_mac(np);
4464 niu_enable_tx_mac(np, 1);
4465
4466 niu_enable_rx_mac(np, 1);
4467
4468 return 0;
4469}
4470
4471static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4472{
4473 (void) niu_tx_channel_stop(np, rp->tx_channel);
4474}
4475
4476static void niu_stop_tx_channels(struct niu *np)
4477{
4478 int i;
4479
4480 for (i = 0; i < np->num_tx_rings; i++) {
4481 struct tx_ring_info *rp = &np->tx_rings[i];
4482
4483 niu_stop_one_tx_channel(np, rp);
4484 }
4485}
4486
4487static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4488{
4489 (void) niu_tx_channel_reset(np, rp->tx_channel);
4490}
4491
4492static void niu_reset_tx_channels(struct niu *np)
4493{
4494 int i;
4495
4496 for (i = 0; i < np->num_tx_rings; i++) {
4497 struct tx_ring_info *rp = &np->tx_rings[i];
4498
4499 niu_reset_one_tx_channel(np, rp);
4500 }
4501}
4502
4503static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4504{
4505 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
4506}
4507
4508static void niu_stop_rx_channels(struct niu *np)
4509{
4510 int i;
4511
4512 for (i = 0; i < np->num_rx_rings; i++) {
4513 struct rx_ring_info *rp = &np->rx_rings[i];
4514
4515 niu_stop_one_rx_channel(np, rp);
4516 }
4517}
4518
4519static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4520{
4521 int channel = rp->rx_channel;
4522
4523 (void) niu_rx_channel_reset(np, channel);
4524 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
4525 nw64(RX_DMA_CTL_STAT(channel), 0);
4526 (void) niu_enable_rx_channel(np, channel, 0);
4527}
4528
4529static void niu_reset_rx_channels(struct niu *np)
4530{
4531 int i;
4532
4533 for (i = 0; i < np->num_rx_rings; i++) {
4534 struct rx_ring_info *rp = &np->rx_rings[i];
4535
4536 niu_reset_one_rx_channel(np, rp);
4537 }
4538}
4539
4540static void niu_disable_ipp(struct niu *np)
4541{
4542 u64 rd, wr, val;
4543 int limit;
4544
4545 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
4546 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
4547 limit = 100;
4548 while (--limit >= 0 && (rd != wr)) {
4549 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
4550 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
4551 }
4552 if (limit < 0 &&
4553 (rd != 0 && wr != 1)) {
4554 dev_err(np->device, PFX "%s: IPP would not quiesce, "
4555 "rd_ptr[%llx] wr_ptr[%llx]\n",
4556 np->dev->name,
4557 (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
4558 (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
4559 }
4560
4561 val = nr64_ipp(IPP_CFIG);
4562 val &= ~(IPP_CFIG_IPP_ENABLE |
4563 IPP_CFIG_DFIFO_ECC_EN |
4564 IPP_CFIG_DROP_BAD_CRC |
4565 IPP_CFIG_CKSUM_EN);
4566 nw64_ipp(IPP_CFIG, val);
4567
4568 (void) niu_ipp_reset(np);
4569}
4570
4571static int niu_init_hw(struct niu *np)
4572{
4573 int i, err;
4574
4575 niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
4576 niu_txc_enable_port(np, 1);
4577 niu_txc_port_dma_enable(np, 1);
4578 niu_txc_set_imask(np, 0);
4579
4580 niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
4581 for (i = 0; i < np->num_tx_rings; i++) {
4582 struct tx_ring_info *rp = &np->tx_rings[i];
4583
4584 err = niu_init_one_tx_channel(np, rp);
4585 if (err)
4586 return err;
4587 }
4588
4589 niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
4590 err = niu_init_rx_channels(np);
4591 if (err)
4592 goto out_uninit_tx_channels;
4593
4594 niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
4595 err = niu_init_classifier_hw(np);
4596 if (err)
4597 goto out_uninit_rx_channels;
4598
4599 niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
4600 err = niu_init_zcp(np);
4601 if (err)
4602 goto out_uninit_rx_channels;
4603
4604 niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
4605 err = niu_init_ipp(np);
4606 if (err)
4607 goto out_uninit_rx_channels;
4608
4609 niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
4610 err = niu_init_mac(np);
4611 if (err)
4612 goto out_uninit_ipp;
4613
4614 return 0;
4615
4616out_uninit_ipp:
4617 niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
4618 niu_disable_ipp(np);
4619
4620out_uninit_rx_channels:
4621 niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
4622 niu_stop_rx_channels(np);
4623 niu_reset_rx_channels(np);
4624
4625out_uninit_tx_channels:
4626 niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
4627 niu_stop_tx_channels(np);
4628 niu_reset_tx_channels(np);
4629
4630 return err;
4631}
4632
4633static void niu_stop_hw(struct niu *np)
4634{
4635 niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
4636 niu_enable_interrupts(np, 0);
4637
4638 niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
4639 niu_enable_rx_mac(np, 0);
4640
4641 niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
4642 niu_disable_ipp(np);
4643
4644 niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
4645 niu_stop_tx_channels(np);
4646
4647 niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
4648 niu_stop_rx_channels(np);
4649
4650 niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
4651 niu_reset_tx_channels(np);
4652
4653 niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
4654 niu_reset_rx_channels(np);
4655}
4656
4657static int niu_request_irq(struct niu *np)
4658{
4659 int i, j, err;
4660
4661 err = 0;
4662 for (i = 0; i < np->num_ldg; i++) {
4663 struct niu_ldg *lp = &np->ldg[i];
4664
4665 err = request_irq(lp->irq, niu_interrupt,
4666 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
4667 np->dev->name, lp);
4668 if (err)
4669 goto out_free_irqs;
4670
4671 }
4672
4673 return 0;
4674
4675out_free_irqs:
4676 for (j = 0; j < i; j++) {
4677 struct niu_ldg *lp = &np->ldg[j];
4678
4679 free_irq(lp->irq, lp);
4680 }
4681 return err;
4682}
4683
4684static void niu_free_irq(struct niu *np)
4685{
4686 int i;
4687
4688 for (i = 0; i < np->num_ldg; i++) {
4689 struct niu_ldg *lp = &np->ldg[i];
4690
4691 free_irq(lp->irq, lp);
4692 }
4693}
4694
4695static void niu_enable_napi(struct niu *np)
4696{
4697 int i;
4698
4699 for (i = 0; i < np->num_ldg; i++)
4700 napi_enable(&np->ldg[i].napi);
4701}
4702
4703static void niu_disable_napi(struct niu *np)
4704{
4705 int i;
4706
4707 for (i = 0; i < np->num_ldg; i++)
4708 napi_disable(&np->ldg[i].napi);
4709}
4710
4711static int niu_open(struct net_device *dev)
4712{
4713 struct niu *np = netdev_priv(dev);
4714 int err;
4715
4716 netif_carrier_off(dev);
4717
4718 err = niu_alloc_channels(np);
4719 if (err)
4720 goto out_err;
4721
4722 err = niu_enable_interrupts(np, 0);
4723 if (err)
4724 goto out_free_channels;
4725
4726 err = niu_request_irq(np);
4727 if (err)
4728 goto out_free_channels;
4729
4730 niu_enable_napi(np);
4731
4732 spin_lock_irq(&np->lock);
4733
4734 err = niu_init_hw(np);
4735 if (!err) {
4736 init_timer(&np->timer);
4737 np->timer.expires = jiffies + HZ;
4738 np->timer.data = (unsigned long) np;
4739 np->timer.function = niu_timer;
4740
4741 err = niu_enable_interrupts(np, 1);
4742 if (err)
4743 niu_stop_hw(np);
4744 }
4745
4746 spin_unlock_irq(&np->lock);
4747
4748 if (err) {
4749 niu_disable_napi(np);
4750 goto out_free_irq;
4751 }
4752
4753 netif_start_queue(dev);
4754
4755 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
4756 netif_carrier_on(dev);
4757
4758 add_timer(&np->timer);
4759
4760 return 0;
4761
4762out_free_irq:
4763 niu_free_irq(np);
4764
4765out_free_channels:
4766 niu_free_channels(np);
4767
4768out_err:
4769 return err;
4770}
4771
4772static void niu_full_shutdown(struct niu *np, struct net_device *dev)
4773{
4774 cancel_work_sync(&np->reset_task);
4775
4776 niu_disable_napi(np);
4777 netif_stop_queue(dev);
4778
4779 del_timer_sync(&np->timer);
4780
4781 spin_lock_irq(&np->lock);
4782
4783 niu_stop_hw(np);
4784
4785 spin_unlock_irq(&np->lock);
4786}
4787
4788static int niu_close(struct net_device *dev)
4789{
4790 struct niu *np = netdev_priv(dev);
4791
4792 niu_full_shutdown(np, dev);
4793
4794 niu_free_irq(np);
4795
4796 niu_free_channels(np);
4797
4798 return 0;
4799}
4800
4801static void niu_sync_xmac_stats(struct niu *np)
4802{
4803 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
4804
4805 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
4806 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
4807
4808 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
4809 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
4810 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
4811 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
4812 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
4813 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
4814 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
4815 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
4816 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
4817 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
4818 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
4819 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
4820 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
4821 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
4822 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
4823 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
4824}
4825
4826static void niu_sync_bmac_stats(struct niu *np)
4827{
4828 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4829
4830 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
4831 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
4832
4833 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
4834 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
4835 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
4836 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
4837}
4838
4839static void niu_sync_mac_stats(struct niu *np)
4840{
4841 if (np->flags & NIU_FLAGS_XMAC)
4842 niu_sync_xmac_stats(np);
4843 else
4844 niu_sync_bmac_stats(np);
4845}
4846
4847static void niu_get_rx_stats(struct niu *np)
4848{
4849 unsigned long pkts, dropped, errors, bytes;
4850 int i;
4851
4852 pkts = dropped = errors = bytes = 0;
4853 for (i = 0; i < np->num_rx_rings; i++) {
4854 struct rx_ring_info *rp = &np->rx_rings[i];
4855
4856 pkts += rp->rx_packets;
4857 bytes += rp->rx_bytes;
4858 dropped += rp->rx_dropped;
4859 errors += rp->rx_errors;
4860 }
4861 np->net_stats.rx_packets = pkts;
4862 np->net_stats.rx_bytes = bytes;
4863 np->net_stats.rx_dropped = dropped;
4864 np->net_stats.rx_errors = errors;
4865}
4866
4867static void niu_get_tx_stats(struct niu *np)
4868{
4869 unsigned long pkts, errors, bytes;
4870 int i;
4871
4872 pkts = errors = bytes = 0;
4873 for (i = 0; i < np->num_tx_rings; i++) {
4874 struct tx_ring_info *rp = &np->tx_rings[i];
4875
4876 pkts += rp->tx_packets;
4877 bytes += rp->tx_bytes;
4878 errors += rp->tx_errors;
4879 }
4880 np->net_stats.tx_packets = pkts;
4881 np->net_stats.tx_bytes = bytes;
4882 np->net_stats.tx_errors = errors;
4883}
4884
4885static struct net_device_stats *niu_get_stats(struct net_device *dev)
4886{
4887 struct niu *np = netdev_priv(dev);
4888
4889 niu_get_rx_stats(np);
4890 niu_get_tx_stats(np);
4891
4892 return &np->net_stats;
4893}
4894
4895static void niu_load_hash_xmac(struct niu *np, u16 *hash)
4896{
4897 int i;
4898
4899 for (i = 0; i < 16; i++)
4900 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
4901}
4902
4903static void niu_load_hash_bmac(struct niu *np, u16 *hash)
4904{
4905 int i;
4906
4907 for (i = 0; i < 16; i++)
4908 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
4909}
4910
4911static void niu_load_hash(struct niu *np, u16 *hash)
4912{
4913 if (np->flags & NIU_FLAGS_XMAC)
4914 niu_load_hash_xmac(np, hash);
4915 else
4916 niu_load_hash_bmac(np, hash);
4917}
4918
4919static void niu_set_rx_mode(struct net_device *dev)
4920{
4921 struct niu *np = netdev_priv(dev);
4922 int i, alt_cnt, err;
4923 struct dev_addr_list *addr;
4924 unsigned long flags;
4925 u16 hash[16] = { 0, };
4926
4927 spin_lock_irqsave(&np->lock, flags);
4928 niu_enable_rx_mac(np, 0);
4929
4930 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
4931 if (dev->flags & IFF_PROMISC)
4932 np->flags |= NIU_FLAGS_PROMISC;
4933 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
4934 np->flags |= NIU_FLAGS_MCAST;
4935
4936 alt_cnt = dev->uc_count;
4937 if (alt_cnt > niu_num_alt_addr(np)) {
4938 alt_cnt = 0;
4939 np->flags |= NIU_FLAGS_PROMISC;
4940 }
4941
4942 if (alt_cnt) {
4943 int index = 0;
4944
4945 for (addr = dev->uc_list; addr; addr = addr->next) {
4946 err = niu_set_alt_mac(np, index,
4947 addr->da_addr);
4948 if (err)
4949 printk(KERN_WARNING PFX "%s: Error %d "
4950 "adding alt mac %d\n",
4951 dev->name, err, index);
4952 err = niu_enable_alt_mac(np, index, 1);
4953 if (err)
4954 printk(KERN_WARNING PFX "%s: Error %d "
4955 "enabling alt mac %d\n",
4956 dev->name, err, index);
4957
4958 index++;
4959 }
4960 } else {
4961 for (i = 0; i < niu_num_alt_addr(np); i++) {
4962 err = niu_enable_alt_mac(np, i, 0);
4963 if (err)
4964 printk(KERN_WARNING PFX "%s: Error %d "
4965 "disabling alt mac %d\n",
4966 dev->name, err, i);
4967 }
4968 }
4969 if (dev->flags & IFF_ALLMULTI) {
4970 for (i = 0; i < 16; i++)
4971 hash[i] = 0xffff;
4972 } else if (dev->mc_count > 0) {
4973 for (addr = dev->mc_list; addr; addr = addr->next) {
4974 u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
4975
4976 crc >>= 24;
4977 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
4978 }
4979 }
4980
4981 if (np->flags & NIU_FLAGS_MCAST)
4982 niu_load_hash(np, hash);
4983
4984 niu_enable_rx_mac(np, 1);
4985 spin_unlock_irqrestore(&np->lock, flags);
4986}
4987
4988static int niu_set_mac_addr(struct net_device *dev, void *p)
4989{
4990 struct niu *np = netdev_priv(dev);
4991 struct sockaddr *addr = p;
4992 unsigned long flags;
4993
4994 if (!is_valid_ether_addr(addr->sa_data))
4995 return -EINVAL;
4996
4997 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
4998
4999 if (!netif_running(dev))
5000 return 0;
5001
5002 spin_lock_irqsave(&np->lock, flags);
5003 niu_enable_rx_mac(np, 0);
5004 niu_set_primary_mac(np, dev->dev_addr);
5005 niu_enable_rx_mac(np, 1);
5006 spin_unlock_irqrestore(&np->lock, flags);
5007
5008 return 0;
5009}
5010
5011static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5012{
5013 return -EOPNOTSUPP;
5014}
5015
5016static void niu_netif_stop(struct niu *np)
5017{
5018 np->dev->trans_start = jiffies; /* prevent tx timeout */
5019
5020 niu_disable_napi(np);
5021
5022 netif_tx_disable(np->dev);
5023}
5024
5025static void niu_netif_start(struct niu *np)
5026{
5027 /* NOTE: unconditional netif_wake_queue is only appropriate
5028 * so long as all callers are assured to have free tx slots
5029 * (such as after niu_init_hw).
5030 */
5031 netif_wake_queue(np->dev);
5032
5033 niu_enable_napi(np);
5034
5035 niu_enable_interrupts(np, 1);
5036}
5037
5038static void niu_reset_task(struct work_struct *work)
5039{
5040 struct niu *np = container_of(work, struct niu, reset_task);
5041 unsigned long flags;
5042 int err;
5043
5044 spin_lock_irqsave(&np->lock, flags);
5045 if (!netif_running(np->dev)) {
5046 spin_unlock_irqrestore(&np->lock, flags);
5047 return;
5048 }
5049
5050 spin_unlock_irqrestore(&np->lock, flags);
5051
5052 del_timer_sync(&np->timer);
5053
5054 niu_netif_stop(np);
5055
5056 spin_lock_irqsave(&np->lock, flags);
5057
5058 niu_stop_hw(np);
5059
5060 err = niu_init_hw(np);
5061 if (!err) {
5062 np->timer.expires = jiffies + HZ;
5063 add_timer(&np->timer);
5064 niu_netif_start(np);
5065 }
5066
5067 spin_unlock_irqrestore(&np->lock, flags);
5068}
5069
5070static void niu_tx_timeout(struct net_device *dev)
5071{
5072 struct niu *np = netdev_priv(dev);
5073
5074 dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
5075 dev->name);
5076
5077 schedule_work(&np->reset_task);
5078}
5079
5080static void niu_set_txd(struct tx_ring_info *rp, int index,
5081 u64 mapping, u64 len, u64 mark,
5082 u64 n_frags)
5083{
5084 __le64 *desc = &rp->descr[index];
5085
5086 *desc = cpu_to_le64(mark |
5087 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
5088 (len << TX_DESC_TR_LEN_SHIFT) |
5089 (mapping & TX_DESC_SAD));
5090}
5091
5092static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
5093 u64 pad_bytes, u64 len)
5094{
5095 u16 eth_proto, eth_proto_inner;
5096 u64 csum_bits, l3off, ihl, ret;
5097 u8 ip_proto;
5098 int ipv6;
5099
5100 eth_proto = be16_to_cpu(ehdr->h_proto);
5101 eth_proto_inner = eth_proto;
5102 if (eth_proto == ETH_P_8021Q) {
5103 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
5104 __be16 val = vp->h_vlan_encapsulated_proto;
5105
5106 eth_proto_inner = be16_to_cpu(val);
5107 }
5108
5109 ipv6 = ihl = 0;
5110 switch (skb->protocol) {
5111 case __constant_htons(ETH_P_IP):
5112 ip_proto = ip_hdr(skb)->protocol;
5113 ihl = ip_hdr(skb)->ihl;
5114 break;
5115 case __constant_htons(ETH_P_IPV6):
5116 ip_proto = ipv6_hdr(skb)->nexthdr;
5117 ihl = (40 >> 2);
5118 ipv6 = 1;
5119 break;
5120 default:
5121 ip_proto = ihl = 0;
5122 break;
5123 }
5124
5125 csum_bits = TXHDR_CSUM_NONE;
5126 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5127 u64 start, stuff;
5128
5129 csum_bits = (ip_proto == IPPROTO_TCP ?
5130 TXHDR_CSUM_TCP :
5131 (ip_proto == IPPROTO_UDP ?
5132 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
5133
5134 start = skb_transport_offset(skb) -
5135 (pad_bytes + sizeof(struct tx_pkt_hdr));
5136 stuff = start + skb->csum_offset;
5137
5138 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
5139 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
5140 }
5141
5142 l3off = skb_network_offset(skb) -
5143 (pad_bytes + sizeof(struct tx_pkt_hdr));
5144
5145 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
5146 (len << TXHDR_LEN_SHIFT) |
5147 ((l3off / 2) << TXHDR_L3START_SHIFT) |
5148 (ihl << TXHDR_IHL_SHIFT) |
5149 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
5150 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
5151 (ipv6 ? TXHDR_IP_VER : 0) |
5152 csum_bits);
5153
5154 return ret;
5155}
5156
5157static struct tx_ring_info *tx_ring_select(struct niu *np, struct sk_buff *skb)
5158{
5159 return &np->tx_rings[0];
5160}
5161
5162static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
5163{
5164 struct niu *np = netdev_priv(dev);
5165 unsigned long align, headroom;
5166 struct tx_ring_info *rp;
5167 struct tx_pkt_hdr *tp;
5168 unsigned int len, nfg;
5169 struct ethhdr *ehdr;
5170 int prod, i, tlen;
5171 u64 mapping, mrk;
5172
5173 rp = tx_ring_select(np, skb);
5174
5175 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
5176 netif_stop_queue(dev);
5177 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
5178 "queue awake!\n", dev->name);
5179 rp->tx_errors++;
5180 return NETDEV_TX_BUSY;
5181 }
5182
5183 if (skb->len < ETH_ZLEN) {
5184 unsigned int pad_bytes = ETH_ZLEN - skb->len;
5185
5186 if (skb_pad(skb, pad_bytes))
5187 goto out;
5188 skb_put(skb, pad_bytes);
5189 }
5190
5191 len = sizeof(struct tx_pkt_hdr) + 15;
5192 if (skb_headroom(skb) < len) {
5193 struct sk_buff *skb_new;
5194
5195 skb_new = skb_realloc_headroom(skb, len);
5196 if (!skb_new) {
5197 rp->tx_errors++;
5198 goto out_drop;
5199 }
5200 kfree_skb(skb);
5201 skb = skb_new;
5202 }
5203
5204 align = ((unsigned long) skb->data & (16 - 1));
5205 headroom = align + sizeof(struct tx_pkt_hdr);
5206
5207 ehdr = (struct ethhdr *) skb->data;
5208 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
5209
5210 len = skb->len - sizeof(struct tx_pkt_hdr);
5211 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
5212 tp->resv = 0;
5213
5214 len = skb_headlen(skb);
5215 mapping = np->ops->map_single(np->device, skb->data,
5216 len, DMA_TO_DEVICE);
5217
5218 prod = rp->prod;
5219
5220 rp->tx_buffs[prod].skb = skb;
5221 rp->tx_buffs[prod].mapping = mapping;
5222
5223 mrk = TX_DESC_SOP;
5224 if (++rp->mark_counter == rp->mark_freq) {
5225 rp->mark_counter = 0;
5226 mrk |= TX_DESC_MARK;
5227 rp->mark_pending++;
5228 }
5229
5230 tlen = len;
5231 nfg = skb_shinfo(skb)->nr_frags;
5232 while (tlen > 0) {
5233 tlen -= MAX_TX_DESC_LEN;
5234 nfg++;
5235 }
5236
5237 while (len > 0) {
5238 unsigned int this_len = len;
5239
5240 if (this_len > MAX_TX_DESC_LEN)
5241 this_len = MAX_TX_DESC_LEN;
5242
5243 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
5244 mrk = nfg = 0;
5245
5246 prod = NEXT_TX(rp, prod);
5247 mapping += this_len;
5248 len -= this_len;
5249 }
5250
5251 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5252 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5253
5254 len = frag->size;
5255 mapping = np->ops->map_page(np->device, frag->page,
5256 frag->page_offset, len,
5257 DMA_TO_DEVICE);
5258
5259 rp->tx_buffs[prod].skb = NULL;
5260 rp->tx_buffs[prod].mapping = mapping;
5261
5262 niu_set_txd(rp, prod, mapping, len, 0, 0);
5263
5264 prod = NEXT_TX(rp, prod);
5265 }
5266
5267 if (prod < rp->prod)
5268 rp->wrap_bit ^= TX_RING_KICK_WRAP;
5269 rp->prod = prod;
5270
5271 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
5272
5273 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
5274 netif_stop_queue(dev);
5275 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
5276 netif_wake_queue(dev);
5277 }
5278
5279 dev->trans_start = jiffies;
5280
5281out:
5282 return NETDEV_TX_OK;
5283
5284out_drop:
5285 rp->tx_errors++;
5286 kfree_skb(skb);
5287 goto out;
5288}
5289
5290static int niu_change_mtu(struct net_device *dev, int new_mtu)
5291{
5292 struct niu *np = netdev_priv(dev);
5293 int err, orig_jumbo, new_jumbo;
5294
5295 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
5296 return -EINVAL;
5297
5298 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
5299 new_jumbo = (new_mtu > ETH_DATA_LEN);
5300
5301 dev->mtu = new_mtu;
5302
5303 if (!netif_running(dev) ||
5304 (orig_jumbo == new_jumbo))
5305 return 0;
5306
5307 niu_full_shutdown(np, dev);
5308
5309 niu_free_channels(np);
5310
5311 niu_enable_napi(np);
5312
5313 err = niu_alloc_channels(np);
5314 if (err)
5315 return err;
5316
5317 spin_lock_irq(&np->lock);
5318
5319 err = niu_init_hw(np);
5320 if (!err) {
5321 init_timer(&np->timer);
5322 np->timer.expires = jiffies + HZ;
5323 np->timer.data = (unsigned long) np;
5324 np->timer.function = niu_timer;
5325
5326 err = niu_enable_interrupts(np, 1);
5327 if (err)
5328 niu_stop_hw(np);
5329 }
5330
5331 spin_unlock_irq(&np->lock);
5332
5333 if (!err) {
5334 netif_start_queue(dev);
5335 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
5336 netif_carrier_on(dev);
5337
5338 add_timer(&np->timer);
5339 }
5340
5341 return err;
5342}
5343
5344static void niu_get_drvinfo(struct net_device *dev,
5345 struct ethtool_drvinfo *info)
5346{
5347 struct niu *np = netdev_priv(dev);
5348 struct niu_vpd *vpd = &np->vpd;
5349
5350 strcpy(info->driver, DRV_MODULE_NAME);
5351 strcpy(info->version, DRV_MODULE_VERSION);
5352 sprintf(info->fw_version, "%d.%d",
5353 vpd->fcode_major, vpd->fcode_minor);
5354 if (np->parent->plat_type != PLAT_TYPE_NIU)
5355 strcpy(info->bus_info, pci_name(np->pdev));
5356}
5357
5358static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5359{
5360 struct niu *np = netdev_priv(dev);
5361 struct niu_link_config *lp;
5362
5363 lp = &np->link_config;
5364
5365 memset(cmd, 0, sizeof(*cmd));
5366 cmd->phy_address = np->phy_addr;
5367 cmd->supported = lp->supported;
5368 cmd->advertising = lp->advertising;
5369 cmd->autoneg = lp->autoneg;
5370 cmd->speed = lp->active_speed;
5371 cmd->duplex = lp->active_duplex;
5372
5373 return 0;
5374}
5375
5376static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5377{
5378 return -EINVAL;
5379}
5380
5381static u32 niu_get_msglevel(struct net_device *dev)
5382{
5383 struct niu *np = netdev_priv(dev);
5384 return np->msg_enable;
5385}
5386
5387static void niu_set_msglevel(struct net_device *dev, u32 value)
5388{
5389 struct niu *np = netdev_priv(dev);
5390 np->msg_enable = value;
5391}
5392
5393static int niu_get_eeprom_len(struct net_device *dev)
5394{
5395 struct niu *np = netdev_priv(dev);
5396
5397 return np->eeprom_len;
5398}
5399
5400static int niu_get_eeprom(struct net_device *dev,
5401 struct ethtool_eeprom *eeprom, u8 *data)
5402{
5403 struct niu *np = netdev_priv(dev);
5404 u32 offset, len, val;
5405
5406 offset = eeprom->offset;
5407 len = eeprom->len;
5408
5409 if (offset + len < offset)
5410 return -EINVAL;
5411 if (offset >= np->eeprom_len)
5412 return -EINVAL;
5413 if (offset + len > np->eeprom_len)
5414 len = eeprom->len = np->eeprom_len - offset;
5415
5416 if (offset & 3) {
5417 u32 b_offset, b_count;
5418
5419 b_offset = offset & 3;
5420 b_count = 4 - b_offset;
5421 if (b_count > len)
5422 b_count = len;
5423
5424 val = nr64(ESPC_NCR((offset - b_offset) / 4));
5425 memcpy(data, ((char *)&val) + b_offset, b_count);
5426 data += b_count;
5427 len -= b_count;
5428 offset += b_count;
5429 }
5430 while (len >= 4) {
5431 val = nr64(ESPC_NCR(offset / 4));
5432 memcpy(data, &val, 4);
5433 data += 4;
5434 len -= 4;
5435 offset += 4;
5436 }
5437 if (len) {
5438 val = nr64(ESPC_NCR(offset / 4));
5439 memcpy(data, &val, len);
5440 }
5441 return 0;
5442}
5443
5444static const struct {
5445 const char string[ETH_GSTRING_LEN];
5446} niu_xmac_stat_keys[] = {
5447 { "tx_frames" },
5448 { "tx_bytes" },
5449 { "tx_fifo_errors" },
5450 { "tx_overflow_errors" },
5451 { "tx_max_pkt_size_errors" },
5452 { "tx_underflow_errors" },
5453 { "rx_local_faults" },
5454 { "rx_remote_faults" },
5455 { "rx_link_faults" },
5456 { "rx_align_errors" },
5457 { "rx_frags" },
5458 { "rx_mcasts" },
5459 { "rx_bcasts" },
5460 { "rx_hist_cnt1" },
5461 { "rx_hist_cnt2" },
5462 { "rx_hist_cnt3" },
5463 { "rx_hist_cnt4" },
5464 { "rx_hist_cnt5" },
5465 { "rx_hist_cnt6" },
5466 { "rx_hist_cnt7" },
5467 { "rx_octets" },
5468 { "rx_code_violations" },
5469 { "rx_len_errors" },
5470 { "rx_crc_errors" },
5471 { "rx_underflows" },
5472 { "rx_overflows" },
5473 { "pause_off_state" },
5474 { "pause_on_state" },
5475 { "pause_received" },
5476};
5477
5478#define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
5479
5480static const struct {
5481 const char string[ETH_GSTRING_LEN];
5482} niu_bmac_stat_keys[] = {
5483 { "tx_underflow_errors" },
5484 { "tx_max_pkt_size_errors" },
5485 { "tx_bytes" },
5486 { "tx_frames" },
5487 { "rx_overflows" },
5488 { "rx_frames" },
5489 { "rx_align_errors" },
5490 { "rx_crc_errors" },
5491 { "rx_len_errors" },
5492 { "pause_off_state" },
5493 { "pause_on_state" },
5494 { "pause_received" },
5495};
5496
5497#define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
5498
5499static const struct {
5500 const char string[ETH_GSTRING_LEN];
5501} niu_rxchan_stat_keys[] = {
5502 { "rx_channel" },
5503 { "rx_packets" },
5504 { "rx_bytes" },
5505 { "rx_dropped" },
5506 { "rx_errors" },
5507};
5508
5509#define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
5510
5511static const struct {
5512 const char string[ETH_GSTRING_LEN];
5513} niu_txchan_stat_keys[] = {
5514 { "tx_channel" },
5515 { "tx_packets" },
5516 { "tx_bytes" },
5517 { "tx_errors" },
5518};
5519
5520#define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
5521
5522static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
5523{
5524 struct niu *np = netdev_priv(dev);
5525 int i;
5526
5527 if (stringset != ETH_SS_STATS)
5528 return;
5529
5530 if (np->flags & NIU_FLAGS_XMAC) {
5531 memcpy(data, niu_xmac_stat_keys,
5532 sizeof(niu_xmac_stat_keys));
5533 data += sizeof(niu_xmac_stat_keys);
5534 } else {
5535 memcpy(data, niu_bmac_stat_keys,
5536 sizeof(niu_bmac_stat_keys));
5537 data += sizeof(niu_bmac_stat_keys);
5538 }
5539 for (i = 0; i < np->num_rx_rings; i++) {
5540 memcpy(data, niu_rxchan_stat_keys,
5541 sizeof(niu_rxchan_stat_keys));
5542 data += sizeof(niu_rxchan_stat_keys);
5543 }
5544 for (i = 0; i < np->num_tx_rings; i++) {
5545 memcpy(data, niu_txchan_stat_keys,
5546 sizeof(niu_txchan_stat_keys));
5547 data += sizeof(niu_txchan_stat_keys);
5548 }
5549}
5550
5551static int niu_get_stats_count(struct net_device *dev)
5552{
5553 struct niu *np = netdev_priv(dev);
5554
5555 return ((np->flags & NIU_FLAGS_XMAC ?
5556 NUM_XMAC_STAT_KEYS :
5557 NUM_BMAC_STAT_KEYS) +
5558 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
5559 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
5560}
5561
5562static void niu_get_ethtool_stats(struct net_device *dev,
5563 struct ethtool_stats *stats, u64 *data)
5564{
5565 struct niu *np = netdev_priv(dev);
5566 int i;
5567
5568 niu_sync_mac_stats(np);
5569 if (np->flags & NIU_FLAGS_XMAC) {
5570 memcpy(data, &np->mac_stats.xmac,
5571 sizeof(struct niu_xmac_stats));
5572 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
5573 } else {
5574 memcpy(data, &np->mac_stats.bmac,
5575 sizeof(struct niu_bmac_stats));
5576 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
5577 }
5578 for (i = 0; i < np->num_rx_rings; i++) {
5579 struct rx_ring_info *rp = &np->rx_rings[i];
5580
5581 data[0] = rp->rx_channel;
5582 data[1] = rp->rx_packets;
5583 data[2] = rp->rx_bytes;
5584 data[3] = rp->rx_dropped;
5585 data[4] = rp->rx_errors;
5586 data += 5;
5587 }
5588 for (i = 0; i < np->num_tx_rings; i++) {
5589 struct tx_ring_info *rp = &np->tx_rings[i];
5590
5591 data[0] = rp->tx_channel;
5592 data[1] = rp->tx_packets;
5593 data[2] = rp->tx_bytes;
5594 data[3] = rp->tx_errors;
5595 data += 4;
5596 }
5597}
5598
5599static u64 niu_led_state_save(struct niu *np)
5600{
5601 if (np->flags & NIU_FLAGS_XMAC)
5602 return nr64_mac(XMAC_CONFIG);
5603 else
5604 return nr64_mac(BMAC_XIF_CONFIG);
5605}
5606
5607static void niu_led_state_restore(struct niu *np, u64 val)
5608{
5609 if (np->flags & NIU_FLAGS_XMAC)
5610 nw64_mac(XMAC_CONFIG, val);
5611 else
5612 nw64_mac(BMAC_XIF_CONFIG, val);
5613}
5614
5615static void niu_force_led(struct niu *np, int on)
5616{
5617 u64 val, reg, bit;
5618
5619 if (np->flags & NIU_FLAGS_XMAC) {
5620 reg = XMAC_CONFIG;
5621 bit = XMAC_CONFIG_FORCE_LED_ON;
5622 } else {
5623 reg = BMAC_XIF_CONFIG;
5624 bit = BMAC_XIF_CONFIG_LINK_LED;
5625 }
5626
5627 val = nr64_mac(reg);
5628 if (on)
5629 val |= bit;
5630 else
5631 val &= ~bit;
5632 nw64_mac(reg, val);
5633}
5634
5635static int niu_phys_id(struct net_device *dev, u32 data)
5636{
5637 struct niu *np = netdev_priv(dev);
5638 u64 orig_led_state;
5639 int i;
5640
5641 if (!netif_running(dev))
5642 return -EAGAIN;
5643
5644 if (data == 0)
5645 data = 2;
5646
5647 orig_led_state = niu_led_state_save(np);
5648 for (i = 0; i < (data * 2); i++) {
5649 int on = ((i % 2) == 0);
5650
5651 niu_force_led(np, on);
5652
5653 if (msleep_interruptible(500))
5654 break;
5655 }
5656 niu_led_state_restore(np, orig_led_state);
5657
5658 return 0;
5659}
5660
5661static const struct ethtool_ops niu_ethtool_ops = {
5662 .get_drvinfo = niu_get_drvinfo,
5663 .get_link = ethtool_op_get_link,
5664 .get_msglevel = niu_get_msglevel,
5665 .set_msglevel = niu_set_msglevel,
5666 .get_eeprom_len = niu_get_eeprom_len,
5667 .get_eeprom = niu_get_eeprom,
5668 .get_settings = niu_get_settings,
5669 .set_settings = niu_set_settings,
5670 .get_strings = niu_get_strings,
5671 .get_stats_count = niu_get_stats_count,
5672 .get_ethtool_stats = niu_get_ethtool_stats,
5673 .phys_id = niu_phys_id,
5674};
5675
5676static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
5677 int ldg, int ldn)
5678{
5679 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
5680 return -EINVAL;
5681 if (ldn < 0 || ldn > LDN_MAX)
5682 return -EINVAL;
5683
5684 parent->ldg_map[ldn] = ldg;
5685
5686 if (np->parent->plat_type == PLAT_TYPE_NIU) {
5687 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
5688 * the firmware, and we're not supposed to change them.
5689 * Validate the mapping, because if it's wrong we probably
5690 * won't get any interrupts and that's painful to debug.
5691 */
5692 if (nr64(LDG_NUM(ldn)) != ldg) {
5693 dev_err(np->device, PFX "Port %u, mis-matched "
5694 "LDG assignment "
5695 "for ldn %d, should be %d is %llu\n",
5696 np->port, ldn, ldg,
5697 (unsigned long long) nr64(LDG_NUM(ldn)));
5698 return -EINVAL;
5699 }
5700 } else
5701 nw64(LDG_NUM(ldn), ldg);
5702
5703 return 0;
5704}
5705
5706static int niu_set_ldg_timer_res(struct niu *np, int res)
5707{
5708 if (res < 0 || res > LDG_TIMER_RES_VAL)
5709 return -EINVAL;
5710
5711
5712 nw64(LDG_TIMER_RES, res);
5713
5714 return 0;
5715}
5716
5717static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
5718{
5719 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
5720 (func < 0 || func > 3) ||
5721 (vector < 0 || vector > 0x1f))
5722 return -EINVAL;
5723
5724 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
5725
5726 return 0;
5727}
5728
5729static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
5730{
5731 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
5732 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
5733 int limit;
5734
5735 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
5736 return -EINVAL;
5737
5738 frame = frame_base;
5739 nw64(ESPC_PIO_STAT, frame);
5740 limit = 64;
5741 do {
5742 udelay(5);
5743 frame = nr64(ESPC_PIO_STAT);
5744 if (frame & ESPC_PIO_STAT_READ_END)
5745 break;
5746 } while (limit--);
5747 if (!(frame & ESPC_PIO_STAT_READ_END)) {
5748 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
5749 (unsigned long long) frame);
5750 return -ENODEV;
5751 }
5752
5753 frame = frame_base;
5754 nw64(ESPC_PIO_STAT, frame);
5755 limit = 64;
5756 do {
5757 udelay(5);
5758 frame = nr64(ESPC_PIO_STAT);
5759 if (frame & ESPC_PIO_STAT_READ_END)
5760 break;
5761 } while (limit--);
5762 if (!(frame & ESPC_PIO_STAT_READ_END)) {
5763 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
5764 (unsigned long long) frame);
5765 return -ENODEV;
5766 }
5767
5768 frame = nr64(ESPC_PIO_STAT);
5769 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
5770}
5771
5772static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
5773{
5774 int err = niu_pci_eeprom_read(np, off);
5775 u16 val;
5776
5777 if (err < 0)
5778 return err;
5779 val = (err << 8);
5780 err = niu_pci_eeprom_read(np, off + 1);
5781 if (err < 0)
5782 return err;
5783 val |= (err & 0xff);
5784
5785 return val;
5786}
5787
5788static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
5789{
5790 int err = niu_pci_eeprom_read(np, off);
5791 u16 val;
5792
5793 if (err < 0)
5794 return err;
5795
5796 val = (err & 0xff);
5797 err = niu_pci_eeprom_read(np, off + 1);
5798 if (err < 0)
5799 return err;
5800
5801 val |= (err & 0xff) << 8;
5802
5803 return val;
5804}
5805
5806static int __devinit niu_pci_vpd_get_propname(struct niu *np,
5807 u32 off,
5808 char *namebuf,
5809 int namebuf_len)
5810{
5811 int i;
5812
5813 for (i = 0; i < namebuf_len; i++) {
5814 int err = niu_pci_eeprom_read(np, off + i);
5815 if (err < 0)
5816 return err;
5817 *namebuf++ = err;
5818 if (!err)
5819 break;
5820 }
5821 if (i >= namebuf_len)
5822 return -EINVAL;
5823
5824 return i + 1;
5825}
5826
5827static void __devinit niu_vpd_parse_version(struct niu *np)
5828{
5829 struct niu_vpd *vpd = &np->vpd;
5830 int len = strlen(vpd->version) + 1;
5831 const char *s = vpd->version;
5832 int i;
5833
5834 for (i = 0; i < len - 5; i++) {
5835 if (!strncmp(s + i, "FCode ", 5))
5836 break;
5837 }
5838 if (i >= len - 5)
5839 return;
5840
5841 s += i + 5;
5842 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
5843
5844 niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
5845 vpd->fcode_major, vpd->fcode_minor);
5846 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
5847 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
5848 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
5849 np->flags |= NIU_FLAGS_VPD_VALID;
5850}
5851
5852/* ESPC_PIO_EN_ENABLE must be set */
5853static int __devinit niu_pci_vpd_scan_props(struct niu *np,
5854 u32 start, u32 end)
5855{
5856 unsigned int found_mask = 0;
5857#define FOUND_MASK_MODEL 0x00000001
5858#define FOUND_MASK_BMODEL 0x00000002
5859#define FOUND_MASK_VERS 0x00000004
5860#define FOUND_MASK_MAC 0x00000008
5861#define FOUND_MASK_NMAC 0x00000010
5862#define FOUND_MASK_PHY 0x00000020
5863#define FOUND_MASK_ALL 0x0000003f
5864
5865 niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
5866 start, end);
5867 while (start < end) {
5868 int len, err, instance, type, prop_len;
5869 char namebuf[64];
5870 u8 *prop_buf;
5871 int max_len;
5872
5873 if (found_mask == FOUND_MASK_ALL) {
5874 niu_vpd_parse_version(np);
5875 return 1;
5876 }
5877
5878 err = niu_pci_eeprom_read(np, start + 2);
5879 if (err < 0)
5880 return err;
5881 len = err;
5882 start += 3;
5883
5884 instance = niu_pci_eeprom_read(np, start);
5885 type = niu_pci_eeprom_read(np, start + 3);
5886 prop_len = niu_pci_eeprom_read(np, start + 4);
5887 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
5888 if (err < 0)
5889 return err;
5890
5891 prop_buf = NULL;
5892 max_len = 0;
5893 if (!strcmp(namebuf, "model")) {
5894 prop_buf = np->vpd.model;
5895 max_len = NIU_VPD_MODEL_MAX;
5896 found_mask |= FOUND_MASK_MODEL;
5897 } else if (!strcmp(namebuf, "board-model")) {
5898 prop_buf = np->vpd.board_model;
5899 max_len = NIU_VPD_BD_MODEL_MAX;
5900 found_mask |= FOUND_MASK_BMODEL;
5901 } else if (!strcmp(namebuf, "version")) {
5902 prop_buf = np->vpd.version;
5903 max_len = NIU_VPD_VERSION_MAX;
5904 found_mask |= FOUND_MASK_VERS;
5905 } else if (!strcmp(namebuf, "local-mac-address")) {
5906 prop_buf = np->vpd.local_mac;
5907 max_len = ETH_ALEN;
5908 found_mask |= FOUND_MASK_MAC;
5909 } else if (!strcmp(namebuf, "num-mac-addresses")) {
5910 prop_buf = &np->vpd.mac_num;
5911 max_len = 1;
5912 found_mask |= FOUND_MASK_NMAC;
5913 } else if (!strcmp(namebuf, "phy-type")) {
5914 prop_buf = np->vpd.phy_type;
5915 max_len = NIU_VPD_PHY_TYPE_MAX;
5916 found_mask |= FOUND_MASK_PHY;
5917 }
5918
5919 if (max_len && prop_len > max_len) {
5920 dev_err(np->device, PFX "Property '%s' length (%d) is "
5921 "too long.\n", namebuf, prop_len);
5922 return -EINVAL;
5923 }
5924
5925 if (prop_buf) {
5926 u32 off = start + 5 + err;
5927 int i;
5928
5929 niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
5930 "len[%d]\n", namebuf, prop_len);
5931 for (i = 0; i < prop_len; i++)
5932 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
5933 }
5934
5935 start += len;
5936 }
5937
5938 return 0;
5939}
5940
5941/* ESPC_PIO_EN_ENABLE must be set */
5942static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
5943{
5944 u32 offset;
5945 int err;
5946
5947 err = niu_pci_eeprom_read16_swp(np, start + 1);
5948 if (err < 0)
5949 return;
5950
5951 offset = err + 3;
5952
5953 while (start + offset < ESPC_EEPROM_SIZE) {
5954 u32 here = start + offset;
5955 u32 end;
5956
5957 err = niu_pci_eeprom_read(np, here);
5958 if (err != 0x90)
5959 return;
5960
5961 err = niu_pci_eeprom_read16_swp(np, here + 1);
5962 if (err < 0)
5963 return;
5964
5965 here = start + offset + 3;
5966 end = start + offset + err;
5967
5968 offset += err;
5969
5970 err = niu_pci_vpd_scan_props(np, here, end);
5971 if (err < 0 || err == 1)
5972 return;
5973 }
5974}
5975
5976/* ESPC_PIO_EN_ENABLE must be set */
5977static u32 __devinit niu_pci_vpd_offset(struct niu *np)
5978{
5979 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
5980 int err;
5981
5982 while (start < end) {
5983 ret = start;
5984
5985 /* ROM header signature? */
5986 err = niu_pci_eeprom_read16(np, start + 0);
5987 if (err != 0x55aa)
5988 return 0;
5989
5990 /* Apply offset to PCI data structure. */
5991 err = niu_pci_eeprom_read16(np, start + 23);
5992 if (err < 0)
5993 return 0;
5994 start += err;
5995
5996 /* Check for "PCIR" signature. */
5997 err = niu_pci_eeprom_read16(np, start + 0);
5998 if (err != 0x5043)
5999 return 0;
6000 err = niu_pci_eeprom_read16(np, start + 2);
6001 if (err != 0x4952)
6002 return 0;
6003
6004 /* Check for OBP image type. */
6005 err = niu_pci_eeprom_read(np, start + 20);
6006 if (err < 0)
6007 return 0;
6008 if (err != 0x01) {
6009 err = niu_pci_eeprom_read(np, ret + 2);
6010 if (err < 0)
6011 return 0;
6012
6013 start = ret + (err * 512);
6014 continue;
6015 }
6016
6017 err = niu_pci_eeprom_read16_swp(np, start + 8);
6018 if (err < 0)
6019 return err;
6020 ret += err;
6021
6022 err = niu_pci_eeprom_read(np, ret + 0);
6023 if (err != 0x82)
6024 return 0;
6025
6026 return ret;
6027 }
6028
6029 return 0;
6030}
6031
6032static int __devinit niu_phy_type_prop_decode(struct niu *np,
6033 const char *phy_prop)
6034{
6035 if (!strcmp(phy_prop, "mif")) {
6036 /* 1G copper, MII */
6037 np->flags &= ~(NIU_FLAGS_FIBER |
6038 NIU_FLAGS_10G);
6039 np->mac_xcvr = MAC_XCVR_MII;
6040 } else if (!strcmp(phy_prop, "xgf")) {
6041 /* 10G fiber, XPCS */
6042 np->flags |= (NIU_FLAGS_10G |
6043 NIU_FLAGS_FIBER);
6044 np->mac_xcvr = MAC_XCVR_XPCS;
6045 } else if (!strcmp(phy_prop, "pcs")) {
6046 /* 1G fiber, PCS */
6047 np->flags &= ~NIU_FLAGS_10G;
6048 np->flags |= NIU_FLAGS_FIBER;
6049 np->mac_xcvr = MAC_XCVR_PCS;
6050 } else if (!strcmp(phy_prop, "xgc")) {
6051 /* 10G copper, XPCS */
6052 np->flags |= NIU_FLAGS_10G;
6053 np->flags &= ~NIU_FLAGS_FIBER;
6054 np->mac_xcvr = MAC_XCVR_XPCS;
6055 } else {
6056 return -EINVAL;
6057 }
6058 return 0;
6059}
6060
6061static void __devinit niu_pci_vpd_validate(struct niu *np)
6062{
6063 struct net_device *dev = np->dev;
6064 struct niu_vpd *vpd = &np->vpd;
6065 u8 val8;
6066
6067 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
6068 dev_err(np->device, PFX "VPD MAC invalid, "
6069 "falling back to SPROM.\n");
6070
6071 np->flags &= ~NIU_FLAGS_VPD_VALID;
6072 return;
6073 }
6074
6075 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
6076 dev_err(np->device, PFX "Illegal phy string [%s].\n",
6077 np->vpd.phy_type);
6078 dev_err(np->device, PFX "Falling back to SPROM.\n");
6079 np->flags &= ~NIU_FLAGS_VPD_VALID;
6080 return;
6081 }
6082
6083 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
6084
6085 val8 = dev->perm_addr[5];
6086 dev->perm_addr[5] += np->port;
6087 if (dev->perm_addr[5] < val8)
6088 dev->perm_addr[4]++;
6089
6090 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6091}
6092
6093static int __devinit niu_pci_probe_sprom(struct niu *np)
6094{
6095 struct net_device *dev = np->dev;
6096 int len, i;
6097 u64 val, sum;
6098 u8 val8;
6099
6100 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
6101 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
6102 len = val / 4;
6103
6104 np->eeprom_len = len;
6105
6106 niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
6107
6108 sum = 0;
6109 for (i = 0; i < len; i++) {
6110 val = nr64(ESPC_NCR(i));
6111 sum += (val >> 0) & 0xff;
6112 sum += (val >> 8) & 0xff;
6113 sum += (val >> 16) & 0xff;
6114 sum += (val >> 24) & 0xff;
6115 }
6116 niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
6117 if ((sum & 0xff) != 0xab) {
6118 dev_err(np->device, PFX "Bad SPROM checksum "
6119 "(%x, should be 0xab)\n", (int) (sum & 0xff));
6120 return -EINVAL;
6121 }
6122
6123 val = nr64(ESPC_PHY_TYPE);
6124 switch (np->port) {
6125 case 0:
6126 val = (val & ESPC_PHY_TYPE_PORT0) >>
6127 ESPC_PHY_TYPE_PORT0_SHIFT;
6128 break;
6129 case 1:
6130 val = (val & ESPC_PHY_TYPE_PORT1) >>
6131 ESPC_PHY_TYPE_PORT1_SHIFT;
6132 break;
6133 case 2:
6134 val = (val & ESPC_PHY_TYPE_PORT2) >>
6135 ESPC_PHY_TYPE_PORT2_SHIFT;
6136 break;
6137 case 3:
6138 val = (val & ESPC_PHY_TYPE_PORT3) >>
6139 ESPC_PHY_TYPE_PORT3_SHIFT;
6140 break;
6141 default:
6142 dev_err(np->device, PFX "Bogus port number %u\n",
6143 np->port);
6144 return -EINVAL;
6145 }
6146 niudbg(PROBE, "SPROM: PHY type %llx\n", (unsigned long long) val);
6147
6148 switch (val) {
6149 case ESPC_PHY_TYPE_1G_COPPER:
6150 /* 1G copper, MII */
6151 np->flags &= ~(NIU_FLAGS_FIBER |
6152 NIU_FLAGS_10G);
6153 np->mac_xcvr = MAC_XCVR_MII;
6154 break;
6155
6156 case ESPC_PHY_TYPE_1G_FIBER:
6157 /* 1G fiber, PCS */
6158 np->flags &= ~NIU_FLAGS_10G;
6159 np->flags |= NIU_FLAGS_FIBER;
6160 np->mac_xcvr = MAC_XCVR_PCS;
6161 break;
6162
6163 case ESPC_PHY_TYPE_10G_COPPER:
6164 /* 10G copper, XPCS */
6165 np->flags |= NIU_FLAGS_10G;
6166 np->flags &= ~NIU_FLAGS_FIBER;
6167 np->mac_xcvr = MAC_XCVR_XPCS;
6168 break;
6169
6170 case ESPC_PHY_TYPE_10G_FIBER:
6171 /* 10G fiber, XPCS */
6172 np->flags |= (NIU_FLAGS_10G |
6173 NIU_FLAGS_FIBER);
6174 np->mac_xcvr = MAC_XCVR_XPCS;
6175 break;
6176
6177 default:
6178 dev_err(np->device, PFX "Bogus SPROM phy type %llu\n",
6179 (unsigned long long) val);
6180 return -EINVAL;
6181 }
6182
6183 val = nr64(ESPC_MAC_ADDR0);
6184 niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
6185 (unsigned long long) val);
6186 dev->perm_addr[0] = (val >> 0) & 0xff;
6187 dev->perm_addr[1] = (val >> 8) & 0xff;
6188 dev->perm_addr[2] = (val >> 16) & 0xff;
6189 dev->perm_addr[3] = (val >> 24) & 0xff;
6190
6191 val = nr64(ESPC_MAC_ADDR1);
6192 niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
6193 (unsigned long long) val);
6194 dev->perm_addr[4] = (val >> 0) & 0xff;
6195 dev->perm_addr[5] = (val >> 8) & 0xff;
6196
6197 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
6198 dev_err(np->device, PFX "SPROM MAC address invalid\n");
6199 dev_err(np->device, PFX "[ \n");
6200 for (i = 0; i < 6; i++)
6201 printk("%02x ", dev->perm_addr[i]);
6202 printk("]\n");
6203 return -EINVAL;
6204 }
6205
6206 val8 = dev->perm_addr[5];
6207 dev->perm_addr[5] += np->port;
6208 if (dev->perm_addr[5] < val8)
6209 dev->perm_addr[4]++;
6210
6211 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6212
6213 val = nr64(ESPC_MOD_STR_LEN);
6214 niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
6215 (unsigned long long) val);
6216 if (val > 8 * 4)
6217 return -EINVAL;
6218
6219 for (i = 0; i < val; i += 4) {
6220 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
6221
6222 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
6223 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
6224 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
6225 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
6226 }
6227 np->vpd.model[val] = '\0';
6228
6229 val = nr64(ESPC_BD_MOD_STR_LEN);
6230 niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
6231 (unsigned long long) val);
6232 if (val > 4 * 4)
6233 return -EINVAL;
6234
6235 for (i = 0; i < val; i += 4) {
6236 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
6237
6238 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
6239 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
6240 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
6241 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
6242 }
6243 np->vpd.board_model[val] = '\0';
6244
6245 np->vpd.mac_num =
6246 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
6247 niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
6248 np->vpd.mac_num);
6249
6250 return 0;
6251}
6252
6253static int __devinit niu_get_and_validate_port(struct niu *np)
6254{
6255 struct niu_parent *parent = np->parent;
6256
6257 if (np->port <= 1)
6258 np->flags |= NIU_FLAGS_XMAC;
6259
6260 if (!parent->num_ports) {
6261 if (parent->plat_type == PLAT_TYPE_NIU) {
6262 parent->num_ports = 2;
6263 } else {
6264 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
6265 ESPC_NUM_PORTS_MACS_VAL;
6266
6267 if (!parent->num_ports)
6268 parent->num_ports = 4;
6269 }
6270 }
6271
6272 niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
6273 np->port, parent->num_ports);
6274 if (np->port >= parent->num_ports)
6275 return -ENODEV;
6276
6277 return 0;
6278}
6279
6280static int __devinit phy_record(struct niu_parent *parent,
6281 struct phy_probe_info *p,
6282 int dev_id_1, int dev_id_2, u8 phy_port,
6283 int type)
6284{
6285 u32 id = (dev_id_1 << 16) | dev_id_2;
6286 u8 idx;
6287
6288 if (dev_id_1 < 0 || dev_id_2 < 0)
6289 return 0;
6290 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
6291 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704)
6292 return 0;
6293 } else {
6294 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
6295 return 0;
6296 }
6297
6298 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
6299 parent->index, id,
6300 (type == PHY_TYPE_PMA_PMD ?
6301 "PMA/PMD" :
6302 (type == PHY_TYPE_PCS ?
6303 "PCS" : "MII")),
6304 phy_port);
6305
6306 if (p->cur[type] >= NIU_MAX_PORTS) {
6307 printk(KERN_ERR PFX "Too many PHY ports.\n");
6308 return -EINVAL;
6309 }
6310 idx = p->cur[type];
6311 p->phy_id[type][idx] = id;
6312 p->phy_port[type][idx] = phy_port;
6313 p->cur[type] = idx + 1;
6314 return 0;
6315}
6316
6317static int __devinit port_has_10g(struct phy_probe_info *p, int port)
6318{
6319 int i;
6320
6321 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
6322 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
6323 return 1;
6324 }
6325 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
6326 if (p->phy_port[PHY_TYPE_PCS][i] == port)
6327 return 1;
6328 }
6329
6330 return 0;
6331}
6332
6333static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
6334{
6335 int port, cnt;
6336
6337 cnt = 0;
6338 *lowest = 32;
6339 for (port = 8; port < 32; port++) {
6340 if (port_has_10g(p, port)) {
6341 if (!cnt)
6342 *lowest = port;
6343 cnt++;
6344 }
6345 }
6346
6347 return cnt;
6348}
6349
6350static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
6351{
6352 *lowest = 32;
6353 if (p->cur[PHY_TYPE_MII])
6354 *lowest = p->phy_port[PHY_TYPE_MII][0];
6355
6356 return p->cur[PHY_TYPE_MII];
6357}
6358
6359static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
6360{
6361 int num_ports = parent->num_ports;
6362 int i;
6363
6364 for (i = 0; i < num_ports; i++) {
6365 parent->rxchan_per_port[i] = (16 / num_ports);
6366 parent->txchan_per_port[i] = (16 / num_ports);
6367
6368 pr_info(PFX "niu%d: Port %u [%u RX chans] "
6369 "[%u TX chans]\n",
6370 parent->index, i,
6371 parent->rxchan_per_port[i],
6372 parent->txchan_per_port[i]);
6373 }
6374}
6375
6376static void __devinit niu_divide_channels(struct niu_parent *parent,
6377 int num_10g, int num_1g)
6378{
6379 int num_ports = parent->num_ports;
6380 int rx_chans_per_10g, rx_chans_per_1g;
6381 int tx_chans_per_10g, tx_chans_per_1g;
6382 int i, tot_rx, tot_tx;
6383
6384 if (!num_10g || !num_1g) {
6385 rx_chans_per_10g = rx_chans_per_1g =
6386 (NIU_NUM_RXCHAN / num_ports);
6387 tx_chans_per_10g = tx_chans_per_1g =
6388 (NIU_NUM_TXCHAN / num_ports);
6389 } else {
6390 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
6391 rx_chans_per_10g = (NIU_NUM_RXCHAN -
6392 (rx_chans_per_1g * num_1g)) /
6393 num_10g;
6394
6395 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
6396 tx_chans_per_10g = (NIU_NUM_TXCHAN -
6397 (tx_chans_per_1g * num_1g)) /
6398 num_10g;
6399 }
6400
6401 tot_rx = tot_tx = 0;
6402 for (i = 0; i < num_ports; i++) {
6403 int type = phy_decode(parent->port_phy, i);
6404
6405 if (type == PORT_TYPE_10G) {
6406 parent->rxchan_per_port[i] = rx_chans_per_10g;
6407 parent->txchan_per_port[i] = tx_chans_per_10g;
6408 } else {
6409 parent->rxchan_per_port[i] = rx_chans_per_1g;
6410 parent->txchan_per_port[i] = tx_chans_per_1g;
6411 }
6412 pr_info(PFX "niu%d: Port %u [%u RX chans] "
6413 "[%u TX chans]\n",
6414 parent->index, i,
6415 parent->rxchan_per_port[i],
6416 parent->txchan_per_port[i]);
6417 tot_rx += parent->rxchan_per_port[i];
6418 tot_tx += parent->txchan_per_port[i];
6419 }
6420
6421 if (tot_rx > NIU_NUM_RXCHAN) {
6422 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
6423 "resetting to one per port.\n",
6424 parent->index, tot_rx);
6425 for (i = 0; i < num_ports; i++)
6426 parent->rxchan_per_port[i] = 1;
6427 }
6428 if (tot_tx > NIU_NUM_TXCHAN) {
6429 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
6430 "resetting to one per port.\n",
6431 parent->index, tot_tx);
6432 for (i = 0; i < num_ports; i++)
6433 parent->txchan_per_port[i] = 1;
6434 }
6435 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
6436 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
6437 "RX[%d] TX[%d]\n",
6438 parent->index, tot_rx, tot_tx);
6439 }
6440}
6441
6442static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
6443 int num_10g, int num_1g)
6444{
6445 int i, num_ports = parent->num_ports;
6446 int rdc_group, rdc_groups_per_port;
6447 int rdc_channel_base;
6448
6449 rdc_group = 0;
6450 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
6451
6452 rdc_channel_base = 0;
6453
6454 for (i = 0; i < num_ports; i++) {
6455 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
6456 int grp, num_channels = parent->rxchan_per_port[i];
6457 int this_channel_offset;
6458
6459 tp->first_table_num = rdc_group;
6460 tp->num_tables = rdc_groups_per_port;
6461 this_channel_offset = 0;
6462 for (grp = 0; grp < tp->num_tables; grp++) {
6463 struct rdc_table *rt = &tp->tables[grp];
6464 int slot;
6465
6466 pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
6467 parent->index, i, tp->first_table_num + grp);
6468 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
6469 rt->rxdma_channel[slot] =
6470 rdc_channel_base + this_channel_offset;
6471
6472 printk("%d ", rt->rxdma_channel[slot]);
6473
6474 if (++this_channel_offset == num_channels)
6475 this_channel_offset = 0;
6476 }
6477 printk("]\n");
6478 }
6479
6480 parent->rdc_default[i] = rdc_channel_base;
6481
6482 rdc_channel_base += num_channels;
6483 rdc_group += rdc_groups_per_port;
6484 }
6485}
6486
6487static int __devinit fill_phy_probe_info(struct niu *np,
6488 struct niu_parent *parent,
6489 struct phy_probe_info *info)
6490{
6491 unsigned long flags;
6492 int port, err;
6493
6494 memset(info, 0, sizeof(*info));
6495
6496 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
6497 niu_lock_parent(np, flags);
6498 err = 0;
6499 for (port = 8; port < 32; port++) {
6500 int dev_id_1, dev_id_2;
6501
6502 dev_id_1 = mdio_read(np, port,
6503 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
6504 dev_id_2 = mdio_read(np, port,
6505 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
6506 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
6507 PHY_TYPE_PMA_PMD);
6508 if (err)
6509 break;
6510 dev_id_1 = mdio_read(np, port,
6511 NIU_PCS_DEV_ADDR, MII_PHYSID1);
6512 dev_id_2 = mdio_read(np, port,
6513 NIU_PCS_DEV_ADDR, MII_PHYSID2);
6514 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
6515 PHY_TYPE_PCS);
6516 if (err)
6517 break;
6518 dev_id_1 = mii_read(np, port, MII_PHYSID1);
6519 dev_id_2 = mii_read(np, port, MII_PHYSID2);
6520 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
6521 PHY_TYPE_MII);
6522 if (err)
6523 break;
6524 }
6525 niu_unlock_parent(np, flags);
6526
6527 return err;
6528}
6529
6530static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
6531{
6532 struct phy_probe_info *info = &parent->phy_probe_info;
6533 int lowest_10g, lowest_1g;
6534 int num_10g, num_1g;
6535 u32 val;
6536 int err;
6537
6538 err = fill_phy_probe_info(np, parent, info);
6539 if (err)
6540 return err;
6541
6542 num_10g = count_10g_ports(info, &lowest_10g);
6543 num_1g = count_1g_ports(info, &lowest_1g);
6544
6545 switch ((num_10g << 4) | num_1g) {
6546 case 0x24:
6547 if (lowest_1g == 10)
6548 parent->plat_type = PLAT_TYPE_VF_P0;
6549 else if (lowest_1g == 26)
6550 parent->plat_type = PLAT_TYPE_VF_P1;
6551 else
6552 goto unknown_vg_1g_port;
6553
6554 /* fallthru */
6555 case 0x22:
6556 val = (phy_encode(PORT_TYPE_10G, 0) |
6557 phy_encode(PORT_TYPE_10G, 1) |
6558 phy_encode(PORT_TYPE_1G, 2) |
6559 phy_encode(PORT_TYPE_1G, 3));
6560 break;
6561
6562 case 0x20:
6563 val = (phy_encode(PORT_TYPE_10G, 0) |
6564 phy_encode(PORT_TYPE_10G, 1));
6565 break;
6566
6567 case 0x10:
6568 val = phy_encode(PORT_TYPE_10G, np->port);
6569 break;
6570
6571 case 0x14:
6572 if (lowest_1g == 10)
6573 parent->plat_type = PLAT_TYPE_VF_P0;
6574 else if (lowest_1g == 26)
6575 parent->plat_type = PLAT_TYPE_VF_P1;
6576 else
6577 goto unknown_vg_1g_port;
6578
6579 /* fallthru */
6580 case 0x13:
6581 if ((lowest_10g & 0x7) == 0)
6582 val = (phy_encode(PORT_TYPE_10G, 0) |
6583 phy_encode(PORT_TYPE_1G, 1) |
6584 phy_encode(PORT_TYPE_1G, 2) |
6585 phy_encode(PORT_TYPE_1G, 3));
6586 else
6587 val = (phy_encode(PORT_TYPE_1G, 0) |
6588 phy_encode(PORT_TYPE_10G, 1) |
6589 phy_encode(PORT_TYPE_1G, 2) |
6590 phy_encode(PORT_TYPE_1G, 3));
6591 break;
6592
6593 case 0x04:
6594 if (lowest_1g == 10)
6595 parent->plat_type = PLAT_TYPE_VF_P0;
6596 else if (lowest_1g == 26)
6597 parent->plat_type = PLAT_TYPE_VF_P1;
6598 else
6599 goto unknown_vg_1g_port;
6600
6601 val = (phy_encode(PORT_TYPE_1G, 0) |
6602 phy_encode(PORT_TYPE_1G, 1) |
6603 phy_encode(PORT_TYPE_1G, 2) |
6604 phy_encode(PORT_TYPE_1G, 3));
6605 break;
6606
6607 default:
6608 printk(KERN_ERR PFX "Unsupported port config "
6609 "10G[%d] 1G[%d]\n",
6610 num_10g, num_1g);
6611 return -EINVAL;
6612 }
6613
6614 parent->port_phy = val;
6615
6616 if (parent->plat_type == PLAT_TYPE_NIU)
6617 niu_n2_divide_channels(parent);
6618 else
6619 niu_divide_channels(parent, num_10g, num_1g);
6620
6621 niu_divide_rdc_groups(parent, num_10g, num_1g);
6622
6623 return 0;
6624
6625unknown_vg_1g_port:
6626 printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
6627 lowest_1g);
6628 return -EINVAL;
6629}
6630
6631static int __devinit niu_probe_ports(struct niu *np)
6632{
6633 struct niu_parent *parent = np->parent;
6634 int err, i;
6635
6636 niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
6637 parent->port_phy);
6638
6639 if (parent->port_phy == PORT_PHY_UNKNOWN) {
6640 err = walk_phys(np, parent);
6641 if (err)
6642 return err;
6643
6644 niu_set_ldg_timer_res(np, 2);
6645 for (i = 0; i <= LDN_MAX; i++)
6646 niu_ldn_irq_enable(np, i, 0);
6647 }
6648
6649 if (parent->port_phy == PORT_PHY_INVALID)
6650 return -EINVAL;
6651
6652 return 0;
6653}
6654
6655static int __devinit niu_classifier_swstate_init(struct niu *np)
6656{
6657 struct niu_classifier *cp = &np->clas;
6658
6659 niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
6660 np->parent->tcam_num_entries);
6661
6662 cp->tcam_index = (u16) np->port;
6663 cp->h1_init = 0xffffffff;
6664 cp->h2_init = 0xffff;
6665
6666 return fflp_early_init(np);
6667}
6668
6669static void __devinit niu_link_config_init(struct niu *np)
6670{
6671 struct niu_link_config *lp = &np->link_config;
6672
6673 lp->advertising = (ADVERTISED_10baseT_Half |
6674 ADVERTISED_10baseT_Full |
6675 ADVERTISED_100baseT_Half |
6676 ADVERTISED_100baseT_Full |
6677 ADVERTISED_1000baseT_Half |
6678 ADVERTISED_1000baseT_Full |
6679 ADVERTISED_10000baseT_Full |
6680 ADVERTISED_Autoneg);
6681 lp->speed = lp->active_speed = SPEED_INVALID;
6682 lp->duplex = lp->active_duplex = DUPLEX_INVALID;
6683#if 0
6684 lp->loopback_mode = LOOPBACK_MAC;
6685 lp->active_speed = SPEED_10000;
6686 lp->active_duplex = DUPLEX_FULL;
6687#else
6688 lp->loopback_mode = LOOPBACK_DISABLED;
6689#endif
6690}
6691
6692static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
6693{
6694 switch (np->port) {
6695 case 0:
6696 np->mac_regs = np->regs + XMAC_PORT0_OFF;
6697 np->ipp_off = 0x00000;
6698 np->pcs_off = 0x04000;
6699 np->xpcs_off = 0x02000;
6700 break;
6701
6702 case 1:
6703 np->mac_regs = np->regs + XMAC_PORT1_OFF;
6704 np->ipp_off = 0x08000;
6705 np->pcs_off = 0x0a000;
6706 np->xpcs_off = 0x08000;
6707 break;
6708
6709 case 2:
6710 np->mac_regs = np->regs + BMAC_PORT2_OFF;
6711 np->ipp_off = 0x04000;
6712 np->pcs_off = 0x0e000;
6713 np->xpcs_off = ~0UL;
6714 break;
6715
6716 case 3:
6717 np->mac_regs = np->regs + BMAC_PORT3_OFF;
6718 np->ipp_off = 0x0c000;
6719 np->pcs_off = 0x12000;
6720 np->xpcs_off = ~0UL;
6721 break;
6722
6723 default:
6724 dev_err(np->device, PFX "Port %u is invalid, cannot "
6725 "compute MAC block offset.\n", np->port);
6726 return -EINVAL;
6727 }
6728
6729 return 0;
6730}
6731
6732static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
6733{
6734 struct msix_entry msi_vec[NIU_NUM_LDG];
6735 struct niu_parent *parent = np->parent;
6736 struct pci_dev *pdev = np->pdev;
6737 int i, num_irqs, err;
6738 u8 first_ldg;
6739
6740 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
6741 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
6742 ldg_num_map[i] = first_ldg + i;
6743
6744 num_irqs = (parent->rxchan_per_port[np->port] +
6745 parent->txchan_per_port[np->port] +
6746 (np->port == 0 ? 3 : 1));
6747 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
6748
6749retry:
6750 for (i = 0; i < num_irqs; i++) {
6751 msi_vec[i].vector = 0;
6752 msi_vec[i].entry = i;
6753 }
6754
6755 err = pci_enable_msix(pdev, msi_vec, num_irqs);
6756 if (err < 0) {
6757 np->flags &= ~NIU_FLAGS_MSIX;
6758 return;
6759 }
6760 if (err > 0) {
6761 num_irqs = err;
6762 goto retry;
6763 }
6764
6765 np->flags |= NIU_FLAGS_MSIX;
6766 for (i = 0; i < num_irqs; i++)
6767 np->ldg[i].irq = msi_vec[i].vector;
6768 np->num_ldg = num_irqs;
6769}
6770
6771static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
6772{
6773#ifdef CONFIG_SPARC64
6774 struct of_device *op = np->op;
6775 const u32 *int_prop;
6776 int i;
6777
6778 int_prop = of_get_property(op->node, "interrupts", NULL);
6779 if (!int_prop)
6780 return -ENODEV;
6781
6782 for (i = 0; i < op->num_irqs; i++) {
6783 ldg_num_map[i] = int_prop[i];
6784 np->ldg[i].irq = op->irqs[i];
6785 }
6786
6787 np->num_ldg = op->num_irqs;
6788
6789 return 0;
6790#else
6791 return -EINVAL;
6792#endif
6793}
6794
6795static int __devinit niu_ldg_init(struct niu *np)
6796{
6797 struct niu_parent *parent = np->parent;
6798 u8 ldg_num_map[NIU_NUM_LDG];
6799 int first_chan, num_chan;
6800 int i, err, ldg_rotor;
6801 u8 port;
6802
6803 np->num_ldg = 1;
6804 np->ldg[0].irq = np->dev->irq;
6805 if (parent->plat_type == PLAT_TYPE_NIU) {
6806 err = niu_n2_irq_init(np, ldg_num_map);
6807 if (err)
6808 return err;
6809 } else
6810 niu_try_msix(np, ldg_num_map);
6811
6812 port = np->port;
6813 for (i = 0; i < np->num_ldg; i++) {
6814 struct niu_ldg *lp = &np->ldg[i];
6815
6816 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
6817
6818 lp->np = np;
6819 lp->ldg_num = ldg_num_map[i];
6820 lp->timer = 2; /* XXX */
6821
6822 /* On N2 NIU the firmware has setup the SID mappings so they go
6823 * to the correct values that will route the LDG to the proper
6824 * interrupt in the NCU interrupt table.
6825 */
6826 if (np->parent->plat_type != PLAT_TYPE_NIU) {
6827 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
6828 if (err)
6829 return err;
6830 }
6831 }
6832
6833 /* We adopt the LDG assignment ordering used by the N2 NIU
6834 * 'interrupt' properties because that simplifies a lot of
6835 * things. This ordering is:
6836 *
6837 * MAC
6838 * MIF (if port zero)
6839 * SYSERR (if port zero)
6840 * RX channels
6841 * TX channels
6842 */
6843
6844 ldg_rotor = 0;
6845
6846 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
6847 LDN_MAC(port));
6848 if (err)
6849 return err;
6850
6851 ldg_rotor++;
6852 if (ldg_rotor == np->num_ldg)
6853 ldg_rotor = 0;
6854
6855 if (port == 0) {
6856 err = niu_ldg_assign_ldn(np, parent,
6857 ldg_num_map[ldg_rotor],
6858 LDN_MIF);
6859 if (err)
6860 return err;
6861
6862 ldg_rotor++;
6863 if (ldg_rotor == np->num_ldg)
6864 ldg_rotor = 0;
6865
6866 err = niu_ldg_assign_ldn(np, parent,
6867 ldg_num_map[ldg_rotor],
6868 LDN_DEVICE_ERROR);
6869 if (err)
6870 return err;
6871
6872 ldg_rotor++;
6873 if (ldg_rotor == np->num_ldg)
6874 ldg_rotor = 0;
6875
6876 }
6877
6878 first_chan = 0;
6879 for (i = 0; i < port; i++)
6880 first_chan += parent->rxchan_per_port[port];
6881 num_chan = parent->rxchan_per_port[port];
6882
6883 for (i = first_chan; i < (first_chan + num_chan); i++) {
6884 err = niu_ldg_assign_ldn(np, parent,
6885 ldg_num_map[ldg_rotor],
6886 LDN_RXDMA(i));
6887 if (err)
6888 return err;
6889 ldg_rotor++;
6890 if (ldg_rotor == np->num_ldg)
6891 ldg_rotor = 0;
6892 }
6893
6894 first_chan = 0;
6895 for (i = 0; i < port; i++)
6896 first_chan += parent->txchan_per_port[port];
6897 num_chan = parent->txchan_per_port[port];
6898 for (i = first_chan; i < (first_chan + num_chan); i++) {
6899 err = niu_ldg_assign_ldn(np, parent,
6900 ldg_num_map[ldg_rotor],
6901 LDN_TXDMA(i));
6902 if (err)
6903 return err;
6904 ldg_rotor++;
6905 if (ldg_rotor == np->num_ldg)
6906 ldg_rotor = 0;
6907 }
6908
6909 return 0;
6910}
6911
6912static void __devexit niu_ldg_free(struct niu *np)
6913{
6914 if (np->flags & NIU_FLAGS_MSIX)
6915 pci_disable_msix(np->pdev);
6916}
6917
6918static int __devinit niu_get_of_props(struct niu *np)
6919{
6920#ifdef CONFIG_SPARC64
6921 struct net_device *dev = np->dev;
6922 struct device_node *dp;
6923 const char *phy_type;
6924 const u8 *mac_addr;
6925 int prop_len;
6926
6927 if (np->parent->plat_type == PLAT_TYPE_NIU)
6928 dp = np->op->node;
6929 else
6930 dp = pci_device_to_OF_node(np->pdev);
6931
6932 phy_type = of_get_property(dp, "phy-type", &prop_len);
6933 if (!phy_type) {
6934 dev_err(np->device, PFX "%s: OF node lacks "
6935 "phy-type property\n",
6936 dp->full_name);
6937 return -EINVAL;
6938 }
6939
6940 if (!strcmp(phy_type, "none"))
6941 return -ENODEV;
6942
6943 strcpy(np->vpd.phy_type, phy_type);
6944
6945 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
6946 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
6947 dp->full_name, np->vpd.phy_type);
6948 return -EINVAL;
6949 }
6950
6951 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
6952 if (!mac_addr) {
6953 dev_err(np->device, PFX "%s: OF node lacks "
6954 "local-mac-address property\n",
6955 dp->full_name);
6956 return -EINVAL;
6957 }
6958 if (prop_len != dev->addr_len) {
6959 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
6960 "is wrong.\n",
6961 dp->full_name, prop_len);
6962 }
6963 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
6964 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
6965 int i;
6966
6967 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
6968 dp->full_name);
6969 dev_err(np->device, PFX "%s: [ \n",
6970 dp->full_name);
6971 for (i = 0; i < 6; i++)
6972 printk("%02x ", dev->perm_addr[i]);
6973 printk("]\n");
6974 return -EINVAL;
6975 }
6976
6977 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6978
6979 return 0;
6980#else
6981 return -EINVAL;
6982#endif
6983}
6984
6985static int __devinit niu_get_invariants(struct niu *np)
6986{
6987 int err, have_props;
6988 u32 offset;
6989
6990 err = niu_get_of_props(np);
6991 if (err == -ENODEV)
6992 return err;
6993
6994 have_props = !err;
6995
6996 err = niu_get_and_validate_port(np);
6997 if (err)
6998 return err;
6999
7000 err = niu_init_mac_ipp_pcs_base(np);
7001 if (err)
7002 return err;
7003
7004 if (!have_props) {
7005 if (np->parent->plat_type == PLAT_TYPE_NIU)
7006 return -EINVAL;
7007
7008 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
7009 offset = niu_pci_vpd_offset(np);
7010 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
7011 offset);
7012 if (offset)
7013 niu_pci_vpd_fetch(np, offset);
7014 nw64(ESPC_PIO_EN, 0);
7015
7016 if (np->flags & NIU_FLAGS_VPD_VALID)
7017 niu_pci_vpd_validate(np);
7018
7019 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7020 err = niu_pci_probe_sprom(np);
7021 if (err)
7022 return err;
7023 }
7024 }
7025
7026 err = niu_probe_ports(np);
7027 if (err)
7028 return err;
7029
7030 niu_ldg_init(np);
7031
7032 niu_classifier_swstate_init(np);
7033 niu_link_config_init(np);
7034
7035 err = niu_determine_phy_disposition(np);
7036 if (!err)
7037 err = niu_init_link(np);
7038
7039 return err;
7040}
7041
7042static LIST_HEAD(niu_parent_list);
7043static DEFINE_MUTEX(niu_parent_lock);
7044static int niu_parent_index;
7045
7046static ssize_t show_port_phy(struct device *dev,
7047 struct device_attribute *attr, char *buf)
7048{
7049 struct platform_device *plat_dev = to_platform_device(dev);
7050 struct niu_parent *p = plat_dev->dev.platform_data;
7051 u32 port_phy = p->port_phy;
7052 char *orig_buf = buf;
7053 int i;
7054
7055 if (port_phy == PORT_PHY_UNKNOWN ||
7056 port_phy == PORT_PHY_INVALID)
7057 return 0;
7058
7059 for (i = 0; i < p->num_ports; i++) {
7060 const char *type_str;
7061 int type;
7062
7063 type = phy_decode(port_phy, i);
7064 if (type == PORT_TYPE_10G)
7065 type_str = "10G";
7066 else
7067 type_str = "1G";
7068 buf += sprintf(buf,
7069 (i == 0) ? "%s" : " %s",
7070 type_str);
7071 }
7072 buf += sprintf(buf, "\n");
7073 return buf - orig_buf;
7074}
7075
7076static ssize_t show_plat_type(struct device *dev,
7077 struct device_attribute *attr, char *buf)
7078{
7079 struct platform_device *plat_dev = to_platform_device(dev);
7080 struct niu_parent *p = plat_dev->dev.platform_data;
7081 const char *type_str;
7082
7083 switch (p->plat_type) {
7084 case PLAT_TYPE_ATLAS:
7085 type_str = "atlas";
7086 break;
7087 case PLAT_TYPE_NIU:
7088 type_str = "niu";
7089 break;
7090 case PLAT_TYPE_VF_P0:
7091 type_str = "vf_p0";
7092 break;
7093 case PLAT_TYPE_VF_P1:
7094 type_str = "vf_p1";
7095 break;
7096 default:
7097 type_str = "unknown";
7098 break;
7099 }
7100
7101 return sprintf(buf, "%s\n", type_str);
7102}
7103
7104static ssize_t __show_chan_per_port(struct device *dev,
7105 struct device_attribute *attr, char *buf,
7106 int rx)
7107{
7108 struct platform_device *plat_dev = to_platform_device(dev);
7109 struct niu_parent *p = plat_dev->dev.platform_data;
7110 char *orig_buf = buf;
7111 u8 *arr;
7112 int i;
7113
7114 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
7115
7116 for (i = 0; i < p->num_ports; i++) {
7117 buf += sprintf(buf,
7118 (i == 0) ? "%d" : " %d",
7119 arr[i]);
7120 }
7121 buf += sprintf(buf, "\n");
7122
7123 return buf - orig_buf;
7124}
7125
7126static ssize_t show_rxchan_per_port(struct device *dev,
7127 struct device_attribute *attr, char *buf)
7128{
7129 return __show_chan_per_port(dev, attr, buf, 1);
7130}
7131
7132static ssize_t show_txchan_per_port(struct device *dev,
7133 struct device_attribute *attr, char *buf)
7134{
7135 return __show_chan_per_port(dev, attr, buf, 1);
7136}
7137
7138static ssize_t show_num_ports(struct device *dev,
7139 struct device_attribute *attr, char *buf)
7140{
7141 struct platform_device *plat_dev = to_platform_device(dev);
7142 struct niu_parent *p = plat_dev->dev.platform_data;
7143
7144 return sprintf(buf, "%d\n", p->num_ports);
7145}
7146
7147static struct device_attribute niu_parent_attributes[] = {
7148 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
7149 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
7150 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
7151 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
7152 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
7153 {}
7154};
7155
7156static struct niu_parent * __devinit niu_new_parent(struct niu *np,
7157 union niu_parent_id *id,
7158 u8 ptype)
7159{
7160 struct platform_device *plat_dev;
7161 struct niu_parent *p;
7162 int i;
7163
7164 niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
7165
7166 plat_dev = platform_device_register_simple("niu", niu_parent_index,
7167 NULL, 0);
7168 if (!plat_dev)
7169 return NULL;
7170
7171 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
7172 int err = device_create_file(&plat_dev->dev,
7173 &niu_parent_attributes[i]);
7174 if (err)
7175 goto fail_unregister;
7176 }
7177
7178 p = kzalloc(sizeof(*p), GFP_KERNEL);
7179 if (!p)
7180 goto fail_unregister;
7181
7182 p->index = niu_parent_index++;
7183
7184 plat_dev->dev.platform_data = p;
7185 p->plat_dev = plat_dev;
7186
7187 memcpy(&p->id, id, sizeof(*id));
7188 p->plat_type = ptype;
7189 INIT_LIST_HEAD(&p->list);
7190 atomic_set(&p->refcnt, 0);
7191 list_add(&p->list, &niu_parent_list);
7192 spin_lock_init(&p->lock);
7193
7194 p->rxdma_clock_divider = 7500;
7195
7196 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
7197 if (p->plat_type == PLAT_TYPE_NIU)
7198 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
7199
7200 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
7201 int index = i - CLASS_CODE_USER_PROG1;
7202
7203 p->tcam_key[index] = TCAM_KEY_TSEL;
7204 p->flow_key[index] = (FLOW_KEY_IPSA |
7205 FLOW_KEY_IPDA |
7206 FLOW_KEY_PROTO |
7207 (FLOW_KEY_L4_BYTE12 <<
7208 FLOW_KEY_L4_0_SHIFT) |
7209 (FLOW_KEY_L4_BYTE12 <<
7210 FLOW_KEY_L4_1_SHIFT));
7211 }
7212
7213 for (i = 0; i < LDN_MAX + 1; i++)
7214 p->ldg_map[i] = LDG_INVALID;
7215
7216 return p;
7217
7218fail_unregister:
7219 platform_device_unregister(plat_dev);
7220 return NULL;
7221}
7222
7223static struct niu_parent * __devinit niu_get_parent(struct niu *np,
7224 union niu_parent_id *id,
7225 u8 ptype)
7226{
7227 struct niu_parent *p, *tmp;
7228 int port = np->port;
7229
7230 niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
7231 ptype, port);
7232
7233 mutex_lock(&niu_parent_lock);
7234 p = NULL;
7235 list_for_each_entry(tmp, &niu_parent_list, list) {
7236 if (!memcmp(id, &tmp->id, sizeof(*id))) {
7237 p = tmp;
7238 break;
7239 }
7240 }
7241 if (!p)
7242 p = niu_new_parent(np, id, ptype);
7243
7244 if (p) {
7245 char port_name[6];
7246 int err;
7247
7248 sprintf(port_name, "port%d", port);
7249 err = sysfs_create_link(&p->plat_dev->dev.kobj,
7250 &np->device->kobj,
7251 port_name);
7252 if (!err) {
7253 p->ports[port] = np;
7254 atomic_inc(&p->refcnt);
7255 }
7256 }
7257 mutex_unlock(&niu_parent_lock);
7258
7259 return p;
7260}
7261
7262static void niu_put_parent(struct niu *np)
7263{
7264 struct niu_parent *p = np->parent;
7265 u8 port = np->port;
7266 char port_name[6];
7267
7268 BUG_ON(!p || p->ports[port] != np);
7269
7270 niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
7271
7272 sprintf(port_name, "port%d", port);
7273
7274 mutex_lock(&niu_parent_lock);
7275
7276 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
7277
7278 p->ports[port] = NULL;
7279 np->parent = NULL;
7280
7281 if (atomic_dec_and_test(&p->refcnt)) {
7282 list_del(&p->list);
7283 platform_device_unregister(p->plat_dev);
7284 }
7285
7286 mutex_unlock(&niu_parent_lock);
7287}
7288
7289static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
7290 u64 *handle, gfp_t flag)
7291{
7292 dma_addr_t dh;
7293 void *ret;
7294
7295 ret = dma_alloc_coherent(dev, size, &dh, flag);
7296 if (ret)
7297 *handle = dh;
7298 return ret;
7299}
7300
7301static void niu_pci_free_coherent(struct device *dev, size_t size,
7302 void *cpu_addr, u64 handle)
7303{
7304 dma_free_coherent(dev, size, cpu_addr, handle);
7305}
7306
7307static u64 niu_pci_map_page(struct device *dev, struct page *page,
7308 unsigned long offset, size_t size,
7309 enum dma_data_direction direction)
7310{
7311 return dma_map_page(dev, page, offset, size, direction);
7312}
7313
7314static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
7315 size_t size, enum dma_data_direction direction)
7316{
7317 return dma_unmap_page(dev, dma_address, size, direction);
7318}
7319
7320static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
7321 size_t size,
7322 enum dma_data_direction direction)
7323{
7324 return dma_map_single(dev, cpu_addr, size, direction);
7325}
7326
7327static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
7328 size_t size,
7329 enum dma_data_direction direction)
7330{
7331 dma_unmap_single(dev, dma_address, size, direction);
7332}
7333
7334static const struct niu_ops niu_pci_ops = {
7335 .alloc_coherent = niu_pci_alloc_coherent,
7336 .free_coherent = niu_pci_free_coherent,
7337 .map_page = niu_pci_map_page,
7338 .unmap_page = niu_pci_unmap_page,
7339 .map_single = niu_pci_map_single,
7340 .unmap_single = niu_pci_unmap_single,
7341};
7342
7343static void __devinit niu_driver_version(void)
7344{
7345 static int niu_version_printed;
7346
7347 if (niu_version_printed++ == 0)
7348 pr_info("%s", version);
7349}
7350
7351static struct net_device * __devinit niu_alloc_and_init(
7352 struct device *gen_dev, struct pci_dev *pdev,
7353 struct of_device *op, const struct niu_ops *ops,
7354 u8 port)
7355{
7356 struct net_device *dev = alloc_etherdev(sizeof(struct niu));
7357 struct niu *np;
7358
7359 if (!dev) {
7360 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
7361 return NULL;
7362 }
7363
7364 SET_NETDEV_DEV(dev, gen_dev);
7365
7366 np = netdev_priv(dev);
7367 np->dev = dev;
7368 np->pdev = pdev;
7369 np->op = op;
7370 np->device = gen_dev;
7371 np->ops = ops;
7372
7373 np->msg_enable = niu_debug;
7374
7375 spin_lock_init(&np->lock);
7376 INIT_WORK(&np->reset_task, niu_reset_task);
7377
7378 np->port = port;
7379
7380 return dev;
7381}
7382
7383static void __devinit niu_assign_netdev_ops(struct net_device *dev)
7384{
7385 dev->open = niu_open;
7386 dev->stop = niu_close;
7387 dev->get_stats = niu_get_stats;
7388 dev->set_multicast_list = niu_set_rx_mode;
7389 dev->set_mac_address = niu_set_mac_addr;
7390 dev->do_ioctl = niu_ioctl;
7391 dev->tx_timeout = niu_tx_timeout;
7392 dev->hard_start_xmit = niu_start_xmit;
7393 dev->ethtool_ops = &niu_ethtool_ops;
7394 dev->watchdog_timeo = NIU_TX_TIMEOUT;
7395 dev->change_mtu = niu_change_mtu;
7396}
7397
7398static void __devinit niu_device_announce(struct niu *np)
7399{
7400 struct net_device *dev = np->dev;
7401 int i;
7402
7403 pr_info("%s: NIU Ethernet ", dev->name);
7404 for (i = 0; i < 6; i++)
7405 printk("%2.2x%c", dev->dev_addr[i],
7406 i == 5 ? '\n' : ':');
7407
7408 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
7409 dev->name,
7410 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
7411 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
7412 (np->flags & NIU_FLAGS_FIBER ? "FIBER" : "COPPER"),
7413 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
7414 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
7415 np->vpd.phy_type);
7416}
7417
7418static int __devinit niu_pci_init_one(struct pci_dev *pdev,
7419 const struct pci_device_id *ent)
7420{
7421 unsigned long niureg_base, niureg_len;
7422 union niu_parent_id parent_id;
7423 struct net_device *dev;
7424 struct niu *np;
7425 int err, pos;
7426 u64 dma_mask;
7427 u16 val16;
7428
7429 niu_driver_version();
7430
7431 err = pci_enable_device(pdev);
7432 if (err) {
7433 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
7434 "aborting.\n");
7435 return err;
7436 }
7437
7438 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
7439 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
7440 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
7441 "base addresses, aborting.\n");
7442 err = -ENODEV;
7443 goto err_out_disable_pdev;
7444 }
7445
7446 err = pci_request_regions(pdev, DRV_MODULE_NAME);
7447 if (err) {
7448 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
7449 "aborting.\n");
7450 goto err_out_disable_pdev;
7451 }
7452
7453 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
7454 if (pos <= 0) {
7455 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
7456 "aborting.\n");
7457 goto err_out_free_res;
7458 }
7459
7460 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
7461 &niu_pci_ops, PCI_FUNC(pdev->devfn));
7462 if (!dev) {
7463 err = -ENOMEM;
7464 goto err_out_free_res;
7465 }
7466 np = netdev_priv(dev);
7467
7468 memset(&parent_id, 0, sizeof(parent_id));
7469 parent_id.pci.domain = pci_domain_nr(pdev->bus);
7470 parent_id.pci.bus = pdev->bus->number;
7471 parent_id.pci.device = PCI_SLOT(pdev->devfn);
7472
7473 np->parent = niu_get_parent(np, &parent_id,
7474 PLAT_TYPE_ATLAS);
7475 if (!np->parent) {
7476 err = -ENOMEM;
7477 goto err_out_free_dev;
7478 }
7479
7480 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
7481 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
7482 val16 |= (PCI_EXP_DEVCTL_CERE |
7483 PCI_EXP_DEVCTL_NFERE |
7484 PCI_EXP_DEVCTL_FERE |
7485 PCI_EXP_DEVCTL_URRE |
7486 PCI_EXP_DEVCTL_RELAX_EN);
7487 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
7488
7489 dma_mask = DMA_44BIT_MASK;
7490 err = pci_set_dma_mask(pdev, dma_mask);
7491 if (!err) {
7492 dev->features |= NETIF_F_HIGHDMA;
7493 err = pci_set_consistent_dma_mask(pdev, dma_mask);
7494 if (err) {
7495 dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
7496 "DMA for consistent allocations, "
7497 "aborting.\n");
7498 goto err_out_release_parent;
7499 }
7500 }
7501 if (err || dma_mask == DMA_32BIT_MASK) {
7502 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
7503 if (err) {
7504 dev_err(&pdev->dev, PFX "No usable DMA configuration, "
7505 "aborting.\n");
7506 goto err_out_release_parent;
7507 }
7508 }
7509
7510 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
7511
7512 niureg_base = pci_resource_start(pdev, 0);
7513 niureg_len = pci_resource_len(pdev, 0);
7514
7515 np->regs = ioremap_nocache(niureg_base, niureg_len);
7516 if (!np->regs) {
7517 dev_err(&pdev->dev, PFX "Cannot map device registers, "
7518 "aborting.\n");
7519 err = -ENOMEM;
7520 goto err_out_release_parent;
7521 }
7522
7523 pci_set_master(pdev);
7524 pci_save_state(pdev);
7525
7526 dev->irq = pdev->irq;
7527
7528 niu_assign_netdev_ops(dev);
7529
7530 err = niu_get_invariants(np);
7531 if (err) {
7532 if (err != -ENODEV)
7533 dev_err(&pdev->dev, PFX "Problem fetching invariants "
7534 "of chip, aborting.\n");
7535 goto err_out_iounmap;
7536 }
7537
7538 err = register_netdev(dev);
7539 if (err) {
7540 dev_err(&pdev->dev, PFX "Cannot register net device, "
7541 "aborting.\n");
7542 goto err_out_iounmap;
7543 }
7544
7545 pci_set_drvdata(pdev, dev);
7546
7547 niu_device_announce(np);
7548
7549 return 0;
7550
7551err_out_iounmap:
7552 if (np->regs) {
7553 iounmap(np->regs);
7554 np->regs = NULL;
7555 }
7556
7557err_out_release_parent:
7558 niu_put_parent(np);
7559
7560err_out_free_dev:
7561 free_netdev(dev);
7562
7563err_out_free_res:
7564 pci_release_regions(pdev);
7565
7566err_out_disable_pdev:
7567 pci_disable_device(pdev);
7568 pci_set_drvdata(pdev, NULL);
7569
7570 return err;
7571}
7572
7573static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
7574{
7575 struct net_device *dev = pci_get_drvdata(pdev);
7576
7577 if (dev) {
7578 struct niu *np = netdev_priv(dev);
7579
7580 unregister_netdev(dev);
7581 if (np->regs) {
7582 iounmap(np->regs);
7583 np->regs = NULL;
7584 }
7585
7586 niu_ldg_free(np);
7587
7588 niu_put_parent(np);
7589
7590 free_netdev(dev);
7591 pci_release_regions(pdev);
7592 pci_disable_device(pdev);
7593 pci_set_drvdata(pdev, NULL);
7594 }
7595}
7596
7597static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
7598{
7599 struct net_device *dev = pci_get_drvdata(pdev);
7600 struct niu *np = netdev_priv(dev);
7601 unsigned long flags;
7602
7603 if (!netif_running(dev))
7604 return 0;
7605
7606 flush_scheduled_work();
7607 niu_netif_stop(np);
7608
7609 del_timer_sync(&np->timer);
7610
7611 spin_lock_irqsave(&np->lock, flags);
7612 niu_enable_interrupts(np, 0);
7613 spin_unlock_irqrestore(&np->lock, flags);
7614
7615 netif_device_detach(dev);
7616
7617 spin_lock_irqsave(&np->lock, flags);
7618 niu_stop_hw(np);
7619 spin_unlock_irqrestore(&np->lock, flags);
7620
7621 pci_save_state(pdev);
7622
7623 return 0;
7624}
7625
7626static int niu_resume(struct pci_dev *pdev)
7627{
7628 struct net_device *dev = pci_get_drvdata(pdev);
7629 struct niu *np = netdev_priv(dev);
7630 unsigned long flags;
7631 int err;
7632
7633 if (!netif_running(dev))
7634 return 0;
7635
7636 pci_restore_state(pdev);
7637
7638 netif_device_attach(dev);
7639
7640 spin_lock_irqsave(&np->lock, flags);
7641
7642 err = niu_init_hw(np);
7643 if (!err) {
7644 np->timer.expires = jiffies + HZ;
7645 add_timer(&np->timer);
7646 niu_netif_start(np);
7647 }
7648
7649 spin_unlock_irqrestore(&np->lock, flags);
7650
7651 return err;
7652}
7653
7654static struct pci_driver niu_pci_driver = {
7655 .name = DRV_MODULE_NAME,
7656 .id_table = niu_pci_tbl,
7657 .probe = niu_pci_init_one,
7658 .remove = __devexit_p(niu_pci_remove_one),
7659 .suspend = niu_suspend,
7660 .resume = niu_resume,
7661};
7662
7663#ifdef CONFIG_SPARC64
7664static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
7665 u64 *dma_addr, gfp_t flag)
7666{
7667 unsigned long order = get_order(size);
7668 unsigned long page = __get_free_pages(flag, order);
7669
7670 if (page == 0UL)
7671 return NULL;
7672 memset((char *)page, 0, PAGE_SIZE << order);
7673 *dma_addr = __pa(page);
7674
7675 return (void *) page;
7676}
7677
7678static void niu_phys_free_coherent(struct device *dev, size_t size,
7679 void *cpu_addr, u64 handle)
7680{
7681 unsigned long order = get_order(size);
7682
7683 free_pages((unsigned long) cpu_addr, order);
7684}
7685
7686static u64 niu_phys_map_page(struct device *dev, struct page *page,
7687 unsigned long offset, size_t size,
7688 enum dma_data_direction direction)
7689{
7690 return page_to_phys(page) + offset;
7691}
7692
7693static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
7694 size_t size, enum dma_data_direction direction)
7695{
7696 /* Nothing to do. */
7697}
7698
7699static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
7700 size_t size,
7701 enum dma_data_direction direction)
7702{
7703 return __pa(cpu_addr);
7704}
7705
7706static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
7707 size_t size,
7708 enum dma_data_direction direction)
7709{
7710 /* Nothing to do. */
7711}
7712
7713static const struct niu_ops niu_phys_ops = {
7714 .alloc_coherent = niu_phys_alloc_coherent,
7715 .free_coherent = niu_phys_free_coherent,
7716 .map_page = niu_phys_map_page,
7717 .unmap_page = niu_phys_unmap_page,
7718 .map_single = niu_phys_map_single,
7719 .unmap_single = niu_phys_unmap_single,
7720};
7721
7722static unsigned long res_size(struct resource *r)
7723{
7724 return r->end - r->start + 1UL;
7725}
7726
7727static int __devinit niu_of_probe(struct of_device *op,
7728 const struct of_device_id *match)
7729{
7730 union niu_parent_id parent_id;
7731 struct net_device *dev;
7732 struct niu *np;
7733 const u32 *reg;
7734 int err;
7735
7736 niu_driver_version();
7737
7738 reg = of_get_property(op->node, "reg", NULL);
7739 if (!reg) {
7740 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
7741 op->node->full_name);
7742 return -ENODEV;
7743 }
7744
7745 dev = niu_alloc_and_init(&op->dev, NULL, op,
7746 &niu_phys_ops, reg[0] & 0x1);
7747 if (!dev) {
7748 err = -ENOMEM;
7749 goto err_out;
7750 }
7751 np = netdev_priv(dev);
7752
7753 memset(&parent_id, 0, sizeof(parent_id));
7754 parent_id.of = of_get_parent(op->node);
7755
7756 np->parent = niu_get_parent(np, &parent_id,
7757 PLAT_TYPE_NIU);
7758 if (!np->parent) {
7759 err = -ENOMEM;
7760 goto err_out_free_dev;
7761 }
7762
7763 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
7764
7765 np->regs = of_ioremap(&op->resource[1], 0,
7766 res_size(&op->resource[1]),
7767 "niu regs");
7768 if (!np->regs) {
7769 dev_err(&op->dev, PFX "Cannot map device registers, "
7770 "aborting.\n");
7771 err = -ENOMEM;
7772 goto err_out_release_parent;
7773 }
7774
7775 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
7776 res_size(&op->resource[2]),
7777 "niu vregs-1");
7778 if (!np->vir_regs_1) {
7779 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
7780 "aborting.\n");
7781 err = -ENOMEM;
7782 goto err_out_iounmap;
7783 }
7784
7785 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
7786 res_size(&op->resource[3]),
7787 "niu vregs-2");
7788 if (!np->vir_regs_2) {
7789 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
7790 "aborting.\n");
7791 err = -ENOMEM;
7792 goto err_out_iounmap;
7793 }
7794
7795 niu_assign_netdev_ops(dev);
7796
7797 err = niu_get_invariants(np);
7798 if (err) {
7799 if (err != -ENODEV)
7800 dev_err(&op->dev, PFX "Problem fetching invariants "
7801 "of chip, aborting.\n");
7802 goto err_out_iounmap;
7803 }
7804
7805 err = register_netdev(dev);
7806 if (err) {
7807 dev_err(&op->dev, PFX "Cannot register net device, "
7808 "aborting.\n");
7809 goto err_out_iounmap;
7810 }
7811
7812 dev_set_drvdata(&op->dev, dev);
7813
7814 niu_device_announce(np);
7815
7816 return 0;
7817
7818err_out_iounmap:
7819 if (np->vir_regs_1) {
7820 of_iounmap(&op->resource[2], np->vir_regs_1,
7821 res_size(&op->resource[2]));
7822 np->vir_regs_1 = NULL;
7823 }
7824
7825 if (np->vir_regs_2) {
7826 of_iounmap(&op->resource[3], np->vir_regs_2,
7827 res_size(&op->resource[3]));
7828 np->vir_regs_2 = NULL;
7829 }
7830
7831 if (np->regs) {
7832 of_iounmap(&op->resource[1], np->regs,
7833 res_size(&op->resource[1]));
7834 np->regs = NULL;
7835 }
7836
7837err_out_release_parent:
7838 niu_put_parent(np);
7839
7840err_out_free_dev:
7841 free_netdev(dev);
7842
7843err_out:
7844 return err;
7845}
7846
7847static int __devexit niu_of_remove(struct of_device *op)
7848{
7849 struct net_device *dev = dev_get_drvdata(&op->dev);
7850
7851 if (dev) {
7852 struct niu *np = netdev_priv(dev);
7853
7854 unregister_netdev(dev);
7855
7856 if (np->vir_regs_1) {
7857 of_iounmap(&op->resource[2], np->vir_regs_1,
7858 res_size(&op->resource[2]));
7859 np->vir_regs_1 = NULL;
7860 }
7861
7862 if (np->vir_regs_2) {
7863 of_iounmap(&op->resource[3], np->vir_regs_2,
7864 res_size(&op->resource[3]));
7865 np->vir_regs_2 = NULL;
7866 }
7867
7868 if (np->regs) {
7869 of_iounmap(&op->resource[1], np->regs,
7870 res_size(&op->resource[1]));
7871 np->regs = NULL;
7872 }
7873
7874 niu_ldg_free(np);
7875
7876 niu_put_parent(np);
7877
7878 free_netdev(dev);
7879 dev_set_drvdata(&op->dev, NULL);
7880 }
7881 return 0;
7882}
7883
7884static struct of_device_id niu_match[] = {
7885 {
7886 .name = "network",
7887 .compatible = "SUNW,niusl",
7888 },
7889 {},
7890};
7891MODULE_DEVICE_TABLE(of, niu_match);
7892
7893static struct of_platform_driver niu_of_driver = {
7894 .name = "niu",
7895 .match_table = niu_match,
7896 .probe = niu_of_probe,
7897 .remove = __devexit_p(niu_of_remove),
7898};
7899
7900#endif /* CONFIG_SPARC64 */
7901
7902static int __init niu_init(void)
7903{
7904 int err = 0;
7905
7906 BUILD_BUG_ON((PAGE_SIZE < 4 * 1024) ||
7907 ((PAGE_SIZE > 32 * 1024) &&
7908 ((PAGE_SIZE % (32 * 1024)) != 0 &&
7909 (PAGE_SIZE % (16 * 1024)) != 0 &&
7910 (PAGE_SIZE % (8 * 1024)) != 0 &&
7911 (PAGE_SIZE % (4 * 1024)) != 0)));
7912
7913 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
7914
7915#ifdef CONFIG_SPARC64
7916 err = of_register_driver(&niu_of_driver, &of_bus_type);
7917#endif
7918
7919 if (!err) {
7920 err = pci_register_driver(&niu_pci_driver);
7921#ifdef CONFIG_SPARC64
7922 if (err)
7923 of_unregister_driver(&niu_of_driver);
7924#endif
7925 }
7926
7927 return err;
7928}
7929
7930static void __exit niu_exit(void)
7931{
7932 pci_unregister_driver(&niu_pci_driver);
7933#ifdef CONFIG_SPARC64
7934 of_unregister_driver(&niu_of_driver);
7935#endif
7936}
7937
7938module_init(niu_init);
7939module_exit(niu_exit);
diff --git a/drivers/net/niu.h b/drivers/net/niu.h
new file mode 100644
index 000000000000..10e3f111b6d5
--- /dev/null
+++ b/drivers/net/niu.h
@@ -0,0 +1,3222 @@
1/* niu.h: Definitions for Neptune ethernet driver.
2 *
3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef _NIU_H
7#define _NIU_H
8
9#define PIO 0x000000UL
10#define FZC_PIO 0x080000UL
11#define FZC_MAC 0x180000UL
12#define FZC_IPP 0x280000UL
13#define FFLP 0x300000UL
14#define FZC_FFLP 0x380000UL
15#define PIO_VADDR 0x400000UL
16#define ZCP 0x500000UL
17#define FZC_ZCP 0x580000UL
18#define DMC 0x600000UL
19#define FZC_DMC 0x680000UL
20#define TXC 0x700000UL
21#define FZC_TXC 0x780000UL
22#define PIO_LDSV 0x800000UL
23#define PIO_PIO_LDGIM 0x900000UL
24#define PIO_IMASK0 0xa00000UL
25#define PIO_IMASK1 0xb00000UL
26#define FZC_PROM 0xc80000UL
27#define FZC_PIM 0xd80000UL
28
29#define LDSV0(LDG) (PIO_LDSV + 0x00000UL + (LDG) * 0x2000UL)
30#define LDSV1(LDG) (PIO_LDSV + 0x00008UL + (LDG) * 0x2000UL)
31#define LDSV2(LDG) (PIO_LDSV + 0x00010UL + (LDG) * 0x2000UL)
32
33#define LDG_IMGMT(LDG) (PIO_LDSV + 0x00018UL + (LDG) * 0x2000UL)
34#define LDG_IMGMT_ARM 0x0000000080000000ULL
35#define LDG_IMGMT_TIMER 0x000000000000003fULL
36
37#define LD_IM0(IDX) (PIO_IMASK0 + 0x00000UL + (IDX) * 0x2000UL)
38#define LD_IM0_MASK 0x0000000000000003ULL
39
40#define LD_IM1(IDX) (PIO_IMASK1 + 0x00000UL + (IDX) * 0x2000UL)
41#define LD_IM1_MASK 0x0000000000000003ULL
42
43#define LDG_TIMER_RES (FZC_PIO + 0x00008UL)
44#define LDG_TIMER_RES_VAL 0x00000000000fffffULL
45
46#define DIRTY_TID_CTL (FZC_PIO + 0x00010UL)
47#define DIRTY_TID_CTL_NPTHRED 0x00000000003f0000ULL
48#define DIRTY_TID_CTL_RDTHRED 0x00000000000003f0ULL
49#define DIRTY_TID_CTL_DTIDCLR 0x0000000000000002ULL
50#define DIRTY_TID_CTL_DTIDENAB 0x0000000000000001ULL
51
52#define DIRTY_TID_STAT (FZC_PIO + 0x00018UL)
53#define DIRTY_TID_STAT_NPWSTAT 0x0000000000003f00ULL
54#define DIRTY_TID_STAT_RDSTAT 0x000000000000003fULL
55
56#define RST_CTL (FZC_PIO + 0x00038UL)
57#define RST_CTL_MAC_RST3 0x0000000000400000ULL
58#define RST_CTL_MAC_RST2 0x0000000000200000ULL
59#define RST_CTL_MAC_RST1 0x0000000000100000ULL
60#define RST_CTL_MAC_RST0 0x0000000000080000ULL
61#define RST_CTL_ACK_TO_EN 0x0000000000000800ULL
62#define RST_CTL_ACK_TO_VAL 0x00000000000007feULL
63
64#define SMX_CFIG_DAT (FZC_PIO + 0x00040UL)
65#define SMX_CFIG_DAT_RAS_DET 0x0000000080000000ULL
66#define SMX_CFIG_DAT_RAS_INJ 0x0000000040000000ULL
67#define SMX_CFIG_DAT_XACT_TO 0x000000000fffffffULL
68
69#define SMX_INT_STAT (FZC_PIO + 0x00048UL)
70#define SMX_INT_STAT_STAT 0x00000000ffffffffULL
71
72#define SMX_CTL (FZC_PIO + 0x00050UL)
73#define SMX_CTL_CTL 0x00000000ffffffffULL
74
75#define SMX_DBG_VEC (FZC_PIO + 0x00058UL)
76#define SMX_DBG_VEC_VEC 0x00000000ffffffffULL
77
78#define PIO_DBG_SEL (FZC_PIO + 0x00060UL)
79#define PIO_DBG_SEL_SEL 0x000000000000003fULL
80
81#define PIO_TRAIN_VEC (FZC_PIO + 0x00068UL)
82#define PIO_TRAIN_VEC_VEC 0x00000000ffffffffULL
83
84#define PIO_ARB_CTL (FZC_PIO + 0x00070UL)
85#define PIO_ARB_CTL_CTL 0x00000000ffffffffULL
86
87#define PIO_ARB_DBG_VEC (FZC_PIO + 0x00078UL)
88#define PIO_ARB_DBG_VEC_VEC 0x00000000ffffffffULL
89
90#define SYS_ERR_MASK (FZC_PIO + 0x00090UL)
91#define SYS_ERR_MASK_META2 0x0000000000000400ULL
92#define SYS_ERR_MASK_META1 0x0000000000000200ULL
93#define SYS_ERR_MASK_PEU 0x0000000000000100ULL
94#define SYS_ERR_MASK_TXC 0x0000000000000080ULL
95#define SYS_ERR_MASK_RDMC 0x0000000000000040ULL
96#define SYS_ERR_MASK_TDMC 0x0000000000000020ULL
97#define SYS_ERR_MASK_ZCP 0x0000000000000010ULL
98#define SYS_ERR_MASK_FFLP 0x0000000000000008ULL
99#define SYS_ERR_MASK_IPP 0x0000000000000004ULL
100#define SYS_ERR_MASK_MAC 0x0000000000000002ULL
101#define SYS_ERR_MASK_SMX 0x0000000000000001ULL
102
103#define SYS_ERR_STAT (FZC_PIO + 0x00098UL)
104#define SYS_ERR_STAT_META2 0x0000000000000400ULL
105#define SYS_ERR_STAT_META1 0x0000000000000200ULL
106#define SYS_ERR_STAT_PEU 0x0000000000000100ULL
107#define SYS_ERR_STAT_TXC 0x0000000000000080ULL
108#define SYS_ERR_STAT_RDMC 0x0000000000000040ULL
109#define SYS_ERR_STAT_TDMC 0x0000000000000020ULL
110#define SYS_ERR_STAT_ZCP 0x0000000000000010ULL
111#define SYS_ERR_STAT_FFLP 0x0000000000000008ULL
112#define SYS_ERR_STAT_IPP 0x0000000000000004ULL
113#define SYS_ERR_STAT_MAC 0x0000000000000002ULL
114#define SYS_ERR_STAT_SMX 0x0000000000000001ULL
115
116#define SID(LDG) (FZC_PIO + 0x10200UL + (LDG) * 8UL)
117#define SID_FUNC 0x0000000000000060ULL
118#define SID_FUNC_SHIFT 5
119#define SID_VECTOR 0x000000000000001fULL
120#define SID_VECTOR_SHIFT 0
121
122#define LDG_NUM(LDN) (FZC_PIO + 0x20000UL + (LDN) * 8UL)
123
124#define XMAC_PORT0_OFF (FZC_MAC + 0x000000)
125#define XMAC_PORT1_OFF (FZC_MAC + 0x006000)
126#define BMAC_PORT2_OFF (FZC_MAC + 0x00c000)
127#define BMAC_PORT3_OFF (FZC_MAC + 0x010000)
128
129/* XMAC registers, offset from np->mac_regs */
130
131#define XTXMAC_SW_RST 0x00000UL
132#define XTXMAC_SW_RST_REG_RS 0x0000000000000002ULL
133#define XTXMAC_SW_RST_SOFT_RST 0x0000000000000001ULL
134
135#define XRXMAC_SW_RST 0x00008UL
136#define XRXMAC_SW_RST_REG_RS 0x0000000000000002ULL
137#define XRXMAC_SW_RST_SOFT_RST 0x0000000000000001ULL
138
139#define XTXMAC_STATUS 0x00020UL
140#define XTXMAC_STATUS_FRAME_CNT_EXP 0x0000000000000800ULL
141#define XTXMAC_STATUS_BYTE_CNT_EXP 0x0000000000000400ULL
142#define XTXMAC_STATUS_TXFIFO_XFR_ERR 0x0000000000000010ULL
143#define XTXMAC_STATUS_TXMAC_OFLOW 0x0000000000000008ULL
144#define XTXMAC_STATUS_MAX_PSIZE_ERR 0x0000000000000004ULL
145#define XTXMAC_STATUS_TXMAC_UFLOW 0x0000000000000002ULL
146#define XTXMAC_STATUS_FRAME_XMITED 0x0000000000000001ULL
147
148#define XRXMAC_STATUS 0x00028UL
149#define XRXMAC_STATUS_RXHIST7_CNT_EXP 0x0000000000100000ULL
150#define XRXMAC_STATUS_LCL_FLT_STATUS 0x0000000000080000ULL
151#define XRXMAC_STATUS_RFLT_DET 0x0000000000040000ULL
152#define XRXMAC_STATUS_LFLT_CNT_EXP 0x0000000000020000ULL
153#define XRXMAC_STATUS_PHY_MDINT 0x0000000000010000ULL
154#define XRXMAC_STATUS_ALIGNERR_CNT_EXP 0x0000000000010000ULL
155#define XRXMAC_STATUS_RXFRAG_CNT_EXP 0x0000000000008000ULL
156#define XRXMAC_STATUS_RXMULTF_CNT_EXP 0x0000000000004000ULL
157#define XRXMAC_STATUS_RXBCAST_CNT_EXP 0x0000000000002000ULL
158#define XRXMAC_STATUS_RXHIST6_CNT_EXP 0x0000000000001000ULL
159#define XRXMAC_STATUS_RXHIST5_CNT_EXP 0x0000000000000800ULL
160#define XRXMAC_STATUS_RXHIST4_CNT_EXP 0x0000000000000400ULL
161#define XRXMAC_STATUS_RXHIST3_CNT_EXP 0x0000000000000200ULL
162#define XRXMAC_STATUS_RXHIST2_CNT_EXP 0x0000000000000100ULL
163#define XRXMAC_STATUS_RXHIST1_CNT_EXP 0x0000000000000080ULL
164#define XRXMAC_STATUS_RXOCTET_CNT_EXP 0x0000000000000040ULL
165#define XRXMAC_STATUS_CVIOLERR_CNT_EXP 0x0000000000000020ULL
166#define XRXMAC_STATUS_LENERR_CNT_EXP 0x0000000000000010ULL
167#define XRXMAC_STATUS_CRCERR_CNT_EXP 0x0000000000000008ULL
168#define XRXMAC_STATUS_RXUFLOW 0x0000000000000004ULL
169#define XRXMAC_STATUS_RXOFLOW 0x0000000000000002ULL
170#define XRXMAC_STATUS_FRAME_RCVD 0x0000000000000001ULL
171
172#define XMAC_FC_STAT 0x00030UL
173#define XMAC_FC_STAT_RX_RCV_PAUSE_TIME 0x00000000ffff0000ULL
174#define XMAC_FC_STAT_TX_MAC_NPAUSE 0x0000000000000004ULL
175#define XMAC_FC_STAT_TX_MAC_PAUSE 0x0000000000000002ULL
176#define XMAC_FC_STAT_RX_MAC_RPAUSE 0x0000000000000001ULL
177
178#define XTXMAC_STAT_MSK 0x00040UL
179#define XTXMAC_STAT_MSK_FRAME_CNT_EXP 0x0000000000000800ULL
180#define XTXMAC_STAT_MSK_BYTE_CNT_EXP 0x0000000000000400ULL
181#define XTXMAC_STAT_MSK_TXFIFO_XFR_ERR 0x0000000000000010ULL
182#define XTXMAC_STAT_MSK_TXMAC_OFLOW 0x0000000000000008ULL
183#define XTXMAC_STAT_MSK_MAX_PSIZE_ERR 0x0000000000000004ULL
184#define XTXMAC_STAT_MSK_TXMAC_UFLOW 0x0000000000000002ULL
185#define XTXMAC_STAT_MSK_FRAME_XMITED 0x0000000000000001ULL
186
187#define XRXMAC_STAT_MSK 0x00048UL
188#define XRXMAC_STAT_MSK_LCL_FLT_STAT_MSK 0x0000000000080000ULL
189#define XRXMAC_STAT_MSK_RFLT_DET 0x0000000000040000ULL
190#define XRXMAC_STAT_MSK_LFLT_CNT_EXP 0x0000000000020000ULL
191#define XRXMAC_STAT_MSK_PHY_MDINT 0x0000000000010000ULL
192#define XRXMAC_STAT_MSK_RXFRAG_CNT_EXP 0x0000000000008000ULL
193#define XRXMAC_STAT_MSK_RXMULTF_CNT_EXP 0x0000000000004000ULL
194#define XRXMAC_STAT_MSK_RXBCAST_CNT_EXP 0x0000000000002000ULL
195#define XRXMAC_STAT_MSK_RXHIST6_CNT_EXP 0x0000000000001000ULL
196#define XRXMAC_STAT_MSK_RXHIST5_CNT_EXP 0x0000000000000800ULL
197#define XRXMAC_STAT_MSK_RXHIST4_CNT_EXP 0x0000000000000400ULL
198#define XRXMAC_STAT_MSK_RXHIST3_CNT_EXP 0x0000000000000200ULL
199#define XRXMAC_STAT_MSK_RXHIST2_CNT_EXP 0x0000000000000100ULL
200#define XRXMAC_STAT_MSK_RXHIST1_CNT_EXP 0x0000000000000080ULL
201#define XRXMAC_STAT_MSK_RXOCTET_CNT_EXP 0x0000000000000040ULL
202#define XRXMAC_STAT_MSK_CVIOLERR_CNT_EXP 0x0000000000000020ULL
203#define XRXMAC_STAT_MSK_LENERR_CNT_EXP 0x0000000000000010ULL
204#define XRXMAC_STAT_MSK_CRCERR_CNT_EXP 0x0000000000000008ULL
205#define XRXMAC_STAT_MSK_RXUFLOW_CNT_EXP 0x0000000000000004ULL
206#define XRXMAC_STAT_MSK_RXOFLOW_CNT_EXP 0x0000000000000002ULL
207#define XRXMAC_STAT_MSK_FRAME_RCVD 0x0000000000000001ULL
208
209#define XMAC_FC_MSK 0x00050UL
210#define XMAC_FC_MSK_TX_MAC_NPAUSE 0x0000000000000004ULL
211#define XMAC_FC_MSK_TX_MAC_PAUSE 0x0000000000000002ULL
212#define XMAC_FC_MSK_RX_MAC_RPAUSE 0x0000000000000001ULL
213
214#define XMAC_CONFIG 0x00060UL
215#define XMAC_CONFIG_SEL_CLK_25MHZ 0x0000000080000000ULL
216#define XMAC_CONFIG_1G_PCS_BYPASS 0x0000000040000000ULL
217#define XMAC_CONFIG_10G_XPCS_BYPASS 0x0000000020000000ULL
218#define XMAC_CONFIG_MODE_MASK 0x0000000018000000ULL
219#define XMAC_CONFIG_MODE_XGMII 0x0000000000000000ULL
220#define XMAC_CONFIG_MODE_GMII 0x0000000008000000ULL
221#define XMAC_CONFIG_MODE_MII 0x0000000010000000ULL
222#define XMAC_CONFIG_LFS_DISABLE 0x0000000004000000ULL
223#define XMAC_CONFIG_LOOPBACK 0x0000000002000000ULL
224#define XMAC_CONFIG_TX_OUTPUT_EN 0x0000000001000000ULL
225#define XMAC_CONFIG_SEL_POR_CLK_SRC 0x0000000000800000ULL
226#define XMAC_CONFIG_LED_POLARITY 0x0000000000400000ULL
227#define XMAC_CONFIG_FORCE_LED_ON 0x0000000000200000ULL
228#define XMAC_CONFIG_PASS_FLOW_CTRL 0x0000000000100000ULL
229#define XMAC_CONFIG_RCV_PAUSE_ENABLE 0x0000000000080000ULL
230#define XMAC_CONFIG_MAC2IPP_PKT_CNT_EN 0x0000000000040000ULL
231#define XMAC_CONFIG_STRIP_CRC 0x0000000000020000ULL
232#define XMAC_CONFIG_ADDR_FILTER_EN 0x0000000000010000ULL
233#define XMAC_CONFIG_HASH_FILTER_EN 0x0000000000008000ULL
234#define XMAC_CONFIG_RX_CODEV_CHK_DIS 0x0000000000004000ULL
235#define XMAC_CONFIG_RESERVED_MULTICAST 0x0000000000002000ULL
236#define XMAC_CONFIG_RX_CRC_CHK_DIS 0x0000000000001000ULL
237#define XMAC_CONFIG_ERR_CHK_DIS 0x0000000000000800ULL
238#define XMAC_CONFIG_PROMISC_GROUP 0x0000000000000400ULL
239#define XMAC_CONFIG_PROMISCUOUS 0x0000000000000200ULL
240#define XMAC_CONFIG_RX_MAC_ENABLE 0x0000000000000100ULL
241#define XMAC_CONFIG_WARNING_MSG_EN 0x0000000000000080ULL
242#define XMAC_CONFIG_ALWAYS_NO_CRC 0x0000000000000008ULL
243#define XMAC_CONFIG_VAR_MIN_IPG_EN 0x0000000000000004ULL
244#define XMAC_CONFIG_STRETCH_MODE 0x0000000000000002ULL
245#define XMAC_CONFIG_TX_ENABLE 0x0000000000000001ULL
246
247#define XMAC_IPG 0x00080UL
248#define XMAC_IPG_STRETCH_CONST 0x0000000000e00000ULL
249#define XMAC_IPG_STRETCH_CONST_SHIFT 21
250#define XMAC_IPG_STRETCH_RATIO 0x00000000001f0000ULL
251#define XMAC_IPG_STRETCH_RATIO_SHIFT 16
252#define XMAC_IPG_IPG_MII_GMII 0x000000000000ff00ULL
253#define XMAC_IPG_IPG_MII_GMII_SHIFT 8
254#define XMAC_IPG_IPG_XGMII 0x0000000000000007ULL
255#define XMAC_IPG_IPG_XGMII_SHIFT 0
256
257#define IPG_12_15_XGMII 3
258#define IPG_16_19_XGMII 4
259#define IPG_20_23_XGMII 5
260#define IPG_12_MII_GMII 10
261#define IPG_13_MII_GMII 11
262#define IPG_14_MII_GMII 12
263#define IPG_15_MII_GMII 13
264#define IPG_16_MII_GMII 14
265
266#define XMAC_MIN 0x00088UL
267#define XMAC_MIN_RX_MIN_PKT_SIZE 0x000000003ff00000ULL
268#define XMAC_MIN_RX_MIN_PKT_SIZE_SHFT 20
269#define XMAC_MIN_SLOT_TIME 0x000000000003fc00ULL
270#define XMAC_MIN_SLOT_TIME_SHFT 10
271#define XMAC_MIN_TX_MIN_PKT_SIZE 0x00000000000003ffULL
272#define XMAC_MIN_TX_MIN_PKT_SIZE_SHFT 0
273
274#define XMAC_MAX 0x00090UL
275#define XMAC_MAX_FRAME_SIZE 0x0000000000003fffULL
276#define XMAC_MAX_FRAME_SIZE_SHFT 0
277
278#define XMAC_ADDR0 0x000a0UL
279#define XMAC_ADDR0_ADDR0 0x000000000000ffffULL
280
281#define XMAC_ADDR1 0x000a8UL
282#define XMAC_ADDR1_ADDR1 0x000000000000ffffULL
283
284#define XMAC_ADDR2 0x000b0UL
285#define XMAC_ADDR2_ADDR2 0x000000000000ffffULL
286
287#define XMAC_ADDR_CMPEN 0x00208UL
288#define XMAC_ADDR_CMPEN_EN15 0x0000000000008000ULL
289#define XMAC_ADDR_CMPEN_EN14 0x0000000000004000ULL
290#define XMAC_ADDR_CMPEN_EN13 0x0000000000002000ULL
291#define XMAC_ADDR_CMPEN_EN12 0x0000000000001000ULL
292#define XMAC_ADDR_CMPEN_EN11 0x0000000000000800ULL
293#define XMAC_ADDR_CMPEN_EN10 0x0000000000000400ULL
294#define XMAC_ADDR_CMPEN_EN9 0x0000000000000200ULL
295#define XMAC_ADDR_CMPEN_EN8 0x0000000000000100ULL
296#define XMAC_ADDR_CMPEN_EN7 0x0000000000000080ULL
297#define XMAC_ADDR_CMPEN_EN6 0x0000000000000040ULL
298#define XMAC_ADDR_CMPEN_EN5 0x0000000000000020ULL
299#define XMAC_ADDR_CMPEN_EN4 0x0000000000000010ULL
300#define XMAC_ADDR_CMPEN_EN3 0x0000000000000008ULL
301#define XMAC_ADDR_CMPEN_EN2 0x0000000000000004ULL
302#define XMAC_ADDR_CMPEN_EN1 0x0000000000000002ULL
303#define XMAC_ADDR_CMPEN_EN0 0x0000000000000001ULL
304
305#define XMAC_NUM_ALT_ADDR 16
306
307#define XMAC_ALT_ADDR0(NUM) (0x00218UL + (NUM)*0x18UL)
308#define XMAC_ALT_ADDR0_ADDR0 0x000000000000ffffULL
309
310#define XMAC_ALT_ADDR1(NUM) (0x00220UL + (NUM)*0x18UL)
311#define XMAC_ALT_ADDR1_ADDR1 0x000000000000ffffULL
312
313#define XMAC_ALT_ADDR2(NUM) (0x00228UL + (NUM)*0x18UL)
314#define XMAC_ALT_ADDR2_ADDR2 0x000000000000ffffULL
315
316#define XMAC_ADD_FILT0 0x00818UL
317#define XMAC_ADD_FILT0_FILT0 0x000000000000ffffULL
318
319#define XMAC_ADD_FILT1 0x00820UL
320#define XMAC_ADD_FILT1_FILT1 0x000000000000ffffULL
321
322#define XMAC_ADD_FILT2 0x00828UL
323#define XMAC_ADD_FILT2_FILT2 0x000000000000ffffULL
324
325#define XMAC_ADD_FILT12_MASK 0x00830UL
326#define XMAC_ADD_FILT12_MASK_VAL 0x00000000000000ffULL
327
328#define XMAC_ADD_FILT00_MASK 0x00838UL
329#define XMAC_ADD_FILT00_MASK_VAL 0x000000000000ffffULL
330
331#define XMAC_HASH_TBL(NUM) (0x00840UL + (NUM) * 0x8UL)
332#define XMAC_HASH_TBL_VAL 0x000000000000ffffULL
333
334#define XMAC_NUM_HOST_INFO 20
335
336#define XMAC_HOST_INFO(NUM) (0x00900UL + (NUM) * 0x8UL)
337
338#define XMAC_PA_DATA0 0x00b80UL
339#define XMAC_PA_DATA0_VAL 0x00000000ffffffffULL
340
341#define XMAC_PA_DATA1 0x00b88UL
342#define XMAC_PA_DATA1_VAL 0x00000000ffffffffULL
343
344#define XMAC_DEBUG_SEL 0x00b90UL
345#define XMAC_DEBUG_SEL_XMAC 0x0000000000000078ULL
346#define XMAC_DEBUG_SEL_MAC 0x0000000000000007ULL
347
348#define XMAC_TRAIN_VEC 0x00b98UL
349#define XMAC_TRAIN_VEC_VAL 0x00000000ffffffffULL
350
351#define RXMAC_BT_CNT 0x00100UL
352#define RXMAC_BT_CNT_COUNT 0x00000000ffffffffULL
353
354#define RXMAC_BC_FRM_CNT 0x00108UL
355#define RXMAC_BC_FRM_CNT_COUNT 0x00000000001fffffULL
356
357#define RXMAC_MC_FRM_CNT 0x00110UL
358#define RXMAC_MC_FRM_CNT_COUNT 0x00000000001fffffULL
359
360#define RXMAC_FRAG_CNT 0x00118UL
361#define RXMAC_FRAG_CNT_COUNT 0x00000000001fffffULL
362
363#define RXMAC_HIST_CNT1 0x00120UL
364#define RXMAC_HIST_CNT1_COUNT 0x00000000001fffffULL
365
366#define RXMAC_HIST_CNT2 0x00128UL
367#define RXMAC_HIST_CNT2_COUNT 0x00000000001fffffULL
368
369#define RXMAC_HIST_CNT3 0x00130UL
370#define RXMAC_HIST_CNT3_COUNT 0x00000000000fffffULL
371
372#define RXMAC_HIST_CNT4 0x00138UL
373#define RXMAC_HIST_CNT4_COUNT 0x000000000007ffffULL
374
375#define RXMAC_HIST_CNT5 0x00140UL
376#define RXMAC_HIST_CNT5_COUNT 0x000000000003ffffULL
377
378#define RXMAC_HIST_CNT6 0x00148UL
379#define RXMAC_HIST_CNT6_COUNT 0x000000000000ffffULL
380
381#define RXMAC_MPSZER_CNT 0x00150UL
382#define RXMAC_MPSZER_CNT_COUNT 0x00000000000000ffULL
383
384#define RXMAC_CRC_ER_CNT 0x00158UL
385#define RXMAC_CRC_ER_CNT_COUNT 0x00000000000000ffULL
386
387#define RXMAC_CD_VIO_CNT 0x00160UL
388#define RXMAC_CD_VIO_CNT_COUNT 0x00000000000000ffULL
389
390#define RXMAC_ALIGN_ERR_CNT 0x00168UL
391#define RXMAC_ALIGN_ERR_CNT_COUNT 0x00000000000000ffULL
392
393#define TXMAC_FRM_CNT 0x00170UL
394#define TXMAC_FRM_CNT_COUNT 0x00000000ffffffffULL
395
396#define TXMAC_BYTE_CNT 0x00178UL
397#define TXMAC_BYTE_CNT_COUNT 0x00000000ffffffffULL
398
399#define LINK_FAULT_CNT 0x00180UL
400#define LINK_FAULT_CNT_COUNT 0x00000000000000ffULL
401
402#define RXMAC_HIST_CNT7 0x00188UL
403#define RXMAC_HIST_CNT7_COUNT 0x0000000007ffffffULL
404
405#define XMAC_SM_REG 0x001a8UL
406#define XMAC_SM_REG_STATE 0x00000000ffffffffULL
407
408#define XMAC_INTER1 0x001b0UL
409#define XMAC_INTERN1_SIGNALS1 0x00000000ffffffffULL
410
411#define XMAC_INTER2 0x001b8UL
412#define XMAC_INTERN2_SIGNALS2 0x00000000ffffffffULL
413
414/* BMAC registers, offset from np->mac_regs */
415
416#define BTXMAC_SW_RST 0x00000UL
417#define BTXMAC_SW_RST_RESET 0x0000000000000001ULL
418
419#define BRXMAC_SW_RST 0x00008UL
420#define BRXMAC_SW_RST_RESET 0x0000000000000001ULL
421
422#define BMAC_SEND_PAUSE 0x00010UL
423#define BMAC_SEND_PAUSE_SEND 0x0000000000010000ULL
424#define BMAC_SEND_PAUSE_TIME 0x000000000000ffffULL
425
426#define BTXMAC_STATUS 0x00020UL
427#define BTXMAC_STATUS_XMIT 0x0000000000000001ULL
428#define BTXMAC_STATUS_UNDERRUN 0x0000000000000002ULL
429#define BTXMAC_STATUS_MAX_PKT_ERR 0x0000000000000004ULL
430#define BTXMAC_STATUS_BYTE_CNT_EXP 0x0000000000000400ULL
431#define BTXMAC_STATUS_FRAME_CNT_EXP 0x0000000000000800ULL
432
433#define BRXMAC_STATUS 0x00028UL
434#define BRXMAC_STATUS_RX_PKT 0x0000000000000001ULL
435#define BRXMAC_STATUS_OVERFLOW 0x0000000000000002ULL
436#define BRXMAC_STATUS_FRAME_CNT_EXP 0x0000000000000004ULL
437#define BRXMAC_STATUS_ALIGN_ERR_EXP 0x0000000000000008ULL
438#define BRXMAC_STATUS_CRC_ERR_EXP 0x0000000000000010ULL
439#define BRXMAC_STATUS_LEN_ERR_EXP 0x0000000000000020ULL
440
441#define BMAC_CTRL_STATUS 0x00030UL
442#define BMAC_CTRL_STATUS_PAUSE_RECV 0x0000000000000001ULL
443#define BMAC_CTRL_STATUS_PAUSE 0x0000000000000002ULL
444#define BMAC_CTRL_STATUS_NOPAUSE 0x0000000000000004ULL
445#define BMAC_CTRL_STATUS_TIME 0x00000000ffff0000ULL
446#define BMAC_CTRL_STATUS_TIME_SHIFT 16
447
448#define BTXMAC_STATUS_MASK 0x00040UL
449#define BRXMAC_STATUS_MASK 0x00048UL
450#define BMAC_CTRL_STATUS_MASK 0x00050UL
451
452#define BTXMAC_CONFIG 0x00060UL
453#define BTXMAC_CONFIG_ENABLE 0x0000000000000001ULL
454#define BTXMAC_CONFIG_FCS_DISABLE 0x0000000000000002ULL
455
456#define BRXMAC_CONFIG 0x00068UL
457#define BRXMAC_CONFIG_DISCARD_DIS 0x0000000000000080ULL
458#define BRXMAC_CONFIG_ADDR_FILT_EN 0x0000000000000040ULL
459#define BRXMAC_CONFIG_HASH_FILT_EN 0x0000000000000020ULL
460#define BRXMAC_CONFIG_PROMISC_GRP 0x0000000000000010ULL
461#define BRXMAC_CONFIG_PROMISC 0x0000000000000008ULL
462#define BRXMAC_CONFIG_STRIP_FCS 0x0000000000000004ULL
463#define BRXMAC_CONFIG_STRIP_PAD 0x0000000000000002ULL
464#define BRXMAC_CONFIG_ENABLE 0x0000000000000001ULL
465
466#define BMAC_CTRL_CONFIG 0x00070UL
467#define BMAC_CTRL_CONFIG_TX_PAUSE_EN 0x0000000000000001ULL
468#define BMAC_CTRL_CONFIG_RX_PAUSE_EN 0x0000000000000002ULL
469#define BMAC_CTRL_CONFIG_PASS_CTRL 0x0000000000000004ULL
470
471#define BMAC_XIF_CONFIG 0x00078UL
472#define BMAC_XIF_CONFIG_TX_OUTPUT_EN 0x0000000000000001ULL
473#define BMAC_XIF_CONFIG_MII_LOOPBACK 0x0000000000000002ULL
474#define BMAC_XIF_CONFIG_GMII_MODE 0x0000000000000008ULL
475#define BMAC_XIF_CONFIG_LINK_LED 0x0000000000000020ULL
476#define BMAC_XIF_CONFIG_LED_POLARITY 0x0000000000000040ULL
477#define BMAC_XIF_CONFIG_25MHZ_CLOCK 0x0000000000000080ULL
478
479#define BMAC_MIN_FRAME 0x000a0UL
480#define BMAC_MIN_FRAME_VAL 0x00000000000003ffULL
481
482#define BMAC_MAX_FRAME 0x000a8UL
483#define BMAC_MAX_FRAME_MAX_BURST 0x000000003fff0000ULL
484#define BMAC_MAX_FRAME_MAX_BURST_SHIFT 16
485#define BMAC_MAX_FRAME_MAX_FRAME 0x0000000000003fffULL
486#define BMAC_MAX_FRAME_MAX_FRAME_SHIFT 0
487
488#define BMAC_PREAMBLE_SIZE 0x000b0UL
489#define BMAC_PREAMBLE_SIZE_VAL 0x00000000000003ffULL
490
491#define BMAC_CTRL_TYPE 0x000c8UL
492
493#define BMAC_ADDR0 0x00100UL
494#define BMAC_ADDR0_ADDR0 0x000000000000ffffULL
495
496#define BMAC_ADDR1 0x00108UL
497#define BMAC_ADDR1_ADDR1 0x000000000000ffffULL
498
499#define BMAC_ADDR2 0x00110UL
500#define BMAC_ADDR2_ADDR2 0x000000000000ffffULL
501
502#define BMAC_NUM_ALT_ADDR 7
503
504#define BMAC_ALT_ADDR0(NUM) (0x00118UL + (NUM)*0x18UL)
505#define BMAC_ALT_ADDR0_ADDR0 0x000000000000ffffULL
506
507#define BMAC_ALT_ADDR1(NUM) (0x00120UL + (NUM)*0x18UL)
508#define BMAC_ALT_ADDR1_ADDR1 0x000000000000ffffULL
509
510#define BMAC_ALT_ADDR2(NUM) (0x00128UL + (NUM)*0x18UL)
511#define BMAC_ALT_ADDR2_ADDR2 0x000000000000ffffULL
512
513#define BMAC_FC_ADDR0 0x00268UL
514#define BMAC_FC_ADDR0_ADDR0 0x000000000000ffffULL
515
516#define BMAC_FC_ADDR1 0x00270UL
517#define BMAC_FC_ADDR1_ADDR1 0x000000000000ffffULL
518
519#define BMAC_FC_ADDR2 0x00278UL
520#define BMAC_FC_ADDR2_ADDR2 0x000000000000ffffULL
521
522#define BMAC_ADD_FILT0 0x00298UL
523#define BMAC_ADD_FILT0_FILT0 0x000000000000ffffULL
524
525#define BMAC_ADD_FILT1 0x002a0UL
526#define BMAC_ADD_FILT1_FILT1 0x000000000000ffffULL
527
528#define BMAC_ADD_FILT2 0x002a8UL
529#define BMAC_ADD_FILT2_FILT2 0x000000000000ffffULL
530
531#define BMAC_ADD_FILT12_MASK 0x002b0UL
532#define BMAC_ADD_FILT12_MASK_VAL 0x00000000000000ffULL
533
534#define BMAC_ADD_FILT00_MASK 0x002b8UL
535#define BMAC_ADD_FILT00_MASK_VAL 0x000000000000ffffULL
536
537#define BMAC_HASH_TBL(NUM) (0x002c0UL + (NUM) * 0x8UL)
538#define BMAC_HASH_TBL_VAL 0x000000000000ffffULL
539
540#define BRXMAC_FRAME_CNT 0x00370
541#define BRXMAC_FRAME_CNT_COUNT 0x000000000000ffffULL
542
543#define BRXMAC_MAX_LEN_ERR_CNT 0x00378
544
545#define BRXMAC_ALIGN_ERR_CNT 0x00380
546#define BRXMAC_ALIGN_ERR_CNT_COUNT 0x000000000000ffffULL
547
548#define BRXMAC_CRC_ERR_CNT 0x00388
549#define BRXMAC_ALIGN_ERR_CNT_COUNT 0x000000000000ffffULL
550
551#define BRXMAC_CODE_VIOL_ERR_CNT 0x00390
552#define BRXMAC_CODE_VIOL_ERR_CNT_COUNT 0x000000000000ffffULL
553
554#define BMAC_STATE_MACHINE 0x003a0
555
556#define BMAC_ADDR_CMPEN 0x003f8UL
557#define BMAC_ADDR_CMPEN_EN15 0x0000000000008000ULL
558#define BMAC_ADDR_CMPEN_EN14 0x0000000000004000ULL
559#define BMAC_ADDR_CMPEN_EN13 0x0000000000002000ULL
560#define BMAC_ADDR_CMPEN_EN12 0x0000000000001000ULL
561#define BMAC_ADDR_CMPEN_EN11 0x0000000000000800ULL
562#define BMAC_ADDR_CMPEN_EN10 0x0000000000000400ULL
563#define BMAC_ADDR_CMPEN_EN9 0x0000000000000200ULL
564#define BMAC_ADDR_CMPEN_EN8 0x0000000000000100ULL
565#define BMAC_ADDR_CMPEN_EN7 0x0000000000000080ULL
566#define BMAC_ADDR_CMPEN_EN6 0x0000000000000040ULL
567#define BMAC_ADDR_CMPEN_EN5 0x0000000000000020ULL
568#define BMAC_ADDR_CMPEN_EN4 0x0000000000000010ULL
569#define BMAC_ADDR_CMPEN_EN3 0x0000000000000008ULL
570#define BMAC_ADDR_CMPEN_EN2 0x0000000000000004ULL
571#define BMAC_ADDR_CMPEN_EN1 0x0000000000000002ULL
572#define BMAC_ADDR_CMPEN_EN0 0x0000000000000001ULL
573
574#define BMAC_NUM_HOST_INFO 9
575
576#define BMAC_HOST_INFO(NUM) (0x00400UL + (NUM) * 0x8UL)
577
578#define BTXMAC_BYTE_CNT 0x00448UL
579#define BTXMAC_BYTE_CNT_COUNT 0x00000000ffffffffULL
580
581#define BTXMAC_FRM_CNT 0x00450UL
582#define BTXMAC_FRM_CNT_COUNT 0x00000000ffffffffULL
583
584#define BRXMAC_BYTE_CNT 0x00458UL
585#define BRXMAC_BYTE_CNT_COUNT 0x00000000ffffffffULL
586
587#define HOST_INFO_MPR 0x0000000000000100ULL
588#define HOST_INFO_MACRDCTBLN 0x0000000000000007ULL
589
590/* XPCS registers, offset from np->regs + np->xpcs_off */
591
592#define XPCS_CONTROL1 (FZC_MAC + 0x00000UL)
593#define XPCS_CONTROL1_RESET 0x0000000000008000ULL
594#define XPCS_CONTROL1_LOOPBACK 0x0000000000004000ULL
595#define XPCS_CONTROL1_SPEED_SELECT3 0x0000000000002000ULL
596#define XPCS_CONTROL1_CSR_LOW_PWR 0x0000000000000800ULL
597#define XPCS_CONTROL1_CSR_SPEED1 0x0000000000000040ULL
598#define XPCS_CONTROL1_CSR_SPEED0 0x000000000000003cULL
599
600#define XPCS_STATUS1 (FZC_MAC + 0x00008UL)
601#define XPCS_STATUS1_CSR_FAULT 0x0000000000000080ULL
602#define XPCS_STATUS1_CSR_RXLNK_STAT 0x0000000000000004ULL
603#define XPCS_STATUS1_CSR_LPWR_ABLE 0x0000000000000002ULL
604
605#define XPCS_DEVICE_IDENTIFIER (FZC_MAC + 0x00010UL)
606#define XPCS_DEVICE_IDENTIFIER_VAL 0x00000000ffffffffULL
607
608#define XPCS_SPEED_ABILITY (FZC_MAC + 0x00018UL)
609#define XPCS_SPEED_ABILITY_10GIG 0x0000000000000001ULL
610
611#define XPCS_DEV_IN_PKG (FZC_MAC + 0x00020UL)
612#define XPCS_DEV_IN_PKG_CSR_VEND2 0x0000000080000000ULL
613#define XPCS_DEV_IN_PKG_CSR_VEND1 0x0000000040000000ULL
614#define XPCS_DEV_IN_PKG_DTE_XS 0x0000000000000020ULL
615#define XPCS_DEV_IN_PKG_PHY_XS 0x0000000000000010ULL
616#define XPCS_DEV_IN_PKG_PCS 0x0000000000000008ULL
617#define XPCS_DEV_IN_PKG_WIS 0x0000000000000004ULL
618#define XPCS_DEV_IN_PKG_PMD_PMA 0x0000000000000002ULL
619#define XPCS_DEV_IN_PKG_CLS22 0x0000000000000001ULL
620
621#define XPCS_CONTROL2 (FZC_MAC + 0x00028UL)
622#define XPCS_CONTROL2_CSR_PSC_SEL 0x0000000000000003ULL
623
624#define XPCS_STATUS2 (FZC_MAC + 0x00030UL)
625#define XPCS_STATUS2_CSR_DEV_PRES 0x000000000000c000ULL
626#define XPCS_STATUS2_CSR_TX_FAULT 0x0000000000000800ULL
627#define XPCS_STATUS2_CSR_RCV_FAULT 0x0000000000000400ULL
628#define XPCS_STATUS2_TEN_GBASE_W 0x0000000000000004ULL
629#define XPCS_STATUS2_TEN_GBASE_X 0x0000000000000002ULL
630#define XPCS_STATUS2_TEN_GBASE_R 0x0000000000000001ULL
631
632#define XPCS_PKG_ID (FZC_MAC + 0x00038UL)
633#define XPCS_PKG_ID_VAL 0x00000000ffffffffULL
634
635#define XPCS_STATUS(IDX) (FZC_MAC + 0x00040UL)
636#define XPCS_STATUS_CSR_LANE_ALIGN 0x0000000000001000ULL
637#define XPCS_STATUS_CSR_PATTEST_CAP 0x0000000000000800ULL
638#define XPCS_STATUS_CSR_LANE3_SYNC 0x0000000000000008ULL
639#define XPCS_STATUS_CSR_LANE2_SYNC 0x0000000000000004ULL
640#define XPCS_STATUS_CSR_LANE1_SYNC 0x0000000000000002ULL
641#define XPCS_STATUS_CSR_LANE0_SYNC 0x0000000000000001ULL
642
643#define XPCS_TEST_CONTROL (FZC_MAC + 0x00048UL)
644#define XPCS_TEST_CONTROL_TXTST_EN 0x0000000000000004ULL
645#define XPCS_TEST_CONTROL_TPAT_SEL 0x0000000000000003ULL
646
647#define XPCS_CFG_VENDOR1 (FZC_MAC + 0x00050UL)
648#define XPCS_CFG_VENDOR1_DBG_IOTST 0x0000000000000080ULL
649#define XPCS_CFG_VENDOR1_DBG_SEL 0x0000000000000078ULL
650#define XPCS_CFG_VENDOR1_BYPASS_DET 0x0000000000000004ULL
651#define XPCS_CFG_VENDOR1_TXBUF_EN 0x0000000000000002ULL
652#define XPCS_CFG_VENDOR1_XPCS_EN 0x0000000000000001ULL
653
654#define XPCS_DIAG_VENDOR2 (FZC_MAC + 0x00058UL)
655#define XPCS_DIAG_VENDOR2_SSM_LANE3 0x0000000001e00000ULL
656#define XPCS_DIAG_VENDOR2_SSM_LANE2 0x00000000001e0000ULL
657#define XPCS_DIAG_VENDOR2_SSM_LANE1 0x000000000001e000ULL
658#define XPCS_DIAG_VENDOR2_SSM_LANE0 0x0000000000001e00ULL
659#define XPCS_DIAG_VENDOR2_EBUF_SM 0x00000000000001feULL
660#define XPCS_DIAG_VENDOR2_RCV_SM 0x0000000000000001ULL
661
662#define XPCS_MASK1 (FZC_MAC + 0x00060UL)
663#define XPCS_MASK1_FAULT_MASK 0x0000000000000080ULL
664#define XPCS_MASK1_RXALIGN_STAT_MSK 0x0000000000000004ULL
665
666#define XPCS_PKT_COUNT (FZC_MAC + 0x00068UL)
667#define XPCS_PKT_COUNT_TX 0x00000000ffff0000ULL
668#define XPCS_PKT_COUNT_RX 0x000000000000ffffULL
669
670#define XPCS_TX_SM (FZC_MAC + 0x00070UL)
671#define XPCS_TX_SM_VAL 0x000000000000000fULL
672
673#define XPCS_DESKEW_ERR_CNT (FZC_MAC + 0x00078UL)
674#define XPCS_DESKEW_ERR_CNT_VAL 0x00000000000000ffULL
675
676#define XPCS_SYMERR_CNT01 (FZC_MAC + 0x00080UL)
677#define XPCS_SYMERR_CNT01_LANE1 0x00000000ffff0000ULL
678#define XPCS_SYMERR_CNT01_LANE0 0x000000000000ffffULL
679
680#define XPCS_SYMERR_CNT23 (FZC_MAC + 0x00088UL)
681#define XPCS_SYMERR_CNT23_LANE3 0x00000000ffff0000ULL
682#define XPCS_SYMERR_CNT23_LANE2 0x000000000000ffffULL
683
684#define XPCS_TRAINING_VECTOR (FZC_MAC + 0x00090UL)
685#define XPCS_TRAINING_VECTOR_VAL 0x00000000ffffffffULL
686
687/* PCS registers, offset from np->regs + np->pcs_off */
688
689#define PCS_MII_CTL (FZC_MAC + 0x00000UL)
690#define PCS_MII_CTL_RST 0x0000000000008000ULL
691#define PCS_MII_CTL_10_100_SPEED 0x0000000000002000ULL
692#define PCS_MII_AUTONEG_EN 0x0000000000001000ULL
693#define PCS_MII_PWR_DOWN 0x0000000000000800ULL
694#define PCS_MII_ISOLATE 0x0000000000000400ULL
695#define PCS_MII_AUTONEG_RESTART 0x0000000000000200ULL
696#define PCS_MII_DUPLEX 0x0000000000000100ULL
697#define PCS_MII_COLL_TEST 0x0000000000000080ULL
698#define PCS_MII_1000MB_SPEED 0x0000000000000040ULL
699
700#define PCS_MII_STAT (FZC_MAC + 0x00008UL)
701#define PCS_MII_STAT_EXT_STATUS 0x0000000000000100ULL
702#define PCS_MII_STAT_AUTONEG_DONE 0x0000000000000020ULL
703#define PCS_MII_STAT_REMOTE_FAULT 0x0000000000000010ULL
704#define PCS_MII_STAT_AUTONEG_ABLE 0x0000000000000008ULL
705#define PCS_MII_STAT_LINK_STATUS 0x0000000000000004ULL
706#define PCS_MII_STAT_JABBER_DET 0x0000000000000002ULL
707#define PCS_MII_STAT_EXT_CAP 0x0000000000000001ULL
708
709#define PCS_MII_ADV (FZC_MAC + 0x00010UL)
710#define PCS_MII_ADV_NEXT_PAGE 0x0000000000008000ULL
711#define PCS_MII_ADV_ACK 0x0000000000004000ULL
712#define PCS_MII_ADV_REMOTE_FAULT 0x0000000000003000ULL
713#define PCS_MII_ADV_ASM_DIR 0x0000000000000100ULL
714#define PCS_MII_ADV_PAUSE 0x0000000000000080ULL
715#define PCS_MII_ADV_HALF_DUPLEX 0x0000000000000040ULL
716#define PCS_MII_ADV_FULL_DUPLEX 0x0000000000000020ULL
717
718#define PCS_MII_PARTNER (FZC_MAC + 0x00018UL)
719#define PCS_MII_PARTNER_NEXT_PAGE 0x0000000000008000ULL
720#define PCS_MII_PARTNER_ACK 0x0000000000004000ULL
721#define PCS_MII_PARTNER_REMOTE_FAULT 0x0000000000002000ULL
722#define PCS_MII_PARTNER_PAUSE 0x0000000000000180ULL
723#define PCS_MII_PARTNER_HALF_DUPLEX 0x0000000000000040ULL
724#define PCS_MII_PARTNER_FULL_DUPLEX 0x0000000000000020ULL
725
726#define PCS_CONF (FZC_MAC + 0x00020UL)
727#define PCS_CONF_MASK 0x0000000000000040ULL
728#define PCS_CONF_10MS_TMR_OVERRIDE 0x0000000000000020ULL
729#define PCS_CONF_JITTER_STUDY 0x0000000000000018ULL
730#define PCS_CONF_SIGDET_ACTIVE_LOW 0x0000000000000004ULL
731#define PCS_CONF_SIGDET_OVERRIDE 0x0000000000000002ULL
732#define PCS_CONF_ENABLE 0x0000000000000001ULL
733
734#define PCS_STATE (FZC_MAC + 0x00028UL)
735#define PCS_STATE_D_PARTNER_FAIL 0x0000000020000000ULL
736#define PCS_STATE_D_WAIT_C_CODES_ACK 0x0000000010000000ULL
737#define PCS_STATE_D_SYNC_LOSS 0x0000000008000000ULL
738#define PCS_STATE_D_NO_GOOD_C_CODES 0x0000000004000000ULL
739#define PCS_STATE_D_SERDES 0x0000000002000000ULL
740#define PCS_STATE_D_BREAKLINK_C_CODES 0x0000000001000000ULL
741#define PCS_STATE_L_SIGDET 0x0000000000400000ULL
742#define PCS_STATE_L_SYNC_LOSS 0x0000000000200000ULL
743#define PCS_STATE_L_C_CODES 0x0000000000100000ULL
744#define PCS_STATE_LINK_CFG_STATE 0x000000000001e000ULL
745#define PCS_STATE_SEQ_DET_STATE 0x0000000000001800ULL
746#define PCS_STATE_WORD_SYNC_STATE 0x0000000000000700ULL
747#define PCS_STATE_NO_IDLE 0x000000000000000fULL
748
749#define PCS_INTERRUPT (FZC_MAC + 0x00030UL)
750#define PCS_INTERRUPT_LSTATUS 0x0000000000000004ULL
751
752#define PCS_DPATH_MODE (FZC_MAC + 0x000a0UL)
753#define PCS_DPATH_MODE_PCS 0x0000000000000000ULL
754#define PCS_DPATH_MODE_MII 0x0000000000000002ULL
755#define PCS_DPATH_MODE_LINKUP_F_ENAB 0x0000000000000001ULL
756
757#define PCS_PKT_CNT (FZC_MAC + 0x000c0UL)
758#define PCS_PKT_CNT_RX 0x0000000007ff0000ULL
759#define PCS_PKT_CNT_TX 0x00000000000007ffULL
760
761#define MIF_BB_MDC (FZC_MAC + 0x16000UL)
762#define MIF_BB_MDC_CLK 0x0000000000000001ULL
763
764#define MIF_BB_MDO (FZC_MAC + 0x16008UL)
765#define MIF_BB_MDO_DAT 0x0000000000000001ULL
766
767#define MIF_BB_MDO_EN (FZC_MAC + 0x16010UL)
768#define MIF_BB_MDO_EN_VAL 0x0000000000000001ULL
769
770#define MIF_FRAME_OUTPUT (FZC_MAC + 0x16018UL)
771#define MIF_FRAME_OUTPUT_ST 0x00000000c0000000ULL
772#define MIF_FRAME_OUTPUT_ST_SHIFT 30
773#define MIF_FRAME_OUTPUT_OP_ADDR 0x0000000000000000ULL
774#define MIF_FRAME_OUTPUT_OP_WRITE 0x0000000010000000ULL
775#define MIF_FRAME_OUTPUT_OP_READ_INC 0x0000000020000000ULL
776#define MIF_FRAME_OUTPUT_OP_READ 0x0000000030000000ULL
777#define MIF_FRAME_OUTPUT_OP_SHIFT 28
778#define MIF_FRAME_OUTPUT_PORT 0x000000000f800000ULL
779#define MIF_FRAME_OUTPUT_PORT_SHIFT 23
780#define MIF_FRAME_OUTPUT_REG 0x00000000007c0000ULL
781#define MIF_FRAME_OUTPUT_REG_SHIFT 18
782#define MIF_FRAME_OUTPUT_TA 0x0000000000030000ULL
783#define MIF_FRAME_OUTPUT_TA_SHIFT 16
784#define MIF_FRAME_OUTPUT_DATA 0x000000000000ffffULL
785#define MIF_FRAME_OUTPUT_DATA_SHIFT 0
786
787#define MDIO_ADDR_OP(port, dev, reg) \
788 ((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
789 MIF_FRAME_OUTPUT_OP_ADDR | \
790 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
791 (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
792 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
793 (reg << MIF_FRAME_OUTPUT_DATA_SHIFT))
794
795#define MDIO_READ_OP(port, dev) \
796 ((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
797 MIF_FRAME_OUTPUT_OP_READ | \
798 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
799 (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
800 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT))
801
802#define MDIO_WRITE_OP(port, dev, data) \
803 ((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
804 MIF_FRAME_OUTPUT_OP_WRITE | \
805 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
806 (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
807 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
808 (data << MIF_FRAME_OUTPUT_DATA_SHIFT))
809
810#define MII_READ_OP(port, reg) \
811 ((1 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
812 (2 << MIF_FRAME_OUTPUT_OP_SHIFT) | \
813 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
814 (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \
815 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT))
816
817#define MII_WRITE_OP(port, reg, data) \
818 ((1 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
819 (1 << MIF_FRAME_OUTPUT_OP_SHIFT) | \
820 (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
821 (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \
822 (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
823 (data << MIF_FRAME_OUTPUT_DATA_SHIFT))
824
825#define MIF_CONFIG (FZC_MAC + 0x16020UL)
826#define MIF_CONFIG_ATCA_GE 0x0000000000010000ULL
827#define MIF_CONFIG_INDIRECT_MODE 0x0000000000008000ULL
828#define MIF_CONFIG_POLL_PRT_PHYADDR 0x0000000000003c00ULL
829#define MIF_CONFIG_POLL_DEV_REG_ADDR 0x00000000000003e0ULL
830#define MIF_CONFIG_BB_MODE 0x0000000000000010ULL
831#define MIF_CONFIG_POLL_EN 0x0000000000000008ULL
832#define MIF_CONFIG_BB_SER_SEL 0x0000000000000006ULL
833#define MIF_CONFIG_MANUAL_MODE 0x0000000000000001ULL
834
835#define MIF_POLL_STATUS (FZC_MAC + 0x16028UL)
836#define MIF_POLL_STATUS_DATA 0x00000000ffff0000ULL
837#define MIF_POLL_STATUS_STAT 0x000000000000ffffULL
838
839#define MIF_POLL_MASK (FZC_MAC + 0x16030UL)
840#define MIF_POLL_MASK_VAL 0x000000000000ffffULL
841
842#define MIF_SM (FZC_MAC + 0x16038UL)
843#define MIF_SM_PORT_ADDR 0x00000000001f0000ULL
844#define MIF_SM_MDI_1 0x0000000000004000ULL
845#define MIF_SM_MDI_0 0x0000000000002400ULL
846#define MIF_SM_MDCLK 0x0000000000001000ULL
847#define MIF_SM_MDO_EN 0x0000000000000800ULL
848#define MIF_SM_MDO 0x0000000000000400ULL
849#define MIF_SM_MDI 0x0000000000000200ULL
850#define MIF_SM_CTL 0x00000000000001c0ULL
851#define MIF_SM_EX 0x000000000000003fULL
852
853#define MIF_STATUS (FZC_MAC + 0x16040UL)
854#define MIF_STATUS_MDINT1 0x0000000000000020ULL
855#define MIF_STATUS_MDINT0 0x0000000000000010ULL
856
857#define MIF_MASK (FZC_MAC + 0x16048UL)
858#define MIF_MASK_MDINT1 0x0000000000000020ULL
859#define MIF_MASK_MDINT0 0x0000000000000010ULL
860#define MIF_MASK_PEU_ERR 0x0000000000000008ULL
861#define MIF_MASK_YC 0x0000000000000004ULL
862#define MIF_MASK_XGE_ERR0 0x0000000000000002ULL
863#define MIF_MASK_MIF_INIT_DONE 0x0000000000000001ULL
864
865#define ENET_SERDES_RESET (FZC_MAC + 0x14000UL)
866#define ENET_SERDES_RESET_1 0x0000000000000002ULL
867#define ENET_SERDES_RESET_0 0x0000000000000001ULL
868
869#define ENET_SERDES_CFG (FZC_MAC + 0x14008UL)
870#define ENET_SERDES_BE_LOOPBACK 0x0000000000000002ULL
871#define ENET_SERDES_CFG_FORCE_RDY 0x0000000000000001ULL
872
873#define ENET_SERDES_0_PLL_CFG (FZC_MAC + 0x14010UL)
874#define ENET_SERDES_PLL_FBDIV0 0x0000000000000001ULL
875#define ENET_SERDES_PLL_FBDIV1 0x0000000000000002ULL
876#define ENET_SERDES_PLL_FBDIV2 0x0000000000000004ULL
877#define ENET_SERDES_PLL_HRATE0 0x0000000000000008ULL
878#define ENET_SERDES_PLL_HRATE1 0x0000000000000010ULL
879#define ENET_SERDES_PLL_HRATE2 0x0000000000000020ULL
880#define ENET_SERDES_PLL_HRATE3 0x0000000000000040ULL
881
882#define ENET_SERDES_0_CTRL_CFG (FZC_MAC + 0x14018UL)
883#define ENET_SERDES_CTRL_SDET_0 0x0000000000000001ULL
884#define ENET_SERDES_CTRL_SDET_1 0x0000000000000002ULL
885#define ENET_SERDES_CTRL_SDET_2 0x0000000000000004ULL
886#define ENET_SERDES_CTRL_SDET_3 0x0000000000000008ULL
887#define ENET_SERDES_CTRL_EMPH_0 0x0000000000000070ULL
888#define ENET_SERDES_CTRL_EMPH_0_SHIFT 4
889#define ENET_SERDES_CTRL_EMPH_1 0x0000000000000380ULL
890#define ENET_SERDES_CTRL_EMPH_1_SHIFT 7
891#define ENET_SERDES_CTRL_EMPH_2 0x0000000000001c00ULL
892#define ENET_SERDES_CTRL_EMPH_2_SHIFT 10
893#define ENET_SERDES_CTRL_EMPH_3 0x000000000000e000ULL
894#define ENET_SERDES_CTRL_EMPH_3_SHIFT 13
895#define ENET_SERDES_CTRL_LADJ_0 0x0000000000070000ULL
896#define ENET_SERDES_CTRL_LADJ_0_SHIFT 16
897#define ENET_SERDES_CTRL_LADJ_1 0x0000000000380000ULL
898#define ENET_SERDES_CTRL_LADJ_1_SHIFT 19
899#define ENET_SERDES_CTRL_LADJ_2 0x0000000001c00000ULL
900#define ENET_SERDES_CTRL_LADJ_2_SHIFT 22
901#define ENET_SERDES_CTRL_LADJ_3 0x000000000e000000ULL
902#define ENET_SERDES_CTRL_LADJ_3_SHIFT 25
903#define ENET_SERDES_CTRL_RXITERM_0 0x0000000010000000ULL
904#define ENET_SERDES_CTRL_RXITERM_1 0x0000000020000000ULL
905#define ENET_SERDES_CTRL_RXITERM_2 0x0000000040000000ULL
906#define ENET_SERDES_CTRL_RXITERM_3 0x0000000080000000ULL
907
908#define ENET_SERDES_0_TEST_CFG (FZC_MAC + 0x14020UL)
909#define ENET_SERDES_TEST_MD_0 0x0000000000000003ULL
910#define ENET_SERDES_TEST_MD_0_SHIFT 0
911#define ENET_SERDES_TEST_MD_1 0x000000000000000cULL
912#define ENET_SERDES_TEST_MD_1_SHIFT 2
913#define ENET_SERDES_TEST_MD_2 0x0000000000000030ULL
914#define ENET_SERDES_TEST_MD_2_SHIFT 4
915#define ENET_SERDES_TEST_MD_3 0x00000000000000c0ULL
916#define ENET_SERDES_TEST_MD_3_SHIFT 6
917
918#define ENET_TEST_MD_NO_LOOPBACK 0x0
919#define ENET_TEST_MD_EWRAP 0x1
920#define ENET_TEST_MD_PAD_LOOPBACK 0x2
921#define ENET_TEST_MD_REV_LOOPBACK 0x3
922
923#define ENET_SERDES_1_PLL_CFG (FZC_MAC + 0x14028UL)
924#define ENET_SERDES_1_CTRL_CFG (FZC_MAC + 0x14030UL)
925#define ENET_SERDES_1_TEST_CFG (FZC_MAC + 0x14038UL)
926
927#define ENET_RGMII_CFG_REG (FZC_MAC + 0x14040UL)
928
929#define ESR_INT_SIGNALS (FZC_MAC + 0x14800UL)
930#define ESR_INT_SIGNALS_ALL 0x00000000ffffffffULL
931#define ESR_INT_SIGNALS_P0_BITS 0x0000000033e0000fULL
932#define ESR_INT_SIGNALS_P1_BITS 0x000000000c1f00f0ULL
933#define ESR_INT_SRDY0_P0 0x0000000020000000ULL
934#define ESR_INT_DET0_P0 0x0000000010000000ULL
935#define ESR_INT_SRDY0_P1 0x0000000008000000ULL
936#define ESR_INT_DET0_P1 0x0000000004000000ULL
937#define ESR_INT_XSRDY_P0 0x0000000002000000ULL
938#define ESR_INT_XDP_P0_CH3 0x0000000001000000ULL
939#define ESR_INT_XDP_P0_CH2 0x0000000000800000ULL
940#define ESR_INT_XDP_P0_CH1 0x0000000000400000ULL
941#define ESR_INT_XDP_P0_CH0 0x0000000000200000ULL
942#define ESR_INT_XSRDY_P1 0x0000000000100000ULL
943#define ESR_INT_XDP_P1_CH3 0x0000000000080000ULL
944#define ESR_INT_XDP_P1_CH2 0x0000000000040000ULL
945#define ESR_INT_XDP_P1_CH1 0x0000000000020000ULL
946#define ESR_INT_XDP_P1_CH0 0x0000000000010000ULL
947#define ESR_INT_SLOSS_P1_CH3 0x0000000000000080ULL
948#define ESR_INT_SLOSS_P1_CH2 0x0000000000000040ULL
949#define ESR_INT_SLOSS_P1_CH1 0x0000000000000020ULL
950#define ESR_INT_SLOSS_P1_CH0 0x0000000000000010ULL
951#define ESR_INT_SLOSS_P0_CH3 0x0000000000000008ULL
952#define ESR_INT_SLOSS_P0_CH2 0x0000000000000004ULL
953#define ESR_INT_SLOSS_P0_CH1 0x0000000000000002ULL
954#define ESR_INT_SLOSS_P0_CH0 0x0000000000000001ULL
955
956#define ESR_DEBUG_SEL (FZC_MAC + 0x14808UL)
957#define ESR_DEBUG_SEL_VAL 0x000000000000003fULL
958
959/* SerDes registers behind MIF */
960#define NIU_ESR_DEV_ADDR 0x1e
961#define ESR_BASE 0x0000
962
963#define ESR_RXTX_COMM_CTRL_L (ESR_BASE + 0x0000)
964#define ESR_RXTX_COMM_CTRL_H (ESR_BASE + 0x0001)
965
966#define ESR_RXTX_RESET_CTRL_L (ESR_BASE + 0x0002)
967#define ESR_RXTX_RESET_CTRL_H (ESR_BASE + 0x0003)
968
969#define ESR_RX_POWER_CTRL_L (ESR_BASE + 0x0004)
970#define ESR_RX_POWER_CTRL_H (ESR_BASE + 0x0005)
971
972#define ESR_TX_POWER_CTRL_L (ESR_BASE + 0x0006)
973#define ESR_TX_POWER_CTRL_H (ESR_BASE + 0x0007)
974
975#define ESR_MISC_POWER_CTRL_L (ESR_BASE + 0x0008)
976#define ESR_MISC_POWER_CTRL_H (ESR_BASE + 0x0009)
977
978#define ESR_RXTX_CTRL_L(CHAN) (ESR_BASE + 0x0080 + (CHAN) * 0x10)
979#define ESR_RXTX_CTRL_H(CHAN) (ESR_BASE + 0x0081 + (CHAN) * 0x10)
980#define ESR_RXTX_CTRL_BIASCNTL 0x80000000
981#define ESR_RXTX_CTRL_RESV1 0x7c000000
982#define ESR_RXTX_CTRL_TDENFIFO 0x02000000
983#define ESR_RXTX_CTRL_TDWS20 0x01000000
984#define ESR_RXTX_CTRL_VMUXLO 0x00c00000
985#define ESR_RXTX_CTRL_VMUXLO_SHIFT 22
986#define ESR_RXTX_CTRL_VPULSELO 0x00300000
987#define ESR_RXTX_CTRL_VPULSELO_SHIFT 20
988#define ESR_RXTX_CTRL_RESV2 0x000f0000
989#define ESR_RXTX_CTRL_RESV3 0x0000c000
990#define ESR_RXTX_CTRL_RXPRESWIN 0x00003000
991#define ESR_RXTX_CTRL_RXPRESWIN_SHIFT 12
992#define ESR_RXTX_CTRL_RESV4 0x00000800
993#define ESR_RXTX_CTRL_RISEFALL 0x00000700
994#define ESR_RXTX_CTRL_RISEFALL_SHIFT 8
995#define ESR_RXTX_CTRL_RESV5 0x000000fe
996#define ESR_RXTX_CTRL_ENSTRETCH 0x00000001
997
998#define ESR_RXTX_TUNING_L(CHAN) (ESR_BASE + 0x0082 + (CHAN) * 0x10)
999#define ESR_RXTX_TUNING_H(CHAN) (ESR_BASE + 0x0083 + (CHAN) * 0x10)
1000
1001#define ESR_RX_SYNCCHAR_L(CHAN) (ESR_BASE + 0x0084 + (CHAN) * 0x10)
1002#define ESR_RX_SYNCCHAR_H(CHAN) (ESR_BASE + 0x0085 + (CHAN) * 0x10)
1003
1004#define ESR_RXTX_TEST_L(CHAN) (ESR_BASE + 0x0086 + (CHAN) * 0x10)
1005#define ESR_RXTX_TEST_H(CHAN) (ESR_BASE + 0x0087 + (CHAN) * 0x10)
1006
1007#define ESR_GLUE_CTRL0_L(CHAN) (ESR_BASE + 0x0088 + (CHAN) * 0x10)
1008#define ESR_GLUE_CTRL0_H(CHAN) (ESR_BASE + 0x0089 + (CHAN) * 0x10)
1009#define ESR_GLUE_CTRL0_RESV1 0xf8000000
1010#define ESR_GLUE_CTRL0_BLTIME 0x07000000
1011#define ESR_GLUE_CTRL0_BLTIME_SHIFT 24
1012#define ESR_GLUE_CTRL0_RESV2 0x00ff0000
1013#define ESR_GLUE_CTRL0_RXLOS_TEST 0x00008000
1014#define ESR_GLUE_CTRL0_RESV3 0x00004000
1015#define ESR_GLUE_CTRL0_RXLOSENAB 0x00002000
1016#define ESR_GLUE_CTRL0_FASTRESYNC 0x00001000
1017#define ESR_GLUE_CTRL0_SRATE 0x00000f00
1018#define ESR_GLUE_CTRL0_SRATE_SHIFT 8
1019#define ESR_GLUE_CTRL0_THCNT 0x000000ff
1020#define ESR_GLUE_CTRL0_THCNT_SHIFT 0
1021
1022#define BLTIME_64_CYCLES 0
1023#define BLTIME_128_CYCLES 1
1024#define BLTIME_256_CYCLES 2
1025#define BLTIME_300_CYCLES 3
1026#define BLTIME_384_CYCLES 4
1027#define BLTIME_512_CYCLES 5
1028#define BLTIME_1024_CYCLES 6
1029#define BLTIME_2048_CYCLES 7
1030
1031#define ESR_GLUE_CTRL1_L(CHAN) (ESR_BASE + 0x008a + (CHAN) * 0x10)
1032#define ESR_GLUE_CTRL1_H(CHAN) (ESR_BASE + 0x008b + (CHAN) * 0x10)
1033#define ESR_RXTX_TUNING1_L(CHAN) (ESR_BASE + 0x00c2 + (CHAN) * 0x10)
1034#define ESR_RXTX_TUNING1_H(CHAN) (ESR_BASE + 0x00c2 + (CHAN) * 0x10)
1035#define ESR_RXTX_TUNING2_L(CHAN) (ESR_BASE + 0x0102 + (CHAN) * 0x10)
1036#define ESR_RXTX_TUNING2_H(CHAN) (ESR_BASE + 0x0102 + (CHAN) * 0x10)
1037#define ESR_RXTX_TUNING3_L(CHAN) (ESR_BASE + 0x0142 + (CHAN) * 0x10)
1038#define ESR_RXTX_TUNING3_H(CHAN) (ESR_BASE + 0x0142 + (CHAN) * 0x10)
1039
1040#define NIU_ESR2_DEV_ADDR 0x1e
1041#define ESR2_BASE 0x8000
1042
1043#define ESR2_TI_PLL_CFG_L (ESR2_BASE + 0x000)
1044#define ESR2_TI_PLL_CFG_H (ESR2_BASE + 0x001)
1045#define PLL_CFG_STD 0x00000c00
1046#define PLL_CFG_STD_SHIFT 10
1047#define PLL_CFG_LD 0x00000300
1048#define PLL_CFG_LD_SHIFT 8
1049#define PLL_CFG_MPY 0x0000001e
1050#define PLL_CFG_MPY_SHIFT 1
1051#define PLL_CFG_ENPLL 0x00000001
1052
1053#define ESR2_TI_PLL_STS_L (ESR2_BASE + 0x002)
1054#define ESR2_TI_PLL_STS_H (ESR2_BASE + 0x003)
1055#define PLL_STS_LOCK 0x00000001
1056
1057#define ESR2_TI_PLL_TEST_CFG_L (ESR2_BASE + 0x004)
1058#define ESR2_TI_PLL_TEST_CFG_H (ESR2_BASE + 0x005)
1059#define PLL_TEST_INVPATT 0x00004000
1060#define PLL_TEST_RATE 0x00003000
1061#define PLL_TEST_RATE_SHIFT 12
1062#define PLL_TEST_CFG_ENBSAC 0x00000400
1063#define PLL_TEST_CFG_ENBSRX 0x00000200
1064#define PLL_TEST_CFG_ENBSTX 0x00000100
1065#define PLL_TEST_CFG_LOOPBACK_PAD 0x00000040
1066#define PLL_TEST_CFG_LOOPBACK_CML_DIS 0x00000080
1067#define PLL_TEST_CFG_LOOPBACK_CML_EN 0x000000c0
1068#define PLL_TEST_CFG_CLKBYP 0x00000030
1069#define PLL_TEST_CFG_CLKBYP_SHIFT 4
1070#define PLL_TEST_CFG_EN_RXPATT 0x00000008
1071#define PLL_TEST_CFG_EN_TXPATT 0x00000004
1072#define PLL_TEST_CFG_TPATT 0x00000003
1073#define PLL_TEST_CFG_TPATT_SHIFT 0
1074
1075#define ESR2_TI_PLL_TX_CFG_L(CHAN) (ESR2_BASE + 0x100 + (CHAN) * 4)
1076#define ESR2_TI_PLL_TX_CFG_H(CHAN) (ESR2_BASE + 0x101 + (CHAN) * 4)
1077#define PLL_TX_CFG_RDTCT 0x00600000
1078#define PLL_TX_CFG_RDTCT_SHIFT 21
1079#define PLL_TX_CFG_ENIDL 0x00100000
1080#define PLL_TX_CFG_BSTX 0x00020000
1081#define PLL_TX_CFG_ENFTP 0x00010000
1082#define PLL_TX_CFG_DE 0x0000f000
1083#define PLL_TX_CFG_DE_SHIFT 12
1084#define PLL_TX_CFG_SWING_125MV 0x00000000
1085#define PLL_TX_CFG_SWING_250MV 0x00000200
1086#define PLL_TX_CFG_SWING_500MV 0x00000400
1087#define PLL_TX_CFG_SWING_625MV 0x00000600
1088#define PLL_TX_CFG_SWING_750MV 0x00000800
1089#define PLL_TX_CFG_SWING_1000MV 0x00000a00
1090#define PLL_TX_CFG_SWING_1250MV 0x00000c00
1091#define PLL_TX_CFG_SWING_1375MV 0x00000e00
1092#define PLL_TX_CFG_CM 0x00000100
1093#define PLL_TX_CFG_INVPAIR 0x00000080
1094#define PLL_TX_CFG_RATE 0x00000060
1095#define PLL_TX_CFG_RATE_SHIFT 5
1096#define PLL_TX_CFG_BUSWIDTH 0x0000001c
1097#define PLL_TX_CFG_BUSWIDTH_SHIFT 2
1098#define PLL_TX_CFG_ENTEST 0x00000002
1099#define PLL_TX_CFG_ENTX 0x00000001
1100
1101#define ESR2_TI_PLL_TX_STS_L(CHAN) (ESR2_BASE + 0x102 + (CHAN) * 4)
1102#define ESR2_TI_PLL_TX_STS_H(CHAN) (ESR2_BASE + 0x103 + (CHAN) * 4)
1103#define PLL_TX_STS_RDTCTIP 0x00000002
1104#define PLL_TX_STS_TESTFAIL 0x00000001
1105
1106#define ESR2_TI_PLL_RX_CFG_L(CHAN) (ESR2_BASE + 0x120 + (CHAN) * 4)
1107#define ESR2_TI_PLL_RX_CFG_H(CHAN) (ESR2_BASE + 0x121 + (CHAN) * 4)
1108#define PLL_RX_CFG_BSINRXN 0x02000000
1109#define PLL_RX_CFG_BSINRXP 0x01000000
1110#define PLL_RX_CFG_EQ_MAX_LF 0x00000000
1111#define PLL_RX_CFG_EQ_LP_ADAPTIVE 0x00080000
1112#define PLL_RX_CFG_EQ_LP_1084MHZ 0x00400000
1113#define PLL_RX_CFG_EQ_LP_805MHZ 0x00480000
1114#define PLL_RX_CFG_EQ_LP_573MHZ 0x00500000
1115#define PLL_RX_CFG_EQ_LP_402MHZ 0x00580000
1116#define PLL_RX_CFG_EQ_LP_304MHZ 0x00600000
1117#define PLL_RX_CFG_EQ_LP_216MHZ 0x00680000
1118#define PLL_RX_CFG_EQ_LP_156MHZ 0x00700000
1119#define PLL_RX_CFG_EQ_LP_135MHZ 0x00780000
1120#define PLL_RX_CFG_EQ_SHIFT 19
1121#define PLL_RX_CFG_CDR 0x00070000
1122#define PLL_RX_CFG_CDR_SHIFT 16
1123#define PLL_RX_CFG_LOS_DIS 0x00000000
1124#define PLL_RX_CFG_LOS_HTHRESH 0x00004000
1125#define PLL_RX_CFG_LOS_LTHRESH 0x00008000
1126#define PLL_RX_CFG_ALIGN_DIS 0x00000000
1127#define PLL_RX_CFG_ALIGN_ENA 0x00001000
1128#define PLL_RX_CFG_ALIGN_JOG 0x00002000
1129#define PLL_RX_CFG_TERM_VDDT 0x00000000
1130#define PLL_RX_CFG_TERM_0P8VDDT 0x00000100
1131#define PLL_RX_CFG_TERM_FLOAT 0x00000300
1132#define PLL_RX_CFG_INVPAIR 0x00000080
1133#define PLL_RX_CFG_RATE 0x00000060
1134#define PLL_RX_CFG_RATE_SHIFT 5
1135#define PLL_RX_CFG_BUSWIDTH 0x0000001c
1136#define PLL_RX_CFG_BUSWIDTH_SHIFT 2
1137#define PLL_RX_CFG_ENTEST 0x00000002
1138#define PLL_RX_CFG_ENRX 0x00000001
1139
1140#define ESR2_TI_PLL_RX_STS_L(CHAN) (ESR2_BASE + 0x122 + (CHAN) * 4)
1141#define ESR2_TI_PLL_RX_STS_H(CHAN) (ESR2_BASE + 0x123 + (CHAN) * 4)
1142#define PLL_RX_STS_CRCIDTCT 0x00000200
1143#define PLL_RX_STS_CWDTCT 0x00000100
1144#define PLL_RX_STS_BSRXN 0x00000020
1145#define PLL_RX_STS_BSRXP 0x00000010
1146#define PLL_RX_STS_LOSDTCT 0x00000008
1147#define PLL_RX_STS_ODDCG 0x00000004
1148#define PLL_RX_STS_SYNC 0x00000002
1149#define PLL_RX_STS_TESTFAIL 0x00000001
1150
1151#define ENET_VLAN_TBL(IDX) (FZC_FFLP + 0x00000UL + (IDX) * 8UL)
1152#define ENET_VLAN_TBL_PARITY1 0x0000000000020000ULL
1153#define ENET_VLAN_TBL_PARITY0 0x0000000000010000ULL
1154#define ENET_VLAN_TBL_VPR 0x0000000000000008ULL
1155#define ENET_VLAN_TBL_VLANRDCTBLN 0x0000000000000007ULL
1156#define ENET_VLAN_TBL_SHIFT(PORT) ((PORT) * 4)
1157
1158#define ENET_VLAN_TBL_NUM_ENTRIES 4096
1159
1160#define FFLP_VLAN_PAR_ERR (FZC_FFLP + 0x0800UL)
1161#define FFLP_VLAN_PAR_ERR_ERR 0x0000000080000000ULL
1162#define FFLP_VLAN_PAR_ERR_M_ERR 0x0000000040000000ULL
1163#define FFLP_VLAN_PAR_ERR_ADDR 0x000000003ffc0000ULL
1164#define FFLP_VLAN_PAR_ERR_DATA 0x000000000003ffffULL
1165
1166#define L2_CLS(IDX) (FZC_FFLP + 0x20000UL + (IDX) * 8UL)
1167#define L2_CLS_VLD 0x0000000000010000ULL
1168#define L2_CLS_ETYPE 0x000000000000ffffULL
1169#define L2_CLS_ETYPE_SHIFT 0
1170
1171#define L3_CLS(IDX) (FZC_FFLP + 0x20010UL + (IDX) * 8UL)
1172#define L3_CLS_VALID 0x0000000002000000ULL
1173#define L3_CLS_IPVER 0x0000000001000000ULL
1174#define L3_CLS_PID 0x0000000000ff0000ULL
1175#define L3_CLS_PID_SHIFT 16
1176#define L3_CLS_TOSMASK 0x000000000000ff00ULL
1177#define L3_CLS_TOSMASK_SHIFT 8
1178#define L3_CLS_TOS 0x00000000000000ffULL
1179#define L3_CLS_TOS_SHIFT 0
1180
1181#define TCAM_KEY(IDX) (FZC_FFLP + 0x20030UL + (IDX) * 8UL)
1182#define TCAM_KEY_DISC 0x0000000000000008ULL
1183#define TCAM_KEY_TSEL 0x0000000000000004ULL
1184#define TCAM_KEY_IPADDR 0x0000000000000001ULL
1185
1186#define TCAM_KEY_0 (FZC_FFLP + 0x20090UL)
1187#define TCAM_KEY_0_KEY 0x00000000000000ffULL /* bits 192-199 */
1188
1189#define TCAM_KEY_1 (FZC_FFLP + 0x20098UL)
1190#define TCAM_KEY_1_KEY 0xffffffffffffffffULL /* bits 128-191 */
1191
1192#define TCAM_KEY_2 (FZC_FFLP + 0x200a0UL)
1193#define TCAM_KEY_2_KEY 0xffffffffffffffffULL /* bits 64-127 */
1194
1195#define TCAM_KEY_3 (FZC_FFLP + 0x200a8UL)
1196#define TCAM_KEY_3_KEY 0xffffffffffffffffULL /* bits 0-63 */
1197
1198#define TCAM_KEY_MASK_0 (FZC_FFLP + 0x200b0UL)
1199#define TCAM_KEY_MASK_0_KEY_SEL 0x00000000000000ffULL /* bits 192-199 */
1200
1201#define TCAM_KEY_MASK_1 (FZC_FFLP + 0x200b8UL)
1202#define TCAM_KEY_MASK_1_KEY_SEL 0xffffffffffffffffULL /* bits 128-191 */
1203
1204#define TCAM_KEY_MASK_2 (FZC_FFLP + 0x200c0UL)
1205#define TCAM_KEY_MASK_2_KEY_SEL 0xffffffffffffffffULL /* bits 64-127 */
1206
1207#define TCAM_KEY_MASK_3 (FZC_FFLP + 0x200c8UL)
1208#define TCAM_KEY_MASK_3_KEY_SEL 0xffffffffffffffffULL /* bits 0-63 */
1209
1210#define TCAM_CTL (FZC_FFLP + 0x200d0UL)
1211#define TCAM_CTL_RWC 0x00000000001c0000ULL
1212#define TCAM_CTL_RWC_TCAM_WRITE 0x0000000000000000ULL
1213#define TCAM_CTL_RWC_TCAM_READ 0x0000000000040000ULL
1214#define TCAM_CTL_RWC_TCAM_COMPARE 0x0000000000080000ULL
1215#define TCAM_CTL_RWC_RAM_WRITE 0x0000000000100000ULL
1216#define TCAM_CTL_RWC_RAM_READ 0x0000000000140000ULL
1217#define TCAM_CTL_STAT 0x0000000000020000ULL
1218#define TCAM_CTL_MATCH 0x0000000000010000ULL
1219#define TCAM_CTL_LOC 0x00000000000003ffULL
1220
1221#define TCAM_ERR (FZC_FFLP + 0x200d8UL)
1222#define TCAM_ERR_ERR 0x0000000080000000ULL
1223#define TCAM_ERR_P_ECC 0x0000000040000000ULL
1224#define TCAM_ERR_MULT 0x0000000020000000ULL
1225#define TCAM_ERR_ADDR 0x0000000000ff0000ULL
1226#define TCAM_ERR_SYNDROME 0x000000000000ffffULL
1227
1228#define HASH_LOOKUP_ERR_LOG1 (FZC_FFLP + 0x200e0UL)
1229#define HASH_LOOKUP_ERR_LOG1_ERR 0x0000000000000008ULL
1230#define HASH_LOOKUP_ERR_LOG1_MULT_LK 0x0000000000000004ULL
1231#define HASH_LOOKUP_ERR_LOG1_CU 0x0000000000000002ULL
1232#define HASH_LOOKUP_ERR_LOG1_MULT_BIT 0x0000000000000001ULL
1233
1234#define HASH_LOOKUP_ERR_LOG2 (FZC_FFLP + 0x200e8UL)
1235#define HASH_LOOKUP_ERR_LOG2_H1 0x000000007ffff800ULL
1236#define HASH_LOOKUP_ERR_LOG2_SUBAREA 0x0000000000000700ULL
1237#define HASH_LOOKUP_ERR_LOG2_SYNDROME 0x00000000000000ffULL
1238
1239#define FFLP_CFG_1 (FZC_FFLP + 0x20100UL)
1240#define FFLP_CFG_1_TCAM_DIS 0x0000000004000000ULL
1241#define FFLP_CFG_1_PIO_DBG_SEL 0x0000000003800000ULL
1242#define FFLP_CFG_1_PIO_FIO_RST 0x0000000000400000ULL
1243#define FFLP_CFG_1_PIO_FIO_LAT 0x0000000000300000ULL
1244#define FFLP_CFG_1_CAMLAT 0x00000000000f0000ULL
1245#define FFLP_CFG_1_CAMLAT_SHIFT 16
1246#define FFLP_CFG_1_CAMRATIO 0x000000000000f000ULL
1247#define FFLP_CFG_1_CAMRATIO_SHIFT 12
1248#define FFLP_CFG_1_FCRAMRATIO 0x0000000000000f00ULL
1249#define FFLP_CFG_1_FCRAMRATIO_SHIFT 8
1250#define FFLP_CFG_1_FCRAMOUTDR_MASK 0x00000000000000f0ULL
1251#define FFLP_CFG_1_FCRAMOUTDR_NORMAL 0x0000000000000000ULL
1252#define FFLP_CFG_1_FCRAMOUTDR_STRONG 0x0000000000000050ULL
1253#define FFLP_CFG_1_FCRAMOUTDR_WEAK 0x00000000000000a0ULL
1254#define FFLP_CFG_1_FCRAMQS 0x0000000000000008ULL
1255#define FFLP_CFG_1_ERRORDIS 0x0000000000000004ULL
1256#define FFLP_CFG_1_FFLPINITDONE 0x0000000000000002ULL
1257#define FFLP_CFG_1_LLCSNAP 0x0000000000000001ULL
1258
1259#define DEFAULT_FCRAMRATIO 10
1260
1261#define DEFAULT_TCAM_LATENCY 4
1262#define DEFAULT_TCAM_ACCESS_RATIO 10
1263
1264#define TCP_CFLAG_MSK (FZC_FFLP + 0x20108UL)
1265#define TCP_CFLAG_MSK_MASK 0x0000000000000fffULL
1266
1267#define FCRAM_REF_TMR (FZC_FFLP + 0x20110UL)
1268#define FCRAM_REF_TMR_MAX 0x00000000ffff0000ULL
1269#define FCRAM_REF_TMR_MAX_SHIFT 16
1270#define FCRAM_REF_TMR_MIN 0x000000000000ffffULL
1271#define FCRAM_REF_TMR_MIN_SHIFT 0
1272
1273#define DEFAULT_FCRAM_REFRESH_MAX 512
1274#define DEFAULT_FCRAM_REFRESH_MIN 512
1275
1276#define FCRAM_FIO_ADDR (FZC_FFLP + 0x20118UL)
1277#define FCRAM_FIO_ADDR_ADDR 0x00000000000000ffULL
1278
1279#define FCRAM_FIO_DAT (FZC_FFLP + 0x20120UL)
1280#define FCRAM_FIO_DAT_DATA 0x000000000000ffffULL
1281
1282#define FCRAM_ERR_TST0 (FZC_FFLP + 0x20128UL)
1283#define FCRAM_ERR_TST0_SYND 0x00000000000000ffULL
1284
1285#define FCRAM_ERR_TST1 (FZC_FFLP + 0x20130UL)
1286#define FCRAM_ERR_TST1_DAT 0x00000000ffffffffULL
1287
1288#define FCRAM_ERR_TST2 (FZC_FFLP + 0x20138UL)
1289#define FCRAM_ERR_TST2_DAT 0x00000000ffffffffULL
1290
1291#define FFLP_ERR_MASK (FZC_FFLP + 0x20140UL)
1292#define FFLP_ERR_MASK_HSH_TBL_DAT 0x00000000000007f8ULL
1293#define FFLP_ERR_MASK_HSH_TBL_LKUP 0x0000000000000004ULL
1294#define FFLP_ERR_MASK_TCAM 0x0000000000000002ULL
1295#define FFLP_ERR_MASK_VLAN 0x0000000000000001ULL
1296
1297#define FFLP_DBG_TRAIN_VCT (FZC_FFLP + 0x20148UL)
1298#define FFLP_DBG_TRAIN_VCT_VECTOR 0x00000000ffffffffULL
1299
1300#define FCRAM_PHY_RD_LAT (FZC_FFLP + 0x20150UL)
1301#define FCRAM_PHY_RD_LAT_LAT 0x00000000000000ffULL
1302
1303/* Ethernet TCAM format */
1304#define TCAM_ETHKEY0_RESV1 0xffffffffffffff00ULL
1305#define TCAM_ETHKEY0_CLASS_CODE 0x00000000000000f8ULL
1306#define TCAM_ETHKEY0_CLASS_CODE_SHIFT 3
1307#define TCAM_ETHKEY0_RESV2 0x0000000000000007ULL
1308#define TCAM_ETHKEY1_FRAME_BYTE0_7(NUM) (0xff << ((7 - NUM) * 8))
1309#define TCAM_ETHKEY2_FRAME_BYTE8 0xff00000000000000ULL
1310#define TCAM_ETHKEY2_FRAME_BYTE8_SHIFT 56
1311#define TCAM_ETHKEY2_FRAME_BYTE9 0x00ff000000000000ULL
1312#define TCAM_ETHKEY2_FRAME_BYTE9_SHIFT 48
1313#define TCAM_ETHKEY2_FRAME_BYTE10 0x0000ff0000000000ULL
1314#define TCAM_ETHKEY2_FRAME_BYTE10_SHIFT 40
1315#define TCAM_ETHKEY2_FRAME_RESV 0x000000ffffffffffULL
1316#define TCAM_ETHKEY3_FRAME_RESV 0xffffffffffffffffULL
1317
1318/* IPV4 TCAM format */
1319#define TCAM_V4KEY0_RESV1 0xffffffffffffff00ULL
1320#define TCAM_V4KEY0_CLASS_CODE 0x00000000000000f8ULL
1321#define TCAM_V4KEY0_CLASS_CODE_SHIFT 3
1322#define TCAM_V4KEY0_RESV2 0x0000000000000007ULL
1323#define TCAM_V4KEY1_L2RDCNUM 0xf800000000000000ULL
1324#define TCAM_V4KEY1_L2RDCNUM_SHIFT 59
1325#define TCAM_V4KEY1_NOPORT 0x0400000000000000ULL
1326#define TCAM_V4KEY1_RESV 0x03ffffffffffffffULL
1327#define TCAM_V4KEY2_RESV 0xffff000000000000ULL
1328#define TCAM_V4KEY2_TOS 0x0000ff0000000000ULL
1329#define TCAM_V4KEY2_TOS_SHIFT 40
1330#define TCAM_V4KEY2_PROTO 0x000000ff00000000ULL
1331#define TCAM_V4KEY2_PROTO_SHIFT 32
1332#define TCAM_V4KEY2_PORT_SPI 0x00000000ffffffffULL
1333#define TCAM_V4KEY2_PORT_SPI_SHIFT 0
1334#define TCAM_V4KEY3_SADDR 0xffffffff00000000ULL
1335#define TCAM_V4KEY3_SADDR_SHIFT 32
1336#define TCAM_V4KEY3_DADDR 0x00000000ffffffffULL
1337#define TCAM_V4KEY3_DADDR_SHIFT 0
1338
1339/* IPV6 TCAM format */
1340#define TCAM_V6KEY0_RESV1 0xffffffffffffff00ULL
1341#define TCAM_V6KEY0_CLASS_CODE 0x00000000000000f8ULL
1342#define TCAM_V6KEY0_CLASS_CODE_SHIFT 3
1343#define TCAM_V6KEY0_RESV2 0x0000000000000007ULL
1344#define TCAM_V6KEY1_L2RDCNUM 0xf800000000000000ULL
1345#define TCAM_V6KEY1_L2RDCNUM_SHIFT 59
1346#define TCAM_V6KEY1_NOPORT 0x0400000000000000ULL
1347#define TCAM_V6KEY1_RESV 0x03ff000000000000ULL
1348#define TCAM_V6KEY1_TOS 0x0000ff0000000000ULL
1349#define TCAM_V6KEY1_TOS_SHIFT 40
1350#define TCAM_V6KEY1_NEXT_HDR 0x000000ff00000000ULL
1351#define TCAM_V6KEY1_NEXT_HDR_SHIFT 32
1352#define TCAM_V6KEY1_PORT_SPI 0x00000000ffffffffULL
1353#define TCAM_V6KEY1_PORT_SPI_SHIFT 0
1354#define TCAM_V6KEY2_ADDR_HIGH 0xffffffffffffffffULL
1355#define TCAM_V6KEY3_ADDR_LOW 0xffffffffffffffffULL
1356
1357#define TCAM_ASSOCDATA_SYNDROME 0x000003fffc000000ULL
1358#define TCAM_ASSOCDATA_SYNDROME_SHIFT 26
1359#define TCAM_ASSOCDATA_ZFID 0x0000000003ffc000ULL
1360#define TCAM_ASSOCDATA_ZFID_SHIFT 14
1361#define TCAM_ASSOCDATA_V4_ECC_OK 0x0000000000002000ULL
1362#define TCAM_ASSOCDATA_DISC 0x0000000000001000ULL
1363#define TCAM_ASSOCDATA_TRES_MASK 0x0000000000000c00ULL
1364#define TCAM_ASSOCDATA_TRES_USE_L2RDC 0x0000000000000000ULL
1365#define TCAM_ASSOCDATA_TRES_USE_OFFSET 0x0000000000000400ULL
1366#define TCAM_ASSOCDATA_TRES_OVR_RDC 0x0000000000000800ULL
1367#define TCAM_ASSOCDATA_TRES_OVR_RDC_OFF 0x0000000000000c00ULL
1368#define TCAM_ASSOCDATA_RDCTBL 0x0000000000000380ULL
1369#define TCAM_ASSOCDATA_RDCTBL_SHIFT 7
1370#define TCAM_ASSOCDATA_OFFSET 0x000000000000007cULL
1371#define TCAM_ASSOCDATA_OFFSET_SHIFT 2
1372#define TCAM_ASSOCDATA_ZFVLD 0x0000000000000002ULL
1373#define TCAM_ASSOCDATA_AGE 0x0000000000000001ULL
1374
1375#define FLOW_KEY(IDX) (FZC_FFLP + 0x40000UL + (IDX) * 8UL)
1376#define FLOW_KEY_PORT 0x0000000000000200ULL
1377#define FLOW_KEY_L2DA 0x0000000000000100ULL
1378#define FLOW_KEY_VLAN 0x0000000000000080ULL
1379#define FLOW_KEY_IPSA 0x0000000000000040ULL
1380#define FLOW_KEY_IPDA 0x0000000000000020ULL
1381#define FLOW_KEY_PROTO 0x0000000000000010ULL
1382#define FLOW_KEY_L4_0 0x000000000000000cULL
1383#define FLOW_KEY_L4_0_SHIFT 2
1384#define FLOW_KEY_L4_1 0x0000000000000003ULL
1385#define FLOW_KEY_L4_1_SHIFT 0
1386
1387#define FLOW_KEY_L4_NONE 0x0
1388#define FLOW_KEY_L4_RESV 0x1
1389#define FLOW_KEY_L4_BYTE12 0x2
1390#define FLOW_KEY_L4_BYTE56 0x3
1391
1392#define H1POLY (FZC_FFLP + 0x40060UL)
1393#define H1POLY_INITVAL 0x00000000ffffffffULL
1394
1395#define H2POLY (FZC_FFLP + 0x40068UL)
1396#define H2POLY_INITVAL 0x000000000000ffffULL
1397
1398#define FLW_PRT_SEL(IDX) (FZC_FFLP + 0x40070UL + (IDX) * 8UL)
1399#define FLW_PRT_SEL_EXT 0x0000000000010000ULL
1400#define FLW_PRT_SEL_MASK 0x0000000000001f00ULL
1401#define FLW_PRT_SEL_MASK_SHIFT 8
1402#define FLW_PRT_SEL_BASE 0x000000000000001fULL
1403#define FLW_PRT_SEL_BASE_SHIFT 0
1404
1405#define HASH_TBL_ADDR(IDX) (FFLP + 0x00000UL + (IDX) * 8192UL)
1406#define HASH_TBL_ADDR_AUTOINC 0x0000000000800000ULL
1407#define HASH_TBL_ADDR_ADDR 0x00000000007fffffULL
1408
1409#define HASH_TBL_DATA(IDX) (FFLP + 0x00008UL + (IDX) * 8192UL)
1410#define HASH_TBL_DATA_DATA 0xffffffffffffffffULL
1411
1412/* FCRAM hash table entries are up to 8 64-bit words in size.
1413 * The layout of each entry is determined by the settings in the
1414 * first word, which is the header.
1415 *
1416 * The indexing is controllable per partition (there is one partition
1417 * per RDC group, thus a total of eight) using the BASE and MASK fields
1418 * of FLW_PRT_SEL above.
1419 */
1420#define FCRAM_SIZE 0x800000
1421#define FCRAM_NUM_PARTITIONS 8
1422
1423/* Generic HASH entry header, used for all non-optimized formats. */
1424#define HASH_HEADER_FMT 0x8000000000000000ULL
1425#define HASH_HEADER_EXT 0x4000000000000000ULL
1426#define HASH_HEADER_VALID 0x2000000000000000ULL
1427#define HASH_HEADER_RESVD 0x1000000000000000ULL
1428#define HASH_HEADER_L2_DADDR 0x0ffffffffffff000ULL
1429#define HASH_HEADER_L2_DADDR_SHIFT 12
1430#define HASH_HEADER_VLAN 0x0000000000000fffULL
1431#define HASH_HEADER_VLAN_SHIFT 0
1432
1433/* Optimized format, just a header with a special layout defined below.
1434 * Set FMT and EXT both to zero to indicate this layout is being used.
1435 */
1436#define HASH_OPT_HEADER_FMT 0x8000000000000000ULL
1437#define HASH_OPT_HEADER_EXT 0x4000000000000000ULL
1438#define HASH_OPT_HEADER_VALID 0x2000000000000000ULL
1439#define HASH_OPT_HEADER_RDCOFF 0x1f00000000000000ULL
1440#define HASH_OPT_HEADER_RDCOFF_SHIFT 56
1441#define HASH_OPT_HEADER_HASH2 0x00ffff0000000000ULL
1442#define HASH_OPT_HEADER_HASH2_SHIFT 40
1443#define HASH_OPT_HEADER_RESVD 0x000000ff00000000ULL
1444#define HASH_OPT_HEADER_USERINFO 0x00000000ffffffffULL
1445#define HASH_OPT_HEADER_USERINFO_SHIFT 0
1446
1447/* Port and protocol word used for ipv4 and ipv6 layouts. */
1448#define HASH_PORT_DPORT 0xffff000000000000ULL
1449#define HASH_PORT_DPORT_SHIFT 48
1450#define HASH_PORT_SPORT 0x0000ffff00000000ULL
1451#define HASH_PORT_SPORT_SHIFT 32
1452#define HASH_PORT_PROTO 0x00000000ff000000ULL
1453#define HASH_PORT_PROTO_SHIFT 24
1454#define HASH_PORT_PORT_OFF 0x0000000000c00000ULL
1455#define HASH_PORT_PORT_OFF_SHIFT 22
1456#define HASH_PORT_PORT_RESV 0x00000000003fffffULL
1457
1458/* Action word used for ipv4 and ipv6 layouts. */
1459#define HASH_ACTION_RESV1 0xe000000000000000ULL
1460#define HASH_ACTION_RDCOFF 0x1f00000000000000ULL
1461#define HASH_ACTION_RDCOFF_SHIFT 56
1462#define HASH_ACTION_ZFVALID 0x0080000000000000ULL
1463#define HASH_ACTION_RESV2 0x0070000000000000ULL
1464#define HASH_ACTION_ZFID 0x000fff0000000000ULL
1465#define HASH_ACTION_ZFID_SHIFT 40
1466#define HASH_ACTION_RESV3 0x000000ff00000000ULL
1467#define HASH_ACTION_USERINFO 0x00000000ffffffffULL
1468#define HASH_ACTION_USERINFO_SHIFT 0
1469
1470/* IPV4 address word. Addresses are in network endian. */
1471#define HASH_IP4ADDR_SADDR 0xffffffff00000000ULL
1472#define HASH_IP4ADDR_SADDR_SHIFT 32
1473#define HASH_IP4ADDR_DADDR 0x00000000ffffffffULL
1474#define HASH_IP4ADDR_DADDR_SHIFT 0
1475
1476/* IPV6 address layout is 4 words, first two are saddr, next two
1477 * are daddr. Addresses are in network endian.
1478 */
1479
1480struct fcram_hash_opt {
1481 u64 header;
1482};
1483
1484/* EXT=1, FMT=0 */
1485struct fcram_hash_ipv4 {
1486 u64 header;
1487 u64 addrs;
1488 u64 ports;
1489 u64 action;
1490};
1491
1492/* EXT=1, FMT=1 */
1493struct fcram_hash_ipv6 {
1494 u64 header;
1495 u64 addrs[4];
1496 u64 ports;
1497 u64 action;
1498};
1499
1500#define HASH_TBL_DATA_LOG(IDX) (FFLP + 0x00010UL + (IDX) * 8192UL)
1501#define HASH_TBL_DATA_LOG_ERR 0x0000000080000000ULL
1502#define HASH_TBL_DATA_LOG_ADDR 0x000000007fffff00ULL
1503#define HASH_TBL_DATA_LOG_SYNDROME 0x00000000000000ffULL
1504
1505#define RX_DMA_CK_DIV (FZC_DMC + 0x00000UL)
1506#define RX_DMA_CK_DIV_CNT 0x000000000000ffffULL
1507
1508#define DEF_RDC(IDX) (FZC_DMC + 0x00008UL + (IDX) * 0x8UL)
1509#define DEF_RDC_VAL 0x000000000000001fULL
1510
1511#define PT_DRR_WT(IDX) (FZC_DMC + 0x00028UL + (IDX) * 0x8UL)
1512#define PT_DRR_WT_VAL 0x000000000000ffffULL
1513
1514#define PT_DRR_WEIGHT_DEFAULT_10G 0x0400
1515#define PT_DRR_WEIGHT_DEFAULT_1G 0x0066
1516
1517#define PT_USE(IDX) (FZC_DMC + 0x00048UL + (IDX) * 0x8UL)
1518#define PT_USE_CNT 0x00000000000fffffULL
1519
1520#define RED_RAN_INIT (FZC_DMC + 0x00068UL)
1521#define RED_RAN_INIT_OPMODE 0x0000000000010000ULL
1522#define RED_RAN_INIT_VAL 0x000000000000ffffULL
1523
1524#define RX_ADDR_MD (FZC_DMC + 0x00070UL)
1525#define RX_ADDR_MD_DBG_PT_MUX_SEL 0x000000000000000cULL
1526#define RX_ADDR_MD_RAM_ACC 0x0000000000000002ULL
1527#define RX_ADDR_MD_MODE32 0x0000000000000001ULL
1528
1529#define RDMC_PRE_PAR_ERR (FZC_DMC + 0x00078UL)
1530#define RDMC_PRE_PAR_ERR_ERR 0x0000000000008000ULL
1531#define RDMC_PRE_PAR_ERR_MERR 0x0000000000004000ULL
1532#define RDMC_PRE_PAR_ERR_ADDR 0x00000000000000ffULL
1533
1534#define RDMC_SHA_PAR_ERR (FZC_DMC + 0x00080UL)
1535#define RDMC_SHA_PAR_ERR_ERR 0x0000000000008000ULL
1536#define RDMC_SHA_PAR_ERR_MERR 0x0000000000004000ULL
1537#define RDMC_SHA_PAR_ERR_ADDR 0x00000000000000ffULL
1538
1539#define RDMC_MEM_ADDR (FZC_DMC + 0x00088UL)
1540#define RDMC_MEM_ADDR_PRE_SHAD 0x0000000000000100ULL
1541#define RDMC_MEM_ADDR_ADDR 0x00000000000000ffULL
1542
1543#define RDMC_MEM_DAT0 (FZC_DMC + 0x00090UL)
1544#define RDMC_MEM_DAT0_DATA 0x00000000ffffffffULL /* bits 31:0 */
1545
1546#define RDMC_MEM_DAT1 (FZC_DMC + 0x00098UL)
1547#define RDMC_MEM_DAT1_DATA 0x00000000ffffffffULL /* bits 63:32 */
1548
1549#define RDMC_MEM_DAT2 (FZC_DMC + 0x000a0UL)
1550#define RDMC_MEM_DAT2_DATA 0x00000000ffffffffULL /* bits 95:64 */
1551
1552#define RDMC_MEM_DAT3 (FZC_DMC + 0x000a8UL)
1553#define RDMC_MEM_DAT3_DATA 0x00000000ffffffffULL /* bits 127:96 */
1554
1555#define RDMC_MEM_DAT4 (FZC_DMC + 0x000b0UL)
1556#define RDMC_MEM_DAT4_DATA 0x00000000000fffffULL /* bits 147:128 */
1557
1558#define RX_CTL_DAT_FIFO_STAT (FZC_DMC + 0x000b8UL)
1559#define RX_CTL_DAT_FIFO_STAT_ID_MISMATCH 0x0000000000000100ULL
1560#define RX_CTL_DAT_FIFO_STAT_ZCP_EOP_ERR 0x00000000000000f0ULL
1561#define RX_CTL_DAT_FIFO_STAT_IPP_EOP_ERR 0x000000000000000fULL
1562
1563#define RX_CTL_DAT_FIFO_MASK (FZC_DMC + 0x000c0UL)
1564#define RX_CTL_DAT_FIFO_MASK_ID_MISMATCH 0x0000000000000100ULL
1565#define RX_CTL_DAT_FIFO_MASK_ZCP_EOP_ERR 0x00000000000000f0ULL
1566#define RX_CTL_DAT_FIFO_MASK_IPP_EOP_ERR 0x000000000000000fULL
1567
1568#define RDMC_TRAINING_VECTOR (FZC_DMC + 0x000c8UL)
1569#define RDMC_TRAINING_VECTOR_TRAINING_VECTOR 0x00000000ffffffffULL
1570
1571#define RX_CTL_DAT_FIFO_STAT_DBG (FZC_DMC + 0x000d0UL)
1572#define RX_CTL_DAT_FIFO_STAT_DBG_ID_MISMATCH 0x0000000000000100ULL
1573#define RX_CTL_DAT_FIFO_STAT_DBG_ZCP_EOP_ERR 0x00000000000000f0ULL
1574#define RX_CTL_DAT_FIFO_STAT_DBG_IPP_EOP_ERR 0x000000000000000fULL
1575
1576#define RDC_TBL(TBL,SLOT) (FZC_ZCP + 0x10000UL + \
1577 (TBL) * (8UL * 16UL) + \
1578 (SLOT) * 8UL)
1579#define RDC_TBL_RDC 0x000000000000000fULL
1580
1581#define RX_LOG_PAGE_VLD(IDX) (FZC_DMC + 0x20000UL + (IDX) * 0x40UL)
1582#define RX_LOG_PAGE_VLD_FUNC 0x000000000000000cULL
1583#define RX_LOG_PAGE_VLD_FUNC_SHIFT 2
1584#define RX_LOG_PAGE_VLD_PAGE1 0x0000000000000002ULL
1585#define RX_LOG_PAGE_VLD_PAGE0 0x0000000000000001ULL
1586
1587#define RX_LOG_MASK1(IDX) (FZC_DMC + 0x20008UL + (IDX) * 0x40UL)
1588#define RX_LOG_MASK1_MASK 0x00000000ffffffffULL
1589
1590#define RX_LOG_VAL1(IDX) (FZC_DMC + 0x20010UL + (IDX) * 0x40UL)
1591#define RX_LOG_VAL1_VALUE 0x00000000ffffffffULL
1592
1593#define RX_LOG_MASK2(IDX) (FZC_DMC + 0x20018UL + (IDX) * 0x40UL)
1594#define RX_LOG_MASK2_MASK 0x00000000ffffffffULL
1595
1596#define RX_LOG_VAL2(IDX) (FZC_DMC + 0x20020UL + (IDX) * 0x40UL)
1597#define RX_LOG_VAL2_VALUE 0x00000000ffffffffULL
1598
1599#define RX_LOG_PAGE_RELO1(IDX) (FZC_DMC + 0x20028UL + (IDX) * 0x40UL)
1600#define RX_LOG_PAGE_RELO1_RELO 0x00000000ffffffffULL
1601
1602#define RX_LOG_PAGE_RELO2(IDX) (FZC_DMC + 0x20030UL + (IDX) * 0x40UL)
1603#define RX_LOG_PAGE_RELO2_RELO 0x00000000ffffffffULL
1604
1605#define RX_LOG_PAGE_HDL(IDX) (FZC_DMC + 0x20038UL + (IDX) * 0x40UL)
1606#define RX_LOG_PAGE_HDL_HANDLE 0x00000000000fffffULL
1607
1608#define TX_LOG_PAGE_VLD(IDX) (FZC_DMC + 0x40000UL + (IDX) * 0x200UL)
1609#define TX_LOG_PAGE_VLD_FUNC 0x000000000000000cULL
1610#define TX_LOG_PAGE_VLD_FUNC_SHIFT 2
1611#define TX_LOG_PAGE_VLD_PAGE1 0x0000000000000002ULL
1612#define TX_LOG_PAGE_VLD_PAGE0 0x0000000000000001ULL
1613
1614#define TX_LOG_MASK1(IDX) (FZC_DMC + 0x40008UL + (IDX) * 0x200UL)
1615#define TX_LOG_MASK1_MASK 0x00000000ffffffffULL
1616
1617#define TX_LOG_VAL1(IDX) (FZC_DMC + 0x40010UL + (IDX) * 0x200UL)
1618#define TX_LOG_VAL1_VALUE 0x00000000ffffffffULL
1619
1620#define TX_LOG_MASK2(IDX) (FZC_DMC + 0x40018UL + (IDX) * 0x200UL)
1621#define TX_LOG_MASK2_MASK 0x00000000ffffffffULL
1622
1623#define TX_LOG_VAL2(IDX) (FZC_DMC + 0x40020UL + (IDX) * 0x200UL)
1624#define TX_LOG_VAL2_VALUE 0x00000000ffffffffULL
1625
1626#define TX_LOG_PAGE_RELO1(IDX) (FZC_DMC + 0x40028UL + (IDX) * 0x200UL)
1627#define TX_LOG_PAGE_RELO1_RELO 0x00000000ffffffffULL
1628
1629#define TX_LOG_PAGE_RELO2(IDX) (FZC_DMC + 0x40030UL + (IDX) * 0x200UL)
1630#define TX_LOG_PAGE_RELO2_RELO 0x00000000ffffffffULL
1631
1632#define TX_LOG_PAGE_HDL(IDX) (FZC_DMC + 0x40038UL + (IDX) * 0x200UL)
1633#define TX_LOG_PAGE_HDL_HANDLE 0x00000000000fffffULL
1634
1635#define TX_ADDR_MD (FZC_DMC + 0x45000UL)
1636#define TX_ADDR_MD_MODE32 0x0000000000000001ULL
1637
1638#define RDC_RED_PARA(IDX) (FZC_DMC + 0x30000UL + (IDX) * 0x40UL)
1639#define RDC_RED_PARA_THRE_SYN 0x00000000fff00000ULL
1640#define RDC_RED_PARA_THRE_SYN_SHIFT 20
1641#define RDC_RED_PARA_WIN_SYN 0x00000000000f0000ULL
1642#define RDC_RED_PARA_WIN_SYN_SHIFT 16
1643#define RDC_RED_PARA_THRE 0x000000000000fff0ULL
1644#define RDC_RED_PARA_THRE_SHIFT 4
1645#define RDC_RED_PARA_WIN 0x000000000000000fULL
1646#define RDC_RED_PARA_WIN_SHIFT 0
1647
1648#define RED_DIS_CNT(IDX) (FZC_DMC + 0x30008UL + (IDX) * 0x40UL)
1649#define RED_DIS_CNT_OFLOW 0x0000000000010000ULL
1650#define RED_DIS_CNT_COUNT 0x000000000000ffffULL
1651
1652#define IPP_CFIG (FZC_IPP + 0x00000UL)
1653#define IPP_CFIG_SOFT_RST 0x0000000080000000ULL
1654#define IPP_CFIG_IP_MAX_PKT 0x0000000001ffff00ULL
1655#define IPP_CFIG_IP_MAX_PKT_SHIFT 8
1656#define IPP_CFIG_FFLP_CS_PIO_W 0x0000000000000080ULL
1657#define IPP_CFIG_PFIFO_PIO_W 0x0000000000000040ULL
1658#define IPP_CFIG_DFIFO_PIO_W 0x0000000000000020ULL
1659#define IPP_CFIG_CKSUM_EN 0x0000000000000010ULL
1660#define IPP_CFIG_DROP_BAD_CRC 0x0000000000000008ULL
1661#define IPP_CFIG_DFIFO_ECC_EN 0x0000000000000004ULL
1662#define IPP_CFIG_DEBUG_BUS_OUT_EN 0x0000000000000002ULL
1663#define IPP_CFIG_IPP_ENABLE 0x0000000000000001ULL
1664
1665#define IPP_PKT_DIS (FZC_IPP + 0x00020UL)
1666#define IPP_PKT_DIS_COUNT 0x0000000000003fffULL
1667
1668#define IPP_BAD_CS_CNT (FZC_IPP + 0x00028UL)
1669#define IPP_BAD_CS_CNT_COUNT 0x0000000000003fffULL
1670
1671#define IPP_ECC (FZC_IPP + 0x00030UL)
1672#define IPP_ECC_COUNT 0x00000000000000ffULL
1673
1674#define IPP_INT_STAT (FZC_IPP + 0x00040UL)
1675#define IPP_INT_STAT_SOP_MISS 0x0000000080000000ULL
1676#define IPP_INT_STAT_EOP_MISS 0x0000000040000000ULL
1677#define IPP_INT_STAT_DFIFO_UE 0x0000000030000000ULL
1678#define IPP_INT_STAT_DFIFO_CE 0x000000000c000000ULL
1679#define IPP_INT_STAT_DFIFO_ECC 0x0000000003000000ULL
1680#define IPP_INT_STAT_DFIFO_ECC_IDX 0x00000000007ff000ULL
1681#define IPP_INT_STAT_PFIFO_PERR 0x0000000000000800ULL
1682#define IPP_INT_STAT_ECC_ERR_MAX 0x0000000000000400ULL
1683#define IPP_INT_STAT_PFIFO_ERR_IDX 0x00000000000003f0ULL
1684#define IPP_INT_STAT_PFIFO_OVER 0x0000000000000008ULL
1685#define IPP_INT_STAT_PFIFO_UND 0x0000000000000004ULL
1686#define IPP_INT_STAT_BAD_CS_MX 0x0000000000000002ULL
1687#define IPP_INT_STAT_PKT_DIS_MX 0x0000000000000001ULL
1688#define IPP_INT_STAT_ALL 0x00000000ff7fffffULL
1689
1690#define IPP_MSK (FZC_IPP + 0x00048UL)
1691#define IPP_MSK_ECC_ERR_MX 0x0000000000000080ULL
1692#define IPP_MSK_DFIFO_EOP_SOP 0x0000000000000040ULL
1693#define IPP_MSK_DFIFO_UC 0x0000000000000020ULL
1694#define IPP_MSK_PFIFO_PAR 0x0000000000000010ULL
1695#define IPP_MSK_PFIFO_OVER 0x0000000000000008ULL
1696#define IPP_MSK_PFIFO_UND 0x0000000000000004ULL
1697#define IPP_MSK_BAD_CS 0x0000000000000002ULL
1698#define IPP_MSK_PKT_DIS_CNT 0x0000000000000001ULL
1699#define IPP_MSK_ALL 0x00000000000000ffULL
1700
1701#define IPP_PFIFO_RD0 (FZC_IPP + 0x00060UL)
1702#define IPP_PFIFO_RD0_DATA 0x00000000ffffffffULL /* bits 31:0 */
1703
1704#define IPP_PFIFO_RD1 (FZC_IPP + 0x00068UL)
1705#define IPP_PFIFO_RD1_DATA 0x00000000ffffffffULL /* bits 63:32 */
1706
1707#define IPP_PFIFO_RD2 (FZC_IPP + 0x00070UL)
1708#define IPP_PFIFO_RD2_DATA 0x00000000ffffffffULL /* bits 95:64 */
1709
1710#define IPP_PFIFO_RD3 (FZC_IPP + 0x00078UL)
1711#define IPP_PFIFO_RD3_DATA 0x00000000ffffffffULL /* bits 127:96 */
1712
1713#define IPP_PFIFO_RD4 (FZC_IPP + 0x00080UL)
1714#define IPP_PFIFO_RD4_DATA 0x00000000ffffffffULL /* bits 145:128 */
1715
1716#define IPP_PFIFO_WR0 (FZC_IPP + 0x00088UL)
1717#define IPP_PFIFO_WR0_DATA 0x00000000ffffffffULL /* bits 31:0 */
1718
1719#define IPP_PFIFO_WR1 (FZC_IPP + 0x00090UL)
1720#define IPP_PFIFO_WR1_DATA 0x00000000ffffffffULL /* bits 63:32 */
1721
1722#define IPP_PFIFO_WR2 (FZC_IPP + 0x00098UL)
1723#define IPP_PFIFO_WR2_DATA 0x00000000ffffffffULL /* bits 95:64 */
1724
1725#define IPP_PFIFO_WR3 (FZC_IPP + 0x000a0UL)
1726#define IPP_PFIFO_WR3_DATA 0x00000000ffffffffULL /* bits 127:96 */
1727
1728#define IPP_PFIFO_WR4 (FZC_IPP + 0x000a8UL)
1729#define IPP_PFIFO_WR4_DATA 0x00000000ffffffffULL /* bits 145:128 */
1730
1731#define IPP_PFIFO_RD_PTR (FZC_IPP + 0x000b0UL)
1732#define IPP_PFIFO_RD_PTR_PTR 0x000000000000003fULL
1733
1734#define IPP_PFIFO_WR_PTR (FZC_IPP + 0x000b8UL)
1735#define IPP_PFIFO_WR_PTR_PTR 0x000000000000007fULL
1736
1737#define IPP_DFIFO_RD0 (FZC_IPP + 0x000c0UL)
1738#define IPP_DFIFO_RD0_DATA 0x00000000ffffffffULL /* bits 31:0 */
1739
1740#define IPP_DFIFO_RD1 (FZC_IPP + 0x000c8UL)
1741#define IPP_DFIFO_RD1_DATA 0x00000000ffffffffULL /* bits 63:32 */
1742
1743#define IPP_DFIFO_RD2 (FZC_IPP + 0x000d0UL)
1744#define IPP_DFIFO_RD2_DATA 0x00000000ffffffffULL /* bits 95:64 */
1745
1746#define IPP_DFIFO_RD3 (FZC_IPP + 0x000d8UL)
1747#define IPP_DFIFO_RD3_DATA 0x00000000ffffffffULL /* bits 127:96 */
1748
1749#define IPP_DFIFO_RD4 (FZC_IPP + 0x000e0UL)
1750#define IPP_DFIFO_RD4_DATA 0x00000000ffffffffULL /* bits 145:128 */
1751
1752#define IPP_DFIFO_WR0 (FZC_IPP + 0x000e8UL)
1753#define IPP_DFIFO_WR0_DATA 0x00000000ffffffffULL /* bits 31:0 */
1754
1755#define IPP_DFIFO_WR1 (FZC_IPP + 0x000f0UL)
1756#define IPP_DFIFO_WR1_DATA 0x00000000ffffffffULL /* bits 63:32 */
1757
1758#define IPP_DFIFO_WR2 (FZC_IPP + 0x000f8UL)
1759#define IPP_DFIFO_WR2_DATA 0x00000000ffffffffULL /* bits 95:64 */
1760
1761#define IPP_DFIFO_WR3 (FZC_IPP + 0x00100UL)
1762#define IPP_DFIFO_WR3_DATA 0x00000000ffffffffULL /* bits 127:96 */
1763
1764#define IPP_DFIFO_WR4 (FZC_IPP + 0x00108UL)
1765#define IPP_DFIFO_WR4_DATA 0x00000000ffffffffULL /* bits 145:128 */
1766
1767#define IPP_DFIFO_RD_PTR (FZC_IPP + 0x00110UL)
1768#define IPP_DFIFO_RD_PTR_PTR 0x0000000000000fffULL
1769
1770#define IPP_DFIFO_WR_PTR (FZC_IPP + 0x00118UL)
1771#define IPP_DFIFO_WR_PTR_PTR 0x0000000000000fffULL
1772
1773#define IPP_SM (FZC_IPP + 0x00120UL)
1774#define IPP_SM_SM 0x00000000ffffffffULL
1775
1776#define IPP_CS_STAT (FZC_IPP + 0x00128UL)
1777#define IPP_CS_STAT_BCYC_CNT 0x00000000ff000000ULL
1778#define IPP_CS_STAT_IP_LEN 0x0000000000fff000ULL
1779#define IPP_CS_STAT_CS_FAIL 0x0000000000000800ULL
1780#define IPP_CS_STAT_TERM 0x0000000000000400ULL
1781#define IPP_CS_STAT_BAD_NUM 0x0000000000000200ULL
1782#define IPP_CS_STAT_CS_STATE 0x00000000000001ffULL
1783
1784#define IPP_FFLP_CS_INFO (FZC_IPP + 0x00130UL)
1785#define IPP_FFLP_CS_INFO_PKT_ID 0x0000000000003c00ULL
1786#define IPP_FFLP_CS_INFO_L4_PROTO 0x0000000000000300ULL
1787#define IPP_FFLP_CS_INFO_V4_HD_LEN 0x00000000000000f0ULL
1788#define IPP_FFLP_CS_INFO_L3_VER 0x000000000000000cULL
1789#define IPP_FFLP_CS_INFO_L2_OP 0x0000000000000003ULL
1790
1791#define IPP_DBG_SEL (FZC_IPP + 0x00138UL)
1792#define IPP_DBG_SEL_SEL 0x000000000000000fULL
1793
1794#define IPP_DFIFO_ECC_SYND (FZC_IPP + 0x00140UL)
1795#define IPP_DFIFO_ECC_SYND_SYND 0x000000000000ffffULL
1796
1797#define IPP_DFIFO_EOP_RD_PTR (FZC_IPP + 0x00148UL)
1798#define IPP_DFIFO_EOP_RD_PTR_PTR 0x0000000000000fffULL
1799
1800#define IPP_ECC_CTL (FZC_IPP + 0x00150UL)
1801#define IPP_ECC_CTL_DIS_DBL 0x0000000080000000ULL
1802#define IPP_ECC_CTL_COR_DBL 0x0000000000020000ULL
1803#define IPP_ECC_CTL_COR_SNG 0x0000000000010000ULL
1804#define IPP_ECC_CTL_COR_ALL 0x0000000000000400ULL
1805#define IPP_ECC_CTL_COR_1 0x0000000000000100ULL
1806#define IPP_ECC_CTL_COR_LST 0x0000000000000004ULL
1807#define IPP_ECC_CTL_COR_SND 0x0000000000000002ULL
1808#define IPP_ECC_CTL_COR_FSR 0x0000000000000001ULL
1809
1810#define NIU_DFIFO_ENTRIES 1024
1811#define ATLAS_P0_P1_DFIFO_ENTRIES 2048
1812#define ATLAS_P2_P3_DFIFO_ENTRIES 1024
1813
1814#define ZCP_CFIG (FZC_ZCP + 0x00000UL)
1815#define ZCP_CFIG_ZCP_32BIT_MODE 0x0000000001000000ULL
1816#define ZCP_CFIG_ZCP_DEBUG_SEL 0x0000000000ff0000ULL
1817#define ZCP_CFIG_DMA_TH 0x000000000000ffe0ULL
1818#define ZCP_CFIG_ECC_CHK_DIS 0x0000000000000010ULL
1819#define ZCP_CFIG_PAR_CHK_DIS 0x0000000000000008ULL
1820#define ZCP_CFIG_DIS_BUFF_RSP_IF 0x0000000000000004ULL
1821#define ZCP_CFIG_DIS_BUFF_REQ_IF 0x0000000000000002ULL
1822#define ZCP_CFIG_ZC_ENABLE 0x0000000000000001ULL
1823
1824#define ZCP_INT_STAT (FZC_ZCP + 0x00008UL)
1825#define ZCP_INT_STAT_RRFIFO_UNDERRUN 0x0000000000008000ULL
1826#define ZCP_INT_STAT_RRFIFO_OVERRUN 0x0000000000004000ULL
1827#define ZCP_INT_STAT_RSPFIFO_UNCOR_ERR 0x0000000000001000ULL
1828#define ZCP_INT_STAT_BUFFER_OVERFLOW 0x0000000000000800ULL
1829#define ZCP_INT_STAT_STAT_TBL_PERR 0x0000000000000400ULL
1830#define ZCP_INT_STAT_DYN_TBL_PERR 0x0000000000000200ULL
1831#define ZCP_INT_STAT_BUF_TBL_PERR 0x0000000000000100ULL
1832#define ZCP_INT_STAT_TT_PROGRAM_ERR 0x0000000000000080ULL
1833#define ZCP_INT_STAT_RSP_TT_INDEX_ERR 0x0000000000000040ULL
1834#define ZCP_INT_STAT_SLV_TT_INDEX_ERR 0x0000000000000020ULL
1835#define ZCP_INT_STAT_ZCP_TT_INDEX_ERR 0x0000000000000010ULL
1836#define ZCP_INT_STAT_CFIFO_ECC3 0x0000000000000008ULL
1837#define ZCP_INT_STAT_CFIFO_ECC2 0x0000000000000004ULL
1838#define ZCP_INT_STAT_CFIFO_ECC1 0x0000000000000002ULL
1839#define ZCP_INT_STAT_CFIFO_ECC0 0x0000000000000001ULL
1840#define ZCP_INT_STAT_ALL 0x000000000000ffffULL
1841
1842#define ZCP_INT_MASK (FZC_ZCP + 0x00010UL)
1843#define ZCP_INT_MASK_RRFIFO_UNDERRUN 0x0000000000008000ULL
1844#define ZCP_INT_MASK_RRFIFO_OVERRUN 0x0000000000004000ULL
1845#define ZCP_INT_MASK_LOJ 0x0000000000002000ULL
1846#define ZCP_INT_MASK_RSPFIFO_UNCOR_ERR 0x0000000000001000ULL
1847#define ZCP_INT_MASK_BUFFER_OVERFLOW 0x0000000000000800ULL
1848#define ZCP_INT_MASK_STAT_TBL_PERR 0x0000000000000400ULL
1849#define ZCP_INT_MASK_DYN_TBL_PERR 0x0000000000000200ULL
1850#define ZCP_INT_MASK_BUF_TBL_PERR 0x0000000000000100ULL
1851#define ZCP_INT_MASK_TT_PROGRAM_ERR 0x0000000000000080ULL
1852#define ZCP_INT_MASK_RSP_TT_INDEX_ERR 0x0000000000000040ULL
1853#define ZCP_INT_MASK_SLV_TT_INDEX_ERR 0x0000000000000020ULL
1854#define ZCP_INT_MASK_ZCP_TT_INDEX_ERR 0x0000000000000010ULL
1855#define ZCP_INT_MASK_CFIFO_ECC3 0x0000000000000008ULL
1856#define ZCP_INT_MASK_CFIFO_ECC2 0x0000000000000004ULL
1857#define ZCP_INT_MASK_CFIFO_ECC1 0x0000000000000002ULL
1858#define ZCP_INT_MASK_CFIFO_ECC0 0x0000000000000001ULL
1859#define ZCP_INT_MASK_ALL 0x000000000000ffffULL
1860
1861#define BAM4BUF (FZC_ZCP + 0x00018UL)
1862#define BAM4BUF_LOJ 0x0000000080000000ULL
1863#define BAM4BUF_EN_CK 0x0000000040000000ULL
1864#define BAM4BUF_IDX_END0 0x000000003ff00000ULL
1865#define BAM4BUF_IDX_ST0 0x00000000000ffc00ULL
1866#define BAM4BUF_OFFSET0 0x00000000000003ffULL
1867
1868#define BAM8BUF (FZC_ZCP + 0x00020UL)
1869#define BAM8BUF_LOJ 0x0000000080000000ULL
1870#define BAM8BUF_EN_CK 0x0000000040000000ULL
1871#define BAM8BUF_IDX_END1 0x000000003ff00000ULL
1872#define BAM8BUF_IDX_ST1 0x00000000000ffc00ULL
1873#define BAM8BUF_OFFSET1 0x00000000000003ffULL
1874
1875#define BAM16BUF (FZC_ZCP + 0x00028UL)
1876#define BAM16BUF_LOJ 0x0000000080000000ULL
1877#define BAM16BUF_EN_CK 0x0000000040000000ULL
1878#define BAM16BUF_IDX_END2 0x000000003ff00000ULL
1879#define BAM16BUF_IDX_ST2 0x00000000000ffc00ULL
1880#define BAM16BUF_OFFSET2 0x00000000000003ffULL
1881
1882#define BAM32BUF (FZC_ZCP + 0x00030UL)
1883#define BAM32BUF_LOJ 0x0000000080000000ULL
1884#define BAM32BUF_EN_CK 0x0000000040000000ULL
1885#define BAM32BUF_IDX_END3 0x000000003ff00000ULL
1886#define BAM32BUF_IDX_ST3 0x00000000000ffc00ULL
1887#define BAM32BUF_OFFSET3 0x00000000000003ffULL
1888
1889#define DST4BUF (FZC_ZCP + 0x00038UL)
1890#define DST4BUF_DS_OFFSET0 0x00000000000003ffULL
1891
1892#define DST8BUF (FZC_ZCP + 0x00040UL)
1893#define DST8BUF_DS_OFFSET1 0x00000000000003ffULL
1894
1895#define DST16BUF (FZC_ZCP + 0x00048UL)
1896#define DST16BUF_DS_OFFSET2 0x00000000000003ffULL
1897
1898#define DST32BUF (FZC_ZCP + 0x00050UL)
1899#define DST32BUF_DS_OFFSET3 0x00000000000003ffULL
1900
1901#define ZCP_RAM_DATA0 (FZC_ZCP + 0x00058UL)
1902#define ZCP_RAM_DATA0_DAT0 0x00000000ffffffffULL
1903
1904#define ZCP_RAM_DATA1 (FZC_ZCP + 0x00060UL)
1905#define ZCP_RAM_DAT10_DAT1 0x00000000ffffffffULL
1906
1907#define ZCP_RAM_DATA2 (FZC_ZCP + 0x00068UL)
1908#define ZCP_RAM_DATA2_DAT2 0x00000000ffffffffULL
1909
1910#define ZCP_RAM_DATA3 (FZC_ZCP + 0x00070UL)
1911#define ZCP_RAM_DATA3_DAT3 0x00000000ffffffffULL
1912
1913#define ZCP_RAM_DATA4 (FZC_ZCP + 0x00078UL)
1914#define ZCP_RAM_DATA4_DAT4 0x00000000000000ffULL
1915
1916#define ZCP_RAM_BE (FZC_ZCP + 0x00080UL)
1917#define ZCP_RAM_BE_VAL 0x000000000001ffffULL
1918
1919#define ZCP_RAM_ACC (FZC_ZCP + 0x00088UL)
1920#define ZCP_RAM_ACC_BUSY 0x0000000080000000ULL
1921#define ZCP_RAM_ACC_READ 0x0000000040000000ULL
1922#define ZCP_RAM_ACC_WRITE 0x0000000000000000ULL
1923#define ZCP_RAM_ACC_LOJ 0x0000000020000000ULL
1924#define ZCP_RAM_ACC_ZFCID 0x000000001ffe0000ULL
1925#define ZCP_RAM_ACC_ZFCID_SHIFT 17
1926#define ZCP_RAM_ACC_RAM_SEL 0x000000000001f000ULL
1927#define ZCP_RAM_ACC_RAM_SEL_SHIFT 12
1928#define ZCP_RAM_ACC_CFIFOADDR 0x0000000000000fffULL
1929#define ZCP_RAM_ACC_CFIFOADDR_SHIFT 0
1930
1931#define ZCP_RAM_SEL_BAM(INDEX) (0x00 + (INDEX))
1932#define ZCP_RAM_SEL_TT_STATIC 0x08
1933#define ZCP_RAM_SEL_TT_DYNAMIC 0x09
1934#define ZCP_RAM_SEL_CFIFO(PORT) (0x10 + (PORT))
1935
1936#define NIU_CFIFO_ENTRIES 1024
1937#define ATLAS_P0_P1_CFIFO_ENTRIES 2048
1938#define ATLAS_P2_P3_CFIFO_ENTRIES 1024
1939
1940#define CHK_BIT_DATA (FZC_ZCP + 0x00090UL)
1941#define CHK_BIT_DATA_DATA 0x000000000000ffffULL
1942
1943#define RESET_CFIFO (FZC_ZCP + 0x00098UL)
1944#define RESET_CFIFO_RST(PORT) (0x1 << (PORT))
1945
1946#define CFIFO_ECC(PORT) (FZC_ZCP + 0x000a0UL + (PORT) * 8UL)
1947#define CFIFO_ECC_DIS_DBLBIT_ERR 0x0000000080000000ULL
1948#define CFIFO_ECC_DBLBIT_ERR 0x0000000000020000ULL
1949#define CFIFO_ECC_SINGLEBIT_ERR 0x0000000000010000ULL
1950#define CFIFO_ECC_ALL_PKT 0x0000000000000400ULL
1951#define CFIFO_ECC_LAST_LINE 0x0000000000000004ULL
1952#define CFIFO_ECC_2ND_LINE 0x0000000000000002ULL
1953#define CFIFO_ECC_1ST_LINE 0x0000000000000001ULL
1954
1955#define ZCP_TRAINING_VECTOR (FZC_ZCP + 0x000c0UL)
1956#define ZCP_TRAINING_VECTOR_VECTOR 0x00000000ffffffffULL
1957
1958#define ZCP_STATE_MACHINE (FZC_ZCP + 0x000c8UL)
1959#define ZCP_STATE_MACHINE_SM 0x00000000ffffffffULL
1960
1961/* Same bits as ZCP_INT_STAT */
1962#define ZCP_INT_STAT_TEST (FZC_ZCP + 0x00108UL)
1963
1964#define RXDMA_CFIG1(IDX) (DMC + 0x00000UL + (IDX) * 0x200UL)
1965#define RXDMA_CFIG1_EN 0x0000000080000000ULL
1966#define RXDMA_CFIG1_RST 0x0000000040000000ULL
1967#define RXDMA_CFIG1_QST 0x0000000020000000ULL
1968#define RXDMA_CFIG1_MBADDR_H 0x0000000000000fffULL /* mboxaddr 43:32 */
1969
1970#define RXDMA_CFIG2(IDX) (DMC + 0x00008UL + (IDX) * 0x200UL)
1971#define RXDMA_CFIG2_MBADDR_L 0x00000000ffffffc0ULL /* mboxaddr 31:6 */
1972#define RXDMA_CFIG2_OFFSET 0x0000000000000006ULL
1973#define RXDMA_CFIG2_OFFSET_SHIFT 1
1974#define RXDMA_CFIG2_FULL_HDR 0x0000000000000001ULL
1975
1976#define RBR_CFIG_A(IDX) (DMC + 0x00010UL + (IDX) * 0x200UL)
1977#define RBR_CFIG_A_LEN 0xffff000000000000ULL
1978#define RBR_CFIG_A_LEN_SHIFT 48
1979#define RBR_CFIG_A_STADDR_BASE 0x00000ffffffc0000ULL
1980#define RBR_CFIG_A_STADDR 0x000000000003ffc0ULL
1981
1982#define RBR_CFIG_B(IDX) (DMC + 0x00018UL + (IDX) * 0x200UL)
1983#define RBR_CFIG_B_BLKSIZE 0x0000000003000000ULL
1984#define RBR_CFIG_B_BLKSIZE_SHIFT 24
1985#define RBR_CFIG_B_VLD2 0x0000000000800000ULL
1986#define RBR_CFIG_B_BUFSZ2 0x0000000000030000ULL
1987#define RBR_CFIG_B_BUFSZ2_SHIFT 16
1988#define RBR_CFIG_B_VLD1 0x0000000000008000ULL
1989#define RBR_CFIG_B_BUFSZ1 0x0000000000000300ULL
1990#define RBR_CFIG_B_BUFSZ1_SHIFT 8
1991#define RBR_CFIG_B_VLD0 0x0000000000000080ULL
1992#define RBR_CFIG_B_BUFSZ0 0x0000000000000003ULL
1993#define RBR_CFIG_B_BUFSZ0_SHIFT 0
1994
1995#define RBR_BLKSIZE_4K 0x0
1996#define RBR_BLKSIZE_8K 0x1
1997#define RBR_BLKSIZE_16K 0x2
1998#define RBR_BLKSIZE_32K 0x3
1999#define RBR_BUFSZ2_2K 0x0
2000#define RBR_BUFSZ2_4K 0x1
2001#define RBR_BUFSZ2_8K 0x2
2002#define RBR_BUFSZ2_16K 0x3
2003#define RBR_BUFSZ1_1K 0x0
2004#define RBR_BUFSZ1_2K 0x1
2005#define RBR_BUFSZ1_4K 0x2
2006#define RBR_BUFSZ1_8K 0x3
2007#define RBR_BUFSZ0_256 0x0
2008#define RBR_BUFSZ0_512 0x1
2009#define RBR_BUFSZ0_1K 0x2
2010#define RBR_BUFSZ0_2K 0x3
2011
2012#define RBR_KICK(IDX) (DMC + 0x00020UL + (IDX) * 0x200UL)
2013#define RBR_KICK_BKADD 0x000000000000ffffULL
2014
2015#define RBR_STAT(IDX) (DMC + 0x00028UL + (IDX) * 0x200UL)
2016#define RBR_STAT_QLEN 0x000000000000ffffULL
2017
2018#define RBR_HDH(IDX) (DMC + 0x00030UL + (IDX) * 0x200UL)
2019#define RBR_HDH_HEAD_H 0x0000000000000fffULL
2020
2021#define RBR_HDL(IDX) (DMC + 0x00038UL + (IDX) * 0x200UL)
2022#define RBR_HDL_HEAD_L 0x00000000fffffffcULL
2023
2024#define RCRCFIG_A(IDX) (DMC + 0x00040UL + (IDX) * 0x200UL)
2025#define RCRCFIG_A_LEN 0xffff000000000000ULL
2026#define RCRCFIG_A_LEN_SHIFT 48
2027#define RCRCFIG_A_STADDR_BASE 0x00000ffffff80000ULL
2028#define RCRCFIG_A_STADDR 0x000000000007ffc0ULL
2029
2030#define RCRCFIG_B(IDX) (DMC + 0x00048UL + (IDX) * 0x200UL)
2031#define RCRCFIG_B_PTHRES 0x00000000ffff0000ULL
2032#define RCRCFIG_B_PTHRES_SHIFT 16
2033#define RCRCFIG_B_ENTOUT 0x0000000000008000ULL
2034#define RCRCFIG_B_TIMEOUT 0x000000000000003fULL
2035#define RCRCFIG_B_TIMEOUT_SHIFT 0
2036
2037#define RCRSTAT_A(IDX) (DMC + 0x00050UL + (IDX) * 0x200UL)
2038#define RCRSTAT_A_QLEN 0x000000000000ffffULL
2039
2040#define RCRSTAT_B(IDX) (DMC + 0x00058UL + (IDX) * 0x200UL)
2041#define RCRSTAT_B_TIPTR_H 0x0000000000000fffULL
2042
2043#define RCRSTAT_C(IDX) (DMC + 0x00060UL + (IDX) * 0x200UL)
2044#define RCRSTAT_C_TIPTR_L 0x00000000fffffff8ULL
2045
2046#define RX_DMA_CTL_STAT(IDX) (DMC + 0x00070UL + (IDX) * 0x200UL)
2047#define RX_DMA_CTL_STAT_RBR_TMOUT 0x0020000000000000ULL
2048#define RX_DMA_CTL_STAT_RSP_CNT_ERR 0x0010000000000000ULL
2049#define RX_DMA_CTL_STAT_BYTE_EN_BUS 0x0008000000000000ULL
2050#define RX_DMA_CTL_STAT_RSP_DAT_ERR 0x0004000000000000ULL
2051#define RX_DMA_CTL_STAT_RCR_ACK_ERR 0x0002000000000000ULL
2052#define RX_DMA_CTL_STAT_DC_FIFO_ERR 0x0001000000000000ULL
2053#define RX_DMA_CTL_STAT_MEX 0x0000800000000000ULL
2054#define RX_DMA_CTL_STAT_RCRTHRES 0x0000400000000000ULL
2055#define RX_DMA_CTL_STAT_RCRTO 0x0000200000000000ULL
2056#define RX_DMA_CTL_STAT_RCR_SHA_PAR 0x0000100000000000ULL
2057#define RX_DMA_CTL_STAT_RBR_PRE_PAR 0x0000080000000000ULL
2058#define RX_DMA_CTL_STAT_PORT_DROP_PKT 0x0000040000000000ULL
2059#define RX_DMA_CTL_STAT_WRED_DROP 0x0000020000000000ULL
2060#define RX_DMA_CTL_STAT_RBR_PRE_EMTY 0x0000010000000000ULL
2061#define RX_DMA_CTL_STAT_RCRSHADOW_FULL 0x0000008000000000ULL
2062#define RX_DMA_CTL_STAT_CONFIG_ERR 0x0000004000000000ULL
2063#define RX_DMA_CTL_STAT_RCRINCON 0x0000002000000000ULL
2064#define RX_DMA_CTL_STAT_RCRFULL 0x0000001000000000ULL
2065#define RX_DMA_CTL_STAT_RBR_EMPTY 0x0000000800000000ULL
2066#define RX_DMA_CTL_STAT_RBRFULL 0x0000000400000000ULL
2067#define RX_DMA_CTL_STAT_RBRLOGPAGE 0x0000000200000000ULL
2068#define RX_DMA_CTL_STAT_CFIGLOGPAGE 0x0000000100000000ULL
2069#define RX_DMA_CTL_STAT_PTRREAD 0x00000000ffff0000ULL
2070#define RX_DMA_CTL_STAT_PTRREAD_SHIFT 16
2071#define RX_DMA_CTL_STAT_PKTREAD 0x000000000000ffffULL
2072#define RX_DMA_CTL_STAT_PKTREAD_SHIFT 0
2073
2074#define RX_DMA_CTL_STAT_CHAN_FATAL (RX_DMA_CTL_STAT_RBR_TMOUT | \
2075 RX_DMA_CTL_STAT_RSP_CNT_ERR | \
2076 RX_DMA_CTL_STAT_BYTE_EN_BUS | \
2077 RX_DMA_CTL_STAT_RSP_DAT_ERR | \
2078 RX_DMA_CTL_STAT_RCR_ACK_ERR | \
2079 RX_DMA_CTL_STAT_RCR_SHA_PAR | \
2080 RX_DMA_CTL_STAT_RBR_PRE_PAR | \
2081 RX_DMA_CTL_STAT_CONFIG_ERR | \
2082 RX_DMA_CTL_STAT_RCRINCON | \
2083 RX_DMA_CTL_STAT_RCRFULL | \
2084 RX_DMA_CTL_STAT_RBRFULL | \
2085 RX_DMA_CTL_STAT_RBRLOGPAGE | \
2086 RX_DMA_CTL_STAT_CFIGLOGPAGE)
2087
2088#define RX_DMA_CTL_STAT_PORT_FATAL (RX_DMA_CTL_STAT_DC_FIFO_ERR)
2089
2090#define RX_DMA_CTL_WRITE_CLEAR_ERRS (RX_DMA_CTL_STAT_RBR_EMPTY | \
2091 RX_DMA_CTL_STAT_RCRSHADOW_FULL | \
2092 RX_DMA_CTL_STAT_RBR_PRE_EMTY | \
2093 RX_DMA_CTL_STAT_WRED_DROP | \
2094 RX_DMA_CTL_STAT_PORT_DROP_PKT | \
2095 RX_DMA_CTL_STAT_RCRTO | \
2096 RX_DMA_CTL_STAT_RCRTHRES | \
2097 RX_DMA_CTL_STAT_DC_FIFO_ERR)
2098
2099#define RCR_FLSH(IDX) (DMC + 0x00078UL + (IDX) * 0x200UL)
2100#define RCR_FLSH_FLSH 0x0000000000000001ULL
2101
2102#define RXMISC(IDX) (DMC + 0x00090UL + (IDX) * 0x200UL)
2103#define RXMISC_OFLOW 0x0000000000010000ULL
2104#define RXMISC_COUNT 0x000000000000ffffULL
2105
2106#define RX_DMA_CTL_STAT_DBG(IDX) (DMC + 0x00098UL + (IDX) * 0x200UL)
2107#define RX_DMA_CTL_STAT_DBG_RBR_TMOUT 0x0020000000000000ULL
2108#define RX_DMA_CTL_STAT_DBG_RSP_CNT_ERR 0x0010000000000000ULL
2109#define RX_DMA_CTL_STAT_DBG_BYTE_EN_BUS 0x0008000000000000ULL
2110#define RX_DMA_CTL_STAT_DBG_RSP_DAT_ERR 0x0004000000000000ULL
2111#define RX_DMA_CTL_STAT_DBG_RCR_ACK_ERR 0x0002000000000000ULL
2112#define RX_DMA_CTL_STAT_DBG_DC_FIFO_ERR 0x0001000000000000ULL
2113#define RX_DMA_CTL_STAT_DBG_MEX 0x0000800000000000ULL
2114#define RX_DMA_CTL_STAT_DBG_RCRTHRES 0x0000400000000000ULL
2115#define RX_DMA_CTL_STAT_DBG_RCRTO 0x0000200000000000ULL
2116#define RX_DMA_CTL_STAT_DBG_RCR_SHA_PAR 0x0000100000000000ULL
2117#define RX_DMA_CTL_STAT_DBG_RBR_PRE_PAR 0x0000080000000000ULL
2118#define RX_DMA_CTL_STAT_DBG_PORT_DROP_PKT 0x0000040000000000ULL
2119#define RX_DMA_CTL_STAT_DBG_WRED_DROP 0x0000020000000000ULL
2120#define RX_DMA_CTL_STAT_DBG_RBR_PRE_EMTY 0x0000010000000000ULL
2121#define RX_DMA_CTL_STAT_DBG_RCRSHADOW_FULL 0x0000008000000000ULL
2122#define RX_DMA_CTL_STAT_DBG_CONFIG_ERR 0x0000004000000000ULL
2123#define RX_DMA_CTL_STAT_DBG_RCRINCON 0x0000002000000000ULL
2124#define RX_DMA_CTL_STAT_DBG_RCRFULL 0x0000001000000000ULL
2125#define RX_DMA_CTL_STAT_DBG_RBR_EMPTY 0x0000000800000000ULL
2126#define RX_DMA_CTL_STAT_DBG_RBRFULL 0x0000000400000000ULL
2127#define RX_DMA_CTL_STAT_DBG_RBRLOGPAGE 0x0000000200000000ULL
2128#define RX_DMA_CTL_STAT_DBG_CFIGLOGPAGE 0x0000000100000000ULL
2129#define RX_DMA_CTL_STAT_DBG_PTRREAD 0x00000000ffff0000ULL
2130#define RX_DMA_CTL_STAT_DBG_PKTREAD 0x000000000000ffffULL
2131
2132#define RX_DMA_ENT_MSK(IDX) (DMC + 0x00068UL + (IDX) * 0x200UL)
2133#define RX_DMA_ENT_MSK_RBR_TMOUT 0x0000000000200000ULL
2134#define RX_DMA_ENT_MSK_RSP_CNT_ERR 0x0000000000100000ULL
2135#define RX_DMA_ENT_MSK_BYTE_EN_BUS 0x0000000000080000ULL
2136#define RX_DMA_ENT_MSK_RSP_DAT_ERR 0x0000000000040000ULL
2137#define RX_DMA_ENT_MSK_RCR_ACK_ERR 0x0000000000020000ULL
2138#define RX_DMA_ENT_MSK_DC_FIFO_ERR 0x0000000000010000ULL
2139#define RX_DMA_ENT_MSK_RCRTHRES 0x0000000000004000ULL
2140#define RX_DMA_ENT_MSK_RCRTO 0x0000000000002000ULL
2141#define RX_DMA_ENT_MSK_RCR_SHA_PAR 0x0000000000001000ULL
2142#define RX_DMA_ENT_MSK_RBR_PRE_PAR 0x0000000000000800ULL
2143#define RX_DMA_ENT_MSK_PORT_DROP_PKT 0x0000000000000400ULL
2144#define RX_DMA_ENT_MSK_WRED_DROP 0x0000000000000200ULL
2145#define RX_DMA_ENT_MSK_RBR_PRE_EMTY 0x0000000000000100ULL
2146#define RX_DMA_ENT_MSK_RCR_SHADOW_FULL 0x0000000000000080ULL
2147#define RX_DMA_ENT_MSK_CONFIG_ERR 0x0000000000000040ULL
2148#define RX_DMA_ENT_MSK_RCRINCON 0x0000000000000020ULL
2149#define RX_DMA_ENT_MSK_RCRFULL 0x0000000000000010ULL
2150#define RX_DMA_ENT_MSK_RBR_EMPTY 0x0000000000000008ULL
2151#define RX_DMA_ENT_MSK_RBRFULL 0x0000000000000004ULL
2152#define RX_DMA_ENT_MSK_RBRLOGPAGE 0x0000000000000002ULL
2153#define RX_DMA_ENT_MSK_CFIGLOGPAGE 0x0000000000000001ULL
2154#define RX_DMA_ENT_MSK_ALL 0x00000000003f7fffULL
2155
2156#define TX_RNG_CFIG(IDX) (DMC + 0x40000UL + (IDX) * 0x200UL)
2157#define TX_RNG_CFIG_LEN 0x1fff000000000000ULL
2158#define TX_RNG_CFIG_LEN_SHIFT 48
2159#define TX_RNG_CFIG_STADDR_BASE 0x00000ffffff80000ULL
2160#define TX_RNG_CFIG_STADDR 0x000000000007ffc0ULL
2161
2162#define TX_RING_HDL(IDX) (DMC + 0x40010UL + (IDX) * 0x200UL)
2163#define TX_RING_HDL_WRAP 0x0000000000080000ULL
2164#define TX_RING_HDL_HEAD 0x000000000007fff8ULL
2165#define TX_RING_HDL_HEAD_SHIFT 3
2166
2167#define TX_RING_KICK(IDX) (DMC + 0x40018UL + (IDX) * 0x200UL)
2168#define TX_RING_KICK_WRAP 0x0000000000080000ULL
2169#define TX_RING_KICK_TAIL 0x000000000007fff8ULL
2170
2171#define TX_ENT_MSK(IDX) (DMC + 0x40020UL + (IDX) * 0x200UL)
2172#define TX_ENT_MSK_MK 0x0000000000008000ULL
2173#define TX_ENT_MSK_MBOX_ERR 0x0000000000000080ULL
2174#define TX_ENT_MSK_PKT_SIZE_ERR 0x0000000000000040ULL
2175#define TX_ENT_MSK_TX_RING_OFLOW 0x0000000000000020ULL
2176#define TX_ENT_MSK_PREF_BUF_ECC_ERR 0x0000000000000010ULL
2177#define TX_ENT_MSK_NACK_PREF 0x0000000000000008ULL
2178#define TX_ENT_MSK_NACK_PKT_RD 0x0000000000000004ULL
2179#define TX_ENT_MSK_CONF_PART_ERR 0x0000000000000002ULL
2180#define TX_ENT_MSK_PKT_PRT_ERR 0x0000000000000001ULL
2181
2182#define TX_CS(IDX) (DMC + 0x40028UL + (IDX)*0x200UL)
2183#define TX_CS_PKT_CNT 0x0fff000000000000ULL
2184#define TX_CS_PKT_CNT_SHIFT 48
2185#define TX_CS_LASTMARK 0x00000fff00000000ULL
2186#define TX_CS_LASTMARK_SHIFT 32
2187#define TX_CS_RST 0x0000000080000000ULL
2188#define TX_CS_RST_STATE 0x0000000040000000ULL
2189#define TX_CS_MB 0x0000000020000000ULL
2190#define TX_CS_STOP_N_GO 0x0000000010000000ULL
2191#define TX_CS_SNG_STATE 0x0000000008000000ULL
2192#define TX_CS_MK 0x0000000000008000ULL
2193#define TX_CS_MMK 0x0000000000004000ULL
2194#define TX_CS_MBOX_ERR 0x0000000000000080ULL
2195#define TX_CS_PKT_SIZE_ERR 0x0000000000000040ULL
2196#define TX_CS_TX_RING_OFLOW 0x0000000000000020ULL
2197#define TX_CS_PREF_BUF_PAR_ERR 0x0000000000000010ULL
2198#define TX_CS_NACK_PREF 0x0000000000000008ULL
2199#define TX_CS_NACK_PKT_RD 0x0000000000000004ULL
2200#define TX_CS_CONF_PART_ERR 0x0000000000000002ULL
2201#define TX_CS_PKT_PRT_ERR 0x0000000000000001ULL
2202
2203#define TXDMA_MBH(IDX) (DMC + 0x40030UL + (IDX) * 0x200UL)
2204#define TXDMA_MBH_MBADDR 0x0000000000000fffULL
2205
2206#define TXDMA_MBL(IDX) (DMC + 0x40038UL + (IDX) * 0x200UL)
2207#define TXDMA_MBL_MBADDR 0x00000000ffffffc0ULL
2208
2209#define TX_DMA_PRE_ST(IDX) (DMC + 0x40040UL + (IDX) * 0x200UL)
2210#define TX_DMA_PRE_ST_SHADOW_HD 0x000000000007ffffULL
2211
2212#define TX_RNG_ERR_LOGH(IDX) (DMC + 0x40048UL + (IDX) * 0x200UL)
2213#define TX_RNG_ERR_LOGH_ERR 0x0000000080000000ULL
2214#define TX_RNG_ERR_LOGH_MERR 0x0000000040000000ULL
2215#define TX_RNG_ERR_LOGH_ERRCODE 0x0000000038000000ULL
2216#define TX_RNG_ERR_LOGH_ERRADDR 0x0000000000000fffULL
2217
2218#define TX_RNG_ERR_LOGL(IDX) (DMC + 0x40050UL + (IDX) * 0x200UL)
2219#define TX_RNG_ERR_LOGL_ERRADDR 0x00000000ffffffffULL
2220
2221#define TDMC_INTR_DBG(IDX) (DMC + 0x40060UL + (IDX) * 0x200UL)
2222#define TDMC_INTR_DBG_MK 0x0000000000008000ULL
2223#define TDMC_INTR_DBG_MBOX_ERR 0x0000000000000080ULL
2224#define TDMC_INTR_DBG_PKT_SIZE_ERR 0x0000000000000040ULL
2225#define TDMC_INTR_DBG_TX_RING_OFLOW 0x0000000000000020ULL
2226#define TDMC_INTR_DBG_PREF_BUF_PAR_ERR 0x0000000000000010ULL
2227#define TDMC_INTR_DBG_NACK_PREF 0x0000000000000008ULL
2228#define TDMC_INTR_DBG_NACK_PKT_RD 0x0000000000000004ULL
2229#define TDMC_INTR_DBG_CONF_PART_ERR 0x0000000000000002ULL
2230#define TDMC_INTR_DBG_PKT_PART_ERR 0x0000000000000001ULL
2231
2232#define TX_CS_DBG(IDX) (DMC + 0x40068UL + (IDX) * 0x200UL)
2233#define TX_CS_DBG_PKT_CNT 0x0fff000000000000ULL
2234
2235#define TDMC_INJ_PAR_ERR(IDX) (DMC + 0x45040UL + (IDX) * 0x200UL)
2236#define TDMC_INJ_PAR_ERR_VAL 0x000000000000ffffULL
2237
2238#define TDMC_DBG_SEL(IDX) (DMC + 0x45080UL + (IDX) * 0x200UL)
2239#define TDMC_DBG_SEL_DBG_SEL 0x000000000000003fULL
2240
2241#define TDMC_TRAINING_VECTOR(IDX) (DMC + 0x45088UL + (IDX) * 0x200UL)
2242#define TDMC_TRAINING_VECTOR_VEC 0x00000000ffffffffULL
2243
2244#define TXC_DMA_MAX(CHAN) (FZC_TXC + 0x00000UL + (CHAN)*0x1000UL)
2245#define TXC_DMA_MAX_LEN(CHAN) (FZC_TXC + 0x00008UL + (CHAN)*0x1000UL)
2246
2247#define TXC_CONTROL (FZC_TXC + 0x20000UL)
2248#define TXC_CONTROL_ENABLE 0x0000000000000010ULL
2249#define TXC_CONTROL_PORT_ENABLE(X) (1 << (X))
2250
2251#define TXC_TRAINING_VEC (FZC_TXC + 0x20008UL)
2252#define TXC_TRAINING_VEC_MASK 0x00000000ffffffffULL
2253
2254#define TXC_DEBUG (FZC_TXC + 0x20010UL)
2255#define TXC_DEBUG_SELECT 0x000000000000003fULL
2256
2257#define TXC_MAX_REORDER (FZC_TXC + 0x20018UL)
2258#define TXC_MAX_REORDER_PORT3 0x000000000f000000ULL
2259#define TXC_MAX_REORDER_PORT2 0x00000000000f0000ULL
2260#define TXC_MAX_REORDER_PORT1 0x0000000000000f00ULL
2261#define TXC_MAX_REORDER_PORT0 0x000000000000000fULL
2262
2263#define TXC_PORT_CTL(PORT) (FZC_TXC + 0x20020UL + (PORT)*0x100UL)
2264#define TXC_PORT_CTL_CLR_ALL_STAT 0x0000000000000001ULL
2265
2266#define TXC_PKT_STUFFED(PORT) (FZC_TXC + 0x20030UL + (PORT)*0x100UL)
2267#define TXC_PKT_STUFFED_PP_REORDER 0x00000000ffff0000ULL
2268#define TXC_PKT_STUFFED_PP_PACKETASSY 0x000000000000ffffULL
2269
2270#define TXC_PKT_XMIT(PORT) (FZC_TXC + 0x20038UL + (PORT)*0x100UL)
2271#define TXC_PKT_XMIT_BYTES 0x00000000ffff0000ULL
2272#define TXC_PKT_XMIT_PKTS 0x000000000000ffffULL
2273
2274#define TXC_ROECC_CTL(PORT) (FZC_TXC + 0x20040UL + (PORT)*0x100UL)
2275#define TXC_ROECC_CTL_DISABLE_UE 0x0000000080000000ULL
2276#define TXC_ROECC_CTL_DBL_BIT_ERR 0x0000000000020000ULL
2277#define TXC_ROECC_CTL_SNGL_BIT_ERR 0x0000000000010000ULL
2278#define TXC_ROECC_CTL_ALL_PKTS 0x0000000000000400ULL
2279#define TXC_ROECC_CTL_ALT_PKTS 0x0000000000000200ULL
2280#define TXC_ROECC_CTL_ONE_PKT_ONLY 0x0000000000000100ULL
2281#define TXC_ROECC_CTL_LST_PKT_LINE 0x0000000000000004ULL
2282#define TXC_ROECC_CTL_2ND_PKT_LINE 0x0000000000000002ULL
2283#define TXC_ROECC_CTL_1ST_PKT_LINE 0x0000000000000001ULL
2284
2285#define TXC_ROECC_ST(PORT) (FZC_TXC + 0x20048UL + (PORT)*0x100UL)
2286#define TXC_ROECC_CLR_ST 0x0000000080000000ULL
2287#define TXC_ROECC_CE 0x0000000000020000ULL
2288#define TXC_ROECC_UE 0x0000000000010000ULL
2289#define TXC_ROECC_ST_ECC_ADDR 0x00000000000003ffULL
2290
2291#define TXC_RO_DATA0(PORT) (FZC_TXC + 0x20050UL + (PORT)*0x100UL)
2292#define TXC_RO_DATA0_DATA0 0x00000000ffffffffULL /* bits 31:0 */
2293
2294#define TXC_RO_DATA1(PORT) (FZC_TXC + 0x20058UL + (PORT)*0x100UL)
2295#define TXC_RO_DATA1_DATA1 0x00000000ffffffffULL /* bits 63:32 */
2296
2297#define TXC_RO_DATA2(PORT) (FZC_TXC + 0x20060UL + (PORT)*0x100UL)
2298#define TXC_RO_DATA2_DATA2 0x00000000ffffffffULL /* bits 95:64 */
2299
2300#define TXC_RO_DATA3(PORT) (FZC_TXC + 0x20068UL + (PORT)*0x100UL)
2301#define TXC_RO_DATA3_DATA3 0x00000000ffffffffULL /* bits 127:96 */
2302
2303#define TXC_RO_DATA4(PORT) (FZC_TXC + 0x20070UL + (PORT)*0x100UL)
2304#define TXC_RO_DATA4_DATA4 0x0000000000ffffffULL /* bits 151:128 */
2305
2306#define TXC_SFECC_CTL(PORT) (FZC_TXC + 0x20078UL + (PORT)*0x100UL)
2307#define TXC_SFECC_CTL_DISABLE_UE 0x0000000080000000ULL
2308#define TXC_SFECC_CTL_DBL_BIT_ERR 0x0000000000020000ULL
2309#define TXC_SFECC_CTL_SNGL_BIT_ERR 0x0000000000010000ULL
2310#define TXC_SFECC_CTL_ALL_PKTS 0x0000000000000400ULL
2311#define TXC_SFECC_CTL_ALT_PKTS 0x0000000000000200ULL
2312#define TXC_SFECC_CTL_ONE_PKT_ONLY 0x0000000000000100ULL
2313#define TXC_SFECC_CTL_LST_PKT_LINE 0x0000000000000004ULL
2314#define TXC_SFECC_CTL_2ND_PKT_LINE 0x0000000000000002ULL
2315#define TXC_SFECC_CTL_1ST_PKT_LINE 0x0000000000000001ULL
2316
2317#define TXC_SFECC_ST(PORT) (FZC_TXC + 0x20080UL + (PORT)*0x100UL)
2318#define TXC_SFECC_ST_CLR_ST 0x0000000080000000ULL
2319#define TXC_SFECC_ST_CE 0x0000000000020000ULL
2320#define TXC_SFECC_ST_UE 0x0000000000010000ULL
2321#define TXC_SFECC_ST_ECC_ADDR 0x00000000000003ffULL
2322
2323#define TXC_SF_DATA0(PORT) (FZC_TXC + 0x20088UL + (PORT)*0x100UL)
2324#define TXC_SF_DATA0_DATA0 0x00000000ffffffffULL /* bits 31:0 */
2325
2326#define TXC_SF_DATA1(PORT) (FZC_TXC + 0x20090UL + (PORT)*0x100UL)
2327#define TXC_SF_DATA1_DATA1 0x00000000ffffffffULL /* bits 63:32 */
2328
2329#define TXC_SF_DATA2(PORT) (FZC_TXC + 0x20098UL + (PORT)*0x100UL)
2330#define TXC_SF_DATA2_DATA2 0x00000000ffffffffULL /* bits 95:64 */
2331
2332#define TXC_SF_DATA3(PORT) (FZC_TXC + 0x200a0UL + (PORT)*0x100UL)
2333#define TXC_SF_DATA3_DATA3 0x00000000ffffffffULL /* bits 127:96 */
2334
2335#define TXC_SF_DATA4(PORT) (FZC_TXC + 0x200a8UL + (PORT)*0x100UL)
2336#define TXC_SF_DATA4_DATA4 0x0000000000ffffffULL /* bits 151:128 */
2337
2338#define TXC_RO_TIDS(PORT) (FZC_TXC + 0x200b0UL + (PORT)*0x100UL)
2339#define TXC_RO_TIDS_IN_USE 0x00000000ffffffffULL
2340
2341#define TXC_RO_STATE0(PORT) (FZC_TXC + 0x200b8UL + (PORT)*0x100UL)
2342#define TXC_RO_STATE0_DUPLICATE_TID 0x00000000ffffffffULL
2343
2344#define TXC_RO_STATE1(PORT) (FZC_TXC + 0x200c0UL + (PORT)*0x100UL)
2345#define TXC_RO_STATE1_UNUSED_TID 0x00000000ffffffffULL
2346
2347#define TXC_RO_STATE2(PORT) (FZC_TXC + 0x200c8UL + (PORT)*0x100UL)
2348#define TXC_RO_STATE2_TRANS_TIMEOUT 0x00000000ffffffffULL
2349
2350#define TXC_RO_STATE3(PORT) (FZC_TXC + 0x200d0UL + (PORT)*0x100UL)
2351#define TXC_RO_STATE3_ENAB_SPC_WMARK 0x0000000080000000ULL
2352#define TXC_RO_STATE3_RO_SPC_WMARK 0x000000007fe00000ULL
2353#define TXC_RO_STATE3_ROFIFO_SPC_AVAIL 0x00000000001ff800ULL
2354#define TXC_RO_STATE3_ENAB_RO_WMARK 0x0000000000000100ULL
2355#define TXC_RO_STATE3_HIGH_RO_USED 0x00000000000000f0ULL
2356#define TXC_RO_STATE3_NUM_RO_USED 0x000000000000000fULL
2357
2358#define TXC_RO_CTL(PORT) (FZC_TXC + 0x200d8UL + (PORT)*0x100UL)
2359#define TXC_RO_CTL_CLR_FAIL_STATE 0x0000000080000000ULL
2360#define TXC_RO_CTL_RO_ADDR 0x000000000f000000ULL
2361#define TXC_RO_CTL_ADDR_FAILED 0x0000000000400000ULL
2362#define TXC_RO_CTL_DMA_FAILED 0x0000000000200000ULL
2363#define TXC_RO_CTL_LEN_FAILED 0x0000000000100000ULL
2364#define TXC_RO_CTL_CAPT_ADDR_FAILED 0x0000000000040000ULL
2365#define TXC_RO_CTL_CAPT_DMA_FAILED 0x0000000000020000ULL
2366#define TXC_RO_CTL_CAPT_LEN_FAILED 0x0000000000010000ULL
2367#define TXC_RO_CTL_RO_STATE_RD_DONE 0x0000000000000080ULL
2368#define TXC_RO_CTL_RO_STATE_WR_DONE 0x0000000000000040ULL
2369#define TXC_RO_CTL_RO_STATE_RD 0x0000000000000020ULL
2370#define TXC_RO_CTL_RO_STATE_WR 0x0000000000000010ULL
2371#define TXC_RO_CTL_RO_STATE_ADDR 0x000000000000000fULL
2372
2373#define TXC_RO_ST_DATA0(PORT) (FZC_TXC + 0x200e0UL + (PORT)*0x100UL)
2374#define TXC_RO_ST_DATA0_DATA0 0x00000000ffffffffULL
2375
2376#define TXC_RO_ST_DATA1(PORT) (FZC_TXC + 0x200e8UL + (PORT)*0x100UL)
2377#define TXC_RO_ST_DATA1_DATA1 0x00000000ffffffffULL
2378
2379#define TXC_RO_ST_DATA2(PORT) (FZC_TXC + 0x200f0UL + (PORT)*0x100UL)
2380#define TXC_RO_ST_DATA2_DATA2 0x00000000ffffffffULL
2381
2382#define TXC_RO_ST_DATA3(PORT) (FZC_TXC + 0x200f8UL + (PORT)*0x100UL)
2383#define TXC_RO_ST_DATA3_DATA3 0x00000000ffffffffULL
2384
2385#define TXC_PORT_PACKET_REQ(PORT) (FZC_TXC + 0x20100UL + (PORT)*0x100UL)
2386#define TXC_PORT_PACKET_REQ_GATHER_REQ 0x00000000f0000000ULL
2387#define TXC_PORT_PACKET_REQ_PKT_REQ 0x000000000fff0000ULL
2388#define TXC_PORT_PACKET_REQ_PERR_ABRT 0x000000000000ffffULL
2389
2390 /* bits are same as TXC_INT_STAT */
2391#define TXC_INT_STAT_DBG (FZC_TXC + 0x20420UL)
2392
2393#define TXC_INT_STAT (FZC_TXC + 0x20428UL)
2394#define TXC_INT_STAT_VAL_SHIFT(PORT) ((PORT) * 8)
2395#define TXC_INT_STAT_VAL(PORT) (0x3f << TXC_INT_STAT_VAL_SHIFT(PORT))
2396#define TXC_INT_STAT_SF_CE(PORT) (0x01 << TXC_INT_STAT_VAL_SHIFT(PORT))
2397#define TXC_INT_STAT_SF_UE(PORT) (0x02 << TXC_INT_STAT_VAL_SHIFT(PORT))
2398#define TXC_INT_STAT_RO_CE(PORT) (0x04 << TXC_INT_STAT_VAL_SHIFT(PORT))
2399#define TXC_INT_STAT_RO_UE(PORT) (0x08 << TXC_INT_STAT_VAL_SHIFT(PORT))
2400#define TXC_INT_STAT_REORDER_ERR(PORT) (0x10 << TXC_INT_STAT_VAL_SHIFT(PORT))
2401#define TXC_INT_STAT_PKTASM_DEAD(PORT) (0x20 << TXC_INT_STAT_VAL_SHIFT(PORT))
2402
2403#define TXC_INT_MASK (FZC_TXC + 0x20430UL)
2404#define TXC_INT_MASK_VAL_SHIFT(PORT) ((PORT) * 8)
2405#define TXC_INT_MASK_VAL(PORT) (0x3f << TXC_INT_STAT_VAL_SHIFT(PORT))
2406
2407#define TXC_INT_MASK_SF_CE 0x01
2408#define TXC_INT_MASK_SF_UE 0x02
2409#define TXC_INT_MASK_RO_CE 0x04
2410#define TXC_INT_MASK_RO_UE 0x08
2411#define TXC_INT_MASK_REORDER_ERR 0x10
2412#define TXC_INT_MASK_PKTASM_DEAD 0x20
2413#define TXC_INT_MASK_ALL 0x3f
2414
2415#define TXC_PORT_DMA(IDX) (FZC_TXC + 0x20028UL + (IDX)*0x100UL)
2416
2417#define ESPC_PIO_EN (FZC_PROM + 0x40000UL)
2418#define ESPC_PIO_EN_ENABLE 0x0000000000000001ULL
2419
2420#define ESPC_PIO_STAT (FZC_PROM + 0x40008UL)
2421#define ESPC_PIO_STAT_READ_START 0x0000000080000000ULL
2422#define ESPC_PIO_STAT_READ_END 0x0000000040000000ULL
2423#define ESPC_PIO_STAT_WRITE_INIT 0x0000000020000000ULL
2424#define ESPC_PIO_STAT_WRITE_END 0x0000000010000000ULL
2425#define ESPC_PIO_STAT_ADDR 0x0000000003ffff00ULL
2426#define ESPC_PIO_STAT_ADDR_SHIFT 8
2427#define ESPC_PIO_STAT_DATA 0x00000000000000ffULL
2428#define ESPC_PIO_STAT_DATA_SHIFT 0
2429
2430#define ESPC_NCR(IDX) (FZC_PROM + 0x40020UL + (IDX)*0x8UL)
2431#define ESPC_NCR_VAL 0x00000000ffffffffULL
2432
2433#define ESPC_MAC_ADDR0 ESPC_NCR(0)
2434#define ESPC_MAC_ADDR1 ESPC_NCR(1)
2435#define ESPC_NUM_PORTS_MACS ESPC_NCR(2)
2436#define ESPC_NUM_PORTS_MACS_VAL 0x00000000000000ffULL
2437#define ESPC_MOD_STR_LEN ESPC_NCR(4)
2438#define ESPC_MOD_STR_1 ESPC_NCR(5)
2439#define ESPC_MOD_STR_2 ESPC_NCR(6)
2440#define ESPC_MOD_STR_3 ESPC_NCR(7)
2441#define ESPC_MOD_STR_4 ESPC_NCR(8)
2442#define ESPC_MOD_STR_5 ESPC_NCR(9)
2443#define ESPC_MOD_STR_6 ESPC_NCR(10)
2444#define ESPC_MOD_STR_7 ESPC_NCR(11)
2445#define ESPC_MOD_STR_8 ESPC_NCR(12)
2446#define ESPC_BD_MOD_STR_LEN ESPC_NCR(13)
2447#define ESPC_BD_MOD_STR_1 ESPC_NCR(14)
2448#define ESPC_BD_MOD_STR_2 ESPC_NCR(15)
2449#define ESPC_BD_MOD_STR_3 ESPC_NCR(16)
2450#define ESPC_BD_MOD_STR_4 ESPC_NCR(17)
2451
2452#define ESPC_PHY_TYPE ESPC_NCR(18)
2453#define ESPC_PHY_TYPE_PORT0 0x00000000ff000000ULL
2454#define ESPC_PHY_TYPE_PORT0_SHIFT 24
2455#define ESPC_PHY_TYPE_PORT1 0x0000000000ff0000ULL
2456#define ESPC_PHY_TYPE_PORT1_SHIFT 16
2457#define ESPC_PHY_TYPE_PORT2 0x000000000000ff00ULL
2458#define ESPC_PHY_TYPE_PORT2_SHIFT 8
2459#define ESPC_PHY_TYPE_PORT3 0x00000000000000ffULL
2460#define ESPC_PHY_TYPE_PORT3_SHIFT 0
2461
2462#define ESPC_PHY_TYPE_1G_COPPER 3
2463#define ESPC_PHY_TYPE_1G_FIBER 2
2464#define ESPC_PHY_TYPE_10G_COPPER 1
2465#define ESPC_PHY_TYPE_10G_FIBER 0
2466
2467#define ESPC_MAX_FM_SZ ESPC_NCR(19)
2468
2469#define ESPC_INTR_NUM ESPC_NCR(20)
2470#define ESPC_INTR_NUM_PORT0 0x00000000ff000000ULL
2471#define ESPC_INTR_NUM_PORT1 0x0000000000ff0000ULL
2472#define ESPC_INTR_NUM_PORT2 0x000000000000ff00ULL
2473#define ESPC_INTR_NUM_PORT3 0x00000000000000ffULL
2474
2475#define ESPC_VER_IMGSZ ESPC_NCR(21)
2476#define ESPC_VER_IMGSZ_IMGSZ 0x00000000ffff0000ULL
2477#define ESPC_VER_IMGSZ_IMGSZ_SHIFT 16
2478#define ESPC_VER_IMGSZ_VER 0x000000000000ffffULL
2479#define ESPC_VER_IMGSZ_VER_SHIFT 0
2480
2481#define ESPC_CHKSUM ESPC_NCR(22)
2482#define ESPC_CHKSUM_SUM 0x00000000000000ffULL
2483
2484#define ESPC_EEPROM_SIZE 0x100000
2485
2486#define CLASS_CODE_UNRECOG 0x00
2487#define CLASS_CODE_DUMMY1 0x01
2488#define CLASS_CODE_ETHERTYPE1 0x02
2489#define CLASS_CODE_ETHERTYPE2 0x03
2490#define CLASS_CODE_USER_PROG1 0x04
2491#define CLASS_CODE_USER_PROG2 0x05
2492#define CLASS_CODE_USER_PROG3 0x06
2493#define CLASS_CODE_USER_PROG4 0x07
2494#define CLASS_CODE_TCP_IPV4 0x08
2495#define CLASS_CODE_UDP_IPV4 0x09
2496#define CLASS_CODE_AH_ESP_IPV4 0x0a
2497#define CLASS_CODE_SCTP_IPV4 0x0b
2498#define CLASS_CODE_TCP_IPV6 0x0c
2499#define CLASS_CODE_UDP_IPV6 0x0d
2500#define CLASS_CODE_AH_ESP_IPV6 0x0e
2501#define CLASS_CODE_SCTP_IPV6 0x0f
2502#define CLASS_CODE_ARP 0x10
2503#define CLASS_CODE_RARP 0x11
2504#define CLASS_CODE_DUMMY2 0x12
2505#define CLASS_CODE_DUMMY3 0x13
2506#define CLASS_CODE_DUMMY4 0x14
2507#define CLASS_CODE_DUMMY5 0x15
2508#define CLASS_CODE_DUMMY6 0x16
2509#define CLASS_CODE_DUMMY7 0x17
2510#define CLASS_CODE_DUMMY8 0x18
2511#define CLASS_CODE_DUMMY9 0x19
2512#define CLASS_CODE_DUMMY10 0x1a
2513#define CLASS_CODE_DUMMY11 0x1b
2514#define CLASS_CODE_DUMMY12 0x1c
2515#define CLASS_CODE_DUMMY13 0x1d
2516#define CLASS_CODE_DUMMY14 0x1e
2517#define CLASS_CODE_DUMMY15 0x1f
2518
2519/* Logical devices and device groups */
2520#define LDN_RXDMA(CHAN) (0 + (CHAN))
2521#define LDN_RESV1(OFF) (16 + (OFF))
2522#define LDN_TXDMA(CHAN) (32 + (CHAN))
2523#define LDN_RESV2(OFF) (56 + (OFF))
2524#define LDN_MIF 63
2525#define LDN_MAC(PORT) (64 + (PORT))
2526#define LDN_DEVICE_ERROR 68
2527#define LDN_MAX LDN_DEVICE_ERROR
2528
2529#define NIU_LDG_MIN 0
2530#define NIU_LDG_MAX 63
2531#define NIU_NUM_LDG 64
2532#define LDG_INVALID 0xff
2533
2534/* PHY stuff */
2535#define NIU_PMA_PMD_DEV_ADDR 1
2536#define NIU_PCS_DEV_ADDR 3
2537
2538#define NIU_PHY_ID_MASK 0xfffff0f0
2539#define NIU_PHY_ID_BCM8704 0x00206030
2540#define NIU_PHY_ID_BCM5464R 0x002060b0
2541
2542#define BCM8704_PMA_PMD_DEV_ADDR 1
2543#define BCM8704_PCS_DEV_ADDR 2
2544#define BCM8704_USER_DEV3_ADDR 3
2545#define BCM8704_PHYXS_DEV_ADDR 4
2546#define BCM8704_USER_DEV4_ADDR 4
2547
2548#define BCM8704_PMD_RCV_SIGDET 0x000a
2549#define PMD_RCV_SIGDET_LANE3 0x0010
2550#define PMD_RCV_SIGDET_LANE2 0x0008
2551#define PMD_RCV_SIGDET_LANE1 0x0004
2552#define PMD_RCV_SIGDET_LANE0 0x0002
2553#define PMD_RCV_SIGDET_GLOBAL 0x0001
2554
2555#define BCM8704_PCS_10G_R_STATUS 0x0020
2556#define PCS_10G_R_STATUS_LINKSTAT 0x1000
2557#define PCS_10G_R_STATUS_PRBS31_ABLE 0x0004
2558#define PCS_10G_R_STATUS_HI_BER 0x0002
2559#define PCS_10G_R_STATUS_BLK_LOCK 0x0001
2560
2561#define BCM8704_USER_CONTROL 0xc800
2562#define USER_CONTROL_OPTXENB_LVL 0x8000
2563#define USER_CONTROL_OPTXRST_LVL 0x4000
2564#define USER_CONTROL_OPBIASFLT_LVL 0x2000
2565#define USER_CONTROL_OBTMPFLT_LVL 0x1000
2566#define USER_CONTROL_OPPRFLT_LVL 0x0800
2567#define USER_CONTROL_OPTXFLT_LVL 0x0400
2568#define USER_CONTROL_OPRXLOS_LVL 0x0200
2569#define USER_CONTROL_OPRXFLT_LVL 0x0100
2570#define USER_CONTROL_OPTXON_LVL 0x0080
2571#define USER_CONTROL_RES1 0x007f
2572#define USER_CONTROL_RES1_SHIFT 0
2573
2574#define BCM8704_USER_ANALOG_CLK 0xc801
2575#define BCM8704_USER_PMD_RX_CONTROL 0xc802
2576
2577#define BCM8704_USER_PMD_TX_CONTROL 0xc803
2578#define USER_PMD_TX_CTL_RES1 0xfe00
2579#define USER_PMD_TX_CTL_XFP_CLKEN 0x0100
2580#define USER_PMD_TX_CTL_TX_DAC_TXD 0x00c0
2581#define USER_PMD_TX_CTL_TX_DAC_TXD_SH 6
2582#define USER_PMD_TX_CTL_TX_DAC_TXCK 0x0030
2583#define USER_PMD_TX_CTL_TX_DAC_TXCK_SH 4
2584#define USER_PMD_TX_CTL_TSD_LPWREN 0x0008
2585#define USER_PMD_TX_CTL_TSCK_LPWREN 0x0004
2586#define USER_PMD_TX_CTL_CMU_LPWREN 0x0002
2587#define USER_PMD_TX_CTL_SFIFORST 0x0001
2588
2589#define BCM8704_USER_ANALOG_STATUS0 0xc804
2590#define BCM8704_USER_OPT_DIGITAL_CTRL 0xc808
2591#define BCM8704_USER_TX_ALARM_STATUS 0x9004
2592
2593#define USER_ODIG_CTRL_FMODE 0x8000
2594#define USER_ODIG_CTRL_TX_PDOWN 0x4000
2595#define USER_ODIG_CTRL_RX_PDOWN 0x2000
2596#define USER_ODIG_CTRL_EFILT_EN 0x1000
2597#define USER_ODIG_CTRL_OPT_RST 0x0800
2598#define USER_ODIG_CTRL_PCS_TIB 0x0400
2599#define USER_ODIG_CTRL_PCS_RI 0x0200
2600#define USER_ODIG_CTRL_RESV1 0x0180
2601#define USER_ODIG_CTRL_GPIOS 0x0060
2602#define USER_ODIG_CTRL_GPIOS_SHIFT 5
2603#define USER_ODIG_CTRL_RESV2 0x0010
2604#define USER_ODIG_CTRL_LB_ERR_DIS 0x0008
2605#define USER_ODIG_CTRL_RESV3 0x0006
2606#define USER_ODIG_CTRL_TXONOFF_PD_DIS 0x0001
2607
2608#define BCM8704_PHYXS_XGXS_LANE_STAT 0x0018
2609#define PHYXS_XGXS_LANE_STAT_ALINGED 0x1000
2610#define PHYXS_XGXS_LANE_STAT_PATTEST 0x0800
2611#define PHYXS_XGXS_LANE_STAT_MAGIC 0x0400
2612#define PHYXS_XGXS_LANE_STAT_LANE3 0x0008
2613#define PHYXS_XGXS_LANE_STAT_LANE2 0x0004
2614#define PHYXS_XGXS_LANE_STAT_LANE1 0x0002
2615#define PHYXS_XGXS_LANE_STAT_LANE0 0x0001
2616
2617#define BCM5464R_AUX_CTL 24
2618#define BCM5464R_AUX_CTL_EXT_LB 0x8000
2619#define BCM5464R_AUX_CTL_EXT_PLEN 0x4000
2620#define BCM5464R_AUX_CTL_ER1000 0x3000
2621#define BCM5464R_AUX_CTL_ER1000_SHIFT 12
2622#define BCM5464R_AUX_CTL_RESV1 0x0800
2623#define BCM5464R_AUX_CTL_WRITE_1 0x0400
2624#define BCM5464R_AUX_CTL_RESV2 0x0300
2625#define BCM5464R_AUX_CTL_PRESP_DIS 0x0080
2626#define BCM5464R_AUX_CTL_RESV3 0x0040
2627#define BCM5464R_AUX_CTL_ER100 0x0030
2628#define BCM5464R_AUX_CTL_ER100_SHIFT 4
2629#define BCM5464R_AUX_CTL_DIAG_MODE 0x0008
2630#define BCM5464R_AUX_CTL_SR_SEL 0x0007
2631#define BCM5464R_AUX_CTL_SR_SEL_SHIFT 0
2632
2633#define BCM5464R_CTRL1000_AS_MASTER 0x0800
2634#define BCM5464R_CTRL1000_ENABLE_AS_MASTER 0x1000
2635
2636#define RCR_ENTRY_MULTI 0x8000000000000000ULL
2637#define RCR_ENTRY_PKT_TYPE 0x6000000000000000ULL
2638#define RCR_ENTRY_PKT_TYPE_SHIFT 61
2639#define RCR_ENTRY_ZERO_COPY 0x1000000000000000ULL
2640#define RCR_ENTRY_NOPORT 0x0800000000000000ULL
2641#define RCR_ENTRY_PROMISC 0x0400000000000000ULL
2642#define RCR_ENTRY_ERROR 0x0380000000000000ULL
2643#define RCR_ENTRY_DCF_ERR 0x0040000000000000ULL
2644#define RCR_ENTRY_L2_LEN 0x003fff0000000000ULL
2645#define RCR_ENTRY_L2_LEN_SHIFT 40
2646#define RCR_ENTRY_PKTBUFSZ 0x000000c000000000ULL
2647#define RCR_ENTRY_PKTBUFSZ_SHIFT 38
2648#define RCR_ENTRY_PKT_BUF_ADDR 0x0000003fffffffffULL /* bits 43:6 */
2649#define RCR_ENTRY_PKT_BUF_ADDR_SHIFT 6
2650
2651#define RCR_PKT_TYPE_OTHER 0x0
2652#define RCR_PKT_TYPE_TCP 0x1
2653#define RCR_PKT_TYPE_UDP 0x2
2654#define RCR_PKT_TYPE_SCTP 0x3
2655
2656#define NIU_RXPULL_MAX ETH_HLEN
2657
2658struct rx_pkt_hdr0 {
2659#if defined(__LITTLE_ENDIAN_BITFIELD)
2660 u8 inputport:2,
2661 maccheck:1,
2662 class:4;
2663 u8 vlan:1,
2664 llcsnap:1,
2665 noport:1,
2666 badip:1,
2667 tcamhit:1,
2668 tres:2,
2669 tzfvld:1;
2670#elif defined(__BIG_ENDIAN_BITFIELD)
2671 u8 class:4,
2672 maccheck:1,
2673 inputport:2;
2674 u8 tzfvld:1,
2675 tres:2,
2676 tcamhit:1,
2677 badip:1,
2678 noport:1,
2679 llcsnap:1,
2680 vlan:1;
2681#endif
2682};
2683
2684struct rx_pkt_hdr1 {
2685 u8 hwrsvd1;
2686 u8 tcammatch;
2687#if defined(__LITTLE_ENDIAN_BITFIELD)
2688 u8 hwrsvd2:2,
2689 hashit:1,
2690 exact:1,
2691 hzfvld:1,
2692 hashsidx:3;
2693#elif defined(__BIG_ENDIAN_BITFIELD)
2694 u8 hashsidx:3,
2695 hzfvld:1,
2696 exact:1,
2697 hashit:1,
2698 hwrsvd2:2;
2699#endif
2700 u8 zcrsvd;
2701
2702 /* Bits 11:8 of zero copy flow ID. */
2703#if defined(__LITTLE_ENDIAN_BITFIELD)
2704 u8 hwrsvd3:4, zflowid0:4;
2705#elif defined(__BIG_ENDIAN_BITFIELD)
2706 u8 zflowid0:4, hwrsvd3:4;
2707#endif
2708
2709 /* Bits 7:0 of zero copy flow ID. */
2710 u8 zflowid1;
2711
2712 /* Bits 15:8 of hash value, H2. */
2713 u8 hashval2_0;
2714
2715 /* Bits 7:0 of hash value, H2. */
2716 u8 hashval2_1;
2717
2718 /* Bits 19:16 of hash value, H1. */
2719#if defined(__LITTLE_ENDIAN_BITFIELD)
2720 u8 hwrsvd4:4, hashval1_0:4;
2721#elif defined(__BIG_ENDIAN_BITFIELD)
2722 u8 hashval1_0:4, hwrsvd4:4;
2723#endif
2724
2725 /* Bits 15:8 of hash value, H1. */
2726 u8 hashval1_1;
2727
2728 /* Bits 7:0 of hash value, H1. */
2729 u8 hashval1_2;
2730
2731 u8 usrdata_0; /* Bits 39:32 of user data. */
2732 u8 usrdata_1; /* Bits 31:24 of user data. */
2733 u8 usrdata_2; /* Bits 23:16 of user data. */
2734 u8 usrdata_3; /* Bits 15:8 of user data. */
2735 u8 usrdata_4; /* Bits 7:0 of user data. */
2736};
2737
2738struct tx_dma_mbox {
2739 u64 tx_dma_pre_st;
2740 u64 tx_cs;
2741 u64 tx_ring_kick;
2742 u64 tx_ring_hdl;
2743 u64 resv1;
2744 u32 tx_rng_err_logl;
2745 u32 tx_rng_err_logh;
2746 u64 resv2;
2747 u64 resv3;
2748};
2749
2750struct tx_pkt_hdr {
2751 __le64 flags;
2752#define TXHDR_PAD 0x0000000000000007ULL
2753#define TXHDR_PAD_SHIFT 0
2754#define TXHDR_LEN 0x000000003fff0000ULL
2755#define TXHDR_LEN_SHIFT 16
2756#define TXHDR_L4STUFF 0x0000003f00000000ULL
2757#define TXHDR_L4STUFF_SHIFT 32
2758#define TXHDR_L4START 0x00003f0000000000ULL
2759#define TXHDR_L4START_SHIFT 40
2760#define TXHDR_L3START 0x000f000000000000ULL
2761#define TXHDR_L3START_SHIFT 48
2762#define TXHDR_IHL 0x00f0000000000000ULL
2763#define TXHDR_IHL_SHIFT 52
2764#define TXHDR_VLAN 0x0100000000000000ULL
2765#define TXHDR_LLC 0x0200000000000000ULL
2766#define TXHDR_IP_VER 0x2000000000000000ULL
2767#define TXHDR_CSUM_NONE 0x0000000000000000ULL
2768#define TXHDR_CSUM_TCP 0x4000000000000000ULL
2769#define TXHDR_CSUM_UDP 0x8000000000000000ULL
2770#define TXHDR_CSUM_SCTP 0xc000000000000000ULL
2771 __le64 resv;
2772};
2773
2774#define TX_DESC_SOP 0x8000000000000000ULL
2775#define TX_DESC_MARK 0x4000000000000000ULL
2776#define TX_DESC_NUM_PTR 0x3c00000000000000ULL
2777#define TX_DESC_NUM_PTR_SHIFT 58
2778#define TX_DESC_TR_LEN 0x01fff00000000000ULL
2779#define TX_DESC_TR_LEN_SHIFT 44
2780#define TX_DESC_SAD 0x00000fffffffffffULL
2781#define TX_DESC_SAD_SHIFT 0
2782
2783struct tx_buff_info {
2784 struct sk_buff *skb;
2785 u64 mapping;
2786};
2787
2788struct txdma_mailbox {
2789 __le64 tx_dma_pre_st;
2790 __le64 tx_cs;
2791 __le64 tx_ring_kick;
2792 __le64 tx_ring_hdl;
2793 __le64 resv1;
2794 __le32 tx_rng_err_logl;
2795 __le32 tx_rng_err_logh;
2796 __le64 resv2[2];
2797} __attribute__((aligned(64)));
2798
2799#define MAX_TX_RING_SIZE 256
2800#define MAX_TX_DESC_LEN 4076
2801
2802struct tx_ring_info {
2803 struct tx_buff_info tx_buffs[MAX_TX_RING_SIZE];
2804 struct niu *np;
2805 u64 tx_cs;
2806 int pending;
2807 int prod;
2808 int cons;
2809 int wrap_bit;
2810 u16 last_pkt_cnt;
2811 u16 tx_channel;
2812 u16 mark_counter;
2813 u16 mark_freq;
2814 u16 mark_pending;
2815 u16 __pad;
2816 struct txdma_mailbox *mbox;
2817 __le64 *descr;
2818
2819 u64 tx_packets;
2820 u64 tx_bytes;
2821 u64 tx_errors;
2822
2823 u64 mbox_dma;
2824 u64 descr_dma;
2825 int max_burst;
2826};
2827
2828#define NEXT_TX(tp, index) \
2829 (((index) + 1) < (tp)->pending ? ((index) + 1) : 0)
2830
2831static inline u32 niu_tx_avail(struct tx_ring_info *tp)
2832{
2833 return (tp->pending -
2834 ((tp->prod - tp->cons) & (MAX_TX_RING_SIZE - 1)));
2835}
2836
2837struct rxdma_mailbox {
2838 __le64 rx_dma_ctl_stat;
2839 __le64 rbr_stat;
2840 __le32 rbr_hdl;
2841 __le32 rbr_hdh;
2842 __le64 resv1;
2843 __le32 rcrstat_c;
2844 __le32 rcrstat_b;
2845 __le64 rcrstat_a;
2846 __le64 resv2[2];
2847} __attribute__((aligned(64)));
2848
2849#define MAX_RBR_RING_SIZE 128
2850#define MAX_RCR_RING_SIZE (MAX_RBR_RING_SIZE * 2)
2851
2852#define RBR_REFILL_MIN 16
2853
2854#define RX_SKB_ALLOC_SIZE 128 + NET_IP_ALIGN
2855
2856struct rx_ring_info {
2857 struct niu *np;
2858 int rx_channel;
2859 u16 rbr_block_size;
2860 u16 rbr_blocks_per_page;
2861 u16 rbr_sizes[4];
2862 unsigned int rcr_index;
2863 unsigned int rcr_table_size;
2864 unsigned int rbr_index;
2865 unsigned int rbr_pending;
2866 unsigned int rbr_refill_pending;
2867 unsigned int rbr_kick_thresh;
2868 unsigned int rbr_table_size;
2869 struct page **rxhash;
2870 struct rxdma_mailbox *mbox;
2871 __le64 *rcr;
2872 __le32 *rbr;
2873#define RBR_DESCR_ADDR_SHIFT 12
2874
2875 u64 rx_packets;
2876 u64 rx_bytes;
2877 u64 rx_dropped;
2878 u64 rx_errors;
2879
2880 u64 mbox_dma;
2881 u64 rcr_dma;
2882 u64 rbr_dma;
2883
2884 /* WRED */
2885 int nonsyn_window;
2886 int nonsyn_threshold;
2887 int syn_window;
2888 int syn_threshold;
2889
2890 /* interrupt mitigation */
2891 int rcr_pkt_threshold;
2892 int rcr_timeout;
2893};
2894
2895#define NEXT_RCR(rp, index) \
2896 (((index) + 1) < (rp)->rcr_table_size ? ((index) + 1) : 0)
2897#define NEXT_RBR(rp, index) \
2898 (((index) + 1) < (rp)->rbr_table_size ? ((index) + 1) : 0)
2899
2900#define NIU_MAX_PORTS 4
2901#define NIU_NUM_RXCHAN 16
2902#define NIU_NUM_TXCHAN 24
2903#define MAC_NUM_HASH 16
2904
2905#define NIU_MAX_MTU 9216
2906
2907#define NIU_VPD_MIN_MAJOR 3
2908#define NIU_VPD_MIN_MINOR 4
2909
2910#define NIU_VPD_MODEL_MAX 32
2911#define NIU_VPD_BD_MODEL_MAX 16
2912#define NIU_VPD_VERSION_MAX 64
2913#define NIU_VPD_PHY_TYPE_MAX 8
2914
2915struct niu_vpd {
2916 char model[NIU_VPD_MODEL_MAX];
2917 char board_model[NIU_VPD_BD_MODEL_MAX];
2918 char version[NIU_VPD_VERSION_MAX];
2919 char phy_type[NIU_VPD_PHY_TYPE_MAX];
2920 u8 mac_num;
2921 u8 __pad;
2922 u8 local_mac[6];
2923 int fcode_major;
2924 int fcode_minor;
2925};
2926
2927struct niu_altmac_rdc {
2928 u8 alt_mac_num;
2929 u8 rdc_num;
2930 u8 mac_pref;
2931};
2932
2933struct niu_vlan_rdc {
2934 u8 rdc_num;
2935 u8 vlan_pref;
2936};
2937
2938struct niu_classifier {
2939 struct niu_altmac_rdc alt_mac_mappings[16];
2940 struct niu_vlan_rdc vlan_mappings[ENET_VLAN_TBL_NUM_ENTRIES];
2941
2942 u16 tcam_index;
2943 u16 num_alt_mac_mappings;
2944
2945 u32 h1_init;
2946 u16 h2_init;
2947};
2948
2949#define NIU_NUM_RDC_TABLES 8
2950#define NIU_RDC_TABLE_SLOTS 16
2951
2952struct rdc_table {
2953 u8 rxdma_channel[NIU_RDC_TABLE_SLOTS];
2954};
2955
2956struct niu_rdc_tables {
2957 struct rdc_table tables[NIU_NUM_RDC_TABLES];
2958 int first_table_num;
2959 int num_tables;
2960};
2961
2962#define PHY_TYPE_PMA_PMD 0
2963#define PHY_TYPE_PCS 1
2964#define PHY_TYPE_MII 2
2965#define PHY_TYPE_MAX 3
2966
2967struct phy_probe_info {
2968 u32 phy_id[PHY_TYPE_MAX][NIU_MAX_PORTS];
2969 u8 phy_port[PHY_TYPE_MAX][NIU_MAX_PORTS];
2970 u8 cur[PHY_TYPE_MAX];
2971
2972 struct device_attribute phy_port_attrs[PHY_TYPE_MAX * NIU_MAX_PORTS];
2973 struct device_attribute phy_type_attrs[PHY_TYPE_MAX * NIU_MAX_PORTS];
2974 struct device_attribute phy_id_attrs[PHY_TYPE_MAX * NIU_MAX_PORTS];
2975};
2976
2977struct niu_tcam_entry {
2978 u64 key[4];
2979 u64 key_mask[4];
2980 u64 assoc_data;
2981};
2982
2983struct device_node;
2984union niu_parent_id {
2985 struct {
2986 int domain;
2987 int bus;
2988 int device;
2989 } pci;
2990 struct device_node *of;
2991};
2992
2993struct niu;
2994struct niu_parent {
2995 struct platform_device *plat_dev;
2996 int index;
2997
2998 union niu_parent_id id;
2999
3000 struct niu *ports[NIU_MAX_PORTS];
3001
3002 atomic_t refcnt;
3003 struct list_head list;
3004
3005 spinlock_t lock;
3006
3007 u32 flags;
3008#define PARENT_FLGS_CLS_HWINIT 0x00000001
3009
3010 u32 port_phy;
3011#define PORT_PHY_UNKNOWN 0x00000000
3012#define PORT_PHY_INVALID 0xffffffff
3013#define PORT_TYPE_10G 0x01
3014#define PORT_TYPE_1G 0x02
3015#define PORT_TYPE_MASK 0x03
3016
3017 u8 rxchan_per_port[NIU_MAX_PORTS];
3018 u8 txchan_per_port[NIU_MAX_PORTS];
3019
3020 struct niu_rdc_tables rdc_group_cfg[NIU_MAX_PORTS];
3021 u8 rdc_default[NIU_MAX_PORTS];
3022
3023 u8 ldg_map[LDN_MAX + 1];
3024
3025 u8 plat_type;
3026#define PLAT_TYPE_INVALID 0x00
3027#define PLAT_TYPE_ATLAS 0x01
3028#define PLAT_TYPE_NIU 0x02
3029#define PLAT_TYPE_VF_P0 0x03
3030#define PLAT_TYPE_VF_P1 0x04
3031
3032 u8 num_ports;
3033
3034 u16 tcam_num_entries;
3035#define NIU_PCI_TCAM_ENTRIES 256
3036#define NIU_NONPCI_TCAM_ENTRIES 128
3037#define NIU_TCAM_ENTRIES_MAX 256
3038
3039 int rxdma_clock_divider;
3040
3041 struct phy_probe_info phy_probe_info;
3042
3043 struct niu_tcam_entry tcam[NIU_TCAM_ENTRIES_MAX];
3044 u64 l2_cls[2];
3045 u64 l3_cls[4];
3046 u64 tcam_key[12];
3047 u64 flow_key[12];
3048};
3049
3050struct niu_ops {
3051 void *(*alloc_coherent)(struct device *dev, size_t size,
3052 u64 *handle, gfp_t flag);
3053 void (*free_coherent)(struct device *dev, size_t size,
3054 void *cpu_addr, u64 handle);
3055 u64 (*map_page)(struct device *dev, struct page *page,
3056 unsigned long offset, size_t size,
3057 enum dma_data_direction direction);
3058 void (*unmap_page)(struct device *dev, u64 dma_address,
3059 size_t size, enum dma_data_direction direction);
3060 u64 (*map_single)(struct device *dev, void *cpu_addr,
3061 size_t size,
3062 enum dma_data_direction direction);
3063 void (*unmap_single)(struct device *dev, u64 dma_address,
3064 size_t size, enum dma_data_direction direction);
3065};
3066
3067struct niu_link_config {
3068 /* Describes what we're trying to get. */
3069 u32 advertising;
3070 u32 supported;
3071 u16 speed;
3072 u8 duplex;
3073 u8 autoneg;
3074
3075 /* Describes what we actually have. */
3076 u16 active_speed;
3077 u8 active_duplex;
3078#define SPEED_INVALID 0xffff
3079#define DUPLEX_INVALID 0xff
3080#define AUTONEG_INVALID 0xff
3081
3082 u8 loopback_mode;
3083#define LOOPBACK_DISABLED 0x00
3084#define LOOPBACK_PHY 0x01
3085#define LOOPBACK_MAC 0x02
3086};
3087
3088struct niu_ldg {
3089 struct napi_struct napi;
3090 struct niu *np;
3091 u8 ldg_num;
3092 u8 timer;
3093 u64 v0, v1, v2;
3094 unsigned int irq;
3095};
3096
3097struct niu_xmac_stats {
3098 u64 tx_frames;
3099 u64 tx_bytes;
3100 u64 tx_fifo_errors;
3101 u64 tx_overflow_errors;
3102 u64 tx_max_pkt_size_errors;
3103 u64 tx_underflow_errors;
3104
3105 u64 rx_local_faults;
3106 u64 rx_remote_faults;
3107 u64 rx_link_faults;
3108 u64 rx_align_errors;
3109 u64 rx_frags;
3110 u64 rx_mcasts;
3111 u64 rx_bcasts;
3112 u64 rx_hist_cnt1;
3113 u64 rx_hist_cnt2;
3114 u64 rx_hist_cnt3;
3115 u64 rx_hist_cnt4;
3116 u64 rx_hist_cnt5;
3117 u64 rx_hist_cnt6;
3118 u64 rx_hist_cnt7;
3119 u64 rx_octets;
3120 u64 rx_code_violations;
3121 u64 rx_len_errors;
3122 u64 rx_crc_errors;
3123 u64 rx_underflows;
3124 u64 rx_overflows;
3125
3126 u64 pause_off_state;
3127 u64 pause_on_state;
3128 u64 pause_received;
3129};
3130
3131struct niu_bmac_stats {
3132 u64 tx_underflow_errors;
3133 u64 tx_max_pkt_size_errors;
3134 u64 tx_bytes;
3135 u64 tx_frames;
3136
3137 u64 rx_overflows;
3138 u64 rx_frames;
3139 u64 rx_align_errors;
3140 u64 rx_crc_errors;
3141 u64 rx_len_errors;
3142
3143 u64 pause_off_state;
3144 u64 pause_on_state;
3145 u64 pause_received;
3146};
3147
3148union niu_mac_stats {
3149 struct niu_xmac_stats xmac;
3150 struct niu_bmac_stats bmac;
3151};
3152
3153struct niu_phy_ops {
3154 int (*serdes_init)(struct niu *np);
3155 int (*xcvr_init)(struct niu *np);
3156 int (*link_status)(struct niu *np, int *);
3157};
3158
3159struct of_device;
3160struct niu {
3161 void __iomem *regs;
3162 struct net_device *dev;
3163 struct pci_dev *pdev;
3164 struct device *device;
3165 struct niu_parent *parent;
3166
3167 u32 flags;
3168#define NIU_FLAGS_MSIX 0x00400000 /* MSI-X in use */
3169#define NIU_FLAGS_MCAST 0x00200000 /* multicast filter enabled */
3170#define NIU_FLAGS_PROMISC 0x00100000 /* PROMISC enabled */
3171#define NIU_FLAGS_VPD_VALID 0x00080000 /* VPD has valid version */
3172#define NIU_FLAGS_10G 0x00040000 /* 0=1G 1=10G */
3173#define NIU_FLAGS_FIBER 0x00020000 /* 0=COPPER 1=FIBER */
3174#define NIU_FLAGS_XMAC 0x00010000 /* 0=BMAC 1=XMAC */
3175
3176 u32 msg_enable;
3177
3178 /* Protects hw programming, and ring state. */
3179 spinlock_t lock;
3180
3181 const struct niu_ops *ops;
3182 struct net_device_stats net_stats;
3183 union niu_mac_stats mac_stats;
3184
3185 struct rx_ring_info *rx_rings;
3186 struct tx_ring_info *tx_rings;
3187 int num_rx_rings;
3188 int num_tx_rings;
3189
3190 struct niu_ldg ldg[NIU_NUM_LDG];
3191 int num_ldg;
3192
3193 void __iomem *mac_regs;
3194 unsigned long ipp_off;
3195 unsigned long pcs_off;
3196 unsigned long xpcs_off;
3197
3198 struct timer_list timer;
3199 const struct niu_phy_ops *phy_ops;
3200 int phy_addr;
3201
3202 struct niu_link_config link_config;
3203
3204 struct work_struct reset_task;
3205
3206 u8 port;
3207 u8 mac_xcvr;
3208#define MAC_XCVR_MII 1
3209#define MAC_XCVR_PCS 2
3210#define MAC_XCVR_XPCS 3
3211
3212 struct niu_classifier clas;
3213
3214 struct niu_vpd vpd;
3215 u32 eeprom_len;
3216
3217 struct of_device *op;
3218 void __iomem *vir_regs_1;
3219 void __iomem *vir_regs_2;
3220};
3221
3222#endif /* _NIU_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-03 20:27:15 -0400