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-rw-r--r--drivers/char/drm/drm_pciids.h4
-rw-r--r--drivers/char/drm/via_drv.h7
-rw-r--r--drivers/char/drm/via_irq.c16
-rw-r--r--drivers/char/drm/via_map.c3
-rw-r--r--drivers/char/drm/via_verifier.c20
5 files changed, 33 insertions, 17 deletions
diff --git a/drivers/char/drm/drm_pciids.h b/drivers/char/drm/drm_pciids.h
index 09398d5fbd3f..ad54b845978b 100644
--- a/drivers/char/drm/drm_pciids.h
+++ b/drivers/char/drm/drm_pciids.h
@@ -226,12 +226,14 @@
226 {0x1106, 0x3022, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 226 {0x1106, 0x3022, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
227 {0x1106, 0x3118, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_PRO_GROUP_A}, \ 227 {0x1106, 0x3118, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_PRO_GROUP_A}, \
228 {0x1106, 0x3122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 228 {0x1106, 0x3122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
229 {0x1106, 0x7204, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
229 {0x1106, 0x7205, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 230 {0x1106, 0x7205, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
230 {0x1106, 0x3108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 231 {0x1106, 0x3108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
231 {0x1106, 0x3304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 232 {0x1106, 0x3304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
232 {0x1106, 0x3157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 233 {0x1106, 0x3157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
233 {0x1106, 0x3344, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 234 {0x1106, 0x3344, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
234 {0x1106, 0x7204, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 235 {0x1106, 0x3343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
236 {0x1106, 0x3230, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_DX9_0}, \
235 {0, 0, 0} 237 {0, 0, 0}
236 238
237#define i810_PCI_IDS \ 239#define i810_PCI_IDS \
diff --git a/drivers/char/drm/via_drv.h b/drivers/char/drm/via_drv.h
index d21b5b75da0f..cfc20a06707e 100644
--- a/drivers/char/drm/via_drv.h
+++ b/drivers/char/drm/via_drv.h
@@ -79,7 +79,7 @@ typedef struct drm_via_private {
79 char pci_buf[VIA_PCI_BUF_SIZE]; 79 char pci_buf[VIA_PCI_BUF_SIZE];
80 const uint32_t *fire_offsets[VIA_FIRE_BUF_SIZE]; 80 const uint32_t *fire_offsets[VIA_FIRE_BUF_SIZE];
81 uint32_t num_fire_offsets; 81 uint32_t num_fire_offsets;
82 int pro_group_a; 82 int chipset;
83 drm_via_irq_t via_irqs[VIA_NUM_IRQS]; 83 drm_via_irq_t via_irqs[VIA_NUM_IRQS];
84 unsigned num_irqs; 84 unsigned num_irqs;
85 maskarray_t *irq_masks; 85 maskarray_t *irq_masks;
@@ -96,8 +96,9 @@ typedef struct drm_via_private {
96} drm_via_private_t; 96} drm_via_private_t;
97 97
98enum via_family { 98enum via_family {
99 VIA_OTHER = 0, 99 VIA_OTHER = 0, /* Baseline */
100 VIA_PRO_GROUP_A, 100 VIA_PRO_GROUP_A, /* Another video engine and DMA commands */
101 VIA_DX9_0 /* Same video as pro_group_a, but 3D is unsupported */
101}; 102};
102 103
103/* VIA MMIO register access */ 104/* VIA MMIO register access */
diff --git a/drivers/char/drm/via_irq.c b/drivers/char/drm/via_irq.c
index c33d068cde19..1ac5941ad237 100644
--- a/drivers/char/drm/via_irq.c
+++ b/drivers/char/drm/via_irq.c
@@ -258,12 +258,16 @@ void via_driver_irq_preinstall(drm_device_t * dev)
258 dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE; 258 dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;
259 dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING; 259 dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;
260 260
261 dev_priv->irq_masks = (dev_priv->pro_group_a) ? 261 if (dev_priv->chipset == VIA_PRO_GROUP_A ||
262 via_pro_group_a_irqs : via_unichrome_irqs; 262 dev_priv->chipset == VIA_DX9_0) {
263 dev_priv->num_irqs = (dev_priv->pro_group_a) ? 263 dev_priv->irq_masks = via_pro_group_a_irqs;
264 via_num_pro_group_a : via_num_unichrome; 264 dev_priv->num_irqs = via_num_pro_group_a;
265 dev_priv->irq_map = (dev_priv->pro_group_a) ? 265 dev_priv->irq_map = via_irqmap_pro_group_a;
266 via_irqmap_pro_group_a : via_irqmap_unichrome; 266 } else {
267 dev_priv->irq_masks = via_unichrome_irqs;
268 dev_priv->num_irqs = via_num_unichrome;
269 dev_priv->irq_map = via_irqmap_unichrome;
270 }
267 271
268 for (i = 0; i < dev_priv->num_irqs; ++i) { 272 for (i = 0; i < dev_priv->num_irqs; ++i) {
269 atomic_set(&cur_irq->irq_received, 0); 273 atomic_set(&cur_irq->irq_received, 0);
diff --git a/drivers/char/drm/via_map.c b/drivers/char/drm/via_map.c
index 782011e0a58d..4e3fc072aa3b 100644
--- a/drivers/char/drm/via_map.c
+++ b/drivers/char/drm/via_map.c
@@ -106,8 +106,7 @@ int via_driver_load(drm_device_t *dev, unsigned long chipset)
106 106
107 dev->dev_private = (void *)dev_priv; 107 dev->dev_private = (void *)dev_priv;
108 108
109 if (chipset == VIA_PRO_GROUP_A) 109 dev_priv->chipset = chipset;
110 dev_priv->pro_group_a = 1;
111 110
112 ret = drm_sman_init(&dev_priv->sman, 2, 12, 8); 111 ret = drm_sman_init(&dev_priv->sman, 2, 12, 8);
113 if (ret) { 112 if (ret) {
diff --git a/drivers/char/drm/via_verifier.c b/drivers/char/drm/via_verifier.c
index 70c897c88766..24fc7cb6e7da 100644
--- a/drivers/char/drm/via_verifier.c
+++ b/drivers/char/drm/via_verifier.c
@@ -961,7 +961,13 @@ via_verify_command_stream(const uint32_t * buf, unsigned int size,
961 uint32_t cmd; 961 uint32_t cmd;
962 const uint32_t *buf_end = buf + (size >> 2); 962 const uint32_t *buf_end = buf + (size >> 2);
963 verifier_state_t state = state_command; 963 verifier_state_t state = state_command;
964 int pro_group_a = dev_priv->pro_group_a; 964 int cme_video;
965 int supported_3d;
966
967 cme_video = (dev_priv->chipset == VIA_PRO_GROUP_A ||
968 dev_priv->chipset == VIA_DX9_0);
969
970 supported_3d = dev_priv->chipset != VIA_DX9_0;
965 971
966 hc_state->dev = dev; 972 hc_state->dev = dev;
967 hc_state->unfinished = no_sequence; 973 hc_state->unfinished = no_sequence;
@@ -986,17 +992,21 @@ via_verify_command_stream(const uint32_t * buf, unsigned int size,
986 state = via_check_vheader6(&buf, buf_end); 992 state = via_check_vheader6(&buf, buf_end);
987 break; 993 break;
988 case state_command: 994 case state_command:
989 if (HALCYON_HEADER2 == (cmd = *buf)) 995 if ((HALCYON_HEADER2 == (cmd = *buf)) &&
996 supported_3d)
990 state = state_header2; 997 state = state_header2;
991 else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) 998 else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
992 state = state_header1; 999 state = state_header1;
993 else if (pro_group_a 1000 else if (cme_video
994 && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5) 1001 && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5)
995 state = state_vheader5; 1002 state = state_vheader5;
996 else if (pro_group_a 1003 else if (cme_video
997 && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6) 1004 && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
998 state = state_vheader6; 1005 state = state_vheader6;
999 else { 1006 else if ((cmd == HALCYON_HEADER2) && !supported_3d) {
1007 DRM_ERROR("Accelerated 3D is not supported on this chipset yet.\n");
1008 state = state_error;
1009 } else {
1000 DRM_ERROR 1010 DRM_ERROR
1001 ("Invalid / Unimplemented DMA HEADER command. 0x%x\n", 1011 ("Invalid / Unimplemented DMA HEADER command. 0x%x\n",
1002 cmd); 1012 cmd);