aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--arch/arm/mach-bcmring/core.c118
1 files changed, 8 insertions, 110 deletions
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index 2cb39890256e..43eadbcc29ed 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -28,8 +28,6 @@
28#include <linux/sysdev.h> 28#include <linux/sysdev.h>
29#include <linux/interrupt.h> 29#include <linux/interrupt.h>
30#include <linux/amba/bus.h> 30#include <linux/amba/bus.h>
31#include <linux/clocksource.h>
32#include <linux/clockchips.h>
33#include <linux/clkdev.h> 31#include <linux/clkdev.h>
34 32
35#include <mach/csp/mm_addr.h> 33#include <mach/csp/mm_addr.h>
@@ -113,8 +111,8 @@ static struct clk dummy_apb_pclk = {
113#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000) 111#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
114#endif 112#endif
115 113
116static struct clk sp804_timer1_clk = { 114static struct clk sp804_timer012_clk = {
117 .name = "sp804-timer-1", 115 .name = "sp804-timer-0,1,2",
118 .type = CLK_TYPE_PRIMARY, 116 .type = CLK_TYPE_PRIMARY,
119 .mode = CLK_MODE_XTAL, 117 .mode = CLK_MODE_XTAL,
120 .rate_hz = TIMER1_FREQUENCY_MHZ * 1000000, 118 .rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
@@ -137,10 +135,14 @@ static struct clk_lookup lookups[] = {
137 }, { /* UART1 */ 135 }, { /* UART1 */
138 .dev_id = "uartb", 136 .dev_id = "uartb",
139 .clk = &uart_clk, 137 .clk = &uart_clk,
138 }, { /* SP804 timer 0 */
139 .dev_id = "sp804",
140 .con_id = "timer0",
141 .clk = &sp804_timer012_clk,
140 }, { /* SP804 timer 1 */ 142 }, { /* SP804 timer 1 */
141 .dev_id = "sp804", 143 .dev_id = "sp804",
142 .con_id = "timer1", 144 .con_id = "timer1",
143 .clk = &sp804_timer1_clk, 145 .clk = &sp804_timer012_clk,
144 }, { /* SP804 timer 3 */ 146 }, { /* SP804 timer 3 */
145 .dev_id = "sp804", 147 .dev_id = "sp804",
146 .con_id = "timer3", 148 .con_id = "timer3",
@@ -203,100 +205,6 @@ void __init bcmring_amba_init(void)
203#define TIMER2_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x40)) 205#define TIMER2_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x40))
204#define TIMER3_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x60)) 206#define TIMER3_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
205 207
206#define TICKS_PER_uSEC TIMER0_FREQUENCY_MHZ
207
208/*
209 * These are useconds NOT ticks.
210 *
211 */
212#define mSEC_1 1000
213#define mSEC_10 (mSEC_1 * 10)
214
215/*
216 * How long is the timer interval?
217 */
218#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
219#if TIMER_INTERVAL >= 0x100000
220#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
221#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
222#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
223#elif TIMER_INTERVAL >= 0x10000
224#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
225#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
226#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
227#else
228#define TIMER_RELOAD (TIMER_INTERVAL)
229#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
230#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
231#endif
232
233static void timer_set_mode(enum clock_event_mode mode,
234 struct clock_event_device *clk)
235{
236 unsigned long ctrl;
237
238 switch (mode) {
239 case CLOCK_EVT_MODE_PERIODIC:
240 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
241
242 ctrl = TIMER_CTRL_PERIODIC;
243 ctrl |=
244 TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE |
245 TIMER_CTRL_ENABLE;
246 break;
247 case CLOCK_EVT_MODE_ONESHOT:
248 /* period set, and timer enabled in 'next_event' hook */
249 ctrl = TIMER_CTRL_ONESHOT;
250 ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE;
251 break;
252 case CLOCK_EVT_MODE_UNUSED:
253 case CLOCK_EVT_MODE_SHUTDOWN:
254 default:
255 ctrl = 0;
256 }
257
258 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
259}
260
261static int timer_set_next_event(unsigned long evt,
262 struct clock_event_device *unused)
263{
264 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
265
266 writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
267 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
268
269 return 0;
270}
271
272static struct clock_event_device timer0_clockevent = {
273 .name = "timer0",
274 .shift = 32,
275 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
276 .set_mode = timer_set_mode,
277 .set_next_event = timer_set_next_event,
278};
279
280/*
281 * IRQ handler for the timer
282 */
283static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id)
284{
285 struct clock_event_device *evt = &timer0_clockevent;
286
287 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
288
289 evt->event_handler(evt);
290
291 return IRQ_HANDLED;
292}
293
294static struct irqaction bcmring_timer_irq = {
295 .name = "bcmring Timer Tick",
296 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
297 .handler = bcmring_timer_interrupt,
298};
299
300static int __init bcmring_clocksource_init(void) 208static int __init bcmring_clocksource_init(void)
301{ 209{
302 /* setup timer1 as free-running clocksource */ 210 /* setup timer1 as free-running clocksource */
@@ -325,19 +233,9 @@ void __init bcmring_init_timer(void)
325 /* 233 /*
326 * Make irqs happen for the system timer 234 * Make irqs happen for the system timer
327 */ 235 */
328 setup_irq(IRQ_TIMER0, &bcmring_timer_irq);
329
330 bcmring_clocksource_init(); 236 bcmring_clocksource_init();
331 237
332 timer0_clockevent.mult = 238 sp804_clockevents_register(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
333 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
334 timer0_clockevent.max_delta_ns =
335 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
336 timer0_clockevent.min_delta_ns =
337 clockevent_delta2ns(0xf, &timer0_clockevent);
338
339 timer0_clockevent.cpumask = cpumask_of(0);
340 clockevents_register_device(&timer0_clockevent);
341} 239}
342 240
343struct sys_timer bcmring_timer = { 241struct sys_timer bcmring_timer = {