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-rw-r--r--MAINTAINERS4
-rw-r--r--arch/blackfin/Makefile5
-rw-r--r--arch/blackfin/configs/BF527-EZKIT_defconfig18
-rw-r--r--arch/blackfin/configs/BF533-EZKIT_defconfig6
-rw-r--r--arch/blackfin/configs/BF533-STAMP_defconfig6
-rw-r--r--arch/blackfin/configs/BF537-STAMP_defconfig6
-rw-r--r--arch/blackfin/configs/BF548-EZKIT_defconfig2
-rw-r--r--arch/blackfin/configs/BF561-EZKIT_defconfig1
-rw-r--r--arch/blackfin/kernel/bfin_dma_5xx.c15
-rw-r--r--arch/blackfin/kernel/gptimers.c8
-rw-r--r--arch/blackfin/kernel/setup.c5
-rw-r--r--arch/blackfin/kernel/vmlinux.lds.S34
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c60
-rw-r--r--arch/blackfin/mach-bf533/boards/ezkit.c21
-rw-r--r--arch/blackfin/mach-bf533/boards/stamp.c43
-rw-r--r--arch/blackfin/mach-bf537/boards/generic_board.c18
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c45
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c25
-rw-r--r--arch/blackfin/mach-bf548/dma.c2
-rw-r--r--arch/blackfin/mach-bf548/head.S9
-rw-r--r--arch/blackfin/mach-bf561/boards/ezkit.c16
-rw-r--r--arch/blackfin/mach-common/dpmc.S137
-rw-r--r--arch/blackfin/mach-common/ints-priority.c174
-rw-r--r--arch/blackfin/mm/init.c4
-rw-r--r--drivers/serial/Kconfig6
-rw-r--r--drivers/serial/bfin_5xx.c281
-rw-r--r--include/asm-blackfin/gptimers.h7
-rw-r--r--include/asm-blackfin/irq.h2
-rw-r--r--include/asm-blackfin/mach-bf527/bfin_serial_5xx.h22
-rw-r--r--include/asm-blackfin/mach-bf533/bfin_serial_5xx.h24
-rw-r--r--include/asm-blackfin/mach-bf537/bfin_serial_5xx.h22
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_serial_5xx.h7
-rw-r--r--include/asm-blackfin/mach-bf561/bfin_serial_5xx.h24
-rw-r--r--include/asm-blackfin/mach-bf561/blackfin.h3
-rw-r--r--include/asm-blackfin/mach-bf561/cdefBF561.h2
35 files changed, 504 insertions, 560 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 799058754236..fed09b547336 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -767,14 +767,14 @@ S: Maintained
767 767
768BLACKFIN ARCHITECTURE 768BLACKFIN ARCHITECTURE
769P: Bryan Wu 769P: Bryan Wu
770M: bryan.wu@analog.com 770M: cooloney@kernel.org
771L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only) 771L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only)
772W: http://blackfin.uclinux.org 772W: http://blackfin.uclinux.org
773S: Supported 773S: Supported
774 774
775BLACKFIN EMAC DRIVER 775BLACKFIN EMAC DRIVER
776P: Bryan Wu 776P: Bryan Wu
777M: bryan.wu@analog.com 777M: cooloney@kernel.org
778L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only) 778L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only)
779W: http://blackfin.uclinux.org 779W: http://blackfin.uclinux.org
780S: Supported 780S: Supported
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index fe254f886a6e..75eba2ca7881 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -98,8 +98,11 @@ drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/
98# them changed. We use .mach to indicate when they were updated 98# them changed. We use .mach to indicate when they were updated
99# last, otherwise make uses the target directory mtime. 99# last, otherwise make uses the target directory mtime.
100 100
101 show_mach_symlink = :
102 quiet_show_mach_symlink = echo ' SYMLINK include/asm-$(ARCH)/mach-$(MACHINE) -> include/asm-$(ARCH)/mach'
103silent_show_mach_symlink = :
101include/asm-blackfin/.mach: $(wildcard include/config/arch/*.h) include/config/auto.conf 104include/asm-blackfin/.mach: $(wildcard include/config/arch/*.h) include/config/auto.conf
102 @echo ' SYMLINK include/asm-$(ARCH)/mach-$(MACHINE) -> include/asm-$(ARCH)/mach' 105 @$($(quiet)show_mach_symlink)
103ifneq ($(KBUILD_SRC),) 106ifneq ($(KBUILD_SRC),)
104 $(Q)mkdir -p include/asm-$(ARCH) 107 $(Q)mkdir -p include/asm-$(ARCH)
105 $(Q)ln -fsn $(srctree)/include/asm-$(ARCH)/mach-$(MACHINE) include/asm-$(ARCH)/mach 108 $(Q)ln -fsn $(srctree)/include/asm-$(ARCH)/mach-$(MACHINE) include/asm-$(ARCH)/mach
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index d59ee1530bd4..ae320dcfedef 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -1,7 +1,6 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22.14 3# Linux kernel version: 2.6.22.16
4# Thu Nov 29 17:32:47 2007
5# 4#
6# CONFIG_MMU is not set 5# CONFIG_MMU is not set
7# CONFIG_FPU is not set 6# CONFIG_FPU is not set
@@ -116,7 +115,10 @@ CONFIG_PREEMPT_VOLUNTARY=y
116# Processor and Board Settings 115# Processor and Board Settings
117# 116#
118# CONFIG_BF522 is not set 117# CONFIG_BF522 is not set
118# CONFIG_BF523 is not set
119# CONFIG_BF524 is not set
119# CONFIG_BF525 is not set 120# CONFIG_BF525 is not set
121# CONFIG_BF526 is not set
120CONFIG_BF527=y 122CONFIG_BF527=y
121# CONFIG_BF531 is not set 123# CONFIG_BF531 is not set
122# CONFIG_BF532 is not set 124# CONFIG_BF532 is not set
@@ -306,6 +308,7 @@ CONFIG_BFIN_DCACHE=y
306# CONFIG_BFIN_WB is not set 308# CONFIG_BFIN_WB is not set
307CONFIG_BFIN_WT=y 309CONFIG_BFIN_WT=y
308CONFIG_L1_MAX_PIECE=16 310CONFIG_L1_MAX_PIECE=16
311# CONFIG_MPU is not set
309 312
310# 313#
311# Asynchonous Memory Configuration 314# Asynchonous Memory Configuration
@@ -354,6 +357,7 @@ CONFIG_BINFMT_ZFLAT=y
354# Power management options 357# Power management options
355# 358#
356# CONFIG_PM is not set 359# CONFIG_PM is not set
360# CONFIG_PM_WAKEUP_BY_GPIO is not set
357 361
358# 362#
359# Networking 363# Networking
@@ -496,7 +500,6 @@ CONFIG_MTD_CFI_I2=y
496# CONFIG_MTD_CFI_INTELEXT is not set 500# CONFIG_MTD_CFI_INTELEXT is not set
497# CONFIG_MTD_CFI_AMDSTD is not set 501# CONFIG_MTD_CFI_AMDSTD is not set
498# CONFIG_MTD_CFI_STAA is not set 502# CONFIG_MTD_CFI_STAA is not set
499CONFIG_MTD_MW320D=m
500CONFIG_MTD_RAM=y 503CONFIG_MTD_RAM=y
501CONFIG_MTD_ROM=m 504CONFIG_MTD_ROM=m
502# CONFIG_MTD_ABSENT is not set 505# CONFIG_MTD_ABSENT is not set
@@ -506,9 +509,6 @@ CONFIG_MTD_ROM=m
506# 509#
507CONFIG_MTD_COMPLEX_MAPPINGS=y 510CONFIG_MTD_COMPLEX_MAPPINGS=y
508# CONFIG_MTD_PHYSMAP is not set 511# CONFIG_MTD_PHYSMAP is not set
509CONFIG_MTD_BF5xx=m
510CONFIG_BFIN_FLASH_SIZE=0x400000
511CONFIG_EBIU_FLASH_BASE=0x20000000
512# CONFIG_MTD_UCLINUX is not set 512# CONFIG_MTD_UCLINUX is not set
513# CONFIG_MTD_PLATRAM is not set 513# CONFIG_MTD_PLATRAM is not set
514 514
@@ -684,7 +684,6 @@ CONFIG_INPUT_MISC=y
684# CONFIG_INPUT_POWERMATE is not set 684# CONFIG_INPUT_POWERMATE is not set
685# CONFIG_INPUT_YEALINK is not set 685# CONFIG_INPUT_YEALINK is not set
686# CONFIG_INPUT_UINPUT is not set 686# CONFIG_INPUT_UINPUT is not set
687# CONFIG_BF53X_PFBUTTONS is not set
688# CONFIG_TWI_KEYPAD is not set 687# CONFIG_TWI_KEYPAD is not set
689 688
690# 689#
@@ -702,12 +701,12 @@ CONFIG_INPUT_MISC=y
702# CONFIG_BF5xx_PPIFCD is not set 701# CONFIG_BF5xx_PPIFCD is not set
703# CONFIG_BFIN_SIMPLE_TIMER is not set 702# CONFIG_BFIN_SIMPLE_TIMER is not set
704# CONFIG_BF5xx_PPI is not set 703# CONFIG_BF5xx_PPI is not set
704CONFIG_BFIN_OTP=y
705# CONFIG_BFIN_OTP_WRITE_ENABLE is not set
705# CONFIG_BFIN_SPORT is not set 706# CONFIG_BFIN_SPORT is not set
706# CONFIG_BFIN_TIMER_LATENCY is not set 707# CONFIG_BFIN_TIMER_LATENCY is not set
707# CONFIG_TWI_LCD is not set 708# CONFIG_TWI_LCD is not set
708# CONFIG_AD5304 is not set 709# CONFIG_AD5304 is not set
709# CONFIG_BF5xx_TEA5764 is not set
710# CONFIG_BF5xx_FBDMA is not set
711# CONFIG_VT is not set 710# CONFIG_VT is not set
712# CONFIG_SERIAL_NONSTANDARD is not set 711# CONFIG_SERIAL_NONSTANDARD is not set
713 712
@@ -772,7 +771,6 @@ CONFIG_I2C_CHARDEV=m
772# 771#
773# I2C Hardware Bus support 772# I2C Hardware Bus support
774# 773#
775# CONFIG_I2C_BLACKFIN_GPIO is not set
776CONFIG_I2C_BLACKFIN_TWI=m 774CONFIG_I2C_BLACKFIN_TWI=m
777CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 775CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
778# CONFIG_I2C_GPIO is not set 776# CONFIG_I2C_GPIO is not set
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
index 811711f59a25..9621caa60b5f 100644
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@@ -322,10 +322,9 @@ CONFIG_PM=y
322# CONFIG_PM_LEGACY is not set 322# CONFIG_PM_LEGACY is not set
323# CONFIG_PM_DEBUG is not set 323# CONFIG_PM_DEBUG is not set
324# CONFIG_PM_SYSFS_DEPRECATED is not set 324# CONFIG_PM_SYSFS_DEPRECATED is not set
325CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR=y 325CONFIG_PM_BFIN_SLEEP_DEEPER=y
326# CONFIG_PM_BFIN_SLEEP is not set
326# CONFIG_PM_WAKEUP_BY_GPIO is not set 327# CONFIG_PM_WAKEUP_BY_GPIO is not set
327# CONFIG_PM_WAKEUP_GPIO_API is not set
328CONFIG_PM_WAKEUP_SIC_IWR=0x80
329 328
330# 329#
331# CPU Frequency scaling 330# CPU Frequency scaling
@@ -697,7 +696,6 @@ CONFIG_SERIAL_BFIN_DMA=y
697# CONFIG_SERIAL_BFIN_PIO is not set 696# CONFIG_SERIAL_BFIN_PIO is not set
698CONFIG_SERIAL_BFIN_UART0=y 697CONFIG_SERIAL_BFIN_UART0=y
699# CONFIG_BFIN_UART0_CTSRTS is not set 698# CONFIG_BFIN_UART0_CTSRTS is not set
700# CONFIG_SERIAL_BFIN_UART1 is not set
701CONFIG_SERIAL_CORE=y 699CONFIG_SERIAL_CORE=y
702CONFIG_SERIAL_CORE_CONSOLE=y 700CONFIG_SERIAL_CORE_CONSOLE=y
703# CONFIG_SERIAL_BFIN_SPORT is not set 701# CONFIG_SERIAL_BFIN_SPORT is not set
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index 198f4123af4b..b51e76ce7f4f 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -323,10 +323,9 @@ CONFIG_PM=y
323# CONFIG_PM_LEGACY is not set 323# CONFIG_PM_LEGACY is not set
324# CONFIG_PM_DEBUG is not set 324# CONFIG_PM_DEBUG is not set
325# CONFIG_PM_SYSFS_DEPRECATED is not set 325# CONFIG_PM_SYSFS_DEPRECATED is not set
326CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR=y 326CONFIG_PM_BFIN_SLEEP_DEEPER=y
327# CONFIG_PM_BFIN_SLEEP is not set
327# CONFIG_PM_WAKEUP_BY_GPIO is not set 328# CONFIG_PM_WAKEUP_BY_GPIO is not set
328# CONFIG_PM_WAKEUP_GPIO_API is not set
329CONFIG_PM_WAKEUP_SIC_IWR=0x80
330 329
331# 330#
332# CPU Frequency scaling 331# CPU Frequency scaling
@@ -714,7 +713,6 @@ CONFIG_SERIAL_BFIN_DMA=y
714# CONFIG_SERIAL_BFIN_PIO is not set 713# CONFIG_SERIAL_BFIN_PIO is not set
715CONFIG_SERIAL_BFIN_UART0=y 714CONFIG_SERIAL_BFIN_UART0=y
716# CONFIG_BFIN_UART0_CTSRTS is not set 715# CONFIG_BFIN_UART0_CTSRTS is not set
717# CONFIG_SERIAL_BFIN_UART1 is not set
718CONFIG_SERIAL_CORE=y 716CONFIG_SERIAL_CORE=y
719CONFIG_SERIAL_CORE_CONSOLE=y 717CONFIG_SERIAL_CORE_CONSOLE=y
720# CONFIG_SERIAL_BFIN_SPORT is not set 718# CONFIG_SERIAL_BFIN_SPORT is not set
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index b37ccc681e7a..d45fa535dad7 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -330,10 +330,9 @@ CONFIG_PM=y
330# CONFIG_PM_LEGACY is not set 330# CONFIG_PM_LEGACY is not set
331# CONFIG_PM_DEBUG is not set 331# CONFIG_PM_DEBUG is not set
332# CONFIG_PM_SYSFS_DEPRECATED is not set 332# CONFIG_PM_SYSFS_DEPRECATED is not set
333CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR=y 333CONFIG_PM_BFIN_SLEEP_DEEPER=y
334# CONFIG_PM_BFIN_SLEEP is not set
334# CONFIG_PM_WAKEUP_BY_GPIO is not set 335# CONFIG_PM_WAKEUP_BY_GPIO is not set
335# CONFIG_PM_WAKEUP_GPIO_API is not set
336CONFIG_PM_WAKEUP_SIC_IWR=0x8
337 336
338# 337#
339# CPU Frequency scaling 338# CPU Frequency scaling
@@ -1013,6 +1012,7 @@ CONFIG_SND_BFIN_AD73311_SE=4
1013CONFIG_SND_SOC_AC97_BUS=y 1012CONFIG_SND_SOC_AC97_BUS=y
1014CONFIG_SND_SOC=m 1013CONFIG_SND_SOC=m
1015CONFIG_SND_BF5XX_SOC=m 1014CONFIG_SND_BF5XX_SOC=m
1015CONFIG_SND_MMAP_SUPPORT=y
1016CONFIG_SND_BF5XX_SOC_AC97=m 1016CONFIG_SND_BF5XX_SOC_AC97=m
1017# CONFIG_SND_BF5XX_SOC_WM8750 is not set 1017# CONFIG_SND_BF5XX_SOC_WM8750 is not set
1018# CONFIG_SND_BF5XX_SOC_WM8731 is not set 1018# CONFIG_SND_BF5XX_SOC_WM8731 is not set
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
index fd702161ef59..c9707f7665ad 100644
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -396,6 +396,7 @@ CONFIG_BINFMT_ZFLAT=y
396# Power management options 396# Power management options
397# 397#
398# CONFIG_PM is not set 398# CONFIG_PM is not set
399# CONFIG_PM_WAKEUP_BY_GPIO is not set
399 400
400# 401#
401# CPU Frequency scaling 402# CPU Frequency scaling
@@ -1075,6 +1076,7 @@ CONFIG_SND_VERBOSE_PROCFS=y
1075CONFIG_SND_SOC_AC97_BUS=y 1076CONFIG_SND_SOC_AC97_BUS=y
1076CONFIG_SND_SOC=y 1077CONFIG_SND_SOC=y
1077CONFIG_SND_BF5XX_SOC=y 1078CONFIG_SND_BF5XX_SOC=y
1079CONFIG_SND_MMAP_SUPPORT=y
1078CONFIG_SND_BF5XX_SOC_AC97=y 1080CONFIG_SND_BF5XX_SOC_AC97=y
1079CONFIG_SND_BF5XX_SOC_BF548_EZKIT=y 1081CONFIG_SND_BF5XX_SOC_BF548_EZKIT=y
1080# CONFIG_SND_BF5XX_SOC_WM8750 is not set 1082# CONFIG_SND_BF5XX_SOC_WM8750 is not set
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index 8546994939fb..4d8a63331309 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -367,6 +367,7 @@ CONFIG_BINFMT_ZFLAT=y
367# Power management options 367# Power management options
368# 368#
369# CONFIG_PM is not set 369# CONFIG_PM is not set
370# CONFIG_PM_WAKEUP_BY_GPIO is not set
370 371
371# 372#
372# Networking 373# Networking
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index 5453bc3664fc..8fd5d22cec34 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -105,13 +105,14 @@ int request_dma(unsigned int channel, char *device_id)
105 mutex_unlock(&(dma_ch[channel].dmalock)); 105 mutex_unlock(&(dma_ch[channel].dmalock));
106 106
107#ifdef CONFIG_BF54x 107#ifdef CONFIG_BF54x
108 if (channel >= CH_UART2_RX && channel <= CH_UART3_TX && 108 if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) {
109 strncmp(device_id, "BFIN_UART", 9) == 0) 109 if (strncmp(device_id, "BFIN_UART", 9) == 0)
110 dma_ch[channel].regs->peripheral_map |= 110 dma_ch[channel].regs->peripheral_map |=
111 (channel - CH_UART2_RX + 0xC); 111 (channel - CH_UART2_RX + 0xC);
112 else 112 else
113 dma_ch[channel].regs->peripheral_map |= 113 dma_ch[channel].regs->peripheral_map |=
114 (channel - CH_UART2_RX + 0x6); 114 (channel - CH_UART2_RX + 0x6);
115 }
115#endif 116#endif
116 117
117 dma_ch[channel].device_id = device_id; 118 dma_ch[channel].device_id = device_id;
diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c
index 5cf4bdb1df3b..1904d8b53328 100644
--- a/arch/blackfin/kernel/gptimers.c
+++ b/arch/blackfin/kernel/gptimers.c
@@ -1,9 +1,9 @@
1/* 1/*
2 * bfin_gptimers.c - derived from bf53x_timers.c 2 * gptimers.c - Blackfin General Purpose Timer core API
3 * Driver for General Purpose Timer functions on the Blackfin processor
4 * 3 *
5 * Copyright (C) 2005 John DeHority 4 * Copyright (c) 2005-2008 Analog Devices Inc.
6 * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de) 5 * Copyright (C) 2005 John DeHority
6 * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de)
7 * 7 *
8 * Licensed under the GPLv2. 8 * Licensed under the GPLv2.
9 */ 9 */
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 8229b1090eb9..2255c289a714 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -32,6 +32,7 @@
32static DEFINE_PER_CPU(struct cpu, cpu_devices); 32static DEFINE_PER_CPU(struct cpu, cpu_devices);
33 33
34u16 _bfin_swrst; 34u16 _bfin_swrst;
35EXPORT_SYMBOL(_bfin_swrst);
35 36
36unsigned long memory_start, memory_end, physical_mem_end; 37unsigned long memory_start, memory_end, physical_mem_end;
37unsigned long reserved_mem_dcache_on; 38unsigned long reserved_mem_dcache_on;
@@ -514,6 +515,7 @@ static __init void memory_setup(void)
514 printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20); 515 printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
515 516
516 printk(KERN_INFO "Memory map:\n" 517 printk(KERN_INFO "Memory map:\n"
518 KERN_INFO " fixedcode = 0x%p-0x%p\n"
517 KERN_INFO " text = 0x%p-0x%p\n" 519 KERN_INFO " text = 0x%p-0x%p\n"
518 KERN_INFO " rodata = 0x%p-0x%p\n" 520 KERN_INFO " rodata = 0x%p-0x%p\n"
519 KERN_INFO " bss = 0x%p-0x%p\n" 521 KERN_INFO " bss = 0x%p-0x%p\n"
@@ -527,7 +529,8 @@ static __init void memory_setup(void)
527#if DMA_UNCACHED_REGION > 0 529#if DMA_UNCACHED_REGION > 0
528 KERN_INFO " DMA Zone = 0x%p-0x%p\n" 530 KERN_INFO " DMA Zone = 0x%p-0x%p\n"
529#endif 531#endif
530 , _stext, _etext, 532 , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END,
533 _stext, _etext,
531 __start_rodata, __end_rodata, 534 __start_rodata, __end_rodata,
532 __bss_start, __bss_stop, 535 __bss_start, __bss_stop,
533 _sdata, _edata, 536 _sdata, _edata,
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index aed832540b3b..cb01a9de2680 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -147,44 +147,64 @@ SECTIONS
147 147
148 __l1_lma_start = .; 148 __l1_lma_start = .;
149 149
150#if L1_CODE_LENGTH
151# define LDS_L1_CODE *(.l1.text)
152#else
153# define LDS_L1_CODE
154#endif
150 .text_l1 L1_CODE_START : AT(LOADADDR(.init.ramfs) + SIZEOF(.init.ramfs)) 155 .text_l1 L1_CODE_START : AT(LOADADDR(.init.ramfs) + SIZEOF(.init.ramfs))
151 { 156 {
152 . = ALIGN(4); 157 . = ALIGN(4);
153 __stext_l1 = .; 158 __stext_l1 = .;
154 *(.l1.text) 159 LDS_L1_CODE
155
156 . = ALIGN(4); 160 . = ALIGN(4);
157 __etext_l1 = .; 161 __etext_l1 = .;
158 } 162 }
159 163
164#if L1_DATA_A_LENGTH
165# define LDS_L1_A_DATA *(.l1.data)
166# define LDS_L1_A_BSS *(.l1.bss)
167# define LDS_L1_A_CACHE *(.data_l1.cacheline_aligned)
168#else
169# define LDS_L1_A_DATA
170# define LDS_L1_A_BSS
171# define LDS_L1_A_CACHE
172#endif
160 .data_l1 L1_DATA_A_START : AT(LOADADDR(.text_l1) + SIZEOF(.text_l1)) 173 .data_l1 L1_DATA_A_START : AT(LOADADDR(.text_l1) + SIZEOF(.text_l1))
161 { 174 {
162 . = ALIGN(4); 175 . = ALIGN(4);
163 __sdata_l1 = .; 176 __sdata_l1 = .;
164 *(.l1.data) 177 LDS_L1_A_DATA
165 __edata_l1 = .; 178 __edata_l1 = .;
166 179
167 . = ALIGN(4); 180 . = ALIGN(4);
168 __sbss_l1 = .; 181 __sbss_l1 = .;
169 *(.l1.bss) 182 LDS_L1_A_BSS
170 183
171 . = ALIGN(32); 184 . = ALIGN(32);
172 *(.data_l1.cacheline_aligned) 185 LDS_L1_A_CACHE
173 186
174 . = ALIGN(4); 187 . = ALIGN(4);
175 __ebss_l1 = .; 188 __ebss_l1 = .;
176 } 189 }
177 190
191#if L1_DATA_B_LENGTH
192# define LDS_L1_B_DATA *(.l1.data.B)
193# define LDS_L1_B_BSS *(.l1.bss.B)
194#else
195# define LDS_L1_B_DATA
196# define LDS_L1_B_BSS
197#endif
178 .data_b_l1 L1_DATA_B_START : AT(LOADADDR(.data_l1) + SIZEOF(.data_l1)) 198 .data_b_l1 L1_DATA_B_START : AT(LOADADDR(.data_l1) + SIZEOF(.data_l1))
179 { 199 {
180 . = ALIGN(4); 200 . = ALIGN(4);
181 __sdata_b_l1 = .; 201 __sdata_b_l1 = .;
182 *(.l1.data.B) 202 LDS_L1_B_DATA
183 __edata_b_l1 = .; 203 __edata_b_l1 = .;
184 204
185 . = ALIGN(4); 205 . = ALIGN(4);
186 __sbss_b_l1 = .; 206 __sbss_b_l1 = .;
187 *(.l1.bss.B) 207 LDS_L1_B_BSS
188 208
189 . = ALIGN(4); 209 . = ALIGN(4);
190 __ebss_b_l1 = .; 210 __ebss_b_l1 = .;
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 337515fba612..cf4bc0d83355 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -180,8 +180,8 @@ static struct mtd_partition partition_info[] = {
180 }, 180 },
181 { 181 {
182 .name = "File System", 182 .name = "File System",
183 .offset = 4 * SIZE_1M, 183 .offset = MTDPART_OFS_APPEND,
184 .size = (256 - 4) * SIZE_1M, 184 .size = MTDPART_SIZ_FULL,
185 }, 185 },
186}; 186};
187 187
@@ -422,11 +422,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
422 }, { 422 }, {
423 .name = "kernel", 423 .name = "kernel",
424 .size = 0xe0000, 424 .size = 0xe0000,
425 .offset = 0x20000 425 .offset = MTDPART_OFS_APPEND,
426 }, { 426 }, {
427 .name = "file system", 427 .name = "file system",
428 .size = 0x700000, 428 .size = MTDPART_SIZ_FULL,
429 .offset = 0x00100000, 429 .offset = MTDPART_OFS_APPEND,
430 } 430 }
431}; 431};
432 432
@@ -484,13 +484,6 @@ static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
484}; 484};
485#endif 485#endif
486 486
487#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
488static struct bfin5xx_spi_chip ad5304_chip_info = {
489 .enable_dma = 0,
490 .bits_per_word = 16,
491};
492#endif
493
494#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 487#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
495static struct bfin5xx_spi_chip spi_ad7877_chip_info = { 488static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
496 .enable_dma = 0, 489 .enable_dma = 0,
@@ -611,17 +604,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
611 .mode = SPI_MODE_3, 604 .mode = SPI_MODE_3,
612 }, 605 },
613#endif 606#endif
614#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
615 {
616 .modalias = "ad5304_spi",
617 .max_speed_hz = 1250000, /* max spi clock (SCK) speed in HZ */
618 .bus_num = 0,
619 .chip_select = 2,
620 .platform_data = NULL,
621 .controller_data = &ad5304_chip_info,
622 .mode = SPI_MODE_2,
623 },
624#endif
625#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 607#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
626 { 608 {
627 .modalias = "ad7877", 609 .modalias = "ad7877",
@@ -818,6 +800,19 @@ static struct platform_device bfin_device_gpiokeys = {
818}; 800};
819#endif 801#endif
820 802
803static struct resource bfin_gpios_resources = {
804 .start = 0,
805 .end = MAX_BLACKFIN_GPIOS - 1,
806 .flags = IORESOURCE_IRQ,
807};
808
809static struct platform_device bfin_gpios_device = {
810 .name = "simple-gpio",
811 .id = -1,
812 .num_resources = 1,
813 .resource = &bfin_gpios_resources,
814};
815
821static struct platform_device *stamp_devices[] __initdata = { 816static struct platform_device *stamp_devices[] __initdata = {
822#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) 817#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
823 &bf5xx_nand_device, 818 &bf5xx_nand_device,
@@ -895,6 +890,8 @@ static struct platform_device *stamp_devices[] __initdata = {
895#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) 890#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
896 &bfin_device_gpiokeys, 891 &bfin_device_gpiokeys,
897#endif 892#endif
893
894 &bfin_gpios_device,
898}; 895};
899 896
900static int __init stamp_init(void) 897static int __init stamp_init(void)
@@ -921,13 +918,18 @@ void native_machine_restart(char *cmd)
921 bfin_gpio_reset_spi0_ssel1(); 918 bfin_gpio_reset_spi0_ssel1();
922} 919}
923 920
924/*
925 * Currently the MAC address is saved in Flash by U-Boot
926 */
927#define FLASH_MAC 0x203f0000
928void bfin_get_ether_addr(char *addr) 921void bfin_get_ether_addr(char *addr)
929{ 922{
930 *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC); 923 /* the MAC is stored in OTP memory page 0xDF */
931 *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4); 924 u32 ret;
925 u64 otp_mac;
926 u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
927
928 ret = otp_read(0xDF, 0x00, &otp_mac);
929 if (!(ret & 0x1)) {
930 char *otp_mac_p = (char *)&otp_mac;
931 for (ret = 0; ret < 6; ++ret)
932 addr[ret] = otp_mac_p[5 - ret];
933 }
932} 934}
933EXPORT_SYMBOL(bfin_get_ether_addr); 935EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index 2b09aa39f565..241b5a20a36a 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -99,11 +99,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
99 }, { 99 }, {
100 .name = "kernel", 100 .name = "kernel",
101 .size = 0xe0000, 101 .size = 0xe0000,
102 .offset = 0x20000 102 .offset = MTDPART_OFS_APPEND,
103 }, { 103 }, {
104 .name = "file system", 104 .name = "file system",
105 .size = 0x700000, 105 .size = MTDPART_SIZ_FULL,
106 .offset = 0x00100000, 106 .offset = MTDPART_OFS_APPEND,
107 } 107 }
108}; 108};
109 109
@@ -298,6 +298,19 @@ static struct platform_device bfin_device_gpiokeys = {
298}; 298};
299#endif 299#endif
300 300
301static struct resource bfin_gpios_resources = {
302 .start = 0,
303 .end = MAX_BLACKFIN_GPIOS - 1,
304 .flags = IORESOURCE_IRQ,
305};
306
307static struct platform_device bfin_gpios_device = {
308 .name = "simple-gpio",
309 .id = -1,
310 .num_resources = 1,
311 .resource = &bfin_gpios_resources,
312};
313
301#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) 314#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
302#include <linux/i2c-gpio.h> 315#include <linux/i2c-gpio.h>
303 316
@@ -350,6 +363,8 @@ static struct platform_device *ezkit_devices[] __initdata = {
350#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) 363#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
351 &i2c_gpio_device, 364 &i2c_gpio_device,
352#endif 365#endif
366
367 &bfin_gpios_device,
353}; 368};
354 369
355static int __init ezkit_init(void) 370static int __init ezkit_init(void)
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index a645f6fd091b..b2ac4816ae62 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -112,7 +112,7 @@ static struct platform_device net2272_bfin_device = {
112static struct mtd_partition stamp_partitions[] = { 112static struct mtd_partition stamp_partitions[] = {
113 { 113 {
114 .name = "Bootloader", 114 .name = "Bootloader",
115 .size = 0x20000, 115 .size = 0x40000,
116 .offset = 0, 116 .offset = 0,
117 }, { 117 }, {
118 .name = "Kernel", 118 .name = "Kernel",
@@ -160,17 +160,17 @@ static struct platform_device stamp_flash_device = {
160static struct mtd_partition bfin_spi_flash_partitions[] = { 160static struct mtd_partition bfin_spi_flash_partitions[] = {
161 { 161 {
162 .name = "bootloader", 162 .name = "bootloader",
163 .size = 0x00020000, 163 .size = 0x00040000,
164 .offset = 0, 164 .offset = 0,
165 .mask_flags = MTD_CAP_ROM 165 .mask_flags = MTD_CAP_ROM
166 }, { 166 }, {
167 .name = "kernel", 167 .name = "kernel",
168 .size = 0xe0000, 168 .size = 0xe0000,
169 .offset = 0x20000 169 .offset = MTDPART_OFS_APPEND,
170 }, { 170 }, {
171 .name = "file system", 171 .name = "file system",
172 .size = 0x700000, 172 .size = MTDPART_SIZ_FULL,
173 .offset = 0x00100000, 173 .offset = MTDPART_OFS_APPEND,
174 } 174 }
175}; 175};
176 176
@@ -212,13 +212,6 @@ static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
212}; 212};
213#endif 213#endif
214 214
215#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
216static struct bfin5xx_spi_chip ad5304_chip_info = {
217 .enable_dma = 0,
218 .bits_per_word = 16,
219};
220#endif
221
222#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 215#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
223static struct bfin5xx_spi_chip spi_mmc_chip_info = { 216static struct bfin5xx_spi_chip spi_mmc_chip_info = {
224 .enable_dma = 1, 217 .enable_dma = 1,
@@ -308,17 +301,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
308 }, 301 },
309#endif 302#endif
310 303
311#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
312 {
313 .modalias = "ad5304_spi",
314 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
315 .bus_num = 0,
316 .chip_select = 2,
317 .platform_data = NULL,
318 .controller_data = &ad5304_chip_info,
319 .mode = SPI_MODE_2,
320 },
321#endif
322#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) 304#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
323 { 305 {
324 .modalias = "spidev", 306 .modalias = "spidev",
@@ -457,6 +439,19 @@ static struct platform_device bfin_device_gpiokeys = {
457}; 439};
458#endif 440#endif
459 441
442static struct resource bfin_gpios_resources = {
443 .start = 0,
444 .end = MAX_BLACKFIN_GPIOS - 1,
445 .flags = IORESOURCE_IRQ,
446};
447
448static struct platform_device bfin_gpios_device = {
449 .name = "simple-gpio",
450 .id = -1,
451 .num_resources = 1,
452 .resource = &bfin_gpios_resources,
453};
454
460#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) 455#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
461#include <linux/i2c-gpio.h> 456#include <linux/i2c-gpio.h>
462 457
@@ -518,6 +513,8 @@ static struct platform_device *stamp_devices[] __initdata = {
518#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) 513#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
519 &i2c_gpio_device, 514 &i2c_gpio_device,
520#endif 515#endif
516
517 &bfin_gpios_device,
521 &stamp_flash_device, 518 &stamp_flash_device,
522}; 519};
523 520
diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c
index 8a3397db1d21..c95395ba7bfa 100644
--- a/arch/blackfin/mach-bf537/boards/generic_board.c
+++ b/arch/blackfin/mach-bf537/boards/generic_board.c
@@ -371,13 +371,6 @@ static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
371}; 371};
372#endif 372#endif
373 373
374#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
375static struct bfin5xx_spi_chip ad5304_chip_info = {
376 .enable_dma = 0,
377 .bits_per_word = 16,
378};
379#endif
380
381#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 374#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
382static struct bfin5xx_spi_chip spi_ad7877_chip_info = { 375static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
383 .enable_dma = 0, 376 .enable_dma = 0,
@@ -483,17 +476,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
483 .mode = SPI_MODE_3, 476 .mode = SPI_MODE_3,
484 }, 477 },
485#endif 478#endif
486#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
487 {
488 .modalias = "ad5304_spi",
489 .max_speed_hz = 1250000, /* max spi clock (SCK) speed in HZ */
490 .bus_num = 0,
491 .chip_select = 2,
492 .platform_data = NULL,
493 .controller_data = &ad5304_chip_info,
494 .mode = SPI_MODE_2,
495 },
496#endif
497#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 479#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
498 { 480 {
499 .modalias = "ad7877", 481 .modalias = "ad7877",
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 9e2277e0d25c..ea83148993da 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -128,6 +128,19 @@ static struct platform_device bfin_device_gpiokeys = {
128}; 128};
129#endif 129#endif
130 130
131static struct resource bfin_gpios_resources = {
132 .start = 0,
133 .end = MAX_BLACKFIN_GPIOS - 1,
134 .flags = IORESOURCE_IRQ,
135};
136
137static struct platform_device bfin_gpios_device = {
138 .name = "simple-gpio",
139 .id = -1,
140 .num_resources = 1,
141 .resource = &bfin_gpios_resources,
142};
143
131#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) 144#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
132static struct resource bfin_pcmcia_cf_resources[] = { 145static struct resource bfin_pcmcia_cf_resources[] = {
133 { 146 {
@@ -343,7 +356,7 @@ static struct platform_device net2272_bfin_device = {
343static struct mtd_partition stamp_partitions[] = { 356static struct mtd_partition stamp_partitions[] = {
344 { 357 {
345 .name = "Bootloader", 358 .name = "Bootloader",
346 .size = 0x20000, 359 .size = 0x40000,
347 .offset = 0, 360 .offset = 0,
348 }, { 361 }, {
349 .name = "Kernel", 362 .name = "Kernel",
@@ -351,7 +364,7 @@ static struct mtd_partition stamp_partitions[] = {
351 .offset = MTDPART_OFS_APPEND, 364 .offset = MTDPART_OFS_APPEND,
352 }, { 365 }, {
353 .name = "RootFS", 366 .name = "RootFS",
354 .size = 0x400000 - 0x20000 - 0xE0000 - 0x10000, 367 .size = 0x400000 - 0x40000 - 0xE0000 - 0x10000,
355 .offset = MTDPART_OFS_APPEND, 368 .offset = MTDPART_OFS_APPEND,
356 }, { 369 }, {
357 .name = "MAC Address", 370 .name = "MAC Address",
@@ -391,17 +404,17 @@ static struct platform_device stamp_flash_device = {
391static struct mtd_partition bfin_spi_flash_partitions[] = { 404static struct mtd_partition bfin_spi_flash_partitions[] = {
392 { 405 {
393 .name = "bootloader", 406 .name = "bootloader",
394 .size = 0x00020000, 407 .size = 0x00040000,
395 .offset = 0, 408 .offset = 0,
396 .mask_flags = MTD_CAP_ROM 409 .mask_flags = MTD_CAP_ROM
397 }, { 410 }, {
398 .name = "kernel", 411 .name = "kernel",
399 .size = 0xe0000, 412 .size = 0xe0000,
400 .offset = 0x20000 413 .offset = MTDPART_OFS_APPEND,
401 }, { 414 }, {
402 .name = "file system", 415 .name = "file system",
403 .size = 0x700000, 416 .size = MTDPART_SIZ_FULL,
404 .offset = 0x00100000, 417 .offset = MTDPART_OFS_APPEND,
405 } 418 }
406}; 419};
407 420
@@ -459,13 +472,6 @@ static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
459}; 472};
460#endif 473#endif
461 474
462#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
463static struct bfin5xx_spi_chip ad5304_chip_info = {
464 .enable_dma = 0,
465 .bits_per_word = 16,
466};
467#endif
468
469#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 475#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
470static struct bfin5xx_spi_chip spi_ad7877_chip_info = { 476static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
471 .enable_dma = 0, 477 .enable_dma = 0,
@@ -578,17 +584,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
578 .mode = SPI_MODE_3, 584 .mode = SPI_MODE_3,
579 }, 585 },
580#endif 586#endif
581#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
582 {
583 .modalias = "ad5304_spi",
584 .max_speed_hz = 1250000, /* max spi clock (SCK) speed in HZ */
585 .bus_num = 0,
586 .chip_select = 2,
587 .platform_data = NULL,
588 .controller_data = &ad5304_chip_info,
589 .mode = SPI_MODE_2,
590 },
591#endif
592#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 587#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
593 { 588 {
594 .modalias = "ad7877", 589 .modalias = "ad7877",
@@ -821,6 +816,8 @@ static struct platform_device *stamp_devices[] __initdata = {
821#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) 816#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
822 &bfin_device_gpiokeys, 817 &bfin_device_gpiokeys,
823#endif 818#endif
819
820 &bfin_gpios_device,
824 &stamp_flash_device, 821 &stamp_flash_device,
825}; 822};
826 823
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 916e963e83ba..a0950c1fd800 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -285,8 +285,8 @@ static struct mtd_partition partition_info[] = {
285 }, 285 },
286 { 286 {
287 .name = "File System", 287 .name = "File System",
288 .offset = 4 * SIZE_1M, 288 .offset = MTDPART_OFS_APPEND,
289 .size = (256 - 4) * SIZE_1M, 289 .size = MTDPART_SIZ_FULL,
290 }, 290 },
291}; 291};
292 292
@@ -333,7 +333,7 @@ static struct platform_device bf54x_sdh_device = {
333static struct mtd_partition ezkit_partitions[] = { 333static struct mtd_partition ezkit_partitions[] = {
334 { 334 {
335 .name = "Bootloader", 335 .name = "Bootloader",
336 .size = 0x20000, 336 .size = 0x40000,
337 .offset = 0, 337 .offset = 0,
338 }, { 338 }, {
339 .name = "Kernel", 339 .name = "Kernel",
@@ -381,8 +381,8 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
381 .mask_flags = MTD_CAP_ROM 381 .mask_flags = MTD_CAP_ROM
382 }, { 382 }, {
383 .name = "linux kernel", 383 .name = "linux kernel",
384 .size = 0x1c0000, 384 .size = MTDPART_SIZ_FULL,
385 .offset = 0x40000 385 .offset = MTDPART_OFS_APPEND,
386 } 386 }
387}; 387};
388 388
@@ -594,6 +594,19 @@ static struct platform_device bfin_device_gpiokeys = {
594}; 594};
595#endif 595#endif
596 596
597static struct resource bfin_gpios_resources = {
598 .start = 0,
599 .end = MAX_BLACKFIN_GPIOS - 1,
600 .flags = IORESOURCE_IRQ,
601};
602
603static struct platform_device bfin_gpios_device = {
604 .name = "simple-gpio",
605 .id = -1,
606 .num_resources = 1,
607 .resource = &bfin_gpios_resources,
608};
609
597static struct platform_device *ezkit_devices[] __initdata = { 610static struct platform_device *ezkit_devices[] __initdata = {
598#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 611#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
599 &rtc_device, 612 &rtc_device,
@@ -646,6 +659,8 @@ static struct platform_device *ezkit_devices[] __initdata = {
646#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) 659#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
647 &bfin_device_gpiokeys, 660 &bfin_device_gpiokeys,
648#endif 661#endif
662
663 &bfin_gpios_device,
649 &ezkit_flash_device, 664 &ezkit_flash_device,
650}; 665};
651 666
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c
index 374803a8d2e8..f5479298bb79 100644
--- a/arch/blackfin/mach-bf548/dma.c
+++ b/arch/blackfin/mach-bf548/dma.c
@@ -27,6 +27,8 @@
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */ 28 */
29 29
30#include <linux/module.h>
31
30#include <asm/blackfin.h> 32#include <asm/blackfin.h>
31#include <asm/dma.h> 33#include <asm/dma.h>
32 34
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
index 74fe258421a5..46222a75321a 100644
--- a/arch/blackfin/mach-bf548/head.S
+++ b/arch/blackfin/mach-bf548/head.S
@@ -28,6 +28,7 @@
28 */ 28 */
29 29
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <linux/init.h>
31#include <asm/blackfin.h> 32#include <asm/blackfin.h>
32#include <asm/trace.h> 33#include <asm/trace.h>
33#if CONFIG_BFIN_KERNEL_CLOCK 34#if CONFIG_BFIN_KERNEL_CLOCK
@@ -44,10 +45,9 @@
44 45
45#define INITIAL_STACK 0xFFB01000 46#define INITIAL_STACK 0xFFB01000
46 47
47.text 48__INIT
48 49
49ENTRY(__start) 50ENTRY(__start)
50ENTRY(__stext)
51 /* R0: argument of command line string, passed from uboot, save it */ 51 /* R0: argument of command line string, passed from uboot, save it */
52 R7 = R0; 52 R7 = R0;
53 /* Enable Cycle Counter and Nesting Of Interrupts */ 53 /* Enable Cycle Counter and Nesting Of Interrupts */
@@ -213,6 +213,7 @@ ENTRY(__stext)
213 213
214.LWAIT_HERE: 214.LWAIT_HERE:
215 jump .LWAIT_HERE; 215 jump .LWAIT_HERE;
216ENDPROC(__start)
216 217
217ENTRY(_real_start) 218ENTRY(_real_start)
218 [ -- sp ] = reti; 219 [ -- sp ] = reti;
@@ -285,6 +286,9 @@ ENTRY(_real_start)
285 call _start_kernel; 286 call _start_kernel;
286.L_exit: 287.L_exit:
287 jump.s .L_exit; 288 jump.s .L_exit;
289ENDPROC(_real_start)
290
291__FINIT
288 292
289.section .l1.text 293.section .l1.text
290#if CONFIG_BFIN_KERNEL_CLOCK 294#if CONFIG_BFIN_KERNEL_CLOCK
@@ -450,6 +454,7 @@ ENTRY(_start_dma_code)
450 SSYNC; 454 SSYNC;
451 455
452 RTS; 456 RTS;
457ENDPROC(_start_dma_code)
453#endif /* CONFIG_BFIN_KERNEL_CLOCK */ 458#endif /* CONFIG_BFIN_KERNEL_CLOCK */
454 459
455.data 460.data
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 43c1b0982819..d357f648d963 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -223,7 +223,7 @@ static struct platform_device bfin_uart_device = {
223static struct mtd_partition ezkit_partitions[] = { 223static struct mtd_partition ezkit_partitions[] = {
224 { 224 {
225 .name = "Bootloader", 225 .name = "Bootloader",
226 .size = 0x20000, 226 .size = 0x40000,
227 .offset = 0, 227 .offset = 0,
228 }, { 228 }, {
229 .name = "Kernel", 229 .name = "Kernel",
@@ -389,6 +389,19 @@ static struct platform_device bfin_device_gpiokeys = {
389}; 389};
390#endif 390#endif
391 391
392static struct resource bfin_gpios_resources = {
393 .start = 0,
394 .end = MAX_BLACKFIN_GPIOS - 1,
395 .flags = IORESOURCE_IRQ,
396};
397
398static struct platform_device bfin_gpios_device = {
399 .name = "simple-gpio",
400 .id = -1,
401 .num_resources = 1,
402 .resource = &bfin_gpios_resources,
403};
404
392#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) 405#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
393#include <linux/i2c-gpio.h> 406#include <linux/i2c-gpio.h>
394 407
@@ -446,6 +459,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
446 &isp1362_hcd_device, 459 &isp1362_hcd_device,
447#endif 460#endif
448 461
462 &bfin_gpios_device,
449 &ezkit_flash_device, 463 &ezkit_flash_device,
450}; 464};
451 465
diff --git a/arch/blackfin/mach-common/dpmc.S b/arch/blackfin/mach-common/dpmc.S
index b80ddd8b232d..9d45aa3265b1 100644
--- a/arch/blackfin/mach-common/dpmc.S
+++ b/arch/blackfin/mach-common/dpmc.S
@@ -31,140 +31,6 @@
31#include <asm/blackfin.h> 31#include <asm/blackfin.h>
32#include <asm/mach/irq.h> 32#include <asm/mach/irq.h>
33 33
34.text
35
36ENTRY(_unmask_wdog_wakeup_evt)
37 [--SP] = ( R7:0, P5:0 );
38#if defined(CONFIG_BF561)
39 P0.H = hi(SICA_IWR1);
40 P0.L = lo(SICA_IWR1);
41#elif defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
42 P0.h = HI(SIC_IWR0);
43 P0.l = LO(SIC_IWR0);
44#else
45 P0.h = HI(SIC_IWR);
46 P0.l = LO(SIC_IWR);
47#endif
48 R7 = [P0];
49#if defined(CONFIG_BF561)
50 BITSET(R7, 27);
51#else
52 BITSET(R7,(IRQ_WATCH - IVG7));
53#endif
54 [P0] = R7;
55 SSYNC;
56
57 ( R7:0, P5:0 ) = [SP++];
58 RTS;
59
60.LWRITE_TO_STAT:
61 /* When watch dog timer is enabled, a write to STAT will load the
62 * contents of CNT to STAT
63 */
64 R7 = 0x0000(z);
65#if defined(CONFIG_BF561)
66 P0.h = HI(WDOGA_STAT);
67 P0.l = LO(WDOGA_STAT);
68#else
69 P0.h = HI(WDOG_STAT);
70 P0.l = LO(WDOG_STAT);
71#endif
72 [P0] = R7;
73 SSYNC;
74 JUMP .LSKIP_WRITE_TO_STAT;
75
76ENTRY(_program_wdog_timer)
77 [--SP] = ( R7:0, P5:0 );
78#if defined(CONFIG_BF561)
79 P0.h = HI(WDOGA_CNT);
80 P0.l = LO(WDOGA_CNT);
81#else
82 P0.h = HI(WDOG_CNT);
83 P0.l = LO(WDOG_CNT);
84#endif
85 [P0] = R0;
86 SSYNC;
87
88#if defined(CONFIG_BF561)
89 P0.h = HI(WDOGA_CTL);
90 P0.l = LO(WDOGA_CTL);
91#else
92 P0.h = HI(WDOG_CTL);
93 P0.l = LO(WDOG_CTL);
94#endif
95 R7 = W[P0](Z);
96 CC = BITTST(R7,1);
97 if !CC JUMP .LWRITE_TO_STAT;
98 CC = BITTST(R7,2);
99 if !CC JUMP .LWRITE_TO_STAT;
100
101.LSKIP_WRITE_TO_STAT:
102#if defined(CONFIG_BF561)
103 P0.h = HI(WDOGA_CTL);
104 P0.l = LO(WDOGA_CTL);
105#else
106 P0.h = HI(WDOG_CTL);
107 P0.l = LO(WDOG_CTL);
108#endif
109 R7 = W[P0](Z);
110 BITCLR(R7,1); /* Enable GP event */
111 BITSET(R7,2);
112 W[P0] = R7.L;
113 SSYNC;
114 NOP;
115
116 R7 = W[P0](Z);
117 BITCLR(R7,4); /* Enable the wdog counter */
118 W[P0] = R7.L;
119 SSYNC;
120
121 ( R7:0, P5:0 ) = [SP++];
122 RTS;
123
124ENTRY(_clear_wdog_wakeup_evt)
125 [--SP] = ( R7:0, P5:0 );
126
127#if defined(CONFIG_BF561)
128 P0.h = HI(WDOGA_CTL);
129 P0.l = LO(WDOGA_CTL);
130#else
131 P0.h = HI(WDOG_CTL);
132 P0.l = LO(WDOG_CTL);
133#endif
134 R7 = 0x0AD6(Z);
135 W[P0] = R7.L;
136 SSYNC;
137
138 R7 = W[P0](Z);
139 BITSET(R7,15);
140 W[P0] = R7.L;
141 SSYNC;
142
143 R7 = W[P0](Z);
144 BITSET(R7,1);
145 BITSET(R7,2);
146 W[P0] = R7.L;
147 SSYNC;
148
149 ( R7:0, P5:0 ) = [SP++];
150 RTS;
151
152ENTRY(_disable_wdog_timer)
153 [--SP] = ( R7:0, P5:0 );
154#if defined(CONFIG_BF561)
155 P0.h = HI(WDOGA_CTL);
156 P0.l = LO(WDOGA_CTL);
157#else
158 P0.h = HI(WDOG_CTL);
159 P0.l = LO(WDOG_CTL);
160#endif
161 R7 = 0xAD6(Z);
162 W[P0] = R7.L;
163 SSYNC;
164 ( R7:0, P5:0 ) = [SP++];
165 RTS;
166
167#if !defined(CONFIG_BF561)
168 34
169.section .l1.text 35.section .l1.text
170 36
@@ -459,10 +325,12 @@ ENTRY(_set_sic_iwr)
459 RTS; 325 RTS;
460 326
461ENTRY(_set_rtc_istat) 327ENTRY(_set_rtc_istat)
328#ifndef CONFIG_BF561
462 P0.H = hi(RTC_ISTAT); 329 P0.H = hi(RTC_ISTAT);
463 P0.L = lo(RTC_ISTAT); 330 P0.L = lo(RTC_ISTAT);
464 w[P0] = R0.L; 331 w[P0] = R0.L;
465 SSYNC; 332 SSYNC;
333#endif
466 RTS; 334 RTS;
467 335
468ENTRY(_test_pll_locked) 336ENTRY(_test_pll_locked)
@@ -473,4 +341,3 @@ ENTRY(_test_pll_locked)
473 CC = BITTST(R0,5); 341 CC = BITTST(R0,5);
474 IF !CC JUMP 1b; 342 IF !CC JUMP 1b;
475 RTS; 343 RTS;
476#endif
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 880595afe98d..225ef14af75e 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -74,7 +74,7 @@ unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
74#endif 74#endif
75 75
76struct ivgx { 76struct ivgx {
77 /* irq number for request_irq, available in mach-bf533/irq.h */ 77 /* irq number for request_irq, available in mach-bf5xx/irq.h */
78 unsigned int irqno; 78 unsigned int irqno;
79 /* corresponding bit in the SIC_ISR register */ 79 /* corresponding bit in the SIC_ISR register */
80 unsigned int isrflag; 80 unsigned int isrflag;
@@ -86,7 +86,6 @@ struct ivg_slice {
86 struct ivgx *istop; 86 struct ivgx *istop;
87} ivg7_13[IVG13 - IVG7 + 1]; 87} ivg7_13[IVG13 - IVG7 + 1];
88 88
89static void search_IAR(void);
90 89
91/* 90/*
92 * Search SIC_IAR and fill tables with the irqvalues 91 * Search SIC_IAR and fill tables with the irqvalues
@@ -120,10 +119,10 @@ static void __init search_IAR(void)
120} 119}
121 120
122/* 121/*
123 * This is for BF533 internal IRQs 122 * This is for core internal IRQs
124 */ 123 */
125 124
126static void ack_noop(unsigned int irq) 125static void bfin_ack_noop(unsigned int irq)
127{ 126{
128 /* Dummy function. */ 127 /* Dummy function. */
129} 128}
@@ -156,11 +155,11 @@ static void bfin_internal_mask_irq(unsigned int irq)
156{ 155{
157#ifdef CONFIG_BF53x 156#ifdef CONFIG_BF53x
158 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & 157 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
159 ~(1 << (irq - (IRQ_CORETMR + 1)))); 158 ~(1 << SIC_SYSIRQ(irq)));
160#else 159#else
161 unsigned mask_bank, mask_bit; 160 unsigned mask_bank, mask_bit;
162 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; 161 mask_bank = SIC_SYSIRQ(irq) / 32;
163 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32; 162 mask_bit = SIC_SYSIRQ(irq) % 32;
164 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & 163 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
165 ~(1 << mask_bit)); 164 ~(1 << mask_bit));
166#endif 165#endif
@@ -171,11 +170,11 @@ static void bfin_internal_unmask_irq(unsigned int irq)
171{ 170{
172#ifdef CONFIG_BF53x 171#ifdef CONFIG_BF53x
173 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 172 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
174 (1 << (irq - (IRQ_CORETMR + 1)))); 173 (1 << SIC_SYSIRQ(irq)));
175#else 174#else
176 unsigned mask_bank, mask_bit; 175 unsigned mask_bank, mask_bit;
177 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; 176 mask_bank = SIC_SYSIRQ(irq) / 32;
178 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32; 177 mask_bit = SIC_SYSIRQ(irq) % 32;
179 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | 178 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
180 (1 << mask_bit)); 179 (1 << mask_bit));
181#endif 180#endif
@@ -187,8 +186,8 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
187{ 186{
188 unsigned bank, bit; 187 unsigned bank, bit;
189 unsigned long flags; 188 unsigned long flags;
190 bank = (irq - (IRQ_CORETMR + 1)) / 32; 189 bank = SIC_SYSIRQ(irq) / 32;
191 bit = (irq - (IRQ_CORETMR + 1)) % 32; 190 bit = SIC_SYSIRQ(irq) % 32;
192 191
193 local_irq_save(flags); 192 local_irq_save(flags);
194 193
@@ -204,15 +203,18 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
204#endif 203#endif
205 204
206static struct irq_chip bfin_core_irqchip = { 205static struct irq_chip bfin_core_irqchip = {
207 .ack = ack_noop, 206 .ack = bfin_ack_noop,
208 .mask = bfin_core_mask_irq, 207 .mask = bfin_core_mask_irq,
209 .unmask = bfin_core_unmask_irq, 208 .unmask = bfin_core_unmask_irq,
210}; 209};
211 210
212static struct irq_chip bfin_internal_irqchip = { 211static struct irq_chip bfin_internal_irqchip = {
213 .ack = ack_noop, 212 .ack = bfin_ack_noop,
214 .mask = bfin_internal_mask_irq, 213 .mask = bfin_internal_mask_irq,
215 .unmask = bfin_internal_unmask_irq, 214 .unmask = bfin_internal_unmask_irq,
215 .mask_ack = bfin_internal_mask_irq,
216 .disable = bfin_internal_mask_irq,
217 .enable = bfin_internal_unmask_irq,
216#ifdef CONFIG_PM 218#ifdef CONFIG_PM
217 .set_wake = bfin_internal_set_wake, 219 .set_wake = bfin_internal_set_wake,
218#endif 220#endif
@@ -221,38 +223,23 @@ static struct irq_chip bfin_internal_irqchip = {
221#ifdef BF537_GENERIC_ERROR_INT_DEMUX 223#ifdef BF537_GENERIC_ERROR_INT_DEMUX
222static int error_int_mask; 224static int error_int_mask;
223 225
224static void bfin_generic_error_ack_irq(unsigned int irq)
225{
226
227}
228
229static void bfin_generic_error_mask_irq(unsigned int irq) 226static void bfin_generic_error_mask_irq(unsigned int irq)
230{ 227{
231 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR)); 228 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
232 229
233 if (!error_int_mask) { 230 if (!error_int_mask)
234 local_irq_disable(); 231 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
235 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
236 ~(1 << (IRQ_GENERIC_ERROR -
237 (IRQ_CORETMR + 1))));
238 SSYNC();
239 local_irq_enable();
240 }
241} 232}
242 233
243static void bfin_generic_error_unmask_irq(unsigned int irq) 234static void bfin_generic_error_unmask_irq(unsigned int irq)
244{ 235{
245 local_irq_disable(); 236 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
246 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 1 <<
247 (IRQ_GENERIC_ERROR - (IRQ_CORETMR + 1)));
248 SSYNC();
249 local_irq_enable();
250
251 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR); 237 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
252} 238}
253 239
254static struct irq_chip bfin_generic_error_irqchip = { 240static struct irq_chip bfin_generic_error_irqchip = {
255 .ack = bfin_generic_error_ack_irq, 241 .ack = bfin_ack_noop,
242 .mask_ack = bfin_generic_error_mask_irq,
256 .mask = bfin_generic_error_mask_irq, 243 .mask = bfin_generic_error_mask_irq,
257 .unmask = bfin_generic_error_unmask_irq, 244 .unmask = bfin_generic_error_unmask_irq,
258}; 245};
@@ -608,7 +595,7 @@ static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
608 (struct pin_int_t *)PINT3_MASK_SET, 595 (struct pin_int_t *)PINT3_MASK_SET,
609}; 596};
610 597
611unsigned short get_irq_base(u8 bank, u8 bmap) 598inline unsigned short get_irq_base(u8 bank, u8 bmap)
612{ 599{
613 600
614 u16 irq_base; 601 u16 irq_base;
@@ -969,17 +956,12 @@ int __init init_arch_irq(void)
969#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) 956#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
970 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); 957 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
971 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); 958 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
972 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
973 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
974# ifdef CONFIG_BF54x 959# ifdef CONFIG_BF54x
975 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); 960 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
976 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
977# endif 961# endif
978#else 962#else
979 bfin_write_SIC_IMASK(SIC_UNMASK_ALL); 963 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
980 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
981#endif 964#endif
982 SSYNC();
983 965
984 local_irq_disable(); 966 local_irq_disable();
985 967
@@ -1001,90 +983,53 @@ int __init init_arch_irq(void)
1001 set_irq_chip(irq, &bfin_core_irqchip); 983 set_irq_chip(irq, &bfin_core_irqchip);
1002 else 984 else
1003 set_irq_chip(irq, &bfin_internal_irqchip); 985 set_irq_chip(irq, &bfin_internal_irqchip);
1004#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1005 if (irq != IRQ_GENERIC_ERROR) {
1006#endif
1007 986
1008 switch (irq) { 987 switch (irq) {
1009#if defined(CONFIG_BF53x) 988#if defined(CONFIG_BF53x)
1010 case IRQ_PROG_INTA: 989 case IRQ_PROG_INTA:
1011 set_irq_chained_handler(irq,
1012 bfin_demux_gpio_irq);
1013 break;
1014# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) 990# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1015 case IRQ_MAC_RX: 991 case IRQ_MAC_RX:
1016 set_irq_chained_handler(irq,
1017 bfin_demux_gpio_irq);
1018 break;
1019# endif 992# endif
1020#elif defined(CONFIG_BF54x) 993#elif defined(CONFIG_BF54x)
1021 case IRQ_PINT0: 994 case IRQ_PINT0:
1022 set_irq_chained_handler(irq, 995 case IRQ_PINT1:
1023 bfin_demux_gpio_irq); 996 case IRQ_PINT2:
1024 break; 997 case IRQ_PINT3:
1025 case IRQ_PINT1:
1026 set_irq_chained_handler(irq,
1027 bfin_demux_gpio_irq);
1028 break;
1029 case IRQ_PINT2:
1030 set_irq_chained_handler(irq,
1031 bfin_demux_gpio_irq);
1032 break;
1033 case IRQ_PINT3:
1034 set_irq_chained_handler(irq,
1035 bfin_demux_gpio_irq);
1036 break;
1037#elif defined(CONFIG_BF52x) 998#elif defined(CONFIG_BF52x)
1038 case IRQ_PORTF_INTA: 999 case IRQ_PORTF_INTA:
1039 set_irq_chained_handler(irq, 1000 case IRQ_PORTG_INTA:
1040 bfin_demux_gpio_irq); 1001 case IRQ_PORTH_INTA:
1041 break;
1042 case IRQ_PORTG_INTA:
1043 set_irq_chained_handler(irq,
1044 bfin_demux_gpio_irq);
1045 break;
1046 case IRQ_PORTH_INTA:
1047 set_irq_chained_handler(irq,
1048 bfin_demux_gpio_irq);
1049 break;
1050#elif defined(CONFIG_BF561) 1002#elif defined(CONFIG_BF561)
1051 case IRQ_PROG0_INTA: 1003 case IRQ_PROG0_INTA:
1052 set_irq_chained_handler(irq, 1004 case IRQ_PROG1_INTA:
1053 bfin_demux_gpio_irq); 1005 case IRQ_PROG2_INTA:
1054 break;
1055 case IRQ_PROG1_INTA:
1056 set_irq_chained_handler(irq,
1057 bfin_demux_gpio_irq);
1058 break;
1059 case IRQ_PROG2_INTA:
1060 set_irq_chained_handler(irq,
1061 bfin_demux_gpio_irq);
1062 break;
1063#endif 1006#endif
1064 default: 1007 set_irq_chained_handler(irq,
1065 set_irq_handler(irq, handle_simple_irq); 1008 bfin_demux_gpio_irq);
1066 break; 1009 break;
1067 }
1068
1069#ifdef BF537_GENERIC_ERROR_INT_DEMUX 1010#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1070 } else { 1011 case IRQ_GENERIC_ERROR:
1071 set_irq_handler(irq, bfin_demux_error_irq); 1012 set_irq_handler(irq, bfin_demux_error_irq);
1072 } 1013
1014 break;
1073#endif 1015#endif
1016 default:
1017 set_irq_handler(irq, handle_simple_irq);
1018 break;
1019 }
1074 } 1020 }
1021
1075#ifdef BF537_GENERIC_ERROR_INT_DEMUX 1022#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1076 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) { 1023 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1077 set_irq_chip(irq, &bfin_generic_error_irqchip); 1024 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1078 set_irq_handler(irq, handle_level_irq); 1025 handle_level_irq);
1079 }
1080#endif 1026#endif
1081 1027
1082 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++) { 1028 /* if configured as edge, then will be changed to do_edge_IRQ */
1029 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1030 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1031 handle_level_irq);
1083 1032
1084 set_irq_chip(irq, &bfin_gpio_irqchip);
1085 /* if configured as edge, then will be changed to do_edge_IRQ */
1086 set_irq_handler(irq, handle_level_irq);
1087 }
1088 1033
1089 bfin_write_IMASK(0); 1034 bfin_write_IMASK(0);
1090 CSYNC(); 1035 CSYNC();
@@ -1106,6 +1051,16 @@ int __init init_arch_irq(void)
1106 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | 1051 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1107 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; 1052 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1108 1053
1054#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1055 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
1056 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
1057# ifdef CONFIG_BF54x
1058 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
1059# endif
1060#else
1061 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
1062#endif
1063
1109 return 0; 1064 return 0;
1110} 1065}
1111 1066
@@ -1122,7 +1077,6 @@ void do_irq(int vec, struct pt_regs *fp)
1122#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) 1077#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1123 unsigned long sic_status[3]; 1078 unsigned long sic_status[3];
1124 1079
1125 SSYNC();
1126 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); 1080 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1127 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); 1081 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1128#ifdef CONFIG_BF54x 1082#ifdef CONFIG_BF54x
@@ -1138,7 +1092,7 @@ void do_irq(int vec, struct pt_regs *fp)
1138 } 1092 }
1139#else 1093#else
1140 unsigned long sic_status; 1094 unsigned long sic_status;
1141 SSYNC(); 1095
1142 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); 1096 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1143 1097
1144 for (;; ivg++) { 1098 for (;; ivg++) {
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index 1f516c55bde6..ec3141fefd20 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -181,7 +181,7 @@ void __init mem_init(void)
181 } 181 }
182} 182}
183 183
184static __init void free_init_pages(const char *what, unsigned long begin, unsigned long end) 184static void __init free_init_pages(const char *what, unsigned long begin, unsigned long end)
185{ 185{
186 unsigned long addr; 186 unsigned long addr;
187 /* next to check that the page we free is not a partial page */ 187 /* next to check that the page we free is not a partial page */
@@ -203,7 +203,7 @@ void __init free_initrd_mem(unsigned long start, unsigned long end)
203} 203}
204#endif 204#endif
205 205
206void __init free_initmem(void) 206void __init_refok free_initmem(void)
207{ 207{
208#if defined CONFIG_RAMKERNEL && !defined CONFIG_MPU 208#if defined CONFIG_RAMKERNEL && !defined CONFIG_MPU
209 free_init_pages("unused kernel memory", 209 free_init_pages("unused kernel memory",
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index b82595cf13e8..cf627cd1b4c8 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -686,7 +686,7 @@ config UART0_RTS_PIN
686 686
687config SERIAL_BFIN_UART1 687config SERIAL_BFIN_UART1
688 bool "Enable UART1" 688 bool "Enable UART1"
689 depends on SERIAL_BFIN && (BF534 || BF536 || BF537 || BF54x) 689 depends on SERIAL_BFIN && (!BF531 && !BF532 && !BF533 && !BF561)
690 help 690 help
691 Enable UART1 691 Enable UART1
692 692
@@ -699,14 +699,14 @@ config BFIN_UART1_CTSRTS
699 699
700config UART1_CTS_PIN 700config UART1_CTS_PIN
701 int "UART1 CTS pin" 701 int "UART1 CTS pin"
702 depends on BFIN_UART1_CTSRTS && (BF53x || BF561) 702 depends on BFIN_UART1_CTSRTS && !BF54x
703 default -1 703 default -1
704 help 704 help
705 Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. 705 Refer to ./include/asm-blackfin/gpio.h to see the GPIO map.
706 706
707config UART1_RTS_PIN 707config UART1_RTS_PIN
708 int "UART1 RTS pin" 708 int "UART1 RTS pin"
709 depends on BFIN_UART1_CTSRTS && (BF53x || BF561) 709 depends on BFIN_UART1_CTSRTS && !BF54x
710 default -1 710 default -1
711 help 711 help
712 Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. 712 Refer to ./include/asm-blackfin/gpio.h to see the GPIO map.
diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c
index ac2a3ef28d55..0aa345b9a38b 100644
--- a/drivers/serial/bfin_5xx.c
+++ b/drivers/serial/bfin_5xx.c
@@ -1,30 +1,11 @@
1/* 1/*
2 * File: drivers/serial/bfin_5xx.c 2 * Blackfin On-Chip Serial Driver
3 * Based on: Based on drivers/serial/sa1100.c
4 * Author: Aubrey Li <aubrey.li@analog.com>
5 * 3 *
6 * Created: 4 * Copyright 2006-2007 Analog Devices Inc.
7 * Description: Driver for blackfin 5xx serial ports
8 * 5 *
9 * Modified: 6 * Enter bugs at http://blackfin.uclinux.org/
10 * Copyright 2006 Analog Devices Inc.
11 * 7 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 8 * Licensed under the GPL-2 or later.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */ 9 */
29 10
30#if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 11#if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
@@ -67,14 +48,12 @@
67#define DMA_RX_XCOUNT 512 48#define DMA_RX_XCOUNT 512
68#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT) 49#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
69 50
70#define DMA_RX_FLUSH_JIFFIES 5 51#define DMA_RX_FLUSH_JIFFIES (HZ / 50)
71 52
72#ifdef CONFIG_SERIAL_BFIN_DMA 53#ifdef CONFIG_SERIAL_BFIN_DMA
73static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart); 54static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
74#else 55#else
75static void bfin_serial_do_work(struct work_struct *work);
76static void bfin_serial_tx_chars(struct bfin_serial_port *uart); 56static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
77static void local_put_char(struct bfin_serial_port *uart, char ch);
78#endif 57#endif
79 58
80static void bfin_serial_mctrl_check(struct bfin_serial_port *uart); 59static void bfin_serial_mctrl_check(struct bfin_serial_port *uart);
@@ -85,23 +64,26 @@ static void bfin_serial_mctrl_check(struct bfin_serial_port *uart);
85static void bfin_serial_stop_tx(struct uart_port *port) 64static void bfin_serial_stop_tx(struct uart_port *port)
86{ 65{
87 struct bfin_serial_port *uart = (struct bfin_serial_port *)port; 66 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
67 struct circ_buf *xmit = &uart->port.info->xmit;
68#if !defined(CONFIG_BF54x) && !defined(CONFIG_SERIAL_BFIN_DMA)
69 unsigned short ier;
70#endif
88 71
89 while (!(UART_GET_LSR(uart) & TEMT)) 72 while (!(UART_GET_LSR(uart) & TEMT))
90 continue; 73 cpu_relax();
91 74
92#ifdef CONFIG_SERIAL_BFIN_DMA 75#ifdef CONFIG_SERIAL_BFIN_DMA
93 disable_dma(uart->tx_dma_channel); 76 disable_dma(uart->tx_dma_channel);
77 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
78 uart->port.icount.tx += uart->tx_count;
79 uart->tx_count = 0;
80 uart->tx_done = 1;
94#else 81#else
95#ifdef CONFIG_BF54x 82#ifdef CONFIG_BF54x
96 /* Waiting for Transmission Finished */
97 while (!(UART_GET_LSR(uart) & TFI))
98 continue;
99 /* Clear TFI bit */ 83 /* Clear TFI bit */
100 UART_PUT_LSR(uart, TFI); 84 UART_PUT_LSR(uart, TFI);
101 UART_CLEAR_IER(uart, ETBEI); 85 UART_CLEAR_IER(uart, ETBEI);
102#else 86#else
103 unsigned short ier;
104
105 ier = UART_GET_IER(uart); 87 ier = UART_GET_IER(uart);
106 ier &= ~ETBEI; 88 ier &= ~ETBEI;
107 UART_PUT_IER(uart, ier); 89 UART_PUT_IER(uart, ier);
@@ -117,7 +99,8 @@ static void bfin_serial_start_tx(struct uart_port *port)
117 struct bfin_serial_port *uart = (struct bfin_serial_port *)port; 99 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
118 100
119#ifdef CONFIG_SERIAL_BFIN_DMA 101#ifdef CONFIG_SERIAL_BFIN_DMA
120 bfin_serial_dma_tx_chars(uart); 102 if (uart->tx_done)
103 bfin_serial_dma_tx_chars(uart);
121#else 104#else
122#ifdef CONFIG_BF54x 105#ifdef CONFIG_BF54x
123 UART_SET_IER(uart, ETBEI); 106 UART_SET_IER(uart, ETBEI);
@@ -209,34 +192,27 @@ int kgdb_get_debug_char(void)
209} 192}
210#endif 193#endif
211 194
212#ifdef CONFIG_SERIAL_BFIN_PIO 195#if ANOMALY_05000230 && defined(CONFIG_SERIAL_BFIN_PIO)
213static void local_put_char(struct bfin_serial_port *uart, char ch) 196# define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
214{ 197# define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
215 unsigned short status; 198#else
216 int flags = 0; 199# define UART_GET_ANOMALY_THRESHOLD(uart) 0
217 200# define UART_SET_ANOMALY_THRESHOLD(uart, v)
218 spin_lock_irqsave(&uart->port.lock, flags); 201#endif
219
220 do {
221 status = UART_GET_LSR(uart);
222 } while (!(status & THRE));
223
224 UART_PUT_CHAR(uart, ch);
225 SSYNC();
226
227 spin_unlock_irqrestore(&uart->port.lock, flags);
228}
229 202
203#ifdef CONFIG_SERIAL_BFIN_PIO
230static void bfin_serial_rx_chars(struct bfin_serial_port *uart) 204static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
231{ 205{
232 struct tty_struct *tty = uart->port.info->tty; 206 struct tty_struct *tty = uart->port.info->tty;
233 unsigned int status, ch, flg; 207 unsigned int status, ch, flg;
234 static int in_break = 0; 208 static struct timeval anomaly_start = { .tv_sec = 0 };
235#ifdef CONFIG_KGDB_UART 209#ifdef CONFIG_KGDB_UART
236 struct pt_regs *regs = get_irq_regs(); 210 struct pt_regs *regs = get_irq_regs();
237#endif 211#endif
238 212
239 status = UART_GET_LSR(uart); 213 status = UART_GET_LSR(uart);
214 UART_CLEAR_LSR(uart);
215
240 ch = UART_GET_CHAR(uart); 216 ch = UART_GET_CHAR(uart);
241 uart->port.icount.rx++; 217 uart->port.icount.rx++;
242 218
@@ -262,28 +238,56 @@ static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
262#endif 238#endif
263 239
264 if (ANOMALY_05000230) { 240 if (ANOMALY_05000230) {
265 /* The BF533 family of processors have a nice misbehavior where 241 /* The BF533 (and BF561) family of processors have a nice anomaly
266 * they continuously generate characters for a "single" break. 242 * where they continuously generate characters for a "single" break.
267 * We have to basically ignore this flood until the "next" valid 243 * We have to basically ignore this flood until the "next" valid
268 * character comes across. All other Blackfin families operate 244 * character comes across. Due to the nature of the flood, it is
269 * properly though. 245 * not possible to reliably catch bytes that are sent too quickly
246 * after this break. So application code talking to the Blackfin
247 * which sends a break signal must allow at least 1.5 character
248 * times after the end of the break for things to stabilize. This
249 * timeout was picked as it must absolutely be larger than 1
250 * character time +/- some percent. So 1.5 sounds good. All other
251 * Blackfin families operate properly. Woo.
270 * Note: While Anomaly 05000230 does not directly address this, 252 * Note: While Anomaly 05000230 does not directly address this,
271 * the changes that went in for it also fixed this issue. 253 * the changes that went in for it also fixed this issue.
254 * That anomaly was fixed in 0.5+ silicon. I like bunnies.
272 */ 255 */
273 if (in_break) { 256 if (anomaly_start.tv_sec) {
274 if (ch != 0) { 257 struct timeval curr;
275 in_break = 0; 258 suseconds_t usecs;
276 ch = UART_GET_CHAR(uart); 259
277 if (bfin_revid() < 5) 260 if ((~ch & (~ch + 1)) & 0xff)
278 return; 261 goto known_good_char;
279 } else 262
280 return; 263 do_gettimeofday(&curr);
264 if (curr.tv_sec - anomaly_start.tv_sec > 1)
265 goto known_good_char;
266
267 usecs = 0;
268 if (curr.tv_sec != anomaly_start.tv_sec)
269 usecs += USEC_PER_SEC;
270 usecs += curr.tv_usec - anomaly_start.tv_usec;
271
272 if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
273 goto known_good_char;
274
275 if (ch)
276 anomaly_start.tv_sec = 0;
277 else
278 anomaly_start = curr;
279
280 return;
281
282 known_good_char:
283 anomaly_start.tv_sec = 0;
281 } 284 }
282 } 285 }
283 286
284 if (status & BI) { 287 if (status & BI) {
285 if (ANOMALY_05000230) 288 if (ANOMALY_05000230)
286 in_break = 1; 289 if (bfin_revid() < 5)
290 do_gettimeofday(&anomaly_start);
287 uart->port.icount.brk++; 291 uart->port.icount.brk++;
288 if (uart_handle_break(&uart->port)) 292 if (uart_handle_break(&uart->port))
289 goto ignore_char; 293 goto ignore_char;
@@ -324,7 +328,6 @@ static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
324 UART_PUT_CHAR(uart, uart->port.x_char); 328 UART_PUT_CHAR(uart, uart->port.x_char);
325 uart->port.icount.tx++; 329 uart->port.icount.tx++;
326 uart->port.x_char = 0; 330 uart->port.x_char = 0;
327 return;
328 } 331 }
329 /* 332 /*
330 * Check the modem control lines before 333 * Check the modem control lines before
@@ -337,9 +340,12 @@ static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
337 return; 340 return;
338 } 341 }
339 342
340 local_put_char(uart, xmit->buf[xmit->tail]); 343 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
341 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 344 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
342 uart->port.icount.tx++; 345 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
346 uart->port.icount.tx++;
347 SSYNC();
348 }
343 349
344 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 350 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
345 uart_write_wakeup(&uart->port); 351 uart_write_wakeup(&uart->port);
@@ -352,21 +358,11 @@ static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
352{ 358{
353 struct bfin_serial_port *uart = dev_id; 359 struct bfin_serial_port *uart = dev_id;
354 360
355#ifdef CONFIG_BF54x
356 unsigned short status;
357 spin_lock(&uart->port.lock);
358 status = UART_GET_LSR(uart);
359 while ((UART_GET_IER(uart) & ERBFI) && (status & DR)) {
360 bfin_serial_rx_chars(uart);
361 status = UART_GET_LSR(uart);
362 }
363 spin_unlock(&uart->port.lock);
364#else
365 spin_lock(&uart->port.lock); 361 spin_lock(&uart->port.lock);
366 while ((UART_GET_IIR(uart) & IIR_STATUS) == IIR_RX_READY) 362 while (UART_GET_LSR(uart) & DR)
367 bfin_serial_rx_chars(uart); 363 bfin_serial_rx_chars(uart);
368 spin_unlock(&uart->port.lock); 364 spin_unlock(&uart->port.lock);
369#endif 365
370 return IRQ_HANDLED; 366 return IRQ_HANDLED;
371} 367}
372 368
@@ -374,25 +370,16 @@ static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
374{ 370{
375 struct bfin_serial_port *uart = dev_id; 371 struct bfin_serial_port *uart = dev_id;
376 372
377#ifdef CONFIG_BF54x
378 unsigned short status;
379 spin_lock(&uart->port.lock); 373 spin_lock(&uart->port.lock);
380 status = UART_GET_LSR(uart); 374 if (UART_GET_LSR(uart) & THRE)
381 while ((UART_GET_IER(uart) & ETBEI) && (status & THRE)) {
382 bfin_serial_tx_chars(uart); 375 bfin_serial_tx_chars(uart);
383 status = UART_GET_LSR(uart);
384 }
385 spin_unlock(&uart->port.lock); 376 spin_unlock(&uart->port.lock);
386#else 377
387 spin_lock(&uart->port.lock);
388 while ((UART_GET_IIR(uart) & IIR_STATUS) == IIR_TX_READY)
389 bfin_serial_tx_chars(uart);
390 spin_unlock(&uart->port.lock);
391#endif
392 return IRQ_HANDLED; 378 return IRQ_HANDLED;
393} 379}
380#endif
394 381
395 382#ifdef CONFIG_SERIAL_BFIN_CTSRTS
396static void bfin_serial_do_work(struct work_struct *work) 383static void bfin_serial_do_work(struct work_struct *work)
397{ 384{
398 struct bfin_serial_port *uart = container_of(work, struct bfin_serial_port, cts_workqueue); 385 struct bfin_serial_port *uart = container_of(work, struct bfin_serial_port, cts_workqueue);
@@ -406,33 +393,27 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
406{ 393{
407 struct circ_buf *xmit = &uart->port.info->xmit; 394 struct circ_buf *xmit = &uart->port.info->xmit;
408 unsigned short ier; 395 unsigned short ier;
409 int flags = 0;
410
411 if (!uart->tx_done)
412 return;
413 396
414 uart->tx_done = 0; 397 uart->tx_done = 0;
415 398
399 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
400 uart->tx_count = 0;
401 uart->tx_done = 1;
402 return;
403 }
404
416 if (uart->port.x_char) { 405 if (uart->port.x_char) {
417 UART_PUT_CHAR(uart, uart->port.x_char); 406 UART_PUT_CHAR(uart, uart->port.x_char);
418 uart->port.icount.tx++; 407 uart->port.icount.tx++;
419 uart->port.x_char = 0; 408 uart->port.x_char = 0;
420 uart->tx_done = 1;
421 return;
422 } 409 }
410
423 /* 411 /*
424 * Check the modem control lines before 412 * Check the modem control lines before
425 * transmitting anything. 413 * transmitting anything.
426 */ 414 */
427 bfin_serial_mctrl_check(uart); 415 bfin_serial_mctrl_check(uart);
428 416
429 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
430 bfin_serial_stop_tx(&uart->port);
431 uart->tx_done = 1;
432 return;
433 }
434
435 spin_lock_irqsave(&uart->port.lock, flags);
436 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE); 417 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
437 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail)) 418 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
438 uart->tx_count = UART_XMIT_SIZE - xmit->tail; 419 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
@@ -448,6 +429,7 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
448 set_dma_x_count(uart->tx_dma_channel, uart->tx_count); 429 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
449 set_dma_x_modify(uart->tx_dma_channel, 1); 430 set_dma_x_modify(uart->tx_dma_channel, 1);
450 enable_dma(uart->tx_dma_channel); 431 enable_dma(uart->tx_dma_channel);
432
451#ifdef CONFIG_BF54x 433#ifdef CONFIG_BF54x
452 UART_SET_IER(uart, ETBEI); 434 UART_SET_IER(uart, ETBEI);
453#else 435#else
@@ -455,7 +437,6 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
455 ier |= ETBEI; 437 ier |= ETBEI;
456 UART_PUT_IER(uart, ier); 438 UART_PUT_IER(uart, ier);
457#endif 439#endif
458 spin_unlock_irqrestore(&uart->port.lock, flags);
459} 440}
460 441
461static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart) 442static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
@@ -464,7 +445,11 @@ static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
464 int i, flg, status; 445 int i, flg, status;
465 446
466 status = UART_GET_LSR(uart); 447 status = UART_GET_LSR(uart);
467 uart->port.icount.rx += CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail, UART_XMIT_SIZE);; 448 UART_CLEAR_LSR(uart);
449
450 uart->port.icount.rx +=
451 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
452 UART_XMIT_SIZE);
468 453
469 if (status & BI) { 454 if (status & BI) {
470 uart->port.icount.brk++; 455 uart->port.icount.brk++;
@@ -490,10 +475,12 @@ static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
490 else 475 else
491 flg = TTY_NORMAL; 476 flg = TTY_NORMAL;
492 477
493 for (i = uart->rx_dma_buf.head; i < uart->rx_dma_buf.tail; i++) { 478 for (i = uart->rx_dma_buf.tail; i != uart->rx_dma_buf.head; i++) {
494 if (uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i])) 479 if (i >= UART_XMIT_SIZE)
495 goto dma_ignore_char; 480 i = 0;
496 uart_insert_char(&uart->port, status, OE, uart->rx_dma_buf.buf[i], flg); 481 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
482 uart_insert_char(&uart->port, status, OE,
483 uart->rx_dma_buf.buf[i], flg);
497 } 484 }
498 485
499 dma_ignore_char: 486 dma_ignore_char:
@@ -503,23 +490,23 @@ static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
503void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart) 490void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
504{ 491{
505 int x_pos, pos; 492 int x_pos, pos;
506 int flags = 0;
507
508 bfin_serial_dma_tx_chars(uart);
509 493
510 spin_lock_irqsave(&uart->port.lock, flags); 494 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
511 x_pos = DMA_RX_XCOUNT - get_dma_curr_xcount(uart->rx_dma_channel); 495 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
496 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
497 if (uart->rx_dma_nrows == DMA_RX_YCOUNT)
498 uart->rx_dma_nrows = 0;
499 x_pos = DMA_RX_XCOUNT - x_pos;
512 if (x_pos == DMA_RX_XCOUNT) 500 if (x_pos == DMA_RX_XCOUNT)
513 x_pos = 0; 501 x_pos = 0;
514 502
515 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos; 503 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
516 504 if (pos != uart->rx_dma_buf.tail) {
517 if (pos>uart->rx_dma_buf.tail) { 505 uart->rx_dma_buf.head = pos;
518 uart->rx_dma_buf.tail = pos;
519 bfin_serial_dma_rx_chars(uart); 506 bfin_serial_dma_rx_chars(uart);
520 uart->rx_dma_buf.head = uart->rx_dma_buf.tail; 507 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
521 } 508 }
522 spin_unlock_irqrestore(&uart->port.lock, flags); 509
523 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; 510 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
524 add_timer(&(uart->rx_dma_timer)); 511 add_timer(&(uart->rx_dma_timer));
525} 512}
@@ -532,8 +519,8 @@ static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
532 519
533 spin_lock(&uart->port.lock); 520 spin_lock(&uart->port.lock);
534 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) { 521 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
535 clear_dma_irqstat(uart->tx_dma_channel);
536 disable_dma(uart->tx_dma_channel); 522 disable_dma(uart->tx_dma_channel);
523 clear_dma_irqstat(uart->tx_dma_channel);
537#ifdef CONFIG_BF54x 524#ifdef CONFIG_BF54x
538 UART_CLEAR_IER(uart, ETBEI); 525 UART_CLEAR_IER(uart, ETBEI);
539#else 526#else
@@ -541,15 +528,13 @@ static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
541 ier &= ~ETBEI; 528 ier &= ~ETBEI;
542 UART_PUT_IER(uart, ier); 529 UART_PUT_IER(uart, ier);
543#endif 530#endif
544 xmit->tail = (xmit->tail+uart->tx_count) &(UART_XMIT_SIZE -1); 531 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
545 uart->port.icount.tx+=uart->tx_count; 532 uart->port.icount.tx += uart->tx_count;
546 533
547 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 534 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
548 uart_write_wakeup(&uart->port); 535 uart_write_wakeup(&uart->port);
549 536
550 if (uart_circ_empty(xmit)) 537 bfin_serial_dma_tx_chars(uart);
551 bfin_serial_stop_tx(&uart->port);
552 uart->tx_done = 1;
553 } 538 }
554 539
555 spin_unlock(&uart->port.lock); 540 spin_unlock(&uart->port.lock);
@@ -561,18 +546,15 @@ static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
561 struct bfin_serial_port *uart = dev_id; 546 struct bfin_serial_port *uart = dev_id;
562 unsigned short irqstat; 547 unsigned short irqstat;
563 548
564 uart->rx_dma_nrows++;
565 if (uart->rx_dma_nrows == DMA_RX_YCOUNT) {
566 uart->rx_dma_nrows = 0;
567 uart->rx_dma_buf.tail = DMA_RX_XCOUNT*DMA_RX_YCOUNT;
568 bfin_serial_dma_rx_chars(uart);
569 uart->rx_dma_buf.head = uart->rx_dma_buf.tail = 0;
570 }
571 spin_lock(&uart->port.lock); 549 spin_lock(&uart->port.lock);
572 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel); 550 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
573 clear_dma_irqstat(uart->rx_dma_channel); 551 clear_dma_irqstat(uart->rx_dma_channel);
574
575 spin_unlock(&uart->port.lock); 552 spin_unlock(&uart->port.lock);
553
554 del_timer(&(uart->rx_dma_timer));
555 uart->rx_dma_timer.expires = jiffies;
556 add_timer(&(uart->rx_dma_timer));
557
576 return IRQ_HANDLED; 558 return IRQ_HANDLED;
577} 559}
578#endif 560#endif
@@ -599,7 +581,11 @@ static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
599 if (uart->cts_pin < 0) 581 if (uart->cts_pin < 0)
600 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 582 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
601 583
584# ifdef BF54x
585 if (UART_GET_MSR(uart) & CTS)
586# else
602 if (gpio_get_value(uart->cts_pin)) 587 if (gpio_get_value(uart->cts_pin))
588# endif
603 return TIOCM_DSR | TIOCM_CAR; 589 return TIOCM_DSR | TIOCM_CAR;
604 else 590 else
605#endif 591#endif
@@ -614,9 +600,17 @@ static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
614 return; 600 return;
615 601
616 if (mctrl & TIOCM_RTS) 602 if (mctrl & TIOCM_RTS)
603# ifdef BF54x
604 UART_PUT_MCR(uart, UART_GET_MCR(uart) & ~MRTS);
605# else
617 gpio_set_value(uart->rts_pin, 0); 606 gpio_set_value(uart->rts_pin, 0);
607# endif
618 else 608 else
609# ifdef BF54x
610 UART_PUT_MCR(uart, UART_GET_MCR(uart) | MRTS);
611# else
619 gpio_set_value(uart->rts_pin, 1); 612 gpio_set_value(uart->rts_pin, 1);
613# endif
620#endif 614#endif
621} 615}
622 616
@@ -627,22 +621,17 @@ static void bfin_serial_mctrl_check(struct bfin_serial_port *uart)
627{ 621{
628#ifdef CONFIG_SERIAL_BFIN_CTSRTS 622#ifdef CONFIG_SERIAL_BFIN_CTSRTS
629 unsigned int status; 623 unsigned int status;
630# ifdef CONFIG_SERIAL_BFIN_DMA
631 struct uart_info *info = uart->port.info; 624 struct uart_info *info = uart->port.info;
632 struct tty_struct *tty = info->tty; 625 struct tty_struct *tty = info->tty;
633 626
634 status = bfin_serial_get_mctrl(&uart->port); 627 status = bfin_serial_get_mctrl(&uart->port);
628 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
635 if (!(status & TIOCM_CTS)) { 629 if (!(status & TIOCM_CTS)) {
636 tty->hw_stopped = 1; 630 tty->hw_stopped = 1;
631 schedule_work(&uart->cts_workqueue);
637 } else { 632 } else {
638 tty->hw_stopped = 0; 633 tty->hw_stopped = 0;
639 } 634 }
640# else
641 status = bfin_serial_get_mctrl(&uart->port);
642 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
643 if (!(status & TIOCM_CTS))
644 schedule_work(&uart->cts_workqueue);
645# endif
646#endif 635#endif
647} 636}
648 637
@@ -743,6 +732,7 @@ static void bfin_serial_shutdown(struct uart_port *port)
743 disable_dma(uart->rx_dma_channel); 732 disable_dma(uart->rx_dma_channel);
744 free_dma(uart->rx_dma_channel); 733 free_dma(uart->rx_dma_channel);
745 del_timer(&(uart->rx_dma_timer)); 734 del_timer(&(uart->rx_dma_timer));
735 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
746#else 736#else
747#ifdef CONFIG_KGDB_UART 737#ifdef CONFIG_KGDB_UART
748 if (uart->port.line != CONFIG_KGDB_UART_PORT) 738 if (uart->port.line != CONFIG_KGDB_UART_PORT)
@@ -814,6 +804,8 @@ bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
814 quot = uart_get_divisor(port, baud); 804 quot = uart_get_divisor(port, baud);
815 spin_lock_irqsave(&uart->port.lock, flags); 805 spin_lock_irqsave(&uart->port.lock, flags);
816 806
807 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
808
817 do { 809 do {
818 lsr = UART_GET_LSR(uart); 810 lsr = UART_GET_LSR(uart);
819 } while (!(lsr & TEMT)); 811 } while (!(lsr & TEMT));
@@ -956,10 +948,9 @@ static void __init bfin_serial_init_ports(void)
956 bfin_serial_ports[i].rx_dma_channel = 948 bfin_serial_ports[i].rx_dma_channel =
957 bfin_serial_resource[i].uart_rx_dma_channel; 949 bfin_serial_resource[i].uart_rx_dma_channel;
958 init_timer(&(bfin_serial_ports[i].rx_dma_timer)); 950 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
959#else
960 INIT_WORK(&bfin_serial_ports[i].cts_workqueue, bfin_serial_do_work);
961#endif 951#endif
962#ifdef CONFIG_SERIAL_BFIN_CTSRTS 952#ifdef CONFIG_SERIAL_BFIN_CTSRTS
953 INIT_WORK(&bfin_serial_ports[i].cts_workqueue, bfin_serial_do_work);
963 bfin_serial_ports[i].cts_pin = 954 bfin_serial_ports[i].cts_pin =
964 bfin_serial_resource[i].uart_cts_pin; 955 bfin_serial_resource[i].uart_cts_pin;
965 bfin_serial_ports[i].rts_pin = 956 bfin_serial_ports[i].rts_pin =
diff --git a/include/asm-blackfin/gptimers.h b/include/asm-blackfin/gptimers.h
index 8265ea473d5b..4f318f1fd2d9 100644
--- a/include/asm-blackfin/gptimers.h
+++ b/include/asm-blackfin/gptimers.h
@@ -1,12 +1,11 @@
1/* 1/*
2 * include/asm/bf5xx_timers.h 2 * gptimers.h - Blackfin General Purpose Timer structs/defines/prototypes
3 *
4 * This file contains the major Data structures and constants
5 * used for General Purpose Timer Implementation in BF5xx
6 * 3 *
4 * Copyright (c) 2005-2008 Analog Devices Inc.
7 * Copyright (C) 2005 John DeHority 5 * Copyright (C) 2005 John DeHority
8 * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de) 6 * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de)
9 * 7 *
8 * Licensed under the GPL-2.
10 */ 9 */
11 10
12#ifndef _BLACKFIN_TIMERS_H_ 11#ifndef _BLACKFIN_TIMERS_H_
diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h
index 65480dab244e..86b67834354d 100644
--- a/include/asm-blackfin/irq.h
+++ b/include/asm-blackfin/irq.h
@@ -67,4 +67,6 @@ static __inline__ int irq_canonicalize(int irq)
67#define NO_IRQ ((unsigned int)(-1)) 67#define NO_IRQ ((unsigned int)(-1))
68#endif 68#endif
69 69
70#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
71
70#endif /* _BFIN_IRQ_H_ */ 72#endif /* _BFIN_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
index 15dbc21eed8b..c0694ecd2ecd 100644
--- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
@@ -23,7 +23,6 @@
23#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) 23#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
24#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) 24#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
25#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) 25#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
26#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
27#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) 26#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
28 27
29#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v) 28#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
@@ -58,6 +57,7 @@
58struct bfin_serial_port { 57struct bfin_serial_port {
59 struct uart_port port; 58 struct uart_port port;
60 unsigned int old_status; 59 unsigned int old_status;
60 unsigned int lsr;
61#ifdef CONFIG_SERIAL_BFIN_DMA 61#ifdef CONFIG_SERIAL_BFIN_DMA
62 int tx_done; 62 int tx_done;
63 int tx_count; 63 int tx_count;
@@ -67,15 +67,31 @@ struct bfin_serial_port {
67 unsigned int tx_dma_channel; 67 unsigned int tx_dma_channel;
68 unsigned int rx_dma_channel; 68 unsigned int rx_dma_channel;
69 struct work_struct tx_dma_workqueue; 69 struct work_struct tx_dma_workqueue;
70#else
71 struct work_struct cts_workqueue;
72#endif 70#endif
73#ifdef CONFIG_SERIAL_BFIN_CTSRTS 71#ifdef CONFIG_SERIAL_BFIN_CTSRTS
72 struct work_struct cts_workqueue;
74 int cts_pin; 73 int cts_pin;
75 int rts_pin; 74 int rts_pin;
76#endif 75#endif
77}; 76};
78 77
78/* The hardware clears the LSR bits upon read, so we need to cache
79 * some of the more fun bits in software so they don't get lost
80 * when checking the LSR in other code paths (TX).
81 */
82static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
83{
84 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
85 uart->lsr |= (lsr & (BI|FE|PE|OE));
86 return lsr | uart->lsr;
87}
88
89static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
90{
91 uart->lsr = 0;
92 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
93}
94
79struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 95struct bfin_serial_port bfin_serial_ports[NR_PORTS];
80struct bfin_serial_res { 96struct bfin_serial_res {
81 unsigned long uart_base_addr; 97 unsigned long uart_base_addr;
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
index 7871d4313f49..b6f513bee56e 100644
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -23,7 +23,6 @@
23#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) 23#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
24#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) 24#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
25#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) 25#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
26#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
27#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) 26#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
28 27
29#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) 28#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
@@ -46,6 +45,7 @@
46struct bfin_serial_port { 45struct bfin_serial_port {
47 struct uart_port port; 46 struct uart_port port;
48 unsigned int old_status; 47 unsigned int old_status;
48 unsigned int lsr;
49#ifdef CONFIG_SERIAL_BFIN_DMA 49#ifdef CONFIG_SERIAL_BFIN_DMA
50 int tx_done; 50 int tx_done;
51 int tx_count; 51 int tx_count;
@@ -56,14 +56,34 @@ struct bfin_serial_port {
56 unsigned int rx_dma_channel; 56 unsigned int rx_dma_channel;
57 struct work_struct tx_dma_workqueue; 57 struct work_struct tx_dma_workqueue;
58#else 58#else
59 struct work_struct cts_workqueue; 59# if ANOMALY_05000230
60 unsigned int anomaly_threshold;
61# endif
60#endif 62#endif
61#ifdef CONFIG_SERIAL_BFIN_CTSRTS 63#ifdef CONFIG_SERIAL_BFIN_CTSRTS
64 struct work_struct cts_workqueue;
62 int cts_pin; 65 int cts_pin;
63 int rts_pin; 66 int rts_pin;
64#endif 67#endif
65}; 68};
66 69
70/* The hardware clears the LSR bits upon read, so we need to cache
71 * some of the more fun bits in software so they don't get lost
72 * when checking the LSR in other code paths (TX).
73 */
74static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
75{
76 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
77 uart->lsr |= (lsr & (BI|FE|PE|OE));
78 return lsr | uart->lsr;
79}
80
81static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
82{
83 uart->lsr = 0;
84 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
85}
86
67struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 87struct bfin_serial_port bfin_serial_ports[NR_PORTS];
68struct bfin_serial_res { 88struct bfin_serial_res {
69 unsigned long uart_base_addr; 89 unsigned long uart_base_addr;
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
index 86e45c379838..8fc672d31057 100644
--- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
@@ -23,7 +23,6 @@
23#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) 23#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
24#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) 24#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
25#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) 25#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
26#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
27#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) 26#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
28 27
29#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) 28#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
@@ -58,6 +57,7 @@
58struct bfin_serial_port { 57struct bfin_serial_port {
59 struct uart_port port; 58 struct uart_port port;
60 unsigned int old_status; 59 unsigned int old_status;
60 unsigned int lsr;
61#ifdef CONFIG_SERIAL_BFIN_DMA 61#ifdef CONFIG_SERIAL_BFIN_DMA
62 int tx_done; 62 int tx_done;
63 int tx_count; 63 int tx_count;
@@ -67,15 +67,31 @@ struct bfin_serial_port {
67 unsigned int tx_dma_channel; 67 unsigned int tx_dma_channel;
68 unsigned int rx_dma_channel; 68 unsigned int rx_dma_channel;
69 struct work_struct tx_dma_workqueue; 69 struct work_struct tx_dma_workqueue;
70#else
71 struct work_struct cts_workqueue;
72#endif 70#endif
73#ifdef CONFIG_SERIAL_BFIN_CTSRTS 71#ifdef CONFIG_SERIAL_BFIN_CTSRTS
72 struct work_struct cts_workqueue;
74 int cts_pin; 73 int cts_pin;
75 int rts_pin; 74 int rts_pin;
76#endif 75#endif
77}; 76};
78 77
78/* The hardware clears the LSR bits upon read, so we need to cache
79 * some of the more fun bits in software so they don't get lost
80 * when checking the LSR in other code paths (TX).
81 */
82static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
83{
84 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
85 uart->lsr |= (lsr & (BI|FE|PE|OE));
86 return lsr | uart->lsr;
87}
88
89static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
90{
91 uart->lsr = 0;
92 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
93}
94
79struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 95struct bfin_serial_port bfin_serial_ports[NR_PORTS];
80struct bfin_serial_res { 96struct bfin_serial_res {
81 unsigned long uart_base_addr; 97 unsigned long uart_base_addr;
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
index 3770aa38ee9f..7e6339f62a50 100644
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -24,6 +24,8 @@
24#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) 24#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
25#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) 25#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
26#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) 26#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
27#define UART_GET_MSR(uart) bfin_read16(((uart)->port.membase + OFFSET_MSR))
28#define UART_GET_MCR(uart) bfin_read16(((uart)->port.membase + OFFSET_MCR))
27 29
28#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) 30#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
29#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) 31#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
@@ -32,7 +34,9 @@
32#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) 34#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
33#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v) 35#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
34#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) 36#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
37#define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
35#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) 38#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
39#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
36 40
37#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 41#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
38# define CONFIG_SERIAL_BFIN_CTSRTS 42# define CONFIG_SERIAL_BFIN_CTSRTS
@@ -68,10 +72,9 @@ struct bfin_serial_port {
68 unsigned int tx_dma_channel; 72 unsigned int tx_dma_channel;
69 unsigned int rx_dma_channel; 73 unsigned int rx_dma_channel;
70 struct work_struct tx_dma_workqueue; 74 struct work_struct tx_dma_workqueue;
71#else
72 struct work_struct cts_workqueue;
73#endif 75#endif
74#ifdef CONFIG_SERIAL_BFIN_CTSRTS 76#ifdef CONFIG_SERIAL_BFIN_CTSRTS
77 struct work_struct cts_workqueue;
75 int cts_pin; 78 int cts_pin;
76 int rts_pin; 79 int rts_pin;
77#endif 80#endif
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
index 7871d4313f49..b6f513bee56e 100644
--- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
@@ -23,7 +23,6 @@
23#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) 23#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
24#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) 24#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
25#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) 25#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
26#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
27#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) 26#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
28 27
29#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) 28#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
@@ -46,6 +45,7 @@
46struct bfin_serial_port { 45struct bfin_serial_port {
47 struct uart_port port; 46 struct uart_port port;
48 unsigned int old_status; 47 unsigned int old_status;
48 unsigned int lsr;
49#ifdef CONFIG_SERIAL_BFIN_DMA 49#ifdef CONFIG_SERIAL_BFIN_DMA
50 int tx_done; 50 int tx_done;
51 int tx_count; 51 int tx_count;
@@ -56,14 +56,34 @@ struct bfin_serial_port {
56 unsigned int rx_dma_channel; 56 unsigned int rx_dma_channel;
57 struct work_struct tx_dma_workqueue; 57 struct work_struct tx_dma_workqueue;
58#else 58#else
59 struct work_struct cts_workqueue; 59# if ANOMALY_05000230
60 unsigned int anomaly_threshold;
61# endif
60#endif 62#endif
61#ifdef CONFIG_SERIAL_BFIN_CTSRTS 63#ifdef CONFIG_SERIAL_BFIN_CTSRTS
64 struct work_struct cts_workqueue;
62 int cts_pin; 65 int cts_pin;
63 int rts_pin; 66 int rts_pin;
64#endif 67#endif
65}; 68};
66 69
70/* The hardware clears the LSR bits upon read, so we need to cache
71 * some of the more fun bits in software so they don't get lost
72 * when checking the LSR in other code paths (TX).
73 */
74static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
75{
76 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
77 uart->lsr |= (lsr & (BI|FE|PE|OE));
78 return lsr | uart->lsr;
79}
80
81static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
82{
83 uart->lsr = 0;
84 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
85}
86
67struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 87struct bfin_serial_port bfin_serial_ports[NR_PORTS];
68struct bfin_serial_res { 88struct bfin_serial_res {
69 unsigned long uart_base_addr; 89 unsigned long uart_base_addr;
diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h
index 362617f93845..3a16df2c86d8 100644
--- a/include/asm-blackfin/mach-bf561/blackfin.h
+++ b/include/asm-blackfin/mach-bf561/blackfin.h
@@ -49,7 +49,8 @@
49#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() 49#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
50#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) 50#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
51 51
52 52#define SIC_IWR0 SICA_IWR0
53#define SIC_IWR1 SICA_IWR1
53#define SIC_IAR0 SICA_IAR0 54#define SIC_IAR0 SICA_IAR0
54#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0 55#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0
55#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1 56#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
index d667816486c0..1bc8d2f89ccc 100644
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -559,6 +559,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
559#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL,val) 559#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL,val)
560#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS) 560#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS)
561#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS,val) 561#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS,val)
562#define bfin_clear_PPI0_STATUS() bfin_read_PPI0_STATUS()
562#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT) 563#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT)
563#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT,val) 564#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT,val)
564#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY) 565#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY)
@@ -570,6 +571,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
570#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL,val) 571#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL,val)
571#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS) 572#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS)
572#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS,val) 573#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS,val)
574#define bfin_clear_PPI1_STATUS() bfin_read_PPI1_STATUS()
573#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT) 575#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT)
574#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT,val) 576#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT,val)
575#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY) 577#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY)