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-rw-r--r--arch/arm/mach-at91rm9200/at91rm9200.c32
-rw-r--r--arch/arm/mach-at91rm9200/clock.c28
-rw-r--r--arch/arm/mach-at91rm9200/devices.c72
-rw-r--r--arch/arm/mach-at91rm9200/gpio.c16
-rw-r--r--arch/arm/mach-at91rm9200/irq.c4
-rw-r--r--arch/arm/mach-at91rm9200/pm.c14
-rw-r--r--drivers/mmc/at91_mci.c4
-rw-r--r--drivers/net/arm/at91_ether.c2
-rw-r--r--drivers/serial/at91_serial.c2
-rw-r--r--drivers/usb/gadget/at91_udc.c6
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200.h118
-rw-r--r--include/asm-arm/arch-at91rm9200/gpio.h2
-rw-r--r--include/asm-arm/arch-at91rm9200/hardware.h37
-rw-r--r--include/asm-arm/arch-at91rm9200/irqs.h2
14 files changed, 173 insertions, 166 deletions
diff --git a/arch/arm/mach-at91rm9200/at91rm9200.c b/arch/arm/mach-at91rm9200/at91rm9200.c
index 0985b1c42c7c..e21cb845d112 100644
--- a/arch/arm/mach-at91rm9200/at91rm9200.c
+++ b/arch/arm/mach-at91rm9200/at91rm9200.c
@@ -26,78 +26,78 @@ static struct map_desc at91rm9200_io_desc[] __initdata = {
26 .type = MT_DEVICE, 26 .type = MT_DEVICE,
27 }, { 27 }, {
28 .virtual = AT91_VA_BASE_SPI, 28 .virtual = AT91_VA_BASE_SPI,
29 .pfn = __phys_to_pfn(AT91_BASE_SPI), 29 .pfn = __phys_to_pfn(AT91RM9200_BASE_SPI),
30 .length = SZ_16K, 30 .length = SZ_16K,
31 .type = MT_DEVICE, 31 .type = MT_DEVICE,
32 }, { 32 }, {
33 .virtual = AT91_VA_BASE_SSC2, 33 .virtual = AT91_VA_BASE_SSC2,
34 .pfn = __phys_to_pfn(AT91_BASE_SSC2), 34 .pfn = __phys_to_pfn(AT91RM9200_BASE_SSC2),
35 .length = SZ_16K, 35 .length = SZ_16K,
36 .type = MT_DEVICE, 36 .type = MT_DEVICE,
37 }, { 37 }, {
38 .virtual = AT91_VA_BASE_SSC1, 38 .virtual = AT91_VA_BASE_SSC1,
39 .pfn = __phys_to_pfn(AT91_BASE_SSC1), 39 .pfn = __phys_to_pfn(AT91RM9200_BASE_SSC1),
40 .length = SZ_16K, 40 .length = SZ_16K,
41 .type = MT_DEVICE, 41 .type = MT_DEVICE,
42 }, { 42 }, {
43 .virtual = AT91_VA_BASE_SSC0, 43 .virtual = AT91_VA_BASE_SSC0,
44 .pfn = __phys_to_pfn(AT91_BASE_SSC0), 44 .pfn = __phys_to_pfn(AT91RM9200_BASE_SSC0),
45 .length = SZ_16K, 45 .length = SZ_16K,
46 .type = MT_DEVICE, 46 .type = MT_DEVICE,
47 }, { 47 }, {
48 .virtual = AT91_VA_BASE_US3, 48 .virtual = AT91_VA_BASE_US3,
49 .pfn = __phys_to_pfn(AT91_BASE_US3), 49 .pfn = __phys_to_pfn(AT91RM9200_BASE_US3),
50 .length = SZ_16K, 50 .length = SZ_16K,
51 .type = MT_DEVICE, 51 .type = MT_DEVICE,
52 }, { 52 }, {
53 .virtual = AT91_VA_BASE_US2, 53 .virtual = AT91_VA_BASE_US2,
54 .pfn = __phys_to_pfn(AT91_BASE_US2), 54 .pfn = __phys_to_pfn(AT91RM9200_BASE_US2),
55 .length = SZ_16K, 55 .length = SZ_16K,
56 .type = MT_DEVICE, 56 .type = MT_DEVICE,
57 }, { 57 }, {
58 .virtual = AT91_VA_BASE_US1, 58 .virtual = AT91_VA_BASE_US1,
59 .pfn = __phys_to_pfn(AT91_BASE_US1), 59 .pfn = __phys_to_pfn(AT91RM9200_BASE_US1),
60 .length = SZ_16K, 60 .length = SZ_16K,
61 .type = MT_DEVICE, 61 .type = MT_DEVICE,
62 }, { 62 }, {
63 .virtual = AT91_VA_BASE_US0, 63 .virtual = AT91_VA_BASE_US0,
64 .pfn = __phys_to_pfn(AT91_BASE_US0), 64 .pfn = __phys_to_pfn(AT91RM9200_BASE_US0),
65 .length = SZ_16K, 65 .length = SZ_16K,
66 .type = MT_DEVICE, 66 .type = MT_DEVICE,
67 }, { 67 }, {
68 .virtual = AT91_VA_BASE_EMAC, 68 .virtual = AT91_VA_BASE_EMAC,
69 .pfn = __phys_to_pfn(AT91_BASE_EMAC), 69 .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC),
70 .length = SZ_16K, 70 .length = SZ_16K,
71 .type = MT_DEVICE, 71 .type = MT_DEVICE,
72 }, { 72 }, {
73 .virtual = AT91_VA_BASE_TWI, 73 .virtual = AT91_VA_BASE_TWI,
74 .pfn = __phys_to_pfn(AT91_BASE_TWI), 74 .pfn = __phys_to_pfn(AT91RM9200_BASE_TWI),
75 .length = SZ_16K, 75 .length = SZ_16K,
76 .type = MT_DEVICE, 76 .type = MT_DEVICE,
77 }, { 77 }, {
78 .virtual = AT91_VA_BASE_MCI, 78 .virtual = AT91_VA_BASE_MCI,
79 .pfn = __phys_to_pfn(AT91_BASE_MCI), 79 .pfn = __phys_to_pfn(AT91RM9200_BASE_MCI),
80 .length = SZ_16K, 80 .length = SZ_16K,
81 .type = MT_DEVICE, 81 .type = MT_DEVICE,
82 }, { 82 }, {
83 .virtual = AT91_VA_BASE_UDP, 83 .virtual = AT91_VA_BASE_UDP,
84 .pfn = __phys_to_pfn(AT91_BASE_UDP), 84 .pfn = __phys_to_pfn(AT91RM9200_BASE_UDP),
85 .length = SZ_16K, 85 .length = SZ_16K,
86 .type = MT_DEVICE, 86 .type = MT_DEVICE,
87 }, { 87 }, {
88 .virtual = AT91_VA_BASE_TCB1, 88 .virtual = AT91_VA_BASE_TCB1,
89 .pfn = __phys_to_pfn(AT91_BASE_TCB1), 89 .pfn = __phys_to_pfn(AT91RM9200_BASE_TCB1),
90 .length = SZ_16K, 90 .length = SZ_16K,
91 .type = MT_DEVICE, 91 .type = MT_DEVICE,
92 }, { 92 }, {
93 .virtual = AT91_VA_BASE_TCB0, 93 .virtual = AT91_VA_BASE_TCB0,
94 .pfn = __phys_to_pfn(AT91_BASE_TCB0), 94 .pfn = __phys_to_pfn(AT91RM9200_BASE_TCB0),
95 .length = SZ_16K, 95 .length = SZ_16K,
96 .type = MT_DEVICE, 96 .type = MT_DEVICE,
97 }, { 97 }, {
98 .virtual = AT91_SRAM_VIRT_BASE, 98 .virtual = AT91_SRAM_VIRT_BASE,
99 .pfn = __phys_to_pfn(AT91_SRAM_BASE), 99 .pfn = __phys_to_pfn(AT91RM9200_SRAM_BASE),
100 .length = AT91_SRAM_SIZE, 100 .length = AT91RM9200_SRAM_SIZE,
101 .type = MT_DEVICE, 101 .type = MT_DEVICE,
102 }, 102 },
103}; 103};
diff --git a/arch/arm/mach-at91rm9200/clock.c b/arch/arm/mach-at91rm9200/clock.c
index edc2cc837ae6..5b7892277bee 100644
--- a/arch/arm/mach-at91rm9200/clock.c
+++ b/arch/arm/mach-at91rm9200/clock.c
@@ -190,85 +190,85 @@ static void pmc_periph_mode(struct clk *clk, int is_on)
190static struct clk udc_clk = { 190static struct clk udc_clk = {
191 .name = "udc_clk", 191 .name = "udc_clk",
192 .parent = &mck, 192 .parent = &mck,
193 .pmc_mask = 1 << AT91_ID_UDP, 193 .pmc_mask = 1 << AT91RM9200_ID_UDP,
194 .mode = pmc_periph_mode, 194 .mode = pmc_periph_mode,
195}; 195};
196static struct clk ohci_clk = { 196static struct clk ohci_clk = {
197 .name = "ohci_clk", 197 .name = "ohci_clk",
198 .parent = &mck, 198 .parent = &mck,
199 .pmc_mask = 1 << AT91_ID_UHP, 199 .pmc_mask = 1 << AT91RM9200_ID_UHP,
200 .mode = pmc_periph_mode, 200 .mode = pmc_periph_mode,
201}; 201};
202static struct clk ether_clk = { 202static struct clk ether_clk = {
203 .name = "ether_clk", 203 .name = "ether_clk",
204 .parent = &mck, 204 .parent = &mck,
205 .pmc_mask = 1 << AT91_ID_EMAC, 205 .pmc_mask = 1 << AT91RM9200_ID_EMAC,
206 .mode = pmc_periph_mode, 206 .mode = pmc_periph_mode,
207}; 207};
208static struct clk mmc_clk = { 208static struct clk mmc_clk = {
209 .name = "mci_clk", 209 .name = "mci_clk",
210 .parent = &mck, 210 .parent = &mck,
211 .pmc_mask = 1 << AT91_ID_MCI, 211 .pmc_mask = 1 << AT91RM9200_ID_MCI,
212 .mode = pmc_periph_mode, 212 .mode = pmc_periph_mode,
213}; 213};
214static struct clk twi_clk = { 214static struct clk twi_clk = {
215 .name = "twi_clk", 215 .name = "twi_clk",
216 .parent = &mck, 216 .parent = &mck,
217 .pmc_mask = 1 << AT91_ID_TWI, 217 .pmc_mask = 1 << AT91RM9200_ID_TWI,
218 .mode = pmc_periph_mode, 218 .mode = pmc_periph_mode,
219}; 219};
220static struct clk usart0_clk = { 220static struct clk usart0_clk = {
221 .name = "usart0_clk", 221 .name = "usart0_clk",
222 .parent = &mck, 222 .parent = &mck,
223 .pmc_mask = 1 << AT91_ID_US0, 223 .pmc_mask = 1 << AT91RM9200_ID_US0,
224 .mode = pmc_periph_mode, 224 .mode = pmc_periph_mode,
225}; 225};
226static struct clk usart1_clk = { 226static struct clk usart1_clk = {
227 .name = "usart1_clk", 227 .name = "usart1_clk",
228 .parent = &mck, 228 .parent = &mck,
229 .pmc_mask = 1 << AT91_ID_US1, 229 .pmc_mask = 1 << AT91RM9200_ID_US1,
230 .mode = pmc_periph_mode, 230 .mode = pmc_periph_mode,
231}; 231};
232static struct clk usart2_clk = { 232static struct clk usart2_clk = {
233 .name = "usart2_clk", 233 .name = "usart2_clk",
234 .parent = &mck, 234 .parent = &mck,
235 .pmc_mask = 1 << AT91_ID_US2, 235 .pmc_mask = 1 << AT91RM9200_ID_US2,
236 .mode = pmc_periph_mode, 236 .mode = pmc_periph_mode,
237}; 237};
238static struct clk usart3_clk = { 238static struct clk usart3_clk = {
239 .name = "usart3_clk", 239 .name = "usart3_clk",
240 .parent = &mck, 240 .parent = &mck,
241 .pmc_mask = 1 << AT91_ID_US3, 241 .pmc_mask = 1 << AT91RM9200_ID_US3,
242 .mode = pmc_periph_mode, 242 .mode = pmc_periph_mode,
243}; 243};
244static struct clk spi_clk = { 244static struct clk spi_clk = {
245 .name = "spi0_clk", 245 .name = "spi0_clk",
246 .parent = &mck, 246 .parent = &mck,
247 .pmc_mask = 1 << AT91_ID_SPI, 247 .pmc_mask = 1 << AT91RM9200_ID_SPI,
248 .mode = pmc_periph_mode, 248 .mode = pmc_periph_mode,
249}; 249};
250static struct clk pioA_clk = { 250static struct clk pioA_clk = {
251 .name = "pioA_clk", 251 .name = "pioA_clk",
252 .parent = &mck, 252 .parent = &mck,
253 .pmc_mask = 1 << AT91_ID_PIOA, 253 .pmc_mask = 1 << AT91RM9200_ID_PIOA,
254 .mode = pmc_periph_mode, 254 .mode = pmc_periph_mode,
255}; 255};
256static struct clk pioB_clk = { 256static struct clk pioB_clk = {
257 .name = "pioB_clk", 257 .name = "pioB_clk",
258 .parent = &mck, 258 .parent = &mck,
259 .pmc_mask = 1 << AT91_ID_PIOB, 259 .pmc_mask = 1 << AT91RM9200_ID_PIOB,
260 .mode = pmc_periph_mode, 260 .mode = pmc_periph_mode,
261}; 261};
262static struct clk pioC_clk = { 262static struct clk pioC_clk = {
263 .name = "pioC_clk", 263 .name = "pioC_clk",
264 .parent = &mck, 264 .parent = &mck,
265 .pmc_mask = 1 << AT91_ID_PIOC, 265 .pmc_mask = 1 << AT91RM9200_ID_PIOC,
266 .mode = pmc_periph_mode, 266 .mode = pmc_periph_mode,
267}; 267};
268static struct clk pioD_clk = { 268static struct clk pioD_clk = {
269 .name = "pioD_clk", 269 .name = "pioD_clk",
270 .parent = &mck, 270 .parent = &mck,
271 .pmc_mask = 1 << AT91_ID_PIOD, 271 .pmc_mask = 1 << AT91RM9200_ID_PIOD,
272 .mode = pmc_periph_mode, 272 .mode = pmc_periph_mode,
273}; 273};
274 274
diff --git a/arch/arm/mach-at91rm9200/devices.c b/arch/arm/mach-at91rm9200/devices.c
index 4352acb88178..db7c684cdb63 100644
--- a/arch/arm/mach-at91rm9200/devices.c
+++ b/arch/arm/mach-at91rm9200/devices.c
@@ -35,13 +35,13 @@ static struct at91_usbh_data usbh_data;
35 35
36static struct resource at91_usbh_resources[] = { 36static struct resource at91_usbh_resources[] = {
37 [0] = { 37 [0] = {
38 .start = AT91_UHP_BASE, 38 .start = AT91RM9200_UHP_BASE,
39 .end = AT91_UHP_BASE + SZ_1M - 1, 39 .end = AT91RM9200_UHP_BASE + SZ_1M - 1,
40 .flags = IORESOURCE_MEM, 40 .flags = IORESOURCE_MEM,
41 }, 41 },
42 [1] = { 42 [1] = {
43 .start = AT91_ID_UHP, 43 .start = AT91RM9200_ID_UHP,
44 .end = AT91_ID_UHP, 44 .end = AT91RM9200_ID_UHP,
45 .flags = IORESOURCE_IRQ, 45 .flags = IORESOURCE_IRQ,
46 }, 46 },
47}; 47};
@@ -80,13 +80,13 @@ static struct at91_udc_data udc_data;
80 80
81static struct resource at91_udc_resources[] = { 81static struct resource at91_udc_resources[] = {
82 [0] = { 82 [0] = {
83 .start = AT91_BASE_UDP, 83 .start = AT91RM9200_BASE_UDP,
84 .end = AT91_BASE_UDP + SZ_16K - 1, 84 .end = AT91RM9200_BASE_UDP + SZ_16K - 1,
85 .flags = IORESOURCE_MEM, 85 .flags = IORESOURCE_MEM,
86 }, 86 },
87 [1] = { 87 [1] = {
88 .start = AT91_ID_UDP, 88 .start = AT91RM9200_ID_UDP,
89 .end = AT91_ID_UDP, 89 .end = AT91RM9200_ID_UDP,
90 .flags = IORESOURCE_IRQ, 90 .flags = IORESOURCE_IRQ,
91 }, 91 },
92}; 92};
@@ -131,13 +131,13 @@ static struct at91_eth_data eth_data;
131 131
132static struct resource at91_eth_resources[] = { 132static struct resource at91_eth_resources[] = {
133 [0] = { 133 [0] = {
134 .start = AT91_BASE_EMAC, 134 .start = AT91RM9200_BASE_EMAC,
135 .end = AT91_BASE_EMAC + SZ_16K - 1, 135 .end = AT91RM9200_BASE_EMAC + SZ_16K - 1,
136 .flags = IORESOURCE_MEM, 136 .flags = IORESOURCE_MEM,
137 }, 137 },
138 [1] = { 138 [1] = {
139 .start = AT91_ID_EMAC, 139 .start = AT91RM9200_ID_EMAC,
140 .end = AT91_ID_EMAC, 140 .end = AT91RM9200_ID_EMAC,
141 .flags = IORESOURCE_IRQ, 141 .flags = IORESOURCE_IRQ,
142 }, 142 },
143}; 143};
@@ -263,13 +263,13 @@ static struct at91_mmc_data mmc_data;
263 263
264static struct resource at91_mmc_resources[] = { 264static struct resource at91_mmc_resources[] = {
265 [0] = { 265 [0] = {
266 .start = AT91_BASE_MCI, 266 .start = AT91RM9200_BASE_MCI,
267 .end = AT91_BASE_MCI + SZ_16K - 1, 267 .end = AT91RM9200_BASE_MCI + SZ_16K - 1,
268 .flags = IORESOURCE_MEM, 268 .flags = IORESOURCE_MEM,
269 }, 269 },
270 [1] = { 270 [1] = {
271 .start = AT91_ID_MCI, 271 .start = AT91RM9200_ID_MCI,
272 .end = AT91_ID_MCI, 272 .end = AT91RM9200_ID_MCI,
273 .flags = IORESOURCE_IRQ, 273 .flags = IORESOURCE_IRQ,
274 }, 274 },
275}; 275};
@@ -423,13 +423,13 @@ static u64 spi_dmamask = 0xffffffffUL;
423 423
424static struct resource at91_spi_resources[] = { 424static struct resource at91_spi_resources[] = {
425 [0] = { 425 [0] = {
426 .start = AT91_BASE_SPI, 426 .start = AT91RM9200_BASE_SPI,
427 .end = AT91_BASE_SPI + SZ_16K - 1, 427 .end = AT91RM9200_BASE_SPI + SZ_16K - 1,
428 .flags = IORESOURCE_MEM, 428 .flags = IORESOURCE_MEM,
429 }, 429 },
430 [1] = { 430 [1] = {
431 .start = AT91_ID_SPI, 431 .start = AT91RM9200_ID_SPI,
432 .end = AT91_ID_SPI, 432 .end = AT91RM9200_ID_SPI,
433 .flags = IORESOURCE_IRQ, 433 .flags = IORESOURCE_IRQ,
434 }, 434 },
435}; 435};
@@ -582,13 +582,13 @@ static inline void configure_dbgu_pins(void)
582 582
583static struct resource uart0_resources[] = { 583static struct resource uart0_resources[] = {
584 [0] = { 584 [0] = {
585 .start = AT91_BASE_US0, 585 .start = AT91RM9200_BASE_US0,
586 .end = AT91_BASE_US0 + SZ_16K - 1, 586 .end = AT91RM9200_BASE_US0 + SZ_16K - 1,
587 .flags = IORESOURCE_MEM, 587 .flags = IORESOURCE_MEM,
588 }, 588 },
589 [1] = { 589 [1] = {
590 .start = AT91_ID_US0, 590 .start = AT91RM9200_ID_US0,
591 .end = AT91_ID_US0, 591 .end = AT91RM9200_ID_US0,
592 .flags = IORESOURCE_IRQ, 592 .flags = IORESOURCE_IRQ,
593 }, 593 },
594}; 594};
@@ -624,13 +624,13 @@ static inline void configure_usart0_pins(void)
624 624
625static struct resource uart1_resources[] = { 625static struct resource uart1_resources[] = {
626 [0] = { 626 [0] = {
627 .start = AT91_BASE_US1, 627 .start = AT91RM9200_BASE_US1,
628 .end = AT91_BASE_US1 + SZ_16K - 1, 628 .end = AT91RM9200_BASE_US1 + SZ_16K - 1,
629 .flags = IORESOURCE_MEM, 629 .flags = IORESOURCE_MEM,
630 }, 630 },
631 [1] = { 631 [1] = {
632 .start = AT91_ID_US1, 632 .start = AT91RM9200_ID_US1,
633 .end = AT91_ID_US1, 633 .end = AT91RM9200_ID_US1,
634 .flags = IORESOURCE_IRQ, 634 .flags = IORESOURCE_IRQ,
635 }, 635 },
636}; 636};
@@ -665,13 +665,13 @@ static inline void configure_usart1_pins(void)
665 665
666static struct resource uart2_resources[] = { 666static struct resource uart2_resources[] = {
667 [0] = { 667 [0] = {
668 .start = AT91_BASE_US2, 668 .start = AT91RM9200_BASE_US2,
669 .end = AT91_BASE_US2 + SZ_16K - 1, 669 .end = AT91RM9200_BASE_US2 + SZ_16K - 1,
670 .flags = IORESOURCE_MEM, 670 .flags = IORESOURCE_MEM,
671 }, 671 },
672 [1] = { 672 [1] = {
673 .start = AT91_ID_US2, 673 .start = AT91RM9200_ID_US2,
674 .end = AT91_ID_US2, 674 .end = AT91RM9200_ID_US2,
675 .flags = IORESOURCE_IRQ, 675 .flags = IORESOURCE_IRQ,
676 }, 676 },
677}; 677};
@@ -700,13 +700,13 @@ static inline void configure_usart2_pins(void)
700 700
701static struct resource uart3_resources[] = { 701static struct resource uart3_resources[] = {
702 [0] = { 702 [0] = {
703 .start = AT91_BASE_US3, 703 .start = AT91RM9200_BASE_US3,
704 .end = AT91_BASE_US3 + SZ_16K - 1, 704 .end = AT91RM9200_BASE_US3 + SZ_16K - 1,
705 .flags = IORESOURCE_MEM, 705 .flags = IORESOURCE_MEM,
706 }, 706 },
707 [1] = { 707 [1] = {
708 .start = AT91_ID_US3, 708 .start = AT91RM9200_ID_US3,
709 .end = AT91_ID_US3, 709 .end = AT91RM9200_ID_US3,
710 .flags = IORESOURCE_IRQ, 710 .flags = IORESOURCE_IRQ,
711 }, 711 },
712}; 712};
diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c
index cec199fd6721..8476cb8856c9 100644
--- a/arch/arm/mach-at91rm9200/gpio.c
+++ b/arch/arm/mach-at91rm9200/gpio.c
@@ -261,10 +261,10 @@ void at91_gpio_suspend(void)
261 at91_sys_write(pio_controller_offset[i] + PIO_IER, wakeups[i]); 261 at91_sys_write(pio_controller_offset[i] + PIO_IER, wakeups[i]);
262 262
263 if (!wakeups[i]) { 263 if (!wakeups[i]) {
264 disable_irq_wake(AT91_ID_PIOA + i); 264 disable_irq_wake(AT91RM9200_ID_PIOA + i);
265 at91_sys_write(AT91_PMC_PCDR, 1 << (AT91_ID_PIOA + i)); 265 at91_sys_write(AT91_PMC_PCDR, 1 << (AT91RM9200_ID_PIOA + i));
266 } else { 266 } else {
267 enable_irq_wake(AT91_ID_PIOA + i); 267 enable_irq_wake(AT91RM9200_ID_PIOA + i);
268#ifdef CONFIG_PM_DEBUG 268#ifdef CONFIG_PM_DEBUG
269 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", "ABCD"[i], wakeups[i]); 269 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", "ABCD"[i], wakeups[i]);
270#endif 270#endif
@@ -282,10 +282,10 @@ void at91_gpio_resume(void)
282 } 282 }
283 283
284 at91_sys_write(AT91_PMC_PCER, 284 at91_sys_write(AT91_PMC_PCER,
285 (1 << AT91_ID_PIOA) 285 (1 << AT91RM9200_ID_PIOA)
286 | (1 << AT91_ID_PIOB) 286 | (1 << AT91RM9200_ID_PIOB)
287 | (1 << AT91_ID_PIOC) 287 | (1 << AT91RM9200_ID_PIOC)
288 | (1 << AT91_ID_PIOD)); 288 | (1 << AT91RM9200_ID_PIOD));
289} 289}
290 290
291#else 291#else
@@ -384,7 +384,7 @@ void __init at91_gpio_irq_setup(unsigned banks)
384 384
385 if (banks > 4) 385 if (banks > 4)
386 banks = 4; 386 banks = 4;
387 for (pioc = 0, pin = PIN_BASE, id = AT91_ID_PIOA; 387 for (pioc = 0, pin = PIN_BASE, id = AT91RM9200_ID_PIOA;
388 pioc < banks; 388 pioc < banks;
389 pioc++, id++) { 389 pioc++, id++) {
390 void __iomem *controller; 390 void __iomem *controller;
diff --git a/arch/arm/mach-at91rm9200/irq.c b/arch/arm/mach-at91rm9200/irq.c
index c3a5e777f9f8..8cd60a99c5b8 100644
--- a/arch/arm/mach-at91rm9200/irq.c
+++ b/arch/arm/mach-at91rm9200/irq.c
@@ -61,12 +61,12 @@ static int at91_aic_set_type(unsigned irq, unsigned type)
61 srctype = AT91_AIC_SRCTYPE_RISING; 61 srctype = AT91_AIC_SRCTYPE_RISING;
62 break; 62 break;
63 case IRQT_LOW: 63 case IRQT_LOW:
64 if ((irq > AT91_ID_FIQ) && (irq < AT91_ID_IRQ0)) /* only supported on external interrupts */ 64 if ((irq > AT91_ID_FIQ) && (irq < AT91RM9200_ID_IRQ0)) /* only supported on external interrupts */
65 return -EINVAL; 65 return -EINVAL;
66 srctype = AT91_AIC_SRCTYPE_LOW; 66 srctype = AT91_AIC_SRCTYPE_LOW;
67 break; 67 break;
68 case IRQT_FALLING: 68 case IRQT_FALLING:
69 if ((irq > AT91_ID_FIQ) && (irq < AT91_ID_IRQ0)) /* only supported on external interrupts */ 69 if ((irq > AT91_ID_FIQ) && (irq < AT91RM9200_ID_IRQ0)) /* only supported on external interrupts */
70 return -EINVAL; 70 return -EINVAL;
71 srctype = AT91_AIC_SRCTYPE_FALLING; 71 srctype = AT91_AIC_SRCTYPE_FALLING;
72 break; 72 break;
diff --git a/arch/arm/mach-at91rm9200/pm.c b/arch/arm/mach-at91rm9200/pm.c
index 47e5480feb7e..32c95d8eaacf 100644
--- a/arch/arm/mach-at91rm9200/pm.c
+++ b/arch/arm/mach-at91rm9200/pm.c
@@ -123,13 +123,13 @@ static int at91_pm_enter(suspend_state_t state)
123 (at91_sys_read(AT91_PMC_PCSR) 123 (at91_sys_read(AT91_PMC_PCSR)
124 | (1 << AT91_ID_FIQ) 124 | (1 << AT91_ID_FIQ)
125 | (1 << AT91_ID_SYS) 125 | (1 << AT91_ID_SYS)
126 | (1 << AT91_ID_IRQ0) 126 | (1 << AT91RM9200_ID_IRQ0)
127 | (1 << AT91_ID_IRQ1) 127 | (1 << AT91RM9200_ID_IRQ1)
128 | (1 << AT91_ID_IRQ2) 128 | (1 << AT91RM9200_ID_IRQ2)
129 | (1 << AT91_ID_IRQ3) 129 | (1 << AT91RM9200_ID_IRQ3)
130 | (1 << AT91_ID_IRQ4) 130 | (1 << AT91RM9200_ID_IRQ4)
131 | (1 << AT91_ID_IRQ5) 131 | (1 << AT91RM9200_ID_IRQ5)
132 | (1 << AT91_ID_IRQ6)) 132 | (1 << AT91RM9200_ID_IRQ6))
133 & at91_sys_read(AT91_AIC_IMR), 133 & at91_sys_read(AT91_AIC_IMR),
134 state); 134 state);
135 135
diff --git a/drivers/mmc/at91_mci.c b/drivers/mmc/at91_mci.c
index 6b7638b84290..4b3d4d637030 100644
--- a/drivers/mmc/at91_mci.c
+++ b/drivers/mmc/at91_mci.c
@@ -850,7 +850,7 @@ static int at91_mci_probe(struct platform_device *pdev)
850 /* 850 /*
851 * Allocate the MCI interrupt 851 * Allocate the MCI interrupt
852 */ 852 */
853 ret = request_irq(AT91_ID_MCI, at91_mci_irq, IRQF_SHARED, DRIVER_NAME, host); 853 ret = request_irq(AT91RM9200_ID_MCI, at91_mci_irq, IRQF_SHARED, DRIVER_NAME, host);
854 if (ret) { 854 if (ret) {
855 printk(KERN_ERR "Failed to request MCI interrupt\n"); 855 printk(KERN_ERR "Failed to request MCI interrupt\n");
856 clk_disable(mci_clk); 856 clk_disable(mci_clk);
@@ -906,7 +906,7 @@ static int at91_mci_remove(struct platform_device *pdev)
906 906
907 mmc_remove_host(mmc); 907 mmc_remove_host(mmc);
908 at91_mci_disable(); 908 at91_mci_disable();
909 free_irq(AT91_ID_MCI, host); 909 free_irq(AT91RM9200_ID_MCI, host);
910 mmc_free_host(mmc); 910 mmc_free_host(mmc);
911 911
912 clk_disable(mci_clk); /* Disable the peripheral clock */ 912 clk_disable(mci_clk); /* Disable the peripheral clock */
diff --git a/drivers/net/arm/at91_ether.c b/drivers/net/arm/at91_ether.c
index 95b28aa01f4f..3ecf2cc53a7c 100644
--- a/drivers/net/arm/at91_ether.c
+++ b/drivers/net/arm/at91_ether.c
@@ -947,7 +947,7 @@ static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_add
947 return -ENOMEM; 947 return -ENOMEM;
948 948
949 dev->base_addr = AT91_VA_BASE_EMAC; 949 dev->base_addr = AT91_VA_BASE_EMAC;
950 dev->irq = AT91_ID_EMAC; 950 dev->irq = AT91RM9200_ID_EMAC;
951 SET_MODULE_OWNER(dev); 951 SET_MODULE_OWNER(dev);
952 952
953 /* Install the interrupt handler */ 953 /* Install the interrupt handler */
diff --git a/drivers/serial/at91_serial.c b/drivers/serial/at91_serial.c
index 54c6b2adf7b7..bf4bf103e5a0 100644
--- a/drivers/serial/at91_serial.c
+++ b/drivers/serial/at91_serial.c
@@ -139,7 +139,7 @@ static void at91_set_mctrl(struct uart_port *port, u_int mctrl)
139 * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21. 139 * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21.
140 * We need to drive the pin manually. 140 * We need to drive the pin manually.
141 */ 141 */
142 if (port->mapbase == AT91_BASE_US0) { 142 if (port->mapbase == AT91RM9200_BASE_US0) {
143 if (mctrl & TIOCM_RTS) 143 if (mctrl & TIOCM_RTS)
144 at91_set_gpio_value(AT91_PIN_PA21, 0); 144 at91_set_gpio_value(AT91_PIN_PA21, 0);
145 else 145 else
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index cfebca05ead5..043744f1ab72 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -1658,7 +1658,7 @@ static int __devinit at91udc_probe(struct platform_device *pdev)
1658 return -ENODEV; 1658 return -ENODEV;
1659 } 1659 }
1660 1660
1661 if (!request_mem_region(AT91_BASE_UDP, SZ_16K, driver_name)) { 1661 if (!request_mem_region(AT91RM9200_BASE_UDP, SZ_16K, driver_name)) {
1662 DBG("someone's using UDC memory\n"); 1662 DBG("someone's using UDC memory\n");
1663 return -EBUSY; 1663 return -EBUSY;
1664 } 1664 }
@@ -1720,7 +1720,7 @@ static int __devinit at91udc_probe(struct platform_device *pdev)
1720fail1: 1720fail1:
1721 device_unregister(&udc->gadget.dev); 1721 device_unregister(&udc->gadget.dev);
1722fail0: 1722fail0:
1723 release_mem_region(AT91_BASE_UDP, SZ_16K); 1723 release_mem_region(AT91RM9200_BASE_UDP, SZ_16K);
1724 DBG("%s probe failed, %d\n", driver_name, retval); 1724 DBG("%s probe failed, %d\n", driver_name, retval);
1725 return retval; 1725 return retval;
1726} 1726}
@@ -1742,7 +1742,7 @@ static int __devexit at91udc_remove(struct platform_device *pdev)
1742 free_irq(udc->board.vbus_pin, udc); 1742 free_irq(udc->board.vbus_pin, udc);
1743 free_irq(udc->udp_irq, udc); 1743 free_irq(udc->udp_irq, udc);
1744 device_unregister(&udc->gadget.dev); 1744 device_unregister(&udc->gadget.dev);
1745 release_mem_region(AT91_BASE_UDP, SZ_16K); 1745 release_mem_region(AT91RM9200_BASE_UDP, SZ_16K);
1746 1746
1747 clk_put(udc->iclk); 1747 clk_put(udc->iclk);
1748 clk_put(udc->fclk); 1748 clk_put(udc->fclk);
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h
index 58f40931a5c1..a5a86b1ff886 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h
@@ -19,67 +19,80 @@
19/* 19/*
20 * Peripheral identifiers/interrupts. 20 * Peripheral identifiers/interrupts.
21 */ 21 */
22#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 22#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
23#define AT91_ID_SYS 1 /* System Peripheral */ 23#define AT91_ID_SYS 1 /* System Peripheral */
24#define AT91_ID_PIOA 2 /* Parallel IO Controller A */ 24#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
25#define AT91_ID_PIOB 3 /* Parallel IO Controller B */ 25#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
26#define AT91_ID_PIOC 4 /* Parallel IO Controller C */ 26#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
27#define AT91_ID_PIOD 5 /* Parallel IO Controller D */ 27#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */
28#define AT91_ID_US0 6 /* USART 0 */ 28#define AT91RM9200_ID_US0 6 /* USART 0 */
29#define AT91_ID_US1 7 /* USART 1 */ 29#define AT91RM9200_ID_US1 7 /* USART 1 */
30#define AT91_ID_US2 8 /* USART 2 */ 30#define AT91RM9200_ID_US2 8 /* USART 2 */
31#define AT91_ID_US3 9 /* USART 3 */ 31#define AT91RM9200_ID_US3 9 /* USART 3 */
32#define AT91_ID_MCI 10 /* Multimedia Card Interface */ 32#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */
33#define AT91_ID_UDP 11 /* USB Device Port */ 33#define AT91RM9200_ID_UDP 11 /* USB Device Port */
34#define AT91_ID_TWI 12 /* Two-Wire Interface */ 34#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */
35#define AT91_ID_SPI 13 /* Serial Peripheral Interface */ 35#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */
36#define AT91_ID_SSC0 14 /* Serial Synchronous Controller 0 */ 36#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */
37#define AT91_ID_SSC1 15 /* Serial Synchronous Controller 1 */ 37#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */
38#define AT91_ID_SSC2 16 /* Serial Synchronous Controller 2 */ 38#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */
39#define AT91_ID_TC0 17 /* Timer Counter 0 */ 39#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */
40#define AT91_ID_TC1 18 /* Timer Counter 1 */ 40#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */
41#define AT91_ID_TC2 19 /* Timer Counter 2 */ 41#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */
42#define AT91_ID_TC3 20 /* Timer Counter 3 */ 42#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */
43#define AT91_ID_TC4 21 /* Timer Counter 4 */ 43#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */
44#define AT91_ID_TC5 22 /* Timer Counter 5 */ 44#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */
45#define AT91_ID_UHP 23 /* USB Host port */ 45#define AT91RM9200_ID_UHP 23 /* USB Host port */
46#define AT91_ID_EMAC 24 /* Ethernet MAC */ 46#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */
47#define AT91_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ 47#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
48#define AT91_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ 48#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */
49#define AT91_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ 49#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */
50#define AT91_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ 50#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */
51#define AT91_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ 51#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */
52#define AT91_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ 52#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */
53#define AT91_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ 53#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */
54 54
55 55
56/* 56/*
57 * Peripheral physical base addresses. 57 * Peripheral physical base addresses.
58 */ 58 */
59#define AT91_BASE_TCB0 0xfffa0000 59#define AT91RM9200_BASE_TCB0 0xfffa0000
60#define AT91_BASE_TC0 0xfffa0000 60#define AT91RM9200_BASE_TC0 0xfffa0000
61#define AT91_BASE_TC1 0xfffa0040 61#define AT91RM9200_BASE_TC1 0xfffa0040
62#define AT91_BASE_TC2 0xfffa0080 62#define AT91RM9200_BASE_TC2 0xfffa0080
63#define AT91_BASE_TCB1 0xfffa4000 63#define AT91RM9200_BASE_TCB1 0xfffa4000
64#define AT91_BASE_TC3 0xfffa4000 64#define AT91RM9200_BASE_TC3 0xfffa4000
65#define AT91_BASE_TC4 0xfffa4040 65#define AT91RM9200_BASE_TC4 0xfffa4040
66#define AT91_BASE_TC5 0xfffa4080 66#define AT91RM9200_BASE_TC5 0xfffa4080
67#define AT91_BASE_UDP 0xfffb0000 67#define AT91RM9200_BASE_UDP 0xfffb0000
68#define AT91_BASE_MCI 0xfffb4000 68#define AT91RM9200_BASE_MCI 0xfffb4000
69#define AT91_BASE_TWI 0xfffb8000 69#define AT91RM9200_BASE_TWI 0xfffb8000
70#define AT91_BASE_EMAC 0xfffbc000 70#define AT91RM9200_BASE_EMAC 0xfffbc000
71#define AT91_BASE_US0 0xfffc0000 71#define AT91RM9200_BASE_US0 0xfffc0000
72#define AT91_BASE_US1 0xfffc4000 72#define AT91RM9200_BASE_US1 0xfffc4000
73#define AT91_BASE_US2 0xfffc8000 73#define AT91RM9200_BASE_US2 0xfffc8000
74#define AT91_BASE_US3 0xfffcc000 74#define AT91RM9200_BASE_US3 0xfffcc000
75#define AT91_BASE_SSC0 0xfffd0000 75#define AT91RM9200_BASE_SSC0 0xfffd0000
76#define AT91_BASE_SSC1 0xfffd4000 76#define AT91RM9200_BASE_SSC1 0xfffd4000
77#define AT91_BASE_SSC2 0xfffd8000 77#define AT91RM9200_BASE_SSC2 0xfffd8000
78#define AT91_BASE_SPI 0xfffe0000 78#define AT91RM9200_BASE_SPI 0xfffe0000
79#define AT91_BASE_SYS 0xfffff000 79#define AT91_BASE_SYS 0xfffff000
80 80
81 81
82/* 82/*
83 * Internal Memory.
84 */
85#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */
86#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
87
88#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */
89#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
90
91#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */
92
93
94#if 0
95/*
83 * PIO pin definitions (peripheral A/B multiplexing). 96 * PIO pin definitions (peripheral A/B multiplexing).
84 */ 97 */
85#define AT91_PA0_MISO (1 << 0) /* A: SPI Master-In Slave-Out */ 98#define AT91_PA0_MISO (1 << 0) /* A: SPI Master-In Slave-Out */
@@ -257,5 +270,6 @@
257#define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */ 270#define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */
258#define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */ 271#define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */
259#define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */ 272#define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */
273#endif
260 274
261#endif 275#endif
diff --git a/include/asm-arm/arch-at91rm9200/gpio.h b/include/asm-arm/arch-at91rm9200/gpio.h
index dbde1baaf251..6243f28a0b81 100644
--- a/include/asm-arm/arch-at91rm9200/gpio.h
+++ b/include/asm-arm/arch-at91rm9200/gpio.h
@@ -20,7 +20,7 @@
20#define PQFP_GPIO_BANKS 3 /* PQFP package has 3 banks */ 20#define PQFP_GPIO_BANKS 3 /* PQFP package has 3 banks */
21#define BGA_GPIO_BANKS 4 /* BGA package has 4 banks */ 21#define BGA_GPIO_BANKS 4 /* BGA package has 4 banks */
22 22
23/* these pin numbers double as IRQ numbers, like AT91_ID_* values */ 23/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
24 24
25#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) 25#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
26#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) 26#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
index 235d39d91107..878e65f369bf 100644
--- a/include/asm-arm/arch-at91rm9200/hardware.h
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -34,27 +34,23 @@
34 * Virtual to Physical Address mapping for IO devices. 34 * Virtual to Physical Address mapping for IO devices.
35 */ 35 */
36#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) 36#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
37#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91_BASE_SPI) 37#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91RM9200_BASE_SPI)
38#define AT91_VA_BASE_SSC2 AT91_IO_P2V(AT91_BASE_SSC2) 38#define AT91_VA_BASE_SSC2 AT91_IO_P2V(AT91RM9200_BASE_SSC2)
39#define AT91_VA_BASE_SSC1 AT91_IO_P2V(AT91_BASE_SSC1) 39#define AT91_VA_BASE_SSC1 AT91_IO_P2V(AT91RM9200_BASE_SSC1)
40#define AT91_VA_BASE_SSC0 AT91_IO_P2V(AT91_BASE_SSC0) 40#define AT91_VA_BASE_SSC0 AT91_IO_P2V(AT91RM9200_BASE_SSC0)
41#define AT91_VA_BASE_US3 AT91_IO_P2V(AT91_BASE_US3) 41#define AT91_VA_BASE_US3 AT91_IO_P2V(AT91RM9200_BASE_US3)
42#define AT91_VA_BASE_US2 AT91_IO_P2V(AT91_BASE_US2) 42#define AT91_VA_BASE_US2 AT91_IO_P2V(AT91RM9200_BASE_US2)
43#define AT91_VA_BASE_US1 AT91_IO_P2V(AT91_BASE_US1) 43#define AT91_VA_BASE_US1 AT91_IO_P2V(AT91RM9200_BASE_US1)
44#define AT91_VA_BASE_US0 AT91_IO_P2V(AT91_BASE_US0) 44#define AT91_VA_BASE_US0 AT91_IO_P2V(AT91RM9200_BASE_US0)
45#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91_BASE_EMAC) 45#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC)
46#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91_BASE_TWI) 46#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91RM9200_BASE_TWI)
47#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91_BASE_MCI) 47#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91RM9200_BASE_MCI)
48#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91_BASE_UDP) 48#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91RM9200_BASE_UDP)
49#define AT91_VA_BASE_TCB1 AT91_IO_P2V(AT91_BASE_TCB1) 49#define AT91_VA_BASE_TCB1 AT91_IO_P2V(AT91RM9200_BASE_TCB1)
50#define AT91_VA_BASE_TCB0 AT91_IO_P2V(AT91_BASE_TCB0) 50#define AT91_VA_BASE_TCB0 AT91_IO_P2V(AT91RM9200_BASE_TCB0)
51
52/* Internal SRAM */
53#define AT91_SRAM_BASE 0x00200000 /* Internal SRAM base address */
54#define AT91_SRAM_SIZE 0x00004000 /* Internal SRAM SIZE (16Kb) */
55 51
56 /* Internal SRAM is mapped below the IO devices */ 52 /* Internal SRAM is mapped below the IO devices */
57#define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_SIZE) 53#define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE)
58 54
59/* Serial ports */ 55/* Serial ports */
60#define AT91_NR_UART 5 /* 4 USART3's and one DBGU port */ 56#define AT91_NR_UART 5 /* 4 USART3's and one DBGU port */
@@ -71,9 +67,6 @@
71/* Compact Flash */ 67/* Compact Flash */
72#define AT91_CF_BASE 0x50000000 /* NCS4-NCS6: Compact Flash physical base address */ 68#define AT91_CF_BASE 0x50000000 /* NCS4-NCS6: Compact Flash physical base address */
73 69
74/* Multi-Master Memory controller */
75#define AT91_UHP_BASE 0x00300000 /* USB Host controller */
76
77/* Clocks */ 70/* Clocks */
78#define AT91_SLOW_CLOCK 32768 /* slow clock */ 71#define AT91_SLOW_CLOCK 32768 /* slow clock */
79 72
diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h
index f63842c2c093..763cb96c418b 100644
--- a/include/asm-arm/arch-at91rm9200/irqs.h
+++ b/include/asm-arm/arch-at91rm9200/irqs.h
@@ -32,7 +32,7 @@
32 32
33 33
34/* 34/*
35 * IRQ interrupt symbols are the AT91_ID_* symbols in at91rm9200.h 35 * IRQ interrupt symbols are the AT91xxx_ID_* symbols
36 * for IRQs handled directly through the AIC, or else the AT91_PIN_* 36 * for IRQs handled directly through the AIC, or else the AT91_PIN_*
37 * symbols in gpio.h for ones handled indirectly as GPIOs. 37 * symbols in gpio.h for ones handled indirectly as GPIOs.
38 * We make provision for 4 banks of GPIO. 38 * We make provision for 4 banks of GPIO.
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 21:05:49 -0500