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-rw-r--r--drivers/staging/Kconfig4
-rw-r--r--drivers/staging/Makefile2
-rw-r--r--drivers/staging/at76_usb/at76_usb.c4
-rw-r--r--drivers/staging/echo/bit_operations.h205
-rw-r--r--drivers/staging/echo/echo.c835
-rw-r--r--drivers/staging/echo/echo.h58
-rw-r--r--drivers/staging/echo/fir.h376
-rw-r--r--drivers/staging/echo/mmx.h29
-rw-r--r--drivers/staging/echo/oslec.h86
-rw-r--r--drivers/staging/et131x/et1310_phy.c2
-rw-r--r--drivers/staging/et131x/et131x_debug.c1
-rw-r--r--drivers/staging/et131x/et131x_initpci.c1
-rw-r--r--drivers/staging/go7007/go7007-driver.c1
-rw-r--r--drivers/staging/go7007/go7007-fw.c1
-rw-r--r--drivers/staging/go7007/go7007-i2c.c1
-rw-r--r--drivers/staging/go7007/go7007-usb.c1
-rw-r--r--drivers/staging/go7007/snd-go7007.c1
-rw-r--r--drivers/staging/go7007/wis-ov7640.c1
-rw-r--r--drivers/staging/go7007/wis-saa7113.c1
-rw-r--r--drivers/staging/go7007/wis-saa7115.c1
-rw-r--r--drivers/staging/go7007/wis-sony-tuner.c1
-rw-r--r--drivers/staging/go7007/wis-tw2804.c1
-rw-r--r--drivers/staging/go7007/wis-tw9903.c1
-rw-r--r--drivers/staging/go7007/wis-uda1342.c1
-rw-r--r--drivers/staging/me4000/me4000.c908
-rw-r--r--drivers/staging/me4000/me4000.h194
-rw-r--r--drivers/staging/pcc-acpi/Kconfig11
-rw-r--r--drivers/staging/pcc-acpi/Makefile1
-rw-r--r--drivers/staging/pcc-acpi/TODO7
-rw-r--r--drivers/staging/pcc-acpi/pcc-acpi.c1111
-rw-r--r--drivers/staging/poch/Kconfig6
-rw-r--r--drivers/staging/poch/Makefile1
-rw-r--r--drivers/staging/poch/README7
-rw-r--r--drivers/staging/poch/poch.c1425
-rw-r--r--drivers/staging/poch/poch.h29
-rw-r--r--drivers/staging/slicoss/slicoss.c18
-rw-r--r--drivers/staging/sxg/README1
-rw-r--r--drivers/staging/sxg/sxg.c1379
-rw-r--r--drivers/staging/sxg/sxg_os.h41
-rw-r--r--drivers/staging/sxg/sxgdbg.h2
-rw-r--r--drivers/staging/sxg/sxghif.h410
-rw-r--r--drivers/staging/sxg/sxghw.h404
-rw-r--r--drivers/staging/sxg/sxgphycode.h12
-rw-r--r--drivers/staging/usbip/usbip_common.c2
-rw-r--r--drivers/staging/usbip/vhci_rx.c2
-rw-r--r--drivers/staging/winbond/Kconfig2
-rw-r--r--drivers/staging/winbond/README1
-rw-r--r--drivers/staging/winbond/bss_f.h6
-rw-r--r--drivers/staging/winbond/ds_tkip.h6
-rw-r--r--drivers/staging/winbond/linux/common.h17
-rw-r--r--drivers/staging/winbond/linux/wb35reg.c63
-rw-r--r--drivers/staging/winbond/linux/wb35reg_f.h12
-rw-r--r--drivers/staging/winbond/linux/wb35reg_s.h4
-rw-r--r--drivers/staging/winbond/linux/wb35rx.c175
-rw-r--r--drivers/staging/winbond/linux/wb35rx_s.h2
-rw-r--r--drivers/staging/winbond/linux/wb35tx.c138
-rw-r--r--drivers/staging/winbond/linux/wb35tx_f.h2
-rw-r--r--drivers/staging/winbond/linux/wbusb.c259
-rw-r--r--drivers/staging/winbond/mds.c30
-rw-r--r--drivers/staging/winbond/mds_f.h6
-rw-r--r--drivers/staging/winbond/mds_s.h8
-rw-r--r--drivers/staging/winbond/mlme_s.h4
-rw-r--r--drivers/staging/winbond/mlmetxrx.c4
-rw-r--r--drivers/staging/winbond/mlmetxrx_f.h4
-rw-r--r--drivers/staging/winbond/reg.c24
-rw-r--r--drivers/staging/winbond/sme_api.c1
-rw-r--r--drivers/staging/winbond/sme_api.h2
-rw-r--r--drivers/staging/winbond/wbhal.c32
-rw-r--r--drivers/staging/winbond/wbhal_f.h28
-rw-r--r--drivers/staging/winbond/wbhal_s.h4
-rw-r--r--drivers/staging/winbond/wblinux.c208
-rw-r--r--drivers/staging/winbond/wblinux_s.h4
-rw-r--r--drivers/staging/wlan-ng/Kconfig2
-rw-r--r--drivers/staging/wlan-ng/hfa384x.h2
-rw-r--r--drivers/staging/wlan-ng/p80211wep.c1
-rw-r--r--drivers/staging/wlan-ng/prism2mib.c2
-rw-r--r--drivers/staging/wlan-ng/wlan_compat.h8
77 files changed, 5560 insertions, 3087 deletions
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 2a79decd7dfc..c4eff44c9f27 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -43,4 +43,8 @@ source "drivers/staging/echo/Kconfig"
43 43
44source "drivers/staging/at76_usb/Kconfig" 44source "drivers/staging/at76_usb/Kconfig"
45 45
46source "drivers/staging/pcc-acpi/Kconfig"
47
48source "drivers/staging/poch/Kconfig"
49
46endif # STAGING 50endif # STAGING
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index 325bca4f71c0..7cb8701d96d4 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -13,3 +13,5 @@ obj-$(CONFIG_W35UND) += winbond/
13obj-$(CONFIG_PRISM2_USB) += wlan-ng/ 13obj-$(CONFIG_PRISM2_USB) += wlan-ng/
14obj-$(CONFIG_ECHO) += echo/ 14obj-$(CONFIG_ECHO) += echo/
15obj-$(CONFIG_USB_ATMEL) += at76_usb/ 15obj-$(CONFIG_USB_ATMEL) += at76_usb/
16obj-$(CONFIG_PCC_ACPI) += pcc-acpi/
17obj-$(CONFIG_POCH) += poch/
diff --git a/drivers/staging/at76_usb/at76_usb.c b/drivers/staging/at76_usb/at76_usb.c
index 52df0c665183..174e2bec9223 100644
--- a/drivers/staging/at76_usb/at76_usb.c
+++ b/drivers/staging/at76_usb/at76_usb.c
@@ -2319,9 +2319,11 @@ static int at76_iw_handler_get_scan(struct net_device *netdev,
2319 if (!iwe) 2319 if (!iwe)
2320 return -ENOMEM; 2320 return -ENOMEM;
2321 2321
2322 if (priv->scan_state != SCAN_COMPLETED) 2322 if (priv->scan_state != SCAN_COMPLETED) {
2323 /* scan not yet finished */ 2323 /* scan not yet finished */
2324 kfree(iwe);
2324 return -EAGAIN; 2325 return -EAGAIN;
2326 }
2325 2327
2326 spin_lock_irqsave(&priv->bss_list_spinlock, flags); 2328 spin_lock_irqsave(&priv->bss_list_spinlock, flags);
2327 2329
diff --git a/drivers/staging/echo/bit_operations.h b/drivers/staging/echo/bit_operations.h
index b32f4bf99397..cecdcf3fd755 100644
--- a/drivers/staging/echo/bit_operations.h
+++ b/drivers/staging/echo/bit_operations.h
@@ -30,114 +30,98 @@
30#if !defined(_BIT_OPERATIONS_H_) 30#if !defined(_BIT_OPERATIONS_H_)
31#define _BIT_OPERATIONS_H_ 31#define _BIT_OPERATIONS_H_
32 32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
37#if defined(__i386__) || defined(__x86_64__) 33#if defined(__i386__) || defined(__x86_64__)
38/*! \brief Find the bit position of the highest set bit in a word 34/*! \brief Find the bit position of the highest set bit in a word
39 \param bits The word to be searched 35 \param bits The word to be searched
40 \return The bit number of the highest set bit, or -1 if the word is zero. */ 36 \return The bit number of the highest set bit, or -1 if the word is zero. */
41static __inline__ int top_bit(unsigned int bits) 37static __inline__ int top_bit(unsigned int bits)
42{ 38{
43 int res; 39 int res;
44 40
45 __asm__ (" xorl %[res],%[res];\n" 41 __asm__(" xorl %[res],%[res];\n"
46 " decl %[res];\n" 42 " decl %[res];\n"
47 " bsrl %[bits],%[res]\n" 43 " bsrl %[bits],%[res]\n"
48 : [res] "=&r" (res) 44 :[res] "=&r" (res)
49 : [bits] "rm" (bits)); 45 :[bits] "rm"(bits)
50 return res; 46 );
47 return res;
51} 48}
52/*- End of function --------------------------------------------------------*/
53 49
54/*! \brief Find the bit position of the lowest set bit in a word 50/*! \brief Find the bit position of the lowest set bit in a word
55 \param bits The word to be searched 51 \param bits The word to be searched
56 \return The bit number of the lowest set bit, or -1 if the word is zero. */ 52 \return The bit number of the lowest set bit, or -1 if the word is zero. */
57static __inline__ int bottom_bit(unsigned int bits) 53static __inline__ int bottom_bit(unsigned int bits)
58{ 54{
59 int res; 55 int res;
60 56
61 __asm__ (" xorl %[res],%[res];\n" 57 __asm__(" xorl %[res],%[res];\n"
62 " decl %[res];\n" 58 " decl %[res];\n"
63 " bsfl %[bits],%[res]\n" 59 " bsfl %[bits],%[res]\n"
64 : [res] "=&r" (res) 60 :[res] "=&r" (res)
65 : [bits] "rm" (bits)); 61 :[bits] "rm"(bits)
66 return res; 62 );
63 return res;
67} 64}
68/*- End of function --------------------------------------------------------*/
69#else 65#else
70static __inline__ int top_bit(unsigned int bits) 66static __inline__ int top_bit(unsigned int bits)
71{ 67{
72 int i; 68 int i;
73 69
74 if (bits == 0) 70 if (bits == 0)
75 return -1; 71 return -1;
76 i = 0; 72 i = 0;
77 if (bits & 0xFFFF0000) 73 if (bits & 0xFFFF0000) {
78 { 74 bits &= 0xFFFF0000;
79 bits &= 0xFFFF0000; 75 i += 16;
80 i += 16; 76 }
81 } 77 if (bits & 0xFF00FF00) {
82 if (bits & 0xFF00FF00) 78 bits &= 0xFF00FF00;
83 { 79 i += 8;
84 bits &= 0xFF00FF00; 80 }
85 i += 8; 81 if (bits & 0xF0F0F0F0) {
86 } 82 bits &= 0xF0F0F0F0;
87 if (bits & 0xF0F0F0F0) 83 i += 4;
88 { 84 }
89 bits &= 0xF0F0F0F0; 85 if (bits & 0xCCCCCCCC) {
90 i += 4; 86 bits &= 0xCCCCCCCC;
91 } 87 i += 2;
92 if (bits & 0xCCCCCCCC) 88 }
93 { 89 if (bits & 0xAAAAAAAA) {
94 bits &= 0xCCCCCCCC; 90 bits &= 0xAAAAAAAA;
95 i += 2; 91 i += 1;
96 } 92 }
97 if (bits & 0xAAAAAAAA) 93 return i;
98 {
99 bits &= 0xAAAAAAAA;
100 i += 1;
101 }
102 return i;
103} 94}
104/*- End of function --------------------------------------------------------*/
105 95
106static __inline__ int bottom_bit(unsigned int bits) 96static __inline__ int bottom_bit(unsigned int bits)
107{ 97{
108 int i; 98 int i;
109 99
110 if (bits == 0) 100 if (bits == 0)
111 return -1; 101 return -1;
112 i = 32; 102 i = 32;
113 if (bits & 0x0000FFFF) 103 if (bits & 0x0000FFFF) {
114 { 104 bits &= 0x0000FFFF;
115 bits &= 0x0000FFFF; 105 i -= 16;
116 i -= 16; 106 }
117 } 107 if (bits & 0x00FF00FF) {
118 if (bits & 0x00FF00FF) 108 bits &= 0x00FF00FF;
119 { 109 i -= 8;
120 bits &= 0x00FF00FF; 110 }
121 i -= 8; 111 if (bits & 0x0F0F0F0F) {
122 } 112 bits &= 0x0F0F0F0F;
123 if (bits & 0x0F0F0F0F) 113 i -= 4;
124 { 114 }
125 bits &= 0x0F0F0F0F; 115 if (bits & 0x33333333) {
126 i -= 4; 116 bits &= 0x33333333;
127 } 117 i -= 2;
128 if (bits & 0x33333333) 118 }
129 { 119 if (bits & 0x55555555) {
130 bits &= 0x33333333; 120 bits &= 0x55555555;
131 i -= 2; 121 i -= 1;
132 } 122 }
133 if (bits & 0x55555555) 123 return i;
134 {
135 bits &= 0x55555555;
136 i -= 1;
137 }
138 return i;
139} 124}
140/*- End of function --------------------------------------------------------*/
141#endif 125#endif
142 126
143/*! \brief Bit reverse a byte. 127/*! \brief Bit reverse a byte.
@@ -146,16 +130,16 @@ static __inline__ int bottom_bit(unsigned int bits)
146static __inline__ uint8_t bit_reverse8(uint8_t x) 130static __inline__ uint8_t bit_reverse8(uint8_t x)
147{ 131{
148#if defined(__i386__) || defined(__x86_64__) 132#if defined(__i386__) || defined(__x86_64__)
149 /* If multiply is fast */ 133 /* If multiply is fast */
150 return ((x*0x0802U & 0x22110U) | (x*0x8020U & 0x88440U))*0x10101U >> 16; 134 return ((x * 0x0802U & 0x22110U) | (x * 0x8020U & 0x88440U)) *
135 0x10101U >> 16;
151#else 136#else
152 /* If multiply is slow, but we have a barrel shifter */ 137 /* If multiply is slow, but we have a barrel shifter */
153 x = (x >> 4) | (x << 4); 138 x = (x >> 4) | (x << 4);
154 x = ((x & 0xCC) >> 2) | ((x & 0x33) << 2); 139 x = ((x & 0xCC) >> 2) | ((x & 0x33) << 2);
155 return ((x & 0xAA) >> 1) | ((x & 0x55) << 1); 140 return ((x & 0xAA) >> 1) | ((x & 0x55) << 1);
156#endif 141#endif
157} 142}
158/*- End of function --------------------------------------------------------*/
159 143
160/*! \brief Bit reverse a 16 bit word. 144/*! \brief Bit reverse a 16 bit word.
161 \param data The word to be reversed. 145 \param data The word to be reversed.
@@ -193,9 +177,8 @@ uint16_t make_mask16(uint16_t x);
193 \return The word with the single set bit. */ 177 \return The word with the single set bit. */
194static __inline__ uint32_t least_significant_one32(uint32_t x) 178static __inline__ uint32_t least_significant_one32(uint32_t x)
195{ 179{
196 return (x & (-(int32_t) x)); 180 return (x & (-(int32_t) x));
197} 181}
198/*- End of function --------------------------------------------------------*/
199 182
200/*! \brief Find the most significant one in a word, and return a word 183/*! \brief Find the most significant one in a word, and return a word
201 with just that bit set. 184 with just that bit set.
@@ -204,50 +187,42 @@ static __inline__ uint32_t least_significant_one32(uint32_t x)
204static __inline__ uint32_t most_significant_one32(uint32_t x) 187static __inline__ uint32_t most_significant_one32(uint32_t x)
205{ 188{
206#if defined(__i386__) || defined(__x86_64__) 189#if defined(__i386__) || defined(__x86_64__)
207 return 1 << top_bit(x); 190 return 1 << top_bit(x);
208#else 191#else
209 x = make_mask32(x); 192 x = make_mask32(x);
210 return (x ^ (x >> 1)); 193 return (x ^ (x >> 1));
211#endif 194#endif
212} 195}
213/*- End of function --------------------------------------------------------*/
214 196
215/*! \brief Find the parity of a byte. 197/*! \brief Find the parity of a byte.
216 \param x The byte to be checked. 198 \param x The byte to be checked.
217 \return 1 for odd, or 0 for even. */ 199 \return 1 for odd, or 0 for even. */
218static __inline__ int parity8(uint8_t x) 200static __inline__ int parity8(uint8_t x)
219{ 201{
220 x = (x ^ (x >> 4)) & 0x0F; 202 x = (x ^ (x >> 4)) & 0x0F;
221 return (0x6996 >> x) & 1; 203 return (0x6996 >> x) & 1;
222} 204}
223/*- End of function --------------------------------------------------------*/
224 205
225/*! \brief Find the parity of a 16 bit word. 206/*! \brief Find the parity of a 16 bit word.
226 \param x The word to be checked. 207 \param x The word to be checked.
227 \return 1 for odd, or 0 for even. */ 208 \return 1 for odd, or 0 for even. */
228static __inline__ int parity16(uint16_t x) 209static __inline__ int parity16(uint16_t x)
229{ 210{
230 x ^= (x >> 8); 211 x ^= (x >> 8);
231 x = (x ^ (x >> 4)) & 0x0F; 212 x = (x ^ (x >> 4)) & 0x0F;
232 return (0x6996 >> x) & 1; 213 return (0x6996 >> x) & 1;
233} 214}
234/*- End of function --------------------------------------------------------*/
235 215
236/*! \brief Find the parity of a 32 bit word. 216/*! \brief Find the parity of a 32 bit word.
237 \param x The word to be checked. 217 \param x The word to be checked.
238 \return 1 for odd, or 0 for even. */ 218 \return 1 for odd, or 0 for even. */
239static __inline__ int parity32(uint32_t x) 219static __inline__ int parity32(uint32_t x)
240{ 220{
241 x ^= (x >> 16); 221 x ^= (x >> 16);
242 x ^= (x >> 8); 222 x ^= (x >> 8);
243 x = (x ^ (x >> 4)) & 0x0F; 223 x = (x ^ (x >> 4)) & 0x0F;
244 return (0x6996 >> x) & 1; 224 return (0x6996 >> x) & 1;
245} 225}
246/*- End of function --------------------------------------------------------*/
247
248#ifdef __cplusplus
249}
250#endif
251 226
252#endif 227#endif
253/*- End of file ------------------------------------------------------------*/ 228/*- End of file ------------------------------------------------------------*/
diff --git a/drivers/staging/echo/echo.c b/drivers/staging/echo/echo.c
index 4a281b14fc58..b8f2c5e9dee5 100644
--- a/drivers/staging/echo/echo.c
+++ b/drivers/staging/echo/echo.c
@@ -74,7 +74,6 @@
74 74
75 Steve also has some nice notes on echo cancellers in echo.h 75 Steve also has some nice notes on echo cancellers in echo.h
76 76
77
78 References: 77 References:
79 78
80 [1] Ochiai, Areseki, and Ogihara, "Echo Canceller with Two Echo 79 [1] Ochiai, Areseki, and Ogihara, "Echo Canceller with Two Echo
@@ -105,20 +104,18 @@
105 Mark, Pawel, and Pavel. 104 Mark, Pawel, and Pavel.
106*/ 105*/
107 106
108#include <linux/kernel.h> /* We're doing kernel work */ 107#include <linux/kernel.h> /* We're doing kernel work */
109#include <linux/module.h> 108#include <linux/module.h>
110#include <linux/kernel.h> 109#include <linux/kernel.h>
111#include <linux/slab.h> 110#include <linux/slab.h>
112#define malloc(a) kmalloc((a), GFP_KERNEL)
113#define free(a) kfree(a)
114 111
115#include "bit_operations.h" 112#include "bit_operations.h"
116#include "echo.h" 113#include "echo.h"
117 114
118#define MIN_TX_POWER_FOR_ADAPTION 64 115#define MIN_TX_POWER_FOR_ADAPTION 64
119#define MIN_RX_POWER_FOR_ADAPTION 64 116#define MIN_RX_POWER_FOR_ADAPTION 64
120#define DTD_HANGOVER 600 /* 600 samples, or 75ms */ 117#define DTD_HANGOVER 600 /* 600 samples, or 75ms */
121#define DC_LOG2BETA 3 /* log2() of DC filter Beta */ 118#define DC_LOG2BETA 3 /* log2() of DC filter Beta */
122 119
123/*-----------------------------------------------------------------------*\ 120/*-----------------------------------------------------------------------*\
124 FUNCTIONS 121 FUNCTIONS
@@ -126,59 +123,58 @@
126 123
127/* adapting coeffs using the traditional stochastic descent (N)LMS algorithm */ 124/* adapting coeffs using the traditional stochastic descent (N)LMS algorithm */
128 125
129 126#ifdef __bfin__
130#ifdef __BLACKFIN_ASM__ 127static void __inline__ lms_adapt_bg(struct oslec_state *ec, int clean,
131static void __inline__ lms_adapt_bg(echo_can_state_t *ec, int clean, int shift) 128 int shift)
132{ 129{
133 int i, j; 130 int i, j;
134 int offset1; 131 int offset1;
135 int offset2; 132 int offset2;
136 int factor; 133 int factor;
137 int exp; 134 int exp;
138 int16_t *phist; 135 int16_t *phist;
139 int n; 136 int n;
140 137
141 if (shift > 0) 138 if (shift > 0)
142 factor = clean << shift; 139 factor = clean << shift;
143 else 140 else
144 factor = clean >> -shift; 141 factor = clean >> -shift;
145 142
146 /* Update the FIR taps */ 143 /* Update the FIR taps */
147 144
148 offset2 = ec->curr_pos; 145 offset2 = ec->curr_pos;
149 offset1 = ec->taps - offset2; 146 offset1 = ec->taps - offset2;
150 phist = &ec->fir_state_bg.history[offset2]; 147 phist = &ec->fir_state_bg.history[offset2];
151 148
152 /* st: and en: help us locate the assembler in echo.s */ 149 /* st: and en: help us locate the assembler in echo.s */
153 150
154 //asm("st:"); 151 //asm("st:");
155 n = ec->taps; 152 n = ec->taps;
156 for (i = 0, j = offset2; i < n; i++, j++) 153 for (i = 0, j = offset2; i < n; i++, j++) {
157 { 154 exp = *phist++ * factor;
158 exp = *phist++ * factor; 155 ec->fir_taps16[1][i] += (int16_t) ((exp + (1 << 14)) >> 15);
159 ec->fir_taps16[1][i] += (int16_t) ((exp+(1<<14)) >> 15); 156 }
160 } 157 //asm("en:");
161 //asm("en:"); 158
162 159 /* Note the asm for the inner loop above generated by Blackfin gcc
163 /* Note the asm for the inner loop above generated by Blackfin gcc 160 4.1.1 is pretty good (note even parallel instructions used):
164 4.1.1 is pretty good (note even parallel instructions used): 161
165 162 R0 = W [P0++] (X);
166 R0 = W [P0++] (X); 163 R0 *= R2;
167 R0 *= R2; 164 R0 = R0 + R3 (NS) ||
168 R0 = R0 + R3 (NS) || 165 R1 = W [P1] (X) ||
169 R1 = W [P1] (X) || 166 nop;
170 nop; 167 R0 >>>= 15;
171 R0 >>>= 15; 168 R0 = R0 + R1;
172 R0 = R0 + R1; 169 W [P1++] = R0;
173 W [P1++] = R0; 170
174 171 A block based update algorithm would be much faster but the
175 A block based update algorithm would be much faster but the 172 above can't be improved on much. Every instruction saved in
176 above can't be improved on much. Every instruction saved in 173 the loop above is 2 MIPs/ch! The for loop above is where the
177 the loop above is 2 MIPs/ch! The for loop above is where the 174 Blackfin spends most of it's time - about 17 MIPs/ch measured
178 Blackfin spends most of it's time - about 17 MIPs/ch measured 175 with speedtest.c with 256 taps (32ms). Write-back and
179 with speedtest.c with 256 taps (32ms). Write-back and 176 Write-through cache gave about the same performance.
180 Write-through cache gave about the same performance. 177 */
181 */
182} 178}
183 179
184/* 180/*
@@ -200,392 +196,393 @@ static void __inline__ lms_adapt_bg(echo_can_state_t *ec, int clean, int shift)
200*/ 196*/
201 197
202#else 198#else
203static __inline__ void lms_adapt_bg(echo_can_state_t *ec, int clean, int shift) 199static __inline__ void lms_adapt_bg(struct oslec_state *ec, int clean,
200 int shift)
204{ 201{
205 int i; 202 int i;
206 203
207 int offset1; 204 int offset1;
208 int offset2; 205 int offset2;
209 int factor; 206 int factor;
210 int exp; 207 int exp;
211 208
212 if (shift > 0) 209 if (shift > 0)
213 factor = clean << shift; 210 factor = clean << shift;
214 else 211 else
215 factor = clean >> -shift; 212 factor = clean >> -shift;
216 213
217 /* Update the FIR taps */ 214 /* Update the FIR taps */
218 215
219 offset2 = ec->curr_pos; 216 offset2 = ec->curr_pos;
220 offset1 = ec->taps - offset2; 217 offset1 = ec->taps - offset2;
221 218
222 for (i = ec->taps - 1; i >= offset1; i--) 219 for (i = ec->taps - 1; i >= offset1; i--) {
223 { 220 exp = (ec->fir_state_bg.history[i - offset1] * factor);
224 exp = (ec->fir_state_bg.history[i - offset1]*factor); 221 ec->fir_taps16[1][i] += (int16_t) ((exp + (1 << 14)) >> 15);
225 ec->fir_taps16[1][i] += (int16_t) ((exp+(1<<14)) >> 15); 222 }
226 } 223 for (; i >= 0; i--) {
227 for ( ; i >= 0; i--) 224 exp = (ec->fir_state_bg.history[i + offset2] * factor);
228 { 225 ec->fir_taps16[1][i] += (int16_t) ((exp + (1 << 14)) >> 15);
229 exp = (ec->fir_state_bg.history[i + offset2]*factor); 226 }
230 ec->fir_taps16[1][i] += (int16_t) ((exp+(1<<14)) >> 15);
231 }
232} 227}
233#endif 228#endif
234 229
235/*- End of function --------------------------------------------------------*/ 230struct oslec_state *oslec_create(int len, int adaption_mode)
236
237echo_can_state_t *echo_can_create(int len, int adaption_mode)
238{ 231{
239 echo_can_state_t *ec; 232 struct oslec_state *ec;
240 int i; 233 int i;
241 int j; 234
242 235 ec = kzalloc(sizeof(*ec), GFP_KERNEL);
243 ec = kmalloc(sizeof(*ec), GFP_KERNEL); 236 if (!ec)
244 if (ec == NULL) 237 return NULL;
245 return NULL; 238
246 memset(ec, 0, sizeof(*ec)); 239 ec->taps = len;
247 240 ec->log2taps = top_bit(len);
248 ec->taps = len; 241 ec->curr_pos = ec->taps - 1;
249 ec->log2taps = top_bit(len); 242
250 ec->curr_pos = ec->taps - 1; 243 for (i = 0; i < 2; i++) {
251 244 ec->fir_taps16[i] =
252 for (i = 0; i < 2; i++) 245 kcalloc(ec->taps, sizeof(int16_t), GFP_KERNEL);
253 { 246 if (!ec->fir_taps16[i])
254 if ((ec->fir_taps16[i] = (int16_t *) malloc((ec->taps)*sizeof(int16_t))) == NULL) 247 goto error_oom;
255 { 248 }
256 for (j = 0; j < i; j++) 249
257 kfree(ec->fir_taps16[j]); 250 fir16_create(&ec->fir_state, ec->fir_taps16[0], ec->taps);
258 kfree(ec); 251 fir16_create(&ec->fir_state_bg, ec->fir_taps16[1], ec->taps);
259 return NULL; 252
260 } 253 for (i = 0; i < 5; i++) {
261 memset(ec->fir_taps16[i], 0, (ec->taps)*sizeof(int16_t)); 254 ec->xvtx[i] = ec->yvtx[i] = ec->xvrx[i] = ec->yvrx[i] = 0;
262 } 255 }
263 256
264 fir16_create(&ec->fir_state, 257 ec->cng_level = 1000;
265 ec->fir_taps16[0], 258 oslec_adaption_mode(ec, adaption_mode);
266 ec->taps); 259
267 fir16_create(&ec->fir_state_bg, 260 ec->snapshot = kcalloc(ec->taps, sizeof(int16_t), GFP_KERNEL);
268 ec->fir_taps16[1], 261 if (!ec->snapshot)
269 ec->taps); 262 goto error_oom;
270 263
271 for(i=0; i<5; i++) { 264 ec->cond_met = 0;
272 ec->xvtx[i] = ec->yvtx[i] = ec->xvrx[i] = ec->yvrx[i] = 0; 265 ec->Pstates = 0;
273 } 266 ec->Ltxacc = ec->Lrxacc = ec->Lcleanacc = ec->Lclean_bgacc = 0;
274 267 ec->Ltx = ec->Lrx = ec->Lclean = ec->Lclean_bg = 0;
275 ec->cng_level = 1000; 268 ec->tx_1 = ec->tx_2 = ec->rx_1 = ec->rx_2 = 0;
276 echo_can_adaption_mode(ec, adaption_mode); 269 ec->Lbgn = ec->Lbgn_acc = 0;
277 270 ec->Lbgn_upper = 200;
278 ec->snapshot = (int16_t*)malloc(ec->taps*sizeof(int16_t)); 271 ec->Lbgn_upper_acc = ec->Lbgn_upper << 13;
279 memset(ec->snapshot, 0, sizeof(int16_t)*ec->taps); 272
280 273 return ec;
281 ec->cond_met = 0; 274
282 ec->Pstates = 0; 275 error_oom:
283 ec->Ltxacc = ec->Lrxacc = ec->Lcleanacc = ec->Lclean_bgacc = 0; 276 for (i = 0; i < 2; i++)
284 ec->Ltx = ec->Lrx = ec->Lclean = ec->Lclean_bg = 0; 277 kfree(ec->fir_taps16[i]);
285 ec->tx_1 = ec->tx_2 = ec->rx_1 = ec->rx_2 = 0; 278
286 ec->Lbgn = ec->Lbgn_acc = 0; 279 kfree(ec);
287 ec->Lbgn_upper = 200; 280 return NULL;
288 ec->Lbgn_upper_acc = ec->Lbgn_upper << 13;
289
290 return ec;
291} 281}
292/*- End of function --------------------------------------------------------*/
293 282
294void echo_can_free(echo_can_state_t *ec) 283EXPORT_SYMBOL_GPL(oslec_create);
284
285void oslec_free(struct oslec_state *ec)
295{ 286{
296 int i; 287 int i;
297 288
298 fir16_free(&ec->fir_state); 289 fir16_free(&ec->fir_state);
299 fir16_free(&ec->fir_state_bg); 290 fir16_free(&ec->fir_state_bg);
300 for (i = 0; i < 2; i++) 291 for (i = 0; i < 2; i++)
301 kfree(ec->fir_taps16[i]); 292 kfree(ec->fir_taps16[i]);
302 kfree(ec->snapshot); 293 kfree(ec->snapshot);
303 kfree(ec); 294 kfree(ec);
304} 295}
305/*- End of function --------------------------------------------------------*/
306 296
307void echo_can_adaption_mode(echo_can_state_t *ec, int adaption_mode) 297EXPORT_SYMBOL_GPL(oslec_free);
298
299void oslec_adaption_mode(struct oslec_state *ec, int adaption_mode)
308{ 300{
309 ec->adaption_mode = adaption_mode; 301 ec->adaption_mode = adaption_mode;
310} 302}
311/*- End of function --------------------------------------------------------*/
312 303
313void echo_can_flush(echo_can_state_t *ec) 304EXPORT_SYMBOL_GPL(oslec_adaption_mode);
305
306void oslec_flush(struct oslec_state *ec)
314{ 307{
315 int i; 308 int i;
316 309
317 ec->Ltxacc = ec->Lrxacc = ec->Lcleanacc = ec->Lclean_bgacc = 0; 310 ec->Ltxacc = ec->Lrxacc = ec->Lcleanacc = ec->Lclean_bgacc = 0;
318 ec->Ltx = ec->Lrx = ec->Lclean = ec->Lclean_bg = 0; 311 ec->Ltx = ec->Lrx = ec->Lclean = ec->Lclean_bg = 0;
319 ec->tx_1 = ec->tx_2 = ec->rx_1 = ec->rx_2 = 0; 312 ec->tx_1 = ec->tx_2 = ec->rx_1 = ec->rx_2 = 0;
320 313
321 ec->Lbgn = ec->Lbgn_acc = 0; 314 ec->Lbgn = ec->Lbgn_acc = 0;
322 ec->Lbgn_upper = 200; 315 ec->Lbgn_upper = 200;
323 ec->Lbgn_upper_acc = ec->Lbgn_upper << 13; 316 ec->Lbgn_upper_acc = ec->Lbgn_upper << 13;
324 317
325 ec->nonupdate_dwell = 0; 318 ec->nonupdate_dwell = 0;
326 319
327 fir16_flush(&ec->fir_state); 320 fir16_flush(&ec->fir_state);
328 fir16_flush(&ec->fir_state_bg); 321 fir16_flush(&ec->fir_state_bg);
329 ec->fir_state.curr_pos = ec->taps - 1; 322 ec->fir_state.curr_pos = ec->taps - 1;
330 ec->fir_state_bg.curr_pos = ec->taps - 1; 323 ec->fir_state_bg.curr_pos = ec->taps - 1;
331 for (i = 0; i < 2; i++) 324 for (i = 0; i < 2; i++)
332 memset(ec->fir_taps16[i], 0, ec->taps*sizeof(int16_t)); 325 memset(ec->fir_taps16[i], 0, ec->taps * sizeof(int16_t));
333 326
334 ec->curr_pos = ec->taps - 1; 327 ec->curr_pos = ec->taps - 1;
335 ec->Pstates = 0; 328 ec->Pstates = 0;
336} 329}
337/*- End of function --------------------------------------------------------*/
338 330
339void echo_can_snapshot(echo_can_state_t *ec) { 331EXPORT_SYMBOL_GPL(oslec_flush);
340 memcpy(ec->snapshot, ec->fir_taps16[0], ec->taps*sizeof(int16_t)); 332
333void oslec_snapshot(struct oslec_state *ec)
334{
335 memcpy(ec->snapshot, ec->fir_taps16[0], ec->taps * sizeof(int16_t));
341} 336}
342/*- End of function --------------------------------------------------------*/ 337
338EXPORT_SYMBOL_GPL(oslec_snapshot);
343 339
344/* Dual Path Echo Canceller ------------------------------------------------*/ 340/* Dual Path Echo Canceller ------------------------------------------------*/
345 341
346int16_t echo_can_update(echo_can_state_t *ec, int16_t tx, int16_t rx) 342int16_t oslec_update(struct oslec_state *ec, int16_t tx, int16_t rx)
347{ 343{
348 int32_t echo_value; 344 int32_t echo_value;
349 int clean_bg; 345 int clean_bg;
350 int tmp, tmp1; 346 int tmp, tmp1;
351 347
352 /* Input scaling was found be required to prevent problems when tx 348 /* Input scaling was found be required to prevent problems when tx
353 starts clipping. Another possible way to handle this would be the 349 starts clipping. Another possible way to handle this would be the
354 filter coefficent scaling. */ 350 filter coefficent scaling. */
355 351
356 ec->tx = tx; ec->rx = rx; 352 ec->tx = tx;
357 tx >>=1; 353 ec->rx = rx;
358 rx >>=1; 354 tx >>= 1;
359 355 rx >>= 1;
360 /* 356
361 Filter DC, 3dB point is 160Hz (I think), note 32 bit precision required 357 /*
362 otherwise values do not track down to 0. Zero at DC, Pole at (1-Beta) 358 Filter DC, 3dB point is 160Hz (I think), note 32 bit precision required
363 only real axis. Some chip sets (like Si labs) don't need 359 otherwise values do not track down to 0. Zero at DC, Pole at (1-Beta)
364 this, but something like a $10 X100P card does. Any DC really slows 360 only real axis. Some chip sets (like Si labs) don't need
365 down convergence. 361 this, but something like a $10 X100P card does. Any DC really slows
366 362 down convergence.
367 Note: removes some low frequency from the signal, this reduces 363
368 the speech quality when listening to samples through headphones 364 Note: removes some low frequency from the signal, this reduces
369 but may not be obvious through a telephone handset. 365 the speech quality when listening to samples through headphones
370 366 but may not be obvious through a telephone handset.
371 Note that the 3dB frequency in radians is approx Beta, e.g. for 367
372 Beta = 2^(-3) = 0.125, 3dB freq is 0.125 rads = 159Hz. 368 Note that the 3dB frequency in radians is approx Beta, e.g. for
373 */ 369 Beta = 2^(-3) = 0.125, 3dB freq is 0.125 rads = 159Hz.
374 370 */
375 if (ec->adaption_mode & ECHO_CAN_USE_RX_HPF) { 371
376 tmp = rx << 15; 372 if (ec->adaption_mode & ECHO_CAN_USE_RX_HPF) {
373 tmp = rx << 15;
377#if 1 374#if 1
378 /* Make sure the gain of the HPF is 1.0. This can still saturate a little under 375 /* Make sure the gain of the HPF is 1.0. This can still saturate a little under
379 impulse conditions, and it might roll to 32768 and need clipping on sustained peak 376 impulse conditions, and it might roll to 32768 and need clipping on sustained peak
380 level signals. However, the scale of such clipping is small, and the error due to 377 level signals. However, the scale of such clipping is small, and the error due to
381 any saturation should not markedly affect the downstream processing. */ 378 any saturation should not markedly affect the downstream processing. */
382 tmp -= (tmp >> 4); 379 tmp -= (tmp >> 4);
383#endif 380#endif
384 ec->rx_1 += -(ec->rx_1>>DC_LOG2BETA) + tmp - ec->rx_2; 381 ec->rx_1 += -(ec->rx_1 >> DC_LOG2BETA) + tmp - ec->rx_2;
382
383 /* hard limit filter to prevent clipping. Note that at this stage
384 rx should be limited to +/- 16383 due to right shift above */
385 tmp1 = ec->rx_1 >> 15;
386 if (tmp1 > 16383)
387 tmp1 = 16383;
388 if (tmp1 < -16383)
389 tmp1 = -16383;
390 rx = tmp1;
391 ec->rx_2 = tmp;
392 }
385 393
386 /* hard limit filter to prevent clipping. Note that at this stage 394 /* Block average of power in the filter states. Used for
387 rx should be limited to +/- 16383 due to right shift above */ 395 adaption power calculation. */
388 tmp1 = ec->rx_1 >> 15;
389 if (tmp1 > 16383) tmp1 = 16383;
390 if (tmp1 < -16383) tmp1 = -16383;
391 rx = tmp1;
392 ec->rx_2 = tmp;
393 }
394 396
395 /* Block average of power in the filter states. Used for 397 {
396 adaption power calculation. */ 398 int new, old;
399
400 /* efficient "out with the old and in with the new" algorithm so
401 we don't have to recalculate over the whole block of
402 samples. */
403 new = (int)tx *(int)tx;
404 old = (int)ec->fir_state.history[ec->fir_state.curr_pos] *
405 (int)ec->fir_state.history[ec->fir_state.curr_pos];
406 ec->Pstates +=
407 ((new - old) + (1 << ec->log2taps)) >> ec->log2taps;
408 if (ec->Pstates < 0)
409 ec->Pstates = 0;
410 }
397 411
398 { 412 /* Calculate short term average levels using simple single pole IIRs */
399 int new, old;
400 413
401 /* efficient "out with the old and in with the new" algorithm so 414 ec->Ltxacc += abs(tx) - ec->Ltx;
402 we don't have to recalculate over the whole block of 415 ec->Ltx = (ec->Ltxacc + (1 << 4)) >> 5;
403 samples. */ 416 ec->Lrxacc += abs(rx) - ec->Lrx;
404 new = (int)tx * (int)tx; 417 ec->Lrx = (ec->Lrxacc + (1 << 4)) >> 5;
405 old = (int)ec->fir_state.history[ec->fir_state.curr_pos] *
406 (int)ec->fir_state.history[ec->fir_state.curr_pos];
407 ec->Pstates += ((new - old) + (1<<ec->log2taps)) >> ec->log2taps;
408 if (ec->Pstates < 0) ec->Pstates = 0;
409 }
410
411 /* Calculate short term average levels using simple single pole IIRs */
412
413 ec->Ltxacc += abs(tx) - ec->Ltx;
414 ec->Ltx = (ec->Ltxacc + (1<<4)) >> 5;
415 ec->Lrxacc += abs(rx) - ec->Lrx;
416 ec->Lrx = (ec->Lrxacc + (1<<4)) >> 5;
417
418 /* Foreground filter ---------------------------------------------------*/
419
420 ec->fir_state.coeffs = ec->fir_taps16[0];
421 echo_value = fir16(&ec->fir_state, tx);
422 ec->clean = rx - echo_value;
423 ec->Lcleanacc += abs(ec->clean) - ec->Lclean;
424 ec->Lclean = (ec->Lcleanacc + (1<<4)) >> 5;
425
426 /* Background filter ---------------------------------------------------*/
427
428 echo_value = fir16(&ec->fir_state_bg, tx);
429 clean_bg = rx - echo_value;
430 ec->Lclean_bgacc += abs(clean_bg) - ec->Lclean_bg;
431 ec->Lclean_bg = (ec->Lclean_bgacc + (1<<4)) >> 5;
432
433 /* Background Filter adaption -----------------------------------------*/
434
435 /* Almost always adap bg filter, just simple DT and energy
436 detection to minimise adaption in cases of strong double talk.
437 However this is not critical for the dual path algorithm.
438 */
439 ec->factor = 0;
440 ec->shift = 0;
441 if ((ec->nonupdate_dwell == 0)) {
442 int P, logP, shift;
443
444 /* Determine:
445
446 f = Beta * clean_bg_rx/P ------ (1)
447
448 where P is the total power in the filter states.
449
450 The Boffins have shown that if we obey (1) we converge
451 quickly and avoid instability.
452
453 The correct factor f must be in Q30, as this is the fixed
454 point format required by the lms_adapt_bg() function,
455 therefore the scaled version of (1) is:
456
457 (2^30) * f = (2^30) * Beta * clean_bg_rx/P
458 factor = (2^30) * Beta * clean_bg_rx/P ----- (2)
459
460 We have chosen Beta = 0.25 by experiment, so:
461
462 factor = (2^30) * (2^-2) * clean_bg_rx/P
463
464 (30 - 2 - log2(P))
465 factor = clean_bg_rx 2 ----- (3)
466
467 To avoid a divide we approximate log2(P) as top_bit(P),
468 which returns the position of the highest non-zero bit in
469 P. This approximation introduces an error as large as a
470 factor of 2, but the algorithm seems to handle it OK.
471
472 Come to think of it a divide may not be a big deal on a
473 modern DSP, so its probably worth checking out the cycles
474 for a divide versus a top_bit() implementation.
475 */
476
477 P = MIN_TX_POWER_FOR_ADAPTION + ec->Pstates;
478 logP = top_bit(P) + ec->log2taps;
479 shift = 30 - 2 - logP;
480 ec->shift = shift;
481
482 lms_adapt_bg(ec, clean_bg, shift);
483 }
484
485 /* very simple DTD to make sure we dont try and adapt with strong
486 near end speech */
487
488 ec->adapt = 0;
489 if ((ec->Lrx > MIN_RX_POWER_FOR_ADAPTION) && (ec->Lrx > ec->Ltx))
490 ec->nonupdate_dwell = DTD_HANGOVER;
491 if (ec->nonupdate_dwell)
492 ec->nonupdate_dwell--;
493 418
494 /* Transfer logic ------------------------------------------------------*/ 419 /* Foreground filter --------------------------------------------------- */
495 420
496 /* These conditions are from the dual path paper [1], I messed with 421 ec->fir_state.coeffs = ec->fir_taps16[0];
497 them a bit to improve performance. */ 422 echo_value = fir16(&ec->fir_state, tx);
423 ec->clean = rx - echo_value;
424 ec->Lcleanacc += abs(ec->clean) - ec->Lclean;
425 ec->Lclean = (ec->Lcleanacc + (1 << 4)) >> 5;
498 426
499 if ((ec->adaption_mode & ECHO_CAN_USE_ADAPTION) && 427 /* Background filter --------------------------------------------------- */
500 (ec->nonupdate_dwell == 0) &&
501 (8*ec->Lclean_bg < 7*ec->Lclean) /* (ec->Lclean_bg < 0.875*ec->Lclean) */ &&
502 (8*ec->Lclean_bg < ec->Ltx) /* (ec->Lclean_bg < 0.125*ec->Ltx) */ )
503 {
504 if (ec->cond_met == 6) {
505 /* BG filter has had better results for 6 consecutive samples */
506 ec->adapt = 1;
507 memcpy(ec->fir_taps16[0], ec->fir_taps16[1], ec->taps*sizeof(int16_t));
508 }
509 else
510 ec->cond_met++;
511 }
512 else
513 ec->cond_met = 0;
514 428
515 /* Non-Linear Processing ---------------------------------------------------*/ 429 echo_value = fir16(&ec->fir_state_bg, tx);
430 clean_bg = rx - echo_value;
431 ec->Lclean_bgacc += abs(clean_bg) - ec->Lclean_bg;
432 ec->Lclean_bg = (ec->Lclean_bgacc + (1 << 4)) >> 5;
516 433
517 ec->clean_nlp = ec->clean; 434 /* Background Filter adaption ----------------------------------------- */
518 if (ec->adaption_mode & ECHO_CAN_USE_NLP)
519 {
520 /* Non-linear processor - a fancy way to say "zap small signals, to avoid
521 residual echo due to (uLaw/ALaw) non-linearity in the channel.". */
522 435
523 if ((16*ec->Lclean < ec->Ltx)) 436 /* Almost always adap bg filter, just simple DT and energy
524 { 437 detection to minimise adaption in cases of strong double talk.
525 /* Our e/c has improved echo by at least 24 dB (each factor of 2 is 6dB, 438 However this is not critical for the dual path algorithm.
526 so 2*2*2*2=16 is the same as 6+6+6+6=24dB) */ 439 */
527 if (ec->adaption_mode & ECHO_CAN_USE_CNG) 440 ec->factor = 0;
528 { 441 ec->shift = 0;
529 ec->cng_level = ec->Lbgn; 442 if ((ec->nonupdate_dwell == 0)) {
530 443 int P, logP, shift;
531 /* Very elementary comfort noise generation. Just random 444
532 numbers rolled off very vaguely Hoth-like. DR: This 445 /* Determine:
533 noise doesn't sound quite right to me - I suspect there 446
534 are some overlfow issues in the filtering as it's too 447 f = Beta * clean_bg_rx/P ------ (1)
535 "crackly". TODO: debug this, maybe just play noise at 448
536 high level or look at spectrum. 449 where P is the total power in the filter states.
537 */ 450
538 451 The Boffins have shown that if we obey (1) we converge
539 ec->cng_rndnum = 1664525U*ec->cng_rndnum + 1013904223U; 452 quickly and avoid instability.
540 ec->cng_filter = ((ec->cng_rndnum & 0xFFFF) - 32768 + 5*ec->cng_filter) >> 3; 453
541 ec->clean_nlp = (ec->cng_filter*ec->cng_level*8) >> 14; 454 The correct factor f must be in Q30, as this is the fixed
542 455 point format required by the lms_adapt_bg() function,
543 } 456 therefore the scaled version of (1) is:
544 else if (ec->adaption_mode & ECHO_CAN_USE_CLIP) 457
545 { 458 (2^30) * f = (2^30) * Beta * clean_bg_rx/P
546 /* This sounds much better than CNG */ 459 factor = (2^30) * Beta * clean_bg_rx/P ----- (2)
547 if (ec->clean_nlp > ec->Lbgn) 460
548 ec->clean_nlp = ec->Lbgn; 461 We have chosen Beta = 0.25 by experiment, so:
549 if (ec->clean_nlp < -ec->Lbgn) 462
550 ec->clean_nlp = -ec->Lbgn; 463 factor = (2^30) * (2^-2) * clean_bg_rx/P
464
465 (30 - 2 - log2(P))
466 factor = clean_bg_rx 2 ----- (3)
467
468 To avoid a divide we approximate log2(P) as top_bit(P),
469 which returns the position of the highest non-zero bit in
470 P. This approximation introduces an error as large as a
471 factor of 2, but the algorithm seems to handle it OK.
472
473 Come to think of it a divide may not be a big deal on a
474 modern DSP, so its probably worth checking out the cycles
475 for a divide versus a top_bit() implementation.
476 */
477
478 P = MIN_TX_POWER_FOR_ADAPTION + ec->Pstates;
479 logP = top_bit(P) + ec->log2taps;
480 shift = 30 - 2 - logP;
481 ec->shift = shift;
482
483 lms_adapt_bg(ec, clean_bg, shift);
551 } 484 }
552 else 485
553 { 486 /* very simple DTD to make sure we dont try and adapt with strong
554 /* just mute the residual, doesn't sound very good, used mainly 487 near end speech */
555 in G168 tests */ 488
556 ec->clean_nlp = 0; 489 ec->adapt = 0;
557 } 490 if ((ec->Lrx > MIN_RX_POWER_FOR_ADAPTION) && (ec->Lrx > ec->Ltx))
558 } 491 ec->nonupdate_dwell = DTD_HANGOVER;
559 else { 492 if (ec->nonupdate_dwell)
560 /* Background noise estimator. I tried a few algorithms 493 ec->nonupdate_dwell--;
561 here without much luck. This very simple one seems to 494
562 work best, we just average the level using a slow (1 sec 495 /* Transfer logic ------------------------------------------------------ */
563 time const) filter if the current level is less than a 496
564 (experimentally derived) constant. This means we dont 497 /* These conditions are from the dual path paper [1], I messed with
565 include high level signals like near end speech. When 498 them a bit to improve performance. */
566 combined with CNG or especially CLIP seems to work OK. 499
567 */ 500 if ((ec->adaption_mode & ECHO_CAN_USE_ADAPTION) &&
568 if (ec->Lclean < 40) { 501 (ec->nonupdate_dwell == 0) &&
569 ec->Lbgn_acc += abs(ec->clean) - ec->Lbgn; 502 (8 * ec->Lclean_bg <
570 ec->Lbgn = (ec->Lbgn_acc + (1<<11)) >> 12; 503 7 * ec->Lclean) /* (ec->Lclean_bg < 0.875*ec->Lclean) */ &&
571 } 504 (8 * ec->Lclean_bg <
572 } 505 ec->Ltx) /* (ec->Lclean_bg < 0.125*ec->Ltx) */ ) {
573 } 506 if (ec->cond_met == 6) {
574 507 /* BG filter has had better results for 6 consecutive samples */
575 /* Roll around the taps buffer */ 508 ec->adapt = 1;
576 if (ec->curr_pos <= 0) 509 memcpy(ec->fir_taps16[0], ec->fir_taps16[1],
577 ec->curr_pos = ec->taps; 510 ec->taps * sizeof(int16_t));
578 ec->curr_pos--; 511 } else
579 512 ec->cond_met++;
580 if (ec->adaption_mode & ECHO_CAN_DISABLE) 513 } else
581 ec->clean_nlp = rx; 514 ec->cond_met = 0;
582 515
583 /* Output scaled back up again to match input scaling */ 516 /* Non-Linear Processing --------------------------------------------------- */
584 517
585 return (int16_t) ec->clean_nlp << 1; 518 ec->clean_nlp = ec->clean;
519 if (ec->adaption_mode & ECHO_CAN_USE_NLP) {
520 /* Non-linear processor - a fancy way to say "zap small signals, to avoid
521 residual echo due to (uLaw/ALaw) non-linearity in the channel.". */
522
523 if ((16 * ec->Lclean < ec->Ltx)) {
524 /* Our e/c has improved echo by at least 24 dB (each factor of 2 is 6dB,
525 so 2*2*2*2=16 is the same as 6+6+6+6=24dB) */
526 if (ec->adaption_mode & ECHO_CAN_USE_CNG) {
527 ec->cng_level = ec->Lbgn;
528
529 /* Very elementary comfort noise generation. Just random
530 numbers rolled off very vaguely Hoth-like. DR: This
531 noise doesn't sound quite right to me - I suspect there
532 are some overlfow issues in the filtering as it's too
533 "crackly". TODO: debug this, maybe just play noise at
534 high level or look at spectrum.
535 */
536
537 ec->cng_rndnum =
538 1664525U * ec->cng_rndnum + 1013904223U;
539 ec->cng_filter =
540 ((ec->cng_rndnum & 0xFFFF) - 32768 +
541 5 * ec->cng_filter) >> 3;
542 ec->clean_nlp =
543 (ec->cng_filter * ec->cng_level * 8) >> 14;
544
545 } else if (ec->adaption_mode & ECHO_CAN_USE_CLIP) {
546 /* This sounds much better than CNG */
547 if (ec->clean_nlp > ec->Lbgn)
548 ec->clean_nlp = ec->Lbgn;
549 if (ec->clean_nlp < -ec->Lbgn)
550 ec->clean_nlp = -ec->Lbgn;
551 } else {
552 /* just mute the residual, doesn't sound very good, used mainly
553 in G168 tests */
554 ec->clean_nlp = 0;
555 }
556 } else {
557 /* Background noise estimator. I tried a few algorithms
558 here without much luck. This very simple one seems to
559 work best, we just average the level using a slow (1 sec
560 time const) filter if the current level is less than a
561 (experimentally derived) constant. This means we dont
562 include high level signals like near end speech. When
563 combined with CNG or especially CLIP seems to work OK.
564 */
565 if (ec->Lclean < 40) {
566 ec->Lbgn_acc += abs(ec->clean) - ec->Lbgn;
567 ec->Lbgn = (ec->Lbgn_acc + (1 << 11)) >> 12;
568 }
569 }
570 }
571
572 /* Roll around the taps buffer */
573 if (ec->curr_pos <= 0)
574 ec->curr_pos = ec->taps;
575 ec->curr_pos--;
576
577 if (ec->adaption_mode & ECHO_CAN_DISABLE)
578 ec->clean_nlp = rx;
579
580 /* Output scaled back up again to match input scaling */
581
582 return (int16_t) ec->clean_nlp << 1;
586} 583}
587 584
588/*- End of function --------------------------------------------------------*/ 585EXPORT_SYMBOL_GPL(oslec_update);
589 586
590/* This function is seperated from the echo canceller is it is usually called 587/* This function is seperated from the echo canceller is it is usually called
591 as part of the tx process. See rx HP (DC blocking) filter above, it's 588 as part of the tx process. See rx HP (DC blocking) filter above, it's
@@ -608,25 +605,35 @@ int16_t echo_can_update(echo_can_state_t *ec, int16_t tx, int16_t rx)
608 precision, which noise shapes things, giving very clean DC removal. 605 precision, which noise shapes things, giving very clean DC removal.
609*/ 606*/
610 607
611int16_t echo_can_hpf_tx(echo_can_state_t *ec, int16_t tx) { 608int16_t oslec_hpf_tx(struct oslec_state * ec, int16_t tx)
612 int tmp, tmp1; 609{
610 int tmp, tmp1;
613 611
614 if (ec->adaption_mode & ECHO_CAN_USE_TX_HPF) { 612 if (ec->adaption_mode & ECHO_CAN_USE_TX_HPF) {
615 tmp = tx << 15; 613 tmp = tx << 15;
616#if 1 614#if 1
617 /* Make sure the gain of the HPF is 1.0. The first can still saturate a little under 615 /* Make sure the gain of the HPF is 1.0. The first can still saturate a little under
618 impulse conditions, and it might roll to 32768 and need clipping on sustained peak 616 impulse conditions, and it might roll to 32768 and need clipping on sustained peak
619 level signals. However, the scale of such clipping is small, and the error due to 617 level signals. However, the scale of such clipping is small, and the error due to
620 any saturation should not markedly affect the downstream processing. */ 618 any saturation should not markedly affect the downstream processing. */
621 tmp -= (tmp >> 4); 619 tmp -= (tmp >> 4);
622#endif 620#endif
623 ec->tx_1 += -(ec->tx_1>>DC_LOG2BETA) + tmp - ec->tx_2; 621 ec->tx_1 += -(ec->tx_1 >> DC_LOG2BETA) + tmp - ec->tx_2;
624 tmp1 = ec->tx_1 >> 15; 622 tmp1 = ec->tx_1 >> 15;
625 if (tmp1 > 32767) tmp1 = 32767; 623 if (tmp1 > 32767)
626 if (tmp1 < -32767) tmp1 = -32767; 624 tmp1 = 32767;
627 tx = tmp1; 625 if (tmp1 < -32767)
628 ec->tx_2 = tmp; 626 tmp1 = -32767;
629 } 627 tx = tmp1;
630 628 ec->tx_2 = tmp;
631 return tx; 629 }
630
631 return tx;
632} 632}
633
634EXPORT_SYMBOL_GPL(oslec_hpf_tx);
635
636MODULE_LICENSE("GPL");
637MODULE_AUTHOR("David Rowe");
638MODULE_DESCRIPTION("Open Source Line Echo Canceller");
639MODULE_VERSION("0.3.0");
diff --git a/drivers/staging/echo/echo.h b/drivers/staging/echo/echo.h
index 7a91b4390f3b..9fb9543c4f13 100644
--- a/drivers/staging/echo/echo.h
+++ b/drivers/staging/echo/echo.h
@@ -118,23 +118,14 @@ a minor burden.
118*/ 118*/
119 119
120#include "fir.h" 120#include "fir.h"
121 121#include "oslec.h"
122/* Mask bits for the adaption mode */
123#define ECHO_CAN_USE_ADAPTION 0x01
124#define ECHO_CAN_USE_NLP 0x02
125#define ECHO_CAN_USE_CNG 0x04
126#define ECHO_CAN_USE_CLIP 0x08
127#define ECHO_CAN_USE_TX_HPF 0x10
128#define ECHO_CAN_USE_RX_HPF 0x20
129#define ECHO_CAN_DISABLE 0x40
130 122
131/*! 123/*!
132 G.168 echo canceller descriptor. This defines the working state for a line 124 G.168 echo canceller descriptor. This defines the working state for a line
133 echo canceller. 125 echo canceller.
134*/ 126*/
135typedef struct 127struct oslec_state {
136{ 128 int16_t tx, rx;
137 int16_t tx,rx;
138 int16_t clean; 129 int16_t clean;
139 int16_t clean_nlp; 130 int16_t clean_nlp;
140 131
@@ -176,45 +167,6 @@ typedef struct
176 167
177 /* snapshot sample of coeffs used for development */ 168 /* snapshot sample of coeffs used for development */
178 int16_t *snapshot; 169 int16_t *snapshot;
179} echo_can_state_t; 170};
180
181/*! Create a voice echo canceller context.
182 \param len The length of the canceller, in samples.
183 \return The new canceller context, or NULL if the canceller could not be created.
184*/
185echo_can_state_t *echo_can_create(int len, int adaption_mode);
186
187/*! Free a voice echo canceller context.
188 \param ec The echo canceller context.
189*/
190void echo_can_free(echo_can_state_t *ec);
191
192/*! Flush (reinitialise) a voice echo canceller context.
193 \param ec The echo canceller context.
194*/
195void echo_can_flush(echo_can_state_t *ec);
196
197/*! Set the adaption mode of a voice echo canceller context.
198 \param ec The echo canceller context.
199 \param adapt The mode.
200*/
201void echo_can_adaption_mode(echo_can_state_t *ec, int adaption_mode);
202
203void echo_can_snapshot(echo_can_state_t *ec);
204
205/*! Process a sample through a voice echo canceller.
206 \param ec The echo canceller context.
207 \param tx The transmitted audio sample.
208 \param rx The received audio sample.
209 \return The clean (echo cancelled) received sample.
210*/
211int16_t echo_can_update(echo_can_state_t *ec, int16_t tx, int16_t rx);
212
213/*! Process to high pass filter the tx signal.
214 \param ec The echo canceller context.
215 \param tx The transmitted auio sample.
216 \return The HP filtered transmit sample, send this to your D/A.
217*/
218int16_t echo_can_hpf_tx(echo_can_state_t *ec, int16_t tx);
219 171
220#endif /* __ECHO_H */ 172#endif /* __ECHO_H */
diff --git a/drivers/staging/echo/fir.h b/drivers/staging/echo/fir.h
index e1bfc4994886..5645cb1b2f90 100644
--- a/drivers/staging/echo/fir.h
+++ b/drivers/staging/echo/fir.h
@@ -72,8 +72,7 @@
72 16 bit integer FIR descriptor. This defines the working state for a single 72 16 bit integer FIR descriptor. This defines the working state for a single
73 instance of an FIR filter using 16 bit integer coefficients. 73 instance of an FIR filter using 16 bit integer coefficients.
74*/ 74*/
75typedef struct 75typedef struct {
76{
77 int taps; 76 int taps;
78 int curr_pos; 77 int curr_pos;
79 const int16_t *coeffs; 78 const int16_t *coeffs;
@@ -85,8 +84,7 @@ typedef struct
85 instance of an FIR filter using 32 bit integer coefficients, and filtering 84 instance of an FIR filter using 32 bit integer coefficients, and filtering
86 16 bit integer data. 85 16 bit integer data.
87*/ 86*/
88typedef struct 87typedef struct {
89{
90 int taps; 88 int taps;
91 int curr_pos; 89 int curr_pos;
92 const int32_t *coeffs; 90 const int32_t *coeffs;
@@ -97,273 +95,201 @@ typedef struct
97 Floating point FIR descriptor. This defines the working state for a single 95 Floating point FIR descriptor. This defines the working state for a single
98 instance of an FIR filter using floating point coefficients and data. 96 instance of an FIR filter using floating point coefficients and data.
99*/ 97*/
100typedef struct 98typedef struct {
101{
102 int taps; 99 int taps;
103 int curr_pos; 100 int curr_pos;
104 const float *coeffs; 101 const float *coeffs;
105 float *history; 102 float *history;
106} fir_float_state_t; 103} fir_float_state_t;
107 104
108#ifdef __cplusplus 105static __inline__ const int16_t *fir16_create(fir16_state_t * fir,
109extern "C" { 106 const int16_t * coeffs, int taps)
110#endif
111
112static __inline__ const int16_t *fir16_create(fir16_state_t *fir,
113 const int16_t *coeffs,
114 int taps)
115{ 107{
116 fir->taps = taps; 108 fir->taps = taps;
117 fir->curr_pos = taps - 1; 109 fir->curr_pos = taps - 1;
118 fir->coeffs = coeffs; 110 fir->coeffs = coeffs;
119#if defined(USE_MMX) || defined(USE_SSE2) || defined(__BLACKFIN_ASM__) 111#if defined(USE_MMX) || defined(USE_SSE2) || defined(__bfin__)
120 if ((fir->history = malloc(2*taps*sizeof(int16_t)))) 112 fir->history = kcalloc(2 * taps, sizeof(int16_t), GFP_KERNEL);
121 memset(fir->history, 0, 2*taps*sizeof(int16_t));
122#else 113#else
123 if ((fir->history = (int16_t *) malloc(taps*sizeof(int16_t)))) 114 fir->history = kcalloc(taps, sizeof(int16_t), GFP_KERNEL);
124 memset(fir->history, 0, taps*sizeof(int16_t));
125#endif 115#endif
126 return fir->history; 116 return fir->history;
127} 117}
128/*- End of function --------------------------------------------------------*/
129 118
130static __inline__ void fir16_flush(fir16_state_t *fir) 119static __inline__ void fir16_flush(fir16_state_t * fir)
131{ 120{
132#if defined(USE_MMX) || defined(USE_SSE2) || defined(__BLACKFIN_ASM__) 121#if defined(USE_MMX) || defined(USE_SSE2) || defined(__bfin__)
133 memset(fir->history, 0, 2*fir->taps*sizeof(int16_t)); 122 memset(fir->history, 0, 2 * fir->taps * sizeof(int16_t));
134#else 123#else
135 memset(fir->history, 0, fir->taps*sizeof(int16_t)); 124 memset(fir->history, 0, fir->taps * sizeof(int16_t));
136#endif 125#endif
137} 126}
138/*- End of function --------------------------------------------------------*/
139 127
140static __inline__ void fir16_free(fir16_state_t *fir) 128static __inline__ void fir16_free(fir16_state_t * fir)
141{ 129{
142 free(fir->history); 130 kfree(fir->history);
143} 131}
144/*- End of function --------------------------------------------------------*/
145 132
146#ifdef __BLACKFIN_ASM__ 133#ifdef __bfin__
147static inline int32_t dot_asm(short *x, short *y, int len) 134static inline int32_t dot_asm(short *x, short *y, int len)
148{ 135{
149 int dot; 136 int dot;
150 137
151 len--; 138 len--;
152 139
153 __asm__ 140 __asm__("I0 = %1;\n\t"
154 ( 141 "I1 = %2;\n\t"
155 "I0 = %1;\n\t" 142 "A0 = 0;\n\t"
156 "I1 = %2;\n\t" 143 "R0.L = W[I0++] || R1.L = W[I1++];\n\t"
157 "A0 = 0;\n\t" 144 "LOOP dot%= LC0 = %3;\n\t"
158 "R0.L = W[I0++] || R1.L = W[I1++];\n\t" 145 "LOOP_BEGIN dot%=;\n\t"
159 "LOOP dot%= LC0 = %3;\n\t" 146 "A0 += R0.L * R1.L (IS) || R0.L = W[I0++] || R1.L = W[I1++];\n\t"
160 "LOOP_BEGIN dot%=;\n\t" 147 "LOOP_END dot%=;\n\t"
161 "A0 += R0.L * R1.L (IS) || R0.L = W[I0++] || R1.L = W[I1++];\n\t" 148 "A0 += R0.L*R1.L (IS);\n\t"
162 "LOOP_END dot%=;\n\t" 149 "R0 = A0;\n\t"
163 "A0 += R0.L*R1.L (IS);\n\t" 150 "%0 = R0;\n\t"
164 "R0 = A0;\n\t" 151 :"=&d"(dot)
165 "%0 = R0;\n\t" 152 :"a"(x), "a"(y), "a"(len)
166 : "=&d" (dot) 153 :"I0", "I1", "A1", "A0", "R0", "R1"
167 : "a" (x), "a" (y), "a" (len) 154 );
168 : "I0", "I1", "A1", "A0", "R0", "R1" 155
169 ); 156 return dot;
170
171 return dot;
172} 157}
173#endif 158#endif
174/*- End of function --------------------------------------------------------*/
175 159
176static __inline__ int16_t fir16(fir16_state_t *fir, int16_t sample) 160static __inline__ int16_t fir16(fir16_state_t * fir, int16_t sample)
177{ 161{
178 int32_t y; 162 int32_t y;
179#if defined(USE_MMX) 163#if defined(USE_MMX)
180 int i; 164 int i;
181 mmx_t *mmx_coeffs; 165 mmx_t *mmx_coeffs;
182 mmx_t *mmx_hist; 166 mmx_t *mmx_hist;
183 167
184 fir->history[fir->curr_pos] = sample; 168 fir->history[fir->curr_pos] = sample;
185 fir->history[fir->curr_pos + fir->taps] = sample; 169 fir->history[fir->curr_pos + fir->taps] = sample;
186 170
187 mmx_coeffs = (mmx_t *) fir->coeffs; 171 mmx_coeffs = (mmx_t *) fir->coeffs;
188 mmx_hist = (mmx_t *) &fir->history[fir->curr_pos]; 172 mmx_hist = (mmx_t *) & fir->history[fir->curr_pos];
189 i = fir->taps; 173 i = fir->taps;
190 pxor_r2r(mm4, mm4); 174 pxor_r2r(mm4, mm4);
191 /* 8 samples per iteration, so the filter must be a multiple of 8 long. */ 175 /* 8 samples per iteration, so the filter must be a multiple of 8 long. */
192 while (i > 0) 176 while (i > 0) {
193 { 177 movq_m2r(mmx_coeffs[0], mm0);
194 movq_m2r(mmx_coeffs[0], mm0); 178 movq_m2r(mmx_coeffs[1], mm2);
195 movq_m2r(mmx_coeffs[1], mm2); 179 movq_m2r(mmx_hist[0], mm1);
196 movq_m2r(mmx_hist[0], mm1); 180 movq_m2r(mmx_hist[1], mm3);
197 movq_m2r(mmx_hist[1], mm3); 181 mmx_coeffs += 2;
198 mmx_coeffs += 2; 182 mmx_hist += 2;
199 mmx_hist += 2; 183 pmaddwd_r2r(mm1, mm0);
200 pmaddwd_r2r(mm1, mm0); 184 pmaddwd_r2r(mm3, mm2);
201 pmaddwd_r2r(mm3, mm2); 185 paddd_r2r(mm0, mm4);
202 paddd_r2r(mm0, mm4); 186 paddd_r2r(mm2, mm4);
203 paddd_r2r(mm2, mm4); 187 i -= 8;
204 i -= 8; 188 }
205 } 189 movq_r2r(mm4, mm0);
206 movq_r2r(mm4, mm0); 190 psrlq_i2r(32, mm0);
207 psrlq_i2r(32, mm0); 191 paddd_r2r(mm0, mm4);
208 paddd_r2r(mm0, mm4); 192 movd_r2m(mm4, y);
209 movd_r2m(mm4, y); 193 emms();
210 emms();
211#elif defined(USE_SSE2) 194#elif defined(USE_SSE2)
212 int i; 195 int i;
213 xmm_t *xmm_coeffs; 196 xmm_t *xmm_coeffs;
214 xmm_t *xmm_hist; 197 xmm_t *xmm_hist;
215 198
216 fir->history[fir->curr_pos] = sample; 199 fir->history[fir->curr_pos] = sample;
217 fir->history[fir->curr_pos + fir->taps] = sample; 200 fir->history[fir->curr_pos + fir->taps] = sample;
218 201
219 xmm_coeffs = (xmm_t *) fir->coeffs; 202 xmm_coeffs = (xmm_t *) fir->coeffs;
220 xmm_hist = (xmm_t *) &fir->history[fir->curr_pos]; 203 xmm_hist = (xmm_t *) & fir->history[fir->curr_pos];
221 i = fir->taps; 204 i = fir->taps;
222 pxor_r2r(xmm4, xmm4); 205 pxor_r2r(xmm4, xmm4);
223 /* 16 samples per iteration, so the filter must be a multiple of 16 long. */ 206 /* 16 samples per iteration, so the filter must be a multiple of 16 long. */
224 while (i > 0) 207 while (i > 0) {
225 { 208 movdqu_m2r(xmm_coeffs[0], xmm0);
226 movdqu_m2r(xmm_coeffs[0], xmm0); 209 movdqu_m2r(xmm_coeffs[1], xmm2);
227 movdqu_m2r(xmm_coeffs[1], xmm2); 210 movdqu_m2r(xmm_hist[0], xmm1);
228 movdqu_m2r(xmm_hist[0], xmm1); 211 movdqu_m2r(xmm_hist[1], xmm3);
229 movdqu_m2r(xmm_hist[1], xmm3); 212 xmm_coeffs += 2;
230 xmm_coeffs += 2; 213 xmm_hist += 2;
231 xmm_hist += 2; 214 pmaddwd_r2r(xmm1, xmm0);
232 pmaddwd_r2r(xmm1, xmm0); 215 pmaddwd_r2r(xmm3, xmm2);
233 pmaddwd_r2r(xmm3, xmm2); 216 paddd_r2r(xmm0, xmm4);
234 paddd_r2r(xmm0, xmm4); 217 paddd_r2r(xmm2, xmm4);
235 paddd_r2r(xmm2, xmm4); 218 i -= 16;
236 i -= 16; 219 }
237 } 220 movdqa_r2r(xmm4, xmm0);
238 movdqa_r2r(xmm4, xmm0); 221 psrldq_i2r(8, xmm0);
239 psrldq_i2r(8, xmm0); 222 paddd_r2r(xmm0, xmm4);
240 paddd_r2r(xmm0, xmm4); 223 movdqa_r2r(xmm4, xmm0);
241 movdqa_r2r(xmm4, xmm0); 224 psrldq_i2r(4, xmm0);
242 psrldq_i2r(4, xmm0); 225 paddd_r2r(xmm0, xmm4);
243 paddd_r2r(xmm0, xmm4); 226 movd_r2m(xmm4, y);
244 movd_r2m(xmm4, y); 227#elif defined(__bfin__)
245#elif defined(__BLACKFIN_ASM__) 228 fir->history[fir->curr_pos] = sample;
246 fir->history[fir->curr_pos] = sample; 229 fir->history[fir->curr_pos + fir->taps] = sample;
247 fir->history[fir->curr_pos + fir->taps] = sample; 230 y = dot_asm((int16_t *) fir->coeffs, &fir->history[fir->curr_pos],
248 y = dot_asm((int16_t*)fir->coeffs, &fir->history[fir->curr_pos], fir->taps); 231 fir->taps);
249#else 232#else
250 int i; 233 int i;
251 int offset1; 234 int offset1;
252 int offset2; 235 int offset2;
253 236
254 fir->history[fir->curr_pos] = sample; 237 fir->history[fir->curr_pos] = sample;
255 238
256 offset2 = fir->curr_pos; 239 offset2 = fir->curr_pos;
257 offset1 = fir->taps - offset2; 240 offset1 = fir->taps - offset2;
258 y = 0; 241 y = 0;
259 for (i = fir->taps - 1; i >= offset1; i--) 242 for (i = fir->taps - 1; i >= offset1; i--)
260 y += fir->coeffs[i]*fir->history[i - offset1]; 243 y += fir->coeffs[i] * fir->history[i - offset1];
261 for ( ; i >= 0; i--) 244 for (; i >= 0; i--)
262 y += fir->coeffs[i]*fir->history[i + offset2]; 245 y += fir->coeffs[i] * fir->history[i + offset2];
263#endif 246#endif
264 if (fir->curr_pos <= 0) 247 if (fir->curr_pos <= 0)
265 fir->curr_pos = fir->taps; 248 fir->curr_pos = fir->taps;
266 fir->curr_pos--; 249 fir->curr_pos--;
267 return (int16_t) (y >> 15); 250 return (int16_t) (y >> 15);
268}
269/*- End of function --------------------------------------------------------*/
270
271static __inline__ const int16_t *fir32_create(fir32_state_t *fir,
272 const int32_t *coeffs,
273 int taps)
274{
275 fir->taps = taps;
276 fir->curr_pos = taps - 1;
277 fir->coeffs = coeffs;
278 fir->history = (int16_t *) malloc(taps*sizeof(int16_t));
279 if (fir->history)
280 memset(fir->history, '\0', taps*sizeof(int16_t));
281 return fir->history;
282}
283/*- End of function --------------------------------------------------------*/
284
285static __inline__ void fir32_flush(fir32_state_t *fir)
286{
287 memset(fir->history, 0, fir->taps*sizeof(int16_t));
288} 251}
289/*- End of function --------------------------------------------------------*/
290 252
291static __inline__ void fir32_free(fir32_state_t *fir) 253static __inline__ const int16_t *fir32_create(fir32_state_t * fir,
254 const int32_t * coeffs, int taps)
292{ 255{
293 free(fir->history); 256 fir->taps = taps;
294} 257 fir->curr_pos = taps - 1;
295/*- End of function --------------------------------------------------------*/ 258 fir->coeffs = coeffs;
296 259 fir->history = kcalloc(taps, sizeof(int16_t), GFP_KERNEL);
297static __inline__ int16_t fir32(fir32_state_t *fir, int16_t sample) 260 return fir->history;
298{
299 int i;
300 int32_t y;
301 int offset1;
302 int offset2;
303
304 fir->history[fir->curr_pos] = sample;
305 offset2 = fir->curr_pos;
306 offset1 = fir->taps - offset2;
307 y = 0;
308 for (i = fir->taps - 1; i >= offset1; i--)
309 y += fir->coeffs[i]*fir->history[i - offset1];
310 for ( ; i >= 0; i--)
311 y += fir->coeffs[i]*fir->history[i + offset2];
312 if (fir->curr_pos <= 0)
313 fir->curr_pos = fir->taps;
314 fir->curr_pos--;
315 return (int16_t) (y >> 15);
316} 261}
317/*- End of function --------------------------------------------------------*/
318 262
319#ifndef __KERNEL__ 263static __inline__ void fir32_flush(fir32_state_t * fir)
320static __inline__ const float *fir_float_create(fir_float_state_t *fir,
321 const float *coeffs,
322 int taps)
323{ 264{
324 fir->taps = taps; 265 memset(fir->history, 0, fir->taps * sizeof(int16_t));
325 fir->curr_pos = taps - 1;
326 fir->coeffs = coeffs;
327 fir->history = (float *) malloc(taps*sizeof(float));
328 if (fir->history)
329 memset(fir->history, '\0', taps*sizeof(float));
330 return fir->history;
331} 266}
332/*- End of function --------------------------------------------------------*/
333 267
334static __inline__ void fir_float_free(fir_float_state_t *fir) 268static __inline__ void fir32_free(fir32_state_t * fir)
335{ 269{
336 free(fir->history); 270 kfree(fir->history);
337} 271}
338/*- End of function --------------------------------------------------------*/
339 272
340static __inline__ int16_t fir_float(fir_float_state_t *fir, int16_t sample) 273static __inline__ int16_t fir32(fir32_state_t * fir, int16_t sample)
341{ 274{
342 int i; 275 int i;
343 float y; 276 int32_t y;
344 int offset1; 277 int offset1;
345 int offset2; 278 int offset2;
346 279
347 fir->history[fir->curr_pos] = sample; 280 fir->history[fir->curr_pos] = sample;
348 281 offset2 = fir->curr_pos;
349 offset2 = fir->curr_pos; 282 offset1 = fir->taps - offset2;
350 offset1 = fir->taps - offset2; 283 y = 0;
351 y = 0; 284 for (i = fir->taps - 1; i >= offset1; i--)
352 for (i = fir->taps - 1; i >= offset1; i--) 285 y += fir->coeffs[i] * fir->history[i - offset1];
353 y += fir->coeffs[i]*fir->history[i - offset1]; 286 for (; i >= 0; i--)
354 for ( ; i >= 0; i--) 287 y += fir->coeffs[i] * fir->history[i + offset2];
355 y += fir->coeffs[i]*fir->history[i + offset2]; 288 if (fir->curr_pos <= 0)
356 if (fir->curr_pos <= 0) 289 fir->curr_pos = fir->taps;
357 fir->curr_pos = fir->taps; 290 fir->curr_pos--;
358 fir->curr_pos--; 291 return (int16_t) (y >> 15);
359 return (int16_t) y;
360} 292}
361/*- End of function --------------------------------------------------------*/
362#endif
363
364#ifdef __cplusplus
365}
366#endif
367 293
368#endif 294#endif
369/*- End of file ------------------------------------------------------------*/ 295/*- End of file ------------------------------------------------------------*/
diff --git a/drivers/staging/echo/mmx.h b/drivers/staging/echo/mmx.h
index b5a3964865b6..35412efe61ce 100644
--- a/drivers/staging/echo/mmx.h
+++ b/drivers/staging/echo/mmx.h
@@ -27,24 +27,23 @@
27 * values by ULL, lest they be truncated by the compiler) 27 * values by ULL, lest they be truncated by the compiler)
28 */ 28 */
29 29
30typedef union { 30typedef union {
31 long long q; /* Quadword (64-bit) value */ 31 long long q; /* Quadword (64-bit) value */
32 unsigned long long uq; /* Unsigned Quadword */ 32 unsigned long long uq; /* Unsigned Quadword */
33 int d[2]; /* 2 Doubleword (32-bit) values */ 33 int d[2]; /* 2 Doubleword (32-bit) values */
34 unsigned int ud[2]; /* 2 Unsigned Doubleword */ 34 unsigned int ud[2]; /* 2 Unsigned Doubleword */
35 short w[4]; /* 4 Word (16-bit) values */ 35 short w[4]; /* 4 Word (16-bit) values */
36 unsigned short uw[4]; /* 4 Unsigned Word */ 36 unsigned short uw[4]; /* 4 Unsigned Word */
37 char b[8]; /* 8 Byte (8-bit) values */ 37 char b[8]; /* 8 Byte (8-bit) values */
38 unsigned char ub[8]; /* 8 Unsigned Byte */ 38 unsigned char ub[8]; /* 8 Unsigned Byte */
39 float s[2]; /* Single-precision (32-bit) value */ 39 float s[2]; /* Single-precision (32-bit) value */
40} mmx_t; /* On an 8-byte (64-bit) boundary */ 40} mmx_t; /* On an 8-byte (64-bit) boundary */
41 41
42/* SSE registers */ 42/* SSE registers */
43typedef union { 43typedef union {
44 char b[16]; 44 char b[16];
45} xmm_t; 45} xmm_t;
46 46
47
48#define mmx_i2r(op,imm,reg) \ 47#define mmx_i2r(op,imm,reg) \
49 __asm__ __volatile__ (#op " %0, %%" #reg \ 48 __asm__ __volatile__ (#op " %0, %%" #reg \
50 : /* nothing */ \ 49 : /* nothing */ \
@@ -63,7 +62,6 @@ typedef union {
63#define mmx_r2r(op,regs,regd) \ 62#define mmx_r2r(op,regs,regd) \
64 __asm__ __volatile__ (#op " %" #regs ", %" #regd) 63 __asm__ __volatile__ (#op " %" #regs ", %" #regd)
65 64
66
67#define emms() __asm__ __volatile__ ("emms") 65#define emms() __asm__ __volatile__ ("emms")
68 66
69#define movd_m2r(var,reg) mmx_m2r (movd, var, reg) 67#define movd_m2r(var,reg) mmx_m2r (movd, var, reg)
@@ -192,16 +190,13 @@ typedef union {
192#define pxor_m2r(var,reg) mmx_m2r (pxor, var, reg) 190#define pxor_m2r(var,reg) mmx_m2r (pxor, var, reg)
193#define pxor_r2r(regs,regd) mmx_r2r (pxor, regs, regd) 191#define pxor_r2r(regs,regd) mmx_r2r (pxor, regs, regd)
194 192
195
196/* 3DNOW extensions */ 193/* 3DNOW extensions */
197 194
198#define pavgusb_m2r(var,reg) mmx_m2r (pavgusb, var, reg) 195#define pavgusb_m2r(var,reg) mmx_m2r (pavgusb, var, reg)
199#define pavgusb_r2r(regs,regd) mmx_r2r (pavgusb, regs, regd) 196#define pavgusb_r2r(regs,regd) mmx_r2r (pavgusb, regs, regd)
200 197
201
202/* AMD MMX extensions - also available in intel SSE */ 198/* AMD MMX extensions - also available in intel SSE */
203 199
204
205#define mmx_m2ri(op,mem,reg,imm) \ 200#define mmx_m2ri(op,mem,reg,imm) \
206 __asm__ __volatile__ (#op " %1, %0, %%" #reg \ 201 __asm__ __volatile__ (#op " %1, %0, %%" #reg \
207 : /* nothing */ \ 202 : /* nothing */ \
@@ -216,7 +211,6 @@ typedef union {
216 : /* nothing */ \ 211 : /* nothing */ \
217 : "m" (mem)) 212 : "m" (mem))
218 213
219
220#define maskmovq(regs,maskreg) mmx_r2ri (maskmovq, regs, maskreg) 214#define maskmovq(regs,maskreg) mmx_r2ri (maskmovq, regs, maskreg)
221 215
222#define movntq_r2m(mmreg,var) mmx_r2m (movntq, mmreg, var) 216#define movntq_r2m(mmreg,var) mmx_r2m (movntq, mmreg, var)
@@ -284,5 +278,4 @@ typedef union {
284#define punpcklqdq_r2r(regs,regd) mmx_r2r (punpcklqdq, regs, regd) 278#define punpcklqdq_r2r(regs,regd) mmx_r2r (punpcklqdq, regs, regd)
285#define punpckhqdq_r2r(regs,regd) mmx_r2r (punpckhqdq, regs, regd) 279#define punpckhqdq_r2r(regs,regd) mmx_r2r (punpckhqdq, regs, regd)
286 280
287
288#endif /* AVCODEC_I386MMX_H */ 281#endif /* AVCODEC_I386MMX_H */
diff --git a/drivers/staging/echo/oslec.h b/drivers/staging/echo/oslec.h
new file mode 100644
index 000000000000..bad852328a2f
--- /dev/null
+++ b/drivers/staging/echo/oslec.h
@@ -0,0 +1,86 @@
1/*
2 * OSLEC - A line echo canceller. This code is being developed
3 * against and partially complies with G168. Using code from SpanDSP
4 *
5 * Written by Steve Underwood <steveu@coppice.org>
6 * and David Rowe <david_at_rowetel_dot_com>
7 *
8 * Copyright (C) 2001 Steve Underwood and 2007-2008 David Rowe
9 *
10 * All rights reserved.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2, as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 */
26
27#ifndef __OSLEC_H
28#define __OSLEC_H
29
30/* TODO: document interface */
31
32/* Mask bits for the adaption mode */
33#define ECHO_CAN_USE_ADAPTION 0x01
34#define ECHO_CAN_USE_NLP 0x02
35#define ECHO_CAN_USE_CNG 0x04
36#define ECHO_CAN_USE_CLIP 0x08
37#define ECHO_CAN_USE_TX_HPF 0x10
38#define ECHO_CAN_USE_RX_HPF 0x20
39#define ECHO_CAN_DISABLE 0x40
40
41/*!
42 G.168 echo canceller descriptor. This defines the working state for a line
43 echo canceller.
44*/
45struct oslec_state;
46
47/*! Create a voice echo canceller context.
48 \param len The length of the canceller, in samples.
49 \return The new canceller context, or NULL if the canceller could not be created.
50*/
51struct oslec_state *oslec_create(int len, int adaption_mode);
52
53/*! Free a voice echo canceller context.
54 \param ec The echo canceller context.
55*/
56void oslec_free(struct oslec_state *ec);
57
58/*! Flush (reinitialise) a voice echo canceller context.
59 \param ec The echo canceller context.
60*/
61void oslec_flush(struct oslec_state *ec);
62
63/*! Set the adaption mode of a voice echo canceller context.
64 \param ec The echo canceller context.
65 \param adapt The mode.
66*/
67void oslec_adaption_mode(struct oslec_state *ec, int adaption_mode);
68
69void oslec_snapshot(struct oslec_state *ec);
70
71/*! Process a sample through a voice echo canceller.
72 \param ec The echo canceller context.
73 \param tx The transmitted audio sample.
74 \param rx The received audio sample.
75 \return The clean (echo cancelled) received sample.
76*/
77int16_t oslec_update(struct oslec_state *ec, int16_t tx, int16_t rx);
78
79/*! Process to high pass filter the tx signal.
80 \param ec The echo canceller context.
81 \param tx The transmitted auio sample.
82 \return The HP filtered transmit sample, send this to your D/A.
83*/
84int16_t oslec_hpf_tx(struct oslec_state *ec, int16_t tx);
85
86#endif /* __OSLEC_H */
diff --git a/drivers/staging/et131x/et1310_phy.c b/drivers/staging/et131x/et1310_phy.c
index 6c4fa54419ea..9dd6dfd9a033 100644
--- a/drivers/staging/et131x/et1310_phy.c
+++ b/drivers/staging/et131x/et1310_phy.c
@@ -84,7 +84,6 @@
84#include <linux/if_arp.h> 84#include <linux/if_arp.h>
85#include <linux/ioport.h> 85#include <linux/ioport.h>
86#include <linux/random.h> 86#include <linux/random.h>
87#include <linux/delay.h>
88 87
89#include "et1310_phy.h" 88#include "et1310_phy.h"
90#include "et1310_pm.h" 89#include "et1310_pm.h"
@@ -95,7 +94,6 @@
95#include "et131x_initpci.h" 94#include "et131x_initpci.h"
96 95
97#include "et1310_address_map.h" 96#include "et1310_address_map.h"
98#include "et1310_jagcore.h"
99#include "et1310_tx.h" 97#include "et1310_tx.h"
100#include "et1310_rx.h" 98#include "et1310_rx.h"
101#include "et1310_mac.h" 99#include "et1310_mac.h"
diff --git a/drivers/staging/et131x/et131x_debug.c b/drivers/staging/et131x/et131x_debug.c
index 9ee5bce92c27..d1dd46e0a9c8 100644
--- a/drivers/staging/et131x/et131x_debug.c
+++ b/drivers/staging/et131x/et131x_debug.c
@@ -97,7 +97,6 @@
97#include "et131x_isr.h" 97#include "et131x_isr.h"
98 98
99#include "et1310_address_map.h" 99#include "et1310_address_map.h"
100#include "et1310_jagcore.h"
101#include "et1310_tx.h" 100#include "et1310_tx.h"
102#include "et1310_rx.h" 101#include "et1310_rx.h"
103#include "et1310_mac.h" 102#include "et1310_mac.h"
diff --git a/drivers/staging/et131x/et131x_initpci.c b/drivers/staging/et131x/et131x_initpci.c
index 4c6f171f5b7c..a18c499d0ae0 100644
--- a/drivers/staging/et131x/et131x_initpci.c
+++ b/drivers/staging/et131x/et131x_initpci.c
@@ -97,7 +97,6 @@
97#include "et131x_isr.h" 97#include "et131x_isr.h"
98 98
99#include "et1310_address_map.h" 99#include "et1310_address_map.h"
100#include "et1310_jagcore.h"
101#include "et1310_tx.h" 100#include "et1310_tx.h"
102#include "et1310_rx.h" 101#include "et1310_rx.h"
103#include "et1310_mac.h" 102#include "et1310_mac.h"
diff --git a/drivers/staging/go7007/go7007-driver.c b/drivers/staging/go7007/go7007-driver.c
index 81ae4b0fa890..e4ead96679c8 100644
--- a/drivers/staging/go7007/go7007-driver.c
+++ b/drivers/staging/go7007/go7007-driver.c
@@ -16,7 +16,6 @@
16 */ 16 */
17 17
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/version.h>
20#include <linux/init.h> 19#include <linux/init.h>
21#include <linux/delay.h> 20#include <linux/delay.h>
22#include <linux/sched.h> 21#include <linux/sched.h>
diff --git a/drivers/staging/go7007/go7007-fw.c b/drivers/staging/go7007/go7007-fw.c
index c2aea1020b0d..a0e17b0e0ce3 100644
--- a/drivers/staging/go7007/go7007-fw.c
+++ b/drivers/staging/go7007/go7007-fw.c
@@ -26,7 +26,6 @@
26 26
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/init.h> 28#include <linux/init.h>
29#include <linux/version.h>
30#include <linux/time.h> 29#include <linux/time.h>
31#include <linux/mm.h> 30#include <linux/mm.h>
32#include <linux/device.h> 31#include <linux/device.h>
diff --git a/drivers/staging/go7007/go7007-i2c.c b/drivers/staging/go7007/go7007-i2c.c
index 10baae3dade6..cd55b76eabc7 100644
--- a/drivers/staging/go7007/go7007-i2c.c
+++ b/drivers/staging/go7007/go7007-i2c.c
@@ -15,7 +15,6 @@
15 * Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 15 * Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 */ 16 */
17 17
18#include <linux/version.h>
19#include <linux/module.h> 18#include <linux/module.h>
20#include <linux/init.h> 19#include <linux/init.h>
21#include <linux/delay.h> 20#include <linux/delay.h>
diff --git a/drivers/staging/go7007/go7007-usb.c b/drivers/staging/go7007/go7007-usb.c
index d4ed6d2b715f..3f5ee3424e72 100644
--- a/drivers/staging/go7007/go7007-usb.c
+++ b/drivers/staging/go7007/go7007-usb.c
@@ -16,7 +16,6 @@
16 */ 16 */
17 17
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/version.h>
20#include <linux/kernel.h> 19#include <linux/kernel.h>
21#include <linux/init.h> 20#include <linux/init.h>
22#include <linux/wait.h> 21#include <linux/wait.h>
diff --git a/drivers/staging/go7007/snd-go7007.c b/drivers/staging/go7007/snd-go7007.c
index 382740c405ff..a7de401f61ab 100644
--- a/drivers/staging/go7007/snd-go7007.c
+++ b/drivers/staging/go7007/snd-go7007.c
@@ -17,7 +17,6 @@
17 17
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/version.h>
21#include <linux/moduleparam.h> 20#include <linux/moduleparam.h>
22#include <linux/init.h> 21#include <linux/init.h>
23#include <linux/spinlock.h> 22#include <linux/spinlock.h>
diff --git a/drivers/staging/go7007/wis-ov7640.c b/drivers/staging/go7007/wis-ov7640.c
index f5f11e927af3..2f9efca04606 100644
--- a/drivers/staging/go7007/wis-ov7640.c
+++ b/drivers/staging/go7007/wis-ov7640.c
@@ -17,7 +17,6 @@
17 17
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/version.h>
21#include <linux/i2c.h> 20#include <linux/i2c.h>
22#include <linux/videodev2.h> 21#include <linux/videodev2.h>
23 22
diff --git a/drivers/staging/go7007/wis-saa7113.c b/drivers/staging/go7007/wis-saa7113.c
index c1aff1b923a0..11689723945e 100644
--- a/drivers/staging/go7007/wis-saa7113.c
+++ b/drivers/staging/go7007/wis-saa7113.c
@@ -17,7 +17,6 @@
17 17
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/version.h>
21#include <linux/i2c.h> 20#include <linux/i2c.h>
22#include <linux/videodev2.h> 21#include <linux/videodev2.h>
23#include <linux/ioctl.h> 22#include <linux/ioctl.h>
diff --git a/drivers/staging/go7007/wis-saa7115.c b/drivers/staging/go7007/wis-saa7115.c
index 5c94c883b312..59417a7174d7 100644
--- a/drivers/staging/go7007/wis-saa7115.c
+++ b/drivers/staging/go7007/wis-saa7115.c
@@ -17,7 +17,6 @@
17 17
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/version.h>
21#include <linux/i2c.h> 20#include <linux/i2c.h>
22#include <linux/videodev2.h> 21#include <linux/videodev2.h>
23#include <linux/ioctl.h> 22#include <linux/ioctl.h>
diff --git a/drivers/staging/go7007/wis-sony-tuner.c b/drivers/staging/go7007/wis-sony-tuner.c
index 5997fb479459..5a91ee409a7c 100644
--- a/drivers/staging/go7007/wis-sony-tuner.c
+++ b/drivers/staging/go7007/wis-sony-tuner.c
@@ -17,7 +17,6 @@
17 17
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/version.h>
21#include <linux/i2c.h> 20#include <linux/i2c.h>
22#include <linux/videodev2.h> 21#include <linux/videodev2.h>
23#include <media/tuner.h> 22#include <media/tuner.h>
diff --git a/drivers/staging/go7007/wis-tw2804.c b/drivers/staging/go7007/wis-tw2804.c
index 27fe4d0d4ed6..57b8f2b1caa3 100644
--- a/drivers/staging/go7007/wis-tw2804.c
+++ b/drivers/staging/go7007/wis-tw2804.c
@@ -17,7 +17,6 @@
17 17
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/version.h>
21#include <linux/i2c.h> 20#include <linux/i2c.h>
22#include <linux/videodev2.h> 21#include <linux/videodev2.h>
23#include <linux/ioctl.h> 22#include <linux/ioctl.h>
diff --git a/drivers/staging/go7007/wis-tw9903.c b/drivers/staging/go7007/wis-tw9903.c
index d8e41968022e..40627b282cb4 100644
--- a/drivers/staging/go7007/wis-tw9903.c
+++ b/drivers/staging/go7007/wis-tw9903.c
@@ -17,7 +17,6 @@
17 17
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/version.h>
21#include <linux/i2c.h> 20#include <linux/i2c.h>
22#include <linux/videodev2.h> 21#include <linux/videodev2.h>
23#include <linux/ioctl.h> 22#include <linux/ioctl.h>
diff --git a/drivers/staging/go7007/wis-uda1342.c b/drivers/staging/go7007/wis-uda1342.c
index a0894e3cb8c7..555645c0cc1a 100644
--- a/drivers/staging/go7007/wis-uda1342.c
+++ b/drivers/staging/go7007/wis-uda1342.c
@@ -17,7 +17,6 @@
17 17
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/version.h>
21#include <linux/i2c.h> 20#include <linux/i2c.h>
22#include <linux/videodev2.h> 21#include <linux/videodev2.h>
23#include <media/tvaudio.h> 22#include <media/tvaudio.h>
diff --git a/drivers/staging/me4000/me4000.c b/drivers/staging/me4000/me4000.c
index 862dd7ffb5c0..0b33773bb4f6 100644
--- a/drivers/staging/me4000/me4000.c
+++ b/drivers/staging/me4000/me4000.c
@@ -25,24 +25,21 @@
25#include <linux/sched.h> 25#include <linux/sched.h>
26#include <linux/interrupt.h> 26#include <linux/interrupt.h>
27#include <linux/pci.h> 27#include <linux/pci.h>
28#include <asm/io.h>
29#include <asm/system.h>
30#include <asm/uaccess.h>
31#include <linux/errno.h> 28#include <linux/errno.h>
32#include <linux/delay.h> 29#include <linux/delay.h>
33#include <linux/fs.h>
34#include <linux/mm.h> 30#include <linux/mm.h>
35#include <linux/unistd.h> 31#include <linux/unistd.h>
36#include <linux/list.h> 32#include <linux/list.h>
37#include <linux/proc_fs.h> 33#include <linux/proc_fs.h>
38 34#include <linux/types.h>
39#include <linux/poll.h> 35#include <linux/poll.h>
40#include <linux/vmalloc.h> 36#include <linux/vmalloc.h>
37#include <linux/slab.h>
41#include <asm/pgtable.h> 38#include <asm/pgtable.h>
42#include <asm/uaccess.h> 39#include <asm/uaccess.h>
43#include <linux/types.h> 40#include <asm/io.h>
44 41#include <asm/system.h>
45#include <linux/slab.h> 42#include <asm/uaccess.h>
46 43
47/* Include-File for the Meilhaus ME-4000 I/O board */ 44/* Include-File for the Meilhaus ME-4000 I/O board */
48#include "me4000.h" 45#include "me4000.h"
@@ -57,14 +54,14 @@ MODULE_SUPPORTED_DEVICE("Meilhaus ME-4000 Multi I/O boards");
57MODULE_LICENSE("GPL"); 54MODULE_LICENSE("GPL");
58 55
59/* Board specific data are kept in a global list */ 56/* Board specific data are kept in a global list */
60LIST_HEAD(me4000_board_info_list); 57static LIST_HEAD(me4000_board_info_list);
61 58
62/* Major Device Numbers. 0 means to get it automatically from the System */ 59/* Major Device Numbers. 0 means to get it automatically from the System */
63static int me4000_ao_major_driver_no = 0; 60static int me4000_ao_major_driver_no;
64static int me4000_ai_major_driver_no = 0; 61static int me4000_ai_major_driver_no;
65static int me4000_dio_major_driver_no = 0; 62static int me4000_dio_major_driver_no;
66static int me4000_cnt_major_driver_no = 0; 63static int me4000_cnt_major_driver_no;
67static int me4000_ext_int_major_driver_no = 0; 64static int me4000_ext_int_major_driver_no;
68 65
69/* Let the user specify a custom major driver number */ 66/* Let the user specify a custom major driver number */
70module_param(me4000_ao_major_driver_no, int, 0); 67module_param(me4000_ao_major_driver_no, int, 0);
@@ -88,36 +85,22 @@ MODULE_PARM_DESC(me4000_ext_int_major_driver_no,
88 "Major driver number for external interrupt (default 0)"); 85 "Major driver number for external interrupt (default 0)");
89 86
90/*----------------------------------------------------------------------------- 87/*-----------------------------------------------------------------------------
91 Module stuff
92 ---------------------------------------------------------------------------*/
93int init_module(void);
94void cleanup_module(void);
95
96/*-----------------------------------------------------------------------------
97 Board detection and initialization 88 Board detection and initialization
98 ---------------------------------------------------------------------------*/ 89 ---------------------------------------------------------------------------*/
99static int me4000_probe(struct pci_dev *dev, const struct pci_device_id *id); 90static int me4000_probe(struct pci_dev *dev, const struct pci_device_id *id);
100static int me4000_xilinx_download(me4000_info_t *); 91static int me4000_xilinx_download(struct me4000_info *);
101static int me4000_reset_board(me4000_info_t *); 92static int me4000_reset_board(struct me4000_info *);
102 93
103static void clear_board_info_list(void); 94static void clear_board_info_list(void);
104static int get_registers(struct pci_dev *dev, me4000_info_t * info); 95static void release_ao_contexts(struct me4000_info *board_info);
105static int init_board_info(struct pci_dev *dev, me4000_info_t * board_info);
106static int alloc_ao_contexts(me4000_info_t * info);
107static void release_ao_contexts(me4000_info_t * board_info);
108static int alloc_ai_context(me4000_info_t * info);
109static int alloc_dio_context(me4000_info_t * info);
110static int alloc_cnt_context(me4000_info_t * info);
111static int alloc_ext_int_context(me4000_info_t * info);
112
113/*----------------------------------------------------------------------------- 96/*-----------------------------------------------------------------------------
114 Stuff used by all device parts 97 Stuff used by all device parts
115 ---------------------------------------------------------------------------*/ 98 ---------------------------------------------------------------------------*/
116static int me4000_open(struct inode *, struct file *); 99static int me4000_open(struct inode *, struct file *);
117static int me4000_release(struct inode *, struct file *); 100static int me4000_release(struct inode *, struct file *);
118 101
119static int me4000_get_user_info(me4000_user_info_t *, 102static int me4000_get_user_info(struct me4000_user_info *,
120 me4000_info_t * board_info); 103 struct me4000_info *board_info);
121static int me4000_read_procmem(char *, char **, off_t, int, int *, void *); 104static int me4000_read_procmem(char *, char **, off_t, int, int *, void *);
122 105
123/*----------------------------------------------------------------------------- 106/*-----------------------------------------------------------------------------
@@ -140,40 +123,42 @@ static int me4000_ao_ioctl_cont(struct inode *, struct file *, unsigned int,
140static unsigned int me4000_ao_poll_cont(struct file *, poll_table *); 123static unsigned int me4000_ao_poll_cont(struct file *, poll_table *);
141static int me4000_ao_fsync_cont(struct file *, struct dentry *, int); 124static int me4000_ao_fsync_cont(struct file *, struct dentry *, int);
142 125
143static int me4000_ao_start(unsigned long *, me4000_ao_context_t *); 126static int me4000_ao_start(unsigned long *, struct me4000_ao_context *);
144static int me4000_ao_stop(me4000_ao_context_t *); 127static int me4000_ao_stop(struct me4000_ao_context *);
145static int me4000_ao_immediate_stop(me4000_ao_context_t *); 128static int me4000_ao_immediate_stop(struct me4000_ao_context *);
146static int me4000_ao_timer_set_divisor(u32 *, me4000_ao_context_t *); 129static int me4000_ao_timer_set_divisor(u32 *, struct me4000_ao_context *);
147static int me4000_ao_preload(me4000_ao_context_t *); 130static int me4000_ao_preload(struct me4000_ao_context *);
148static int me4000_ao_preload_update(me4000_ao_context_t *); 131static int me4000_ao_preload_update(struct me4000_ao_context *);
149static int me4000_ao_ex_trig_set_edge(int *, me4000_ao_context_t *); 132static int me4000_ao_ex_trig_set_edge(int *, struct me4000_ao_context *);
150static int me4000_ao_ex_trig_enable(me4000_ao_context_t *); 133static int me4000_ao_ex_trig_enable(struct me4000_ao_context *);
151static int me4000_ao_ex_trig_disable(me4000_ao_context_t *); 134static int me4000_ao_ex_trig_disable(struct me4000_ao_context *);
152static int me4000_ao_prepare(me4000_ao_context_t * ao_info); 135static int me4000_ao_prepare(struct me4000_ao_context *ao_info);
153static int me4000_ao_reset(me4000_ao_context_t * ao_info); 136static int me4000_ao_reset(struct me4000_ao_context *ao_info);
154static int me4000_ao_enable_do(me4000_ao_context_t *); 137static int me4000_ao_enable_do(struct me4000_ao_context *);
155static int me4000_ao_disable_do(me4000_ao_context_t *); 138static int me4000_ao_disable_do(struct me4000_ao_context *);
156static int me4000_ao_fsm_state(int *, me4000_ao_context_t *); 139static int me4000_ao_fsm_state(int *, struct me4000_ao_context *);
157 140
158static int me4000_ao_simultaneous_ex_trig(me4000_ao_context_t * ao_context); 141static int me4000_ao_simultaneous_ex_trig(struct me4000_ao_context *ao_context);
159static int me4000_ao_simultaneous_sw(me4000_ao_context_t * ao_context); 142static int me4000_ao_simultaneous_sw(struct me4000_ao_context *ao_context);
160static int me4000_ao_simultaneous_disable(me4000_ao_context_t * ao_context); 143static int me4000_ao_simultaneous_disable(struct me4000_ao_context *ao_context);
161static int me4000_ao_simultaneous_update(me4000_ao_channel_list_t * channels, 144static int me4000_ao_simultaneous_update(
162 me4000_ao_context_t * ao_context); 145 struct me4000_ao_channel_list *channels,
163 146 struct me4000_ao_context *ao_context);
164static int me4000_ao_synchronous_ex_trig(me4000_ao_context_t * ao_context); 147
165static int me4000_ao_synchronous_sw(me4000_ao_context_t * ao_context); 148static int me4000_ao_synchronous_ex_trig(struct me4000_ao_context *ao_context);
166static int me4000_ao_synchronous_disable(me4000_ao_context_t * ao_context); 149static int me4000_ao_synchronous_sw(struct me4000_ao_context *ao_context);
150static int me4000_ao_synchronous_disable(struct me4000_ao_context *ao_context);
167 151
168static int me4000_ao_ex_trig_timeout(unsigned long *arg, 152static int me4000_ao_ex_trig_timeout(unsigned long *arg,
169 me4000_ao_context_t * ao_context); 153 struct me4000_ao_context *ao_context);
170static int me4000_ao_get_free_buffer(unsigned long *arg, 154static int me4000_ao_get_free_buffer(unsigned long *arg,
171 me4000_ao_context_t * ao_context); 155 struct me4000_ao_context *ao_context);
172 156
173/*----------------------------------------------------------------------------- 157/*-----------------------------------------------------------------------------
174 Analog input stuff 158 Analog input stuff
175 ---------------------------------------------------------------------------*/ 159 ---------------------------------------------------------------------------*/
176static int me4000_ai_single(me4000_ai_single_t *, me4000_ai_context_t *); 160static int me4000_ai_single(struct me4000_ai_single *,
161 struct me4000_ai_context *);
177static int me4000_ai_ioctl_sing(struct inode *, struct file *, unsigned int, 162static int me4000_ai_ioctl_sing(struct inode *, struct file *, unsigned int,
178 unsigned long); 163 unsigned long);
179 164
@@ -186,68 +171,69 @@ static int me4000_ai_fasync(int fd, struct file *file_p, int mode);
186static int me4000_ai_ioctl_ext(struct inode *, struct file *, unsigned int, 171static int me4000_ai_ioctl_ext(struct inode *, struct file *, unsigned int,
187 unsigned long); 172 unsigned long);
188 173
189static int me4000_ai_prepare(me4000_ai_context_t * ai_context); 174static int me4000_ai_prepare(struct me4000_ai_context *ai_context);
190static int me4000_ai_reset(me4000_ai_context_t * ai_context); 175static int me4000_ai_reset(struct me4000_ai_context *ai_context);
191static int me4000_ai_config(me4000_ai_config_t *, me4000_ai_context_t *); 176static int me4000_ai_config(struct me4000_ai_config *,
192static int me4000_ai_start(me4000_ai_context_t *); 177 struct me4000_ai_context *);
193static int me4000_ai_start_ex(unsigned long *, me4000_ai_context_t *); 178static int me4000_ai_start(struct me4000_ai_context *);
194static int me4000_ai_stop(me4000_ai_context_t *); 179static int me4000_ai_start_ex(unsigned long *, struct me4000_ai_context *);
195static int me4000_ai_immediate_stop(me4000_ai_context_t *); 180static int me4000_ai_stop(struct me4000_ai_context *);
196static int me4000_ai_ex_trig_enable(me4000_ai_context_t *); 181static int me4000_ai_immediate_stop(struct me4000_ai_context *);
197static int me4000_ai_ex_trig_disable(me4000_ai_context_t *); 182static int me4000_ai_ex_trig_enable(struct me4000_ai_context *);
198static int me4000_ai_ex_trig_setup(me4000_ai_trigger_t *, 183static int me4000_ai_ex_trig_disable(struct me4000_ai_context *);
199 me4000_ai_context_t *); 184static int me4000_ai_ex_trig_setup(struct me4000_ai_trigger *,
200static int me4000_ai_sc_setup(me4000_ai_sc_t * arg, 185 struct me4000_ai_context *);
201 me4000_ai_context_t * ai_context); 186static int me4000_ai_sc_setup(struct me4000_ai_sc *arg,
202static int me4000_ai_offset_enable(me4000_ai_context_t * ai_context); 187 struct me4000_ai_context *ai_context);
203static int me4000_ai_offset_disable(me4000_ai_context_t * ai_context); 188static int me4000_ai_offset_enable(struct me4000_ai_context *ai_context);
204static int me4000_ai_fullscale_enable(me4000_ai_context_t * ai_context); 189static int me4000_ai_offset_disable(struct me4000_ai_context *ai_context);
205static int me4000_ai_fullscale_disable(me4000_ai_context_t * ai_context); 190static int me4000_ai_fullscale_enable(struct me4000_ai_context *ai_context);
206static int me4000_ai_fsm_state(int *arg, me4000_ai_context_t * ai_context); 191static int me4000_ai_fullscale_disable(struct me4000_ai_context *ai_context);
192static int me4000_ai_fsm_state(int *arg, struct me4000_ai_context *ai_context);
207static int me4000_ai_get_count_buffer(unsigned long *arg, 193static int me4000_ai_get_count_buffer(unsigned long *arg,
208 me4000_ai_context_t * ai_context); 194 struct me4000_ai_context *ai_context);
209 195
210/*----------------------------------------------------------------------------- 196/*-----------------------------------------------------------------------------
211 EEPROM stuff 197 EEPROM stuff
212 ---------------------------------------------------------------------------*/ 198 ---------------------------------------------------------------------------*/
213static int me4000_eeprom_read(me4000_eeprom_t * arg, 199static int me4000_eeprom_read(struct me4000_eeprom *arg,
214 me4000_ai_context_t * ai_context); 200 struct me4000_ai_context *ai_context);
215static int me4000_eeprom_write(me4000_eeprom_t * arg, 201static int me4000_eeprom_write(struct me4000_eeprom *arg,
216 me4000_ai_context_t * ai_context); 202 struct me4000_ai_context *ai_context);
217static unsigned short eeprom_read_cmd(me4000_ai_context_t * ai_context,
218 unsigned long cmd, int length);
219static int eeprom_write_cmd(me4000_ai_context_t * ai_context, unsigned long cmd,
220 int length);
221 203
222/*----------------------------------------------------------------------------- 204/*-----------------------------------------------------------------------------
223 Digital I/O stuff 205 Digital I/O stuff
224 ---------------------------------------------------------------------------*/ 206 ---------------------------------------------------------------------------*/
225static int me4000_dio_ioctl(struct inode *, struct file *, unsigned int, 207static int me4000_dio_ioctl(struct inode *, struct file *, unsigned int,
226 unsigned long); 208 unsigned long);
227static int me4000_dio_config(me4000_dio_config_t *, me4000_dio_context_t *); 209static int me4000_dio_config(struct me4000_dio_config *,
228static int me4000_dio_get_byte(me4000_dio_byte_t *, me4000_dio_context_t *); 210 struct me4000_dio_context *);
229static int me4000_dio_set_byte(me4000_dio_byte_t *, me4000_dio_context_t *); 211static int me4000_dio_get_byte(struct me4000_dio_byte *,
230static int me4000_dio_reset(me4000_dio_context_t *); 212 struct me4000_dio_context *);
213static int me4000_dio_set_byte(struct me4000_dio_byte *,
214 struct me4000_dio_context *);
215static int me4000_dio_reset(struct me4000_dio_context *);
231 216
232/*----------------------------------------------------------------------------- 217/*-----------------------------------------------------------------------------
233 Counter stuff 218 Counter stuff
234 ---------------------------------------------------------------------------*/ 219 ---------------------------------------------------------------------------*/
235static int me4000_cnt_ioctl(struct inode *, struct file *, unsigned int, 220static int me4000_cnt_ioctl(struct inode *, struct file *, unsigned int,
236 unsigned long); 221 unsigned long);
237static int me4000_cnt_config(me4000_cnt_config_t *, me4000_cnt_context_t *); 222static int me4000_cnt_config(struct me4000_cnt_config *,
238static int me4000_cnt_read(me4000_cnt_t *, me4000_cnt_context_t *); 223 struct me4000_cnt_context *);
239static int me4000_cnt_write(me4000_cnt_t *, me4000_cnt_context_t *); 224static int me4000_cnt_read(struct me4000_cnt *, struct me4000_cnt_context *);
240static int me4000_cnt_reset(me4000_cnt_context_t *); 225static int me4000_cnt_write(struct me4000_cnt *, struct me4000_cnt_context *);
226static int me4000_cnt_reset(struct me4000_cnt_context *);
241 227
242/*----------------------------------------------------------------------------- 228/*-----------------------------------------------------------------------------
243 External interrupt routines 229 External interrupt routines
244 ---------------------------------------------------------------------------*/ 230 ---------------------------------------------------------------------------*/
245static int me4000_ext_int_ioctl(struct inode *, struct file *, unsigned int, 231static int me4000_ext_int_ioctl(struct inode *, struct file *, unsigned int,
246 unsigned long); 232 unsigned long);
247static int me4000_ext_int_enable(me4000_ext_int_context_t *); 233static int me4000_ext_int_enable(struct me4000_ext_int_context *);
248static int me4000_ext_int_disable(me4000_ext_int_context_t *); 234static int me4000_ext_int_disable(struct me4000_ext_int_context *);
249static int me4000_ext_int_count(unsigned long *arg, 235static int me4000_ext_int_count(unsigned long *arg,
250 me4000_ext_int_context_t * ext_int_context); 236 struct me4000_ext_int_context *ext_int_context);
251static int me4000_ext_int_fasync(int fd, struct file *file_ptr, int mode); 237static int me4000_ext_int_fasync(int fd, struct file *file_ptr, int mode);
252 238
253/*----------------------------------------------------------------------------- 239/*-----------------------------------------------------------------------------
@@ -260,27 +246,18 @@ static irqreturn_t me4000_ext_int_isr(int, void *);
260/*----------------------------------------------------------------------------- 246/*-----------------------------------------------------------------------------
261 Inline functions 247 Inline functions
262 ---------------------------------------------------------------------------*/ 248 ---------------------------------------------------------------------------*/
263static int inline me4000_buf_count(me4000_circ_buf_t, int);
264static int inline me4000_buf_space(me4000_circ_buf_t, int);
265static int inline me4000_space_to_end(me4000_circ_buf_t, int);
266static int inline me4000_values_to_end(me4000_circ_buf_t, int);
267
268static void inline me4000_outb(unsigned char value, unsigned long port);
269static void inline me4000_outl(unsigned long value, unsigned long port);
270static unsigned long inline me4000_inl(unsigned long port);
271static unsigned char inline me4000_inb(unsigned long port);
272 249
273static int me4000_buf_count(me4000_circ_buf_t buf, int size) 250static int inline me4000_buf_count(struct me4000_circ_buf buf, int size)
274{ 251{
275 return ((buf.head - buf.tail) & (size - 1)); 252 return ((buf.head - buf.tail) & (size - 1));
276} 253}
277 254
278static int me4000_buf_space(me4000_circ_buf_t buf, int size) 255static int inline me4000_buf_space(struct me4000_circ_buf buf, int size)
279{ 256{
280 return ((buf.tail - (buf.head + 1)) & (size - 1)); 257 return ((buf.tail - (buf.head + 1)) & (size - 1));
281} 258}
282 259
283static int me4000_values_to_end(me4000_circ_buf_t buf, int size) 260static int inline me4000_values_to_end(struct me4000_circ_buf buf, int size)
284{ 261{
285 int end; 262 int end;
286 int n; 263 int n;
@@ -289,7 +266,7 @@ static int me4000_values_to_end(me4000_circ_buf_t buf, int size)
289 return (n < end) ? n : end; 266 return (n < end) ? n : end;
290} 267}
291 268
292static int me4000_space_to_end(me4000_circ_buf_t buf, int size) 269static int inline me4000_space_to_end(struct me4000_circ_buf buf, int size)
293{ 270{
294 int end; 271 int end;
295 int n; 272 int n;
@@ -299,19 +276,19 @@ static int me4000_space_to_end(me4000_circ_buf_t buf, int size)
299 return (n <= end) ? n : (end + 1); 276 return (n <= end) ? n : (end + 1);
300} 277}
301 278
302static void me4000_outb(unsigned char value, unsigned long port) 279static void inline me4000_outb(unsigned char value, unsigned long port)
303{ 280{
304 PORT_PDEBUG("--> 0x%02X port 0x%04lX\n", value, port); 281 PORT_PDEBUG("--> 0x%02X port 0x%04lX\n", value, port);
305 outb(value, port); 282 outb(value, port);
306} 283}
307 284
308static void me4000_outl(unsigned long value, unsigned long port) 285static void inline me4000_outl(unsigned long value, unsigned long port)
309{ 286{
310 PORT_PDEBUG("--> 0x%08lX port 0x%04lX\n", value, port); 287 PORT_PDEBUG("--> 0x%08lX port 0x%04lX\n", value, port);
311 outl(value, port); 288 outl(value, port);
312} 289}
313 290
314static unsigned long me4000_inl(unsigned long port) 291static unsigned long inline me4000_inl(unsigned long port)
315{ 292{
316 unsigned long value; 293 unsigned long value;
317 value = inl(port); 294 value = inl(port);
@@ -319,7 +296,7 @@ static unsigned long me4000_inl(unsigned long port)
319 return value; 296 return value;
320} 297}
321 298
322static unsigned char me4000_inb(unsigned long port) 299static unsigned char inline me4000_inb(unsigned long port)
323{ 300{
324 unsigned char value; 301 unsigned char value;
325 value = inb(port); 302 value = inb(port);
@@ -327,102 +304,102 @@ static unsigned char me4000_inb(unsigned long port)
327 return value; 304 return value;
328} 305}
329 306
330struct pci_driver me4000_driver = { 307static struct pci_driver me4000_driver = {
331 .name = ME4000_NAME, 308 .name = ME4000_NAME,
332 .id_table = me4000_pci_table, 309 .id_table = me4000_pci_table,
333 .probe = me4000_probe 310 .probe = me4000_probe
334}; 311};
335 312
336static struct file_operations me4000_ao_fops_sing = { 313static struct file_operations me4000_ao_fops_sing = {
337 owner:THIS_MODULE, 314 .owner = THIS_MODULE,
338 write:me4000_ao_write_sing, 315 .write = me4000_ao_write_sing,
339 ioctl:me4000_ao_ioctl_sing, 316 .ioctl = me4000_ao_ioctl_sing,
340 open:me4000_open, 317 .open = me4000_open,
341 release:me4000_release, 318 .release = me4000_release,
342}; 319};
343 320
344static struct file_operations me4000_ao_fops_wrap = { 321static struct file_operations me4000_ao_fops_wrap = {
345 owner:THIS_MODULE, 322 .owner = THIS_MODULE,
346 write:me4000_ao_write_wrap, 323 .write = me4000_ao_write_wrap,
347 ioctl:me4000_ao_ioctl_wrap, 324 .ioctl = me4000_ao_ioctl_wrap,
348 open:me4000_open, 325 .open = me4000_open,
349 release:me4000_release, 326 .release = me4000_release,
350}; 327};
351 328
352static struct file_operations me4000_ao_fops_cont = { 329static struct file_operations me4000_ao_fops_cont = {
353 owner:THIS_MODULE, 330 .owner = THIS_MODULE,
354 write:me4000_ao_write_cont, 331 .write = me4000_ao_write_cont,
355 poll:me4000_ao_poll_cont, 332 .poll = me4000_ao_poll_cont,
356 ioctl:me4000_ao_ioctl_cont, 333 .ioctl = me4000_ao_ioctl_cont,
357 open:me4000_open, 334 .open = me4000_open,
358 release:me4000_release, 335 .release = me4000_release,
359 fsync:me4000_ao_fsync_cont, 336 .fsync = me4000_ao_fsync_cont,
360}; 337};
361 338
362static struct file_operations me4000_ai_fops_sing = { 339static struct file_operations me4000_ai_fops_sing = {
363 owner:THIS_MODULE, 340 .owner = THIS_MODULE,
364 ioctl:me4000_ai_ioctl_sing, 341 .ioctl = me4000_ai_ioctl_sing,
365 open:me4000_open, 342 .open = me4000_open,
366 release:me4000_release, 343 .release = me4000_release,
367}; 344};
368 345
369static struct file_operations me4000_ai_fops_cont_sw = { 346static struct file_operations me4000_ai_fops_cont_sw = {
370 owner:THIS_MODULE, 347 .owner = THIS_MODULE,
371 read:me4000_ai_read, 348 .read = me4000_ai_read,
372 poll:me4000_ai_poll, 349 .poll = me4000_ai_poll,
373 ioctl:me4000_ai_ioctl_sw, 350 .ioctl = me4000_ai_ioctl_sw,
374 open:me4000_open, 351 .open = me4000_open,
375 release:me4000_release, 352 .release = me4000_release,
376 fasync:me4000_ai_fasync, 353 .fasync = me4000_ai_fasync,
377}; 354};
378 355
379static struct file_operations me4000_ai_fops_cont_et = { 356static struct file_operations me4000_ai_fops_cont_et = {
380 owner:THIS_MODULE, 357 .owner = THIS_MODULE,
381 read:me4000_ai_read, 358 .read = me4000_ai_read,
382 poll:me4000_ai_poll, 359 .poll = me4000_ai_poll,
383 ioctl:me4000_ai_ioctl_ext, 360 .ioctl = me4000_ai_ioctl_ext,
384 open:me4000_open, 361 .open = me4000_open,
385 release:me4000_release, 362 .release = me4000_release,
386}; 363};
387 364
388static struct file_operations me4000_ai_fops_cont_et_value = { 365static struct file_operations me4000_ai_fops_cont_et_value = {
389 owner:THIS_MODULE, 366 .owner = THIS_MODULE,
390 read:me4000_ai_read, 367 .read = me4000_ai_read,
391 poll:me4000_ai_poll, 368 .poll = me4000_ai_poll,
392 ioctl:me4000_ai_ioctl_ext, 369 .ioctl = me4000_ai_ioctl_ext,
393 open:me4000_open, 370 .open = me4000_open,
394 release:me4000_release, 371 .release = me4000_release,
395}; 372};
396 373
397static struct file_operations me4000_ai_fops_cont_et_chanlist = { 374static struct file_operations me4000_ai_fops_cont_et_chanlist = {
398 owner:THIS_MODULE, 375 .owner = THIS_MODULE,
399 read:me4000_ai_read, 376 .read = me4000_ai_read,
400 poll:me4000_ai_poll, 377 .poll = me4000_ai_poll,
401 ioctl:me4000_ai_ioctl_ext, 378 .ioctl = me4000_ai_ioctl_ext,
402 open:me4000_open, 379 .open = me4000_open,
403 release:me4000_release, 380 .release = me4000_release,
404}; 381};
405 382
406static struct file_operations me4000_dio_fops = { 383static struct file_operations me4000_dio_fops = {
407 owner:THIS_MODULE, 384 .owner = THIS_MODULE,
408 ioctl:me4000_dio_ioctl, 385 .ioctl = me4000_dio_ioctl,
409 open:me4000_open, 386 .open = me4000_open,
410 release:me4000_release, 387 .release = me4000_release,
411}; 388};
412 389
413static struct file_operations me4000_cnt_fops = { 390static struct file_operations me4000_cnt_fops = {
414 owner:THIS_MODULE, 391 .owner = THIS_MODULE,
415 ioctl:me4000_cnt_ioctl, 392 .ioctl = me4000_cnt_ioctl,
416 open:me4000_open, 393 .open = me4000_open,
417 release:me4000_release, 394 .release = me4000_release,
418}; 395};
419 396
420static struct file_operations me4000_ext_int_fops = { 397static struct file_operations me4000_ext_int_fops = {
421 owner:THIS_MODULE, 398 .owner = THIS_MODULE,
422 ioctl:me4000_ext_int_ioctl, 399 .ioctl = me4000_ext_int_ioctl,
423 open:me4000_open, 400 .open = me4000_open,
424 release:me4000_release, 401 .release = me4000_release,
425 fasync:me4000_ext_int_fasync, 402 .fasync = me4000_ext_int_fasync,
426}; 403};
427 404
428static struct file_operations *me4000_ao_fops_array[] = { 405static struct file_operations *me4000_ao_fops_array[] = {
@@ -439,9 +416,9 @@ static struct file_operations *me4000_ai_fops_array[] = {
439 &me4000_ai_fops_cont_et_chanlist, // work through one channel list by external trigger 416 &me4000_ai_fops_cont_et_chanlist, // work through one channel list by external trigger
440}; 417};
441 418
442int __init me4000_init_module(void) 419static int __init me4000_init_module(void)
443{ 420{
444 int result = 0; 421 int result;
445 422
446 CALL_PDEBUG("init_module() is executed\n"); 423 CALL_PDEBUG("init_module() is executed\n");
447 424
@@ -533,26 +510,26 @@ int __init me4000_init_module(void)
533 510
534 return 0; 511 return 0;
535 512
536 INIT_ERROR_7: 513INIT_ERROR_7:
537 unregister_chrdev(me4000_ext_int_major_driver_no, ME4000_EXT_INT_NAME); 514 unregister_chrdev(me4000_ext_int_major_driver_no, ME4000_EXT_INT_NAME);
538 515
539 INIT_ERROR_6: 516INIT_ERROR_6:
540 unregister_chrdev(me4000_cnt_major_driver_no, ME4000_CNT_NAME); 517 unregister_chrdev(me4000_cnt_major_driver_no, ME4000_CNT_NAME);
541 518
542 INIT_ERROR_5: 519INIT_ERROR_5:
543 unregister_chrdev(me4000_dio_major_driver_no, ME4000_DIO_NAME); 520 unregister_chrdev(me4000_dio_major_driver_no, ME4000_DIO_NAME);
544 521
545 INIT_ERROR_4: 522INIT_ERROR_4:
546 unregister_chrdev(me4000_ai_major_driver_no, ME4000_AI_NAME); 523 unregister_chrdev(me4000_ai_major_driver_no, ME4000_AI_NAME);
547 524
548 INIT_ERROR_3: 525INIT_ERROR_3:
549 unregister_chrdev(me4000_ao_major_driver_no, ME4000_AO_NAME); 526 unregister_chrdev(me4000_ao_major_driver_no, ME4000_AO_NAME);
550 527
551 INIT_ERROR_2: 528INIT_ERROR_2:
552 pci_unregister_driver(&me4000_driver); 529 pci_unregister_driver(&me4000_driver);
553 clear_board_info_list(); 530 clear_board_info_list();
554 531
555 INIT_ERROR_1: 532INIT_ERROR_1:
556 return result; 533 return result;
557} 534}
558 535
@@ -562,18 +539,18 @@ static void clear_board_info_list(void)
562{ 539{
563 struct list_head *board_p; 540 struct list_head *board_p;
564 struct list_head *dac_p; 541 struct list_head *dac_p;
565 me4000_info_t *board_info; 542 struct me4000_info *board_info;
566 me4000_ao_context_t *ao_context; 543 struct me4000_ao_context *ao_context;
567 544
568 /* Clear context lists */ 545 /* Clear context lists */
569 for (board_p = me4000_board_info_list.next; 546 for (board_p = me4000_board_info_list.next;
570 board_p != &me4000_board_info_list; board_p = board_p->next) { 547 board_p != &me4000_board_info_list; board_p = board_p->next) {
571 board_info = list_entry(board_p, me4000_info_t, list); 548 board_info = list_entry(board_p, struct me4000_info, list);
572 /* Clear analog output context list */ 549 /* Clear analog output context list */
573 while (!list_empty(&board_info->ao_context_list)) { 550 while (!list_empty(&board_info->ao_context_list)) {
574 dac_p = board_info->ao_context_list.next; 551 dac_p = board_info->ao_context_list.next;
575 ao_context = 552 ao_context =
576 list_entry(dac_p, me4000_ao_context_t, list); 553 list_entry(dac_p, struct me4000_ao_context, list);
577 me4000_ao_reset(ao_context); 554 me4000_ao_reset(ao_context);
578 free_irq(ao_context->irq, ao_context); 555 free_irq(ao_context->irq, ao_context);
579 if (ao_context->circ_buf.buf) 556 if (ao_context->circ_buf.buf)
@@ -600,14 +577,14 @@ static void clear_board_info_list(void)
600 /* Clear the board info list */ 577 /* Clear the board info list */
601 while (!list_empty(&me4000_board_info_list)) { 578 while (!list_empty(&me4000_board_info_list)) {
602 board_p = me4000_board_info_list.next; 579 board_p = me4000_board_info_list.next;
603 board_info = list_entry(board_p, me4000_info_t, list); 580 board_info = list_entry(board_p, struct me4000_info, list);
604 pci_release_regions(board_info->pci_dev_p); 581 pci_release_regions(board_info->pci_dev_p);
605 list_del(board_p); 582 list_del(board_p);
606 kfree(board_info); 583 kfree(board_info);
607 } 584 }
608} 585}
609 586
610static int get_registers(struct pci_dev *dev, me4000_info_t * board_info) 587static int get_registers(struct pci_dev *dev, struct me4000_info *board_info)
611{ 588{
612 589
613 /*--------------------------- plx regbase ---------------------------------*/ 590 /*--------------------------- plx regbase ---------------------------------*/
@@ -667,20 +644,20 @@ static int get_registers(struct pci_dev *dev, me4000_info_t * board_info)
667} 644}
668 645
669static int init_board_info(struct pci_dev *pci_dev_p, 646static int init_board_info(struct pci_dev *pci_dev_p,
670 me4000_info_t * board_info) 647 struct me4000_info *board_info)
671{ 648{
672 int i; 649 int i;
673 int result; 650 int result;
674 struct list_head *board_p; 651 struct list_head *board_p;
675 board_info->pci_dev_p = pci_dev_p; 652 board_info->pci_dev_p = pci_dev_p;
676 653
677 for (i = 0; i < ME4000_BOARD_VERSIONS; i++) { 654 for (i = 0; i < ARRAY_SIZE(me4000_boards); i++) {
678 if (me4000_boards[i].device_id == pci_dev_p->device) { 655 if (me4000_boards[i].device_id == pci_dev_p->device) {
679 board_info->board_p = &me4000_boards[i]; 656 board_info->board_p = &me4000_boards[i];
680 break; 657 break;
681 } 658 }
682 } 659 }
683 if (i == ME4000_BOARD_VERSIONS) { 660 if (i == ARRAY_SIZE(me4000_boards)) {
684 printk(KERN_ERR 661 printk(KERN_ERR
685 "ME4000:init_board_info():Device ID not valid\n"); 662 "ME4000:init_board_info():Device ID not valid\n");
686 return -ENODEV; 663 return -ENODEV;
@@ -755,21 +732,21 @@ static int init_board_info(struct pci_dev *pci_dev_p,
755 return 0; 732 return 0;
756} 733}
757 734
758static int alloc_ao_contexts(me4000_info_t * info) 735static int alloc_ao_contexts(struct me4000_info *info)
759{ 736{
760 int i; 737 int i;
761 int err; 738 int err;
762 me4000_ao_context_t *ao_context; 739 struct me4000_ao_context *ao_context;
763 740
764 for (i = 0; i < info->board_p->ao.count; i++) { 741 for (i = 0; i < info->board_p->ao.count; i++) {
765 ao_context = kmalloc(sizeof(me4000_ao_context_t), GFP_KERNEL); 742 ao_context = kzalloc(sizeof(struct me4000_ao_context),
743 GFP_KERNEL);
766 if (!ao_context) { 744 if (!ao_context) {
767 printk(KERN_ERR 745 printk(KERN_ERR
768 "alloc_ao_contexts():Can't get memory for ao context\n"); 746 "alloc_ao_contexts():Can't get memory for ao context\n");
769 release_ao_contexts(info); 747 release_ao_contexts(info);
770 return -ENOMEM; 748 return -ENOMEM;
771 } 749 }
772 memset(ao_context, 0, sizeof(me4000_ao_context_t));
773 750
774 spin_lock_init(&ao_context->use_lock); 751 spin_lock_init(&ao_context->use_lock);
775 spin_lock_init(&ao_context->int_lock); 752 spin_lock_init(&ao_context->int_lock);
@@ -780,15 +757,13 @@ static int alloc_ao_contexts(me4000_info_t * info)
780 if (info->board_p->ao.fifo_count) { 757 if (info->board_p->ao.fifo_count) {
781 /* Allocate circular buffer */ 758 /* Allocate circular buffer */
782 ao_context->circ_buf.buf = 759 ao_context->circ_buf.buf =
783 kmalloc(ME4000_AO_BUFFER_SIZE, GFP_KERNEL); 760 kzalloc(ME4000_AO_BUFFER_SIZE, GFP_KERNEL);
784 if (!ao_context->circ_buf.buf) { 761 if (!ao_context->circ_buf.buf) {
785 printk(KERN_ERR 762 printk(KERN_ERR
786 "alloc_ao_contexts():Can't get circular buffer\n"); 763 "alloc_ao_contexts():Can't get circular buffer\n");
787 release_ao_contexts(info); 764 release_ao_contexts(info);
788 return -ENOMEM; 765 return -ENOMEM;
789 } 766 }
790 memset(ao_context->circ_buf.buf, 0,
791 ME4000_AO_BUFFER_SIZE);
792 767
793 /* Clear the circular buffer */ 768 /* Clear the circular buffer */
794 ao_context->circ_buf.head = 0; 769 ao_context->circ_buf.head = 0;
@@ -872,9 +847,8 @@ static int alloc_ao_contexts(me4000_info_t * info)
872 ME4000_NAME, ao_context); 847 ME4000_NAME, ao_context);
873 if (err) { 848 if (err) {
874 printk(KERN_ERR 849 printk(KERN_ERR
875 "alloc_ao_contexts():Can't get interrupt line"); 850 "%s:Can't get interrupt line", __func__);
876 if (ao_context->circ_buf.buf) 851 kfree(ao_context->circ_buf.buf);
877 kfree(ao_context->circ_buf.buf);
878 kfree(ao_context); 852 kfree(ao_context);
879 release_ao_contexts(info); 853 release_ao_contexts(info);
880 return -ENODEV; 854 return -ENODEV;
@@ -888,35 +862,34 @@ static int alloc_ao_contexts(me4000_info_t * info)
888 return 0; 862 return 0;
889} 863}
890 864
891static void release_ao_contexts(me4000_info_t * board_info) 865static void release_ao_contexts(struct me4000_info *board_info)
892{ 866{
893 struct list_head *dac_p; 867 struct list_head *dac_p;
894 me4000_ao_context_t *ao_context; 868 struct me4000_ao_context *ao_context;
895 869
896 /* Clear analog output context list */ 870 /* Clear analog output context list */
897 while (!list_empty(&board_info->ao_context_list)) { 871 while (!list_empty(&board_info->ao_context_list)) {
898 dac_p = board_info->ao_context_list.next; 872 dac_p = board_info->ao_context_list.next;
899 ao_context = list_entry(dac_p, me4000_ao_context_t, list); 873 ao_context = list_entry(dac_p, struct me4000_ao_context, list);
900 free_irq(ao_context->irq, ao_context); 874 free_irq(ao_context->irq, ao_context);
901 if (ao_context->circ_buf.buf) 875 kfree(ao_context->circ_buf.buf);
902 kfree(ao_context->circ_buf.buf);
903 list_del(dac_p); 876 list_del(dac_p);
904 kfree(ao_context); 877 kfree(ao_context);
905 } 878 }
906} 879}
907 880
908static int alloc_ai_context(me4000_info_t * info) 881static int alloc_ai_context(struct me4000_info *info)
909{ 882{
910 me4000_ai_context_t *ai_context; 883 struct me4000_ai_context *ai_context;
911 884
912 if (info->board_p->ai.count) { 885 if (info->board_p->ai.count) {
913 ai_context = kmalloc(sizeof(me4000_ai_context_t), GFP_KERNEL); 886 ai_context = kzalloc(sizeof(struct me4000_ai_context),
887 GFP_KERNEL);
914 if (!ai_context) { 888 if (!ai_context) {
915 printk(KERN_ERR 889 printk(KERN_ERR
916 "ME4000:alloc_ai_context():Can't get memory for ai context\n"); 890 "ME4000:alloc_ai_context():Can't get memory for ai context\n");
917 return -ENOMEM; 891 return -ENOMEM;
918 } 892 }
919 memset(ai_context, 0, sizeof(me4000_ai_context_t));
920 893
921 info->ai_context = ai_context; 894 info->ai_context = ai_context;
922 895
@@ -958,18 +931,18 @@ static int alloc_ai_context(me4000_info_t * info)
958 return 0; 931 return 0;
959} 932}
960 933
961static int alloc_dio_context(me4000_info_t * info) 934static int alloc_dio_context(struct me4000_info *info)
962{ 935{
963 me4000_dio_context_t *dio_context; 936 struct me4000_dio_context *dio_context;
964 937
965 if (info->board_p->dio.count) { 938 if (info->board_p->dio.count) {
966 dio_context = kmalloc(sizeof(me4000_dio_context_t), GFP_KERNEL); 939 dio_context = kzalloc(sizeof(struct me4000_dio_context),
940 GFP_KERNEL);
967 if (!dio_context) { 941 if (!dio_context) {
968 printk(KERN_ERR 942 printk(KERN_ERR
969 "ME4000:alloc_dio_context():Can't get memory for dio context\n"); 943 "ME4000:alloc_dio_context():Can't get memory for dio context\n");
970 return -ENOMEM; 944 return -ENOMEM;
971 } 945 }
972 memset(dio_context, 0, sizeof(me4000_dio_context_t));
973 946
974 info->dio_context = dio_context; 947 info->dio_context = dio_context;
975 948
@@ -995,18 +968,18 @@ static int alloc_dio_context(me4000_info_t * info)
995 return 0; 968 return 0;
996} 969}
997 970
998static int alloc_cnt_context(me4000_info_t * info) 971static int alloc_cnt_context(struct me4000_info *info)
999{ 972{
1000 me4000_cnt_context_t *cnt_context; 973 struct me4000_cnt_context *cnt_context;
1001 974
1002 if (info->board_p->cnt.count) { 975 if (info->board_p->cnt.count) {
1003 cnt_context = kmalloc(sizeof(me4000_cnt_context_t), GFP_KERNEL); 976 cnt_context = kzalloc(sizeof(struct me4000_cnt_context),
977 GFP_KERNEL);
1004 if (!cnt_context) { 978 if (!cnt_context) {
1005 printk(KERN_ERR 979 printk(KERN_ERR
1006 "ME4000:alloc_cnt_context():Can't get memory for cnt context\n"); 980 "ME4000:alloc_cnt_context():Can't get memory for cnt context\n");
1007 return -ENOMEM; 981 return -ENOMEM;
1008 } 982 }
1009 memset(cnt_context, 0, sizeof(me4000_cnt_context_t));
1010 983
1011 info->cnt_context = cnt_context; 984 info->cnt_context = cnt_context;
1012 985
@@ -1026,19 +999,18 @@ static int alloc_cnt_context(me4000_info_t * info)
1026 return 0; 999 return 0;
1027} 1000}
1028 1001
1029static int alloc_ext_int_context(me4000_info_t * info) 1002static int alloc_ext_int_context(struct me4000_info *info)
1030{ 1003{
1031 me4000_ext_int_context_t *ext_int_context; 1004 struct me4000_ext_int_context *ext_int_context;
1032 1005
1033 if (info->board_p->cnt.count) { 1006 if (info->board_p->cnt.count) {
1034 ext_int_context = 1007 ext_int_context =
1035 kmalloc(sizeof(me4000_ext_int_context_t), GFP_KERNEL); 1008 kzalloc(sizeof(struct me4000_ext_int_context), GFP_KERNEL);
1036 if (!ext_int_context) { 1009 if (!ext_int_context) {
1037 printk(KERN_ERR 1010 printk(KERN_ERR
1038 "ME4000:alloc_ext_int_context():Can't get memory for cnt context\n"); 1011 "ME4000:alloc_ext_int_context():Can't get memory for cnt context\n");
1039 return -ENOMEM; 1012 return -ENOMEM;
1040 } 1013 }
1041 memset(ext_int_context, 0, sizeof(me4000_ext_int_context_t));
1042 1014
1043 info->ext_int_context = ext_int_context; 1015 info->ext_int_context = ext_int_context;
1044 1016
@@ -1060,19 +1032,18 @@ static int alloc_ext_int_context(me4000_info_t * info)
1060static int me4000_probe(struct pci_dev *dev, const struct pci_device_id *id) 1032static int me4000_probe(struct pci_dev *dev, const struct pci_device_id *id)
1061{ 1033{
1062 int result = 0; 1034 int result = 0;
1063 me4000_info_t *board_info; 1035 struct me4000_info *board_info;
1064 1036
1065 CALL_PDEBUG("me4000_probe() is executed\n"); 1037 CALL_PDEBUG("me4000_probe() is executed\n");
1066 1038
1067 /* Allocate structure for board context */ 1039 /* Allocate structure for board context */
1068 board_info = kmalloc(sizeof(me4000_info_t), GFP_KERNEL); 1040 board_info = kzalloc(sizeof(struct me4000_info), GFP_KERNEL);
1069 if (!board_info) { 1041 if (!board_info) {
1070 printk(KERN_ERR 1042 printk(KERN_ERR
1071 "ME4000:Can't get memory for board info structure\n"); 1043 "ME4000:Can't get memory for board info structure\n");
1072 result = -ENOMEM; 1044 result = -ENOMEM;
1073 goto PROBE_ERROR_1; 1045 goto PROBE_ERROR_1;
1074 } 1046 }
1075 memset(board_info, 0, sizeof(me4000_info_t));
1076 1047
1077 /* Add to global linked list */ 1048 /* Add to global linked list */
1078 list_add_tail(&board_info->list, &me4000_board_info_list); 1049 list_add_tail(&board_info->list, &me4000_board_info_list);
@@ -1080,70 +1051,70 @@ static int me4000_probe(struct pci_dev *dev, const struct pci_device_id *id)
1080 /* Get the PCI base registers */ 1051 /* Get the PCI base registers */
1081 result = get_registers(dev, board_info); 1052 result = get_registers(dev, board_info);
1082 if (result) { 1053 if (result) {
1083 printk(KERN_ERR "me4000_probe():Cannot get registers\n"); 1054 printk(KERN_ERR "%s:Cannot get registers\n", __func__);
1084 goto PROBE_ERROR_2; 1055 goto PROBE_ERROR_2;
1085 } 1056 }
1086 1057
1087 /* Enable the device */ 1058 /* Enable the device */
1088 result = pci_enable_device(dev); 1059 result = pci_enable_device(dev);
1089 if (result < 0) { 1060 if (result < 0) {
1090 printk(KERN_ERR "me4000_probe():Cannot enable PCI device\n"); 1061 printk(KERN_ERR "%s:Cannot enable PCI device\n", __func__);
1091 goto PROBE_ERROR_2; 1062 goto PROBE_ERROR_2;
1092 } 1063 }
1093 1064
1094 /* Request the PCI register regions */ 1065 /* Request the PCI register regions */
1095 result = pci_request_regions(dev, ME4000_NAME); 1066 result = pci_request_regions(dev, ME4000_NAME);
1096 if (result < 0) { 1067 if (result < 0) {
1097 printk(KERN_ERR "me4000_probe():Cannot request I/O regions\n"); 1068 printk(KERN_ERR "%s:Cannot request I/O regions\n", __func__);
1098 goto PROBE_ERROR_2; 1069 goto PROBE_ERROR_2;
1099 } 1070 }
1100 1071
1101 /* Initialize board info */ 1072 /* Initialize board info */
1102 result = init_board_info(dev, board_info); 1073 result = init_board_info(dev, board_info);
1103 if (result) { 1074 if (result) {
1104 printk(KERN_ERR "me4000_probe():Cannot init baord info\n"); 1075 printk(KERN_ERR "%s:Cannot init baord info\n", __func__);
1105 goto PROBE_ERROR_3; 1076 goto PROBE_ERROR_3;
1106 } 1077 }
1107 1078
1108 /* Download the xilinx firmware */ 1079 /* Download the xilinx firmware */
1109 result = me4000_xilinx_download(board_info); 1080 result = me4000_xilinx_download(board_info);
1110 if (result) { 1081 if (result) {
1111 printk(KERN_ERR "me4000_probe:Can't download firmware\n"); 1082 printk(KERN_ERR "%s:Can't download firmware\n", __func__);
1112 goto PROBE_ERROR_3; 1083 goto PROBE_ERROR_3;
1113 } 1084 }
1114 1085
1115 /* Make a hardware reset */ 1086 /* Make a hardware reset */
1116 result = me4000_reset_board(board_info); 1087 result = me4000_reset_board(board_info);
1117 if (result) { 1088 if (result) {
1118 printk(KERN_ERR "me4000_probe:Can't reset board\n"); 1089 printk(KERN_ERR "%s :Can't reset board\n", __func__);
1119 goto PROBE_ERROR_3; 1090 goto PROBE_ERROR_3;
1120 } 1091 }
1121 1092
1122 /* Allocate analog output context structures */ 1093 /* Allocate analog output context structures */
1123 result = alloc_ao_contexts(board_info); 1094 result = alloc_ao_contexts(board_info);
1124 if (result) { 1095 if (result) {
1125 printk(KERN_ERR "me4000_probe():Cannot allocate ao contexts\n"); 1096 printk(KERN_ERR "%s:Cannot allocate ao contexts\n", __func__);
1126 goto PROBE_ERROR_3; 1097 goto PROBE_ERROR_3;
1127 } 1098 }
1128 1099
1129 /* Allocate analog input context */ 1100 /* Allocate analog input context */
1130 result = alloc_ai_context(board_info); 1101 result = alloc_ai_context(board_info);
1131 if (result) { 1102 if (result) {
1132 printk(KERN_ERR "me4000_probe():Cannot allocate ai context\n"); 1103 printk(KERN_ERR "%s:Cannot allocate ai context\n", __func__);
1133 goto PROBE_ERROR_4; 1104 goto PROBE_ERROR_4;
1134 } 1105 }
1135 1106
1136 /* Allocate digital I/O context */ 1107 /* Allocate digital I/O context */
1137 result = alloc_dio_context(board_info); 1108 result = alloc_dio_context(board_info);
1138 if (result) { 1109 if (result) {
1139 printk(KERN_ERR "me4000_probe():Cannot allocate dio context\n"); 1110 printk(KERN_ERR "%s:Cannot allocate dio context\n", __func__);
1140 goto PROBE_ERROR_5; 1111 goto PROBE_ERROR_5;
1141 } 1112 }
1142 1113
1143 /* Allocate counter context */ 1114 /* Allocate counter context */
1144 result = alloc_cnt_context(board_info); 1115 result = alloc_cnt_context(board_info);
1145 if (result) { 1116 if (result) {
1146 printk(KERN_ERR "me4000_probe():Cannot allocate cnt context\n"); 1117 printk(KERN_ERR "%s:Cannot allocate cnt context\n", __func__);
1147 goto PROBE_ERROR_6; 1118 goto PROBE_ERROR_6;
1148 } 1119 }
1149 1120
@@ -1151,36 +1122,36 @@ static int me4000_probe(struct pci_dev *dev, const struct pci_device_id *id)
1151 result = alloc_ext_int_context(board_info); 1122 result = alloc_ext_int_context(board_info);
1152 if (result) { 1123 if (result) {
1153 printk(KERN_ERR 1124 printk(KERN_ERR
1154 "me4000_probe():Cannot allocate ext_int context\n"); 1125 "%s:Cannot allocate ext_int context\n", __func__);
1155 goto PROBE_ERROR_7; 1126 goto PROBE_ERROR_7;
1156 } 1127 }
1157 1128
1158 return 0; 1129 return 0;
1159 1130
1160 PROBE_ERROR_7: 1131PROBE_ERROR_7:
1161 kfree(board_info->cnt_context); 1132 kfree(board_info->cnt_context);
1162 1133
1163 PROBE_ERROR_6: 1134PROBE_ERROR_6:
1164 kfree(board_info->dio_context); 1135 kfree(board_info->dio_context);
1165 1136
1166 PROBE_ERROR_5: 1137PROBE_ERROR_5:
1167 kfree(board_info->ai_context); 1138 kfree(board_info->ai_context);
1168 1139
1169 PROBE_ERROR_4: 1140PROBE_ERROR_4:
1170 release_ao_contexts(board_info); 1141 release_ao_contexts(board_info);
1171 1142
1172 PROBE_ERROR_3: 1143PROBE_ERROR_3:
1173 pci_release_regions(dev); 1144 pci_release_regions(dev);
1174 1145
1175 PROBE_ERROR_2: 1146PROBE_ERROR_2:
1176 list_del(&board_info->list); 1147 list_del(&board_info->list);
1177 kfree(board_info); 1148 kfree(board_info);
1178 1149
1179 PROBE_ERROR_1: 1150PROBE_ERROR_1:
1180 return result; 1151 return result;
1181} 1152}
1182 1153
1183static int me4000_xilinx_download(me4000_info_t * info) 1154static int me4000_xilinx_download(struct me4000_info *info)
1184{ 1155{
1185 int size = 0; 1156 int size = 0;
1186 u32 value = 0; 1157 u32 value = 0;
@@ -1211,7 +1182,7 @@ static int me4000_xilinx_download(me4000_info_t * info)
1211 /* Wait until /INIT pin is set */ 1182 /* Wait until /INIT pin is set */
1212 udelay(20); 1183 udelay(20);
1213 if (!inl(info->plx_regbase + PLX_INTCSR) & 0x20) { 1184 if (!inl(info->plx_regbase + PLX_INTCSR) & 0x20) {
1214 printk(KERN_ERR "me4000_xilinx_download():Can't init Xilinx\n"); 1185 printk(KERN_ERR "%s:Can't init Xilinx\n", __func__);
1215 return -EIO; 1186 return -EIO;
1216 } 1187 }
1217 1188
@@ -1232,7 +1203,7 @@ static int me4000_xilinx_download(me4000_info_t * info)
1232 /* Check if BUSY flag is low */ 1203 /* Check if BUSY flag is low */
1233 if (inl(info->plx_regbase + PLX_ICR) & 0x20) { 1204 if (inl(info->plx_regbase + PLX_ICR) & 0x20) {
1234 printk(KERN_ERR 1205 printk(KERN_ERR
1235 "me4000_xilinx_download():Xilinx is still busy (idx = %d)\n", 1206 "%s:Xilinx is still busy (idx = %d)\n", __func__,
1236 idx); 1207 idx);
1237 return -EIO; 1208 return -EIO;
1238 } 1209 }
@@ -1246,9 +1217,9 @@ static int me4000_xilinx_download(me4000_info_t * info)
1246 PDEBUG("me4000_xilinx_download():Download was successful\n"); 1217 PDEBUG("me4000_xilinx_download():Download was successful\n");
1247 } else { 1218 } else {
1248 printk(KERN_ERR 1219 printk(KERN_ERR
1249 "ME4000:me4000_xilinx_download():DONE flag is not set\n"); 1220 "ME4000:%s:DONE flag is not set\n", __func__);
1250 printk(KERN_ERR 1221 printk(KERN_ERR
1251 "ME4000:me4000_xilinx_download():Download not succesful\n"); 1222 "ME4000:%s:Download not succesful\n", __func__);
1252 return -EIO; 1223 return -EIO;
1253 } 1224 }
1254 1225
@@ -1260,7 +1231,7 @@ static int me4000_xilinx_download(me4000_info_t * info)
1260 return 0; 1231 return 0;
1261} 1232}
1262 1233
1263static int me4000_reset_board(me4000_info_t * info) 1234static int me4000_reset_board(struct me4000_info *info)
1264{ 1235{
1265 unsigned long icr; 1236 unsigned long icr;
1266 1237
@@ -1314,12 +1285,12 @@ static int me4000_open(struct inode *inode_p, struct file *file_p)
1314 int err = 0; 1285 int err = 0;
1315 int i; 1286 int i;
1316 struct list_head *ptr; 1287 struct list_head *ptr;
1317 me4000_info_t *board_info = NULL; 1288 struct me4000_info *board_info = NULL;
1318 me4000_ao_context_t *ao_context = NULL; 1289 struct me4000_ao_context *ao_context = NULL;
1319 me4000_ai_context_t *ai_context = NULL; 1290 struct me4000_ai_context *ai_context = NULL;
1320 me4000_dio_context_t *dio_context = NULL; 1291 struct me4000_dio_context *dio_context = NULL;
1321 me4000_cnt_context_t *cnt_context = NULL; 1292 struct me4000_cnt_context *cnt_context = NULL;
1322 me4000_ext_int_context_t *ext_int_context = NULL; 1293 struct me4000_ext_int_context *ext_int_context = NULL;
1323 1294
1324 CALL_PDEBUG("me4000_open() is executed\n"); 1295 CALL_PDEBUG("me4000_open() is executed\n");
1325 1296
@@ -1335,7 +1306,7 @@ static int me4000_open(struct inode *inode_p, struct file *file_p)
1335 /* Search for the board context */ 1306 /* Search for the board context */
1336 for (ptr = me4000_board_info_list.next, i = 0; 1307 for (ptr = me4000_board_info_list.next, i = 0;
1337 ptr != &me4000_board_info_list; ptr = ptr->next, i++) { 1308 ptr != &me4000_board_info_list; ptr = ptr->next, i++) {
1338 board_info = list_entry(ptr, me4000_info_t, list); 1309 board_info = list_entry(ptr, struct me4000_info, list);
1339 if (i == board) 1310 if (i == board)
1340 break; 1311 break;
1341 } 1312 }
@@ -1351,7 +1322,8 @@ static int me4000_open(struct inode *inode_p, struct file *file_p)
1351 for (ptr = board_info->ao_context_list.next, i = 0; 1322 for (ptr = board_info->ao_context_list.next, i = 0;
1352 ptr != &board_info->ao_context_list; 1323 ptr != &board_info->ao_context_list;
1353 ptr = ptr->next, i++) { 1324 ptr = ptr->next, i++) {
1354 ao_context = list_entry(ptr, me4000_ao_context_t, list); 1325 ao_context = list_entry(ptr, struct me4000_ao_context,
1326 list);
1355 if (i == dev) 1327 if (i == dev)
1356 break; 1328 break;
1357 } 1329 }
@@ -1415,7 +1387,7 @@ static int me4000_open(struct inode *inode_p, struct file *file_p)
1415 /* Search for the board context */ 1387 /* Search for the board context */
1416 for (ptr = me4000_board_info_list.next, i = 0; 1388 for (ptr = me4000_board_info_list.next, i = 0;
1417 ptr != &me4000_board_info_list; ptr = ptr->next, i++) { 1389 ptr != &me4000_board_info_list; ptr = ptr->next, i++) {
1418 board_info = list_entry(ptr, me4000_info_t, list); 1390 board_info = list_entry(ptr, struct me4000_info, list);
1419 if (i == board) 1391 if (i == board)
1420 break; 1392 break;
1421 } 1393 }
@@ -1469,7 +1441,7 @@ static int me4000_open(struct inode *inode_p, struct file *file_p)
1469 /* Search for the board context */ 1441 /* Search for the board context */
1470 for (ptr = me4000_board_info_list.next; 1442 for (ptr = me4000_board_info_list.next;
1471 ptr != &me4000_board_info_list; ptr = ptr->next) { 1443 ptr != &me4000_board_info_list; ptr = ptr->next) {
1472 board_info = list_entry(ptr, me4000_info_t, list); 1444 board_info = list_entry(ptr, struct me4000_info, list);
1473 if (board_info->board_count == board) 1445 if (board_info->board_count == board)
1474 break; 1446 break;
1475 } 1447 }
@@ -1514,7 +1486,7 @@ static int me4000_open(struct inode *inode_p, struct file *file_p)
1514 /* Search for the board context */ 1486 /* Search for the board context */
1515 for (ptr = me4000_board_info_list.next; 1487 for (ptr = me4000_board_info_list.next;
1516 ptr != &me4000_board_info_list; ptr = ptr->next) { 1488 ptr != &me4000_board_info_list; ptr = ptr->next) {
1517 board_info = list_entry(ptr, me4000_info_t, list); 1489 board_info = list_entry(ptr, struct me4000_info, list);
1518 if (board_info->board_count == board) 1490 if (board_info->board_count == board)
1519 break; 1491 break;
1520 } 1492 }
@@ -1557,7 +1529,7 @@ static int me4000_open(struct inode *inode_p, struct file *file_p)
1557 /* Search for the board context */ 1529 /* Search for the board context */
1558 for (ptr = me4000_board_info_list.next; 1530 for (ptr = me4000_board_info_list.next;
1559 ptr != &me4000_board_info_list; ptr = ptr->next) { 1531 ptr != &me4000_board_info_list; ptr = ptr->next) {
1560 board_info = list_entry(ptr, me4000_info_t, list); 1532 board_info = list_entry(ptr, struct me4000_info, list);
1561 if (board_info->board_count == board) 1533 if (board_info->board_count == board)
1562 break; 1534 break;
1563 } 1535 }
@@ -1613,11 +1585,11 @@ static int me4000_open(struct inode *inode_p, struct file *file_p)
1613 1585
1614static int me4000_release(struct inode *inode_p, struct file *file_p) 1586static int me4000_release(struct inode *inode_p, struct file *file_p)
1615{ 1587{
1616 me4000_ao_context_t *ao_context; 1588 struct me4000_ao_context *ao_context;
1617 me4000_ai_context_t *ai_context; 1589 struct me4000_ai_context *ai_context;
1618 me4000_dio_context_t *dio_context; 1590 struct me4000_dio_context *dio_context;
1619 me4000_cnt_context_t *cnt_context; 1591 struct me4000_cnt_context *cnt_context;
1620 me4000_ext_int_context_t *ext_int_context; 1592 struct me4000_ext_int_context *ext_int_context;
1621 1593
1622 CALL_PDEBUG("me4000_release() is executed\n"); 1594 CALL_PDEBUG("me4000_release() is executed\n");
1623 1595
@@ -1677,7 +1649,7 @@ static int me4000_release(struct inode *inode_p, struct file *file_p)
1677 1649
1678/*------------------------------- Analog output stuff --------------------------------------*/ 1650/*------------------------------- Analog output stuff --------------------------------------*/
1679 1651
1680static int me4000_ao_prepare(me4000_ao_context_t * ao_context) 1652static int me4000_ao_prepare(struct me4000_ao_context *ao_context)
1681{ 1653{
1682 unsigned long flags; 1654 unsigned long flags;
1683 1655
@@ -1756,7 +1728,7 @@ static int me4000_ao_prepare(me4000_ao_context_t * ao_context)
1756 return 0; 1728 return 0;
1757} 1729}
1758 1730
1759static int me4000_ao_reset(me4000_ao_context_t * ao_context) 1731static int me4000_ao_reset(struct me4000_ao_context *ao_context)
1760{ 1732{
1761 u32 tmp; 1733 u32 tmp;
1762 wait_queue_head_t queue; 1734 wait_queue_head_t queue;
@@ -1777,9 +1749,10 @@ static int me4000_ao_reset(me4000_ao_context_t * ao_context)
1777 tmp |= ME4000_AO_CTRL_BIT_IMMEDIATE_STOP; 1749 tmp |= ME4000_AO_CTRL_BIT_IMMEDIATE_STOP;
1778 me4000_outl(tmp, ao_context->ctrl_reg); 1750 me4000_outl(tmp, ao_context->ctrl_reg);
1779 1751
1780 while (inl(ao_context->status_reg) & ME4000_AO_STATUS_BIT_FSM) { 1752 wait_event_timeout(queue,
1781 sleep_on_timeout(&queue, 1); 1753 (inl(ao_context->status_reg) &
1782 } 1754 ME4000_AO_STATUS_BIT_FSM) == 0,
1755 1);
1783 1756
1784 /* Set to transparent mode */ 1757 /* Set to transparent mode */
1785 me4000_ao_simultaneous_disable(ao_context); 1758 me4000_ao_simultaneous_disable(ao_context);
@@ -1812,9 +1785,10 @@ static int me4000_ao_reset(me4000_ao_context_t * ao_context)
1812 me4000_outl(tmp, ao_context->ctrl_reg); 1785 me4000_outl(tmp, ao_context->ctrl_reg);
1813 spin_unlock_irqrestore(&ao_context->int_lock, flags); 1786 spin_unlock_irqrestore(&ao_context->int_lock, flags);
1814 1787
1815 while (inl(ao_context->status_reg) & ME4000_AO_STATUS_BIT_FSM) { 1788 wait_event_timeout(queue,
1816 sleep_on_timeout(&queue, 1); 1789 (inl(ao_context->status_reg) &
1817 } 1790 ME4000_AO_STATUS_BIT_FSM) == 0,
1791 1);
1818 1792
1819 /* Clear the circular buffer */ 1793 /* Clear the circular buffer */
1820 ao_context->circ_buf.head = 0; 1794 ao_context->circ_buf.head = 0;
@@ -1853,9 +1827,9 @@ static int me4000_ao_reset(me4000_ao_context_t * ao_context)
1853} 1827}
1854 1828
1855static ssize_t me4000_ao_write_sing(struct file *filep, const char *buff, 1829static ssize_t me4000_ao_write_sing(struct file *filep, const char *buff,
1856 size_t cnt, loff_t * offp) 1830 size_t cnt, loff_t *offp)
1857{ 1831{
1858 me4000_ao_context_t *ao_context = filep->private_data; 1832 struct me4000_ao_context *ao_context = filep->private_data;
1859 u32 value; 1833 u32 value;
1860 const u16 *buffer = (const u16 *)buff; 1834 const u16 *buffer = (const u16 *)buff;
1861 1835
@@ -1863,13 +1837,13 @@ static ssize_t me4000_ao_write_sing(struct file *filep, const char *buff,
1863 1837
1864 if (cnt != 2) { 1838 if (cnt != 2) {
1865 printk(KERN_ERR 1839 printk(KERN_ERR
1866 "me4000_ao_write_sing():Write count is not 2\n"); 1840 "%s:Write count is not 2\n", __func__);
1867 return -EINVAL; 1841 return -EINVAL;
1868 } 1842 }
1869 1843
1870 if (get_user(value, buffer)) { 1844 if (get_user(value, buffer)) {
1871 printk(KERN_ERR 1845 printk(KERN_ERR
1872 "me4000_ao_write_sing():Cannot copy data from user\n"); 1846 "%s:Cannot copy data from user\n", __func__);
1873 return -EFAULT; 1847 return -EFAULT;
1874 } 1848 }
1875 1849
@@ -1879,9 +1853,9 @@ static ssize_t me4000_ao_write_sing(struct file *filep, const char *buff,
1879} 1853}
1880 1854
1881static ssize_t me4000_ao_write_wrap(struct file *filep, const char *buff, 1855static ssize_t me4000_ao_write_wrap(struct file *filep, const char *buff,
1882 size_t cnt, loff_t * offp) 1856 size_t cnt, loff_t *offp)
1883{ 1857{
1884 me4000_ao_context_t *ao_context = filep->private_data; 1858 struct me4000_ao_context *ao_context = filep->private_data;
1885 size_t i; 1859 size_t i;
1886 u32 value; 1860 u32 value;
1887 u32 tmp; 1861 u32 tmp;
@@ -1893,13 +1867,13 @@ static ssize_t me4000_ao_write_wrap(struct file *filep, const char *buff,
1893 /* Check if a conversion is already running */ 1867 /* Check if a conversion is already running */
1894 if (inl(ao_context->status_reg) & ME4000_AO_STATUS_BIT_FSM) { 1868 if (inl(ao_context->status_reg) & ME4000_AO_STATUS_BIT_FSM) {
1895 printk(KERN_ERR 1869 printk(KERN_ERR
1896 "ME4000:me4000_ao_write_wrap():There is already a conversion running\n"); 1870 "%s:There is already a conversion running\n", __func__);
1897 return -EBUSY; 1871 return -EBUSY;
1898 } 1872 }
1899 1873
1900 if (count > ME4000_AO_FIFO_COUNT) { 1874 if (count > ME4000_AO_FIFO_COUNT) {
1901 printk(KERN_ERR 1875 printk(KERN_ERR
1902 "me4000_ao_write_wrap():Can't load more than %d values\n", 1876 "%s:Can't load more than %d values\n", __func__,
1903 ME4000_AO_FIFO_COUNT); 1877 ME4000_AO_FIFO_COUNT);
1904 return -ENOSPC; 1878 return -ENOSPC;
1905 } 1879 }
@@ -1914,7 +1888,7 @@ static ssize_t me4000_ao_write_wrap(struct file *filep, const char *buff,
1914 for (i = 0; i < count; i++) { 1888 for (i = 0; i < count; i++) {
1915 if (get_user(value, buffer + i)) { 1889 if (get_user(value, buffer + i)) {
1916 printk(KERN_ERR 1890 printk(KERN_ERR
1917 "me4000_ao_write_single():Cannot copy data from user\n"); 1891 "%s:Cannot copy data from user\n", __func__);
1918 return -EFAULT; 1892 return -EFAULT;
1919 } 1893 }
1920 if (((ao_context->fifo_reg & 0xFF) == ME4000_AO_01_FIFO_REG) 1894 if (((ao_context->fifo_reg & 0xFF) == ME4000_AO_01_FIFO_REG)
@@ -1928,9 +1902,9 @@ static ssize_t me4000_ao_write_wrap(struct file *filep, const char *buff,
1928} 1902}
1929 1903
1930static ssize_t me4000_ao_write_cont(struct file *filep, const char *buff, 1904static ssize_t me4000_ao_write_cont(struct file *filep, const char *buff,
1931 size_t cnt, loff_t * offp) 1905 size_t cnt, loff_t *offp)
1932{ 1906{
1933 me4000_ao_context_t *ao_context = filep->private_data; 1907 struct me4000_ao_context *ao_context = filep->private_data;
1934 const u16 *buffer = (const u16 *)buff; 1908 const u16 *buffer = (const u16 *)buff;
1935 size_t count = cnt / 2; 1909 size_t count = cnt / 2;
1936 unsigned long flags; 1910 unsigned long flags;
@@ -2154,9 +2128,9 @@ static ssize_t me4000_ao_write_cont(struct file *filep, const char *buff,
2154 return 2 * ret; 2128 return 2 * ret;
2155} 2129}
2156 2130
2157static unsigned int me4000_ao_poll_cont(struct file *file_p, poll_table * wait) 2131static unsigned int me4000_ao_poll_cont(struct file *file_p, poll_table *wait)
2158{ 2132{
2159 me4000_ao_context_t *ao_context; 2133 struct me4000_ao_context *ao_context;
2160 unsigned long mask = 0; 2134 unsigned long mask = 0;
2161 2135
2162 CALL_PDEBUG("me4000_ao_poll_cont() is executed\n"); 2136 CALL_PDEBUG("me4000_ao_poll_cont() is executed\n");
@@ -2177,7 +2151,7 @@ static unsigned int me4000_ao_poll_cont(struct file *file_p, poll_table * wait)
2177static int me4000_ao_fsync_cont(struct file *file_p, struct dentry *dentry_p, 2151static int me4000_ao_fsync_cont(struct file *file_p, struct dentry *dentry_p,
2178 int datasync) 2152 int datasync)
2179{ 2153{
2180 me4000_ao_context_t *ao_context; 2154 struct me4000_ao_context *ao_context;
2181 wait_queue_head_t queue; 2155 wait_queue_head_t queue;
2182 2156
2183 CALL_PDEBUG("me4000_ao_fsync_cont() is executed\n"); 2157 CALL_PDEBUG("me4000_ao_fsync_cont() is executed\n");
@@ -2187,15 +2161,19 @@ static int me4000_ao_fsync_cont(struct file *file_p, struct dentry *dentry_p,
2187 2161
2188 while (inl(ao_context->status_reg) & ME4000_AO_STATUS_BIT_FSM) { 2162 while (inl(ao_context->status_reg) & ME4000_AO_STATUS_BIT_FSM) {
2189 interruptible_sleep_on_timeout(&queue, 1); 2163 interruptible_sleep_on_timeout(&queue, 1);
2164 wait_event_interruptible_timeout(queue,
2165 !(inl(ao_context->status_reg) & ME4000_AO_STATUS_BIT_FSM),
2166 1);
2190 if (ao_context->pipe_flag) { 2167 if (ao_context->pipe_flag) {
2191 printk(KERN_ERR 2168 printk(KERN_ERR
2192 "me4000_ao_fsync_cont():Broken pipe detected\n"); 2169 "%s:Broken pipe detected\n", __func__);
2193 return -EPIPE; 2170 return -EPIPE;
2194 } 2171 }
2195 2172
2196 if (signal_pending(current)) { 2173 if (signal_pending(current)) {
2197 printk(KERN_ERR 2174 printk(KERN_ERR
2198 "me4000_ao_fsync_cont():Wait on state machine interrupted\n"); 2175 "%s:Wait on state machine interrupted\n",
2176 __func__);
2199 return -EINTR; 2177 return -EINTR;
2200 } 2178 }
2201 } 2179 }
@@ -2206,7 +2184,7 @@ static int me4000_ao_fsync_cont(struct file *file_p, struct dentry *dentry_p,
2206static int me4000_ao_ioctl_sing(struct inode *inode_p, struct file *file_p, 2184static int me4000_ao_ioctl_sing(struct inode *inode_p, struct file *file_p,
2207 unsigned int service, unsigned long arg) 2185 unsigned int service, unsigned long arg)
2208{ 2186{
2209 me4000_ao_context_t *ao_context; 2187 struct me4000_ao_context *ao_context;
2210 2188
2211 CALL_PDEBUG("me4000_ao_ioctl_sing() is executed\n"); 2189 CALL_PDEBUG("me4000_ao_ioctl_sing() is executed\n");
2212 2190
@@ -2229,7 +2207,7 @@ static int me4000_ao_ioctl_sing(struct inode *inode_p, struct file *file_p,
2229 case ME4000_AO_PRELOAD_UPDATE: 2207 case ME4000_AO_PRELOAD_UPDATE:
2230 return me4000_ao_preload_update(ao_context); 2208 return me4000_ao_preload_update(ao_context);
2231 case ME4000_GET_USER_INFO: 2209 case ME4000_GET_USER_INFO:
2232 return me4000_get_user_info((me4000_user_info_t *) arg, 2210 return me4000_get_user_info((struct me4000_user_info *)arg,
2233 ao_context->board_info); 2211 ao_context->board_info);
2234 case ME4000_AO_SIMULTANEOUS_EX_TRIG: 2212 case ME4000_AO_SIMULTANEOUS_EX_TRIG:
2235 return me4000_ao_simultaneous_ex_trig(ao_context); 2213 return me4000_ao_simultaneous_ex_trig(ao_context);
@@ -2239,8 +2217,9 @@ static int me4000_ao_ioctl_sing(struct inode *inode_p, struct file *file_p,
2239 return me4000_ao_simultaneous_disable(ao_context); 2217 return me4000_ao_simultaneous_disable(ao_context);
2240 case ME4000_AO_SIMULTANEOUS_UPDATE: 2218 case ME4000_AO_SIMULTANEOUS_UPDATE:
2241 return 2219 return
2242 me4000_ao_simultaneous_update((me4000_ao_channel_list_t *) 2220 me4000_ao_simultaneous_update(
2243 arg, ao_context); 2221 (struct me4000_ao_channel_list *)arg,
2222 ao_context);
2244 case ME4000_AO_EX_TRIG_TIMEOUT: 2223 case ME4000_AO_EX_TRIG_TIMEOUT:
2245 return me4000_ao_ex_trig_timeout((unsigned long *)arg, 2224 return me4000_ao_ex_trig_timeout((unsigned long *)arg,
2246 ao_context); 2225 ao_context);
@@ -2258,7 +2237,7 @@ static int me4000_ao_ioctl_sing(struct inode *inode_p, struct file *file_p,
2258static int me4000_ao_ioctl_wrap(struct inode *inode_p, struct file *file_p, 2237static int me4000_ao_ioctl_wrap(struct inode *inode_p, struct file *file_p,
2259 unsigned int service, unsigned long arg) 2238 unsigned int service, unsigned long arg)
2260{ 2239{
2261 me4000_ao_context_t *ao_context; 2240 struct me4000_ao_context *ao_context;
2262 2241
2263 CALL_PDEBUG("me4000_ao_ioctl_wrap() is executed\n"); 2242 CALL_PDEBUG("me4000_ao_ioctl_wrap() is executed\n");
2264 2243
@@ -2287,7 +2266,7 @@ static int me4000_ao_ioctl_wrap(struct inode *inode_p, struct file *file_p,
2287 case ME4000_AO_EX_TRIG_DISABLE: 2266 case ME4000_AO_EX_TRIG_DISABLE:
2288 return me4000_ao_ex_trig_disable(ao_context); 2267 return me4000_ao_ex_trig_disable(ao_context);
2289 case ME4000_GET_USER_INFO: 2268 case ME4000_GET_USER_INFO:
2290 return me4000_get_user_info((me4000_user_info_t *) arg, 2269 return me4000_get_user_info((struct me4000_user_info *)arg,
2291 ao_context->board_info); 2270 ao_context->board_info);
2292 case ME4000_AO_FSM_STATE: 2271 case ME4000_AO_FSM_STATE:
2293 return me4000_ao_fsm_state((int *)arg, ao_context); 2272 return me4000_ao_fsm_state((int *)arg, ao_context);
@@ -2310,7 +2289,7 @@ static int me4000_ao_ioctl_wrap(struct inode *inode_p, struct file *file_p,
2310static int me4000_ao_ioctl_cont(struct inode *inode_p, struct file *file_p, 2289static int me4000_ao_ioctl_cont(struct inode *inode_p, struct file *file_p,
2311 unsigned int service, unsigned long arg) 2290 unsigned int service, unsigned long arg)
2312{ 2291{
2313 me4000_ao_context_t *ao_context; 2292 struct me4000_ao_context *ao_context;
2314 2293
2315 CALL_PDEBUG("me4000_ao_ioctl_cont() is executed\n"); 2294 CALL_PDEBUG("me4000_ao_ioctl_cont() is executed\n");
2316 2295
@@ -2345,7 +2324,7 @@ static int me4000_ao_ioctl_cont(struct inode *inode_p, struct file *file_p,
2345 case ME4000_AO_FSM_STATE: 2324 case ME4000_AO_FSM_STATE:
2346 return me4000_ao_fsm_state((int *)arg, ao_context); 2325 return me4000_ao_fsm_state((int *)arg, ao_context);
2347 case ME4000_GET_USER_INFO: 2326 case ME4000_GET_USER_INFO:
2348 return me4000_get_user_info((me4000_user_info_t *) arg, 2327 return me4000_get_user_info((struct me4000_user_info *)arg,
2349 ao_context->board_info); 2328 ao_context->board_info);
2350 case ME4000_AO_SYNCHRONOUS_EX_TRIG: 2329 case ME4000_AO_SYNCHRONOUS_EX_TRIG:
2351 return me4000_ao_synchronous_ex_trig(ao_context); 2330 return me4000_ao_synchronous_ex_trig(ao_context);
@@ -2362,7 +2341,8 @@ static int me4000_ao_ioctl_cont(struct inode *inode_p, struct file *file_p,
2362 return 0; 2341 return 0;
2363} 2342}
2364 2343
2365static int me4000_ao_start(unsigned long *arg, me4000_ao_context_t * ao_context) 2344static int me4000_ao_start(unsigned long *arg,
2345 struct me4000_ao_context *ao_context)
2366{ 2346{
2367 u32 tmp; 2347 u32 tmp;
2368 wait_queue_head_t queue; 2348 wait_queue_head_t queue;
@@ -2412,7 +2392,7 @@ static int me4000_ao_start(unsigned long *arg, me4000_ao_context_t * ao_context)
2412 return 0; 2392 return 0;
2413} 2393}
2414 2394
2415static int me4000_ao_stop(me4000_ao_context_t * ao_context) 2395static int me4000_ao_stop(struct me4000_ao_context *ao_context)
2416{ 2396{
2417 u32 tmp; 2397 u32 tmp;
2418 wait_queue_head_t queue; 2398 wait_queue_head_t queue;
@@ -2445,7 +2425,7 @@ static int me4000_ao_stop(me4000_ao_context_t * ao_context)
2445 return 0; 2425 return 0;
2446} 2426}
2447 2427
2448static int me4000_ao_immediate_stop(me4000_ao_context_t * ao_context) 2428static int me4000_ao_immediate_stop(struct me4000_ao_context *ao_context)
2449{ 2429{
2450 u32 tmp; 2430 u32 tmp;
2451 wait_queue_head_t queue; 2431 wait_queue_head_t queue;
@@ -2477,8 +2457,8 @@ static int me4000_ao_immediate_stop(me4000_ao_context_t * ao_context)
2477 return 0; 2457 return 0;
2478} 2458}
2479 2459
2480static int me4000_ao_timer_set_divisor(u32 * arg, 2460static int me4000_ao_timer_set_divisor(u32 *arg,
2481 me4000_ao_context_t * ao_context) 2461 struct me4000_ao_context *ao_context)
2482{ 2462{
2483 u32 divisor; 2463 u32 divisor;
2484 u32 tmp; 2464 u32 tmp;
@@ -2518,7 +2498,7 @@ static int me4000_ao_timer_set_divisor(u32 * arg,
2518} 2498}
2519 2499
2520static int me4000_ao_ex_trig_set_edge(int *arg, 2500static int me4000_ao_ex_trig_set_edge(int *arg,
2521 me4000_ao_context_t * ao_context) 2501 struct me4000_ao_context *ao_context)
2522{ 2502{
2523 int mode; 2503 int mode;
2524 u32 tmp; 2504 u32 tmp;
@@ -2569,7 +2549,7 @@ static int me4000_ao_ex_trig_set_edge(int *arg,
2569 return 0; 2549 return 0;
2570} 2550}
2571 2551
2572static int me4000_ao_ex_trig_enable(me4000_ao_context_t * ao_context) 2552static int me4000_ao_ex_trig_enable(struct me4000_ao_context *ao_context)
2573{ 2553{
2574 u32 tmp; 2554 u32 tmp;
2575 unsigned long flags; 2555 unsigned long flags;
@@ -2593,7 +2573,7 @@ static int me4000_ao_ex_trig_enable(me4000_ao_context_t * ao_context)
2593 return 0; 2573 return 0;
2594} 2574}
2595 2575
2596static int me4000_ao_ex_trig_disable(me4000_ao_context_t * ao_context) 2576static int me4000_ao_ex_trig_disable(struct me4000_ao_context *ao_context)
2597{ 2577{
2598 u32 tmp; 2578 u32 tmp;
2599 unsigned long flags; 2579 unsigned long flags;
@@ -2617,7 +2597,7 @@ static int me4000_ao_ex_trig_disable(me4000_ao_context_t * ao_context)
2617 return 0; 2597 return 0;
2618} 2598}
2619 2599
2620static int me4000_ao_simultaneous_disable(me4000_ao_context_t * ao_context) 2600static int me4000_ao_simultaneous_disable(struct me4000_ao_context *ao_context)
2621{ 2601{
2622 u32 tmp; 2602 u32 tmp;
2623 2603
@@ -2643,7 +2623,7 @@ static int me4000_ao_simultaneous_disable(me4000_ao_context_t * ao_context)
2643 return 0; 2623 return 0;
2644} 2624}
2645 2625
2646static int me4000_ao_simultaneous_ex_trig(me4000_ao_context_t * ao_context) 2626static int me4000_ao_simultaneous_ex_trig(struct me4000_ao_context *ao_context)
2647{ 2627{
2648 u32 tmp; 2628 u32 tmp;
2649 2629
@@ -2659,7 +2639,7 @@ static int me4000_ao_simultaneous_ex_trig(me4000_ao_context_t * ao_context)
2659 return 0; 2639 return 0;
2660} 2640}
2661 2641
2662static int me4000_ao_simultaneous_sw(me4000_ao_context_t * ao_context) 2642static int me4000_ao_simultaneous_sw(struct me4000_ao_context *ao_context)
2663{ 2643{
2664 u32 tmp; 2644 u32 tmp;
2665 2645
@@ -2675,13 +2655,13 @@ static int me4000_ao_simultaneous_sw(me4000_ao_context_t * ao_context)
2675 return 0; 2655 return 0;
2676} 2656}
2677 2657
2678static int me4000_ao_preload(me4000_ao_context_t * ao_context) 2658static int me4000_ao_preload(struct me4000_ao_context *ao_context)
2679{ 2659{
2680 CALL_PDEBUG("me4000_ao_preload() is executed\n"); 2660 CALL_PDEBUG("me4000_ao_preload() is executed\n");
2681 return me4000_ao_simultaneous_sw(ao_context); 2661 return me4000_ao_simultaneous_sw(ao_context);
2682} 2662}
2683 2663
2684static int me4000_ao_preload_update(me4000_ao_context_t * ao_context) 2664static int me4000_ao_preload_update(struct me4000_ao_context *ao_context)
2685{ 2665{
2686 u32 tmp; 2666 u32 tmp;
2687 u32 ctrl; 2667 u32 ctrl;
@@ -2705,10 +2685,12 @@ static int me4000_ao_preload_update(me4000_ao_context_t * ao_context)
2705 if (! 2685 if (!
2706 (tmp & 2686 (tmp &
2707 (0x1 << 2687 (0x1 <<
2708 (((me4000_ao_context_t *) entry)->index + 16)))) { 2688 (((struct me4000_ao_context *)entry)->index
2689 + 16)))) {
2709 tmp &= 2690 tmp &=
2710 ~(0x1 << 2691 ~(0x1 <<
2711 (((me4000_ao_context_t *) entry)->index)); 2692 (((struct me4000_ao_context *)entry)->
2693 index));
2712 } 2694 }
2713 } 2695 }
2714 } 2696 }
@@ -2718,18 +2700,19 @@ static int me4000_ao_preload_update(me4000_ao_context_t * ao_context)
2718 return 0; 2700 return 0;
2719} 2701}
2720 2702
2721static int me4000_ao_simultaneous_update(me4000_ao_channel_list_t * arg, 2703static int me4000_ao_simultaneous_update(struct me4000_ao_channel_list *arg,
2722 me4000_ao_context_t * ao_context) 2704 struct me4000_ao_context *ao_context)
2723{ 2705{
2724 int err; 2706 int err;
2725 int i; 2707 int i;
2726 u32 tmp; 2708 u32 tmp;
2727 me4000_ao_channel_list_t channels; 2709 struct me4000_ao_channel_list channels;
2728 2710
2729 CALL_PDEBUG("me4000_ao_simultaneous_update() is executed\n"); 2711 CALL_PDEBUG("me4000_ao_simultaneous_update() is executed\n");
2730 2712
2731 /* Copy data from user */ 2713 /* Copy data from user */
2732 err = copy_from_user(&channels, arg, sizeof(me4000_ao_channel_list_t)); 2714 err = copy_from_user(&channels, arg,
2715 sizeof(struct me4000_ao_channel_list));
2733 if (err) { 2716 if (err) {
2734 printk(KERN_ERR 2717 printk(KERN_ERR
2735 "ME4000:me4000_ao_simultaneous_update():Can't copy command\n"); 2718 "ME4000:me4000_ao_simultaneous_update():Can't copy command\n");
@@ -2737,13 +2720,12 @@ static int me4000_ao_simultaneous_update(me4000_ao_channel_list_t * arg,
2737 } 2720 }
2738 2721
2739 channels.list = 2722 channels.list =
2740 kmalloc(sizeof(unsigned long) * channels.count, GFP_KERNEL); 2723 kzalloc(sizeof(unsigned long) * channels.count, GFP_KERNEL);
2741 if (!channels.list) { 2724 if (!channels.list) {
2742 printk(KERN_ERR 2725 printk(KERN_ERR
2743 "ME4000:me4000_ao_simultaneous_update():Can't get buffer\n"); 2726 "ME4000:me4000_ao_simultaneous_update():Can't get buffer\n");
2744 return -ENOMEM; 2727 return -ENOMEM;
2745 } 2728 }
2746 memset(channels.list, 0, sizeof(unsigned long) * channels.count);
2747 2729
2748 /* Copy channel list from user */ 2730 /* Copy channel list from user */
2749 err = 2731 err =
@@ -2777,7 +2759,7 @@ static int me4000_ao_simultaneous_update(me4000_ao_channel_list_t * arg,
2777 return 0; 2759 return 0;
2778} 2760}
2779 2761
2780static int me4000_ao_synchronous_ex_trig(me4000_ao_context_t * ao_context) 2762static int me4000_ao_synchronous_ex_trig(struct me4000_ao_context *ao_context)
2781{ 2763{
2782 u32 tmp; 2764 u32 tmp;
2783 unsigned long flags; 2765 unsigned long flags;
@@ -2813,7 +2795,7 @@ static int me4000_ao_synchronous_ex_trig(me4000_ao_context_t * ao_context)
2813 return 0; 2795 return 0;
2814} 2796}
2815 2797
2816static int me4000_ao_synchronous_sw(me4000_ao_context_t * ao_context) 2798static int me4000_ao_synchronous_sw(struct me4000_ao_context *ao_context)
2817{ 2799{
2818 u32 tmp; 2800 u32 tmp;
2819 unsigned long flags; 2801 unsigned long flags;
@@ -2848,13 +2830,13 @@ static int me4000_ao_synchronous_sw(me4000_ao_context_t * ao_context)
2848 return 0; 2830 return 0;
2849} 2831}
2850 2832
2851static int me4000_ao_synchronous_disable(me4000_ao_context_t * ao_context) 2833static int me4000_ao_synchronous_disable(struct me4000_ao_context *ao_context)
2852{ 2834{
2853 return me4000_ao_simultaneous_disable(ao_context); 2835 return me4000_ao_simultaneous_disable(ao_context);
2854} 2836}
2855 2837
2856static int me4000_ao_get_free_buffer(unsigned long *arg, 2838static int me4000_ao_get_free_buffer(unsigned long *arg,
2857 me4000_ao_context_t * ao_context) 2839 struct me4000_ao_context *ao_context)
2858{ 2840{
2859 unsigned long c; 2841 unsigned long c;
2860 int err; 2842 int err;
@@ -2864,7 +2846,7 @@ static int me4000_ao_get_free_buffer(unsigned long *arg,
2864 err = copy_to_user(arg, &c, sizeof(unsigned long)); 2846 err = copy_to_user(arg, &c, sizeof(unsigned long));
2865 if (err) { 2847 if (err) {
2866 printk(KERN_ERR 2848 printk(KERN_ERR
2867 "ME4000:me4000_ao_get_free_buffer():Can't copy to user space\n"); 2849 "%s:Can't copy to user space\n", __func__);
2868 return -EFAULT; 2850 return -EFAULT;
2869 } 2851 }
2870 2852
@@ -2872,7 +2854,7 @@ static int me4000_ao_get_free_buffer(unsigned long *arg,
2872} 2854}
2873 2855
2874static int me4000_ao_ex_trig_timeout(unsigned long *arg, 2856static int me4000_ao_ex_trig_timeout(unsigned long *arg,
2875 me4000_ao_context_t * ao_context) 2857 struct me4000_ao_context *ao_context)
2876{ 2858{
2877 u32 tmp; 2859 u32 tmp;
2878 wait_queue_head_t queue; 2860 wait_queue_head_t queue;
@@ -2928,7 +2910,7 @@ static int me4000_ao_ex_trig_timeout(unsigned long *arg,
2928 return 0; 2910 return 0;
2929} 2911}
2930 2912
2931static int me4000_ao_enable_do(me4000_ao_context_t * ao_context) 2913static int me4000_ao_enable_do(struct me4000_ao_context *ao_context)
2932{ 2914{
2933 u32 tmp; 2915 u32 tmp;
2934 unsigned long flags; 2916 unsigned long flags;
@@ -2959,7 +2941,7 @@ static int me4000_ao_enable_do(me4000_ao_context_t * ao_context)
2959 return 0; 2941 return 0;
2960} 2942}
2961 2943
2962static int me4000_ao_disable_do(me4000_ao_context_t * ao_context) 2944static int me4000_ao_disable_do(struct me4000_ao_context *ao_context)
2963{ 2945{
2964 u32 tmp; 2946 u32 tmp;
2965 unsigned long flags; 2947 unsigned long flags;
@@ -2989,7 +2971,7 @@ static int me4000_ao_disable_do(me4000_ao_context_t * ao_context)
2989 return 0; 2971 return 0;
2990} 2972}
2991 2973
2992static int me4000_ao_fsm_state(int *arg, me4000_ao_context_t * ao_context) 2974static int me4000_ao_fsm_state(int *arg, struct me4000_ao_context *ao_context)
2993{ 2975{
2994 unsigned long tmp; 2976 unsigned long tmp;
2995 2977
@@ -3012,9 +2994,9 @@ static int me4000_ao_fsm_state(int *arg, me4000_ao_context_t * ao_context)
3012 return 0; 2994 return 0;
3013} 2995}
3014 2996
3015/*------------------------------- Analog input stuff --------------------------------------*/ 2997/*------------------------- Analog input stuff -------------------------------*/
3016 2998
3017static int me4000_ai_prepare(me4000_ai_context_t * ai_context) 2999static int me4000_ai_prepare(struct me4000_ai_context *ai_context)
3018{ 3000{
3019 wait_queue_head_t queue; 3001 wait_queue_head_t queue;
3020 int err; 3002 int err;
@@ -3057,14 +3039,13 @@ static int me4000_ai_prepare(me4000_ai_context_t * ai_context)
3057 3039
3058 /* Allocate circular buffer */ 3040 /* Allocate circular buffer */
3059 ai_context->circ_buf.buf = 3041 ai_context->circ_buf.buf =
3060 kmalloc(ME4000_AI_BUFFER_SIZE, GFP_KERNEL); 3042 kzalloc(ME4000_AI_BUFFER_SIZE, GFP_KERNEL);
3061 if (!ai_context->circ_buf.buf) { 3043 if (!ai_context->circ_buf.buf) {
3062 printk(KERN_ERR 3044 printk(KERN_ERR
3063 "ME4000:me4000_ai_prepare():Can't get circular buffer\n"); 3045 "ME4000:me4000_ai_prepare():Can't get circular buffer\n");
3064 free_irq(ai_context->irq, ai_context); 3046 free_irq(ai_context->irq, ai_context);
3065 return -ENOMEM; 3047 return -ENOMEM;
3066 } 3048 }
3067 memset(ai_context->circ_buf.buf, 0, ME4000_AI_BUFFER_SIZE);
3068 3049
3069 /* Clear the circular buffer */ 3050 /* Clear the circular buffer */
3070 ai_context->circ_buf.head = 0; 3051 ai_context->circ_buf.head = 0;
@@ -3074,7 +3055,7 @@ static int me4000_ai_prepare(me4000_ai_context_t * ai_context)
3074 return 0; 3055 return 0;
3075} 3056}
3076 3057
3077static int me4000_ai_reset(me4000_ai_context_t * ai_context) 3058static int me4000_ai_reset(struct me4000_ai_context *ai_context)
3078{ 3059{
3079 wait_queue_head_t queue; 3060 wait_queue_head_t queue;
3080 u32 tmp; 3061 u32 tmp;
@@ -3139,7 +3120,7 @@ static int me4000_ai_reset(me4000_ai_context_t * ai_context)
3139static int me4000_ai_ioctl_sing(struct inode *inode_p, struct file *file_p, 3120static int me4000_ai_ioctl_sing(struct inode *inode_p, struct file *file_p,
3140 unsigned int service, unsigned long arg) 3121 unsigned int service, unsigned long arg)
3141{ 3122{
3142 me4000_ai_context_t *ai_context; 3123 struct me4000_ai_context *ai_context;
3143 3124
3144 CALL_PDEBUG("me4000_ai_ioctl_sing() is executed\n"); 3125 CALL_PDEBUG("me4000_ai_ioctl_sing() is executed\n");
3145 3126
@@ -3157,16 +3138,17 @@ static int me4000_ai_ioctl_sing(struct inode *inode_p, struct file *file_p,
3157 3138
3158 switch (service) { 3139 switch (service) {
3159 case ME4000_AI_SINGLE: 3140 case ME4000_AI_SINGLE:
3160 return me4000_ai_single((me4000_ai_single_t *) arg, ai_context); 3141 return me4000_ai_single((struct me4000_ai_single *)arg,
3142 ai_context);
3161 case ME4000_AI_EX_TRIG_ENABLE: 3143 case ME4000_AI_EX_TRIG_ENABLE:
3162 return me4000_ai_ex_trig_enable(ai_context); 3144 return me4000_ai_ex_trig_enable(ai_context);
3163 case ME4000_AI_EX_TRIG_DISABLE: 3145 case ME4000_AI_EX_TRIG_DISABLE:
3164 return me4000_ai_ex_trig_disable(ai_context); 3146 return me4000_ai_ex_trig_disable(ai_context);
3165 case ME4000_AI_EX_TRIG_SETUP: 3147 case ME4000_AI_EX_TRIG_SETUP:
3166 return me4000_ai_ex_trig_setup((me4000_ai_trigger_t *) arg, 3148 return me4000_ai_ex_trig_setup((struct me4000_ai_trigger *)arg,
3167 ai_context); 3149 ai_context);
3168 case ME4000_GET_USER_INFO: 3150 case ME4000_GET_USER_INFO:
3169 return me4000_get_user_info((me4000_user_info_t *) arg, 3151 return me4000_get_user_info((struct me4000_user_info *)arg,
3170 ai_context->board_info); 3152 ai_context->board_info);
3171 case ME4000_AI_OFFSET_ENABLE: 3153 case ME4000_AI_OFFSET_ENABLE:
3172 return me4000_ai_offset_enable(ai_context); 3154 return me4000_ai_offset_enable(ai_context);
@@ -3177,9 +3159,11 @@ static int me4000_ai_ioctl_sing(struct inode *inode_p, struct file *file_p,
3177 case ME4000_AI_FULLSCALE_DISABLE: 3159 case ME4000_AI_FULLSCALE_DISABLE:
3178 return me4000_ai_fullscale_disable(ai_context); 3160 return me4000_ai_fullscale_disable(ai_context);
3179 case ME4000_AI_EEPROM_READ: 3161 case ME4000_AI_EEPROM_READ:
3180 return me4000_eeprom_read((me4000_eeprom_t *) arg, ai_context); 3162 return me4000_eeprom_read((struct me4000_eeprom *)arg,
3163 ai_context);
3181 case ME4000_AI_EEPROM_WRITE: 3164 case ME4000_AI_EEPROM_WRITE:
3182 return me4000_eeprom_write((me4000_eeprom_t *) arg, ai_context); 3165 return me4000_eeprom_write((struct me4000_eeprom *)arg,
3166 ai_context);
3183 default: 3167 default:
3184 printk(KERN_ERR 3168 printk(KERN_ERR
3185 "me4000_ai_ioctl_sing():Invalid service number\n"); 3169 "me4000_ai_ioctl_sing():Invalid service number\n");
@@ -3188,10 +3172,10 @@ static int me4000_ai_ioctl_sing(struct inode *inode_p, struct file *file_p,
3188 return 0; 3172 return 0;
3189} 3173}
3190 3174
3191static int me4000_ai_single(me4000_ai_single_t * arg, 3175static int me4000_ai_single(struct me4000_ai_single *arg,
3192 me4000_ai_context_t * ai_context) 3176 struct me4000_ai_context *ai_context)
3193{ 3177{
3194 me4000_ai_single_t cmd; 3178 struct me4000_ai_single cmd;
3195 int err; 3179 int err;
3196 u32 tmp; 3180 u32 tmp;
3197 wait_queue_head_t queue; 3181 wait_queue_head_t queue;
@@ -3202,7 +3186,7 @@ static int me4000_ai_single(me4000_ai_single_t * arg,
3202 init_waitqueue_head(&queue); 3186 init_waitqueue_head(&queue);
3203 3187
3204 /* Copy data from user */ 3188 /* Copy data from user */
3205 err = copy_from_user(&cmd, arg, sizeof(me4000_ai_single_t)); 3189 err = copy_from_user(&cmd, arg, sizeof(struct me4000_ai_single));
3206 if (err) { 3190 if (err) {
3207 printk(KERN_ERR 3191 printk(KERN_ERR
3208 "ME4000:me4000_ai_single():Can't copy from user space\n"); 3192 "ME4000:me4000_ai_single():Can't copy from user space\n");
@@ -3301,7 +3285,7 @@ static int me4000_ai_single(me4000_ai_single_t * arg,
3301 cmd.value = me4000_inl(ai_context->data_reg) & 0xFFFF; 3285 cmd.value = me4000_inl(ai_context->data_reg) & 0xFFFF;
3302 3286
3303 /* Copy result back to user */ 3287 /* Copy result back to user */
3304 err = copy_to_user(arg, &cmd, sizeof(me4000_ai_single_t)); 3288 err = copy_to_user(arg, &cmd, sizeof(struct me4000_ai_single));
3305 if (err) { 3289 if (err) {
3306 printk(KERN_ERR 3290 printk(KERN_ERR
3307 "ME4000:me4000_ai_single():Can't copy to user space\n"); 3291 "ME4000:me4000_ai_single():Can't copy to user space\n");
@@ -3314,7 +3298,7 @@ static int me4000_ai_single(me4000_ai_single_t * arg,
3314static int me4000_ai_ioctl_sw(struct inode *inode_p, struct file *file_p, 3298static int me4000_ai_ioctl_sw(struct inode *inode_p, struct file *file_p,
3315 unsigned int service, unsigned long arg) 3299 unsigned int service, unsigned long arg)
3316{ 3300{
3317 me4000_ai_context_t *ai_context; 3301 struct me4000_ai_context *ai_context;
3318 3302
3319 CALL_PDEBUG("me4000_ai_ioctl_sw() is executed\n"); 3303 CALL_PDEBUG("me4000_ai_ioctl_sw() is executed\n");
3320 3304
@@ -3332,9 +3316,11 @@ static int me4000_ai_ioctl_sw(struct inode *inode_p, struct file *file_p,
3332 3316
3333 switch (service) { 3317 switch (service) {
3334 case ME4000_AI_SC_SETUP: 3318 case ME4000_AI_SC_SETUP:
3335 return me4000_ai_sc_setup((me4000_ai_sc_t *) arg, ai_context); 3319 return me4000_ai_sc_setup((struct me4000_ai_sc *)arg,
3320 ai_context);
3336 case ME4000_AI_CONFIG: 3321 case ME4000_AI_CONFIG:
3337 return me4000_ai_config((me4000_ai_config_t *) arg, ai_context); 3322 return me4000_ai_config((struct me4000_ai_config *)arg,
3323 ai_context);
3338 case ME4000_AI_START: 3324 case ME4000_AI_START:
3339 return me4000_ai_start(ai_context); 3325 return me4000_ai_start(ai_context);
3340 case ME4000_AI_STOP: 3326 case ME4000_AI_STOP:
@@ -3344,19 +3330,20 @@ static int me4000_ai_ioctl_sw(struct inode *inode_p, struct file *file_p,
3344 case ME4000_AI_FSM_STATE: 3330 case ME4000_AI_FSM_STATE:
3345 return me4000_ai_fsm_state((int *)arg, ai_context); 3331 return me4000_ai_fsm_state((int *)arg, ai_context);
3346 case ME4000_GET_USER_INFO: 3332 case ME4000_GET_USER_INFO:
3347 return me4000_get_user_info((me4000_user_info_t *) arg, 3333 return me4000_get_user_info((struct me4000_user_info *)arg,
3348 ai_context->board_info); 3334 ai_context->board_info);
3349 case ME4000_AI_EEPROM_READ: 3335 case ME4000_AI_EEPROM_READ:
3350 return me4000_eeprom_read((me4000_eeprom_t *) arg, ai_context); 3336 return me4000_eeprom_read((struct me4000_eeprom *)arg,
3337 ai_context);
3351 case ME4000_AI_EEPROM_WRITE: 3338 case ME4000_AI_EEPROM_WRITE:
3352 return me4000_eeprom_write((me4000_eeprom_t *) arg, ai_context); 3339 return me4000_eeprom_write((struct me4000_eeprom *)arg,
3340 ai_context);
3353 case ME4000_AI_GET_COUNT_BUFFER: 3341 case ME4000_AI_GET_COUNT_BUFFER:
3354 return me4000_ai_get_count_buffer((unsigned long *)arg, 3342 return me4000_ai_get_count_buffer((unsigned long *)arg,
3355 ai_context); 3343 ai_context);
3356 default: 3344 default:
3357 printk(KERN_ERR 3345 printk(KERN_ERR
3358 "ME4000:me4000_ai_ioctl_sw():Invalid service number %d\n", 3346 "%s:Invalid service number %d\n", __func__, service);
3359 service);
3360 return -ENOTTY; 3347 return -ENOTTY;
3361 } 3348 }
3362 return 0; 3349 return 0;
@@ -3365,7 +3352,7 @@ static int me4000_ai_ioctl_sw(struct inode *inode_p, struct file *file_p,
3365static int me4000_ai_ioctl_ext(struct inode *inode_p, struct file *file_p, 3352static int me4000_ai_ioctl_ext(struct inode *inode_p, struct file *file_p,
3366 unsigned int service, unsigned long arg) 3353 unsigned int service, unsigned long arg)
3367{ 3354{
3368 me4000_ai_context_t *ai_context; 3355 struct me4000_ai_context *ai_context;
3369 3356
3370 CALL_PDEBUG("me4000_ai_ioctl_ext() is executed\n"); 3357 CALL_PDEBUG("me4000_ai_ioctl_ext() is executed\n");
3371 3358
@@ -3383,9 +3370,11 @@ static int me4000_ai_ioctl_ext(struct inode *inode_p, struct file *file_p,
3383 3370
3384 switch (service) { 3371 switch (service) {
3385 case ME4000_AI_SC_SETUP: 3372 case ME4000_AI_SC_SETUP:
3386 return me4000_ai_sc_setup((me4000_ai_sc_t *) arg, ai_context); 3373 return me4000_ai_sc_setup((struct me4000_ai_sc *)arg,
3374 ai_context);
3387 case ME4000_AI_CONFIG: 3375 case ME4000_AI_CONFIG:
3388 return me4000_ai_config((me4000_ai_config_t *) arg, ai_context); 3376 return me4000_ai_config((struct me4000_ai_config *)arg,
3377 ai_context);
3389 case ME4000_AI_START: 3378 case ME4000_AI_START:
3390 return me4000_ai_start_ex((unsigned long *)arg, ai_context); 3379 return me4000_ai_start_ex((unsigned long *)arg, ai_context);
3391 case ME4000_AI_STOP: 3380 case ME4000_AI_STOP:
@@ -3397,20 +3386,19 @@ static int me4000_ai_ioctl_ext(struct inode *inode_p, struct file *file_p,
3397 case ME4000_AI_EX_TRIG_DISABLE: 3386 case ME4000_AI_EX_TRIG_DISABLE:
3398 return me4000_ai_ex_trig_disable(ai_context); 3387 return me4000_ai_ex_trig_disable(ai_context);
3399 case ME4000_AI_EX_TRIG_SETUP: 3388 case ME4000_AI_EX_TRIG_SETUP:
3400 return me4000_ai_ex_trig_setup((me4000_ai_trigger_t *) arg, 3389 return me4000_ai_ex_trig_setup((struct me4000_ai_trigger *)arg,
3401 ai_context); 3390 ai_context);
3402 case ME4000_AI_FSM_STATE: 3391 case ME4000_AI_FSM_STATE:
3403 return me4000_ai_fsm_state((int *)arg, ai_context); 3392 return me4000_ai_fsm_state((int *)arg, ai_context);
3404 case ME4000_GET_USER_INFO: 3393 case ME4000_GET_USER_INFO:
3405 return me4000_get_user_info((me4000_user_info_t *) arg, 3394 return me4000_get_user_info((struct me4000_user_info *)arg,
3406 ai_context->board_info); 3395 ai_context->board_info);
3407 case ME4000_AI_GET_COUNT_BUFFER: 3396 case ME4000_AI_GET_COUNT_BUFFER:
3408 return me4000_ai_get_count_buffer((unsigned long *)arg, 3397 return me4000_ai_get_count_buffer((unsigned long *)arg,
3409 ai_context); 3398 ai_context);
3410 default: 3399 default:
3411 printk(KERN_ERR 3400 printk(KERN_ERR
3412 "ME4000:me4000_ai_ioctl_ext():Invalid service number %d\n", 3401 "%s:Invalid service number %d\n", __func__ , service);
3413 service);
3414 return -ENOTTY; 3402 return -ENOTTY;
3415 } 3403 }
3416 return 0; 3404 return 0;
@@ -3418,7 +3406,7 @@ static int me4000_ai_ioctl_ext(struct inode *inode_p, struct file *file_p,
3418 3406
3419static int me4000_ai_fasync(int fd, struct file *file_p, int mode) 3407static int me4000_ai_fasync(int fd, struct file *file_p, int mode)
3420{ 3408{
3421 me4000_ai_context_t *ai_context; 3409 struct me4000_ai_context *ai_context;
3422 3410
3423 CALL_PDEBUG("me4000_ao_fasync_cont() is executed\n"); 3411 CALL_PDEBUG("me4000_ao_fasync_cont() is executed\n");
3424 3412
@@ -3426,10 +3414,10 @@ static int me4000_ai_fasync(int fd, struct file *file_p, int mode)
3426 return fasync_helper(fd, file_p, mode, &ai_context->fasync_p); 3414 return fasync_helper(fd, file_p, mode, &ai_context->fasync_p);
3427} 3415}
3428 3416
3429static int me4000_ai_config(me4000_ai_config_t * arg, 3417static int me4000_ai_config(struct me4000_ai_config *arg,
3430 me4000_ai_context_t * ai_context) 3418 struct me4000_ai_context *ai_context)
3431{ 3419{
3432 me4000_ai_config_t cmd; 3420 struct me4000_ai_config cmd;
3433 u32 *list = NULL; 3421 u32 *list = NULL;
3434 u32 mode; 3422 u32 mode;
3435 int i; 3423 int i;
@@ -3451,7 +3439,7 @@ static int me4000_ai_config(me4000_ai_config_t * arg,
3451 } 3439 }
3452 3440
3453 /* Copy data from user */ 3441 /* Copy data from user */
3454 err = copy_from_user(&cmd, arg, sizeof(me4000_ai_config_t)); 3442 err = copy_from_user(&cmd, arg, sizeof(struct me4000_ai_config));
3455 if (err) { 3443 if (err) {
3456 printk(KERN_ERR 3444 printk(KERN_ERR
3457 "ME4000:me4000_ai_config():Can't copy from user space\n"); 3445 "ME4000:me4000_ai_config():Can't copy from user space\n");
@@ -3671,7 +3659,7 @@ static int me4000_ai_config(me4000_ai_config_t * arg,
3671 3659
3672 return 0; 3660 return 0;
3673 3661
3674 AI_CONFIG_ERR: 3662AI_CONFIG_ERR:
3675 3663
3676 /* Reset the timers */ 3664 /* Reset the timers */
3677 ai_context->chan_timer = 66; 3665 ai_context->chan_timer = 66;
@@ -3699,7 +3687,7 @@ static int me4000_ai_config(me4000_ai_config_t * arg,
3699 3687
3700} 3688}
3701 3689
3702static int ai_common_start(me4000_ai_context_t * ai_context) 3690static int ai_common_start(struct me4000_ai_context *ai_context)
3703{ 3691{
3704 u32 tmp; 3692 u32 tmp;
3705 CALL_PDEBUG("ai_common_start() is executed\n"); 3693 CALL_PDEBUG("ai_common_start() is executed\n");
@@ -3762,7 +3750,7 @@ static int ai_common_start(me4000_ai_context_t * ai_context)
3762 return 0; 3750 return 0;
3763} 3751}
3764 3752
3765static int me4000_ai_start(me4000_ai_context_t * ai_context) 3753static int me4000_ai_start(struct me4000_ai_context *ai_context)
3766{ 3754{
3767 int err; 3755 int err;
3768 CALL_PDEBUG("me4000_ai_start() is executed\n"); 3756 CALL_PDEBUG("me4000_ai_start() is executed\n");
@@ -3779,7 +3767,7 @@ static int me4000_ai_start(me4000_ai_context_t * ai_context)
3779} 3767}
3780 3768
3781static int me4000_ai_start_ex(unsigned long *arg, 3769static int me4000_ai_start_ex(unsigned long *arg,
3782 me4000_ai_context_t * ai_context) 3770 struct me4000_ai_context *ai_context)
3783{ 3771{
3784 int err; 3772 int err;
3785 wait_queue_head_t queue; 3773 wait_queue_head_t queue;
@@ -3834,7 +3822,7 @@ static int me4000_ai_start_ex(unsigned long *arg,
3834 return 0; 3822 return 0;
3835} 3823}
3836 3824
3837static int me4000_ai_stop(me4000_ai_context_t * ai_context) 3825static int me4000_ai_stop(struct me4000_ai_context *ai_context)
3838{ 3826{
3839 wait_queue_head_t queue; 3827 wait_queue_head_t queue;
3840 u32 tmp; 3828 u32 tmp;
@@ -3871,7 +3859,7 @@ static int me4000_ai_stop(me4000_ai_context_t * ai_context)
3871 return 0; 3859 return 0;
3872} 3860}
3873 3861
3874static int me4000_ai_immediate_stop(me4000_ai_context_t * ai_context) 3862static int me4000_ai_immediate_stop(struct me4000_ai_context *ai_context)
3875{ 3863{
3876 wait_queue_head_t queue; 3864 wait_queue_head_t queue;
3877 u32 tmp; 3865 u32 tmp;
@@ -3908,7 +3896,7 @@ static int me4000_ai_immediate_stop(me4000_ai_context_t * ai_context)
3908 return 0; 3896 return 0;
3909} 3897}
3910 3898
3911static int me4000_ai_ex_trig_enable(me4000_ai_context_t * ai_context) 3899static int me4000_ai_ex_trig_enable(struct me4000_ai_context *ai_context)
3912{ 3900{
3913 u32 tmp; 3901 u32 tmp;
3914 unsigned long flags; 3902 unsigned long flags;
@@ -3924,7 +3912,7 @@ static int me4000_ai_ex_trig_enable(me4000_ai_context_t * ai_context)
3924 return 0; 3912 return 0;
3925} 3913}
3926 3914
3927static int me4000_ai_ex_trig_disable(me4000_ai_context_t * ai_context) 3915static int me4000_ai_ex_trig_disable(struct me4000_ai_context *ai_context)
3928{ 3916{
3929 u32 tmp; 3917 u32 tmp;
3930 unsigned long flags; 3918 unsigned long flags;
@@ -3940,10 +3928,10 @@ static int me4000_ai_ex_trig_disable(me4000_ai_context_t * ai_context)
3940 return 0; 3928 return 0;
3941} 3929}
3942 3930
3943static int me4000_ai_ex_trig_setup(me4000_ai_trigger_t * arg, 3931static int me4000_ai_ex_trig_setup(struct me4000_ai_trigger *arg,
3944 me4000_ai_context_t * ai_context) 3932 struct me4000_ai_context *ai_context)
3945{ 3933{
3946 me4000_ai_trigger_t cmd; 3934 struct me4000_ai_trigger cmd;
3947 int err; 3935 int err;
3948 u32 tmp; 3936 u32 tmp;
3949 unsigned long flags; 3937 unsigned long flags;
@@ -3951,7 +3939,7 @@ static int me4000_ai_ex_trig_setup(me4000_ai_trigger_t * arg,
3951 CALL_PDEBUG("me4000_ai_ex_trig_setup() is executed\n"); 3939 CALL_PDEBUG("me4000_ai_ex_trig_setup() is executed\n");
3952 3940
3953 /* Copy data from user */ 3941 /* Copy data from user */
3954 err = copy_from_user(&cmd, arg, sizeof(me4000_ai_trigger_t)); 3942 err = copy_from_user(&cmd, arg, sizeof(struct me4000_ai_trigger));
3955 if (err) { 3943 if (err) {
3956 printk(KERN_ERR 3944 printk(KERN_ERR
3957 "ME4000:me4000_ai_ex_trig_setup():Can't copy from user space\n"); 3945 "ME4000:me4000_ai_ex_trig_setup():Can't copy from user space\n");
@@ -4000,16 +3988,16 @@ static int me4000_ai_ex_trig_setup(me4000_ai_trigger_t * arg,
4000 return 0; 3988 return 0;
4001} 3989}
4002 3990
4003static int me4000_ai_sc_setup(me4000_ai_sc_t * arg, 3991static int me4000_ai_sc_setup(struct me4000_ai_sc *arg,
4004 me4000_ai_context_t * ai_context) 3992 struct me4000_ai_context *ai_context)
4005{ 3993{
4006 me4000_ai_sc_t cmd; 3994 struct me4000_ai_sc cmd;
4007 int err; 3995 int err;
4008 3996
4009 CALL_PDEBUG("me4000_ai_sc_setup() is executed\n"); 3997 CALL_PDEBUG("me4000_ai_sc_setup() is executed\n");
4010 3998
4011 /* Copy data from user */ 3999 /* Copy data from user */
4012 err = copy_from_user(&cmd, arg, sizeof(me4000_ai_sc_t)); 4000 err = copy_from_user(&cmd, arg, sizeof(struct me4000_ai_sc));
4013 if (err) { 4001 if (err) {
4014 printk(KERN_ERR 4002 printk(KERN_ERR
4015 "ME4000:me4000_ai_sc_setup():Can't copy from user space\n"); 4003 "ME4000:me4000_ai_sc_setup():Can't copy from user space\n");
@@ -4023,9 +4011,9 @@ static int me4000_ai_sc_setup(me4000_ai_sc_t * arg,
4023} 4011}
4024 4012
4025static ssize_t me4000_ai_read(struct file *filep, char *buff, size_t cnt, 4013static ssize_t me4000_ai_read(struct file *filep, char *buff, size_t cnt,
4026 loff_t * offp) 4014 loff_t *offp)
4027{ 4015{
4028 me4000_ai_context_t *ai_context = filep->private_data; 4016 struct me4000_ai_context *ai_context = filep->private_data;
4029 s16 *buffer = (s16 *) buff; 4017 s16 *buffer = (s16 *) buff;
4030 size_t count = cnt / 2; 4018 size_t count = cnt / 2;
4031 unsigned long flags; 4019 unsigned long flags;
@@ -4150,9 +4138,9 @@ static ssize_t me4000_ai_read(struct file *filep, char *buff, size_t cnt,
4150 return ret * 2; 4138 return ret * 2;
4151} 4139}
4152 4140
4153static unsigned int me4000_ai_poll(struct file *file_p, poll_table * wait) 4141static unsigned int me4000_ai_poll(struct file *file_p, poll_table *wait)
4154{ 4142{
4155 me4000_ai_context_t *ai_context; 4143 struct me4000_ai_context *ai_context;
4156 unsigned long mask = 0; 4144 unsigned long mask = 0;
4157 4145
4158 CALL_PDEBUG("me4000_ai_poll() is executed\n"); 4146 CALL_PDEBUG("me4000_ai_poll() is executed\n");
@@ -4171,7 +4159,7 @@ static unsigned int me4000_ai_poll(struct file *file_p, poll_table * wait)
4171 return mask; 4159 return mask;
4172} 4160}
4173 4161
4174static int me4000_ai_offset_enable(me4000_ai_context_t * ai_context) 4162static int me4000_ai_offset_enable(struct me4000_ai_context *ai_context)
4175{ 4163{
4176 unsigned long tmp; 4164 unsigned long tmp;
4177 4165
@@ -4184,7 +4172,7 @@ static int me4000_ai_offset_enable(me4000_ai_context_t * ai_context)
4184 return 0; 4172 return 0;
4185} 4173}
4186 4174
4187static int me4000_ai_offset_disable(me4000_ai_context_t * ai_context) 4175static int me4000_ai_offset_disable(struct me4000_ai_context *ai_context)
4188{ 4176{
4189 unsigned long tmp; 4177 unsigned long tmp;
4190 4178
@@ -4197,7 +4185,7 @@ static int me4000_ai_offset_disable(me4000_ai_context_t * ai_context)
4197 return 0; 4185 return 0;
4198} 4186}
4199 4187
4200static int me4000_ai_fullscale_enable(me4000_ai_context_t * ai_context) 4188static int me4000_ai_fullscale_enable(struct me4000_ai_context *ai_context)
4201{ 4189{
4202 unsigned long tmp; 4190 unsigned long tmp;
4203 4191
@@ -4210,7 +4198,7 @@ static int me4000_ai_fullscale_enable(me4000_ai_context_t * ai_context)
4210 return 0; 4198 return 0;
4211} 4199}
4212 4200
4213static int me4000_ai_fullscale_disable(me4000_ai_context_t * ai_context) 4201static int me4000_ai_fullscale_disable(struct me4000_ai_context *ai_context)
4214{ 4202{
4215 unsigned long tmp; 4203 unsigned long tmp;
4216 4204
@@ -4223,7 +4211,7 @@ static int me4000_ai_fullscale_disable(me4000_ai_context_t * ai_context)
4223 return 0; 4211 return 0;
4224} 4212}
4225 4213
4226static int me4000_ai_fsm_state(int *arg, me4000_ai_context_t * ai_context) 4214static int me4000_ai_fsm_state(int *arg, struct me4000_ai_context *ai_context)
4227{ 4215{
4228 unsigned long tmp; 4216 unsigned long tmp;
4229 4217
@@ -4242,7 +4230,7 @@ static int me4000_ai_fsm_state(int *arg, me4000_ai_context_t * ai_context)
4242} 4230}
4243 4231
4244static int me4000_ai_get_count_buffer(unsigned long *arg, 4232static int me4000_ai_get_count_buffer(unsigned long *arg,
4245 me4000_ai_context_t * ai_context) 4233 struct me4000_ai_context *ai_context)
4246{ 4234{
4247 unsigned long c; 4235 unsigned long c;
4248 int err; 4236 int err;
@@ -4252,7 +4240,7 @@ static int me4000_ai_get_count_buffer(unsigned long *arg,
4252 err = copy_to_user(arg, &c, sizeof(unsigned long)); 4240 err = copy_to_user(arg, &c, sizeof(unsigned long));
4253 if (err) { 4241 if (err) {
4254 printk(KERN_ERR 4242 printk(KERN_ERR
4255 "ME4000:me4000_ai_get_count_buffer():Can't copy to user space\n"); 4243 "%s:Can't copy to user space\n", __func__);
4256 return -EFAULT; 4244 return -EFAULT;
4257 } 4245 }
4258 4246
@@ -4261,7 +4249,7 @@ static int me4000_ai_get_count_buffer(unsigned long *arg,
4261 4249
4262/*---------------------------------- EEPROM stuff ---------------------------*/ 4250/*---------------------------------- EEPROM stuff ---------------------------*/
4263 4251
4264static int eeprom_write_cmd(me4000_ai_context_t * ai_context, unsigned long cmd, 4252static int eeprom_write_cmd(struct me4000_ai_context *ai_context, unsigned long cmd,
4265 int length) 4253 int length)
4266{ 4254{
4267 int i; 4255 int i;
@@ -4318,7 +4306,7 @@ static int eeprom_write_cmd(me4000_ai_context_t * ai_context, unsigned long cmd,
4318 return 0; 4306 return 0;
4319} 4307}
4320 4308
4321static unsigned short eeprom_read_cmd(me4000_ai_context_t * ai_context, 4309static unsigned short eeprom_read_cmd(struct me4000_ai_context *ai_context,
4322 unsigned long cmd, int length) 4310 unsigned long cmd, int length)
4323{ 4311{
4324 int i; 4312 int i;
@@ -4397,11 +4385,11 @@ static unsigned short eeprom_read_cmd(me4000_ai_context_t * ai_context,
4397 return id; 4385 return id;
4398} 4386}
4399 4387
4400static int me4000_eeprom_write(me4000_eeprom_t * arg, 4388static int me4000_eeprom_write(struct me4000_eeprom *arg,
4401 me4000_ai_context_t * ai_context) 4389 struct me4000_ai_context *ai_context)
4402{ 4390{
4403 int err; 4391 int err;
4404 me4000_eeprom_t setup; 4392 struct me4000_eeprom setup;
4405 unsigned long cmd; 4393 unsigned long cmd;
4406 unsigned long date_high; 4394 unsigned long date_high;
4407 unsigned long date_low; 4395 unsigned long date_low;
@@ -4594,12 +4582,12 @@ static int me4000_eeprom_write(me4000_eeprom_t * arg,
4594 return 0; 4582 return 0;
4595} 4583}
4596 4584
4597static int me4000_eeprom_read(me4000_eeprom_t * arg, 4585static int me4000_eeprom_read(struct me4000_eeprom *arg,
4598 me4000_ai_context_t * ai_context) 4586 struct me4000_ai_context *ai_context)
4599{ 4587{
4600 int err; 4588 int err;
4601 unsigned long cmd; 4589 unsigned long cmd;
4602 me4000_eeprom_t setup; 4590 struct me4000_eeprom setup;
4603 4591
4604 CALL_PDEBUG("me4000_eeprom_read() is executed\n"); 4592 CALL_PDEBUG("me4000_eeprom_read() is executed\n");
4605 4593
@@ -4687,7 +4675,7 @@ static int me4000_eeprom_read(me4000_eeprom_t * arg,
4687static int me4000_dio_ioctl(struct inode *inode_p, struct file *file_p, 4675static int me4000_dio_ioctl(struct inode *inode_p, struct file *file_p,
4688 unsigned int service, unsigned long arg) 4676 unsigned int service, unsigned long arg)
4689{ 4677{
4690 me4000_dio_context_t *dio_context; 4678 struct me4000_dio_context *dio_context;
4691 4679
4692 CALL_PDEBUG("me4000_dio_ioctl() is executed\n"); 4680 CALL_PDEBUG("me4000_dio_ioctl() is executed\n");
4693 4681
@@ -4704,13 +4692,13 @@ static int me4000_dio_ioctl(struct inode *inode_p, struct file *file_p,
4704 4692
4705 switch (service) { 4693 switch (service) {
4706 case ME4000_DIO_CONFIG: 4694 case ME4000_DIO_CONFIG:
4707 return me4000_dio_config((me4000_dio_config_t *) arg, 4695 return me4000_dio_config((struct me4000_dio_config *)arg,
4708 dio_context); 4696 dio_context);
4709 case ME4000_DIO_SET_BYTE: 4697 case ME4000_DIO_SET_BYTE:
4710 return me4000_dio_set_byte((me4000_dio_byte_t *) arg, 4698 return me4000_dio_set_byte((struct me4000_dio_byte *)arg,
4711 dio_context); 4699 dio_context);
4712 case ME4000_DIO_GET_BYTE: 4700 case ME4000_DIO_GET_BYTE:
4713 return me4000_dio_get_byte((me4000_dio_byte_t *) arg, 4701 return me4000_dio_get_byte((struct me4000_dio_byte *)arg,
4714 dio_context); 4702 dio_context);
4715 case ME4000_DIO_RESET: 4703 case ME4000_DIO_RESET:
4716 return me4000_dio_reset(dio_context); 4704 return me4000_dio_reset(dio_context);
@@ -4723,17 +4711,17 @@ static int me4000_dio_ioctl(struct inode *inode_p, struct file *file_p,
4723 return 0; 4711 return 0;
4724} 4712}
4725 4713
4726static int me4000_dio_config(me4000_dio_config_t * arg, 4714static int me4000_dio_config(struct me4000_dio_config *arg,
4727 me4000_dio_context_t * dio_context) 4715 struct me4000_dio_context *dio_context)
4728{ 4716{
4729 me4000_dio_config_t cmd; 4717 struct me4000_dio_config cmd;
4730 u32 tmp; 4718 u32 tmp;
4731 int err; 4719 int err;
4732 4720
4733 CALL_PDEBUG("me4000_dio_config() is executed\n"); 4721 CALL_PDEBUG("me4000_dio_config() is executed\n");
4734 4722
4735 /* Copy data from user */ 4723 /* Copy data from user */
4736 err = copy_from_user(&cmd, arg, sizeof(me4000_dio_config_t)); 4724 err = copy_from_user(&cmd, arg, sizeof(struct me4000_dio_config));
4737 if (err) { 4725 if (err) {
4738 printk(KERN_ERR 4726 printk(KERN_ERR
4739 "ME4000:me4000_dio_config():Can't copy from user space\n"); 4727 "ME4000:me4000_dio_config():Can't copy from user space\n");
@@ -4964,16 +4952,16 @@ static int me4000_dio_config(me4000_dio_config_t * arg,
4964 return 0; 4952 return 0;
4965} 4953}
4966 4954
4967static int me4000_dio_set_byte(me4000_dio_byte_t * arg, 4955static int me4000_dio_set_byte(struct me4000_dio_byte *arg,
4968 me4000_dio_context_t * dio_context) 4956 struct me4000_dio_context *dio_context)
4969{ 4957{
4970 me4000_dio_byte_t cmd; 4958 struct me4000_dio_byte cmd;
4971 int err; 4959 int err;
4972 4960
4973 CALL_PDEBUG("me4000_dio_set_byte() is executed\n"); 4961 CALL_PDEBUG("me4000_dio_set_byte() is executed\n");
4974 4962
4975 /* Copy data from user */ 4963 /* Copy data from user */
4976 err = copy_from_user(&cmd, arg, sizeof(me4000_dio_byte_t)); 4964 err = copy_from_user(&cmd, arg, sizeof(struct me4000_dio_byte));
4977 if (err) { 4965 if (err) {
4978 printk(KERN_ERR 4966 printk(KERN_ERR
4979 "ME4000:me4000_dio_set_byte():Can't copy from user space\n"); 4967 "ME4000:me4000_dio_set_byte():Can't copy from user space\n");
@@ -5030,16 +5018,16 @@ static int me4000_dio_set_byte(me4000_dio_byte_t * arg,
5030 return 0; 5018 return 0;
5031} 5019}
5032 5020
5033static int me4000_dio_get_byte(me4000_dio_byte_t * arg, 5021static int me4000_dio_get_byte(struct me4000_dio_byte *arg,
5034 me4000_dio_context_t * dio_context) 5022 struct me4000_dio_context *dio_context)
5035{ 5023{
5036 me4000_dio_byte_t cmd; 5024 struct me4000_dio_byte cmd;
5037 int err; 5025 int err;
5038 5026
5039 CALL_PDEBUG("me4000_dio_get_byte() is executed\n"); 5027 CALL_PDEBUG("me4000_dio_get_byte() is executed\n");
5040 5028
5041 /* Copy data from user */ 5029 /* Copy data from user */
5042 err = copy_from_user(&cmd, arg, sizeof(me4000_dio_byte_t)); 5030 err = copy_from_user(&cmd, arg, sizeof(struct me4000_dio_byte));
5043 if (err) { 5031 if (err) {
5044 printk(KERN_ERR 5032 printk(KERN_ERR
5045 "ME4000:me4000_dio_get_byte():Can't copy from user space\n"); 5033 "ME4000:me4000_dio_get_byte():Can't copy from user space\n");
@@ -5070,7 +5058,7 @@ static int me4000_dio_get_byte(me4000_dio_byte_t * arg,
5070 } 5058 }
5071 5059
5072 /* Copy result back to user */ 5060 /* Copy result back to user */
5073 err = copy_to_user(arg, &cmd, sizeof(me4000_dio_byte_t)); 5061 err = copy_to_user(arg, &cmd, sizeof(struct me4000_dio_byte));
5074 if (err) { 5062 if (err) {
5075 printk(KERN_ERR 5063 printk(KERN_ERR
5076 "ME4000:me4000_dio_get_byte():Can't copy to user space\n"); 5064 "ME4000:me4000_dio_get_byte():Can't copy to user space\n");
@@ -5080,7 +5068,7 @@ static int me4000_dio_get_byte(me4000_dio_byte_t * arg,
5080 return 0; 5068 return 0;
5081} 5069}
5082 5070
5083static int me4000_dio_reset(me4000_dio_context_t * dio_context) 5071static int me4000_dio_reset(struct me4000_dio_context *dio_context)
5084{ 5072{
5085 CALL_PDEBUG("me4000_dio_reset() is executed\n"); 5073 CALL_PDEBUG("me4000_dio_reset() is executed\n");
5086 5074
@@ -5101,7 +5089,7 @@ static int me4000_dio_reset(me4000_dio_context_t * dio_context)
5101static int me4000_cnt_ioctl(struct inode *inode_p, struct file *file_p, 5089static int me4000_cnt_ioctl(struct inode *inode_p, struct file *file_p,
5102 unsigned int service, unsigned long arg) 5090 unsigned int service, unsigned long arg)
5103{ 5091{
5104 me4000_cnt_context_t *cnt_context; 5092 struct me4000_cnt_context *cnt_context;
5105 5093
5106 CALL_PDEBUG("me4000_cnt_ioctl() is executed\n"); 5094 CALL_PDEBUG("me4000_cnt_ioctl() is executed\n");
5107 5095
@@ -5118,11 +5106,11 @@ static int me4000_cnt_ioctl(struct inode *inode_p, struct file *file_p,
5118 5106
5119 switch (service) { 5107 switch (service) {
5120 case ME4000_CNT_READ: 5108 case ME4000_CNT_READ:
5121 return me4000_cnt_read((me4000_cnt_t *) arg, cnt_context); 5109 return me4000_cnt_read((struct me4000_cnt *)arg, cnt_context);
5122 case ME4000_CNT_WRITE: 5110 case ME4000_CNT_WRITE:
5123 return me4000_cnt_write((me4000_cnt_t *) arg, cnt_context); 5111 return me4000_cnt_write((struct me4000_cnt *)arg, cnt_context);
5124 case ME4000_CNT_CONFIG: 5112 case ME4000_CNT_CONFIG:
5125 return me4000_cnt_config((me4000_cnt_config_t *) arg, 5113 return me4000_cnt_config((struct me4000_cnt_config *)arg,
5126 cnt_context); 5114 cnt_context);
5127 case ME4000_CNT_RESET: 5115 case ME4000_CNT_RESET:
5128 return me4000_cnt_reset(cnt_context); 5116 return me4000_cnt_reset(cnt_context);
@@ -5135,10 +5123,10 @@ static int me4000_cnt_ioctl(struct inode *inode_p, struct file *file_p,
5135 return 0; 5123 return 0;
5136} 5124}
5137 5125
5138static int me4000_cnt_config(me4000_cnt_config_t * arg, 5126static int me4000_cnt_config(struct me4000_cnt_config *arg,
5139 me4000_cnt_context_t * cnt_context) 5127 struct me4000_cnt_context *cnt_context)
5140{ 5128{
5141 me4000_cnt_config_t cmd; 5129 struct me4000_cnt_config cmd;
5142 u8 counter; 5130 u8 counter;
5143 u8 mode; 5131 u8 mode;
5144 int err; 5132 int err;
@@ -5146,7 +5134,7 @@ static int me4000_cnt_config(me4000_cnt_config_t * arg,
5146 CALL_PDEBUG("me4000_cnt_config() is executed\n"); 5134 CALL_PDEBUG("me4000_cnt_config() is executed\n");
5147 5135
5148 /* Copy data from user */ 5136 /* Copy data from user */
5149 err = copy_from_user(&cmd, arg, sizeof(me4000_cnt_config_t)); 5137 err = copy_from_user(&cmd, arg, sizeof(struct me4000_cnt_config));
5150 if (err) { 5138 if (err) {
5151 printk(KERN_ERR 5139 printk(KERN_ERR
5152 "ME4000:me4000_cnt_config():Can't copy from user space\n"); 5140 "ME4000:me4000_cnt_config():Can't copy from user space\n");
@@ -5204,17 +5192,17 @@ static int me4000_cnt_config(me4000_cnt_config_t * arg,
5204 return 0; 5192 return 0;
5205} 5193}
5206 5194
5207static int me4000_cnt_read(me4000_cnt_t * arg, 5195static int me4000_cnt_read(struct me4000_cnt *arg,
5208 me4000_cnt_context_t * cnt_context) 5196 struct me4000_cnt_context *cnt_context)
5209{ 5197{
5210 me4000_cnt_t cmd; 5198 struct me4000_cnt cmd;
5211 u8 tmp; 5199 u8 tmp;
5212 int err; 5200 int err;
5213 5201
5214 CALL_PDEBUG("me4000_cnt_read() is executed\n"); 5202 CALL_PDEBUG("me4000_cnt_read() is executed\n");
5215 5203
5216 /* Copy data from user */ 5204 /* Copy data from user */
5217 err = copy_from_user(&cmd, arg, sizeof(me4000_cnt_t)); 5205 err = copy_from_user(&cmd, arg, sizeof(struct me4000_cnt));
5218 if (err) { 5206 if (err) {
5219 printk(KERN_ERR 5207 printk(KERN_ERR
5220 "ME4000:me4000_cnt_read():Can't copy from user space\n"); 5208 "ME4000:me4000_cnt_read():Can't copy from user space\n");
@@ -5249,7 +5237,7 @@ static int me4000_cnt_read(me4000_cnt_t * arg,
5249 } 5237 }
5250 5238
5251 /* Copy result back to user */ 5239 /* Copy result back to user */
5252 err = copy_to_user(arg, &cmd, sizeof(me4000_cnt_t)); 5240 err = copy_to_user(arg, &cmd, sizeof(struct me4000_cnt));
5253 if (err) { 5241 if (err) {
5254 printk(KERN_ERR 5242 printk(KERN_ERR
5255 "ME4000:me4000_cnt_read():Can't copy to user space\n"); 5243 "ME4000:me4000_cnt_read():Can't copy to user space\n");
@@ -5259,17 +5247,17 @@ static int me4000_cnt_read(me4000_cnt_t * arg,
5259 return 0; 5247 return 0;
5260} 5248}
5261 5249
5262static int me4000_cnt_write(me4000_cnt_t * arg, 5250static int me4000_cnt_write(struct me4000_cnt *arg,
5263 me4000_cnt_context_t * cnt_context) 5251 struct me4000_cnt_context *cnt_context)
5264{ 5252{
5265 me4000_cnt_t cmd; 5253 struct me4000_cnt cmd;
5266 u8 tmp; 5254 u8 tmp;
5267 int err; 5255 int err;
5268 5256
5269 CALL_PDEBUG("me4000_cnt_write() is executed\n"); 5257 CALL_PDEBUG("me4000_cnt_write() is executed\n");
5270 5258
5271 /* Copy data from user */ 5259 /* Copy data from user */
5272 err = copy_from_user(&cmd, arg, sizeof(me4000_cnt_t)); 5260 err = copy_from_user(&cmd, arg, sizeof(struct me4000_cnt));
5273 if (err) { 5261 if (err) {
5274 printk(KERN_ERR 5262 printk(KERN_ERR
5275 "ME4000:me4000_cnt_write():Can't copy from user space\n"); 5263 "ME4000:me4000_cnt_write():Can't copy from user space\n");
@@ -5306,7 +5294,7 @@ static int me4000_cnt_write(me4000_cnt_t * arg,
5306 return 0; 5294 return 0;
5307} 5295}
5308 5296
5309static int me4000_cnt_reset(me4000_cnt_context_t * cnt_context) 5297static int me4000_cnt_reset(struct me4000_cnt_context *cnt_context)
5310{ 5298{
5311 CALL_PDEBUG("me4000_cnt_reset() is executed\n"); 5299 CALL_PDEBUG("me4000_cnt_reset() is executed\n");
5312 5300
@@ -5333,7 +5321,7 @@ static int me4000_cnt_reset(me4000_cnt_context_t * cnt_context)
5333static int me4000_ext_int_ioctl(struct inode *inode_p, struct file *file_p, 5321static int me4000_ext_int_ioctl(struct inode *inode_p, struct file *file_p,
5334 unsigned int service, unsigned long arg) 5322 unsigned int service, unsigned long arg)
5335{ 5323{
5336 me4000_ext_int_context_t *ext_int_context; 5324 struct me4000_ext_int_context *ext_int_context;
5337 5325
5338 CALL_PDEBUG("me4000_ext_int_ioctl() is executed\n"); 5326 CALL_PDEBUG("me4000_ext_int_ioctl() is executed\n");
5339 5327
@@ -5366,7 +5354,7 @@ static int me4000_ext_int_ioctl(struct inode *inode_p, struct file *file_p,
5366 return 0; 5354 return 0;
5367} 5355}
5368 5356
5369static int me4000_ext_int_enable(me4000_ext_int_context_t * ext_int_context) 5357static int me4000_ext_int_enable(struct me4000_ext_int_context *ext_int_context)
5370{ 5358{
5371 unsigned long tmp; 5359 unsigned long tmp;
5372 5360
@@ -5379,7 +5367,7 @@ static int me4000_ext_int_enable(me4000_ext_int_context_t * ext_int_context)
5379 return 0; 5367 return 0;
5380} 5368}
5381 5369
5382static int me4000_ext_int_disable(me4000_ext_int_context_t * ext_int_context) 5370static int me4000_ext_int_disable(struct me4000_ext_int_context *ext_int_context)
5383{ 5371{
5384 unsigned long tmp; 5372 unsigned long tmp;
5385 5373
@@ -5393,7 +5381,7 @@ static int me4000_ext_int_disable(me4000_ext_int_context_t * ext_int_context)
5393} 5381}
5394 5382
5395static int me4000_ext_int_count(unsigned long *arg, 5383static int me4000_ext_int_count(unsigned long *arg,
5396 me4000_ext_int_context_t * ext_int_context) 5384 struct me4000_ext_int_context *ext_int_context)
5397{ 5385{
5398 5386
5399 CALL_PDEBUG("me4000_ext_int_count() is executed\n"); 5387 CALL_PDEBUG("me4000_ext_int_count() is executed\n");
@@ -5404,10 +5392,10 @@ static int me4000_ext_int_count(unsigned long *arg,
5404 5392
5405/*------------------------------------ General stuff ------------------------------------*/ 5393/*------------------------------------ General stuff ------------------------------------*/
5406 5394
5407static int me4000_get_user_info(me4000_user_info_t * arg, 5395static int me4000_get_user_info(struct me4000_user_info *arg,
5408 me4000_info_t * board_info) 5396 struct me4000_info *board_info)
5409{ 5397{
5410 me4000_user_info_t user_info; 5398 struct me4000_user_info user_info;
5411 5399
5412 CALL_PDEBUG("me4000_get_user_info() is executed\n"); 5400 CALL_PDEBUG("me4000_get_user_info() is executed\n");
5413 5401
@@ -5437,7 +5425,7 @@ static int me4000_get_user_info(me4000_user_info_t * arg,
5437 5425
5438 user_info.cnt_count = board_info->board_p->cnt.count; 5426 user_info.cnt_count = board_info->board_p->cnt.count;
5439 5427
5440 if (copy_to_user(arg, &user_info, sizeof(me4000_user_info_t))) 5428 if (copy_to_user(arg, &user_info, sizeof(struct me4000_user_info)))
5441 return -EFAULT; 5429 return -EFAULT;
5442 5430
5443 return 0; 5431 return 0;
@@ -5448,7 +5436,7 @@ static int me4000_get_user_info(me4000_user_info_t * arg,
5448static int me4000_ext_int_fasync(int fd, struct file *file_ptr, int mode) 5436static int me4000_ext_int_fasync(int fd, struct file *file_ptr, int mode)
5449{ 5437{
5450 int result = 0; 5438 int result = 0;
5451 me4000_ext_int_context_t *ext_int_context; 5439 struct me4000_ext_int_context *ext_int_context;
5452 5440
5453 CALL_PDEBUG("me4000_ext_int_fasync() is executed\n"); 5441 CALL_PDEBUG("me4000_ext_int_fasync() is executed\n");
5454 5442
@@ -5465,7 +5453,7 @@ static irqreturn_t me4000_ao_isr(int irq, void *dev_id)
5465{ 5453{
5466 u32 tmp; 5454 u32 tmp;
5467 u32 value; 5455 u32 value;
5468 me4000_ao_context_t *ao_context; 5456 struct me4000_ao_context *ao_context;
5469 int i; 5457 int i;
5470 int c = 0; 5458 int c = 0;
5471 int c1 = 0; 5459 int c1 = 0;
@@ -5589,7 +5577,7 @@ static irqreturn_t me4000_ao_isr(int irq, void *dev_id)
5589static irqreturn_t me4000_ai_isr(int irq, void *dev_id) 5577static irqreturn_t me4000_ai_isr(int irq, void *dev_id)
5590{ 5578{
5591 u32 tmp; 5579 u32 tmp;
5592 me4000_ai_context_t *ai_context; 5580 struct me4000_ai_context *ai_context;
5593 int i; 5581 int i;
5594 int c = 0; 5582 int c = 0;
5595 int c1 = 0; 5583 int c1 = 0;
@@ -5933,7 +5921,7 @@ static irqreturn_t me4000_ai_isr(int irq, void *dev_id)
5933 5921
5934static irqreturn_t me4000_ext_int_isr(int irq, void *dev_id) 5922static irqreturn_t me4000_ext_int_isr(int irq, void *dev_id)
5935{ 5923{
5936 me4000_ext_int_context_t *ext_int_context; 5924 struct me4000_ext_int_context *ext_int_context;
5937 unsigned long tmp; 5925 unsigned long tmp;
5938 5926
5939 ISR_PDEBUG("me4000_ext_int_isr() is executed\n"); 5927 ISR_PDEBUG("me4000_ext_int_isr() is executed\n");
@@ -5969,10 +5957,10 @@ static irqreturn_t me4000_ext_int_isr(int irq, void *dev_id)
5969 return IRQ_HANDLED; 5957 return IRQ_HANDLED;
5970} 5958}
5971 5959
5972void __exit me4000_module_exit(void) 5960static void __exit me4000_module_exit(void)
5973{ 5961{
5974 struct list_head *board_p; 5962 struct list_head *board_p;
5975 me4000_info_t *board_info; 5963 struct me4000_info *board_info;
5976 5964
5977 CALL_PDEBUG("cleanup_module() is executed\n"); 5965 CALL_PDEBUG("cleanup_module() is executed\n");
5978 5966
@@ -5993,7 +5981,7 @@ void __exit me4000_module_exit(void)
5993 /* Reset the boards */ 5981 /* Reset the boards */
5994 for (board_p = me4000_board_info_list.next; 5982 for (board_p = me4000_board_info_list.next;
5995 board_p != &me4000_board_info_list; board_p = board_p->next) { 5983 board_p != &me4000_board_info_list; board_p = board_p->next) {
5996 board_info = list_entry(board_p, me4000_info_t, list); 5984 board_info = list_entry(board_p, struct me4000_info, list);
5997 me4000_reset_board(board_info); 5985 me4000_reset_board(board_info);
5998 } 5986 }
5999 5987
@@ -6007,7 +5995,7 @@ static int me4000_read_procmem(char *buf, char **start, off_t offset, int count,
6007{ 5995{
6008 int len = 0; 5996 int len = 0;
6009 int limit = count - 1000; 5997 int limit = count - 1000;
6010 me4000_info_t *board_info; 5998 struct me4000_info *board_info;
6011 struct list_head *ptr; 5999 struct list_head *ptr;
6012 6000
6013 len += sprintf(buf + len, "\nME4000 DRIVER VERSION %X.%X.%X\n\n", 6001 len += sprintf(buf + len, "\nME4000 DRIVER VERSION %X.%X.%X\n\n",
@@ -6019,7 +6007,7 @@ static int me4000_read_procmem(char *buf, char **start, off_t offset, int count,
6019 for (ptr = me4000_board_info_list.next; 6007 for (ptr = me4000_board_info_list.next;
6020 (ptr != &me4000_board_info_list) && (len < limit); 6008 (ptr != &me4000_board_info_list) && (len < limit);
6021 ptr = ptr->next) { 6009 ptr = ptr->next) {
6022 board_info = list_entry(ptr, me4000_info_t, list); 6010 board_info = list_entry(ptr, struct me4000_info, list);
6023 6011
6024 len += 6012 len +=
6025 sprintf(buf + len, "Board number %d:\n", 6013 sprintf(buf + len, "Board number %d:\n",
@@ -6029,14 +6017,14 @@ static int me4000_read_procmem(char *buf, char **start, off_t offset, int count,
6029 sprintf(buf + len, "PLX base register = 0x%lX\n", 6017 sprintf(buf + len, "PLX base register = 0x%lX\n",
6030 board_info->plx_regbase); 6018 board_info->plx_regbase);
6031 len += 6019 len +=
6032 sprintf(buf + len, "PLX base register size = 0x%lX\n", 6020 sprintf(buf + len, "PLX base register size = 0x%X\n",
6033 board_info->plx_regbase_size); 6021 (unsigned int)board_info->plx_regbase_size);
6034 len += 6022 len +=
6035 sprintf(buf + len, "ME4000 base register = 0x%lX\n", 6023 sprintf(buf + len, "ME4000 base register = 0x%X\n",
6036 board_info->me4000_regbase); 6024 (unsigned int)board_info->me4000_regbase);
6037 len += 6025 len +=
6038 sprintf(buf + len, "ME4000 base register size = 0x%lX\n", 6026 sprintf(buf + len, "ME4000 base register size = 0x%X\n",
6039 board_info->me4000_regbase_size); 6027 (unsigned int)board_info->me4000_regbase_size);
6040 len += 6028 len +=
6041 sprintf(buf + len, "Serial number = 0x%X\n", 6029 sprintf(buf + len, "Serial number = 0x%X\n",
6042 board_info->serial_no); 6030 board_info->serial_no);
diff --git a/drivers/staging/me4000/me4000.h b/drivers/staging/me4000/me4000.h
index c35e4b9793a0..81c6f4d5e25c 100644
--- a/drivers/staging/me4000/me4000.h
+++ b/drivers/staging/me4000/me4000.h
@@ -329,46 +329,46 @@
329 Circular buffer used for analog input/output reads/writes. 329 Circular buffer used for analog input/output reads/writes.
330 ===========================================================================*/ 330 ===========================================================================*/
331 331
332typedef struct me4000_circ_buf { 332struct me4000_circ_buf {
333 s16 *buf; 333 s16 *buf;
334 int volatile head; 334 int volatile head;
335 int volatile tail; 335 int volatile tail;
336} me4000_circ_buf_t; 336};
337 337
338/*============================================================================= 338/*=============================================================================
339 Information about the hardware capabilities 339 Information about the hardware capabilities
340 ===========================================================================*/ 340 ===========================================================================*/
341 341
342typedef struct me4000_ao_info { 342struct me4000_ao_info {
343 int count; 343 int count;
344 int fifo_count; 344 int fifo_count;
345} me4000_ao_info_t; 345};
346 346
347typedef struct me4000_ai_info { 347struct me4000_ai_info {
348 int count; 348 int count;
349 int sh_count; 349 int sh_count;
350 int diff_count; 350 int diff_count;
351 int ex_trig_analog; 351 int ex_trig_analog;
352} me4000_ai_info_t; 352};
353 353
354typedef struct me4000_dio_info { 354struct me4000_dio_info {
355 int count; 355 int count;
356} me4000_dio_info_t; 356};
357 357
358typedef struct me4000_cnt_info { 358struct me4000_cnt_info {
359 int count; 359 int count;
360} me4000_cnt_info_t; 360};
361 361
362typedef struct me4000_board { 362struct me4000_board {
363 u16 vendor_id; 363 u16 vendor_id;
364 u16 device_id; 364 u16 device_id;
365 me4000_ao_info_t ao; 365 struct me4000_ao_info ao;
366 me4000_ai_info_t ai; 366 struct me4000_ai_info ai;
367 me4000_dio_info_t dio; 367 struct me4000_dio_info dio;
368 me4000_cnt_info_t cnt; 368 struct me4000_cnt_info cnt;
369} me4000_board_t; 369};
370 370
371static me4000_board_t me4000_boards[] = { 371static struct me4000_board me4000_boards[] = {
372 {PCI_VENDOR_ID_MEILHAUS, 0x4610, {0, 0}, {16, 0, 0, 0}, {4}, {3}}, 372 {PCI_VENDOR_ID_MEILHAUS, 0x4610, {0, 0}, {16, 0, 0, 0}, {4}, {3}},
373 373
374 {PCI_VENDOR_ID_MEILHAUS, 0x4650, {0, 0}, {16, 0, 0, 0}, {4}, {0}}, 374 {PCI_VENDOR_ID_MEILHAUS, 0x4650, {0, 0}, {16, 0, 0, 0}, {4}, {0}},
@@ -391,8 +391,6 @@ static me4000_board_t me4000_boards[] = {
391 {0}, 391 {0},
392}; 392};
393 393
394#define ME4000_BOARD_VERSIONS (sizeof(me4000_boards) / sizeof(me4000_board_t) - 1)
395
396/*============================================================================= 394/*=============================================================================
397 PCI device table. 395 PCI device table.
398 This is used by modprobe to translate PCI IDs to drivers. 396 This is used by modprobe to translate PCI IDs to drivers.
@@ -427,19 +425,19 @@ MODULE_DEVICE_TABLE(pci, me4000_pci_table);
427 Global board and subdevice information structures 425 Global board and subdevice information structures
428 ===========================================================================*/ 426 ===========================================================================*/
429 427
430typedef struct me4000_info { 428struct me4000_info {
431 struct list_head list; // List of all detected boards 429 struct list_head list; // List of all detected boards
432 int board_count; // Index of the board after detection 430 int board_count; // Index of the board after detection
433 431
434 unsigned long plx_regbase; // PLX configuration space base address 432 unsigned long plx_regbase; // PLX configuration space base address
435 unsigned long me4000_regbase; // Base address of the ME4000 433 resource_size_t me4000_regbase; // Base address of the ME4000
436 unsigned long timer_regbase; // Base address of the timer circuit 434 resource_size_t timer_regbase; // Base address of the timer circuit
437 unsigned long program_regbase; // Base address to set the program pin for the xilinx 435 resource_size_t program_regbase; // Base address to set the program pin for the xilinx
438 436
439 unsigned long plx_regbase_size; // PLX register set space 437 unsigned long plx_regbase_size; // PLX register set space
440 unsigned long me4000_regbase_size; // ME4000 register set space 438 resource_size_t me4000_regbase_size; // ME4000 register set space
441 unsigned long timer_regbase_size; // Timer circuit register set space 439 resource_size_t timer_regbase_size; // Timer circuit register set space
442 unsigned long program_regbase_size; // Size of program base address of the ME4000 440 resource_size_t program_regbase_size; // Size of program base address of the ME4000
443 441
444 unsigned int serial_no; // Serial number of the board 442 unsigned int serial_no; // Serial number of the board
445 unsigned char hw_revision; // Hardware revision of the board 443 unsigned char hw_revision; // Hardware revision of the board
@@ -451,7 +449,7 @@ typedef struct me4000_info {
451 int pci_func_no; // PCI function number 449 int pci_func_no; // PCI function number
452 struct pci_dev *pci_dev_p; // General PCI information 450 struct pci_dev *pci_dev_p; // General PCI information
453 451
454 me4000_board_t *board_p; // Holds the board capabilities 452 struct me4000_board *board_p; // Holds the board capabilities
455 453
456 unsigned int irq; // IRQ assigned from the PCI BIOS 454 unsigned int irq; // IRQ assigned from the PCI BIOS
457 unsigned int irq_count; // Count of external interrupts 455 unsigned int irq_count; // Count of external interrupts
@@ -464,18 +462,18 @@ typedef struct me4000_info {
464 struct me4000_dio_context *dio_context; // Digital I/O specific context 462 struct me4000_dio_context *dio_context; // Digital I/O specific context
465 struct me4000_cnt_context *cnt_context; // Counter specific context 463 struct me4000_cnt_context *cnt_context; // Counter specific context
466 struct me4000_ext_int_context *ext_int_context; // External interrupt specific context 464 struct me4000_ext_int_context *ext_int_context; // External interrupt specific context
467} me4000_info_t; 465};
468 466
469typedef struct me4000_ao_context { 467struct me4000_ao_context {
470 struct list_head list; // linked list of me4000_ao_context_t 468 struct list_head list; // linked list of me4000_ao_context_t
471 int index; // Index in the list 469 int index; // Index in the list
472 int mode; // Indicates mode (0 = single, 1 = wraparound, 2 = continous) 470 int mode; // Indicates mode (0 = single, 1 = wraparound, 2 = continous)
473 int dac_in_use; // Indicates if already opend 471 int dac_in_use; // Indicates if already opend
474 spinlock_t use_lock; // Guards in_use 472 spinlock_t use_lock; // Guards in_use
475 spinlock_t int_lock; // Used when locking out interrupts 473 spinlock_t int_lock; // Used when locking out interrupts
476 me4000_circ_buf_t circ_buf; // Circular buffer 474 struct me4000_circ_buf circ_buf; // Circular buffer
477 wait_queue_head_t wait_queue; // Wait queue to sleep while blocking write 475 wait_queue_head_t wait_queue; // Wait queue to sleep while blocking write
478 me4000_info_t *board_info; 476 struct me4000_info *board_info;
479 unsigned int irq; // The irq associated with this ADC 477 unsigned int irq; // The irq associated with this ADC
480 int volatile pipe_flag; // Indicates broken pipe set from me4000_ao_isr() 478 int volatile pipe_flag; // Indicates broken pipe set from me4000_ao_isr()
481 unsigned long ctrl_reg; 479 unsigned long ctrl_reg;
@@ -486,9 +484,9 @@ typedef struct me4000_ao_context {
486 unsigned long irq_status_reg; 484 unsigned long irq_status_reg;
487 unsigned long preload_reg; 485 unsigned long preload_reg;
488 struct fasync_struct *fasync_p; // Queue for asynchronous notification 486 struct fasync_struct *fasync_p; // Queue for asynchronous notification
489} me4000_ao_context_t; 487};
490 488
491typedef struct me4000_ai_context { 489struct me4000_ai_context {
492 struct list_head list; // linked list of me4000_ai_info_t 490 struct list_head list; // linked list of me4000_ai_info_t
493 int mode; // Indicates mode 491 int mode; // Indicates mode
494 int in_use; // Indicates if already opend 492 int in_use; // Indicates if already opend
@@ -496,9 +494,9 @@ typedef struct me4000_ai_context {
496 spinlock_t int_lock; // Used when locking out interrupts 494 spinlock_t int_lock; // Used when locking out interrupts
497 int number; // Number of the DAC 495 int number; // Number of the DAC
498 unsigned int irq; // The irq associated with this ADC 496 unsigned int irq; // The irq associated with this ADC
499 me4000_circ_buf_t circ_buf; // Circular buffer 497 struct me4000_circ_buf circ_buf; // Circular buffer
500 wait_queue_head_t wait_queue; // Wait queue to sleep while blocking read 498 wait_queue_head_t wait_queue; // Wait queue to sleep while blocking read
501 me4000_info_t *board_info; 499 struct me4000_info *board_info;
502 500
503 struct fasync_struct *fasync_p; // Queue for asynchronous notification 501 struct fasync_struct *fasync_p; // Queue for asynchronous notification
504 502
@@ -523,48 +521,48 @@ typedef struct me4000_ai_context {
523 unsigned long channel_list_count; 521 unsigned long channel_list_count;
524 unsigned long sample_counter; 522 unsigned long sample_counter;
525 int sample_counter_reload; 523 int sample_counter_reload;
526} me4000_ai_context_t; 524};
527 525
528typedef struct me4000_dio_context { 526struct me4000_dio_context {
529 struct list_head list; // linked list of me4000_dio_context_t 527 struct list_head list; // linked list of me4000_dio_context_t
530 int in_use; // Indicates if already opend 528 int in_use; // Indicates if already opend
531 spinlock_t use_lock; // Guards in_use 529 spinlock_t use_lock; // Guards in_use
532 int number; 530 int number;
533 int dio_count; 531 int dio_count;
534 me4000_info_t *board_info; 532 struct me4000_info *board_info;
535 unsigned long dir_reg; 533 unsigned long dir_reg;
536 unsigned long ctrl_reg; 534 unsigned long ctrl_reg;
537 unsigned long port_0_reg; 535 unsigned long port_0_reg;
538 unsigned long port_1_reg; 536 unsigned long port_1_reg;
539 unsigned long port_2_reg; 537 unsigned long port_2_reg;
540 unsigned long port_3_reg; 538 unsigned long port_3_reg;
541} me4000_dio_context_t; 539};
542 540
543typedef struct me4000_cnt_context { 541struct me4000_cnt_context {
544 struct list_head list; // linked list of me4000_dio_context_t 542 struct list_head list; // linked list of me4000_dio_context_t
545 int in_use; // Indicates if already opend 543 int in_use; // Indicates if already opend
546 spinlock_t use_lock; // Guards in_use 544 spinlock_t use_lock; // Guards in_use
547 int number; 545 int number;
548 int cnt_count; 546 int cnt_count;
549 me4000_info_t *board_info; 547 struct me4000_info *board_info;
550 unsigned long ctrl_reg; 548 unsigned long ctrl_reg;
551 unsigned long counter_0_reg; 549 unsigned long counter_0_reg;
552 unsigned long counter_1_reg; 550 unsigned long counter_1_reg;
553 unsigned long counter_2_reg; 551 unsigned long counter_2_reg;
554} me4000_cnt_context_t; 552};
555 553
556typedef struct me4000_ext_int_context { 554struct me4000_ext_int_context {
557 struct list_head list; // linked list of me4000_dio_context_t 555 struct list_head list; // linked list of me4000_dio_context_t
558 int in_use; // Indicates if already opend 556 int in_use; // Indicates if already opend
559 spinlock_t use_lock; // Guards in_use 557 spinlock_t use_lock; // Guards in_use
560 int number; 558 int number;
561 me4000_info_t *board_info; 559 struct me4000_info *board_info;
562 unsigned int irq; 560 unsigned int irq;
563 unsigned long int_count; 561 unsigned long int_count;
564 struct fasync_struct *fasync_ptr; 562 struct fasync_struct *fasync_ptr;
565 unsigned long ctrl_reg; 563 unsigned long ctrl_reg;
566 unsigned long irq_status_reg; 564 unsigned long irq_status_reg;
567} me4000_ext_int_context_t; 565};
568 566
569#endif 567#endif
570 568
@@ -745,12 +743,12 @@ typedef struct me4000_ext_int_context {
745 General type definitions 743 General type definitions
746 ----------------------------------------------------------------------------*/ 744 ----------------------------------------------------------------------------*/
747 745
748typedef struct me4000_user_info { 746struct me4000_user_info {
749 int board_count; // Index of the board after detection 747 int board_count; // Index of the board after detection
750 unsigned long plx_regbase; // PLX configuration space base address 748 unsigned long plx_regbase; // PLX configuration space base address
751 unsigned long me4000_regbase; // Base address of the ME4000 749 resource_size_t me4000_regbase; // Base address of the ME4000
752 unsigned long plx_regbase_size; // PLX register set space 750 unsigned long plx_regbase_size; // PLX register set space
753 unsigned long me4000_regbase_size; // ME4000 register set space 751 resource_size_t me4000_regbase_size; // ME4000 register set space
754 unsigned long serial_no; // Serial number of the board 752 unsigned long serial_no; // Serial number of the board
755 unsigned char hw_revision; // Hardware revision of the board 753 unsigned char hw_revision; // Hardware revision of the board
756 unsigned short vendor_id; // Meilhaus vendor id (0x1402) 754 unsigned short vendor_id; // Meilhaus vendor id (0x1402)
@@ -773,62 +771,62 @@ typedef struct me4000_user_info {
773 int dio_count; // Count of digital I/O ports 771 int dio_count; // Count of digital I/O ports
774 772
775 int cnt_count; // Count of counters 773 int cnt_count; // Count of counters
776} me4000_user_info_t; 774};
777 775
778/*----------------------------------------------------------------------------- 776/*-----------------------------------------------------------------------------
779 Type definitions for analog output 777 Type definitions for analog output
780 ----------------------------------------------------------------------------*/ 778 ----------------------------------------------------------------------------*/
781 779
782typedef struct me4000_ao_channel_list { 780struct me4000_ao_channel_list {
783 unsigned long count; 781 unsigned long count;
784 unsigned long *list; 782 unsigned long *list;
785} me4000_ao_channel_list_t; 783};
786 784
787/*----------------------------------------------------------------------------- 785/*-----------------------------------------------------------------------------
788 Type definitions for analog input 786 Type definitions for analog input
789 ----------------------------------------------------------------------------*/ 787 ----------------------------------------------------------------------------*/
790 788
791typedef struct me4000_ai_channel_list { 789struct me4000_ai_channel_list {
792 unsigned long count; 790 unsigned long count;
793 unsigned long *list; 791 unsigned long *list;
794} me4000_ai_channel_list_t; 792};
795 793
796typedef struct me4000_ai_timer { 794struct me4000_ai_timer {
797 unsigned long pre_chan; 795 unsigned long pre_chan;
798 unsigned long chan; 796 unsigned long chan;
799 unsigned long scan_low; 797 unsigned long scan_low;
800 unsigned long scan_high; 798 unsigned long scan_high;
801} me4000_ai_timer_t; 799};
802 800
803typedef struct me4000_ai_config { 801struct me4000_ai_config {
804 me4000_ai_timer_t timer; 802 struct me4000_ai_timer timer;
805 me4000_ai_channel_list_t channel_list; 803 struct me4000_ai_channel_list channel_list;
806 int sh; 804 int sh;
807} me4000_ai_config_t; 805};
808 806
809typedef struct me4000_ai_single { 807struct me4000_ai_single {
810 int channel; 808 int channel;
811 int range; 809 int range;
812 int mode; 810 int mode;
813 short value; 811 short value;
814 unsigned long timeout; 812 unsigned long timeout;
815} me4000_ai_single_t; 813};
816 814
817typedef struct me4000_ai_trigger { 815struct me4000_ai_trigger {
818 int mode; 816 int mode;
819 int edge; 817 int edge;
820} me4000_ai_trigger_t; 818};
821 819
822typedef struct me4000_ai_sc { 820struct me4000_ai_sc {
823 unsigned long value; 821 unsigned long value;
824 int reload; 822 int reload;
825} me4000_ai_sc_t; 823};
826 824
827/*----------------------------------------------------------------------------- 825/*-----------------------------------------------------------------------------
828 Type definitions for eeprom 826 Type definitions for eeprom
829 ----------------------------------------------------------------------------*/ 827 ----------------------------------------------------------------------------*/
830 828
831typedef struct me4000_eeprom { 829struct me4000_eeprom {
832 unsigned long date; 830 unsigned long date;
833 short uni_10_offset; 831 short uni_10_offset;
834 short uni_10_fullscale; 832 short uni_10_fullscale;
@@ -842,45 +840,45 @@ typedef struct me4000_eeprom {
842 short diff_10_fullscale; 840 short diff_10_fullscale;
843 short diff_2_5_offset; 841 short diff_2_5_offset;
844 short diff_2_5_fullscale; 842 short diff_2_5_fullscale;
845} me4000_eeprom_t; 843};
846 844
847/*----------------------------------------------------------------------------- 845/*-----------------------------------------------------------------------------
848 Type definitions for digital I/O 846 Type definitions for digital I/O
849 ----------------------------------------------------------------------------*/ 847 ----------------------------------------------------------------------------*/
850 848
851typedef struct me4000_dio_config { 849struct me4000_dio_config {
852 int port; 850 int port;
853 int mode; 851 int mode;
854 int function; 852 int function;
855} me4000_dio_config_t; 853};
856 854
857typedef struct me4000_dio_byte { 855struct me4000_dio_byte {
858 int port; 856 int port;
859 unsigned char byte; 857 unsigned char byte;
860} me4000_dio_byte_t; 858};
861 859
862/*----------------------------------------------------------------------------- 860/*-----------------------------------------------------------------------------
863 Type definitions for counters 861 Type definitions for counters
864 ----------------------------------------------------------------------------*/ 862 ----------------------------------------------------------------------------*/
865 863
866typedef struct me4000_cnt { 864struct me4000_cnt {
867 int counter; 865 int counter;
868 unsigned short value; 866 unsigned short value;
869} me4000_cnt_t; 867};
870 868
871typedef struct me4000_cnt_config { 869struct me4000_cnt_config {
872 int counter; 870 int counter;
873 int mode; 871 int mode;
874} me4000_cnt_config_t; 872};
875 873
876/*----------------------------------------------------------------------------- 874/*-----------------------------------------------------------------------------
877 Type definitions for external interrupt 875 Type definitions for external interrupt
878 ----------------------------------------------------------------------------*/ 876 ----------------------------------------------------------------------------*/
879 877
880typedef struct { 878struct me4000_int {
881 int int1_count; 879 int int1_count;
882 int int2_count; 880 int int2_count;
883} me4000_int_type; 881};
884 882
885/*----------------------------------------------------------------------------- 883/*-----------------------------------------------------------------------------
886 The ioctls of the board 884 The ioctls of the board
@@ -888,7 +886,8 @@ typedef struct {
888 886
889#define ME4000_IOCTL_MAXNR 50 887#define ME4000_IOCTL_MAXNR 50
890#define ME4000_MAGIC 'y' 888#define ME4000_MAGIC 'y'
891#define ME4000_GET_USER_INFO _IOR (ME4000_MAGIC, 0, me4000_user_info_t) 889#define ME4000_GET_USER_INFO _IOR (ME4000_MAGIC, 0, \
890 struct me4000_user_info)
892 891
893#define ME4000_AO_START _IOW (ME4000_MAGIC, 1, unsigned long) 892#define ME4000_AO_START _IOW (ME4000_MAGIC, 1, unsigned long)
894#define ME4000_AO_STOP _IO (ME4000_MAGIC, 2) 893#define ME4000_AO_STOP _IO (ME4000_MAGIC, 2)
@@ -904,25 +903,35 @@ typedef struct {
904#define ME4000_AO_DISABLE_DO _IO (ME4000_MAGIC, 12) 903#define ME4000_AO_DISABLE_DO _IO (ME4000_MAGIC, 12)
905#define ME4000_AO_FSM_STATE _IOR (ME4000_MAGIC, 13, int) 904#define ME4000_AO_FSM_STATE _IOR (ME4000_MAGIC, 13, int)
906 905
907#define ME4000_AI_SINGLE _IOR (ME4000_MAGIC, 14, me4000_ai_single_t) 906#define ME4000_AI_SINGLE _IOR (ME4000_MAGIC, 14, \
907 struct me4000_ai_single)
908#define ME4000_AI_START _IOW (ME4000_MAGIC, 15, unsigned long) 908#define ME4000_AI_START _IOW (ME4000_MAGIC, 15, unsigned long)
909#define ME4000_AI_STOP _IO (ME4000_MAGIC, 16) 909#define ME4000_AI_STOP _IO (ME4000_MAGIC, 16)
910#define ME4000_AI_IMMEDIATE_STOP _IO (ME4000_MAGIC, 17) 910#define ME4000_AI_IMMEDIATE_STOP _IO (ME4000_MAGIC, 17)
911#define ME4000_AI_EX_TRIG_ENABLE _IO (ME4000_MAGIC, 18) 911#define ME4000_AI_EX_TRIG_ENABLE _IO (ME4000_MAGIC, 18)
912#define ME4000_AI_EX_TRIG_DISABLE _IO (ME4000_MAGIC, 19) 912#define ME4000_AI_EX_TRIG_DISABLE _IO (ME4000_MAGIC, 19)
913#define ME4000_AI_EX_TRIG_SETUP _IOW (ME4000_MAGIC, 20, me4000_ai_trigger_t) 913#define ME4000_AI_EX_TRIG_SETUP _IOW (ME4000_MAGIC, 20, \
914#define ME4000_AI_CONFIG _IOW (ME4000_MAGIC, 21, me4000_ai_config_t) 914 struct me4000_ai_trigger)
915#define ME4000_AI_SC_SETUP _IOW (ME4000_MAGIC, 22, me4000_ai_sc_t) 915#define ME4000_AI_CONFIG _IOW (ME4000_MAGIC, 21, \
916 struct me4000_ai_config)
917#define ME4000_AI_SC_SETUP _IOW (ME4000_MAGIC, 22, \
918 struct me4000_ai_sc)
916#define ME4000_AI_FSM_STATE _IOR (ME4000_MAGIC, 23, int) 919#define ME4000_AI_FSM_STATE _IOR (ME4000_MAGIC, 23, int)
917 920
918#define ME4000_DIO_CONFIG _IOW (ME4000_MAGIC, 24, me4000_dio_config_t) 921#define ME4000_DIO_CONFIG _IOW (ME4000_MAGIC, 24, \
919#define ME4000_DIO_GET_BYTE _IOR (ME4000_MAGIC, 25, me4000_dio_byte_t) 922 struct me4000_dio_config)
920#define ME4000_DIO_SET_BYTE _IOW (ME4000_MAGIC, 26, me4000_dio_byte_t) 923#define ME4000_DIO_GET_BYTE _IOR (ME4000_MAGIC, 25, \
924 struct me4000_dio_byte)
925#define ME4000_DIO_SET_BYTE _IOW (ME4000_MAGIC, 26, \
926 struct me4000_dio_byte)
921#define ME4000_DIO_RESET _IO (ME4000_MAGIC, 27) 927#define ME4000_DIO_RESET _IO (ME4000_MAGIC, 27)
922 928
923#define ME4000_CNT_READ _IOR (ME4000_MAGIC, 28, me4000_cnt_t) 929#define ME4000_CNT_READ _IOR (ME4000_MAGIC, 28, \
924#define ME4000_CNT_WRITE _IOW (ME4000_MAGIC, 29, me4000_cnt_t) 930 struct me4000_cnt)
925#define ME4000_CNT_CONFIG _IOW (ME4000_MAGIC, 30, me4000_cnt_config_t) 931#define ME4000_CNT_WRITE _IOW (ME4000_MAGIC, 29, \
932 struct me4000_cnt)
933#define ME4000_CNT_CONFIG _IOW (ME4000_MAGIC, 30, \
934 struct me4000_cnt_config)
926#define ME4000_CNT_RESET _IO (ME4000_MAGIC, 31) 935#define ME4000_CNT_RESET _IO (ME4000_MAGIC, 31)
927 936
928#define ME4000_EXT_INT_DISABLE _IO (ME4000_MAGIC, 32) 937#define ME4000_EXT_INT_DISABLE _IO (ME4000_MAGIC, 32)
@@ -934,13 +943,16 @@ typedef struct {
934#define ME4000_AI_FULLSCALE_ENABLE _IO (ME4000_MAGIC, 37) 943#define ME4000_AI_FULLSCALE_ENABLE _IO (ME4000_MAGIC, 37)
935#define ME4000_AI_FULLSCALE_DISABLE _IO (ME4000_MAGIC, 38) 944#define ME4000_AI_FULLSCALE_DISABLE _IO (ME4000_MAGIC, 38)
936 945
937#define ME4000_AI_EEPROM_READ _IOR (ME4000_MAGIC, 39, me4000_eeprom_t) 946#define ME4000_AI_EEPROM_READ _IOR (ME4000_MAGIC, 39, \
938#define ME4000_AI_EEPROM_WRITE _IOW (ME4000_MAGIC, 40, me4000_eeprom_t) 947 struct me4000_eeprom)
948#define ME4000_AI_EEPROM_WRITE _IOW (ME4000_MAGIC, 40, \
949 struct me4000_eeprom)
939 950
940#define ME4000_AO_SIMULTANEOUS_EX_TRIG _IO (ME4000_MAGIC, 41) 951#define ME4000_AO_SIMULTANEOUS_EX_TRIG _IO (ME4000_MAGIC, 41)
941#define ME4000_AO_SIMULTANEOUS_SW _IO (ME4000_MAGIC, 42) 952#define ME4000_AO_SIMULTANEOUS_SW _IO (ME4000_MAGIC, 42)
942#define ME4000_AO_SIMULTANEOUS_DISABLE _IO (ME4000_MAGIC, 43) 953#define ME4000_AO_SIMULTANEOUS_DISABLE _IO (ME4000_MAGIC, 43)
943#define ME4000_AO_SIMULTANEOUS_UPDATE _IOW (ME4000_MAGIC, 44, me4000_ao_channel_list_t) 954#define ME4000_AO_SIMULTANEOUS_UPDATE _IOW (ME4000_MAGIC, 44, \
955 struct me4000_ao_channel_list)
944 956
945#define ME4000_AO_SYNCHRONOUS_EX_TRIG _IO (ME4000_MAGIC, 45) 957#define ME4000_AO_SYNCHRONOUS_EX_TRIG _IO (ME4000_MAGIC, 45)
946#define ME4000_AO_SYNCHRONOUS_SW _IO (ME4000_MAGIC, 46) 958#define ME4000_AO_SYNCHRONOUS_SW _IO (ME4000_MAGIC, 46)
diff --git a/drivers/staging/pcc-acpi/Kconfig b/drivers/staging/pcc-acpi/Kconfig
new file mode 100644
index 000000000000..6720d4086baf
--- /dev/null
+++ b/drivers/staging/pcc-acpi/Kconfig
@@ -0,0 +1,11 @@
1config PCC_ACPI
2 tristate "Panasonic ACPI Hotkey support"
3 depends on ACPI
4 default n
5 ---help---
6 This driver provides support for Panasonic hotkeys through the
7 ACPI interface. This works for the Panasonic R1 (N variant),
8 R2, R3, T2, W2, and Y2 laptops.
9
10 To compile this driver as a module, choose M here. The module
11 will be called pcc-acpi.
diff --git a/drivers/staging/pcc-acpi/Makefile b/drivers/staging/pcc-acpi/Makefile
new file mode 100644
index 000000000000..f93b29edf61e
--- /dev/null
+++ b/drivers/staging/pcc-acpi/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_PCC_ACPI) += pcc-acpi.o
diff --git a/drivers/staging/pcc-acpi/TODO b/drivers/staging/pcc-acpi/TODO
new file mode 100644
index 000000000000..fab240982286
--- /dev/null
+++ b/drivers/staging/pcc-acpi/TODO
@@ -0,0 +1,7 @@
1TODO:
2 - Lindent fixes
3 - checkpatch.pl fixes
4 - verify that the acpi interface is correct
5 - remove /proc dependancy if needed (not sure yet.)
6
7Please send any patches for this driver to Greg Kroah-Hartman <greg@kroah.com>
diff --git a/drivers/staging/pcc-acpi/pcc-acpi.c b/drivers/staging/pcc-acpi/pcc-acpi.c
new file mode 100644
index 000000000000..7715c31f2731
--- /dev/null
+++ b/drivers/staging/pcc-acpi/pcc-acpi.c
@@ -0,0 +1,1111 @@
1/*
2 * Panasonic HotKey and lcd brightness control Extra driver
3 * (C) 2004 Hiroshi Miura <miura@da-cha.org>
4 * (C) 2004 NTT DATA Intellilink Co. http://www.intellilink.co.jp/
5 * (C) YOKOTA Hiroshi <yokota (at) netlab. is. tsukuba. ac. jp>
6 * (C) 2004 David Bronaugh <dbronaugh>
7 *
8 * derived from toshiba_acpi.c, Copyright (C) 2002-2004 John Belmonte
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * publicshed by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 *---------------------------------------------------------------------------
24 *
25 * ChangeLog:
26 *
27 * Nov.04, 2006 Hiroshi Miura <miura@da-cha.org>
28 * -v0.9 remove warning about section reference.
29 * remove acpi_os_free
30 * add /proc/acpi/pcc/brightness interface to
31 * allow HAL to access.
32 * merge dbronaugh's enhancement
33 * Aug.17, 2004 David Bronaugh (dbronaugh)
34 * - Added screen brightness setting interface
35 * Thanks to the FreeBSD crew
36 * (acpi_panasonic.c authors)
37 * for the ideas I needed to accomplish it
38 *
39 * May.29, 2006 Hiroshi Miura <miura@da-cha.org>
40 * -v0.8.4 follow to change keyinput structure
41 * thanks Fabian Yamaguchi <fabs@cs.tu-berlin.de>,
42 * Jacob Bower <jacob.bower@ic.ac.uk> and
43 * Hiroshi Yokota for providing solutions.
44 *
45 * Oct.02, 2004 Hiroshi Miura <miura@da-cha.org>
46 * -v0.8.2 merge code of YOKOTA Hiroshi
47 * <yokota@netlab.is.tsukuba.ac.jp>.
48 * Add sticky key mode interface.
49 * Refactoring acpi_pcc_generete_keyinput().
50 *
51 * Sep.15, 2004 Hiroshi Miura <miura@da-cha.org>
52 * -v0.8 Generate key input event on input subsystem.
53 * This is based on yet another driver
54 * written by Ryuta Nakanishi.
55 *
56 * Sep.10, 2004 Hiroshi Miura <miura@da-cha.org>
57 * -v0.7 Change proc interface functions using seq_file
58 * facility as same as other ACPI drivers.
59 *
60 * Aug.28, 2004 Hiroshi Miura <miura@da-cha.org>
61 * -v0.6.4 Fix a silly error with status checking
62 *
63 * Aug.25, 2004 Hiroshi Miura <miura@da-cha.org>
64 * -v0.6.3 replace read_acpi_int by standard
65 * function acpi_evaluate_integer
66 * some clean up and make smart copyright notice.
67 * fix return value of pcc_acpi_get_key()
68 * fix checking return value of acpi_bus_register_driver()
69 *
70 * Aug.22, 2004 David Bronaugh <dbronaugh@linuxboxen.org>
71 * -v0.6.2 Add check on ACPI data (num_sifr)
72 * Coding style cleanups, better error messages/handling
73 * Fixed an off-by-one error in memory allocation
74 *
75 * Aug.21, 2004 David Bronaugh <dbronaugh@linuxboxen.org>
76 * -v0.6.1 Fix a silly error with status checking
77 *
78 * Aug.20, 2004 David Bronaugh <dbronaugh@linuxboxen.org>
79 * - v0.6 Correct brightness controls to reflect reality
80 * based on information gleaned by Hiroshi Miura
81 * and discussions with Hiroshi Miura
82 *
83 * Aug.10, 2004 Hiroshi Miura <miura@da-cha.org>
84 * - v0.5 support LCD brightness control
85 * based on the disclosed information by MEI.
86 *
87 * Jul.25, 2004 Hiroshi Miura <miura@da-cha.org>
88 * - v0.4 first post version
89 * add function to retrive SIFR
90 *
91 * Jul.24, 2004 Hiroshi Miura <miura@da-cha.org>
92 * - v0.3 get proper status of hotkey
93 *
94 * Jul.22, 2004 Hiroshi Miura <miura@da-cha.org>
95 * - v0.2 add HotKey handler
96 *
97 * Jul.17, 2004 Hiroshi Miura <miura@da-cha.org>
98 * - v0.1 start from toshiba_acpi driver written by John Belmonte
99 *
100 */
101
102#define ACPI_PCC_VERSION "0.9+hy"
103
104#include <linux/kernel.h>
105#include <linux/module.h>
106#include <linux/types.h>
107#include <linux/ctype.h>
108#include <linux/init.h>
109#include <linux/input.h>
110#include <linux/proc_fs.h>
111#include <linux/seq_file.h>
112#include <linux/slab.h>
113#include <linux/uaccess.h>
114#include <acpi/acpi_bus.h>
115#include <acpi/acpi_drivers.h>
116
117
118/*************************************************************************
119 * "seq" file template definition.
120 */
121/* "seq" initializer */
122#define SEQ_OPEN_FS(_open_func_name_, _show_func_name_) \
123static int _open_func_name_(struct inode *inode, struct file *file) \
124{ \
125 return single_open(file, _show_func_name_, PDE(inode)->data); \
126}
127
128/*-------------------------------------------------------------------------
129 * "seq" fops template for read-only files.
130 */
131#define SEQ_FILEOPS_R(_open_func_name_) \
132{ \
133 .open = _open_func_name_, \
134 .read = seq_read, \
135 .llseek = seq_lseek, \
136 .release = single_release, \
137}
138
139/*------------------------------------------------------------------------
140 * "seq" fops template for read-write files.
141 */
142#define SEQ_FILEOPS_RW(_open_func_name_, _write_func_name_) \
143{ \
144 .open = _open_func_name_ , \
145 .read = seq_read, \
146 .write = _write_func_name_, \
147 .llseek = seq_lseek, \
148 .release = single_release, \
149}
150
151/*
152 * "seq" file template definition ended.
153 ***************************************************************************
154 */
155#ifndef ACPI_HOTKEY_COMPONENT
156#define ACPI_HOTKEY_COMPONENT 0x10000000
157#endif
158
159#define _COMPONENT ACPI_HOTKEY_COMPONENT
160ACPI_MODULE_NAME("pcc_acpi");
161
162MODULE_AUTHOR("Hiroshi Miura, Hiroshi Yokota");
163MODULE_DESCRIPTION("ACPI HotKey driver for Panasonic Let's Note laptops");
164MODULE_LICENSE("GPL");
165
166#define LOGPREFIX "pcc_acpi: "
167
168/****************************************************
169 * Define ACPI PATHs
170 ****************************************************/
171/* Lets note hotkeys */
172#define METHOD_HKEY_QUERY "HINF"
173#define METHOD_HKEY_SQTY "SQTY"
174#define METHOD_HKEY_SINF "SINF"
175#define METHOD_HKEY_SSET "SSET"
176#define HKEY_NOTIFY 0x80
177
178/* for brightness control */
179#define LCD_MAX_BRIGHTNESS 255
180/* This may be magical -- beware */
181#define LCD_BRIGHTNESS_INCREMENT 17
182/* Registers of SINF */
183#define SINF_LCD_BRIGHTNESS 4
184
185/*******************************************************************
186 *
187 * definitions for /proc/ interface
188 *
189 *******************************************************************/
190#define ACPI_PCC_DRIVER_NAME "pcc_acpi"
191#define ACPI_PCC_DEVICE_NAME "PCCExtra"
192#define ACPI_PCC_CLASS "pcc"
193#define PROC_PCC ACPI_PCC_CLASS
194
195#define ACPI_PCC_INPUT_PHYS "panasonic/hkey0"
196
197/* This is transitional definition */
198#ifndef KEY_BATT
199# define KEY_BATT 227
200#endif
201
202#define PROC_STR_MAX_LEN 8
203
204#define BUS_PCC_HOTKEY BUS_I8042 /*0x1a*/ /* FIXME: BUS_I8042? */
205
206/* Fn+F4/F5 confricts with Shift+F1/F2 */
207/* This hack avoids key number confrict */
208#define PCC_KEYINPUT_MODE (0)
209
210/* LCD_TYPEs: 0 = Normal, 1 = Semi-transparent
211 ENV_STATEs: Normal temp=0x01, High temp=0x81, N/A=0x00
212*/
213enum SINF_BITS { SINF_NUM_BATTERIES = 0,
214 SINF_LCD_TYPE,
215 SINF_AC_MAX_BRIGHT,
216 SINF_AC_MIN_BRIGHT,
217 SINF_AC_CUR_BRIGHT,
218 /* 4 = R1 only handle SINF_AC_CUR_BRIGHT
219 * as SINF_CUR_BRIGHT and don't know AC state */
220 SINF_DC_MAX_BRIGHT,
221 SINF_DC_MIN_BRIGHT,
222 SINF_DC_CUR_BRIGHT,
223 SINF_MUTE,
224 SINF_RESERVED,
225 SINF_ENV_STATE, /* 10 */
226 SINF_STICKY_KEY = 0x80,
227};
228
229static struct acpi_device_id pcc_device_ids[] = {
230 {"MAT0012", 0},
231 {"MAT0013", 0},
232 {"MAT0018", 0},
233 {"MAT0019", 0},
234 {"", 0},
235};
236MODULE_DEVICE_TABLE(acpi, pcc_device_ids);
237
238
239static int __devinit acpi_pcc_hotkey_add(struct acpi_device *device);
240static int __devexit acpi_pcc_hotkey_remove(struct acpi_device *device,
241 int type);
242static int acpi_pcc_hotkey_resume(struct acpi_device *device);
243
244
245static struct acpi_driver acpi_pcc_driver = {
246 .name = ACPI_PCC_DRIVER_NAME,
247 .class = ACPI_PCC_CLASS,
248 .ids = pcc_device_ids,
249 .ops = {
250 .add = acpi_pcc_hotkey_add,
251 .remove = __devexit_p(acpi_pcc_hotkey_remove),
252#ifdef CONFIG_PM
253 /*.suspend = acpi_pcc_hotkey_suspend,*/
254 .resume = acpi_pcc_hotkey_resume,
255#endif
256 },
257};
258
259struct acpi_hotkey {
260 acpi_handle handle;
261 struct acpi_device *device;
262 struct proc_dir_entry *proc_dir_entry;
263 unsigned long num_sifr;
264 unsigned long status;
265 struct input_dev *input_dev;
266 int sticky_mode;
267};
268
269struct pcc_keyinput {
270 struct acpi_hotkey *hotkey;
271 int key_mode;
272};
273
274/* *************************************************************************
275 Hotkey driver core
276 ************************************************************************* */
277/* -------------------------------------------------------------------------
278 method access functions
279 ------------------------------------------------------------------------- */
280static int acpi_pcc_write_sset(struct acpi_hotkey *hotkey, int func, int val)
281{
282 union acpi_object in_objs[] = {
283 { .integer.type = ACPI_TYPE_INTEGER,
284 .integer.value = func, },
285 { .integer.type = ACPI_TYPE_INTEGER,
286 .integer.value = val, },
287 };
288 struct acpi_object_list params = {
289 .count = ARRAY_SIZE(in_objs),
290 .pointer = in_objs,
291 };
292 acpi_status status;
293
294 ACPI_FUNCTION_TRACE("acpi_pcc_write_sset");
295
296 status = acpi_evaluate_object(hotkey->handle, METHOD_HKEY_SSET,
297 &params, NULL);
298
299 return_VALUE(status == AE_OK ? AE_OK : AE_ERROR);
300}
301
302static inline int acpi_pcc_get_sqty(struct acpi_device *device)
303{
304 unsigned long s;
305 acpi_status status;
306
307 ACPI_FUNCTION_TRACE("acpi_pcc_get_sqty");
308
309 status = acpi_evaluate_integer(device->handle, METHOD_HKEY_SQTY,
310 NULL, &s);
311 if (ACPI_SUCCESS(status)) {
312 return_VALUE(s);
313 } else {
314 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
315 "evaluation error HKEY.SQTY\n"));
316 return_VALUE(-EINVAL);
317 }
318}
319
320static int acpi_pcc_retrieve_biosdata(struct acpi_hotkey *hotkey, u32 *sinf)
321{
322 acpi_status status;
323 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
324 union acpi_object *hkey = NULL;
325 int i;
326
327 ACPI_FUNCTION_TRACE("acpi_pcc_retrieve_biosdata");
328
329 status = acpi_evaluate_object(hotkey->handle, METHOD_HKEY_SINF, 0,
330 &buffer);
331 if (ACPI_FAILURE(status)) {
332 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
333 "evaluation error HKEY.SINF\n"));
334 status = AE_ERROR;
335 return_VALUE(status);
336 }
337
338 hkey = buffer.pointer;
339 if (!hkey || (hkey->type != ACPI_TYPE_PACKAGE)) {
340 ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid HKEY.SINF\n"));
341 goto free_buffer;
342 }
343
344 if (hotkey->num_sifr < hkey->package.count) {
345 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
346 "SQTY reports bad SINF length\n"));
347 status = AE_ERROR;
348 goto free_buffer;
349 }
350
351 for (i = 0; i < hkey->package.count; i++) {
352 union acpi_object *element = &(hkey->package.elements[i]);
353 if (likely(element->type == ACPI_TYPE_INTEGER)) {
354 sinf[i] = element->integer.value;
355 } else {
356 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
357 "Invalid HKEY.SINF data\n"));
358 status = AE_ERROR;
359 break;
360 }
361 }
362 sinf[hkey->package.count] = -1;
363
364 free_buffer:
365 kfree(buffer.pointer);
366 return_VALUE(status == AE_OK ? AE_OK : AE_ERROR);
367}
368
369static int acpi_pcc_read_sinf_field(struct seq_file *seq, int field)
370{
371 struct acpi_hotkey *hotkey = (struct acpi_hotkey *) seq->private;
372 u32 sinf[hotkey->num_sifr + 1];
373
374 ACPI_FUNCTION_TRACE("acpi_pcc_read_sinf_field");
375
376 if (ACPI_SUCCESS(acpi_pcc_retrieve_biosdata(hotkey, sinf)))
377 seq_printf(seq, "%u\n", sinf[field]);
378 else
379 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
380 "Couldn't retrieve BIOS data\n"));
381
382 return_VALUE(AE_OK);
383}
384
385/* -------------------------------------------------------------------------
386 user interface functions
387 ------------------------------------------------------------------------- */
388/* read methods */
389/* Sinf read methods */
390#define PCC_SINF_READ_F(_name_, FUNC) \
391static int _name_(struct seq_file *seq, void *offset) \
392{ \
393 return_VALUE(ACPI_SUCCESS(acpi_pcc_read_sinf_field(seq, \
394 (FUNC))) \
395 ? 0 : -EINVAL); \
396}
397
398PCC_SINF_READ_F(acpi_pcc_numbatteries_show, SINF_NUM_BATTERIES);
399PCC_SINF_READ_F(acpi_pcc_lcdtype_show, SINF_LCD_TYPE);
400PCC_SINF_READ_F(acpi_pcc_ac_brightness_max_show, SINF_AC_MAX_BRIGHT);
401PCC_SINF_READ_F(acpi_pcc_ac_brightness_min_show, SINF_AC_MIN_BRIGHT);
402PCC_SINF_READ_F(acpi_pcc_ac_brightness_show, SINF_AC_CUR_BRIGHT);
403PCC_SINF_READ_F(acpi_pcc_dc_brightness_max_show, SINF_DC_MAX_BRIGHT);
404PCC_SINF_READ_F(acpi_pcc_dc_brightness_min_show, SINF_DC_MIN_BRIGHT);
405PCC_SINF_READ_F(acpi_pcc_dc_brightness_show, SINF_DC_CUR_BRIGHT);
406PCC_SINF_READ_F(acpi_pcc_brightness_show, SINF_AC_CUR_BRIGHT);
407PCC_SINF_READ_F(acpi_pcc_mute_show, SINF_MUTE);
408
409static int acpi_pcc_sticky_key_show(struct seq_file *seq, void *offset)
410{
411 struct acpi_hotkey *hotkey = seq->private;
412
413 ACPI_FUNCTION_TRACE("acpi_pcc_sticky_key_show");
414
415 if (!hotkey || !hotkey->device)
416 return_VALUE(-EINVAL);
417
418 seq_printf(seq, "%d\n", hotkey->sticky_mode);
419
420 return_VALUE(0);
421}
422
423static int acpi_pcc_keyinput_show(struct seq_file *seq, void *offset)
424{
425 struct acpi_hotkey *hotkey = seq->private;
426 struct input_dev *hotk_input_dev = hotkey->input_dev;
427 struct pcc_keyinput *keyinput = input_get_drvdata(hotk_input_dev);
428
429 ACPI_FUNCTION_TRACE("acpi_pcc_keyinput_show");
430
431 seq_printf(seq, "%d\n", keyinput->key_mode);
432
433 return_VALUE(0);
434}
435
436static int acpi_pcc_version_show(struct seq_file *seq, void *offset)
437{
438 struct acpi_hotkey *hotkey = seq->private;
439
440 ACPI_FUNCTION_TRACE("acpi_pcc_version_show");
441
442 if (!hotkey || !hotkey->device)
443 return_VALUE(-EINVAL);
444
445 seq_printf(seq, "%s version %s\n", ACPI_PCC_DRIVER_NAME,
446 ACPI_PCC_VERSION);
447 seq_printf(seq, "%li functions\n", hotkey->num_sifr);
448
449 return_VALUE(0);
450}
451
452/* write methods */
453static ssize_t acpi_pcc_write_single_flag(struct file *file,
454 const char __user *buffer,
455 size_t count,
456 int sinf_func)
457{
458 struct seq_file *seq = file->private_data;
459 struct acpi_hotkey *hotkey = seq->private;
460 char write_string[PROC_STR_MAX_LEN];
461 u32 val;
462
463 ACPI_FUNCTION_TRACE("acpi_pcc_write_single_flag");
464
465 if (!hotkey || (count > sizeof(write_string) - 1))
466 return_VALUE(-EINVAL);
467
468 if (copy_from_user(write_string, buffer, count))
469 return_VALUE(-EFAULT);
470
471 write_string[count] = '\0';
472
473 if ((sscanf(write_string, "%3i", &val) == 1) &&
474 (val == 0 || val == 1))
475 acpi_pcc_write_sset(hotkey, sinf_func, val);
476
477 return_VALUE(count);
478}
479
480static unsigned long acpi_pcc_write_brightness(struct file *file,
481 const char __user *buffer,
482 size_t count,
483 int min_index, int max_index,
484 int cur_index)
485{
486 struct seq_file *seq = (struct seq_file *)file->private_data;
487 struct acpi_hotkey *hotkey = (struct acpi_hotkey *)seq->private;
488 char write_string[PROC_STR_MAX_LEN];
489 u32 bright;
490 u32 sinf[hotkey->num_sifr + 1];
491
492 ACPI_FUNCTION_TRACE("acpi_pcc_write_brightness");
493
494 if (!hotkey || (count > sizeof(write_string) - 1))
495 return_VALUE(-EINVAL);
496
497 if (copy_from_user(write_string, buffer, count))
498 return_VALUE(-EFAULT);
499
500 write_string[count] = '\0';
501
502 if (ACPI_FAILURE(acpi_pcc_retrieve_biosdata(hotkey, sinf))) {
503 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
504 "Couldn't retrieve BIOS data\n"));
505 goto end;
506 }
507
508 if ((sscanf(write_string, "%4i", &bright) == 1) &&
509 (bright >= sinf[min_index]) &&
510 (bright <= sinf[max_index]))
511 acpi_pcc_write_sset(hotkey, cur_index, bright);
512
513end:
514 return_VALUE(count);
515}
516
517static ssize_t acpi_pcc_write_ac_brightness(struct file *file,
518 const char __user *buffer,
519 size_t count, loff_t *ppos)
520{
521 return_VALUE(acpi_pcc_write_brightness(file, buffer, count,
522 SINF_AC_MIN_BRIGHT,
523 SINF_AC_MAX_BRIGHT,
524 SINF_AC_CUR_BRIGHT));
525}
526
527static ssize_t acpi_pcc_write_dc_brightness(struct file *file,
528 const char __user *buffer,
529 size_t count, loff_t *ppos)
530{
531 return_VALUE(acpi_pcc_write_brightness(file, buffer, count,
532 SINF_DC_MIN_BRIGHT,
533 SINF_DC_MAX_BRIGHT,
534 SINF_DC_CUR_BRIGHT));
535}
536
537static ssize_t acpi_pcc_write_no_brightness(struct file *file,
538 const char __user *buffer,
539 size_t count, loff_t *ppos)
540{
541 return acpi_pcc_write_brightness(file, buffer, count,
542 SINF_AC_MIN_BRIGHT,
543 SINF_AC_MAX_BRIGHT,
544 SINF_AC_CUR_BRIGHT);
545}
546
547static ssize_t acpi_pcc_write_mute(struct file *file,
548 const char __user *buffer,
549 size_t count, loff_t *ppos)
550{
551 return_VALUE(acpi_pcc_write_single_flag(file, buffer, count,
552 SINF_MUTE));
553}
554
555static ssize_t acpi_pcc_write_sticky_key(struct file *file,
556 const char __user *buffer,
557 size_t count, loff_t *ppos)
558{
559 struct seq_file *seq = (struct seq_file *)file->private_data;
560 struct acpi_hotkey *hotkey = (struct acpi_hotkey *)seq->private;
561 char write_string[PROC_STR_MAX_LEN];
562 int mode;
563
564 ACPI_FUNCTION_TRACE("acpi_pcc_write_sticky_key");
565
566 if (!hotkey || (count > sizeof(write_string) - 1))
567 return_VALUE(-EINVAL);
568
569 if (copy_from_user(write_string, buffer, count))
570 return_VALUE(-EFAULT);
571
572 write_string[count] = '\0';
573
574 if ((sscanf(write_string, "%3i", &mode) == 1) &&
575 (mode == 0 || mode == 1)) {
576 acpi_pcc_write_sset(hotkey, SINF_STICKY_KEY, mode);
577 hotkey->sticky_mode = mode;
578 }
579
580 return_VALUE(count);
581}
582
583static ssize_t acpi_pcc_write_keyinput(struct file *file,
584 const char __user *buffer,
585 size_t count, loff_t *ppos)
586{
587 struct seq_file *seq = (struct seq_file *)file->private_data;
588 struct acpi_hotkey *hotkey = (struct acpi_hotkey *)seq->private;
589 struct pcc_keyinput *keyinput;
590 char write_string[PROC_STR_MAX_LEN];
591 int key_mode;
592
593 ACPI_FUNCTION_TRACE("acpi_pcc_write_keyinput");
594
595 if (!hotkey || (count > (sizeof(write_string) - 1)))
596 return_VALUE(-EINVAL);
597
598 if (copy_from_user(write_string, buffer, count))
599 return_VALUE(-EFAULT);
600
601 write_string[count] = '\0';
602
603 if ((sscanf(write_string, "%4i", &key_mode) == 1) &&
604 (key_mode == 0 || key_mode == 1)) {
605 keyinput = input_get_drvdata(hotkey->input_dev);
606 keyinput->key_mode = key_mode;
607 }
608
609 return_VALUE(count);
610}
611
612/* -------------------------------------------------------------------------
613 hotkey driver
614 ------------------------------------------------------------------------- */
615static void acpi_pcc_generete_keyinput(struct acpi_hotkey *hotkey)
616{
617 struct input_dev *hotk_input_dev = hotkey->input_dev;
618 struct pcc_keyinput *keyinput = input_get_drvdata(hotk_input_dev);
619 int hinf = hotkey->status;
620 int key_code, hkey_num;
621 const int key_map[] = {
622 /* 0 */ -1,
623 /* 1 */ KEY_BRIGHTNESSDOWN,
624 /* 2 */ KEY_BRIGHTNESSUP,
625 /* 3 */ -1, /* vga/lcd switch event is not occur on
626 hotkey driver. */
627 /* 4 */ KEY_MUTE,
628 /* 5 */ KEY_VOLUMEDOWN,
629 /* 6 */ KEY_VOLUMEUP,
630 /* 7 */ KEY_SLEEP,
631 /* 8 */ -1, /* Change CPU boost: do nothing */
632 /* 9 */ KEY_BATT,
633 /* 10 */ KEY_SUSPEND,
634 };
635
636 ACPI_FUNCTION_TRACE("acpi_pcc_generete_keyinput");
637
638 if (keyinput->key_mode == 0)
639 return_VOID;
640
641 hkey_num = hinf & 0xf;
642
643 if ((0 > hkey_num) ||
644 (hkey_num > ARRAY_SIZE(key_map))) {
645 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
646 "hotkey number out of range: %d\n",
647 hkey_num));
648 return_VOID;
649 }
650
651 key_code = key_map[hkey_num];
652
653 if (key_code != -1) {
654 int pushed = (hinf & 0x80) ? TRUE : FALSE;
655
656 input_report_key(hotk_input_dev, key_code, pushed);
657 input_sync(hotk_input_dev);
658 }
659}
660
661static int acpi_pcc_hotkey_get_key(struct acpi_hotkey *hotkey)
662{
663 unsigned long result;
664 acpi_status status = AE_OK;
665
666 ACPI_FUNCTION_TRACE("acpi_pcc_hotkey_get_key");
667
668 status = acpi_evaluate_integer(hotkey->handle, METHOD_HKEY_QUERY,
669 NULL, &result);
670 if (likely(ACPI_SUCCESS(status)))
671 hotkey->status = result;
672 else
673 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
674 "error getting hotkey status\n"));
675
676 return_VALUE(status == AE_OK);
677}
678
679void acpi_pcc_hotkey_notify(acpi_handle handle, u32 event, void *data)
680{
681 struct acpi_hotkey *hotkey = (struct acpi_hotkey *) data;
682
683 ACPI_FUNCTION_TRACE("acpi_pcc_hotkey_notify");
684
685 switch (event) {
686 case HKEY_NOTIFY:
687 if (acpi_pcc_hotkey_get_key(hotkey)) {
688 /* generate event like '"pcc HKEY 00000080 00000084"'
689 * when Fn+F4 pressed */
690 acpi_bus_generate_proc_event(hotkey->device, event,
691 hotkey->status);
692 }
693 acpi_pcc_generete_keyinput(hotkey);
694 break;
695 default:
696 /* nothing to do */
697 break;
698 }
699 return_VOID;
700}
701
702/* *************************************************************************
703 FS Interface (/proc)
704 ************************************************************************* */
705/* oepn proc file fs*/
706SEQ_OPEN_FS(acpi_pcc_dc_brightness_open_fs, acpi_pcc_dc_brightness_show);
707SEQ_OPEN_FS(acpi_pcc_numbatteries_open_fs, acpi_pcc_numbatteries_show);
708SEQ_OPEN_FS(acpi_pcc_lcdtype_open_fs, acpi_pcc_lcdtype_show);
709SEQ_OPEN_FS(acpi_pcc_ac_brightness_max_open_fs,
710 acpi_pcc_ac_brightness_max_show);
711SEQ_OPEN_FS(acpi_pcc_ac_brightness_min_open_fs,
712 acpi_pcc_ac_brightness_min_show);
713SEQ_OPEN_FS(acpi_pcc_ac_brightness_open_fs, acpi_pcc_ac_brightness_show);
714SEQ_OPEN_FS(acpi_pcc_dc_brightness_max_open_fs,
715 acpi_pcc_dc_brightness_max_show);
716SEQ_OPEN_FS(acpi_pcc_dc_brightness_min_open_fs,
717 acpi_pcc_dc_brightness_min_show);
718SEQ_OPEN_FS(acpi_pcc_brightness_open_fs, acpi_pcc_brightness_show);
719SEQ_OPEN_FS(acpi_pcc_mute_open_fs, acpi_pcc_mute_show);
720SEQ_OPEN_FS(acpi_pcc_version_open_fs, acpi_pcc_version_show);
721SEQ_OPEN_FS(acpi_pcc_keyinput_open_fs, acpi_pcc_keyinput_show);
722SEQ_OPEN_FS(acpi_pcc_sticky_key_open_fs, acpi_pcc_sticky_key_show);
723
724static struct file_operations acpi_pcc_numbatteries_fops =
725 SEQ_FILEOPS_R(acpi_pcc_numbatteries_open_fs);
726static struct file_operations acpi_pcc_lcdtype_fops =
727 SEQ_FILEOPS_R(acpi_pcc_lcdtype_open_fs);
728static struct file_operations acpi_pcc_mute_fops =
729 SEQ_FILEOPS_RW(acpi_pcc_mute_open_fs, acpi_pcc_write_mute);
730static struct file_operations acpi_pcc_ac_brightness_fops =
731 SEQ_FILEOPS_RW(acpi_pcc_ac_brightness_open_fs,
732 acpi_pcc_write_ac_brightness);
733static struct file_operations acpi_pcc_ac_brightness_max_fops =
734 SEQ_FILEOPS_R(acpi_pcc_ac_brightness_max_open_fs);
735static struct file_operations acpi_pcc_ac_brightness_min_fops =
736 SEQ_FILEOPS_R(acpi_pcc_ac_brightness_min_open_fs);
737static struct file_operations acpi_pcc_dc_brightness_fops =
738 SEQ_FILEOPS_RW(acpi_pcc_dc_brightness_open_fs,
739 acpi_pcc_write_dc_brightness);
740static struct file_operations acpi_pcc_dc_brightness_max_fops =
741 SEQ_FILEOPS_R(acpi_pcc_dc_brightness_max_open_fs);
742static struct file_operations acpi_pcc_dc_brightness_min_fops =
743 SEQ_FILEOPS_R(acpi_pcc_dc_brightness_min_open_fs);
744static struct file_operations acpi_pcc_brightness_fops =
745 SEQ_FILEOPS_RW(acpi_pcc_brightness_open_fs,
746 acpi_pcc_write_no_brightness);
747static struct file_operations acpi_pcc_sticky_key_fops =
748 SEQ_FILEOPS_RW(acpi_pcc_sticky_key_open_fs, acpi_pcc_write_sticky_key);
749static struct file_operations acpi_pcc_keyinput_fops =
750 SEQ_FILEOPS_RW(acpi_pcc_keyinput_open_fs, acpi_pcc_write_keyinput);
751static struct file_operations acpi_pcc_version_fops =
752 SEQ_FILEOPS_R(acpi_pcc_version_open_fs);
753
754struct proc_item {
755 const char *name;
756 struct file_operations *fops;
757 mode_t flag;
758};
759
760/* Note: These functions map *exactly* to the SINF/SSET functions */
761struct proc_item acpi_pcc_proc_items_sifr[] = {
762 { "num_batteries", &acpi_pcc_numbatteries_fops, S_IRUGO },
763 { "lcd_type", &acpi_pcc_lcdtype_fops, S_IRUGO },
764 { "ac_brightness_max", &acpi_pcc_ac_brightness_max_fops, S_IRUGO },
765 { "ac_brightness_min", &acpi_pcc_ac_brightness_min_fops, S_IRUGO },
766 { "ac_brightness", &acpi_pcc_ac_brightness_fops,
767 S_IFREG | S_IRUGO | S_IWUSR },
768 { "dc_brightness_max", &acpi_pcc_dc_brightness_max_fops, S_IRUGO },
769 { "dc_brightness_min", &acpi_pcc_dc_brightness_min_fops, S_IRUGO },
770 { "dc_brightness", &acpi_pcc_dc_brightness_fops,
771 S_IFREG | S_IRUGO | S_IWUSR },
772 { "brightness", &acpi_pcc_brightness_fops, S_IFREG | S_IRUGO | S_IWUSR},
773 { "mute", &acpi_pcc_mute_fops, S_IFREG | S_IRUGO | S_IWUSR },
774 { NULL, NULL, 0 },
775};
776
777struct proc_item acpi_pcc_proc_items[] = {
778 { "sticky_key", &acpi_pcc_sticky_key_fops, S_IFREG | S_IRUGO | S_IWUSR},
779 { "keyinput", &acpi_pcc_keyinput_fops, S_IFREG | S_IRUGO | S_IWUSR },
780 { "version", &acpi_pcc_version_fops, S_IRUGO },
781 { NULL, NULL, 0 },
782};
783
784static int __devinit acpi_pcc_add_device(struct acpi_device *device,
785 struct proc_item *proc_items,
786 int num)
787{
788 struct acpi_hotkey *hotkey = acpi_driver_data(device);
789 struct proc_dir_entry *proc;
790 struct proc_item *item;
791 int i;
792
793 for (item = proc_items, i = 0; item->name && i < num; ++item, ++i) {
794 proc = create_proc_entry(item->name, item->flag,
795 hotkey->proc_dir_entry);
796 if (likely(proc)) {
797 proc->proc_fops = item->fops;
798 proc->data = hotkey;
799 proc->owner = THIS_MODULE;
800 } else {
801 while (i-- > 0) {
802 item--;
803 remove_proc_entry(item->name,
804 hotkey->proc_dir_entry);
805 }
806 return_VALUE(-ENODEV);
807 }
808 }
809 return_VALUE(0);
810}
811
812static int __devinit acpi_pcc_proc_init(struct acpi_device *device)
813{
814 struct proc_dir_entry *acpi_pcc_dir;
815 struct acpi_hotkey *hotkey = acpi_driver_data(device);
816 acpi_status status;
817
818 ACPI_FUNCTION_TRACE("acpi_pcc_proc_init");
819
820 acpi_pcc_dir = proc_mkdir(PROC_PCC, acpi_root_dir);
821
822 if (unlikely(!acpi_pcc_dir)) {
823 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
824 "Couldn't create dir in /proc\n"));
825 return_VALUE(-ENODEV);
826 }
827
828 acpi_pcc_dir->owner = THIS_MODULE;
829 hotkey->proc_dir_entry = acpi_pcc_dir;
830
831 status = acpi_pcc_add_device(device, acpi_pcc_proc_items_sifr,
832 hotkey->num_sifr);
833 status |= acpi_pcc_add_device(device, acpi_pcc_proc_items,
834 ARRAY_SIZE(acpi_pcc_proc_items));
835 if (unlikely(status)) {
836 remove_proc_entry(PROC_PCC, acpi_root_dir);
837 hotkey->proc_dir_entry = NULL;
838 return_VALUE(-ENODEV);
839 }
840
841 return_VALUE(status);
842}
843
844static void __devexit acpi_pcc_remove_device(struct acpi_device *device,
845 struct proc_item *proc_items,
846 int num)
847{
848 struct acpi_hotkey *hotkey = acpi_driver_data(device);
849 struct proc_item *item;
850 int i;
851
852 for (item = proc_items, i = 0;
853 item->name != NULL && i < num;
854 ++item, ++i) {
855 remove_proc_entry(item->name, hotkey->proc_dir_entry);
856 }
857
858 return_VOID;
859}
860
861/* *************************************************************************
862 Power Management
863 ************************************************************************* */
864#ifdef CONFIG_PM
865static int acpi_pcc_hotkey_resume(struct acpi_device *device)
866{
867 struct acpi_hotkey *hotkey = acpi_driver_data(device);
868 acpi_status status = AE_OK;
869
870 ACPI_FUNCTION_TRACE("acpi_pcc_hotkey_resume");
871
872 if (device == NULL || hotkey == NULL)
873 return_VALUE(-EINVAL);
874
875 if (hotkey->num_sifr != 0) {
876 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Sticky mode restore: %d\n",
877 hotkey->sticky_mode));
878
879 status = acpi_pcc_write_sset(hotkey, SINF_STICKY_KEY,
880 hotkey->sticky_mode);
881 }
882 if (status != AE_OK)
883 return_VALUE(-EINVAL);
884
885 return_VALUE(0);
886}
887#endif
888
889/* *************************************************************************
890 Module init/remove
891 ************************************************************************* */
892/* -------------------------------------------------------------------------
893 input
894 ------------------------------------------------------------------------- */
895static int __devinit acpi_pcc_init_input(struct acpi_hotkey *hotkey)
896{
897 struct input_dev *hotk_input_dev;
898 struct pcc_keyinput *pcc_keyinput;
899 int error;
900
901 ACPI_FUNCTION_TRACE("acpi_pcc_init_input");
902
903 hotk_input_dev = input_allocate_device();
904 if (hotk_input_dev == NULL) {
905 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
906 "Couldn't allocate input device for hotkey"));
907 goto err_input;
908 }
909
910 pcc_keyinput = kcalloc(1, sizeof(struct pcc_keyinput), GFP_KERNEL);
911
912 if (pcc_keyinput == NULL) {
913 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
914 "Couldn't allocate mem for private data"));
915 goto err_pcc;
916 }
917
918 hotk_input_dev->evbit[0] = BIT(EV_KEY);
919
920 set_bit(KEY_BRIGHTNESSDOWN, hotk_input_dev->keybit);
921 set_bit(KEY_BRIGHTNESSUP, hotk_input_dev->keybit);
922 set_bit(KEY_MUTE, hotk_input_dev->keybit);
923 set_bit(KEY_VOLUMEDOWN, hotk_input_dev->keybit);
924 set_bit(KEY_VOLUMEUP, hotk_input_dev->keybit);
925 set_bit(KEY_SLEEP, hotk_input_dev->keybit);
926 set_bit(KEY_BATT, hotk_input_dev->keybit);
927 set_bit(KEY_SUSPEND, hotk_input_dev->keybit);
928
929 hotk_input_dev->name = ACPI_PCC_DRIVER_NAME;
930 hotk_input_dev->phys = ACPI_PCC_INPUT_PHYS;
931 hotk_input_dev->id.bustype = BUS_PCC_HOTKEY;
932 hotk_input_dev->id.vendor = 0x0001;
933 hotk_input_dev->id.product = 0x0001;
934 hotk_input_dev->id.version = 0x0100;
935
936 pcc_keyinput->key_mode = PCC_KEYINPUT_MODE;
937 pcc_keyinput->hotkey = hotkey;
938
939 input_set_drvdata(hotk_input_dev, pcc_keyinput);
940
941 hotkey->input_dev = hotk_input_dev;
942
943 error = input_register_device(hotk_input_dev);
944
945 if (error)
946 goto err_pcc;
947
948 return_VALUE(0);
949
950 err_pcc:
951 input_unregister_device(hotk_input_dev);
952 err_input:
953 return_VALUE(-ENOMEM);
954}
955
956static void __devexit acpi_pcc_remove_input(struct acpi_hotkey *hotkey)
957{
958 struct input_dev *hotk_input_dev;
959 struct pcc_keyinput *pcc_keyinput;
960
961 ACPI_FUNCTION_TRACE("acpi_pcc_remove_input");
962
963 if (hotkey == NULL) {
964 ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Can't free memory"));
965 return_VOID;
966 }
967
968 hotk_input_dev = hotkey->input_dev;
969 pcc_keyinput = input_get_drvdata(hotk_input_dev);
970
971 input_unregister_device(hotk_input_dev);
972
973 kfree(pcc_keyinput);
974}
975
976/* -------------------------------------------------------------------------
977 ACPI
978 ------------------------------------------------------------------------- */
979static int __devinit acpi_pcc_hotkey_add(struct acpi_device *device)
980{
981 acpi_status status = AE_OK;
982 struct acpi_hotkey *hotkey = NULL;
983 int sifr_status, num_sifr, result;
984
985 ACPI_FUNCTION_TRACE("acpi_pcc_hotkey_add");
986
987 if (device == NULL)
988 return_VALUE(-EINVAL);
989
990 sifr_status = acpi_pcc_get_sqty(device);
991
992 if (sifr_status > 255) {
993 ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "num_sifr too large"));
994 return_VALUE(-ENODEV);
995 }
996
997 if (sifr_status < 0) {
998 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "not support SQTY"));
999 num_sifr = 0;
1000 } else {
1001 num_sifr = sifr_status;
1002 }
1003
1004 hotkey = kcalloc(1, sizeof(struct acpi_hotkey), GFP_KERNEL);
1005 if (hotkey == NULL) {
1006 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
1007 "Couldn't allocate mem for hotkey"));
1008 return_VALUE(-ENOMEM);
1009 }
1010
1011 hotkey->device = device;
1012 hotkey->handle = device->handle;
1013 hotkey->num_sifr = num_sifr;
1014 acpi_driver_data(device) = hotkey;
1015 strcpy(acpi_device_name(device), ACPI_PCC_DEVICE_NAME);
1016 strcpy(acpi_device_class(device), ACPI_PCC_CLASS);
1017
1018 status = acpi_install_notify_handler(hotkey->handle,
1019 ACPI_DEVICE_NOTIFY,
1020 acpi_pcc_hotkey_notify,
1021 hotkey);
1022
1023 if (ACPI_FAILURE(status)) {
1024 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
1025 "Error installing notify handler\n"));
1026 kfree(hotkey);
1027 return_VALUE(-ENODEV);
1028 }
1029
1030 result = acpi_pcc_init_input(hotkey);
1031 if (result != 0) {
1032 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
1033 "Error installing keyinput handler\n"));
1034 kfree(hotkey);
1035 return_VALUE(result);
1036 }
1037
1038 return_VALUE(acpi_pcc_proc_init(device));
1039}
1040
1041static int __devexit acpi_pcc_hotkey_remove(struct acpi_device *device,
1042 int type)
1043{
1044 acpi_status status = AE_OK;
1045 struct acpi_hotkey *hotkey = acpi_driver_data(device);
1046
1047 ACPI_FUNCTION_TRACE("acpi_pcc_hotkey_remove");
1048
1049 if (!device || !hotkey)
1050 return_VALUE(-EINVAL);
1051
1052 if (hotkey->proc_dir_entry) {
1053 acpi_pcc_remove_device(device, acpi_pcc_proc_items_sifr,
1054 hotkey->num_sifr);
1055 acpi_pcc_remove_device(device, acpi_pcc_proc_items,
1056 ARRAY_SIZE(acpi_pcc_proc_items));
1057 remove_proc_entry(PROC_PCC, acpi_root_dir);
1058 }
1059
1060 status = acpi_remove_notify_handler(hotkey->handle,
1061 ACPI_DEVICE_NOTIFY, acpi_pcc_hotkey_notify);
1062
1063 if (ACPI_FAILURE(status)) {
1064 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
1065 "Error removing notify handler\n"));
1066 }
1067
1068 acpi_pcc_remove_input(hotkey);
1069 kfree(hotkey);
1070 return_VALUE(status == AE_OK);
1071}
1072
1073/* *********************************************************************
1074 Module entry point
1075 ********************************************************************* */
1076static int __init acpi_pcc_init(void)
1077{
1078 int result;
1079
1080 ACPI_FUNCTION_TRACE("acpi_pcc_init");
1081
1082 printk(KERN_INFO LOGPREFIX "loading...\n");
1083
1084 if (acpi_disabled) {
1085 printk(KERN_INFO LOGPREFIX "ACPI disabled.\n");
1086 return_VALUE(-ENODEV);
1087 }
1088
1089 result = acpi_bus_register_driver(&acpi_pcc_driver);
1090 if (result < 0) {
1091 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
1092 "Error registering hotkey driver\n"));
1093 return_VALUE(-ENODEV);
1094 }
1095
1096 return_VALUE(result);
1097}
1098
1099static void __exit acpi_pcc_exit(void)
1100{
1101 ACPI_FUNCTION_TRACE("acpi_pcc_exit");
1102
1103 printk(KERN_INFO LOGPREFIX "unloading...\n");
1104
1105 acpi_bus_unregister_driver(&acpi_pcc_driver);
1106
1107 return_VOID;
1108}
1109
1110module_init(acpi_pcc_init);
1111module_exit(acpi_pcc_exit);
diff --git a/drivers/staging/poch/Kconfig b/drivers/staging/poch/Kconfig
new file mode 100644
index 000000000000..b3b33b984a57
--- /dev/null
+++ b/drivers/staging/poch/Kconfig
@@ -0,0 +1,6 @@
1config POCH
2 tristate "Redrapids Pocket Change CardBus support"
3 depends on PCI && UIO
4 default N
5 ---help---
6 Enable support for Redrapids Pocket Change CardBus devices.
diff --git a/drivers/staging/poch/Makefile b/drivers/staging/poch/Makefile
new file mode 100644
index 000000000000..d2b96805cb9e
--- /dev/null
+++ b/drivers/staging/poch/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_POCH) += poch.o
diff --git a/drivers/staging/poch/README b/drivers/staging/poch/README
new file mode 100644
index 000000000000..f65e979743ba
--- /dev/null
+++ b/drivers/staging/poch/README
@@ -0,0 +1,7 @@
1TODO:
2 - fix transmit overflows
3 - audit userspace interfaces
4 - get reserved major/minor if needed
5
6Please send patches to Greg Kroah-Hartman <greg@kroah.com> and
7Vijay Kumar <vijaykumar@bravegnu.org> and Jaya Kumar <jayakumar.lkml@gmail.com>
diff --git a/drivers/staging/poch/poch.c b/drivers/staging/poch/poch.c
new file mode 100644
index 000000000000..0e113f9a1581
--- /dev/null
+++ b/drivers/staging/poch/poch.c
@@ -0,0 +1,1425 @@
1/*
2 * User-space DMA and UIO based Redrapids Pocket Change CardBus driver
3 *
4 * Copyright 2008 Vijay Kumar <vijaykumar@bravegnu.org>
5 *
6 * Licensed under GPL version 2 only.
7 */
8
9#include <linux/device.h>
10#include <linux/module.h>
11#include <linux/pci.h>
12#include <linux/uio_driver.h>
13#include <linux/spinlock.h>
14#include <linux/cdev.h>
15#include <linux/delay.h>
16#include <linux/sysfs.h>
17#include <linux/poll.h>
18#include <linux/idr.h>
19#include <linux/interrupt.h>
20#include <linux/init.h>
21#include <linux/ioctl.h>
22#include <linux/io.h>
23
24#include "poch.h"
25
26#include <asm/cacheflush.h>
27
28#ifndef PCI_VENDOR_ID_RRAPIDS
29#define PCI_VENDOR_ID_RRAPIDS 0x17D2
30#endif
31
32#ifndef PCI_DEVICE_ID_RRAPIDS_POCKET_CHANGE
33#define PCI_DEVICE_ID_RRAPIDS_POCKET_CHANGE 0x0351
34#endif
35
36#define POCH_NCHANNELS 2
37
38#define MAX_POCH_CARDS 8
39#define MAX_POCH_DEVICES (MAX_POCH_CARDS * POCH_NCHANNELS)
40
41#define DRV_NAME "poch"
42#define PFX DRV_NAME ": "
43
44/*
45 * BAR0 Bridge Register Definitions
46 */
47
48#define BRIDGE_REV_REG 0x0
49#define BRIDGE_INT_MASK_REG 0x4
50#define BRIDGE_INT_STAT_REG 0x8
51
52#define BRIDGE_INT_ACTIVE (0x1 << 31)
53#define BRIDGE_INT_FPGA (0x1 << 2)
54#define BRIDGE_INT_TEMP_FAIL (0x1 << 1)
55#define BRIDGE_INT_TEMP_WARN (0x1 << 0)
56
57#define BRIDGE_FPGA_RESET_REG 0xC
58
59#define BRIDGE_CARD_POWER_REG 0x10
60#define BRIDGE_CARD_POWER_EN (0x1 << 0)
61#define BRIDGE_CARD_POWER_PROG_DONE (0x1 << 31)
62
63#define BRIDGE_JTAG_REG 0x14
64#define BRIDGE_DMA_GO_REG 0x18
65#define BRIDGE_STAT_0_REG 0x1C
66#define BRIDGE_STAT_1_REG 0x20
67#define BRIDGE_STAT_2_REG 0x24
68#define BRIDGE_STAT_3_REG 0x28
69#define BRIDGE_TEMP_STAT_REG 0x2C
70#define BRIDGE_TEMP_THRESH_REG 0x30
71#define BRIDGE_EEPROM_REVSEL_REG 0x34
72#define BRIDGE_CIS_STRUCT_REG 0x100
73#define BRIDGE_BOARDREV_REG 0x124
74
75/*
76 * BAR1 FPGA Register Definitions
77 */
78
79#define FPGA_IFACE_REV_REG 0x0
80#define FPGA_RX_BLOCK_SIZE_REG 0x8
81#define FPGA_TX_BLOCK_SIZE_REG 0xC
82#define FPGA_RX_BLOCK_COUNT_REG 0x10
83#define FPGA_TX_BLOCK_COUNT_REG 0x14
84#define FPGA_RX_CURR_DMA_BLOCK_REG 0x18
85#define FPGA_TX_CURR_DMA_BLOCK_REG 0x1C
86#define FPGA_RX_GROUP_COUNT_REG 0x20
87#define FPGA_TX_GROUP_COUNT_REG 0x24
88#define FPGA_RX_CURR_GROUP_REG 0x28
89#define FPGA_TX_CURR_GROUP_REG 0x2C
90#define FPGA_RX_CURR_PCI_REG 0x38
91#define FPGA_TX_CURR_PCI_REG 0x3C
92#define FPGA_RX_GROUP0_START_REG 0x40
93#define FPGA_TX_GROUP0_START_REG 0xC0
94#define FPGA_DMA_DESC_1_REG 0x140
95#define FPGA_DMA_DESC_2_REG 0x144
96#define FPGA_DMA_DESC_3_REG 0x148
97#define FPGA_DMA_DESC_4_REG 0x14C
98
99#define FPGA_DMA_INT_STAT_REG 0x150
100#define FPGA_DMA_INT_MASK_REG 0x154
101#define FPGA_DMA_INT_RX (1 << 0)
102#define FPGA_DMA_INT_TX (1 << 1)
103
104#define FPGA_RX_GROUPS_PER_INT_REG 0x158
105#define FPGA_TX_GROUPS_PER_INT_REG 0x15C
106#define FPGA_DMA_ADR_PAGE_REG 0x160
107#define FPGA_FPGA_REV_REG 0x200
108
109#define FPGA_ADC_CLOCK_CTL_REG 0x204
110#define FPGA_ADC_CLOCK_CTL_OSC_EN (0x1 << 3)
111#define FPGA_ADC_CLOCK_LOCAL_CLK (0x1 | FPGA_ADC_CLOCK_CTL_OSC_EN)
112#define FPGA_ADC_CLOCK_EXT_SAMP_CLK 0X0
113
114#define FPGA_ADC_DAC_EN_REG 0x208
115#define FPGA_ADC_DAC_EN_DAC_OFF (0x1 << 1)
116#define FPGA_ADC_DAC_EN_ADC_OFF (0x1 << 0)
117
118#define FPGA_INT_STAT_REG 0x20C
119#define FPGA_INT_MASK_REG 0x210
120#define FPGA_INT_PLL_UNLOCKED (0x1 << 9)
121#define FPGA_INT_DMA_CORE (0x1 << 8)
122#define FPGA_INT_TX_FF_EMPTY (0x1 << 7)
123#define FPGA_INT_RX_FF_EMPTY (0x1 << 6)
124#define FPGA_INT_TX_FF_OVRFLW (0x1 << 3)
125#define FPGA_INT_RX_FF_OVRFLW (0x1 << 2)
126#define FPGA_INT_TX_ACQ_DONE (0x1 << 1)
127#define FPGA_INT_RX_ACQ_DONE (0x1)
128
129#define FPGA_RX_ADC_CTL_REG 0x214
130#define FPGA_RX_ADC_CTL_CONT_CAP (0x0)
131#define FPGA_RX_ADC_CTL_SNAP_CAP (0x1)
132
133#define FPGA_RX_ARM_REG 0x21C
134
135#define FPGA_DOM_REG 0x224
136#define FPGA_DOM_DCM_RESET (0x1 << 5)
137#define FPGA_DOM_SOFT_RESET (0x1 << 4)
138#define FPGA_DOM_DUAL_M_SG_DMA (0x0)
139#define FPGA_DOM_TARGET_ACCESS (0x1)
140
141#define FPGA_TX_CTL_REG 0x228
142#define FPGA_TX_CTL_FIFO_FLUSH (0x1 << 9)
143#define FPGA_TX_CTL_OUTPUT_ZERO (0x0 << 2)
144#define FPGA_TX_CTL_OUTPUT_CARDBUS (0x1 << 2)
145#define FPGA_TX_CTL_OUTPUT_ADC (0x2 << 2)
146#define FPGA_TX_CTL_OUTPUT_SNAPSHOT (0x3 << 2)
147#define FPGA_TX_CTL_LOOPBACK (0x1 << 0)
148
149#define FPGA_ENDIAN_MODE_REG 0x22C
150#define FPGA_RX_FIFO_COUNT_REG 0x28C
151#define FPGA_TX_ENABLE_REG 0x298
152#define FPGA_TX_TRIGGER_REG 0x29C
153#define FPGA_TX_DATAMEM_COUNT_REG 0x2A8
154#define FPGA_CAP_FIFO_REG 0x300
155#define FPGA_TX_SNAPSHOT_REG 0x8000
156
157/*
158 * Channel Index Definitions
159 */
160
161enum {
162 CHNO_RX_CHANNEL,
163 CHNO_TX_CHANNEL,
164};
165
166struct poch_dev;
167
168enum channel_dir {
169 CHANNEL_DIR_RX,
170 CHANNEL_DIR_TX,
171};
172
173struct poch_group_info {
174 struct page *pg;
175 dma_addr_t dma_addr;
176 unsigned long user_offset;
177};
178
179struct channel_info {
180 unsigned int chno;
181
182 atomic_t sys_block_size;
183 atomic_t sys_group_size;
184 atomic_t sys_group_count;
185
186 enum channel_dir dir;
187
188 unsigned long block_size;
189 unsigned long group_size;
190 unsigned long group_count;
191
192 /* Contains the DMA address and VM offset of each group. */
193 struct poch_group_info *groups;
194
195 /* Contains the header and circular buffer exported to userspace. */
196 spinlock_t group_offsets_lock;
197 struct poch_cbuf_header *header;
198 struct page *header_pg;
199 unsigned long header_size;
200
201 /* Last group indicated as 'complete' to user space. */
202 unsigned int transfer;
203
204 wait_queue_head_t wq;
205
206 union {
207 unsigned int data_available;
208 unsigned int space_available;
209 };
210
211 void __iomem *bridge_iomem;
212 void __iomem *fpga_iomem;
213 spinlock_t *iomem_lock;
214
215 atomic_t free;
216 atomic_t inited;
217
218 /* Error counters */
219 struct poch_counters counters;
220 spinlock_t counters_lock;
221
222 struct device *dev;
223};
224
225struct poch_dev {
226 struct uio_info uio;
227 struct pci_dev *pci_dev;
228 unsigned int nchannels;
229 struct channel_info channels[POCH_NCHANNELS];
230 struct cdev cdev;
231
232 /* Counts the no. of channels that have been opened. On first
233 * open, the card is powered on. On last channel close, the
234 * card is powered off.
235 */
236 atomic_t usage;
237
238 void __iomem *bridge_iomem;
239 void __iomem *fpga_iomem;
240 spinlock_t iomem_lock;
241
242 struct device *dev;
243};
244
245static dev_t poch_first_dev;
246static struct class *poch_cls;
247static DEFINE_IDR(poch_ids);
248
249static ssize_t store_block_size(struct device *dev,
250 struct device_attribute *attr,
251 const char *buf, size_t count)
252{
253 struct channel_info *channel = dev_get_drvdata(dev);
254 unsigned long block_size;
255
256 sscanf(buf, "%lu", &block_size);
257 atomic_set(&channel->sys_block_size, block_size);
258
259 return count;
260}
261static DEVICE_ATTR(block_size, S_IWUSR|S_IWGRP, NULL, store_block_size);
262
263static ssize_t store_group_size(struct device *dev,
264 struct device_attribute *attr,
265 const char *buf, size_t count)
266{
267 struct channel_info *channel = dev_get_drvdata(dev);
268 unsigned long group_size;
269
270 sscanf(buf, "%lu", &group_size);
271 atomic_set(&channel->sys_group_size, group_size);
272
273 return count;
274}
275static DEVICE_ATTR(group_size, S_IWUSR|S_IWGRP, NULL, store_group_size);
276
277static ssize_t store_group_count(struct device *dev,
278 struct device_attribute *attr,
279 const char *buf, size_t count)
280{
281 struct channel_info *channel = dev_get_drvdata(dev);
282 unsigned long group_count;
283
284 sscanf(buf, "%lu", &group_count);
285 atomic_set(&channel->sys_group_count, group_count);
286
287 return count;
288}
289static DEVICE_ATTR(group_count, S_IWUSR|S_IWGRP, NULL, store_group_count);
290
291static ssize_t show_direction(struct device *dev,
292 struct device_attribute *attr, char *buf)
293{
294 struct channel_info *channel = dev_get_drvdata(dev);
295 int len;
296
297 len = sprintf(buf, "%s\n", (channel->dir ? "tx" : "rx"));
298 return len;
299}
300static DEVICE_ATTR(dir, S_IRUSR|S_IRGRP, show_direction, NULL);
301
302static ssize_t show_mmap_size(struct device *dev,
303 struct device_attribute *attr, char *buf)
304{
305 struct channel_info *channel = dev_get_drvdata(dev);
306 int len;
307 unsigned long mmap_size;
308 unsigned long group_pages;
309 unsigned long header_pages;
310 unsigned long total_group_pages;
311
312 /* FIXME: We do not have to add 1, if group_size a multiple of
313 PAGE_SIZE. */
314 group_pages = (channel->group_size / PAGE_SIZE) + 1;
315 header_pages = (channel->header_size / PAGE_SIZE) + 1;
316 total_group_pages = group_pages * channel->group_count;
317
318 mmap_size = (header_pages + total_group_pages) * PAGE_SIZE;
319 len = sprintf(buf, "%lu\n", mmap_size);
320 return len;
321}
322static DEVICE_ATTR(mmap_size, S_IRUSR|S_IRGRP, show_mmap_size, NULL);
323
324static struct device_attribute *poch_class_attrs[] = {
325 &dev_attr_block_size,
326 &dev_attr_group_size,
327 &dev_attr_group_count,
328 &dev_attr_dir,
329 &dev_attr_mmap_size,
330};
331
332static void poch_channel_free_groups(struct channel_info *channel)
333{
334 unsigned long i;
335
336 for (i = 0; i < channel->group_count; i++) {
337 struct poch_group_info *group;
338 unsigned int order;
339
340 group = &channel->groups[i];
341 order = get_order(channel->group_size);
342 if (group->pg)
343 __free_pages(group->pg, order);
344 }
345}
346
347static int poch_channel_alloc_groups(struct channel_info *channel)
348{
349 unsigned long i;
350 unsigned long group_pages;
351 unsigned long header_pages;
352
353 group_pages = (channel->group_size / PAGE_SIZE) + 1;
354 header_pages = (channel->header_size / PAGE_SIZE) + 1;
355
356 for (i = 0; i < channel->group_count; i++) {
357 struct poch_group_info *group;
358 unsigned int order;
359 gfp_t gfp_mask;
360
361 group = &channel->groups[i];
362 order = get_order(channel->group_size);
363
364 /*
365 * __GFP_COMP is required here since we are going to
366 * perform non-linear mapping to userspace. For more
367 * information read the vm_insert_page() function
368 * comments.
369 */
370
371 gfp_mask = GFP_KERNEL | GFP_DMA32 | __GFP_ZERO;
372 group->pg = alloc_pages(gfp_mask, order);
373 if (!group->pg) {
374 poch_channel_free_groups(channel);
375 return -ENOMEM;
376 }
377
378 /* FIXME: This is the physical address not the bus
379 * address! This won't work in architectures that
380 * have an IOMMU. Can we use pci_map_single() for
381 * this?
382 */
383 group->dma_addr = page_to_pfn(group->pg) * PAGE_SIZE;
384 group->user_offset =
385 (header_pages + (i * group_pages)) * PAGE_SIZE;
386
387 printk(KERN_INFO PFX "%ld: user_offset: 0x%lx dma: 0x%x\n", i,
388 group->user_offset, group->dma_addr);
389 }
390
391 return 0;
392}
393
394static void channel_latch_attr(struct channel_info *channel)
395{
396 channel->group_count = atomic_read(&channel->sys_group_count);
397 channel->group_size = atomic_read(&channel->sys_group_size);
398 channel->block_size = atomic_read(&channel->sys_block_size);
399}
400
401/*
402 * Configure DMA group registers
403 */
404static void channel_dma_init(struct channel_info *channel)
405{
406 void __iomem *fpga = channel->fpga_iomem;
407 u32 group_regs_base;
408 u32 group_reg;
409 unsigned int page;
410 unsigned int group_in_page;
411 unsigned long i;
412 u32 block_size_reg;
413 u32 block_count_reg;
414 u32 group_count_reg;
415 u32 groups_per_int_reg;
416 u32 curr_pci_reg;
417
418 if (channel->chno == CHNO_RX_CHANNEL) {
419 group_regs_base = FPGA_RX_GROUP0_START_REG;
420 block_size_reg = FPGA_RX_BLOCK_SIZE_REG;
421 block_count_reg = FPGA_RX_BLOCK_COUNT_REG;
422 group_count_reg = FPGA_RX_GROUP_COUNT_REG;
423 groups_per_int_reg = FPGA_RX_GROUPS_PER_INT_REG;
424 curr_pci_reg = FPGA_RX_CURR_PCI_REG;
425 } else {
426 group_regs_base = FPGA_TX_GROUP0_START_REG;
427 block_size_reg = FPGA_TX_BLOCK_SIZE_REG;
428 block_count_reg = FPGA_TX_BLOCK_COUNT_REG;
429 group_count_reg = FPGA_TX_GROUP_COUNT_REG;
430 groups_per_int_reg = FPGA_TX_GROUPS_PER_INT_REG;
431 curr_pci_reg = FPGA_TX_CURR_PCI_REG;
432 }
433
434 printk(KERN_WARNING "block_size, group_size, group_count\n");
435 iowrite32(channel->block_size, fpga + block_size_reg);
436 iowrite32(channel->group_size / channel->block_size,
437 fpga + block_count_reg);
438 iowrite32(channel->group_count, fpga + group_count_reg);
439 /* FIXME: Hardcoded groups per int. Get it from sysfs? */
440 iowrite32(1, fpga + groups_per_int_reg);
441
442 /* Unlock PCI address? Not defined in the data sheet, but used
443 * in the reference code by Redrapids.
444 */
445 iowrite32(0x1, fpga + curr_pci_reg);
446
447 /* The DMA address page register is shared between the RX and
448 * TX channels, so acquire lock.
449 */
450 spin_lock(channel->iomem_lock);
451 for (i = 0; i < channel->group_count; i++) {
452 page = i / 32;
453 group_in_page = i % 32;
454
455 group_reg = group_regs_base + (group_in_page * 4);
456
457 iowrite32(page, fpga + FPGA_DMA_ADR_PAGE_REG);
458 iowrite32(channel->groups[i].dma_addr, fpga + group_reg);
459 }
460 for (i = 0; i < channel->group_count; i++) {
461 page = i / 32;
462 group_in_page = i % 32;
463
464 group_reg = group_regs_base + (group_in_page * 4);
465
466 iowrite32(page, fpga + FPGA_DMA_ADR_PAGE_REG);
467 printk(KERN_INFO PFX "%ld: read dma_addr: 0x%x\n", i,
468 ioread32(fpga + group_reg));
469 }
470 spin_unlock(channel->iomem_lock);
471
472}
473
474static int poch_channel_alloc_header(struct channel_info *channel)
475{
476 struct poch_cbuf_header *header = channel->header;
477 unsigned long group_offset_size;
478 unsigned long tot_group_offsets_size;
479
480 /* Allocate memory to hold header exported userspace */
481 group_offset_size = sizeof(header->group_offsets[0]);
482 tot_group_offsets_size = group_offset_size * channel->group_count;
483 channel->header_size = sizeof(*header) + tot_group_offsets_size;
484 channel->header_pg = alloc_pages(GFP_KERNEL | __GFP_ZERO,
485 get_order(channel->header_size));
486 if (!channel->header_pg)
487 return -ENOMEM;
488
489 channel->header = page_address(channel->header_pg);
490
491 return 0;
492}
493
494static void poch_channel_free_header(struct channel_info *channel)
495{
496 unsigned int order;
497
498 order = get_order(channel->header_size);
499 __free_pages(channel->header_pg, order);
500}
501
502static void poch_channel_init_header(struct channel_info *channel)
503{
504 int i;
505 struct poch_group_info *groups;
506 s32 *group_offsets;
507
508 channel->header->group_size_bytes = channel->group_size;
509 channel->header->group_count = channel->group_count;
510
511 spin_lock_init(&channel->group_offsets_lock);
512
513 group_offsets = channel->header->group_offsets;
514 groups = channel->groups;
515
516 for (i = 0; i < channel->group_count; i++) {
517 if (channel->dir == CHANNEL_DIR_RX)
518 group_offsets[i] = -1;
519 else
520 group_offsets[i] = groups[i].user_offset;
521 }
522}
523
524static void __poch_channel_clear_counters(struct channel_info *channel)
525{
526 channel->counters.pll_unlock = 0;
527 channel->counters.fifo_empty = 0;
528 channel->counters.fifo_overflow = 0;
529}
530
531static int poch_channel_init(struct channel_info *channel,
532 struct poch_dev *poch_dev)
533{
534 struct pci_dev *pdev = poch_dev->pci_dev;
535 struct device *dev = &pdev->dev;
536 unsigned long alloc_size;
537 int ret;
538
539 printk(KERN_WARNING "channel_latch_attr\n");
540
541 channel_latch_attr(channel);
542
543 channel->transfer = 0;
544
545 /* Allocate memory to hold group information. */
546 alloc_size = channel->group_count * sizeof(struct poch_group_info);
547 channel->groups = kzalloc(alloc_size, GFP_KERNEL);
548 if (!channel->groups) {
549 dev_err(dev, "error allocating memory for group info\n");
550 ret = -ENOMEM;
551 goto out;
552 }
553
554 printk(KERN_WARNING "poch_channel_alloc_groups\n");
555
556 ret = poch_channel_alloc_groups(channel);
557 if (ret) {
558 dev_err(dev, "error allocating groups of order %d\n",
559 get_order(channel->group_size));
560 goto out_free_group_info;
561 }
562
563 ret = poch_channel_alloc_header(channel);
564 if (ret) {
565 dev_err(dev, "error allocating user space header\n");
566 goto out_free_groups;
567 }
568
569 channel->fpga_iomem = poch_dev->fpga_iomem;
570 channel->bridge_iomem = poch_dev->bridge_iomem;
571 channel->iomem_lock = &poch_dev->iomem_lock;
572 spin_lock_init(&channel->counters_lock);
573
574 __poch_channel_clear_counters(channel);
575
576 printk(KERN_WARNING "poch_channel_init_header\n");
577
578 poch_channel_init_header(channel);
579
580 return 0;
581
582 out_free_groups:
583 poch_channel_free_groups(channel);
584 out_free_group_info:
585 kfree(channel->groups);
586 out:
587 return ret;
588}
589
590static int poch_wait_fpga_prog(void __iomem *bridge)
591{
592 unsigned long total_wait;
593 const unsigned long wait_period = 100;
594 /* FIXME: Get the actual timeout */
595 const unsigned long prog_timeo = 10000; /* 10 Seconds */
596 u32 card_power;
597
598 printk(KERN_WARNING "poch_wait_fpg_prog\n");
599
600 printk(KERN_INFO PFX "programming fpga ...\n");
601 total_wait = 0;
602 while (1) {
603 msleep(wait_period);
604 total_wait += wait_period;
605
606 card_power = ioread32(bridge + BRIDGE_CARD_POWER_REG);
607 if (card_power & BRIDGE_CARD_POWER_PROG_DONE) {
608 printk(KERN_INFO PFX "programming done\n");
609 return 0;
610 }
611 if (total_wait > prog_timeo) {
612 printk(KERN_ERR PFX
613 "timed out while programming FPGA\n");
614 return -EIO;
615 }
616 }
617}
618
619static void poch_card_power_off(struct poch_dev *poch_dev)
620{
621 void __iomem *bridge = poch_dev->bridge_iomem;
622 u32 card_power;
623
624 iowrite32(0, bridge + BRIDGE_INT_MASK_REG);
625 iowrite32(0, bridge + BRIDGE_DMA_GO_REG);
626
627 card_power = ioread32(bridge + BRIDGE_CARD_POWER_REG);
628 iowrite32(card_power & ~BRIDGE_CARD_POWER_EN,
629 bridge + BRIDGE_CARD_POWER_REG);
630}
631
632enum clk_src {
633 CLK_SRC_ON_BOARD,
634 CLK_SRC_EXTERNAL
635};
636
637static void poch_card_clock_on(void __iomem *fpga)
638{
639 /* FIXME: Get this data through sysfs? */
640 enum clk_src clk_src = CLK_SRC_ON_BOARD;
641
642 if (clk_src == CLK_SRC_ON_BOARD) {
643 iowrite32(FPGA_ADC_CLOCK_LOCAL_CLK | FPGA_ADC_CLOCK_CTL_OSC_EN,
644 fpga + FPGA_ADC_CLOCK_CTL_REG);
645 } else if (clk_src == CLK_SRC_EXTERNAL) {
646 iowrite32(FPGA_ADC_CLOCK_EXT_SAMP_CLK,
647 fpga + FPGA_ADC_CLOCK_CTL_REG);
648 }
649}
650
651static int poch_card_power_on(struct poch_dev *poch_dev)
652{
653 void __iomem *bridge = poch_dev->bridge_iomem;
654 void __iomem *fpga = poch_dev->fpga_iomem;
655
656 iowrite32(BRIDGE_CARD_POWER_EN, bridge + BRIDGE_CARD_POWER_REG);
657
658 if (poch_wait_fpga_prog(bridge) != 0) {
659 poch_card_power_off(poch_dev);
660 return -EIO;
661 }
662
663 poch_card_clock_on(fpga);
664
665 /* Sync to new clock, reset state machines, set DMA mode. */
666 iowrite32(FPGA_DOM_DCM_RESET | FPGA_DOM_SOFT_RESET
667 | FPGA_DOM_DUAL_M_SG_DMA, fpga + FPGA_DOM_REG);
668
669 /* FIXME: The time required for sync. needs to be tuned. */
670 msleep(1000);
671
672 return 0;
673}
674
675static void poch_channel_analog_on(struct channel_info *channel)
676{
677 void __iomem *fpga = channel->fpga_iomem;
678 u32 adc_dac_en;
679
680 spin_lock(channel->iomem_lock);
681 adc_dac_en = ioread32(fpga + FPGA_ADC_DAC_EN_REG);
682 switch (channel->chno) {
683 case CHNO_RX_CHANNEL:
684 iowrite32(adc_dac_en & ~FPGA_ADC_DAC_EN_ADC_OFF,
685 fpga + FPGA_ADC_DAC_EN_REG);
686 break;
687 case CHNO_TX_CHANNEL:
688 iowrite32(adc_dac_en & ~FPGA_ADC_DAC_EN_DAC_OFF,
689 fpga + FPGA_ADC_DAC_EN_REG);
690 break;
691 }
692 spin_unlock(channel->iomem_lock);
693}
694
695static int poch_open(struct inode *inode, struct file *filp)
696{
697 struct poch_dev *poch_dev;
698 struct channel_info *channel;
699 void __iomem *bridge;
700 void __iomem *fpga;
701 int chno;
702 int usage;
703 int ret;
704
705 poch_dev = container_of(inode->i_cdev, struct poch_dev, cdev);
706 bridge = poch_dev->bridge_iomem;
707 fpga = poch_dev->fpga_iomem;
708
709 chno = iminor(inode) % poch_dev->nchannels;
710 channel = &poch_dev->channels[chno];
711
712 if (!atomic_dec_and_test(&channel->free)) {
713 atomic_inc(&channel->free);
714 ret = -EBUSY;
715 goto out;
716 }
717
718 usage = atomic_inc_return(&poch_dev->usage);
719
720 printk(KERN_WARNING "poch_card_power_on\n");
721
722 if (usage == 1) {
723 ret = poch_card_power_on(poch_dev);
724 if (ret)
725 goto out_dec_usage;
726 }
727
728 printk(KERN_INFO "CardBus Bridge Revision: %x\n",
729 ioread32(bridge + BRIDGE_REV_REG));
730 printk(KERN_INFO "CardBus Interface Revision: %x\n",
731 ioread32(fpga + FPGA_IFACE_REV_REG));
732
733 channel->chno = chno;
734 filp->private_data = channel;
735
736 printk(KERN_WARNING "poch_channel_init\n");
737
738 ret = poch_channel_init(channel, poch_dev);
739 if (ret)
740 goto out_power_off;
741
742 poch_channel_analog_on(channel);
743
744 printk(KERN_WARNING "channel_dma_init\n");
745
746 channel_dma_init(channel);
747
748 printk(KERN_WARNING "poch_channel_analog_on\n");
749
750 if (usage == 1) {
751 printk(KERN_WARNING "setting up DMA\n");
752
753 /* Initialize DMA Controller. */
754 iowrite32(FPGA_CAP_FIFO_REG, bridge + BRIDGE_STAT_2_REG);
755 iowrite32(FPGA_DMA_DESC_1_REG, bridge + BRIDGE_STAT_3_REG);
756
757 ioread32(fpga + FPGA_DMA_INT_STAT_REG);
758 ioread32(fpga + FPGA_INT_STAT_REG);
759 ioread32(bridge + BRIDGE_INT_STAT_REG);
760
761 /* Initialize Interrupts. FIXME: Enable temperature
762 * handling We are enabling both Tx and Rx channel
763 * interrupts here. Do we need to enable interrupts
764 * only for the current channel? Anyways we won't get
765 * the interrupt unless the DMA is activated.
766 */
767 iowrite32(BRIDGE_INT_FPGA, bridge + BRIDGE_INT_MASK_REG);
768 iowrite32(FPGA_INT_DMA_CORE
769 | FPGA_INT_PLL_UNLOCKED
770 | FPGA_INT_TX_FF_EMPTY
771 | FPGA_INT_RX_FF_EMPTY
772 | FPGA_INT_TX_FF_OVRFLW
773 | FPGA_INT_RX_FF_OVRFLW,
774 fpga + FPGA_INT_MASK_REG);
775 iowrite32(FPGA_DMA_INT_RX | FPGA_DMA_INT_TX,
776 fpga + FPGA_DMA_INT_MASK_REG);
777 }
778
779 if (channel->dir == CHANNEL_DIR_TX) {
780 /* Flush TX FIFO and output data from cardbus. */
781 iowrite32(FPGA_TX_CTL_FIFO_FLUSH
782 | FPGA_TX_CTL_OUTPUT_CARDBUS,
783 fpga + FPGA_TX_CTL_REG);
784 }
785
786 atomic_inc(&channel->inited);
787
788 return 0;
789
790 out_power_off:
791 if (usage == 1)
792 poch_card_power_off(poch_dev);
793 out_dec_usage:
794 atomic_dec(&poch_dev->usage);
795 atomic_inc(&channel->free);
796 out:
797 return ret;
798}
799
800static int poch_release(struct inode *inode, struct file *filp)
801{
802 struct channel_info *channel = filp->private_data;
803 struct poch_dev *poch_dev;
804 int usage;
805
806 poch_dev = container_of(inode->i_cdev, struct poch_dev, cdev);
807
808 usage = atomic_dec_return(&poch_dev->usage);
809 if (usage == 0) {
810 printk(KERN_WARNING "poch_card_power_off\n");
811 poch_card_power_off(poch_dev);
812 }
813
814 atomic_dec(&channel->inited);
815 poch_channel_free_header(channel);
816 poch_channel_free_groups(channel);
817 kfree(channel->groups);
818 atomic_inc(&channel->free);
819
820 return 0;
821}
822
823/*
824 * Map the header and the group buffers, to user space.
825 */
826static int poch_mmap(struct file *filp, struct vm_area_struct *vma)
827{
828 struct channel_info *channel = filp->private_data;
829
830 unsigned long start;
831 unsigned long size;
832
833 unsigned long group_pages;
834 unsigned long header_pages;
835 unsigned long total_group_pages;
836
837 int pg_num;
838 struct page *pg;
839
840 int i;
841 int ret;
842
843 printk(KERN_WARNING "poch_mmap\n");
844
845 if (vma->vm_pgoff) {
846 printk(KERN_WARNING PFX "page offset: %lu\n", vma->vm_pgoff);
847 return -EINVAL;
848 }
849
850 group_pages = (channel->group_size / PAGE_SIZE) + 1;
851 header_pages = (channel->header_size / PAGE_SIZE) + 1;
852 total_group_pages = group_pages * channel->group_count;
853
854 size = vma->vm_end - vma->vm_start;
855 if (size != (header_pages + total_group_pages) * PAGE_SIZE) {
856 printk(KERN_WARNING PFX "required %lu bytes\n", size);
857 return -EINVAL;
858 }
859
860 start = vma->vm_start;
861
862 /* FIXME: Cleanup required on failure? */
863 pg = channel->header_pg;
864 for (pg_num = 0; pg_num < header_pages; pg_num++, pg++) {
865 printk(KERN_DEBUG PFX "page_count: %d\n", page_count(pg));
866 printk(KERN_DEBUG PFX "%d: header: 0x%lx\n", pg_num, start);
867 ret = vm_insert_page(vma, start, pg);
868 if (ret) {
869 printk(KERN_DEBUG "vm_insert 1 failed at %lx\n", start);
870 return ret;
871 }
872 start += PAGE_SIZE;
873 }
874
875 for (i = 0; i < channel->group_count; i++) {
876 pg = channel->groups[i].pg;
877 for (pg_num = 0; pg_num < group_pages; pg_num++, pg++) {
878 printk(KERN_DEBUG PFX "%d: group %d: 0x%lx\n",
879 pg_num, i, start);
880 ret = vm_insert_page(vma, start, pg);
881 if (ret) {
882 printk(KERN_DEBUG PFX
883 "vm_insert 2 failed at %d\n", pg_num);
884 return ret;
885 }
886 start += PAGE_SIZE;
887 }
888 }
889
890 return 0;
891}
892
893/*
894 * Check whether there is some group that the user space has not
895 * consumed yet. When the user space consumes a group, it sets it to
896 * -1. Cosuming could be reading data in case of RX and filling a
897 * buffer in case of TX.
898 */
899static int poch_channel_available(struct channel_info *channel)
900{
901 int i;
902
903 spin_lock_irq(&channel->group_offsets_lock);
904
905 for (i = 0; i < channel->group_count; i++) {
906 if (channel->dir == CHANNEL_DIR_RX
907 && channel->header->group_offsets[i] == -1) {
908 spin_unlock_irq(&channel->group_offsets_lock);
909 return 1;
910 }
911
912 if (channel->dir == CHANNEL_DIR_TX
913 && channel->header->group_offsets[i] != -1) {
914 spin_unlock_irq(&channel->group_offsets_lock);
915 return 1;
916 }
917 }
918
919 spin_unlock_irq(&channel->group_offsets_lock);
920
921 return 0;
922}
923
924static unsigned int poch_poll(struct file *filp, poll_table *pt)
925{
926 struct channel_info *channel = filp->private_data;
927 unsigned int ret = 0;
928
929 poll_wait(filp, &channel->wq, pt);
930
931 if (poch_channel_available(channel)) {
932 if (channel->dir == CHANNEL_DIR_RX)
933 ret = POLLIN | POLLRDNORM;
934 else
935 ret = POLLOUT | POLLWRNORM;
936 }
937
938 return ret;
939}
940
941static int poch_ioctl(struct inode *inode, struct file *filp,
942 unsigned int cmd, unsigned long arg)
943{
944 struct channel_info *channel = filp->private_data;
945 void __iomem *fpga = channel->fpga_iomem;
946 void __iomem *bridge = channel->bridge_iomem;
947 void __user *argp = (void __user *)arg;
948 struct vm_area_struct *vms;
949 struct poch_counters counters;
950 int ret;
951
952 switch (cmd) {
953 case POCH_IOC_TRANSFER_START:
954 switch (channel->chno) {
955 case CHNO_TX_CHANNEL:
956 printk(KERN_INFO PFX "ioctl: Tx start\n");
957 iowrite32(0x1, fpga + FPGA_TX_TRIGGER_REG);
958 iowrite32(0x1, fpga + FPGA_TX_ENABLE_REG);
959
960 /* FIXME: Does it make sense to do a DMA GO
961 * twice, once in Tx and once in Rx.
962 */
963 iowrite32(0x1, bridge + BRIDGE_DMA_GO_REG);
964 break;
965 case CHNO_RX_CHANNEL:
966 printk(KERN_INFO PFX "ioctl: Rx start\n");
967 iowrite32(0x1, fpga + FPGA_RX_ARM_REG);
968 iowrite32(0x1, bridge + BRIDGE_DMA_GO_REG);
969 break;
970 }
971 break;
972 case POCH_IOC_TRANSFER_STOP:
973 switch (channel->chno) {
974 case CHNO_TX_CHANNEL:
975 printk(KERN_INFO PFX "ioctl: Tx stop\n");
976 iowrite32(0x0, fpga + FPGA_TX_ENABLE_REG);
977 iowrite32(0x0, fpga + FPGA_TX_TRIGGER_REG);
978 iowrite32(0x0, bridge + BRIDGE_DMA_GO_REG);
979 break;
980 case CHNO_RX_CHANNEL:
981 printk(KERN_INFO PFX "ioctl: Rx stop\n");
982 iowrite32(0x0, fpga + FPGA_RX_ARM_REG);
983 iowrite32(0x0, bridge + BRIDGE_DMA_GO_REG);
984 break;
985 }
986 break;
987 case POCH_IOC_GET_COUNTERS:
988 if (access_ok(VERIFY_WRITE, argp, sizeof(struct poch_counters)))
989 return -EFAULT;
990
991 spin_lock_irq(&channel->counters_lock);
992 counters = channel->counters;
993 __poch_channel_clear_counters(channel);
994 spin_unlock_irq(&channel->counters_lock);
995
996 ret = copy_to_user(argp, &counters,
997 sizeof(struct poch_counters));
998 if (ret)
999 return ret;
1000
1001 break;
1002 case POCH_IOC_SYNC_GROUP_FOR_USER:
1003 case POCH_IOC_SYNC_GROUP_FOR_DEVICE:
1004 vms = find_vma(current->mm, arg);
1005 if (!vms)
1006 /* Address not mapped. */
1007 return -EINVAL;
1008 if (vms->vm_file != filp)
1009 /* Address mapped from different device/file. */
1010 return -EINVAL;
1011
1012 flush_cache_range(vms, arg, arg + channel->group_size);
1013 break;
1014 }
1015 return 0;
1016}
1017
1018static struct file_operations poch_fops = {
1019 .owner = THIS_MODULE,
1020 .open = poch_open,
1021 .release = poch_release,
1022 .ioctl = poch_ioctl,
1023 .poll = poch_poll,
1024 .mmap = poch_mmap
1025};
1026
1027static void poch_irq_dma(struct channel_info *channel)
1028{
1029 u32 prev_transfer;
1030 u32 curr_transfer;
1031 long groups_done;
1032 unsigned long i, j;
1033 struct poch_group_info *groups;
1034 s32 *group_offsets;
1035 u32 curr_group_reg;
1036
1037 if (!atomic_read(&channel->inited))
1038 return;
1039
1040 prev_transfer = channel->transfer;
1041
1042 if (channel->chno == CHNO_RX_CHANNEL)
1043 curr_group_reg = FPGA_RX_CURR_GROUP_REG;
1044 else
1045 curr_group_reg = FPGA_TX_CURR_GROUP_REG;
1046
1047 curr_transfer = ioread32(channel->fpga_iomem + curr_group_reg);
1048
1049 groups_done = curr_transfer - prev_transfer;
1050 /* Check wrap over, and handle it. */
1051 if (groups_done <= 0)
1052 groups_done += channel->group_count;
1053
1054 group_offsets = channel->header->group_offsets;
1055 groups = channel->groups;
1056
1057 spin_lock(&channel->group_offsets_lock);
1058
1059 for (i = 0; i < groups_done; i++) {
1060 j = (prev_transfer + i) % channel->group_count;
1061 if (channel->dir == CHANNEL_DIR_RX)
1062 group_offsets[j] = -1;
1063 else
1064 group_offsets[j] = groups[j].user_offset;
1065 }
1066
1067 spin_unlock(&channel->group_offsets_lock);
1068
1069 channel->transfer = curr_transfer;
1070
1071 wake_up_interruptible(&channel->wq);
1072}
1073
1074static irqreturn_t poch_irq_handler(int irq, void *p)
1075{
1076 struct poch_dev *poch_dev = p;
1077 void __iomem *bridge = poch_dev->bridge_iomem;
1078 void __iomem *fpga = poch_dev->fpga_iomem;
1079 struct channel_info *channel_rx = &poch_dev->channels[CHNO_RX_CHANNEL];
1080 struct channel_info *channel_tx = &poch_dev->channels[CHNO_TX_CHANNEL];
1081 u32 bridge_stat;
1082 u32 fpga_stat;
1083 u32 dma_stat;
1084
1085 bridge_stat = ioread32(bridge + BRIDGE_INT_STAT_REG);
1086 fpga_stat = ioread32(fpga + FPGA_INT_STAT_REG);
1087 dma_stat = ioread32(fpga + FPGA_DMA_INT_STAT_REG);
1088
1089 ioread32(fpga + FPGA_DMA_INT_STAT_REG);
1090 ioread32(fpga + FPGA_INT_STAT_REG);
1091 ioread32(bridge + BRIDGE_INT_STAT_REG);
1092
1093 if (bridge_stat & BRIDGE_INT_FPGA) {
1094 if (fpga_stat & FPGA_INT_DMA_CORE) {
1095 if (dma_stat & FPGA_DMA_INT_RX)
1096 poch_irq_dma(channel_rx);
1097 if (dma_stat & FPGA_DMA_INT_TX)
1098 poch_irq_dma(channel_tx);
1099 }
1100 if (fpga_stat & FPGA_INT_PLL_UNLOCKED) {
1101 channel_tx->counters.pll_unlock++;
1102 channel_rx->counters.pll_unlock++;
1103 if (printk_ratelimit())
1104 printk(KERN_WARNING PFX "PLL unlocked\n");
1105 }
1106 if (fpga_stat & FPGA_INT_TX_FF_EMPTY)
1107 channel_tx->counters.fifo_empty++;
1108 if (fpga_stat & FPGA_INT_TX_FF_OVRFLW)
1109 channel_tx->counters.fifo_overflow++;
1110 if (fpga_stat & FPGA_INT_RX_FF_EMPTY)
1111 channel_rx->counters.fifo_empty++;
1112 if (fpga_stat & FPGA_INT_RX_FF_OVRFLW)
1113 channel_rx->counters.fifo_overflow++;
1114
1115 /*
1116 * FIXME: These errors should be notified through the
1117 * poll interface as POLLERR.
1118 */
1119
1120 /* Re-enable interrupts. */
1121 iowrite32(BRIDGE_INT_FPGA, bridge + BRIDGE_INT_MASK_REG);
1122
1123 return IRQ_HANDLED;
1124 }
1125
1126 return IRQ_NONE;
1127}
1128
1129static void poch_class_dev_unregister(struct poch_dev *poch_dev, int id)
1130{
1131 int i, j;
1132 int nattrs;
1133 struct channel_info *channel;
1134 dev_t devno;
1135
1136 if (poch_dev->dev == NULL)
1137 return;
1138
1139 for (i = 0; i < poch_dev->nchannels; i++) {
1140 channel = &poch_dev->channels[i];
1141 devno = poch_first_dev + (id * poch_dev->nchannels) + i;
1142
1143 if (!channel->dev)
1144 continue;
1145
1146 nattrs = sizeof(poch_class_attrs)/sizeof(poch_class_attrs[0]);
1147 for (j = 0; j < nattrs; j++)
1148 device_remove_file(channel->dev, poch_class_attrs[j]);
1149
1150 device_unregister(channel->dev);
1151 }
1152
1153 device_unregister(poch_dev->dev);
1154}
1155
1156static int __devinit poch_class_dev_register(struct poch_dev *poch_dev,
1157 int id)
1158{
1159 struct device *dev = &poch_dev->pci_dev->dev;
1160 int i, j;
1161 int nattrs;
1162 int ret;
1163 struct channel_info *channel;
1164 dev_t devno;
1165
1166 poch_dev->dev = device_create(poch_cls, &poch_dev->pci_dev->dev,
1167 MKDEV(0, 0), NULL, "poch%d", id);
1168 if (IS_ERR(poch_dev->dev)) {
1169 dev_err(dev, "error creating parent class device");
1170 ret = PTR_ERR(poch_dev->dev);
1171 poch_dev->dev = NULL;
1172 return ret;
1173 }
1174
1175 for (i = 0; i < poch_dev->nchannels; i++) {
1176 channel = &poch_dev->channels[i];
1177
1178 devno = poch_first_dev + (id * poch_dev->nchannels) + i;
1179 channel->dev = device_create(poch_cls, poch_dev->dev, devno,
1180 NULL, "ch%d", i);
1181 if (IS_ERR(channel->dev)) {
1182 dev_err(dev, "error creating channel class device");
1183 ret = PTR_ERR(channel->dev);
1184 channel->dev = NULL;
1185 poch_class_dev_unregister(poch_dev, id);
1186 return ret;
1187 }
1188
1189 dev_set_drvdata(channel->dev, channel);
1190 nattrs = sizeof(poch_class_attrs)/sizeof(poch_class_attrs[0]);
1191 for (j = 0; j < nattrs; j++) {
1192 ret = device_create_file(channel->dev,
1193 poch_class_attrs[j]);
1194 if (ret) {
1195 dev_err(dev, "error creating attribute file");
1196 poch_class_dev_unregister(poch_dev, id);
1197 return ret;
1198 }
1199 }
1200 }
1201
1202 return 0;
1203}
1204
1205static int __devinit poch_pci_probe(struct pci_dev *pdev,
1206 const struct pci_device_id *pci_id)
1207{
1208 struct device *dev = &pdev->dev;
1209 struct poch_dev *poch_dev;
1210 struct uio_info *uio;
1211 int ret;
1212 int id;
1213 int i;
1214
1215 poch_dev = kzalloc(sizeof(struct poch_dev), GFP_KERNEL);
1216 if (!poch_dev) {
1217 dev_err(dev, "error allocating priv. data memory\n");
1218 return -ENOMEM;
1219 }
1220
1221 poch_dev->pci_dev = pdev;
1222 uio = &poch_dev->uio;
1223
1224 pci_set_drvdata(pdev, poch_dev);
1225
1226 spin_lock_init(&poch_dev->iomem_lock);
1227
1228 poch_dev->nchannels = POCH_NCHANNELS;
1229 poch_dev->channels[CHNO_RX_CHANNEL].dir = CHANNEL_DIR_RX;
1230 poch_dev->channels[CHNO_TX_CHANNEL].dir = CHANNEL_DIR_TX;
1231
1232 for (i = 0; i < poch_dev->nchannels; i++) {
1233 init_waitqueue_head(&poch_dev->channels[i].wq);
1234 atomic_set(&poch_dev->channels[i].free, 1);
1235 atomic_set(&poch_dev->channels[i].inited, 0);
1236 }
1237
1238 ret = pci_enable_device(pdev);
1239 if (ret) {
1240 dev_err(dev, "error enabling device\n");
1241 goto out_free;
1242 }
1243
1244 ret = pci_request_regions(pdev, "poch");
1245 if (ret) {
1246 dev_err(dev, "error requesting resources\n");
1247 goto out_disable;
1248 }
1249
1250 uio->mem[0].addr = pci_resource_start(pdev, 1);
1251 if (!uio->mem[0].addr) {
1252 dev_err(dev, "invalid BAR1\n");
1253 ret = -ENODEV;
1254 goto out_release;
1255 }
1256
1257 uio->mem[0].size = pci_resource_len(pdev, 1);
1258 uio->mem[0].memtype = UIO_MEM_PHYS;
1259
1260 uio->name = "poch";
1261 uio->version = "0.0.1";
1262 uio->irq = -1;
1263 ret = uio_register_device(dev, uio);
1264 if (ret) {
1265 dev_err(dev, "error register UIO device: %d\n", ret);
1266 goto out_release;
1267 }
1268
1269 poch_dev->bridge_iomem = ioremap(pci_resource_start(pdev, 0),
1270 pci_resource_len(pdev, 0));
1271 if (poch_dev->bridge_iomem == NULL) {
1272 dev_err(dev, "error mapping bridge (bar0) registers\n");
1273 ret = -ENOMEM;
1274 goto out_uio_unreg;
1275 }
1276
1277 poch_dev->fpga_iomem = ioremap(pci_resource_start(pdev, 1),
1278 pci_resource_len(pdev, 1));
1279 if (poch_dev->fpga_iomem == NULL) {
1280 dev_err(dev, "error mapping fpga (bar1) registers\n");
1281 ret = -ENOMEM;
1282 goto out_bar0_unmap;
1283 }
1284
1285 ret = request_irq(pdev->irq, poch_irq_handler, IRQF_SHARED,
1286 dev->bus_id, poch_dev);
1287 if (ret) {
1288 dev_err(dev, "error requesting IRQ %u\n", pdev->irq);
1289 ret = -ENOMEM;
1290 goto out_bar1_unmap;
1291 }
1292
1293 if (!idr_pre_get(&poch_ids, GFP_KERNEL)) {
1294 dev_err(dev, "error allocating memory ids\n");
1295 ret = -ENOMEM;
1296 goto out_free_irq;
1297 }
1298
1299 idr_get_new(&poch_ids, poch_dev, &id);
1300 if (id >= MAX_POCH_CARDS) {
1301 dev_err(dev, "minors exhausted\n");
1302 ret = -EBUSY;
1303 goto out_free_irq;
1304 }
1305
1306 cdev_init(&poch_dev->cdev, &poch_fops);
1307 poch_dev->cdev.owner = THIS_MODULE;
1308 ret = cdev_add(&poch_dev->cdev,
1309 poch_first_dev + (id * poch_dev->nchannels),
1310 poch_dev->nchannels);
1311 if (ret) {
1312 dev_err(dev, "error register character device\n");
1313 goto out_idr_remove;
1314 }
1315
1316 ret = poch_class_dev_register(poch_dev, id);
1317 if (ret)
1318 goto out_cdev_del;
1319
1320 return 0;
1321
1322 out_cdev_del:
1323 cdev_del(&poch_dev->cdev);
1324 out_idr_remove:
1325 idr_remove(&poch_ids, id);
1326 out_free_irq:
1327 free_irq(pdev->irq, poch_dev);
1328 out_bar1_unmap:
1329 iounmap(poch_dev->fpga_iomem);
1330 out_bar0_unmap:
1331 iounmap(poch_dev->bridge_iomem);
1332 out_uio_unreg:
1333 uio_unregister_device(uio);
1334 out_release:
1335 pci_release_regions(pdev);
1336 out_disable:
1337 pci_disable_device(pdev);
1338 out_free:
1339 kfree(poch_dev);
1340 return ret;
1341}
1342
1343/*
1344 * FIXME: We are yet to handle the hot unplug case.
1345 */
1346static void poch_pci_remove(struct pci_dev *pdev)
1347{
1348 struct poch_dev *poch_dev = pci_get_drvdata(pdev);
1349 struct uio_info *uio = &poch_dev->uio;
1350 unsigned int minor = MINOR(poch_dev->cdev.dev);
1351 unsigned int id = minor / poch_dev->nchannels;
1352
1353 /* FIXME: unmap fpga_iomem and bridge_iomem */
1354
1355 poch_class_dev_unregister(poch_dev, id);
1356 cdev_del(&poch_dev->cdev);
1357 idr_remove(&poch_ids, id);
1358 free_irq(pdev->irq, poch_dev);
1359 uio_unregister_device(uio);
1360 pci_release_regions(pdev);
1361 pci_disable_device(pdev);
1362 pci_set_drvdata(pdev, NULL);
1363 iounmap(uio->mem[0].internal_addr);
1364
1365 kfree(poch_dev);
1366}
1367
1368static const struct pci_device_id poch_pci_ids[] /* __devinitconst */ = {
1369 { PCI_DEVICE(PCI_VENDOR_ID_RRAPIDS,
1370 PCI_DEVICE_ID_RRAPIDS_POCKET_CHANGE) },
1371 { 0, }
1372};
1373
1374static struct pci_driver poch_pci_driver = {
1375 .name = DRV_NAME,
1376 .id_table = poch_pci_ids,
1377 .probe = poch_pci_probe,
1378 .remove = poch_pci_remove,
1379};
1380
1381static int __init poch_init_module(void)
1382{
1383 int ret = 0;
1384
1385 ret = alloc_chrdev_region(&poch_first_dev, 0,
1386 MAX_POCH_DEVICES, DRV_NAME);
1387 if (ret) {
1388 printk(KERN_ERR PFX "error allocating device no.");
1389 return ret;
1390 }
1391
1392 poch_cls = class_create(THIS_MODULE, "pocketchange");
1393 if (IS_ERR(poch_cls)) {
1394 ret = PTR_ERR(poch_cls);
1395 goto out_unreg_chrdev;
1396 }
1397
1398 ret = pci_register_driver(&poch_pci_driver);
1399 if (ret) {
1400 printk(KERN_ERR PFX "error register PCI device");
1401 goto out_class_destroy;
1402 }
1403
1404 return 0;
1405
1406 out_class_destroy:
1407 class_destroy(poch_cls);
1408
1409 out_unreg_chrdev:
1410 unregister_chrdev_region(poch_first_dev, MAX_POCH_DEVICES);
1411
1412 return ret;
1413}
1414
1415static void __exit poch_exit_module(void)
1416{
1417 pci_unregister_driver(&poch_pci_driver);
1418 class_destroy(poch_cls);
1419 unregister_chrdev_region(poch_first_dev, MAX_POCH_DEVICES);
1420}
1421
1422module_init(poch_init_module);
1423module_exit(poch_exit_module);
1424
1425MODULE_LICENSE("GPL v2");
diff --git a/drivers/staging/poch/poch.h b/drivers/staging/poch/poch.h
new file mode 100644
index 000000000000..51a2d145798e
--- /dev/null
+++ b/drivers/staging/poch/poch.h
@@ -0,0 +1,29 @@
1/*
2 * User-space DMA and UIO based Redrapids Pocket Change CardBus driver
3 *
4 * Copyright 2008 Vijay Kumar <vijaykumar@bravegnu.org>
5 *
6 * Part of userspace API. Should be moved to a header file in
7 * include/linux for final version.
8 *
9 */
10struct poch_cbuf_header {
11 __s32 group_size_bytes;
12 __s32 group_count;
13 __s32 group_offsets[0];
14};
15
16struct poch_counters {
17 __u32 fifo_empty;
18 __u32 fifo_overflow;
19 __u32 pll_unlock;
20};
21
22#define POCH_IOC_NUM '9'
23
24#define POCH_IOC_TRANSFER_START _IO(POCH_IOC_NUM, 0)
25#define POCH_IOC_TRANSFER_STOP _IO(POCH_IOC_NUM, 1)
26#define POCH_IOC_GET_COUNTERS _IOR(POCH_IOC_NUM, 2, \
27 struct poch_counters)
28#define POCH_IOC_SYNC_GROUP_FOR_USER _IO(POCH_IOC_NUM, 3)
29#define POCH_IOC_SYNC_GROUP_FOR_DEVICE _IO(POCH_IOC_NUM, 4)
diff --git a/drivers/staging/slicoss/slicoss.c b/drivers/staging/slicoss/slicoss.c
index b61ac4b2db9e..8fa9490b3e2c 100644
--- a/drivers/staging/slicoss/slicoss.c
+++ b/drivers/staging/slicoss/slicoss.c
@@ -54,7 +54,6 @@
54 * IS-NIC driver. 54 * IS-NIC driver.
55 */ 55 */
56 56
57#include <linux/version.h>
58 57
59#define SLIC_DUMP_ENABLED 0 58#define SLIC_DUMP_ENABLED 0
60#define KLUDGE_FOR_4GB_BOUNDARY 1 59#define KLUDGE_FOR_4GB_BOUNDARY 1
@@ -96,17 +95,9 @@
96#include <linux/moduleparam.h> 95#include <linux/moduleparam.h>
97 96
98#include <linux/types.h> 97#include <linux/types.h>
99#include <linux/slab.h>
100#include <linux/delay.h>
101#include <linux/init.h>
102#include <linux/pci.h>
103#include <linux/dma-mapping.h> 98#include <linux/dma-mapping.h>
104#include <linux/netdevice.h>
105#include <linux/etherdevice.h>
106#include <linux/mii.h> 99#include <linux/mii.h>
107#include <linux/if_vlan.h> 100#include <linux/if_vlan.h>
108#include <linux/skbuff.h>
109#include <linux/string.h>
110#include <asm/unaligned.h> 101#include <asm/unaligned.h>
111 102
112#include <linux/ethtool.h> 103#include <linux/ethtool.h>
@@ -275,7 +266,6 @@ static void slic_dbg_register_trace(struct adapter *adapter,
275 card->reg_value[i], card->reg_valueh[i]); 266 card->reg_value[i], card->reg_valueh[i]);
276 } 267 }
277} 268}
278}
279#endif 269#endif
280 270
281static void slic_init_adapter(struct net_device *netdev, 271static void slic_init_adapter(struct net_device *netdev,
@@ -606,6 +596,7 @@ static void __devexit slic_entry_remove(struct pci_dev *pcidev)
606 uint mmio_len = 0; 596 uint mmio_len = 0;
607 struct adapter *adapter = (struct adapter *) netdev_priv(dev); 597 struct adapter *adapter = (struct adapter *) netdev_priv(dev);
608 struct sliccard *card; 598 struct sliccard *card;
599 struct mcast_address *mcaddr, *mlist;
609 600
610 ASSERT(adapter); 601 ASSERT(adapter);
611 DBG_MSG("slicoss: %s ENTER dev[%p] adapter[%p]\n", __func__, dev, 602 DBG_MSG("slicoss: %s ENTER dev[%p] adapter[%p]\n", __func__, dev,
@@ -625,6 +616,13 @@ static void __devexit slic_entry_remove(struct pci_dev *pcidev)
625 DBG_MSG("slicoss: %s iounmap dev->base_addr[%x]\n", __func__, 616 DBG_MSG("slicoss: %s iounmap dev->base_addr[%x]\n", __func__,
626 (uint) dev->base_addr); 617 (uint) dev->base_addr);
627 iounmap((void __iomem *)dev->base_addr); 618 iounmap((void __iomem *)dev->base_addr);
619 /* free multicast addresses */
620 mlist = adapter->mcastaddrs;
621 while (mlist) {
622 mcaddr = mlist;
623 mlist = mlist->next;
624 kfree(mcaddr);
625 }
628 ASSERT(adapter->card); 626 ASSERT(adapter->card);
629 card = adapter->card; 627 card = adapter->card;
630 ASSERT(card->adapters_allocated); 628 ASSERT(card->adapters_allocated);
diff --git a/drivers/staging/sxg/README b/drivers/staging/sxg/README
index 4d1ddbe4c335..d514d1848803 100644
--- a/drivers/staging/sxg/README
+++ b/drivers/staging/sxg/README
@@ -7,6 +7,7 @@ TODO:
7 - remove wrappers 7 - remove wrappers
8 - checkpatch.pl cleanups 8 - checkpatch.pl cleanups
9 - new functionality that the card needs 9 - new functionality that the card needs
10 - remove reliance on x86
10 11
11Please send patches to: 12Please send patches to:
12 Greg Kroah-Hartman <gregkh@suse.de> 13 Greg Kroah-Hartman <gregkh@suse.de>
diff --git a/drivers/staging/sxg/sxg.c b/drivers/staging/sxg/sxg.c
index 6ccbee875ab3..5272a18e2043 100644
--- a/drivers/staging/sxg/sxg.c
+++ b/drivers/staging/sxg/sxg.c
@@ -112,12 +112,16 @@ static bool sxg_mac_filter(p_adapter_t adapter,
112static struct net_device_stats *sxg_get_stats(p_net_device dev); 112static struct net_device_stats *sxg_get_stats(p_net_device dev);
113#endif 113#endif
114 114
115#define XXXTODO 0
116
117#if XXXTODO
115static int sxg_mac_set_address(p_net_device dev, void *ptr); 118static int sxg_mac_set_address(p_net_device dev, void *ptr);
119static void sxg_mcast_set_list(p_net_device dev);
120#endif
116 121
117static void sxg_adapter_set_hwaddr(p_adapter_t adapter); 122static void sxg_adapter_set_hwaddr(p_adapter_t adapter);
118 123
119static void sxg_unmap_mmio_space(p_adapter_t adapter); 124static void sxg_unmap_mmio_space(p_adapter_t adapter);
120static void sxg_mcast_set_mask(p_adapter_t adapter);
121 125
122static int sxg_initialize_adapter(p_adapter_t adapter); 126static int sxg_initialize_adapter(p_adapter_t adapter);
123static void sxg_stock_rcv_buffers(p_adapter_t adapter); 127static void sxg_stock_rcv_buffers(p_adapter_t adapter);
@@ -132,9 +136,6 @@ static int sxg_write_mdio_reg(p_adapter_t adapter,
132 u32 DevAddr, u32 RegAddr, u32 Value); 136 u32 DevAddr, u32 RegAddr, u32 Value);
133static int sxg_read_mdio_reg(p_adapter_t adapter, 137static int sxg_read_mdio_reg(p_adapter_t adapter,
134 u32 DevAddr, u32 RegAddr, u32 *pValue); 138 u32 DevAddr, u32 RegAddr, u32 *pValue);
135static void sxg_mcast_set_list(p_net_device dev);
136
137#define XXXTODO 0
138 139
139static unsigned int sxg_first_init = 1; 140static unsigned int sxg_first_init = 1;
140static char *sxg_banner = 141static char *sxg_banner =
@@ -202,7 +203,7 @@ static void sxg_init_driver(void)
202{ 203{
203 if (sxg_first_init) { 204 if (sxg_first_init) {
204 DBG_ERROR("sxg: %s sxg_first_init set jiffies[%lx]\n", 205 DBG_ERROR("sxg: %s sxg_first_init set jiffies[%lx]\n",
205 __FUNCTION__, jiffies); 206 __func__, jiffies);
206 sxg_first_init = 0; 207 sxg_first_init = 0;
207 spin_lock_init(&sxg_global.driver_lock); 208 spin_lock_init(&sxg_global.driver_lock);
208 } 209 }
@@ -223,7 +224,7 @@ static void sxg_dbg_macaddrs(p_adapter_t adapter)
223 return; 224 return;
224} 225}
225 226
226// SXG Globals 227/* SXG Globals */
227static SXG_DRIVER SxgDriver; 228static SXG_DRIVER SxgDriver;
228 229
229#ifdef ATKDBG 230#ifdef ATKDBG
@@ -250,7 +251,7 @@ static bool sxg_download_microcode(p_adapter_t adapter, SXG_UCODE_SEL UcodeSel)
250 u32 ThisSectionSize; 251 u32 ThisSectionSize;
251 u32 *Instruction = NULL; 252 u32 *Instruction = NULL;
252 u32 BaseAddress, AddressOffset, Address; 253 u32 BaseAddress, AddressOffset, Address;
253// u32 Failure; 254/* u32 Failure; */
254 u32 ValueRead; 255 u32 ValueRead;
255 u32 i; 256 u32 i;
256 u32 numSections = 0; 257 u32 numSections = 0;
@@ -259,10 +260,10 @@ static bool sxg_download_microcode(p_adapter_t adapter, SXG_UCODE_SEL UcodeSel)
259 260
260 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DnldUcod", 261 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DnldUcod",
261 adapter, 0, 0, 0); 262 adapter, 0, 0, 0);
262 DBG_ERROR("sxg: %s ENTER\n", __FUNCTION__); 263 DBG_ERROR("sxg: %s ENTER\n", __func__);
263 264
264 switch (UcodeSel) { 265 switch (UcodeSel) {
265 case SXG_UCODE_SAHARA: // Sahara operational ucode 266 case SXG_UCODE_SAHARA: /* Sahara operational ucode */
266 numSections = SNumSections; 267 numSections = SNumSections;
267 for (i = 0; i < numSections; i++) { 268 for (i = 0; i < numSections; i++) {
268 sectionSize[i] = SSectionSize[i]; 269 sectionSize[i] = SSectionSize[i];
@@ -276,13 +277,13 @@ static bool sxg_download_microcode(p_adapter_t adapter, SXG_UCODE_SEL UcodeSel)
276 } 277 }
277 278
278 DBG_ERROR("sxg: RESET THE CARD\n"); 279 DBG_ERROR("sxg: RESET THE CARD\n");
279 // First, reset the card 280 /* First, reset the card */
280 WRITE_REG(HwRegs->Reset, 0xDEAD, FLUSH); 281 WRITE_REG(HwRegs->Reset, 0xDEAD, FLUSH);
281 282
282 // Download each section of the microcode as specified in 283 /* Download each section of the microcode as specified in */
283 // its download file. The *download.c file is generated using 284 /* its download file. The *download.c file is generated using */
284 // the saharaobjtoc facility which converts the metastep .obj 285 /* the saharaobjtoc facility which converts the metastep .obj */
285 // file to a .c file which contains a two dimentional array. 286 /* file to a .c file which contains a two dimentional array. */
286 for (Section = 0; Section < numSections; Section++) { 287 for (Section = 0; Section < numSections; Section++) {
287 DBG_ERROR("sxg: SECTION # %d\n", Section); 288 DBG_ERROR("sxg: SECTION # %d\n", Section);
288 switch (UcodeSel) { 289 switch (UcodeSel) {
@@ -294,35 +295,35 @@ static bool sxg_download_microcode(p_adapter_t adapter, SXG_UCODE_SEL UcodeSel)
294 break; 295 break;
295 } 296 }
296 BaseAddress = sectionStart[Section]; 297 BaseAddress = sectionStart[Section];
297 ThisSectionSize = sectionSize[Section] / 12; // Size in instructions 298 ThisSectionSize = sectionSize[Section] / 12; /* Size in instructions */
298 for (AddressOffset = 0; AddressOffset < ThisSectionSize; 299 for (AddressOffset = 0; AddressOffset < ThisSectionSize;
299 AddressOffset++) { 300 AddressOffset++) {
300 Address = BaseAddress + AddressOffset; 301 Address = BaseAddress + AddressOffset;
301 ASSERT((Address & ~MICROCODE_ADDRESS_MASK) == 0); 302 ASSERT((Address & ~MICROCODE_ADDRESS_MASK) == 0);
302 // Write instruction bits 31 - 0 303 /* Write instruction bits 31 - 0 */
303 WRITE_REG(HwRegs->UcodeDataLow, *Instruction, FLUSH); 304 WRITE_REG(HwRegs->UcodeDataLow, *Instruction, FLUSH);
304 // Write instruction bits 63-32 305 /* Write instruction bits 63-32 */
305 WRITE_REG(HwRegs->UcodeDataMiddle, *(Instruction + 1), 306 WRITE_REG(HwRegs->UcodeDataMiddle, *(Instruction + 1),
306 FLUSH); 307 FLUSH);
307 // Write instruction bits 95-64 308 /* Write instruction bits 95-64 */
308 WRITE_REG(HwRegs->UcodeDataHigh, *(Instruction + 2), 309 WRITE_REG(HwRegs->UcodeDataHigh, *(Instruction + 2),
309 FLUSH); 310 FLUSH);
310 // Write instruction address with the WRITE bit set 311 /* Write instruction address with the WRITE bit set */
311 WRITE_REG(HwRegs->UcodeAddr, 312 WRITE_REG(HwRegs->UcodeAddr,
312 (Address | MICROCODE_ADDRESS_WRITE), FLUSH); 313 (Address | MICROCODE_ADDRESS_WRITE), FLUSH);
313 // Sahara bug in the ucode download logic - the write to DataLow 314 /* Sahara bug in the ucode download logic - the write to DataLow */
314 // for the next instruction could get corrupted. To avoid this, 315 /* for the next instruction could get corrupted. To avoid this, */
315 // write to DataLow again for this instruction (which may get 316 /* write to DataLow again for this instruction (which may get */
316 // corrupted, but it doesn't matter), then increment the address 317 /* corrupted, but it doesn't matter), then increment the address */
317 // and write the data for the next instruction to DataLow. That 318 /* and write the data for the next instruction to DataLow. That */
318 // write should succeed. 319 /* write should succeed. */
319 WRITE_REG(HwRegs->UcodeDataLow, *Instruction, TRUE); 320 WRITE_REG(HwRegs->UcodeDataLow, *Instruction, TRUE);
320 // Advance 3 u32S to start of next instruction 321 /* Advance 3 u32S to start of next instruction */
321 Instruction += 3; 322 Instruction += 3;
322 } 323 }
323 } 324 }
324 // Now repeat the entire operation reading the instruction back and 325 /* Now repeat the entire operation reading the instruction back and */
325 // checking for parity errors 326 /* checking for parity errors */
326 for (Section = 0; Section < numSections; Section++) { 327 for (Section = 0; Section < numSections; Section++) {
327 DBG_ERROR("sxg: check SECTION # %d\n", Section); 328 DBG_ERROR("sxg: check SECTION # %d\n", Section);
328 switch (UcodeSel) { 329 switch (UcodeSel) {
@@ -334,74 +335,74 @@ static bool sxg_download_microcode(p_adapter_t adapter, SXG_UCODE_SEL UcodeSel)
334 break; 335 break;
335 } 336 }
336 BaseAddress = sectionStart[Section]; 337 BaseAddress = sectionStart[Section];
337 ThisSectionSize = sectionSize[Section] / 12; // Size in instructions 338 ThisSectionSize = sectionSize[Section] / 12; /* Size in instructions */
338 for (AddressOffset = 0; AddressOffset < ThisSectionSize; 339 for (AddressOffset = 0; AddressOffset < ThisSectionSize;
339 AddressOffset++) { 340 AddressOffset++) {
340 Address = BaseAddress + AddressOffset; 341 Address = BaseAddress + AddressOffset;
341 // Write the address with the READ bit set 342 /* Write the address with the READ bit set */
342 WRITE_REG(HwRegs->UcodeAddr, 343 WRITE_REG(HwRegs->UcodeAddr,
343 (Address | MICROCODE_ADDRESS_READ), FLUSH); 344 (Address | MICROCODE_ADDRESS_READ), FLUSH);
344 // Read it back and check parity bit. 345 /* Read it back and check parity bit. */
345 READ_REG(HwRegs->UcodeAddr, ValueRead); 346 READ_REG(HwRegs->UcodeAddr, ValueRead);
346 if (ValueRead & MICROCODE_ADDRESS_PARITY) { 347 if (ValueRead & MICROCODE_ADDRESS_PARITY) {
347 DBG_ERROR("sxg: %s PARITY ERROR\n", 348 DBG_ERROR("sxg: %s PARITY ERROR\n",
348 __FUNCTION__); 349 __func__);
349 350
350 return (FALSE); // Parity error 351 return (FALSE); /* Parity error */
351 } 352 }
352 ASSERT((ValueRead & MICROCODE_ADDRESS_MASK) == Address); 353 ASSERT((ValueRead & MICROCODE_ADDRESS_MASK) == Address);
353 // Read the instruction back and compare 354 /* Read the instruction back and compare */
354 READ_REG(HwRegs->UcodeDataLow, ValueRead); 355 READ_REG(HwRegs->UcodeDataLow, ValueRead);
355 if (ValueRead != *Instruction) { 356 if (ValueRead != *Instruction) {
356 DBG_ERROR("sxg: %s MISCOMPARE LOW\n", 357 DBG_ERROR("sxg: %s MISCOMPARE LOW\n",
357 __FUNCTION__); 358 __func__);
358 return (FALSE); // Miscompare 359 return (FALSE); /* Miscompare */
359 } 360 }
360 READ_REG(HwRegs->UcodeDataMiddle, ValueRead); 361 READ_REG(HwRegs->UcodeDataMiddle, ValueRead);
361 if (ValueRead != *(Instruction + 1)) { 362 if (ValueRead != *(Instruction + 1)) {
362 DBG_ERROR("sxg: %s MISCOMPARE MIDDLE\n", 363 DBG_ERROR("sxg: %s MISCOMPARE MIDDLE\n",
363 __FUNCTION__); 364 __func__);
364 return (FALSE); // Miscompare 365 return (FALSE); /* Miscompare */
365 } 366 }
366 READ_REG(HwRegs->UcodeDataHigh, ValueRead); 367 READ_REG(HwRegs->UcodeDataHigh, ValueRead);
367 if (ValueRead != *(Instruction + 2)) { 368 if (ValueRead != *(Instruction + 2)) {
368 DBG_ERROR("sxg: %s MISCOMPARE HIGH\n", 369 DBG_ERROR("sxg: %s MISCOMPARE HIGH\n",
369 __FUNCTION__); 370 __func__);
370 return (FALSE); // Miscompare 371 return (FALSE); /* Miscompare */
371 } 372 }
372 // Advance 3 u32S to start of next instruction 373 /* Advance 3 u32S to start of next instruction */
373 Instruction += 3; 374 Instruction += 3;
374 } 375 }
375 } 376 }
376 377
377 // Everything OK, Go. 378 /* Everything OK, Go. */
378 WRITE_REG(HwRegs->UcodeAddr, MICROCODE_ADDRESS_GO, FLUSH); 379 WRITE_REG(HwRegs->UcodeAddr, MICROCODE_ADDRESS_GO, FLUSH);
379 380
380 // Poll the CardUp register to wait for microcode to initialize 381 /* Poll the CardUp register to wait for microcode to initialize */
381 // Give up after 10,000 attemps (500ms). 382 /* Give up after 10,000 attemps (500ms). */
382 for (i = 0; i < 10000; i++) { 383 for (i = 0; i < 10000; i++) {
383 udelay(50); 384 udelay(50);
384 READ_REG(adapter->UcodeRegs[0].CardUp, ValueRead); 385 READ_REG(adapter->UcodeRegs[0].CardUp, ValueRead);
385 if (ValueRead == 0xCAFE) { 386 if (ValueRead == 0xCAFE) {
386 DBG_ERROR("sxg: %s BOO YA 0xCAFE\n", __FUNCTION__); 387 DBG_ERROR("sxg: %s BOO YA 0xCAFE\n", __func__);
387 break; 388 break;
388 } 389 }
389 } 390 }
390 if (i == 10000) { 391 if (i == 10000) {
391 DBG_ERROR("sxg: %s TIMEOUT\n", __FUNCTION__); 392 DBG_ERROR("sxg: %s TIMEOUT\n", __func__);
392 393
393 return (FALSE); // Timeout 394 return (FALSE); /* Timeout */
394 } 395 }
395 // Now write the LoadSync register. This is used to 396 /* Now write the LoadSync register. This is used to */
396 // synchronize with the card so it can scribble on the memory 397 /* synchronize with the card so it can scribble on the memory */
397 // that contained 0xCAFE from the "CardUp" step above 398 /* that contained 0xCAFE from the "CardUp" step above */
398 if (UcodeSel == SXG_UCODE_SAHARA) { 399 if (UcodeSel == SXG_UCODE_SAHARA) {
399 WRITE_REG(adapter->UcodeRegs[0].LoadSync, 0, FLUSH); 400 WRITE_REG(adapter->UcodeRegs[0].LoadSync, 0, FLUSH);
400 } 401 }
401 402
402 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDnldUcd", 403 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDnldUcd",
403 adapter, 0, 0, 0); 404 adapter, 0, 0, 0);
404 DBG_ERROR("sxg: %s EXIT\n", __FUNCTION__); 405 DBG_ERROR("sxg: %s EXIT\n", __func__);
405 406
406 return (TRUE); 407 return (TRUE);
407} 408}
@@ -420,29 +421,29 @@ static int sxg_allocate_resources(p_adapter_t adapter)
420 int status; 421 int status;
421 u32 i; 422 u32 i;
422 u32 RssIds, IsrCount; 423 u32 RssIds, IsrCount;
423// PSXG_XMT_RING XmtRing; 424/* PSXG_XMT_RING XmtRing; */
424// PSXG_RCV_RING RcvRing; 425/* PSXG_RCV_RING RcvRing; */
425 426
426 DBG_ERROR("%s ENTER\n", __FUNCTION__); 427 DBG_ERROR("%s ENTER\n", __func__);
427 428
428 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocRes", 429 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocRes",
429 adapter, 0, 0, 0); 430 adapter, 0, 0, 0);
430 431
431 // Windows tells us how many CPUs it plans to use for 432 /* Windows tells us how many CPUs it plans to use for */
432 // RSS 433 /* RSS */
433 RssIds = SXG_RSS_CPU_COUNT(adapter); 434 RssIds = SXG_RSS_CPU_COUNT(adapter);
434 IsrCount = adapter->MsiEnabled ? RssIds : 1; 435 IsrCount = adapter->MsiEnabled ? RssIds : 1;
435 436
436 DBG_ERROR("%s Setup the spinlocks\n", __FUNCTION__); 437 DBG_ERROR("%s Setup the spinlocks\n", __func__);
437 438
438 // Allocate spinlocks and initialize listheads first. 439 /* Allocate spinlocks and initialize listheads first. */
439 spin_lock_init(&adapter->RcvQLock); 440 spin_lock_init(&adapter->RcvQLock);
440 spin_lock_init(&adapter->SglQLock); 441 spin_lock_init(&adapter->SglQLock);
441 spin_lock_init(&adapter->XmtZeroLock); 442 spin_lock_init(&adapter->XmtZeroLock);
442 spin_lock_init(&adapter->Bit64RegLock); 443 spin_lock_init(&adapter->Bit64RegLock);
443 spin_lock_init(&adapter->AdapterLock); 444 spin_lock_init(&adapter->AdapterLock);
444 445
445 DBG_ERROR("%s Setup the lists\n", __FUNCTION__); 446 DBG_ERROR("%s Setup the lists\n", __func__);
446 447
447 InitializeListHead(&adapter->FreeRcvBuffers); 448 InitializeListHead(&adapter->FreeRcvBuffers);
448 InitializeListHead(&adapter->FreeRcvBlocks); 449 InitializeListHead(&adapter->FreeRcvBlocks);
@@ -450,39 +451,39 @@ static int sxg_allocate_resources(p_adapter_t adapter)
450 InitializeListHead(&adapter->FreeSglBuffers); 451 InitializeListHead(&adapter->FreeSglBuffers);
451 InitializeListHead(&adapter->AllSglBuffers); 452 InitializeListHead(&adapter->AllSglBuffers);
452 453
453 // Mark these basic allocations done. This flags essentially 454 /* Mark these basic allocations done. This flags essentially */
454 // tells the SxgFreeResources routine that it can grab spinlocks 455 /* tells the SxgFreeResources routine that it can grab spinlocks */
455 // and reference listheads. 456 /* and reference listheads. */
456 adapter->BasicAllocations = TRUE; 457 adapter->BasicAllocations = TRUE;
457 // Main allocation loop. Start with the maximum supported by 458 /* Main allocation loop. Start with the maximum supported by */
458 // the microcode and back off if memory allocation 459 /* the microcode and back off if memory allocation */
459 // fails. If we hit a minimum, fail. 460 /* fails. If we hit a minimum, fail. */
460 461
461 for (;;) { 462 for (;;) {
462 DBG_ERROR("%s Allocate XmtRings size[%lx]\n", __FUNCTION__, 463 DBG_ERROR("%s Allocate XmtRings size[%x]\n", __func__,
463 (sizeof(SXG_XMT_RING) * 1)); 464 (unsigned int)(sizeof(SXG_XMT_RING) * 1));
464 465
465 // Start with big items first - receive and transmit rings. At the moment 466 /* Start with big items first - receive and transmit rings. At the moment */
466 // I'm going to keep the ring size fixed and adjust the number of 467 /* I'm going to keep the ring size fixed and adjust the number of */
467 // TCBs if we fail. Later we might consider reducing the ring size as well.. 468 /* TCBs if we fail. Later we might consider reducing the ring size as well.. */
468 adapter->XmtRings = pci_alloc_consistent(adapter->pcidev, 469 adapter->XmtRings = pci_alloc_consistent(adapter->pcidev,
469 sizeof(SXG_XMT_RING) * 470 sizeof(SXG_XMT_RING) *
470 1, 471 1,
471 &adapter->PXmtRings); 472 &adapter->PXmtRings);
472 DBG_ERROR("%s XmtRings[%p]\n", __FUNCTION__, adapter->XmtRings); 473 DBG_ERROR("%s XmtRings[%p]\n", __func__, adapter->XmtRings);
473 474
474 if (!adapter->XmtRings) { 475 if (!adapter->XmtRings) {
475 goto per_tcb_allocation_failed; 476 goto per_tcb_allocation_failed;
476 } 477 }
477 memset(adapter->XmtRings, 0, sizeof(SXG_XMT_RING) * 1); 478 memset(adapter->XmtRings, 0, sizeof(SXG_XMT_RING) * 1);
478 479
479 DBG_ERROR("%s Allocate RcvRings size[%lx]\n", __FUNCTION__, 480 DBG_ERROR("%s Allocate RcvRings size[%x]\n", __func__,
480 (sizeof(SXG_RCV_RING) * 1)); 481 (unsigned int)(sizeof(SXG_RCV_RING) * 1));
481 adapter->RcvRings = 482 adapter->RcvRings =
482 pci_alloc_consistent(adapter->pcidev, 483 pci_alloc_consistent(adapter->pcidev,
483 sizeof(SXG_RCV_RING) * 1, 484 sizeof(SXG_RCV_RING) * 1,
484 &adapter->PRcvRings); 485 &adapter->PRcvRings);
485 DBG_ERROR("%s RcvRings[%p]\n", __FUNCTION__, adapter->RcvRings); 486 DBG_ERROR("%s RcvRings[%p]\n", __func__, adapter->RcvRings);
486 if (!adapter->RcvRings) { 487 if (!adapter->RcvRings) {
487 goto per_tcb_allocation_failed; 488 goto per_tcb_allocation_failed;
488 } 489 }
@@ -490,7 +491,7 @@ static int sxg_allocate_resources(p_adapter_t adapter)
490 break; 491 break;
491 492
492 per_tcb_allocation_failed: 493 per_tcb_allocation_failed:
493 // an allocation failed. Free any successful allocations. 494 /* an allocation failed. Free any successful allocations. */
494 if (adapter->XmtRings) { 495 if (adapter->XmtRings) {
495 pci_free_consistent(adapter->pcidev, 496 pci_free_consistent(adapter->pcidev,
496 sizeof(SXG_XMT_RING) * 4096, 497 sizeof(SXG_XMT_RING) * 4096,
@@ -505,22 +506,22 @@ static int sxg_allocate_resources(p_adapter_t adapter)
505 adapter->PRcvRings); 506 adapter->PRcvRings);
506 adapter->RcvRings = NULL; 507 adapter->RcvRings = NULL;
507 } 508 }
508 // Loop around and try again.... 509 /* Loop around and try again.... */
509 } 510 }
510 511
511 DBG_ERROR("%s Initialize RCV ZERO and XMT ZERO rings\n", __FUNCTION__); 512 DBG_ERROR("%s Initialize RCV ZERO and XMT ZERO rings\n", __func__);
512 // Initialize rcv zero and xmt zero rings 513 /* Initialize rcv zero and xmt zero rings */
513 SXG_INITIALIZE_RING(adapter->RcvRingZeroInfo, SXG_RCV_RING_SIZE); 514 SXG_INITIALIZE_RING(adapter->RcvRingZeroInfo, SXG_RCV_RING_SIZE);
514 SXG_INITIALIZE_RING(adapter->XmtRingZeroInfo, SXG_XMT_RING_SIZE); 515 SXG_INITIALIZE_RING(adapter->XmtRingZeroInfo, SXG_XMT_RING_SIZE);
515 516
516 // Sanity check receive data structure format 517 /* Sanity check receive data structure format */
517 ASSERT((adapter->ReceiveBufferSize == SXG_RCV_DATA_BUFFER_SIZE) || 518 ASSERT((adapter->ReceiveBufferSize == SXG_RCV_DATA_BUFFER_SIZE) ||
518 (adapter->ReceiveBufferSize == SXG_RCV_JUMBO_BUFFER_SIZE)); 519 (adapter->ReceiveBufferSize == SXG_RCV_JUMBO_BUFFER_SIZE));
519 ASSERT(sizeof(SXG_RCV_DESCRIPTOR_BLOCK) == 520 ASSERT(sizeof(SXG_RCV_DESCRIPTOR_BLOCK) ==
520 SXG_RCV_DESCRIPTOR_BLOCK_SIZE); 521 SXG_RCV_DESCRIPTOR_BLOCK_SIZE);
521 522
522 // Allocate receive data buffers. We allocate a block of buffers and 523 /* Allocate receive data buffers. We allocate a block of buffers and */
523 // a corresponding descriptor block at once. See sxghw.h:SXG_RCV_BLOCK 524 /* a corresponding descriptor block at once. See sxghw.h:SXG_RCV_BLOCK */
524 for (i = 0; i < SXG_INITIAL_RCV_DATA_BUFFERS; 525 for (i = 0; i < SXG_INITIAL_RCV_DATA_BUFFERS;
525 i += SXG_RCV_DESCRIPTORS_PER_BLOCK) { 526 i += SXG_RCV_DESCRIPTORS_PER_BLOCK) {
526 sxg_allocate_buffer_memory(adapter, 527 sxg_allocate_buffer_memory(adapter,
@@ -528,8 +529,8 @@ static int sxg_allocate_resources(p_adapter_t adapter)
528 ReceiveBufferSize), 529 ReceiveBufferSize),
529 SXG_BUFFER_TYPE_RCV); 530 SXG_BUFFER_TYPE_RCV);
530 } 531 }
531 // NBL resource allocation can fail in the 'AllocateComplete' routine, which 532 /* NBL resource allocation can fail in the 'AllocateComplete' routine, which */
532 // doesn't return status. Make sure we got the number of buffers we requested 533 /* doesn't return status. Make sure we got the number of buffers we requested */
533 if (adapter->FreeRcvBufferCount < SXG_INITIAL_RCV_DATA_BUFFERS) { 534 if (adapter->FreeRcvBufferCount < SXG_INITIAL_RCV_DATA_BUFFERS) {
534 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF6", 535 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF6",
535 adapter, adapter->FreeRcvBufferCount, SXG_MAX_ENTRIES, 536 adapter, adapter->FreeRcvBufferCount, SXG_MAX_ENTRIES,
@@ -537,17 +538,17 @@ static int sxg_allocate_resources(p_adapter_t adapter)
537 return (STATUS_RESOURCES); 538 return (STATUS_RESOURCES);
538 } 539 }
539 540
540 DBG_ERROR("%s Allocate EventRings size[%lx]\n", __FUNCTION__, 541 DBG_ERROR("%s Allocate EventRings size[%x]\n", __func__,
541 (sizeof(SXG_EVENT_RING) * RssIds)); 542 (unsigned int)(sizeof(SXG_EVENT_RING) * RssIds));
542 543
543 // Allocate event queues. 544 /* Allocate event queues. */
544 adapter->EventRings = pci_alloc_consistent(adapter->pcidev, 545 adapter->EventRings = pci_alloc_consistent(adapter->pcidev,
545 sizeof(SXG_EVENT_RING) * 546 sizeof(SXG_EVENT_RING) *
546 RssIds, 547 RssIds,
547 &adapter->PEventRings); 548 &adapter->PEventRings);
548 549
549 if (!adapter->EventRings) { 550 if (!adapter->EventRings) {
550 // Caller will call SxgFreeAdapter to clean up above allocations 551 /* Caller will call SxgFreeAdapter to clean up above allocations */
551 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF8", 552 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF8",
552 adapter, SXG_MAX_ENTRIES, 0, 0); 553 adapter, SXG_MAX_ENTRIES, 0, 0);
553 status = STATUS_RESOURCES; 554 status = STATUS_RESOURCES;
@@ -555,12 +556,12 @@ static int sxg_allocate_resources(p_adapter_t adapter)
555 } 556 }
556 memset(adapter->EventRings, 0, sizeof(SXG_EVENT_RING) * RssIds); 557 memset(adapter->EventRings, 0, sizeof(SXG_EVENT_RING) * RssIds);
557 558
558 DBG_ERROR("%s Allocate ISR size[%x]\n", __FUNCTION__, IsrCount); 559 DBG_ERROR("%s Allocate ISR size[%x]\n", __func__, IsrCount);
559 // Allocate ISR 560 /* Allocate ISR */
560 adapter->Isr = pci_alloc_consistent(adapter->pcidev, 561 adapter->Isr = pci_alloc_consistent(adapter->pcidev,
561 IsrCount, &adapter->PIsr); 562 IsrCount, &adapter->PIsr);
562 if (!adapter->Isr) { 563 if (!adapter->Isr) {
563 // Caller will call SxgFreeAdapter to clean up above allocations 564 /* Caller will call SxgFreeAdapter to clean up above allocations */
564 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF9", 565 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF9",
565 adapter, SXG_MAX_ENTRIES, 0, 0); 566 adapter, SXG_MAX_ENTRIES, 0, 0);
566 status = STATUS_RESOURCES; 567 status = STATUS_RESOURCES;
@@ -568,10 +569,10 @@ static int sxg_allocate_resources(p_adapter_t adapter)
568 } 569 }
569 memset(adapter->Isr, 0, sizeof(u32) * IsrCount); 570 memset(adapter->Isr, 0, sizeof(u32) * IsrCount);
570 571
571 DBG_ERROR("%s Allocate shared XMT ring zero index location size[%lx]\n", 572 DBG_ERROR("%s Allocate shared XMT ring zero index location size[%x]\n",
572 __FUNCTION__, sizeof(u32)); 573 __func__, (unsigned int)sizeof(u32));
573 574
574 // Allocate shared XMT ring zero index location 575 /* Allocate shared XMT ring zero index location */
575 adapter->XmtRingZeroIndex = pci_alloc_consistent(adapter->pcidev, 576 adapter->XmtRingZeroIndex = pci_alloc_consistent(adapter->pcidev,
576 sizeof(u32), 577 sizeof(u32),
577 &adapter-> 578 &adapter->
@@ -587,7 +588,7 @@ static int sxg_allocate_resources(p_adapter_t adapter)
587 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlcResS", 588 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlcResS",
588 adapter, SXG_MAX_ENTRIES, 0, 0); 589 adapter, SXG_MAX_ENTRIES, 0, 0);
589 590
590 DBG_ERROR("%s EXIT\n", __FUNCTION__); 591 DBG_ERROR("%s EXIT\n", __func__);
591 return (STATUS_SUCCESS); 592 return (STATUS_SUCCESS);
592} 593}
593 594
@@ -606,17 +607,17 @@ static void sxg_config_pci(struct pci_dev *pcidev)
606 u16 new_command; 607 u16 new_command;
607 608
608 pci_read_config_word(pcidev, PCI_COMMAND, &pci_command); 609 pci_read_config_word(pcidev, PCI_COMMAND, &pci_command);
609 DBG_ERROR("sxg: %s PCI command[%4.4x]\n", __FUNCTION__, pci_command); 610 DBG_ERROR("sxg: %s PCI command[%4.4x]\n", __func__, pci_command);
610 // Set the command register 611 /* Set the command register */
611 new_command = pci_command | (PCI_COMMAND_MEMORY | // Memory Space Enable 612 new_command = pci_command | (PCI_COMMAND_MEMORY | /* Memory Space Enable */
612 PCI_COMMAND_MASTER | // Bus master enable 613 PCI_COMMAND_MASTER | /* Bus master enable */
613 PCI_COMMAND_INVALIDATE | // Memory write and invalidate 614 PCI_COMMAND_INVALIDATE | /* Memory write and invalidate */
614 PCI_COMMAND_PARITY | // Parity error response 615 PCI_COMMAND_PARITY | /* Parity error response */
615 PCI_COMMAND_SERR | // System ERR 616 PCI_COMMAND_SERR | /* System ERR */
616 PCI_COMMAND_FAST_BACK); // Fast back-to-back 617 PCI_COMMAND_FAST_BACK); /* Fast back-to-back */
617 if (pci_command != new_command) { 618 if (pci_command != new_command) {
618 DBG_ERROR("%s -- Updating PCI COMMAND register %4.4x->%4.4x.\n", 619 DBG_ERROR("%s -- Updating PCI COMMAND register %4.4x->%4.4x.\n",
619 __FUNCTION__, pci_command, new_command); 620 __func__, pci_command, new_command);
620 pci_write_config_word(pcidev, PCI_COMMAND, new_command); 621 pci_write_config_word(pcidev, PCI_COMMAND, new_command);
621 } 622 }
622} 623}
@@ -634,9 +635,9 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
634 ulong mmio_len = 0; 635 ulong mmio_len = 0;
635 636
636 DBG_ERROR("sxg: %s 2.6 VERSION ENTER jiffies[%lx] cpu %d\n", 637 DBG_ERROR("sxg: %s 2.6 VERSION ENTER jiffies[%lx] cpu %d\n",
637 __FUNCTION__, jiffies, smp_processor_id()); 638 __func__, jiffies, smp_processor_id());
638 639
639 // Initialize trace buffer 640 /* Initialize trace buffer */
640#ifdef ATKDBG 641#ifdef ATKDBG
641 SxgTraceBuffer = &LSxgTraceBuffer; 642 SxgTraceBuffer = &LSxgTraceBuffer;
642 SXG_TRACE_INIT(SxgTraceBuffer, TRACE_NOISY); 643 SXG_TRACE_INIT(SxgTraceBuffer, TRACE_NOISY);
@@ -701,11 +702,11 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
701 mmio_start, mmio_len); 702 mmio_start, mmio_len);
702 703
703 memmapped_ioaddr = ioremap(mmio_start, mmio_len); 704 memmapped_ioaddr = ioremap(mmio_start, mmio_len);
704 DBG_ERROR("sxg: %s MEMMAPPED_IOADDR [%p]\n", __FUNCTION__, 705 DBG_ERROR("sxg: %s MEMMAPPED_IOADDR [%p]\n", __func__,
705 memmapped_ioaddr); 706 memmapped_ioaddr);
706 if (!memmapped_ioaddr) { 707 if (!memmapped_ioaddr) {
707 DBG_ERROR("%s cannot remap MMIO region %lx @ %lx\n", 708 DBG_ERROR("%s cannot remap MMIO region %lx @ %lx\n",
708 __FUNCTION__, mmio_len, mmio_start); 709 __func__, mmio_len, mmio_start);
709 goto err_out_free_mmio_region; 710 goto err_out_free_mmio_region;
710 } 711 }
711 712
@@ -727,7 +728,7 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
727 memmapped_ioaddr); 728 memmapped_ioaddr);
728 if (!memmapped_ioaddr) { 729 if (!memmapped_ioaddr) {
729 DBG_ERROR("%s cannot remap MMIO region %lx @ %lx\n", 730 DBG_ERROR("%s cannot remap MMIO region %lx @ %lx\n",
730 __FUNCTION__, mmio_len, mmio_start); 731 __func__, mmio_len, mmio_start);
731 goto err_out_free_mmio_region; 732 goto err_out_free_mmio_region;
732 } 733 }
733 734
@@ -738,13 +739,13 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
738 adapter->UcodeRegs = (void *)memmapped_ioaddr; 739 adapter->UcodeRegs = (void *)memmapped_ioaddr;
739 740
740 adapter->State = SXG_STATE_INITIALIZING; 741 adapter->State = SXG_STATE_INITIALIZING;
741 // Maintain a list of all adapters anchored by 742 /* Maintain a list of all adapters anchored by */
742 // the global SxgDriver structure. 743 /* the global SxgDriver structure. */
743 adapter->Next = SxgDriver.Adapters; 744 adapter->Next = SxgDriver.Adapters;
744 SxgDriver.Adapters = adapter; 745 SxgDriver.Adapters = adapter;
745 adapter->AdapterID = ++SxgDriver.AdapterID; 746 adapter->AdapterID = ++SxgDriver.AdapterID;
746 747
747 // Initialize CRC table used to determine multicast hash 748 /* Initialize CRC table used to determine multicast hash */
748 sxg_mcast_init_crc32(); 749 sxg_mcast_init_crc32();
749 750
750 adapter->JumboEnabled = FALSE; 751 adapter->JumboEnabled = FALSE;
@@ -757,18 +758,18 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
757 adapter->ReceiveBufferSize = SXG_RCV_DATA_BUFFER_SIZE; 758 adapter->ReceiveBufferSize = SXG_RCV_DATA_BUFFER_SIZE;
758 } 759 }
759 760
760// status = SXG_READ_EEPROM(adapter); 761/* status = SXG_READ_EEPROM(adapter); */
761// if (!status) { 762/* if (!status) { */
762// goto sxg_init_bad; 763/* goto sxg_init_bad; */
763// } 764/* } */
764 765
765 DBG_ERROR("sxg: %s ENTER sxg_config_pci\n", __FUNCTION__); 766 DBG_ERROR("sxg: %s ENTER sxg_config_pci\n", __func__);
766 sxg_config_pci(pcidev); 767 sxg_config_pci(pcidev);
767 DBG_ERROR("sxg: %s EXIT sxg_config_pci\n", __FUNCTION__); 768 DBG_ERROR("sxg: %s EXIT sxg_config_pci\n", __func__);
768 769
769 DBG_ERROR("sxg: %s ENTER sxg_init_driver\n", __FUNCTION__); 770 DBG_ERROR("sxg: %s ENTER sxg_init_driver\n", __func__);
770 sxg_init_driver(); 771 sxg_init_driver();
771 DBG_ERROR("sxg: %s EXIT sxg_init_driver\n", __FUNCTION__); 772 DBG_ERROR("sxg: %s EXIT sxg_init_driver\n", __func__);
772 773
773 adapter->vendid = pci_tbl_entry->vendor; 774 adapter->vendid = pci_tbl_entry->vendor;
774 adapter->devid = pci_tbl_entry->device; 775 adapter->devid = pci_tbl_entry->device;
@@ -780,23 +781,23 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
780 adapter->irq = pcidev->irq; 781 adapter->irq = pcidev->irq;
781 adapter->next_netdevice = head_netdevice; 782 adapter->next_netdevice = head_netdevice;
782 head_netdevice = netdev; 783 head_netdevice = netdev;
783// adapter->chipid = chip_idx; 784/* adapter->chipid = chip_idx; */
784 adapter->port = 0; //adapter->functionnumber; 785 adapter->port = 0; /*adapter->functionnumber; */
785 adapter->cardindex = adapter->port; 786 adapter->cardindex = adapter->port;
786 787
787 // Allocate memory and other resources 788 /* Allocate memory and other resources */
788 DBG_ERROR("sxg: %s ENTER sxg_allocate_resources\n", __FUNCTION__); 789 DBG_ERROR("sxg: %s ENTER sxg_allocate_resources\n", __func__);
789 status = sxg_allocate_resources(adapter); 790 status = sxg_allocate_resources(adapter);
790 DBG_ERROR("sxg: %s EXIT sxg_allocate_resources status %x\n", 791 DBG_ERROR("sxg: %s EXIT sxg_allocate_resources status %x\n",
791 __FUNCTION__, status); 792 __func__, status);
792 if (status != STATUS_SUCCESS) { 793 if (status != STATUS_SUCCESS) {
793 goto err_out_unmap; 794 goto err_out_unmap;
794 } 795 }
795 796
796 DBG_ERROR("sxg: %s ENTER sxg_download_microcode\n", __FUNCTION__); 797 DBG_ERROR("sxg: %s ENTER sxg_download_microcode\n", __func__);
797 if (sxg_download_microcode(adapter, SXG_UCODE_SAHARA)) { 798 if (sxg_download_microcode(adapter, SXG_UCODE_SAHARA)) {
798 DBG_ERROR("sxg: %s ENTER sxg_adapter_set_hwaddr\n", 799 DBG_ERROR("sxg: %s ENTER sxg_adapter_set_hwaddr\n",
799 __FUNCTION__); 800 __func__);
800 sxg_adapter_set_hwaddr(adapter); 801 sxg_adapter_set_hwaddr(adapter);
801 } else { 802 } else {
802 adapter->state = ADAPT_FAIL; 803 adapter->state = ADAPT_FAIL;
@@ -819,7 +820,7 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
819#endif 820#endif
820 821
821 strcpy(netdev->name, "eth%d"); 822 strcpy(netdev->name, "eth%d");
822// strcpy(netdev->name, pci_name(pcidev)); 823/* strcpy(netdev->name, pci_name(pcidev)); */
823 if ((err = register_netdev(netdev))) { 824 if ((err = register_netdev(netdev))) {
824 DBG_ERROR("Cannot register net device, aborting. %s\n", 825 DBG_ERROR("Cannot register net device, aborting. %s\n",
825 netdev->name); 826 netdev->name);
@@ -832,11 +833,11 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
832 netdev->dev_addr[1], netdev->dev_addr[2], netdev->dev_addr[3], 833 netdev->dev_addr[1], netdev->dev_addr[2], netdev->dev_addr[3],
833 netdev->dev_addr[4], netdev->dev_addr[5]); 834 netdev->dev_addr[4], netdev->dev_addr[5]);
834 835
835//sxg_init_bad: 836/*sxg_init_bad: */
836 ASSERT(status == FALSE); 837 ASSERT(status == FALSE);
837// sxg_free_adapter(adapter); 838/* sxg_free_adapter(adapter); */
838 839
839 DBG_ERROR("sxg: %s EXIT status[%x] jiffies[%lx] cpu %d\n", __FUNCTION__, 840 DBG_ERROR("sxg: %s EXIT status[%x] jiffies[%lx] cpu %d\n", __func__,
840 status, jiffies, smp_processor_id()); 841 status, jiffies, smp_processor_id());
841 return status; 842 return status;
842 843
@@ -848,7 +849,7 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
848 849
849 err_out_exit_sxg_probe: 850 err_out_exit_sxg_probe:
850 851
851 DBG_ERROR("%s EXIT jiffies[%lx] cpu %d\n", __FUNCTION__, jiffies, 852 DBG_ERROR("%s EXIT jiffies[%lx] cpu %d\n", __func__, jiffies,
852 smp_processor_id()); 853 smp_processor_id());
853 854
854 return -ENODEV; 855 return -ENODEV;
@@ -874,12 +875,12 @@ static void sxg_disable_interrupt(p_adapter_t adapter)
874{ 875{
875 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DisIntr", 876 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DisIntr",
876 adapter, adapter->InterruptsEnabled, 0, 0); 877 adapter, adapter->InterruptsEnabled, 0, 0);
877 // For now, RSS is disabled with line based interrupts 878 /* For now, RSS is disabled with line based interrupts */
878 ASSERT(adapter->RssEnabled == FALSE); 879 ASSERT(adapter->RssEnabled == FALSE);
879 ASSERT(adapter->MsiEnabled == FALSE); 880 ASSERT(adapter->MsiEnabled == FALSE);
880 // 881 /* */
881 // Turn off interrupts by writing to the icr register. 882 /* Turn off interrupts by writing to the icr register. */
882 // 883 /* */
883 WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_DISABLE), TRUE); 884 WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_DISABLE), TRUE);
884 885
885 adapter->InterruptsEnabled = 0; 886 adapter->InterruptsEnabled = 0;
@@ -905,12 +906,12 @@ static void sxg_enable_interrupt(p_adapter_t adapter)
905{ 906{
906 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "EnIntr", 907 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "EnIntr",
907 adapter, adapter->InterruptsEnabled, 0, 0); 908 adapter, adapter->InterruptsEnabled, 0, 0);
908 // For now, RSS is disabled with line based interrupts 909 /* For now, RSS is disabled with line based interrupts */
909 ASSERT(adapter->RssEnabled == FALSE); 910 ASSERT(adapter->RssEnabled == FALSE);
910 ASSERT(adapter->MsiEnabled == FALSE); 911 ASSERT(adapter->MsiEnabled == FALSE);
911 // 912 /* */
912 // Turn on interrupts by writing to the icr register. 913 /* Turn on interrupts by writing to the icr register. */
913 // 914 /* */
914 WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_ENABLE), TRUE); 915 WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_ENABLE), TRUE);
915 916
916 adapter->InterruptsEnabled = 1; 917 adapter->InterruptsEnabled = 1;
@@ -935,29 +936,29 @@ static irqreturn_t sxg_isr(int irq, void *dev_id)
935{ 936{
936 p_net_device dev = (p_net_device) dev_id; 937 p_net_device dev = (p_net_device) dev_id;
937 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev); 938 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev);
938// u32 CpuMask = 0, i; 939/* u32 CpuMask = 0, i; */
939 940
940 adapter->Stats.NumInts++; 941 adapter->Stats.NumInts++;
941 if (adapter->Isr[0] == 0) { 942 if (adapter->Isr[0] == 0) {
942 // The SLIC driver used to experience a number of spurious interrupts 943 /* The SLIC driver used to experience a number of spurious interrupts */
943 // due to the delay associated with the masking of the interrupt 944 /* due to the delay associated with the masking of the interrupt */
944 // (we'd bounce back in here). If we see that again with Sahara, 945 /* (we'd bounce back in here). If we see that again with Sahara, */
945 // add a READ_REG of the Icr register after the WRITE_REG below. 946 /* add a READ_REG of the Icr register after the WRITE_REG below. */
946 adapter->Stats.FalseInts++; 947 adapter->Stats.FalseInts++;
947 return IRQ_NONE; 948 return IRQ_NONE;
948 } 949 }
949 // 950 /* */
950 // Move the Isr contents and clear the value in 951 /* Move the Isr contents and clear the value in */
951 // shared memory, and mask interrupts 952 /* shared memory, and mask interrupts */
952 // 953 /* */
953 adapter->IsrCopy[0] = adapter->Isr[0]; 954 adapter->IsrCopy[0] = adapter->Isr[0];
954 adapter->Isr[0] = 0; 955 adapter->Isr[0] = 0;
955 WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_MASK), TRUE); 956 WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_MASK), TRUE);
956// ASSERT(adapter->IsrDpcsPending == 0); 957/* ASSERT(adapter->IsrDpcsPending == 0); */
957#if XXXTODO // RSS Stuff 958#if XXXTODO /* RSS Stuff */
958 // If RSS is enabled and the ISR specifies 959 /* If RSS is enabled and the ISR specifies */
959 // SXG_ISR_EVENT, then schedule DPC's 960 /* SXG_ISR_EVENT, then schedule DPC's */
960 // based on event queues. 961 /* based on event queues. */
961 if (adapter->RssEnabled && (adapter->IsrCopy[0] & SXG_ISR_EVENT)) { 962 if (adapter->RssEnabled && (adapter->IsrCopy[0] & SXG_ISR_EVENT)) {
962 for (i = 0; 963 for (i = 0;
963 i < adapter->RssSystemInfo->ProcessorInfo.RssCpuCount; 964 i < adapter->RssSystemInfo->ProcessorInfo.RssCpuCount;
@@ -973,8 +974,8 @@ static irqreturn_t sxg_isr(int irq, void *dev_id)
973 } 974 }
974 } 975 }
975 } 976 }
976 // Now, either schedule the CPUs specified by the CpuMask, 977 /* Now, either schedule the CPUs specified by the CpuMask, */
977 // or queue default 978 /* or queue default */
978 if (CpuMask) { 979 if (CpuMask) {
979 *QueueDefault = FALSE; 980 *QueueDefault = FALSE;
980 } else { 981 } else {
@@ -983,9 +984,9 @@ static irqreturn_t sxg_isr(int irq, void *dev_id)
983 } 984 }
984 *TargetCpus = CpuMask; 985 *TargetCpus = CpuMask;
985#endif 986#endif
986 // 987 /* */
987 // There are no DPCs in Linux, so call the handler now 988 /* There are no DPCs in Linux, so call the handler now */
988 // 989 /* */
989 sxg_handle_interrupt(adapter); 990 sxg_handle_interrupt(adapter);
990 991
991 return IRQ_HANDLED; 992 return IRQ_HANDLED;
@@ -993,7 +994,7 @@ static irqreturn_t sxg_isr(int irq, void *dev_id)
993 994
994static void sxg_handle_interrupt(p_adapter_t adapter) 995static void sxg_handle_interrupt(p_adapter_t adapter)
995{ 996{
996// unsigned char RssId = 0; 997/* unsigned char RssId = 0; */
997 u32 NewIsr; 998 u32 NewIsr;
998 999
999 if (adapter->Stats.RcvNoBuffer < 5) { 1000 if (adapter->Stats.RcvNoBuffer < 5) {
@@ -1002,32 +1003,32 @@ static void sxg_handle_interrupt(p_adapter_t adapter)
1002 } 1003 }
1003 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "HndlIntr", 1004 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "HndlIntr",
1004 adapter, adapter->IsrCopy[0], 0, 0); 1005 adapter, adapter->IsrCopy[0], 0, 0);
1005 // For now, RSS is disabled with line based interrupts 1006 /* For now, RSS is disabled with line based interrupts */
1006 ASSERT(adapter->RssEnabled == FALSE); 1007 ASSERT(adapter->RssEnabled == FALSE);
1007 ASSERT(adapter->MsiEnabled == FALSE); 1008 ASSERT(adapter->MsiEnabled == FALSE);
1008 ASSERT(adapter->IsrCopy[0]); 1009 ASSERT(adapter->IsrCopy[0]);
1009///////////////////////////// 1010/*/////////////////////////// */
1010 1011
1011 // Always process the event queue. 1012 /* Always process the event queue. */
1012 sxg_process_event_queue(adapter, 1013 sxg_process_event_queue(adapter,
1013 (adapter->RssEnabled ? /*RssId */ 0 : 0)); 1014 (adapter->RssEnabled ? /*RssId */ 0 : 0));
1014 1015
1015#if XXXTODO // RSS stuff 1016#if XXXTODO /* RSS stuff */
1016 if (--adapter->IsrDpcsPending) { 1017 if (--adapter->IsrDpcsPending) {
1017 // We're done. 1018 /* We're done. */
1018 ASSERT(adapter->RssEnabled); 1019 ASSERT(adapter->RssEnabled);
1019 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DPCsPend", 1020 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DPCsPend",
1020 adapter, 0, 0, 0); 1021 adapter, 0, 0, 0);
1021 return; 1022 return;
1022 } 1023 }
1023#endif 1024#endif
1024 // 1025 /* */
1025 // Last (or only) DPC processes the ISR and clears the interrupt. 1026 /* Last (or only) DPC processes the ISR and clears the interrupt. */
1026 // 1027 /* */
1027 NewIsr = sxg_process_isr(adapter, 0); 1028 NewIsr = sxg_process_isr(adapter, 0);
1028 // 1029 /* */
1029 // Reenable interrupts 1030 /* Reenable interrupts */
1030 // 1031 /* */
1031 adapter->IsrCopy[0] = 0; 1032 adapter->IsrCopy[0] = 0;
1032 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "ClearIsr", 1033 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "ClearIsr",
1033 adapter, NewIsr, 0, 0); 1034 adapter, NewIsr, 0, 0);
@@ -1063,75 +1064,75 @@ static int sxg_process_isr(p_adapter_t adapter, u32 MessageId)
1063 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "ProcIsr", 1064 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "ProcIsr",
1064 adapter, Isr, 0, 0); 1065 adapter, Isr, 0, 0);
1065 1066
1066 // Error 1067 /* Error */
1067 if (Isr & SXG_ISR_ERR) { 1068 if (Isr & SXG_ISR_ERR) {
1068 if (Isr & SXG_ISR_PDQF) { 1069 if (Isr & SXG_ISR_PDQF) {
1069 adapter->Stats.PdqFull++; 1070 adapter->Stats.PdqFull++;
1070 DBG_ERROR("%s: SXG_ISR_ERR PDQF!!\n", __FUNCTION__); 1071 DBG_ERROR("%s: SXG_ISR_ERR PDQF!!\n", __func__);
1071 } 1072 }
1072 // No host buffer 1073 /* No host buffer */
1073 if (Isr & SXG_ISR_RMISS) { 1074 if (Isr & SXG_ISR_RMISS) {
1074 // There is a bunch of code in the SLIC driver which 1075 /* There is a bunch of code in the SLIC driver which */
1075 // attempts to process more receive events per DPC 1076 /* attempts to process more receive events per DPC */
1076 // if we start to fall behind. We'll probably 1077 /* if we start to fall behind. We'll probably */
1077 // need to do something similar here, but hold 1078 /* need to do something similar here, but hold */
1078 // off for now. I don't want to make the code more 1079 /* off for now. I don't want to make the code more */
1079 // complicated than strictly needed. 1080 /* complicated than strictly needed. */
1080 adapter->Stats.RcvNoBuffer++; 1081 adapter->Stats.RcvNoBuffer++;
1081 if (adapter->Stats.RcvNoBuffer < 5) { 1082 if (adapter->Stats.RcvNoBuffer < 5) {
1082 DBG_ERROR("%s: SXG_ISR_ERR RMISS!!\n", 1083 DBG_ERROR("%s: SXG_ISR_ERR RMISS!!\n",
1083 __FUNCTION__); 1084 __func__);
1084 } 1085 }
1085 } 1086 }
1086 // Card crash 1087 /* Card crash */
1087 if (Isr & SXG_ISR_DEAD) { 1088 if (Isr & SXG_ISR_DEAD) {
1088 // Set aside the crash info and set the adapter state to RESET 1089 /* Set aside the crash info and set the adapter state to RESET */
1089 adapter->CrashCpu = 1090 adapter->CrashCpu =
1090 (unsigned char)((Isr & SXG_ISR_CPU) >> 1091 (unsigned char)((Isr & SXG_ISR_CPU) >>
1091 SXG_ISR_CPU_SHIFT); 1092 SXG_ISR_CPU_SHIFT);
1092 adapter->CrashLocation = (ushort) (Isr & SXG_ISR_CRASH); 1093 adapter->CrashLocation = (ushort) (Isr & SXG_ISR_CRASH);
1093 adapter->Dead = TRUE; 1094 adapter->Dead = TRUE;
1094 DBG_ERROR("%s: ISR_DEAD %x, CPU: %d\n", __FUNCTION__, 1095 DBG_ERROR("%s: ISR_DEAD %x, CPU: %d\n", __func__,
1095 adapter->CrashLocation, adapter->CrashCpu); 1096 adapter->CrashLocation, adapter->CrashCpu);
1096 } 1097 }
1097 // Event ring full 1098 /* Event ring full */
1098 if (Isr & SXG_ISR_ERFULL) { 1099 if (Isr & SXG_ISR_ERFULL) {
1099 // Same issue as RMISS, really. This means the 1100 /* Same issue as RMISS, really. This means the */
1100 // host is falling behind the card. Need to increase 1101 /* host is falling behind the card. Need to increase */
1101 // event ring size, process more events per interrupt, 1102 /* event ring size, process more events per interrupt, */
1102 // and/or reduce/remove interrupt aggregation. 1103 /* and/or reduce/remove interrupt aggregation. */
1103 adapter->Stats.EventRingFull++; 1104 adapter->Stats.EventRingFull++;
1104 DBG_ERROR("%s: SXG_ISR_ERR EVENT RING FULL!!\n", 1105 DBG_ERROR("%s: SXG_ISR_ERR EVENT RING FULL!!\n",
1105 __FUNCTION__); 1106 __func__);
1106 } 1107 }
1107 // Transmit drop - no DRAM buffers or XMT error 1108 /* Transmit drop - no DRAM buffers or XMT error */
1108 if (Isr & SXG_ISR_XDROP) { 1109 if (Isr & SXG_ISR_XDROP) {
1109 adapter->Stats.XmtDrops++; 1110 adapter->Stats.XmtDrops++;
1110 adapter->Stats.XmtErrors++; 1111 adapter->Stats.XmtErrors++;
1111 DBG_ERROR("%s: SXG_ISR_ERR XDROP!!\n", __FUNCTION__); 1112 DBG_ERROR("%s: SXG_ISR_ERR XDROP!!\n", __func__);
1112 } 1113 }
1113 } 1114 }
1114 // Slowpath send completions 1115 /* Slowpath send completions */
1115 if (Isr & SXG_ISR_SPSEND) { 1116 if (Isr & SXG_ISR_SPSEND) {
1116 sxg_complete_slow_send(adapter); 1117 sxg_complete_slow_send(adapter);
1117 } 1118 }
1118 // Dump 1119 /* Dump */
1119 if (Isr & SXG_ISR_UPC) { 1120 if (Isr & SXG_ISR_UPC) {
1120 ASSERT(adapter->DumpCmdRunning); // Maybe change when debug is added.. 1121 ASSERT(adapter->DumpCmdRunning); /* Maybe change when debug is added.. */
1121 adapter->DumpCmdRunning = FALSE; 1122 adapter->DumpCmdRunning = FALSE;
1122 } 1123 }
1123 // Link event 1124 /* Link event */
1124 if (Isr & SXG_ISR_LINK) { 1125 if (Isr & SXG_ISR_LINK) {
1125 sxg_link_event(adapter); 1126 sxg_link_event(adapter);
1126 } 1127 }
1127 // Debug - breakpoint hit 1128 /* Debug - breakpoint hit */
1128 if (Isr & SXG_ISR_BREAK) { 1129 if (Isr & SXG_ISR_BREAK) {
1129 // At the moment AGDB isn't written to support interactive 1130 /* At the moment AGDB isn't written to support interactive */
1130 // debug sessions. When it is, this interrupt will be used 1131 /* debug sessions. When it is, this interrupt will be used */
1131 // to signal AGDB that it has hit a breakpoint. For now, ASSERT. 1132 /* to signal AGDB that it has hit a breakpoint. For now, ASSERT. */
1132 ASSERT(0); 1133 ASSERT(0);
1133 } 1134 }
1134 // Heartbeat response 1135 /* Heartbeat response */
1135 if (Isr & SXG_ISR_PING) { 1136 if (Isr & SXG_ISR_PING) {
1136 adapter->PingOutstanding = FALSE; 1137 adapter->PingOutstanding = FALSE;
1137 } 1138 }
@@ -1171,39 +1172,39 @@ static u32 sxg_process_event_queue(p_adapter_t adapter, u32 RssId)
1171 (adapter->State == SXG_STATE_PAUSING) || 1172 (adapter->State == SXG_STATE_PAUSING) ||
1172 (adapter->State == SXG_STATE_PAUSED) || 1173 (adapter->State == SXG_STATE_PAUSED) ||
1173 (adapter->State == SXG_STATE_HALTING)); 1174 (adapter->State == SXG_STATE_HALTING));
1174 // We may still have unprocessed events on the queue if 1175 /* We may still have unprocessed events on the queue if */
1175 // the card crashed. Don't process them. 1176 /* the card crashed. Don't process them. */
1176 if (adapter->Dead) { 1177 if (adapter->Dead) {
1177 return (0); 1178 return (0);
1178 } 1179 }
1179 // In theory there should only be a single processor that 1180 /* In theory there should only be a single processor that */
1180 // accesses this queue, and only at interrupt-DPC time. So 1181 /* accesses this queue, and only at interrupt-DPC time. So */
1181 // we shouldn't need a lock for any of this. 1182 /* we shouldn't need a lock for any of this. */
1182 while (Event->Status & EVENT_STATUS_VALID) { 1183 while (Event->Status & EVENT_STATUS_VALID) {
1183 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "Event", 1184 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "Event",
1184 Event, Event->Code, Event->Status, 1185 Event, Event->Code, Event->Status,
1185 adapter->NextEvent); 1186 adapter->NextEvent);
1186 switch (Event->Code) { 1187 switch (Event->Code) {
1187 case EVENT_CODE_BUFFERS: 1188 case EVENT_CODE_BUFFERS:
1188 ASSERT(!(Event->CommandIndex & 0xFF00)); // SXG_RING_INFO Head & Tail == unsigned char 1189 ASSERT(!(Event->CommandIndex & 0xFF00)); /* SXG_RING_INFO Head & Tail == unsigned char */
1189 // 1190 /* */
1190 sxg_complete_descriptor_blocks(adapter, 1191 sxg_complete_descriptor_blocks(adapter,
1191 Event->CommandIndex); 1192 Event->CommandIndex);
1192 // 1193 /* */
1193 break; 1194 break;
1194 case EVENT_CODE_SLOWRCV: 1195 case EVENT_CODE_SLOWRCV:
1195 --adapter->RcvBuffersOnCard; 1196 --adapter->RcvBuffersOnCard;
1196 if ((skb = sxg_slow_receive(adapter, Event))) { 1197 if ((skb = sxg_slow_receive(adapter, Event))) {
1197 u32 rx_bytes; 1198 u32 rx_bytes;
1198#ifdef LINUX_HANDLES_RCV_INDICATION_LISTS 1199#ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
1199 // Add it to our indication list 1200 /* Add it to our indication list */
1200 SXG_ADD_RCV_PACKET(adapter, skb, prev_skb, 1201 SXG_ADD_RCV_PACKET(adapter, skb, prev_skb,
1201 IndicationList, num_skbs); 1202 IndicationList, num_skbs);
1202 // In Linux, we just pass up each skb to the protocol above at this point, 1203 /* In Linux, we just pass up each skb to the protocol above at this point, */
1203 // there is no capability of an indication list. 1204 /* there is no capability of an indication list. */
1204#else 1205#else
1205// CHECK skb_pull(skb, INIC_RCVBUF_HEADSIZE); 1206/* CHECK skb_pull(skb, INIC_RCVBUF_HEADSIZE); */
1206 rx_bytes = Event->Length; // (rcvbuf->length & IRHDDR_FLEN_MSK); 1207 rx_bytes = Event->Length; /* (rcvbuf->length & IRHDDR_FLEN_MSK); */
1207 skb_put(skb, rx_bytes); 1208 skb_put(skb, rx_bytes);
1208 adapter->stats.rx_packets++; 1209 adapter->stats.rx_packets++;
1209 adapter->stats.rx_bytes += rx_bytes; 1210 adapter->stats.rx_bytes += rx_bytes;
@@ -1218,43 +1219,43 @@ static u32 sxg_process_event_queue(p_adapter_t adapter, u32 RssId)
1218 break; 1219 break;
1219 default: 1220 default:
1220 DBG_ERROR("%s: ERROR Invalid EventCode %d\n", 1221 DBG_ERROR("%s: ERROR Invalid EventCode %d\n",
1221 __FUNCTION__, Event->Code); 1222 __func__, Event->Code);
1222// ASSERT(0); 1223/* ASSERT(0); */
1223 } 1224 }
1224 // See if we need to restock card receive buffers. 1225 /* See if we need to restock card receive buffers. */
1225 // There are two things to note here: 1226 /* There are two things to note here: */
1226 // First - This test is not SMP safe. The 1227 /* First - This test is not SMP safe. The */
1227 // adapter->BuffersOnCard field is protected via atomic interlocked calls, but 1228 /* adapter->BuffersOnCard field is protected via atomic interlocked calls, but */
1228 // we do not protect it with respect to these tests. The only way to do that 1229 /* we do not protect it with respect to these tests. The only way to do that */
1229 // is with a lock, and I don't want to grab a lock every time we adjust the 1230 /* is with a lock, and I don't want to grab a lock every time we adjust the */
1230 // BuffersOnCard count. Instead, we allow the buffer replenishment to be off 1231 /* BuffersOnCard count. Instead, we allow the buffer replenishment to be off */
1231 // once in a while. The worst that can happen is the card is given one 1232 /* once in a while. The worst that can happen is the card is given one */
1232 // more-or-less descriptor block than the arbitrary value we've chosen. 1233 /* more-or-less descriptor block than the arbitrary value we've chosen. */
1233 // No big deal 1234 /* No big deal */
1234 // In short DO NOT ADD A LOCK HERE, OR WHERE RcvBuffersOnCard is adjusted. 1235 /* In short DO NOT ADD A LOCK HERE, OR WHERE RcvBuffersOnCard is adjusted. */
1235 // Second - We expect this test to rarely evaluate to true. We attempt to 1236 /* Second - We expect this test to rarely evaluate to true. We attempt to */
1236 // refill descriptor blocks as they are returned to us 1237 /* refill descriptor blocks as they are returned to us */
1237 // (sxg_complete_descriptor_blocks), so The only time this should evaluate 1238 /* (sxg_complete_descriptor_blocks), so The only time this should evaluate */
1238 // to true is when sxg_complete_descriptor_blocks failed to allocate 1239 /* to true is when sxg_complete_descriptor_blocks failed to allocate */
1239 // receive buffers. 1240 /* receive buffers. */
1240 if (adapter->RcvBuffersOnCard < SXG_RCV_DATA_BUFFERS) { 1241 if (adapter->RcvBuffersOnCard < SXG_RCV_DATA_BUFFERS) {
1241 sxg_stock_rcv_buffers(adapter); 1242 sxg_stock_rcv_buffers(adapter);
1242 } 1243 }
1243 // It's more efficient to just set this to zero. 1244 /* It's more efficient to just set this to zero. */
1244 // But clearing the top bit saves potential debug info... 1245 /* But clearing the top bit saves potential debug info... */
1245 Event->Status &= ~EVENT_STATUS_VALID; 1246 Event->Status &= ~EVENT_STATUS_VALID;
1246 // Advanct to the next event 1247 /* Advanct to the next event */
1247 SXG_ADVANCE_INDEX(adapter->NextEvent[RssId], EVENT_RING_SIZE); 1248 SXG_ADVANCE_INDEX(adapter->NextEvent[RssId], EVENT_RING_SIZE);
1248 Event = &EventRing->Ring[adapter->NextEvent[RssId]]; 1249 Event = &EventRing->Ring[adapter->NextEvent[RssId]];
1249 EventsProcessed++; 1250 EventsProcessed++;
1250 if (EventsProcessed == EVENT_RING_BATCH) { 1251 if (EventsProcessed == EVENT_RING_BATCH) {
1251 // Release a batch of events back to the card 1252 /* Release a batch of events back to the card */
1252 WRITE_REG(adapter->UcodeRegs[RssId].EventRelease, 1253 WRITE_REG(adapter->UcodeRegs[RssId].EventRelease,
1253 EVENT_RING_BATCH, FALSE); 1254 EVENT_RING_BATCH, FALSE);
1254 EventsProcessed = 0; 1255 EventsProcessed = 0;
1255 // If we've processed our batch limit, break out of the 1256 /* If we've processed our batch limit, break out of the */
1256 // loop and return SXG_ISR_EVENT to arrange for us to 1257 /* loop and return SXG_ISR_EVENT to arrange for us to */
1257 // be called again 1258 /* be called again */
1258 if (Batches++ == EVENT_BATCH_LIMIT) { 1259 if (Batches++ == EVENT_BATCH_LIMIT) {
1259 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, 1260 SXG_TRACE(TRACE_SXG, SxgTraceBuffer,
1260 TRACE_NOISY, "EvtLimit", Batches, 1261 TRACE_NOISY, "EvtLimit", Batches,
@@ -1265,14 +1266,14 @@ static u32 sxg_process_event_queue(p_adapter_t adapter, u32 RssId)
1265 } 1266 }
1266 } 1267 }
1267#ifdef LINUX_HANDLES_RCV_INDICATION_LISTS 1268#ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
1268 // 1269 /* */
1269 // Indicate any received dumb-nic frames 1270 /* Indicate any received dumb-nic frames */
1270 // 1271 /* */
1271 SXG_INDICATE_PACKETS(adapter, IndicationList, num_skbs); 1272 SXG_INDICATE_PACKETS(adapter, IndicationList, num_skbs);
1272#endif 1273#endif
1273 // 1274 /* */
1274 // Release events back to the card. 1275 /* Release events back to the card. */
1275 // 1276 /* */
1276 if (EventsProcessed) { 1277 if (EventsProcessed) {
1277 WRITE_REG(adapter->UcodeRegs[RssId].EventRelease, 1278 WRITE_REG(adapter->UcodeRegs[RssId].EventRelease,
1278 EventsProcessed, FALSE); 1279 EventsProcessed, FALSE);
@@ -1299,43 +1300,43 @@ static void sxg_complete_slow_send(p_adapter_t adapter)
1299 u32 *ContextType; 1300 u32 *ContextType;
1300 PSXG_CMD XmtCmd; 1301 PSXG_CMD XmtCmd;
1301 1302
1302 // NOTE - This lock is dropped and regrabbed in this loop. 1303 /* NOTE - This lock is dropped and regrabbed in this loop. */
1303 // This means two different processors can both be running 1304 /* This means two different processors can both be running */
1304 // through this loop. Be *very* careful. 1305 /* through this loop. Be *very* careful. */
1305 spin_lock(&adapter->XmtZeroLock); 1306 spin_lock(&adapter->XmtZeroLock);
1306 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnds", 1307 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnds",
1307 adapter, XmtRingInfo->Head, XmtRingInfo->Tail, 0); 1308 adapter, XmtRingInfo->Head, XmtRingInfo->Tail, 0);
1308 1309
1309 while (XmtRingInfo->Tail != *adapter->XmtRingZeroIndex) { 1310 while (XmtRingInfo->Tail != *adapter->XmtRingZeroIndex) {
1310 // Locate the current Cmd (ring descriptor entry), and 1311 /* Locate the current Cmd (ring descriptor entry), and */
1311 // associated SGL, and advance the tail 1312 /* associated SGL, and advance the tail */
1312 SXG_RETURN_CMD(XmtRing, XmtRingInfo, XmtCmd, ContextType); 1313 SXG_RETURN_CMD(XmtRing, XmtRingInfo, XmtCmd, ContextType);
1313 ASSERT(ContextType); 1314 ASSERT(ContextType);
1314 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnd", 1315 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnd",
1315 XmtRingInfo->Head, XmtRingInfo->Tail, XmtCmd, 0); 1316 XmtRingInfo->Head, XmtRingInfo->Tail, XmtCmd, 0);
1316 // Clear the SGL field. 1317 /* Clear the SGL field. */
1317 XmtCmd->Sgl = 0; 1318 XmtCmd->Sgl = 0;
1318 1319
1319 switch (*ContextType) { 1320 switch (*ContextType) {
1320 case SXG_SGL_DUMB: 1321 case SXG_SGL_DUMB:
1321 { 1322 {
1322 struct sk_buff *skb; 1323 struct sk_buff *skb;
1323 // Dumb-nic send. Command context is the dumb-nic SGL 1324 /* Dumb-nic send. Command context is the dumb-nic SGL */
1324 skb = (struct sk_buff *)ContextType; 1325 skb = (struct sk_buff *)ContextType;
1325 // Complete the send 1326 /* Complete the send */
1326 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, 1327 SXG_TRACE(TRACE_SXG, SxgTraceBuffer,
1327 TRACE_IMPORTANT, "DmSndCmp", skb, 0, 1328 TRACE_IMPORTANT, "DmSndCmp", skb, 0,
1328 0, 0); 1329 0, 0);
1329 ASSERT(adapter->Stats.XmtQLen); 1330 ASSERT(adapter->Stats.XmtQLen);
1330 adapter->Stats.XmtQLen--; // within XmtZeroLock 1331 adapter->Stats.XmtQLen--; /* within XmtZeroLock */
1331 adapter->Stats.XmtOk++; 1332 adapter->Stats.XmtOk++;
1332 // Now drop the lock and complete the send back to 1333 /* Now drop the lock and complete the send back to */
1333 // Microsoft. We need to drop the lock because 1334 /* Microsoft. We need to drop the lock because */
1334 // Microsoft can come back with a chimney send, which 1335 /* Microsoft can come back with a chimney send, which */
1335 // results in a double trip in SxgTcpOuput 1336 /* results in a double trip in SxgTcpOuput */
1336 spin_unlock(&adapter->XmtZeroLock); 1337 spin_unlock(&adapter->XmtZeroLock);
1337 SXG_COMPLETE_DUMB_SEND(adapter, skb); 1338 SXG_COMPLETE_DUMB_SEND(adapter, skb);
1338 // and reacquire.. 1339 /* and reacquire.. */
1339 spin_lock(&adapter->XmtZeroLock); 1340 spin_lock(&adapter->XmtZeroLock);
1340 } 1341 }
1341 break; 1342 break;
@@ -1371,7 +1372,7 @@ static struct sk_buff *sxg_slow_receive(p_adapter_t adapter, PSXG_EVENT Event)
1371 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "SlowRcv", Event, 1372 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "SlowRcv", Event,
1372 RcvDataBufferHdr, RcvDataBufferHdr->State, 1373 RcvDataBufferHdr, RcvDataBufferHdr->State,
1373 RcvDataBufferHdr->VirtualAddress); 1374 RcvDataBufferHdr->VirtualAddress);
1374 // Drop rcv frames in non-running state 1375 /* Drop rcv frames in non-running state */
1375 switch (adapter->State) { 1376 switch (adapter->State) {
1376 case SXG_STATE_RUNNING: 1377 case SXG_STATE_RUNNING:
1377 break; 1378 break;
@@ -1384,12 +1385,12 @@ static struct sk_buff *sxg_slow_receive(p_adapter_t adapter, PSXG_EVENT Event)
1384 goto drop; 1385 goto drop;
1385 } 1386 }
1386 1387
1387 // Change buffer state to UPSTREAM 1388 /* Change buffer state to UPSTREAM */
1388 RcvDataBufferHdr->State = SXG_BUFFER_UPSTREAM; 1389 RcvDataBufferHdr->State = SXG_BUFFER_UPSTREAM;
1389 if (Event->Status & EVENT_STATUS_RCVERR) { 1390 if (Event->Status & EVENT_STATUS_RCVERR) {
1390 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RcvError", 1391 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RcvError",
1391 Event, Event->Status, Event->HostHandle, 0); 1392 Event, Event->Status, Event->HostHandle, 0);
1392 // XXXTODO - Remove this print later 1393 /* XXXTODO - Remove this print later */
1393 DBG_ERROR("SXG: Receive error %x\n", *(u32 *) 1394 DBG_ERROR("SXG: Receive error %x\n", *(u32 *)
1394 SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr)); 1395 SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr));
1395 sxg_process_rcv_error(adapter, *(u32 *) 1396 sxg_process_rcv_error(adapter, *(u32 *)
@@ -1397,8 +1398,8 @@ static struct sk_buff *sxg_slow_receive(p_adapter_t adapter, PSXG_EVENT Event)
1397 (RcvDataBufferHdr)); 1398 (RcvDataBufferHdr));
1398 goto drop; 1399 goto drop;
1399 } 1400 }
1400#if XXXTODO // VLAN stuff 1401#if XXXTODO /* VLAN stuff */
1401 // If there's a VLAN tag, extract it and validate it 1402 /* If there's a VLAN tag, extract it and validate it */
1402 if (((p_ether_header) (SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr)))-> 1403 if (((p_ether_header) (SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr)))->
1403 EtherType == ETHERTYPE_VLAN) { 1404 EtherType == ETHERTYPE_VLAN) {
1404 if (SxgExtractVlanHeader(adapter, RcvDataBufferHdr, Event) != 1405 if (SxgExtractVlanHeader(adapter, RcvDataBufferHdr, Event) !=
@@ -1411,9 +1412,9 @@ static struct sk_buff *sxg_slow_receive(p_adapter_t adapter, PSXG_EVENT Event)
1411 } 1412 }
1412 } 1413 }
1413#endif 1414#endif
1414 // 1415 /* */
1415 // Dumb-nic frame. See if it passes our mac filter and update stats 1416 /* Dumb-nic frame. See if it passes our mac filter and update stats */
1416 // 1417 /* */
1417 if (!sxg_mac_filter(adapter, (p_ether_header) 1418 if (!sxg_mac_filter(adapter, (p_ether_header)
1418 SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr), 1419 SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr),
1419 Event->Length)) { 1420 Event->Length)) {
@@ -1427,9 +1428,9 @@ static struct sk_buff *sxg_slow_receive(p_adapter_t adapter, PSXG_EVENT Event)
1427 1428
1428 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "DumbRcv", 1429 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "DumbRcv",
1429 RcvDataBufferHdr, Packet, Event->Length, 0); 1430 RcvDataBufferHdr, Packet, Event->Length, 0);
1430 // 1431 /* */
1431 // Lastly adjust the receive packet length. 1432 /* Lastly adjust the receive packet length. */
1432 // 1433 /* */
1433 SXG_ADJUST_RCV_PACKET(Packet, RcvDataBufferHdr, Event); 1434 SXG_ADJUST_RCV_PACKET(Packet, RcvDataBufferHdr, Event);
1434 1435
1435 return (Packet); 1436 return (Packet);
@@ -1541,7 +1542,7 @@ static bool sxg_mac_filter(p_adapter_t adapter, p_ether_header EtherHdr,
1541 1542
1542 if (SXG_MULTICAST_PACKET(EtherHdr)) { 1543 if (SXG_MULTICAST_PACKET(EtherHdr)) {
1543 if (SXG_BROADCAST_PACKET(EtherHdr)) { 1544 if (SXG_BROADCAST_PACKET(EtherHdr)) {
1544 // broadcast 1545 /* broadcast */
1545 if (adapter->MacFilter & MAC_BCAST) { 1546 if (adapter->MacFilter & MAC_BCAST) {
1546 adapter->Stats.DumbRcvBcastPkts++; 1547 adapter->Stats.DumbRcvBcastPkts++;
1547 adapter->Stats.DumbRcvBcastBytes += length; 1548 adapter->Stats.DumbRcvBcastBytes += length;
@@ -1550,7 +1551,7 @@ static bool sxg_mac_filter(p_adapter_t adapter, p_ether_header EtherHdr,
1550 return (TRUE); 1551 return (TRUE);
1551 } 1552 }
1552 } else { 1553 } else {
1553 // multicast 1554 /* multicast */
1554 if (adapter->MacFilter & MAC_ALLMCAST) { 1555 if (adapter->MacFilter & MAC_ALLMCAST) {
1555 adapter->Stats.DumbRcvMcastPkts++; 1556 adapter->Stats.DumbRcvMcastPkts++;
1556 adapter->Stats.DumbRcvMcastBytes += length; 1557 adapter->Stats.DumbRcvMcastBytes += length;
@@ -1580,9 +1581,9 @@ static bool sxg_mac_filter(p_adapter_t adapter, p_ether_header EtherHdr,
1580 } 1581 }
1581 } 1582 }
1582 } else if (adapter->MacFilter & MAC_DIRECTED) { 1583 } else if (adapter->MacFilter & MAC_DIRECTED) {
1583 // Not broadcast or multicast. Must be directed at us or 1584 /* Not broadcast or multicast. Must be directed at us or */
1584 // the card is in promiscuous mode. Either way, consider it 1585 /* the card is in promiscuous mode. Either way, consider it */
1585 // ours if MAC_DIRECTED is set 1586 /* ours if MAC_DIRECTED is set */
1586 adapter->Stats.DumbRcvUcastPkts++; 1587 adapter->Stats.DumbRcvUcastPkts++;
1587 adapter->Stats.DumbRcvUcastBytes += length; 1588 adapter->Stats.DumbRcvUcastBytes += length;
1588 adapter->Stats.DumbRcvPkts++; 1589 adapter->Stats.DumbRcvPkts++;
@@ -1590,7 +1591,7 @@ static bool sxg_mac_filter(p_adapter_t adapter, p_ether_header EtherHdr,
1590 return (TRUE); 1591 return (TRUE);
1591 } 1592 }
1592 if (adapter->MacFilter & MAC_PROMISC) { 1593 if (adapter->MacFilter & MAC_PROMISC) {
1593 // Whatever it is, keep it. 1594 /* Whatever it is, keep it. */
1594 adapter->Stats.DumbRcvPkts++; 1595 adapter->Stats.DumbRcvPkts++;
1595 adapter->Stats.DumbRcvBytes += length; 1596 adapter->Stats.DumbRcvBytes += length;
1596 return (TRUE); 1597 return (TRUE);
@@ -1606,7 +1607,7 @@ static int sxg_register_interrupt(p_adapter_t adapter)
1606 1607
1607 DBG_ERROR 1608 DBG_ERROR
1608 ("sxg: %s AllocAdaptRsrcs adapter[%p] dev->irq[%x] %x\n", 1609 ("sxg: %s AllocAdaptRsrcs adapter[%p] dev->irq[%x] %x\n",
1609 __FUNCTION__, adapter, adapter->netdev->irq, NR_IRQS); 1610 __func__, adapter, adapter->netdev->irq, NR_IRQS);
1610 1611
1611 spin_unlock_irqrestore(&sxg_global.driver_lock, 1612 spin_unlock_irqrestore(&sxg_global.driver_lock,
1612 sxg_global.flags); 1613 sxg_global.flags);
@@ -1625,18 +1626,18 @@ static int sxg_register_interrupt(p_adapter_t adapter)
1625 } 1626 }
1626 adapter->intrregistered = 1; 1627 adapter->intrregistered = 1;
1627 adapter->IntRegistered = TRUE; 1628 adapter->IntRegistered = TRUE;
1628 // Disable RSS with line-based interrupts 1629 /* Disable RSS with line-based interrupts */
1629 adapter->MsiEnabled = FALSE; 1630 adapter->MsiEnabled = FALSE;
1630 adapter->RssEnabled = FALSE; 1631 adapter->RssEnabled = FALSE;
1631 DBG_ERROR("sxg: %s AllocAdaptRsrcs adapter[%p] dev->irq[%x]\n", 1632 DBG_ERROR("sxg: %s AllocAdaptRsrcs adapter[%p] dev->irq[%x]\n",
1632 __FUNCTION__, adapter, adapter->netdev->irq); 1633 __func__, adapter, adapter->netdev->irq);
1633 } 1634 }
1634 return (STATUS_SUCCESS); 1635 return (STATUS_SUCCESS);
1635} 1636}
1636 1637
1637static void sxg_deregister_interrupt(p_adapter_t adapter) 1638static void sxg_deregister_interrupt(p_adapter_t adapter)
1638{ 1639{
1639 DBG_ERROR("sxg: %s ENTER adapter[%p]\n", __FUNCTION__, adapter); 1640 DBG_ERROR("sxg: %s ENTER adapter[%p]\n", __func__, adapter);
1640#if XXXTODO 1641#if XXXTODO
1641 slic_init_cleanup(adapter); 1642 slic_init_cleanup(adapter);
1642#endif 1643#endif
@@ -1651,7 +1652,7 @@ static void sxg_deregister_interrupt(p_adapter_t adapter)
1651 adapter->rcv_broadcasts = 0; 1652 adapter->rcv_broadcasts = 0;
1652 adapter->rcv_multicasts = 0; 1653 adapter->rcv_multicasts = 0;
1653 adapter->rcv_unicasts = 0; 1654 adapter->rcv_unicasts = 0;
1654 DBG_ERROR("sxg: %s EXIT\n", __FUNCTION__); 1655 DBG_ERROR("sxg: %s EXIT\n", __func__);
1655} 1656}
1656 1657
1657/* 1658/*
@@ -1666,7 +1667,7 @@ static int sxg_if_init(p_adapter_t adapter)
1666 int status = 0; 1667 int status = 0;
1667 1668
1668 DBG_ERROR("sxg: %s (%s) ENTER states[%d:%d:%d] flags[%x]\n", 1669 DBG_ERROR("sxg: %s (%s) ENTER states[%d:%d:%d] flags[%x]\n",
1669 __FUNCTION__, adapter->netdev->name, 1670 __func__, adapter->netdev->name,
1670 adapter->queues_initialized, adapter->state, 1671 adapter->queues_initialized, adapter->state,
1671 adapter->linkstate, dev->flags); 1672 adapter->linkstate, dev->flags);
1672 1673
@@ -1680,7 +1681,7 @@ static int sxg_if_init(p_adapter_t adapter)
1680 adapter->devflags_prev = dev->flags; 1681 adapter->devflags_prev = dev->flags;
1681 adapter->macopts = MAC_DIRECTED; 1682 adapter->macopts = MAC_DIRECTED;
1682 if (dev->flags) { 1683 if (dev->flags) {
1683 DBG_ERROR("sxg: %s (%s) Set MAC options: ", __FUNCTION__, 1684 DBG_ERROR("sxg: %s (%s) Set MAC options: ", __func__,
1684 adapter->netdev->name); 1685 adapter->netdev->name);
1685 if (dev->flags & IFF_BROADCAST) { 1686 if (dev->flags & IFF_BROADCAST) {
1686 adapter->macopts |= MAC_BCAST; 1687 adapter->macopts |= MAC_BCAST;
@@ -1713,7 +1714,7 @@ static int sxg_if_init(p_adapter_t adapter)
1713 /* 1714 /*
1714 * clear any pending events, then enable interrupts 1715 * clear any pending events, then enable interrupts
1715 */ 1716 */
1716 DBG_ERROR("sxg: %s ENABLE interrupts(slic)\n", __FUNCTION__); 1717 DBG_ERROR("sxg: %s ENABLE interrupts(slic)\n", __func__);
1717 1718
1718 return (STATUS_SUCCESS); 1719 return (STATUS_SUCCESS);
1719} 1720}
@@ -1724,11 +1725,11 @@ static int sxg_entry_open(p_net_device dev)
1724 int status; 1725 int status;
1725 1726
1726 ASSERT(adapter); 1727 ASSERT(adapter);
1727 DBG_ERROR("sxg: %s adapter->activated[%d]\n", __FUNCTION__, 1728 DBG_ERROR("sxg: %s adapter->activated[%d]\n", __func__,
1728 adapter->activated); 1729 adapter->activated);
1729 DBG_ERROR 1730 DBG_ERROR
1730 ("sxg: %s (%s): [jiffies[%lx] cpu %d] dev[%p] adapt[%p] port[%d]\n", 1731 ("sxg: %s (%s): [jiffies[%lx] cpu %d] dev[%p] adapt[%p] port[%d]\n",
1731 __FUNCTION__, adapter->netdev->name, jiffies, smp_processor_id(), 1732 __func__, adapter->netdev->name, jiffies, smp_processor_id(),
1732 adapter->netdev, adapter, adapter->port); 1733 adapter->netdev, adapter, adapter->port);
1733 1734
1734 netif_stop_queue(adapter->netdev); 1735 netif_stop_queue(adapter->netdev);
@@ -1738,16 +1739,16 @@ static int sxg_entry_open(p_net_device dev)
1738 sxg_global.num_sxg_ports_active++; 1739 sxg_global.num_sxg_ports_active++;
1739 adapter->activated = 1; 1740 adapter->activated = 1;
1740 } 1741 }
1741 // Initialize the adapter 1742 /* Initialize the adapter */
1742 DBG_ERROR("sxg: %s ENTER sxg_initialize_adapter\n", __FUNCTION__); 1743 DBG_ERROR("sxg: %s ENTER sxg_initialize_adapter\n", __func__);
1743 status = sxg_initialize_adapter(adapter); 1744 status = sxg_initialize_adapter(adapter);
1744 DBG_ERROR("sxg: %s EXIT sxg_initialize_adapter status[%x]\n", 1745 DBG_ERROR("sxg: %s EXIT sxg_initialize_adapter status[%x]\n",
1745 __FUNCTION__, status); 1746 __func__, status);
1746 1747
1747 if (status == STATUS_SUCCESS) { 1748 if (status == STATUS_SUCCESS) {
1748 DBG_ERROR("sxg: %s ENTER sxg_if_init\n", __FUNCTION__); 1749 DBG_ERROR("sxg: %s ENTER sxg_if_init\n", __func__);
1749 status = sxg_if_init(adapter); 1750 status = sxg_if_init(adapter);
1750 DBG_ERROR("sxg: %s EXIT sxg_if_init status[%x]\n", __FUNCTION__, 1751 DBG_ERROR("sxg: %s EXIT sxg_if_init status[%x]\n", __func__,
1751 status); 1752 status);
1752 } 1753 }
1753 1754
@@ -1760,12 +1761,12 @@ static int sxg_entry_open(p_net_device dev)
1760 sxg_global.flags); 1761 sxg_global.flags);
1761 return (status); 1762 return (status);
1762 } 1763 }
1763 DBG_ERROR("sxg: %s ENABLE ALL INTERRUPTS\n", __FUNCTION__); 1764 DBG_ERROR("sxg: %s ENABLE ALL INTERRUPTS\n", __func__);
1764 1765
1765 // Enable interrupts 1766 /* Enable interrupts */
1766 SXG_ENABLE_ALL_INTERRUPTS(adapter); 1767 SXG_ENABLE_ALL_INTERRUPTS(adapter);
1767 1768
1768 DBG_ERROR("sxg: %s EXIT\n", __FUNCTION__); 1769 DBG_ERROR("sxg: %s EXIT\n", __func__);
1769 1770
1770 spin_unlock_irqrestore(&sxg_global.driver_lock, sxg_global.flags); 1771 spin_unlock_irqrestore(&sxg_global.driver_lock, sxg_global.flags);
1771 return STATUS_SUCCESS; 1772 return STATUS_SUCCESS;
@@ -1779,27 +1780,27 @@ static void __devexit sxg_entry_remove(struct pci_dev *pcidev)
1779 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev); 1780 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev);
1780 1781
1781 ASSERT(adapter); 1782 ASSERT(adapter);
1782 DBG_ERROR("sxg: %s ENTER dev[%p] adapter[%p]\n", __FUNCTION__, dev, 1783 DBG_ERROR("sxg: %s ENTER dev[%p] adapter[%p]\n", __func__, dev,
1783 adapter); 1784 adapter);
1784 sxg_deregister_interrupt(adapter); 1785 sxg_deregister_interrupt(adapter);
1785 sxg_unmap_mmio_space(adapter); 1786 sxg_unmap_mmio_space(adapter);
1786 DBG_ERROR("sxg: %s unregister_netdev\n", __FUNCTION__); 1787 DBG_ERROR("sxg: %s unregister_netdev\n", __func__);
1787 unregister_netdev(dev); 1788 unregister_netdev(dev);
1788 1789
1789 mmio_start = pci_resource_start(pcidev, 0); 1790 mmio_start = pci_resource_start(pcidev, 0);
1790 mmio_len = pci_resource_len(pcidev, 0); 1791 mmio_len = pci_resource_len(pcidev, 0);
1791 1792
1792 DBG_ERROR("sxg: %s rel_region(0) start[%x] len[%x]\n", __FUNCTION__, 1793 DBG_ERROR("sxg: %s rel_region(0) start[%x] len[%x]\n", __func__,
1793 mmio_start, mmio_len); 1794 mmio_start, mmio_len);
1794 release_mem_region(mmio_start, mmio_len); 1795 release_mem_region(mmio_start, mmio_len);
1795 1796
1796 DBG_ERROR("sxg: %s iounmap dev->base_addr[%x]\n", __FUNCTION__, 1797 DBG_ERROR("sxg: %s iounmap dev->base_addr[%x]\n", __func__,
1797 (unsigned int)dev->base_addr); 1798 (unsigned int)dev->base_addr);
1798 iounmap((char *)dev->base_addr); 1799 iounmap((char *)dev->base_addr);
1799 1800
1800 DBG_ERROR("sxg: %s deallocate device\n", __FUNCTION__); 1801 DBG_ERROR("sxg: %s deallocate device\n", __func__);
1801 kfree(dev); 1802 kfree(dev);
1802 DBG_ERROR("sxg: %s EXIT\n", __FUNCTION__); 1803 DBG_ERROR("sxg: %s EXIT\n", __func__);
1803} 1804}
1804 1805
1805static int sxg_entry_halt(p_net_device dev) 1806static int sxg_entry_halt(p_net_device dev)
@@ -1807,17 +1808,17 @@ static int sxg_entry_halt(p_net_device dev)
1807 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev); 1808 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev);
1808 1809
1809 spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags); 1810 spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags);
1810 DBG_ERROR("sxg: %s (%s) ENTER\n", __FUNCTION__, dev->name); 1811 DBG_ERROR("sxg: %s (%s) ENTER\n", __func__, dev->name);
1811 1812
1812 netif_stop_queue(adapter->netdev); 1813 netif_stop_queue(adapter->netdev);
1813 adapter->state = ADAPT_DOWN; 1814 adapter->state = ADAPT_DOWN;
1814 adapter->linkstate = LINK_DOWN; 1815 adapter->linkstate = LINK_DOWN;
1815 adapter->devflags_prev = 0; 1816 adapter->devflags_prev = 0;
1816 DBG_ERROR("sxg: %s (%s) set adapter[%p] state to ADAPT_DOWN(%d)\n", 1817 DBG_ERROR("sxg: %s (%s) set adapter[%p] state to ADAPT_DOWN(%d)\n",
1817 __FUNCTION__, dev->name, adapter, adapter->state); 1818 __func__, dev->name, adapter, adapter->state);
1818 1819
1819 DBG_ERROR("sxg: %s (%s) EXIT\n", __FUNCTION__, dev->name); 1820 DBG_ERROR("sxg: %s (%s) EXIT\n", __func__, dev->name);
1820 DBG_ERROR("sxg: %s EXIT\n", __FUNCTION__); 1821 DBG_ERROR("sxg: %s EXIT\n", __func__);
1821 spin_unlock_irqrestore(&sxg_global.driver_lock, sxg_global.flags); 1822 spin_unlock_irqrestore(&sxg_global.driver_lock, sxg_global.flags);
1822 return (STATUS_SUCCESS); 1823 return (STATUS_SUCCESS);
1823} 1824}
@@ -1825,11 +1826,11 @@ static int sxg_entry_halt(p_net_device dev)
1825static int sxg_ioctl(p_net_device dev, struct ifreq *rq, int cmd) 1826static int sxg_ioctl(p_net_device dev, struct ifreq *rq, int cmd)
1826{ 1827{
1827 ASSERT(rq); 1828 ASSERT(rq);
1828// DBG_ERROR("sxg: %s cmd[%x] rq[%p] dev[%p]\n", __FUNCTION__, cmd, rq, dev); 1829/* DBG_ERROR("sxg: %s cmd[%x] rq[%p] dev[%p]\n", __func__, cmd, rq, dev); */
1829 switch (cmd) { 1830 switch (cmd) {
1830 case SIOCSLICSETINTAGG: 1831 case SIOCSLICSETINTAGG:
1831 { 1832 {
1832// p_adapter_t adapter = (p_adapter_t) netdev_priv(dev); 1833/* p_adapter_t adapter = (p_adapter_t) netdev_priv(dev); */
1833 u32 data[7]; 1834 u32 data[7];
1834 u32 intagg; 1835 u32 intagg;
1835 1836
@@ -1841,12 +1842,12 @@ static int sxg_ioctl(p_net_device dev, struct ifreq *rq, int cmd)
1841 intagg = data[0]; 1842 intagg = data[0];
1842 printk(KERN_EMERG 1843 printk(KERN_EMERG
1843 "%s: set interrupt aggregation to %d\n", 1844 "%s: set interrupt aggregation to %d\n",
1844 __FUNCTION__, intagg); 1845 __func__, intagg);
1845 return 0; 1846 return 0;
1846 } 1847 }
1847 1848
1848 default: 1849 default:
1849// DBG_ERROR("sxg: %s UNSUPPORTED[%x]\n", __FUNCTION__, cmd); 1850/* DBG_ERROR("sxg: %s UNSUPPORTED[%x]\n", __func__, cmd); */
1850 return -EOPNOTSUPP; 1851 return -EOPNOTSUPP;
1851 } 1852 }
1852 return 0; 1853 return 0;
@@ -1870,15 +1871,15 @@ static int sxg_send_packets(struct sk_buff *skb, p_net_device dev)
1870 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev); 1871 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev);
1871 u32 status = STATUS_SUCCESS; 1872 u32 status = STATUS_SUCCESS;
1872 1873
1873 DBG_ERROR("sxg: %s ENTER sxg_send_packets skb[%p]\n", __FUNCTION__, 1874 DBG_ERROR("sxg: %s ENTER sxg_send_packets skb[%p]\n", __func__,
1874 skb); 1875 skb);
1875 // Check the adapter state 1876 /* Check the adapter state */
1876 switch (adapter->State) { 1877 switch (adapter->State) {
1877 case SXG_STATE_INITIALIZING: 1878 case SXG_STATE_INITIALIZING:
1878 case SXG_STATE_HALTED: 1879 case SXG_STATE_HALTED:
1879 case SXG_STATE_SHUTDOWN: 1880 case SXG_STATE_SHUTDOWN:
1880 ASSERT(0); // unexpected 1881 ASSERT(0); /* unexpected */
1881 // fall through 1882 /* fall through */
1882 case SXG_STATE_RESETTING: 1883 case SXG_STATE_RESETTING:
1883 case SXG_STATE_SLEEP: 1884 case SXG_STATE_SLEEP:
1884 case SXG_STATE_BOOTDIAG: 1885 case SXG_STATE_BOOTDIAG:
@@ -1898,23 +1899,23 @@ static int sxg_send_packets(struct sk_buff *skb, p_net_device dev)
1898 if (status != STATUS_SUCCESS) { 1899 if (status != STATUS_SUCCESS) {
1899 goto xmit_fail; 1900 goto xmit_fail;
1900 } 1901 }
1901 // send a packet 1902 /* send a packet */
1902 status = sxg_transmit_packet(adapter, skb); 1903 status = sxg_transmit_packet(adapter, skb);
1903 if (status == STATUS_SUCCESS) { 1904 if (status == STATUS_SUCCESS) {
1904 goto xmit_done; 1905 goto xmit_done;
1905 } 1906 }
1906 1907
1907 xmit_fail: 1908 xmit_fail:
1908 // reject & complete all the packets if they cant be sent 1909 /* reject & complete all the packets if they cant be sent */
1909 if (status != STATUS_SUCCESS) { 1910 if (status != STATUS_SUCCESS) {
1910#if XXXTODO 1911#if XXXTODO
1911// sxg_send_packets_fail(adapter, skb, status); 1912/* sxg_send_packets_fail(adapter, skb, status); */
1912#else 1913#else
1913 SXG_DROP_DUMB_SEND(adapter, skb); 1914 SXG_DROP_DUMB_SEND(adapter, skb);
1914 adapter->stats.tx_dropped++; 1915 adapter->stats.tx_dropped++;
1915#endif 1916#endif
1916 } 1917 }
1917 DBG_ERROR("sxg: %s EXIT sxg_send_packets status[%x]\n", __FUNCTION__, 1918 DBG_ERROR("sxg: %s EXIT sxg_send_packets status[%x]\n", __func__,
1918 status); 1919 status);
1919 1920
1920 xmit_done: 1921 xmit_done:
@@ -1940,12 +1941,12 @@ static int sxg_transmit_packet(p_adapter_t adapter, struct sk_buff *skb)
1940 void *SglBuffer; 1941 void *SglBuffer;
1941 u32 SglBufferLength; 1942 u32 SglBufferLength;
1942 1943
1943 // The vast majority of work is done in the shared 1944 /* The vast majority of work is done in the shared */
1944 // sxg_dumb_sgl routine. 1945 /* sxg_dumb_sgl routine. */
1945 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbSend", 1946 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbSend",
1946 adapter, skb, 0, 0); 1947 adapter, skb, 0, 0);
1947 1948
1948 // Allocate a SGL buffer 1949 /* Allocate a SGL buffer */
1949 SXG_GET_SGL_BUFFER(adapter, SxgSgl); 1950 SXG_GET_SGL_BUFFER(adapter, SxgSgl);
1950 if (!SxgSgl) { 1951 if (!SxgSgl) {
1951 adapter->Stats.NoSglBuf++; 1952 adapter->Stats.NoSglBuf++;
@@ -1963,9 +1964,9 @@ static int sxg_transmit_packet(p_adapter_t adapter, struct sk_buff *skb)
1963 SxgSgl->DumbPacket = skb; 1964 SxgSgl->DumbPacket = skb;
1964 pSgl = NULL; 1965 pSgl = NULL;
1965 1966
1966 // Call the common sxg_dumb_sgl routine to complete the send. 1967 /* Call the common sxg_dumb_sgl routine to complete the send. */
1967 sxg_dumb_sgl(pSgl, SxgSgl); 1968 sxg_dumb_sgl(pSgl, SxgSgl);
1968 // Return success sxg_dumb_sgl (or something later) will complete it. 1969 /* Return success sxg_dumb_sgl (or something later) will complete it. */
1969 return (STATUS_SUCCESS); 1970 return (STATUS_SUCCESS);
1970} 1971}
1971 1972
@@ -1983,39 +1984,39 @@ static void sxg_dumb_sgl(PSCATTER_GATHER_LIST pSgl, PSXG_SCATTER_GATHER SxgSgl)
1983{ 1984{
1984 p_adapter_t adapter = SxgSgl->adapter; 1985 p_adapter_t adapter = SxgSgl->adapter;
1985 struct sk_buff *skb = SxgSgl->DumbPacket; 1986 struct sk_buff *skb = SxgSgl->DumbPacket;
1986 // For now, all dumb-nic sends go on RSS queue zero 1987 /* For now, all dumb-nic sends go on RSS queue zero */
1987 PSXG_XMT_RING XmtRing = &adapter->XmtRings[0]; 1988 PSXG_XMT_RING XmtRing = &adapter->XmtRings[0];
1988 PSXG_RING_INFO XmtRingInfo = &adapter->XmtRingZeroInfo; 1989 PSXG_RING_INFO XmtRingInfo = &adapter->XmtRingZeroInfo;
1989 PSXG_CMD XmtCmd = NULL; 1990 PSXG_CMD XmtCmd = NULL;
1990// u32 Index = 0; 1991/* u32 Index = 0; */
1991 u32 DataLength = skb->len; 1992 u32 DataLength = skb->len;
1992// unsigned int BufLen; 1993/* unsigned int BufLen; */
1993// u32 SglOffset; 1994/* u32 SglOffset; */
1994 u64 phys_addr; 1995 u64 phys_addr;
1995 1996
1996 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbSgl", 1997 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbSgl",
1997 pSgl, SxgSgl, 0, 0); 1998 pSgl, SxgSgl, 0, 0);
1998 1999
1999 // Set aside a pointer to the sgl 2000 /* Set aside a pointer to the sgl */
2000 SxgSgl->pSgl = pSgl; 2001 SxgSgl->pSgl = pSgl;
2001 2002
2002 // Sanity check that our SGL format is as we expect. 2003 /* Sanity check that our SGL format is as we expect. */
2003 ASSERT(sizeof(SXG_X64_SGE) == sizeof(SCATTER_GATHER_ELEMENT)); 2004 ASSERT(sizeof(SXG_X64_SGE) == sizeof(SCATTER_GATHER_ELEMENT));
2004 // Shouldn't be a vlan tag on this frame 2005 /* Shouldn't be a vlan tag on this frame */
2005 ASSERT(SxgSgl->VlanTag.VlanTci == 0); 2006 ASSERT(SxgSgl->VlanTag.VlanTci == 0);
2006 ASSERT(SxgSgl->VlanTag.VlanTpid == 0); 2007 ASSERT(SxgSgl->VlanTag.VlanTpid == 0);
2007 2008
2008 // From here below we work with the SGL placed in our 2009 /* From here below we work with the SGL placed in our */
2009 // buffer. 2010 /* buffer. */
2010 2011
2011 SxgSgl->Sgl.NumberOfElements = 1; 2012 SxgSgl->Sgl.NumberOfElements = 1;
2012 2013
2013 // Grab the spinlock and acquire a command 2014 /* Grab the spinlock and acquire a command */
2014 spin_lock(&adapter->XmtZeroLock); 2015 spin_lock(&adapter->XmtZeroLock);
2015 SXG_GET_CMD(XmtRing, XmtRingInfo, XmtCmd, SxgSgl); 2016 SXG_GET_CMD(XmtRing, XmtRingInfo, XmtCmd, SxgSgl);
2016 if (XmtCmd == NULL) { 2017 if (XmtCmd == NULL) {
2017 // Call sxg_complete_slow_send to see if we can 2018 /* Call sxg_complete_slow_send to see if we can */
2018 // free up any XmtRingZero entries and then try again 2019 /* free up any XmtRingZero entries and then try again */
2019 spin_unlock(&adapter->XmtZeroLock); 2020 spin_unlock(&adapter->XmtZeroLock);
2020 sxg_complete_slow_send(adapter); 2021 sxg_complete_slow_send(adapter);
2021 spin_lock(&adapter->XmtZeroLock); 2022 spin_lock(&adapter->XmtZeroLock);
@@ -2027,10 +2028,10 @@ static void sxg_dumb_sgl(PSCATTER_GATHER_LIST pSgl, PSXG_SCATTER_GATHER SxgSgl)
2027 } 2028 }
2028 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbCmd", 2029 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbCmd",
2029 XmtCmd, XmtRingInfo->Head, XmtRingInfo->Tail, 0); 2030 XmtCmd, XmtRingInfo->Head, XmtRingInfo->Tail, 0);
2030 // Update stats 2031 /* Update stats */
2031 adapter->Stats.DumbXmtPkts++; 2032 adapter->Stats.DumbXmtPkts++;
2032 adapter->Stats.DumbXmtBytes += DataLength; 2033 adapter->Stats.DumbXmtBytes += DataLength;
2033#if XXXTODO // Stats stuff 2034#if XXXTODO /* Stats stuff */
2034 if (SXG_MULTICAST_PACKET(EtherHdr)) { 2035 if (SXG_MULTICAST_PACKET(EtherHdr)) {
2035 if (SXG_BROADCAST_PACKET(EtherHdr)) { 2036 if (SXG_BROADCAST_PACKET(EtherHdr)) {
2036 adapter->Stats.DumbXmtBcastPkts++; 2037 adapter->Stats.DumbXmtBcastPkts++;
@@ -2044,8 +2045,8 @@ static void sxg_dumb_sgl(PSCATTER_GATHER_LIST pSgl, PSXG_SCATTER_GATHER SxgSgl)
2044 adapter->Stats.DumbXmtUcastBytes += DataLength; 2045 adapter->Stats.DumbXmtUcastBytes += DataLength;
2045 } 2046 }
2046#endif 2047#endif
2047 // Fill in the command 2048 /* Fill in the command */
2048 // Copy out the first SGE to the command and adjust for offset 2049 /* Copy out the first SGE to the command and adjust for offset */
2049 phys_addr = 2050 phys_addr =
2050 pci_map_single(adapter->pcidev, skb->data, skb->len, 2051 pci_map_single(adapter->pcidev, skb->data, skb->len,
2051 PCI_DMA_TODEVICE); 2052 PCI_DMA_TODEVICE);
@@ -2053,54 +2054,54 @@ static void sxg_dumb_sgl(PSCATTER_GATHER_LIST pSgl, PSXG_SCATTER_GATHER SxgSgl)
2053 XmtCmd->Buffer.FirstSgeAddress = XmtCmd->Buffer.FirstSgeAddress << 32; 2054 XmtCmd->Buffer.FirstSgeAddress = XmtCmd->Buffer.FirstSgeAddress << 32;
2054 XmtCmd->Buffer.FirstSgeAddress = 2055 XmtCmd->Buffer.FirstSgeAddress =
2055 XmtCmd->Buffer.FirstSgeAddress | SXG_GET_ADDR_LOW(phys_addr); 2056 XmtCmd->Buffer.FirstSgeAddress | SXG_GET_ADDR_LOW(phys_addr);
2056// XmtCmd->Buffer.FirstSgeAddress = SxgSgl->Sgl.Elements[Index].Address; 2057/* XmtCmd->Buffer.FirstSgeAddress = SxgSgl->Sgl.Elements[Index].Address; */
2057// XmtCmd->Buffer.FirstSgeAddress.LowPart += MdlOffset; 2058/* XmtCmd->Buffer.FirstSgeAddress.LowPart += MdlOffset; */
2058 XmtCmd->Buffer.FirstSgeLength = DataLength; 2059 XmtCmd->Buffer.FirstSgeLength = DataLength;
2059 // Set a pointer to the remaining SGL entries 2060 /* Set a pointer to the remaining SGL entries */
2060// XmtCmd->Sgl = SxgSgl->PhysicalAddress; 2061/* XmtCmd->Sgl = SxgSgl->PhysicalAddress; */
2061 // Advance the physical address of the SxgSgl structure to 2062 /* Advance the physical address of the SxgSgl structure to */
2062 // the second SGE 2063 /* the second SGE */
2063// SglOffset = (u32)((u32 *)(&SxgSgl->Sgl.Elements[Index+1]) - 2064/* SglOffset = (u32)((u32 *)(&SxgSgl->Sgl.Elements[Index+1]) - */
2064// (u32 *)SxgSgl); 2065/* (u32 *)SxgSgl); */
2065// XmtCmd->Sgl.LowPart += SglOffset; 2066/* XmtCmd->Sgl.LowPart += SglOffset; */
2066 XmtCmd->Buffer.SgeOffset = 0; 2067 XmtCmd->Buffer.SgeOffset = 0;
2067 // Note - TotalLength might be overwritten with MSS below.. 2068 /* Note - TotalLength might be overwritten with MSS below.. */
2068 XmtCmd->Buffer.TotalLength = DataLength; 2069 XmtCmd->Buffer.TotalLength = DataLength;
2069 XmtCmd->SgEntries = 1; //(ushort)(SxgSgl->Sgl.NumberOfElements - Index); 2070 XmtCmd->SgEntries = 1; /*(ushort)(SxgSgl->Sgl.NumberOfElements - Index); */
2070 XmtCmd->Flags = 0; 2071 XmtCmd->Flags = 0;
2071 // 2072 /* */
2072 // Advance transmit cmd descripter by 1. 2073 /* Advance transmit cmd descripter by 1. */
2073 // NOTE - See comments in SxgTcpOutput where we write 2074 /* NOTE - See comments in SxgTcpOutput where we write */
2074 // to the XmtCmd register regarding CPU ID values and/or 2075 /* to the XmtCmd register regarding CPU ID values and/or */
2075 // multiple commands. 2076 /* multiple commands. */
2076 // 2077 /* */
2077 // 2078 /* */
2078 WRITE_REG(adapter->UcodeRegs[0].XmtCmd, 1, TRUE); 2079 WRITE_REG(adapter->UcodeRegs[0].XmtCmd, 1, TRUE);
2079 // 2080 /* */
2080 // 2081 /* */
2081 adapter->Stats.XmtQLen++; // Stats within lock 2082 adapter->Stats.XmtQLen++; /* Stats within lock */
2082 spin_unlock(&adapter->XmtZeroLock); 2083 spin_unlock(&adapter->XmtZeroLock);
2083 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDumSgl2", 2084 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDumSgl2",
2084 XmtCmd, pSgl, SxgSgl, 0); 2085 XmtCmd, pSgl, SxgSgl, 0);
2085 return; 2086 return;
2086 2087
2087 abortcmd: 2088 abortcmd:
2088 // NOTE - Only jump to this label AFTER grabbing the 2089 /* NOTE - Only jump to this label AFTER grabbing the */
2089 // XmtZeroLock, and DO NOT DROP IT between the 2090 /* XmtZeroLock, and DO NOT DROP IT between the */
2090 // command allocation and the following abort. 2091 /* command allocation and the following abort. */
2091 if (XmtCmd) { 2092 if (XmtCmd) {
2092 SXG_ABORT_CMD(XmtRingInfo); 2093 SXG_ABORT_CMD(XmtRingInfo);
2093 } 2094 }
2094 spin_unlock(&adapter->XmtZeroLock); 2095 spin_unlock(&adapter->XmtZeroLock);
2095 2096
2096// failsgl: 2097/* failsgl: */
2097 // Jump to this label if failure occurs before the 2098 /* Jump to this label if failure occurs before the */
2098 // XmtZeroLock is grabbed 2099 /* XmtZeroLock is grabbed */
2099 adapter->Stats.XmtErrors++; 2100 adapter->Stats.XmtErrors++;
2100 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "DumSGFal", 2101 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "DumSGFal",
2101 pSgl, SxgSgl, XmtRingInfo->Head, XmtRingInfo->Tail); 2102 pSgl, SxgSgl, XmtRingInfo->Head, XmtRingInfo->Tail);
2102 2103
2103 SXG_COMPLETE_DUMB_SEND(adapter, SxgSgl->DumbPacket); // SxgSgl->DumbPacket is the skb 2104 SXG_COMPLETE_DUMB_SEND(adapter, SxgSgl->DumbPacket); /* SxgSgl->DumbPacket is the skb */
2104} 2105}
2105 2106
2106/*************************************************************** 2107/***************************************************************
@@ -2127,122 +2128,122 @@ static int sxg_initialize_link(p_adapter_t adapter)
2127 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "InitLink", 2128 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "InitLink",
2128 adapter, 0, 0, 0); 2129 adapter, 0, 0, 0);
2129 2130
2130 // Reset PHY and XGXS module 2131 /* Reset PHY and XGXS module */
2131 WRITE_REG(HwRegs->LinkStatus, LS_SERDES_POWER_DOWN, TRUE); 2132 WRITE_REG(HwRegs->LinkStatus, LS_SERDES_POWER_DOWN, TRUE);
2132 2133
2133 // Reset transmit configuration register 2134 /* Reset transmit configuration register */
2134 WRITE_REG(HwRegs->XmtConfig, XMT_CONFIG_RESET, TRUE); 2135 WRITE_REG(HwRegs->XmtConfig, XMT_CONFIG_RESET, TRUE);
2135 2136
2136 // Reset receive configuration register 2137 /* Reset receive configuration register */
2137 WRITE_REG(HwRegs->RcvConfig, RCV_CONFIG_RESET, TRUE); 2138 WRITE_REG(HwRegs->RcvConfig, RCV_CONFIG_RESET, TRUE);
2138 2139
2139 // Reset all MAC modules 2140 /* Reset all MAC modules */
2140 WRITE_REG(HwRegs->MacConfig0, AXGMAC_CFG0_SUB_RESET, TRUE); 2141 WRITE_REG(HwRegs->MacConfig0, AXGMAC_CFG0_SUB_RESET, TRUE);
2141 2142
2142 // Link address 0 2143 /* Link address 0 */
2143 // XXXTODO - This assumes the MAC address (0a:0b:0c:0d:0e:0f) 2144 /* XXXTODO - This assumes the MAC address (0a:0b:0c:0d:0e:0f) */
2144 // is stored with the first nibble (0a) in the byte 0 2145 /* is stored with the first nibble (0a) in the byte 0 */
2145 // of the Mac address. Possibly reverse? 2146 /* of the Mac address. Possibly reverse? */
2146 Value = *(u32 *) adapter->MacAddr; 2147 Value = *(u32 *) adapter->MacAddr;
2147 WRITE_REG(HwRegs->LinkAddress0Low, Value, TRUE); 2148 WRITE_REG(HwRegs->LinkAddress0Low, Value, TRUE);
2148 // also write the MAC address to the MAC. Endian is reversed. 2149 /* also write the MAC address to the MAC. Endian is reversed. */
2149 WRITE_REG(HwRegs->MacAddressLow, ntohl(Value), TRUE); 2150 WRITE_REG(HwRegs->MacAddressLow, ntohl(Value), TRUE);
2150 Value = (*(u16 *) & adapter->MacAddr[4] & 0x0000FFFF); 2151 Value = (*(u16 *) & adapter->MacAddr[4] & 0x0000FFFF);
2151 WRITE_REG(HwRegs->LinkAddress0High, Value | LINK_ADDRESS_ENABLE, TRUE); 2152 WRITE_REG(HwRegs->LinkAddress0High, Value | LINK_ADDRESS_ENABLE, TRUE);
2152 // endian swap for the MAC (put high bytes in bits [31:16], swapped) 2153 /* endian swap for the MAC (put high bytes in bits [31:16], swapped) */
2153 Value = ntohl(Value); 2154 Value = ntohl(Value);
2154 WRITE_REG(HwRegs->MacAddressHigh, Value, TRUE); 2155 WRITE_REG(HwRegs->MacAddressHigh, Value, TRUE);
2155 // Link address 1 2156 /* Link address 1 */
2156 WRITE_REG(HwRegs->LinkAddress1Low, 0, TRUE); 2157 WRITE_REG(HwRegs->LinkAddress1Low, 0, TRUE);
2157 WRITE_REG(HwRegs->LinkAddress1High, 0, TRUE); 2158 WRITE_REG(HwRegs->LinkAddress1High, 0, TRUE);
2158 // Link address 2 2159 /* Link address 2 */
2159 WRITE_REG(HwRegs->LinkAddress2Low, 0, TRUE); 2160 WRITE_REG(HwRegs->LinkAddress2Low, 0, TRUE);
2160 WRITE_REG(HwRegs->LinkAddress2High, 0, TRUE); 2161 WRITE_REG(HwRegs->LinkAddress2High, 0, TRUE);
2161 // Link address 3 2162 /* Link address 3 */
2162 WRITE_REG(HwRegs->LinkAddress3Low, 0, TRUE); 2163 WRITE_REG(HwRegs->LinkAddress3Low, 0, TRUE);
2163 WRITE_REG(HwRegs->LinkAddress3High, 0, TRUE); 2164 WRITE_REG(HwRegs->LinkAddress3High, 0, TRUE);
2164 2165
2165 // Enable MAC modules 2166 /* Enable MAC modules */
2166 WRITE_REG(HwRegs->MacConfig0, 0, TRUE); 2167 WRITE_REG(HwRegs->MacConfig0, 0, TRUE);
2167 2168
2168 // Configure MAC 2169 /* Configure MAC */
2169 WRITE_REG(HwRegs->MacConfig1, (AXGMAC_CFG1_XMT_PAUSE | // Allow sending of pause 2170 WRITE_REG(HwRegs->MacConfig1, (AXGMAC_CFG1_XMT_PAUSE | /* Allow sending of pause */
2170 AXGMAC_CFG1_XMT_EN | // Enable XMT 2171 AXGMAC_CFG1_XMT_EN | /* Enable XMT */
2171 AXGMAC_CFG1_RCV_PAUSE | // Enable detection of pause 2172 AXGMAC_CFG1_RCV_PAUSE | /* Enable detection of pause */
2172 AXGMAC_CFG1_RCV_EN | // Enable receive 2173 AXGMAC_CFG1_RCV_EN | /* Enable receive */
2173 AXGMAC_CFG1_SHORT_ASSERT | // short frame detection 2174 AXGMAC_CFG1_SHORT_ASSERT | /* short frame detection */
2174 AXGMAC_CFG1_CHECK_LEN | // Verify frame length 2175 AXGMAC_CFG1_CHECK_LEN | /* Verify frame length */
2175 AXGMAC_CFG1_GEN_FCS | // Generate FCS 2176 AXGMAC_CFG1_GEN_FCS | /* Generate FCS */
2176 AXGMAC_CFG1_PAD_64), // Pad frames to 64 bytes 2177 AXGMAC_CFG1_PAD_64), /* Pad frames to 64 bytes */
2177 TRUE); 2178 TRUE);
2178 2179
2179 // Set AXGMAC max frame length if jumbo. Not needed for standard MTU 2180 /* Set AXGMAC max frame length if jumbo. Not needed for standard MTU */
2180 if (adapter->JumboEnabled) { 2181 if (adapter->JumboEnabled) {
2181 WRITE_REG(HwRegs->MacMaxFrameLen, AXGMAC_MAXFRAME_JUMBO, TRUE); 2182 WRITE_REG(HwRegs->MacMaxFrameLen, AXGMAC_MAXFRAME_JUMBO, TRUE);
2182 } 2183 }
2183 // AMIIM Configuration Register - 2184 /* AMIIM Configuration Register - */
2184 // The value placed in the AXGMAC_AMIIM_CFG_HALF_CLOCK portion 2185 /* The value placed in the AXGMAC_AMIIM_CFG_HALF_CLOCK portion */
2185 // (bottom bits) of this register is used to determine the 2186 /* (bottom bits) of this register is used to determine the */
2186 // MDC frequency as specified in the A-XGMAC Design Document. 2187 /* MDC frequency as specified in the A-XGMAC Design Document. */
2187 // This value must not be zero. The following value (62 or 0x3E) 2188 /* This value must not be zero. The following value (62 or 0x3E) */
2188 // is based on our MAC transmit clock frequency (MTCLK) of 312.5 MHz. 2189 /* is based on our MAC transmit clock frequency (MTCLK) of 312.5 MHz. */
2189 // Given a maximum MDIO clock frequency of 2.5 MHz (see the PHY spec), 2190 /* Given a maximum MDIO clock frequency of 2.5 MHz (see the PHY spec), */
2190 // we get: 312.5/(2*(X+1)) < 2.5 ==> X = 62. 2191 /* we get: 312.5/(2*(X+1)) < 2.5 ==> X = 62. */
2191 // This value happens to be the default value for this register, 2192 /* This value happens to be the default value for this register, */
2192 // so we really don't have to do this. 2193 /* so we really don't have to do this. */
2193 WRITE_REG(HwRegs->MacAmiimConfig, 0x0000003E, TRUE); 2194 WRITE_REG(HwRegs->MacAmiimConfig, 0x0000003E, TRUE);
2194 2195
2195 // Power up and enable PHY and XAUI/XGXS/Serdes logic 2196 /* Power up and enable PHY and XAUI/XGXS/Serdes logic */
2196 WRITE_REG(HwRegs->LinkStatus, 2197 WRITE_REG(HwRegs->LinkStatus,
2197 (LS_PHY_CLR_RESET | 2198 (LS_PHY_CLR_RESET |
2198 LS_XGXS_ENABLE | 2199 LS_XGXS_ENABLE |
2199 LS_XGXS_CTL | LS_PHY_CLK_EN | LS_ATTN_ALARM), TRUE); 2200 LS_XGXS_CTL | LS_PHY_CLK_EN | LS_ATTN_ALARM), TRUE);
2200 DBG_ERROR("After Power Up and enable PHY in sxg_initialize_link\n"); 2201 DBG_ERROR("After Power Up and enable PHY in sxg_initialize_link\n");
2201 2202
2202 // Per information given by Aeluros, wait 100 ms after removing reset. 2203 /* Per information given by Aeluros, wait 100 ms after removing reset. */
2203 // It's not enough to wait for the self-clearing reset bit in reg 0 to clear. 2204 /* It's not enough to wait for the self-clearing reset bit in reg 0 to clear. */
2204 mdelay(100); 2205 mdelay(100);
2205 2206
2206 // Verify the PHY has come up by checking that the Reset bit has cleared. 2207 /* Verify the PHY has come up by checking that the Reset bit has cleared. */
2207 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, // PHY PMA/PMD module 2208 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
2208 PHY_PMA_CONTROL1, // PMA/PMD control register 2209 PHY_PMA_CONTROL1, /* PMA/PMD control register */
2209 &Value); 2210 &Value);
2210 if (status != STATUS_SUCCESS) 2211 if (status != STATUS_SUCCESS)
2211 return (STATUS_FAILURE); 2212 return (STATUS_FAILURE);
2212 if (Value & PMA_CONTROL1_RESET) // reset complete if bit is 0 2213 if (Value & PMA_CONTROL1_RESET) /* reset complete if bit is 0 */
2213 return (STATUS_FAILURE); 2214 return (STATUS_FAILURE);
2214 2215
2215 // The SERDES should be initialized by now - confirm 2216 /* The SERDES should be initialized by now - confirm */
2216 READ_REG(HwRegs->LinkStatus, Value); 2217 READ_REG(HwRegs->LinkStatus, Value);
2217 if (Value & LS_SERDES_DOWN) // verify SERDES is initialized 2218 if (Value & LS_SERDES_DOWN) /* verify SERDES is initialized */
2218 return (STATUS_FAILURE); 2219 return (STATUS_FAILURE);
2219 2220
2220 // The XAUI link should also be up - confirm 2221 /* The XAUI link should also be up - confirm */
2221 if (!(Value & LS_XAUI_LINK_UP)) // verify XAUI link is up 2222 if (!(Value & LS_XAUI_LINK_UP)) /* verify XAUI link is up */
2222 return (STATUS_FAILURE); 2223 return (STATUS_FAILURE);
2223 2224
2224 // Initialize the PHY 2225 /* Initialize the PHY */
2225 status = sxg_phy_init(adapter); 2226 status = sxg_phy_init(adapter);
2226 if (status != STATUS_SUCCESS) 2227 if (status != STATUS_SUCCESS)
2227 return (STATUS_FAILURE); 2228 return (STATUS_FAILURE);
2228 2229
2229 // Enable the Link Alarm 2230 /* Enable the Link Alarm */
2230 status = sxg_write_mdio_reg(adapter, MIIM_DEV_PHY_PMA, // PHY PMA/PMD module 2231 status = sxg_write_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
2231 LASI_CONTROL, // LASI control register 2232 LASI_CONTROL, /* LASI control register */
2232 LASI_CTL_LS_ALARM_ENABLE); // enable link alarm bit 2233 LASI_CTL_LS_ALARM_ENABLE); /* enable link alarm bit */
2233 if (status != STATUS_SUCCESS) 2234 if (status != STATUS_SUCCESS)
2234 return (STATUS_FAILURE); 2235 return (STATUS_FAILURE);
2235 2236
2236 // XXXTODO - temporary - verify bit is set 2237 /* XXXTODO - temporary - verify bit is set */
2237 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, // PHY PMA/PMD module 2238 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
2238 LASI_CONTROL, // LASI control register 2239 LASI_CONTROL, /* LASI control register */
2239 &Value); 2240 &Value);
2240 if (status != STATUS_SUCCESS) 2241 if (status != STATUS_SUCCESS)
2241 return (STATUS_FAILURE); 2242 return (STATUS_FAILURE);
2242 if (!(Value & LASI_CTL_LS_ALARM_ENABLE)) { 2243 if (!(Value & LASI_CTL_LS_ALARM_ENABLE)) {
2243 DBG_ERROR("Error! LASI Control Alarm Enable bit not set!\n"); 2244 DBG_ERROR("Error! LASI Control Alarm Enable bit not set!\n");
2244 } 2245 }
2245 // Enable receive 2246 /* Enable receive */
2246 MaxFrame = adapter->JumboEnabled ? JUMBOMAXFRAME : ETHERMAXFRAME; 2247 MaxFrame = adapter->JumboEnabled ? JUMBOMAXFRAME : ETHERMAXFRAME;
2247 ConfigData = (RCV_CONFIG_ENABLE | 2248 ConfigData = (RCV_CONFIG_ENABLE |
2248 RCV_CONFIG_ENPARSE | 2249 RCV_CONFIG_ENPARSE |
@@ -2256,7 +2257,7 @@ static int sxg_initialize_link(p_adapter_t adapter)
2256 2257
2257 WRITE_REG(HwRegs->XmtConfig, XMT_CONFIG_ENABLE, TRUE); 2258 WRITE_REG(HwRegs->XmtConfig, XMT_CONFIG_ENABLE, TRUE);
2258 2259
2259 // Mark the link as down. We'll get a link event when it comes up. 2260 /* Mark the link as down. We'll get a link event when it comes up. */
2260 sxg_link_state(adapter, SXG_LINK_DOWN); 2261 sxg_link_state(adapter, SXG_LINK_DOWN);
2261 2262
2262 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XInitLnk", 2263 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XInitLnk",
@@ -2279,35 +2280,35 @@ static int sxg_phy_init(p_adapter_t adapter)
2279 PPHY_UCODE p; 2280 PPHY_UCODE p;
2280 int status; 2281 int status;
2281 2282
2282 DBG_ERROR("ENTER %s\n", __FUNCTION__); 2283 DBG_ERROR("ENTER %s\n", __func__);
2283 2284
2284 // Read a register to identify the PHY type 2285 /* Read a register to identify the PHY type */
2285 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, // PHY PMA/PMD module 2286 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
2286 0xC205, // PHY ID register (?) 2287 0xC205, /* PHY ID register (?) */
2287 &Value); // XXXTODO - add def 2288 &Value); /* XXXTODO - add def */
2288 if (status != STATUS_SUCCESS) 2289 if (status != STATUS_SUCCESS)
2289 return (STATUS_FAILURE); 2290 return (STATUS_FAILURE);
2290 2291
2291 if (Value == 0x0012) { // 0x0012 == AEL2005C PHY(?) - XXXTODO - add def 2292 if (Value == 0x0012) { /* 0x0012 == AEL2005C PHY(?) - XXXTODO - add def */
2292 DBG_ERROR 2293 DBG_ERROR
2293 ("AEL2005C PHY detected. Downloading PHY microcode.\n"); 2294 ("AEL2005C PHY detected. Downloading PHY microcode.\n");
2294 2295
2295 // Initialize AEL2005C PHY and download PHY microcode 2296 /* Initialize AEL2005C PHY and download PHY microcode */
2296 for (p = PhyUcode; p->Addr != 0xFFFF; p++) { 2297 for (p = PhyUcode; p->Addr != 0xFFFF; p++) {
2297 if (p->Addr == 0) { 2298 if (p->Addr == 0) {
2298 // if address == 0, data == sleep time in ms 2299 /* if address == 0, data == sleep time in ms */
2299 mdelay(p->Data); 2300 mdelay(p->Data);
2300 } else { 2301 } else {
2301 // write the given data to the specified address 2302 /* write the given data to the specified address */
2302 status = sxg_write_mdio_reg(adapter, MIIM_DEV_PHY_PMA, // PHY PMA/PMD module 2303 status = sxg_write_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
2303 p->Addr, // PHY address 2304 p->Addr, /* PHY address */
2304 p->Data); // PHY data 2305 p->Data); /* PHY data */
2305 if (status != STATUS_SUCCESS) 2306 if (status != STATUS_SUCCESS)
2306 return (STATUS_FAILURE); 2307 return (STATUS_FAILURE);
2307 } 2308 }
2308 } 2309 }
2309 } 2310 }
2310 DBG_ERROR("EXIT %s\n", __FUNCTION__); 2311 DBG_ERROR("EXIT %s\n", __func__);
2311 2312
2312 return (STATUS_SUCCESS); 2313 return (STATUS_SUCCESS);
2313} 2314}
@@ -2330,42 +2331,42 @@ static void sxg_link_event(p_adapter_t adapter)
2330 2331
2331 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "LinkEvnt", 2332 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "LinkEvnt",
2332 adapter, 0, 0, 0); 2333 adapter, 0, 0, 0);
2333 DBG_ERROR("ENTER %s\n", __FUNCTION__); 2334 DBG_ERROR("ENTER %s\n", __func__);
2334 2335
2335 // Check the Link Status register. We should have a Link Alarm. 2336 /* Check the Link Status register. We should have a Link Alarm. */
2336 READ_REG(HwRegs->LinkStatus, Value); 2337 READ_REG(HwRegs->LinkStatus, Value);
2337 if (Value & LS_LINK_ALARM) { 2338 if (Value & LS_LINK_ALARM) {
2338 // We got a Link Status alarm. First, pause to let the 2339 /* We got a Link Status alarm. First, pause to let the */
2339 // link state settle (it can bounce a number of times) 2340 /* link state settle (it can bounce a number of times) */
2340 mdelay(10); 2341 mdelay(10);
2341 2342
2342 // Now clear the alarm by reading the LASI status register. 2343 /* Now clear the alarm by reading the LASI status register. */
2343 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, // PHY PMA/PMD module 2344 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
2344 LASI_STATUS, // LASI status register 2345 LASI_STATUS, /* LASI status register */
2345 &Value); 2346 &Value);
2346 if (status != STATUS_SUCCESS) { 2347 if (status != STATUS_SUCCESS) {
2347 DBG_ERROR("Error reading LASI Status MDIO register!\n"); 2348 DBG_ERROR("Error reading LASI Status MDIO register!\n");
2348 sxg_link_state(adapter, SXG_LINK_DOWN); 2349 sxg_link_state(adapter, SXG_LINK_DOWN);
2349// ASSERT(0); 2350/* ASSERT(0); */
2350 } 2351 }
2351 ASSERT(Value & LASI_STATUS_LS_ALARM); 2352 ASSERT(Value & LASI_STATUS_LS_ALARM);
2352 2353
2353 // Now get and set the link state 2354 /* Now get and set the link state */
2354 LinkState = sxg_get_link_state(adapter); 2355 LinkState = sxg_get_link_state(adapter);
2355 sxg_link_state(adapter, LinkState); 2356 sxg_link_state(adapter, LinkState);
2356 DBG_ERROR("SXG: Link Alarm occurred. Link is %s\n", 2357 DBG_ERROR("SXG: Link Alarm occurred. Link is %s\n",
2357 ((LinkState == SXG_LINK_UP) ? "UP" : "DOWN")); 2358 ((LinkState == SXG_LINK_UP) ? "UP" : "DOWN"));
2358 } else { 2359 } else {
2359 // XXXTODO - Assuming Link Attention is only being generated for the 2360 /* XXXTODO - Assuming Link Attention is only being generated for the */
2360 // Link Alarm pin (and not for a XAUI Link Status change), then it's 2361 /* Link Alarm pin (and not for a XAUI Link Status change), then it's */
2361 // impossible to get here. Yet we've gotten here twice (under extreme 2362 /* impossible to get here. Yet we've gotten here twice (under extreme */
2362 // conditions - bouncing the link up and down many times a second). 2363 /* conditions - bouncing the link up and down many times a second). */
2363 // Needs further investigation. 2364 /* Needs further investigation. */
2364 DBG_ERROR("SXG: sxg_link_event: Can't get here!\n"); 2365 DBG_ERROR("SXG: sxg_link_event: Can't get here!\n");
2365 DBG_ERROR("SXG: Link Status == 0x%08X.\n", Value); 2366 DBG_ERROR("SXG: Link Status == 0x%08X.\n", Value);
2366// ASSERT(0); 2367/* ASSERT(0); */
2367 } 2368 }
2368 DBG_ERROR("EXIT %s\n", __FUNCTION__); 2369 DBG_ERROR("EXIT %s\n", __func__);
2369 2370
2370} 2371}
2371 2372
@@ -2383,50 +2384,50 @@ static SXG_LINK_STATE sxg_get_link_state(p_adapter_t adapter)
2383 int status; 2384 int status;
2384 u32 Value; 2385 u32 Value;
2385 2386
2386 DBG_ERROR("ENTER %s\n", __FUNCTION__); 2387 DBG_ERROR("ENTER %s\n", __func__);
2387 2388
2388 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "GetLink", 2389 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "GetLink",
2389 adapter, 0, 0, 0); 2390 adapter, 0, 0, 0);
2390 2391
2391 // Per the Xenpak spec (and the IEEE 10Gb spec?), the link is up if 2392 /* Per the Xenpak spec (and the IEEE 10Gb spec?), the link is up if */
2392 // the following 3 bits (from 3 different MDIO registers) are all true. 2393 /* the following 3 bits (from 3 different MDIO registers) are all true. */
2393 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, // PHY PMA/PMD module 2394 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
2394 PHY_PMA_RCV_DET, // PMA/PMD Receive Signal Detect register 2395 PHY_PMA_RCV_DET, /* PMA/PMD Receive Signal Detect register */
2395 &Value); 2396 &Value);
2396 if (status != STATUS_SUCCESS) 2397 if (status != STATUS_SUCCESS)
2397 goto bad; 2398 goto bad;
2398 2399
2399 // If PMA/PMD receive signal detect is 0, then the link is down 2400 /* If PMA/PMD receive signal detect is 0, then the link is down */
2400 if (!(Value & PMA_RCV_DETECT)) 2401 if (!(Value & PMA_RCV_DETECT))
2401 return (SXG_LINK_DOWN); 2402 return (SXG_LINK_DOWN);
2402 2403
2403 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PCS, // PHY PCS module 2404 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PCS, /* PHY PCS module */
2404 PHY_PCS_10G_STATUS1, // PCS 10GBASE-R Status 1 register 2405 PHY_PCS_10G_STATUS1, /* PCS 10GBASE-R Status 1 register */
2405 &Value); 2406 &Value);
2406 if (status != STATUS_SUCCESS) 2407 if (status != STATUS_SUCCESS)
2407 goto bad; 2408 goto bad;
2408 2409
2409 // If PCS is not locked to receive blocks, then the link is down 2410 /* If PCS is not locked to receive blocks, then the link is down */
2410 if (!(Value & PCS_10B_BLOCK_LOCK)) 2411 if (!(Value & PCS_10B_BLOCK_LOCK))
2411 return (SXG_LINK_DOWN); 2412 return (SXG_LINK_DOWN);
2412 2413
2413 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_XS, // PHY XS module 2414 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_XS, /* PHY XS module */
2414 PHY_XS_LANE_STATUS, // XS Lane Status register 2415 PHY_XS_LANE_STATUS, /* XS Lane Status register */
2415 &Value); 2416 &Value);
2416 if (status != STATUS_SUCCESS) 2417 if (status != STATUS_SUCCESS)
2417 goto bad; 2418 goto bad;
2418 2419
2419 // If XS transmit lanes are not aligned, then the link is down 2420 /* If XS transmit lanes are not aligned, then the link is down */
2420 if (!(Value & XS_LANE_ALIGN)) 2421 if (!(Value & XS_LANE_ALIGN))
2421 return (SXG_LINK_DOWN); 2422 return (SXG_LINK_DOWN);
2422 2423
2423 // All 3 bits are true, so the link is up 2424 /* All 3 bits are true, so the link is up */
2424 DBG_ERROR("EXIT %s\n", __FUNCTION__); 2425 DBG_ERROR("EXIT %s\n", __func__);
2425 2426
2426 return (SXG_LINK_UP); 2427 return (SXG_LINK_UP);
2427 2428
2428 bad: 2429 bad:
2429 // An error occurred reading an MDIO register. This shouldn't happen. 2430 /* An error occurred reading an MDIO register. This shouldn't happen. */
2430 DBG_ERROR("Error reading an MDIO register!\n"); 2431 DBG_ERROR("Error reading an MDIO register!\n");
2431 ASSERT(0); 2432 ASSERT(0);
2432 return (SXG_LINK_DOWN); 2433 return (SXG_LINK_DOWN);
@@ -2437,11 +2438,11 @@ static void sxg_indicate_link_state(p_adapter_t adapter,
2437{ 2438{
2438 if (adapter->LinkState == SXG_LINK_UP) { 2439 if (adapter->LinkState == SXG_LINK_UP) {
2439 DBG_ERROR("%s: LINK now UP, call netif_start_queue\n", 2440 DBG_ERROR("%s: LINK now UP, call netif_start_queue\n",
2440 __FUNCTION__); 2441 __func__);
2441 netif_start_queue(adapter->netdev); 2442 netif_start_queue(adapter->netdev);
2442 } else { 2443 } else {
2443 DBG_ERROR("%s: LINK now DOWN, call netif_stop_queue\n", 2444 DBG_ERROR("%s: LINK now DOWN, call netif_stop_queue\n",
2444 __FUNCTION__); 2445 __func__);
2445 netif_stop_queue(adapter->netdev); 2446 netif_stop_queue(adapter->netdev);
2446 } 2447 }
2447} 2448}
@@ -2464,23 +2465,23 @@ static void sxg_link_state(p_adapter_t adapter, SXG_LINK_STATE LinkState)
2464 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "LnkINDCT", 2465 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "LnkINDCT",
2465 adapter, LinkState, adapter->LinkState, adapter->State); 2466 adapter, LinkState, adapter->LinkState, adapter->State);
2466 2467
2467 DBG_ERROR("ENTER %s\n", __FUNCTION__); 2468 DBG_ERROR("ENTER %s\n", __func__);
2468 2469
2469 // Hold the adapter lock during this routine. Maybe move 2470 /* Hold the adapter lock during this routine. Maybe move */
2470 // the lock to the caller. 2471 /* the lock to the caller. */
2471 spin_lock(&adapter->AdapterLock); 2472 spin_lock(&adapter->AdapterLock);
2472 if (LinkState == adapter->LinkState) { 2473 if (LinkState == adapter->LinkState) {
2473 // Nothing changed.. 2474 /* Nothing changed.. */
2474 spin_unlock(&adapter->AdapterLock); 2475 spin_unlock(&adapter->AdapterLock);
2475 DBG_ERROR("EXIT #0 %s\n", __FUNCTION__); 2476 DBG_ERROR("EXIT #0 %s\n", __func__);
2476 return; 2477 return;
2477 } 2478 }
2478 // Save the adapter state 2479 /* Save the adapter state */
2479 adapter->LinkState = LinkState; 2480 adapter->LinkState = LinkState;
2480 2481
2481 // Drop the lock and indicate link state 2482 /* Drop the lock and indicate link state */
2482 spin_unlock(&adapter->AdapterLock); 2483 spin_unlock(&adapter->AdapterLock);
2483 DBG_ERROR("EXIT #1 %s\n", __FUNCTION__); 2484 DBG_ERROR("EXIT #1 %s\n", __func__);
2484 2485
2485 sxg_indicate_link_state(adapter, LinkState); 2486 sxg_indicate_link_state(adapter, LinkState);
2486} 2487}
@@ -2501,76 +2502,76 @@ static int sxg_write_mdio_reg(p_adapter_t adapter,
2501 u32 DevAddr, u32 RegAddr, u32 Value) 2502 u32 DevAddr, u32 RegAddr, u32 Value)
2502{ 2503{
2503 PSXG_HW_REGS HwRegs = adapter->HwRegs; 2504 PSXG_HW_REGS HwRegs = adapter->HwRegs;
2504 u32 AddrOp; // Address operation (written to MIIM field reg) 2505 u32 AddrOp; /* Address operation (written to MIIM field reg) */
2505 u32 WriteOp; // Write operation (written to MIIM field reg) 2506 u32 WriteOp; /* Write operation (written to MIIM field reg) */
2506 u32 Cmd; // Command (written to MIIM command reg) 2507 u32 Cmd; /* Command (written to MIIM command reg) */
2507 u32 ValueRead; 2508 u32 ValueRead;
2508 u32 Timeout; 2509 u32 Timeout;
2509 2510
2510// DBG_ERROR("ENTER %s\n", __FUNCTION__); 2511/* DBG_ERROR("ENTER %s\n", __func__); */
2511 2512
2512 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "WrtMDIO", 2513 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "WrtMDIO",
2513 adapter, 0, 0, 0); 2514 adapter, 0, 0, 0);
2514 2515
2515 // Ensure values don't exceed field width 2516 /* Ensure values don't exceed field width */
2516 DevAddr &= 0x001F; // 5-bit field 2517 DevAddr &= 0x001F; /* 5-bit field */
2517 RegAddr &= 0xFFFF; // 16-bit field 2518 RegAddr &= 0xFFFF; /* 16-bit field */
2518 Value &= 0xFFFF; // 16-bit field 2519 Value &= 0xFFFF; /* 16-bit field */
2519 2520
2520 // Set MIIM field register bits for an MIIM address operation 2521 /* Set MIIM field register bits for an MIIM address operation */
2521 AddrOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) | 2522 AddrOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
2522 (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) | 2523 (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
2523 (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) | 2524 (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
2524 (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT) | RegAddr; 2525 (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT) | RegAddr;
2525 2526
2526 // Set MIIM field register bits for an MIIM write operation 2527 /* Set MIIM field register bits for an MIIM write operation */
2527 WriteOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) | 2528 WriteOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
2528 (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) | 2529 (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
2529 (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) | 2530 (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
2530 (MIIM_OP_WRITE << AXGMAC_AMIIM_FIELD_OP_SHIFT) | Value; 2531 (MIIM_OP_WRITE << AXGMAC_AMIIM_FIELD_OP_SHIFT) | Value;
2531 2532
2532 // Set MIIM command register bits to execute an MIIM command 2533 /* Set MIIM command register bits to execute an MIIM command */
2533 Cmd = AXGMAC_AMIIM_CMD_START | AXGMAC_AMIIM_CMD_10G_OPERATION; 2534 Cmd = AXGMAC_AMIIM_CMD_START | AXGMAC_AMIIM_CMD_10G_OPERATION;
2534 2535
2535 // Reset the command register command bit (in case it's not 0) 2536 /* Reset the command register command bit (in case it's not 0) */
2536 WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE); 2537 WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
2537 2538
2538 // MIIM write to set the address of the specified MDIO register 2539 /* MIIM write to set the address of the specified MDIO register */
2539 WRITE_REG(HwRegs->MacAmiimField, AddrOp, TRUE); 2540 WRITE_REG(HwRegs->MacAmiimField, AddrOp, TRUE);
2540 2541
2541 // Write to MIIM Command Register to execute to address operation 2542 /* Write to MIIM Command Register to execute to address operation */
2542 WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE); 2543 WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
2543 2544
2544 // Poll AMIIM Indicator register to wait for completion 2545 /* Poll AMIIM Indicator register to wait for completion */
2545 Timeout = SXG_LINK_TIMEOUT; 2546 Timeout = SXG_LINK_TIMEOUT;
2546 do { 2547 do {
2547 udelay(100); // Timeout in 100us units 2548 udelay(100); /* Timeout in 100us units */
2548 READ_REG(HwRegs->MacAmiimIndicator, ValueRead); 2549 READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
2549 if (--Timeout == 0) { 2550 if (--Timeout == 0) {
2550 return (STATUS_FAILURE); 2551 return (STATUS_FAILURE);
2551 } 2552 }
2552 } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY); 2553 } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
2553 2554
2554 // Reset the command register command bit 2555 /* Reset the command register command bit */
2555 WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE); 2556 WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
2556 2557
2557 // MIIM write to set up an MDIO write operation 2558 /* MIIM write to set up an MDIO write operation */
2558 WRITE_REG(HwRegs->MacAmiimField, WriteOp, TRUE); 2559 WRITE_REG(HwRegs->MacAmiimField, WriteOp, TRUE);
2559 2560
2560 // Write to MIIM Command Register to execute the write operation 2561 /* Write to MIIM Command Register to execute the write operation */
2561 WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE); 2562 WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
2562 2563
2563 // Poll AMIIM Indicator register to wait for completion 2564 /* Poll AMIIM Indicator register to wait for completion */
2564 Timeout = SXG_LINK_TIMEOUT; 2565 Timeout = SXG_LINK_TIMEOUT;
2565 do { 2566 do {
2566 udelay(100); // Timeout in 100us units 2567 udelay(100); /* Timeout in 100us units */
2567 READ_REG(HwRegs->MacAmiimIndicator, ValueRead); 2568 READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
2568 if (--Timeout == 0) { 2569 if (--Timeout == 0) {
2569 return (STATUS_FAILURE); 2570 return (STATUS_FAILURE);
2570 } 2571 }
2571 } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY); 2572 } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
2572 2573
2573// DBG_ERROR("EXIT %s\n", __FUNCTION__); 2574/* DBG_ERROR("EXIT %s\n", __func__); */
2574 2575
2575 return (STATUS_SUCCESS); 2576 return (STATUS_SUCCESS);
2576} 2577}
@@ -2591,110 +2592,78 @@ static int sxg_read_mdio_reg(p_adapter_t adapter,
2591 u32 DevAddr, u32 RegAddr, u32 *pValue) 2592 u32 DevAddr, u32 RegAddr, u32 *pValue)
2592{ 2593{
2593 PSXG_HW_REGS HwRegs = adapter->HwRegs; 2594 PSXG_HW_REGS HwRegs = adapter->HwRegs;
2594 u32 AddrOp; // Address operation (written to MIIM field reg) 2595 u32 AddrOp; /* Address operation (written to MIIM field reg) */
2595 u32 ReadOp; // Read operation (written to MIIM field reg) 2596 u32 ReadOp; /* Read operation (written to MIIM field reg) */
2596 u32 Cmd; // Command (written to MIIM command reg) 2597 u32 Cmd; /* Command (written to MIIM command reg) */
2597 u32 ValueRead; 2598 u32 ValueRead;
2598 u32 Timeout; 2599 u32 Timeout;
2599 2600
2600 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "WrtMDIO", 2601 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "WrtMDIO",
2601 adapter, 0, 0, 0); 2602 adapter, 0, 0, 0);
2602// DBG_ERROR("ENTER %s\n", __FUNCTION__); 2603/* DBG_ERROR("ENTER %s\n", __func__); */
2603 2604
2604 // Ensure values don't exceed field width 2605 /* Ensure values don't exceed field width */
2605 DevAddr &= 0x001F; // 5-bit field 2606 DevAddr &= 0x001F; /* 5-bit field */
2606 RegAddr &= 0xFFFF; // 16-bit field 2607 RegAddr &= 0xFFFF; /* 16-bit field */
2607 2608
2608 // Set MIIM field register bits for an MIIM address operation 2609 /* Set MIIM field register bits for an MIIM address operation */
2609 AddrOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) | 2610 AddrOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
2610 (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) | 2611 (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
2611 (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) | 2612 (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
2612 (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT) | RegAddr; 2613 (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT) | RegAddr;
2613 2614
2614 // Set MIIM field register bits for an MIIM read operation 2615 /* Set MIIM field register bits for an MIIM read operation */
2615 ReadOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) | 2616 ReadOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
2616 (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) | 2617 (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
2617 (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) | 2618 (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
2618 (MIIM_OP_READ << AXGMAC_AMIIM_FIELD_OP_SHIFT); 2619 (MIIM_OP_READ << AXGMAC_AMIIM_FIELD_OP_SHIFT);
2619 2620
2620 // Set MIIM command register bits to execute an MIIM command 2621 /* Set MIIM command register bits to execute an MIIM command */
2621 Cmd = AXGMAC_AMIIM_CMD_START | AXGMAC_AMIIM_CMD_10G_OPERATION; 2622 Cmd = AXGMAC_AMIIM_CMD_START | AXGMAC_AMIIM_CMD_10G_OPERATION;
2622 2623
2623 // Reset the command register command bit (in case it's not 0) 2624 /* Reset the command register command bit (in case it's not 0) */
2624 WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE); 2625 WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
2625 2626
2626 // MIIM write to set the address of the specified MDIO register 2627 /* MIIM write to set the address of the specified MDIO register */
2627 WRITE_REG(HwRegs->MacAmiimField, AddrOp, TRUE); 2628 WRITE_REG(HwRegs->MacAmiimField, AddrOp, TRUE);
2628 2629
2629 // Write to MIIM Command Register to execute to address operation 2630 /* Write to MIIM Command Register to execute to address operation */
2630 WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE); 2631 WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
2631 2632
2632 // Poll AMIIM Indicator register to wait for completion 2633 /* Poll AMIIM Indicator register to wait for completion */
2633 Timeout = SXG_LINK_TIMEOUT; 2634 Timeout = SXG_LINK_TIMEOUT;
2634 do { 2635 do {
2635 udelay(100); // Timeout in 100us units 2636 udelay(100); /* Timeout in 100us units */
2636 READ_REG(HwRegs->MacAmiimIndicator, ValueRead); 2637 READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
2637 if (--Timeout == 0) { 2638 if (--Timeout == 0) {
2638 return (STATUS_FAILURE); 2639 return (STATUS_FAILURE);
2639 } 2640 }
2640 } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY); 2641 } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
2641 2642
2642 // Reset the command register command bit 2643 /* Reset the command register command bit */
2643 WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE); 2644 WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
2644 2645
2645 // MIIM write to set up an MDIO register read operation 2646 /* MIIM write to set up an MDIO register read operation */
2646 WRITE_REG(HwRegs->MacAmiimField, ReadOp, TRUE); 2647 WRITE_REG(HwRegs->MacAmiimField, ReadOp, TRUE);
2647 2648
2648 // Write to MIIM Command Register to execute the read operation 2649 /* Write to MIIM Command Register to execute the read operation */
2649 WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE); 2650 WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
2650 2651
2651 // Poll AMIIM Indicator register to wait for completion 2652 /* Poll AMIIM Indicator register to wait for completion */
2652 Timeout = SXG_LINK_TIMEOUT; 2653 Timeout = SXG_LINK_TIMEOUT;
2653 do { 2654 do {
2654 udelay(100); // Timeout in 100us units 2655 udelay(100); /* Timeout in 100us units */
2655 READ_REG(HwRegs->MacAmiimIndicator, ValueRead); 2656 READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
2656 if (--Timeout == 0) { 2657 if (--Timeout == 0) {
2657 return (STATUS_FAILURE); 2658 return (STATUS_FAILURE);
2658 } 2659 }
2659 } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY); 2660 } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
2660 2661
2661 // Read the MDIO register data back from the field register 2662 /* Read the MDIO register data back from the field register */
2662 READ_REG(HwRegs->MacAmiimField, *pValue); 2663 READ_REG(HwRegs->MacAmiimField, *pValue);
2663 *pValue &= 0xFFFF; // data is in the lower 16 bits 2664 *pValue &= 0xFFFF; /* data is in the lower 16 bits */
2664 2665
2665// DBG_ERROR("EXIT %s\n", __FUNCTION__); 2666/* DBG_ERROR("EXIT %s\n", __func__); */
2666
2667 return (STATUS_SUCCESS);
2668}
2669
2670/*
2671 * Allocate a mcast_address structure to hold the multicast address.
2672 * Link it in.
2673 */
2674static int sxg_mcast_add_list(p_adapter_t adapter, char *address)
2675{
2676 p_mcast_address_t mcaddr, mlist;
2677 bool equaladdr;
2678
2679 /* Check to see if it already exists */
2680 mlist = adapter->mcastaddrs;
2681 while (mlist) {
2682 ETHER_EQ_ADDR(mlist->address, address, equaladdr);
2683 if (equaladdr) {
2684 return (STATUS_SUCCESS);
2685 }
2686 mlist = mlist->next;
2687 }
2688
2689 /* Doesn't already exist. Allocate a structure to hold it */
2690 mcaddr = kmalloc(sizeof(mcast_address_t), GFP_ATOMIC);
2691 if (mcaddr == NULL)
2692 return 1;
2693
2694 memcpy(mcaddr->address, address, 6);
2695
2696 mcaddr->next = adapter->mcastaddrs;
2697 adapter->mcastaddrs = mcaddr;
2698 2667
2699 return (STATUS_SUCCESS); 2668 return (STATUS_SUCCESS);
2700} 2669}
@@ -2710,7 +2679,6 @@ static int sxg_mcast_add_list(p_adapter_t adapter, char *address)
2710 * 2679 *
2711 */ 2680 */
2712static u32 sxg_crc_table[256]; /* Table of CRC's for all possible byte values */ 2681static u32 sxg_crc_table[256]; /* Table of CRC's for all possible byte values */
2713static u32 sxg_crc_init; /* Is table initialized */
2714 2682
2715/* 2683/*
2716 * Contruct the CRC32 table 2684 * Contruct the CRC32 table
@@ -2737,6 +2705,8 @@ static void sxg_mcast_init_crc32(void)
2737 } 2705 }
2738} 2706}
2739 2707
2708#if XXXTODO
2709static u32 sxg_crc_init; /* Is table initialized */
2740/* 2710/*
2741 * Return the MAC hast as described above. 2711 * Return the MAC hast as described above.
2742 */ 2712 */
@@ -2765,6 +2735,74 @@ static unsigned char sxg_mcast_get_mac_hash(char *macaddr)
2765 return (machash); 2735 return (machash);
2766} 2736}
2767 2737
2738static void sxg_mcast_set_mask(p_adapter_t adapter)
2739{
2740 PSXG_UCODE_REGS sxg_regs = adapter->UcodeRegs;
2741
2742 DBG_ERROR("%s ENTER (%s) macopts[%x] mask[%llx]\n", __func__,
2743 adapter->netdev->name, (unsigned int)adapter->MacFilter,
2744 adapter->MulticastMask);
2745
2746 if (adapter->MacFilter & (MAC_ALLMCAST | MAC_PROMISC)) {
2747 /* Turn on all multicast addresses. We have to do this for promiscuous
2748 * mode as well as ALLMCAST mode. It saves the Microcode from having
2749 * to keep state about the MAC configuration.
2750 */
2751/* DBG_ERROR("sxg: %s macopts = MAC_ALLMCAST | MAC_PROMISC\n SLUT MODE!!!\n",__func__); */
2752 WRITE_REG(sxg_regs->McastLow, 0xFFFFFFFF, FLUSH);
2753 WRITE_REG(sxg_regs->McastHigh, 0xFFFFFFFF, FLUSH);
2754/* DBG_ERROR("%s (%s) WRITE to slic_regs slic_mcastlow&high 0xFFFFFFFF\n",__func__, adapter->netdev->name); */
2755
2756 } else {
2757 /* Commit our multicast mast to the SLIC by writing to the multicast
2758 * address mask registers
2759 */
2760 DBG_ERROR("%s (%s) WRITE mcastlow[%lx] mcasthigh[%lx]\n",
2761 __func__, adapter->netdev->name,
2762 ((ulong) (adapter->MulticastMask & 0xFFFFFFFF)),
2763 ((ulong)
2764 ((adapter->MulticastMask >> 32) & 0xFFFFFFFF)));
2765
2766 WRITE_REG(sxg_regs->McastLow,
2767 (u32) (adapter->MulticastMask & 0xFFFFFFFF), FLUSH);
2768 WRITE_REG(sxg_regs->McastHigh,
2769 (u32) ((adapter->
2770 MulticastMask >> 32) & 0xFFFFFFFF), FLUSH);
2771 }
2772}
2773
2774/*
2775 * Allocate a mcast_address structure to hold the multicast address.
2776 * Link it in.
2777 */
2778static int sxg_mcast_add_list(p_adapter_t adapter, char *address)
2779{
2780 p_mcast_address_t mcaddr, mlist;
2781 bool equaladdr;
2782
2783 /* Check to see if it already exists */
2784 mlist = adapter->mcastaddrs;
2785 while (mlist) {
2786 ETHER_EQ_ADDR(mlist->address, address, equaladdr);
2787 if (equaladdr) {
2788 return (STATUS_SUCCESS);
2789 }
2790 mlist = mlist->next;
2791 }
2792
2793 /* Doesn't already exist. Allocate a structure to hold it */
2794 mcaddr = kmalloc(sizeof(mcast_address_t), GFP_ATOMIC);
2795 if (mcaddr == NULL)
2796 return 1;
2797
2798 memcpy(mcaddr->address, address, 6);
2799
2800 mcaddr->next = adapter->mcastaddrs;
2801 adapter->mcastaddrs = mcaddr;
2802
2803 return (STATUS_SUCCESS);
2804}
2805
2768static void sxg_mcast_set_bit(p_adapter_t adapter, char *address) 2806static void sxg_mcast_set_bit(p_adapter_t adapter, char *address)
2769{ 2807{
2770 unsigned char crcpoly; 2808 unsigned char crcpoly;
@@ -2783,7 +2821,6 @@ static void sxg_mcast_set_bit(p_adapter_t adapter, char *address)
2783 2821
2784static void sxg_mcast_set_list(p_net_device dev) 2822static void sxg_mcast_set_list(p_net_device dev)
2785{ 2823{
2786#if XXXTODO
2787 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev); 2824 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev);
2788 int status = STATUS_SUCCESS; 2825 int status = STATUS_SUCCESS;
2789 int i; 2826 int i;
@@ -2809,7 +2846,7 @@ static void sxg_mcast_set_list(p_net_device dev)
2809 } 2846 }
2810 2847
2811 DBG_ERROR("%s a->devflags_prev[%x] dev->flags[%x] status[%x]\n", 2848 DBG_ERROR("%s a->devflags_prev[%x] dev->flags[%x] status[%x]\n",
2812 __FUNCTION__, adapter->devflags_prev, dev->flags, status); 2849 __func__, adapter->devflags_prev, dev->flags, status);
2813 if (adapter->devflags_prev != dev->flags) { 2850 if (adapter->devflags_prev != dev->flags) {
2814 adapter->macopts = MAC_DIRECTED; 2851 adapter->macopts = MAC_DIRECTED;
2815 if (dev->flags) { 2852 if (dev->flags) {
@@ -2828,60 +2865,24 @@ static void sxg_mcast_set_list(p_net_device dev)
2828 } 2865 }
2829 adapter->devflags_prev = dev->flags; 2866 adapter->devflags_prev = dev->flags;
2830 DBG_ERROR("%s call sxg_config_set adapter->macopts[%x]\n", 2867 DBG_ERROR("%s call sxg_config_set adapter->macopts[%x]\n",
2831 __FUNCTION__, adapter->macopts); 2868 __func__, adapter->macopts);
2832 sxg_config_set(adapter, TRUE); 2869 sxg_config_set(adapter, TRUE);
2833 } else { 2870 } else {
2834 if (status == STATUS_SUCCESS) { 2871 if (status == STATUS_SUCCESS) {
2835 sxg_mcast_set_mask(adapter); 2872 sxg_mcast_set_mask(adapter);
2836 } 2873 }
2837 } 2874 }
2838#endif
2839 return; 2875 return;
2840} 2876}
2841 2877#endif
2842static void sxg_mcast_set_mask(p_adapter_t adapter)
2843{
2844 PSXG_UCODE_REGS sxg_regs = adapter->UcodeRegs;
2845
2846 DBG_ERROR("%s ENTER (%s) macopts[%x] mask[%llx]\n", __FUNCTION__,
2847 adapter->netdev->name, (unsigned int)adapter->MacFilter,
2848 adapter->MulticastMask);
2849
2850 if (adapter->MacFilter & (MAC_ALLMCAST | MAC_PROMISC)) {
2851 /* Turn on all multicast addresses. We have to do this for promiscuous
2852 * mode as well as ALLMCAST mode. It saves the Microcode from having
2853 * to keep state about the MAC configuration.
2854 */
2855// DBG_ERROR("sxg: %s macopts = MAC_ALLMCAST | MAC_PROMISC\n SLUT MODE!!!\n",__FUNCTION__);
2856 WRITE_REG(sxg_regs->McastLow, 0xFFFFFFFF, FLUSH);
2857 WRITE_REG(sxg_regs->McastHigh, 0xFFFFFFFF, FLUSH);
2858// DBG_ERROR("%s (%s) WRITE to slic_regs slic_mcastlow&high 0xFFFFFFFF\n",__FUNCTION__, adapter->netdev->name);
2859
2860 } else {
2861 /* Commit our multicast mast to the SLIC by writing to the multicast
2862 * address mask registers
2863 */
2864 DBG_ERROR("%s (%s) WRITE mcastlow[%lx] mcasthigh[%lx]\n",
2865 __FUNCTION__, adapter->netdev->name,
2866 ((ulong) (adapter->MulticastMask & 0xFFFFFFFF)),
2867 ((ulong)
2868 ((adapter->MulticastMask >> 32) & 0xFFFFFFFF)));
2869
2870 WRITE_REG(sxg_regs->McastLow,
2871 (u32) (adapter->MulticastMask & 0xFFFFFFFF), FLUSH);
2872 WRITE_REG(sxg_regs->McastHigh,
2873 (u32) ((adapter->
2874 MulticastMask >> 32) & 0xFFFFFFFF), FLUSH);
2875 }
2876}
2877 2878
2878static void sxg_unmap_mmio_space(p_adapter_t adapter) 2879static void sxg_unmap_mmio_space(p_adapter_t adapter)
2879{ 2880{
2880#if LINUX_FREES_ADAPTER_RESOURCES 2881#if LINUX_FREES_ADAPTER_RESOURCES
2881// if (adapter->Regs) { 2882/* if (adapter->Regs) { */
2882// iounmap(adapter->Regs); 2883/* iounmap(adapter->Regs); */
2883// } 2884/* } */
2884// adapter->slic_regs = NULL; 2885/* adapter->slic_regs = NULL; */
2885#endif 2886#endif
2886} 2887}
2887 2888
@@ -2909,8 +2910,8 @@ void SxgFreeResources(p_adapter_t adapter)
2909 IsrCount = adapter->MsiEnabled ? RssIds : 1; 2910 IsrCount = adapter->MsiEnabled ? RssIds : 1;
2910 2911
2911 if (adapter->BasicAllocations == FALSE) { 2912 if (adapter->BasicAllocations == FALSE) {
2912 // No allocations have been made, including spinlocks, 2913 /* No allocations have been made, including spinlocks, */
2913 // or listhead initializations. Return. 2914 /* or listhead initializations. Return. */
2914 return; 2915 return;
2915 } 2916 }
2916 2917
@@ -2920,7 +2921,7 @@ void SxgFreeResources(p_adapter_t adapter)
2920 if (!(IsListEmpty(&adapter->AllSglBuffers))) { 2921 if (!(IsListEmpty(&adapter->AllSglBuffers))) {
2921 SxgFreeSglBuffers(adapter); 2922 SxgFreeSglBuffers(adapter);
2922 } 2923 }
2923 // Free event queues. 2924 /* Free event queues. */
2924 if (adapter->EventRings) { 2925 if (adapter->EventRings) {
2925 pci_free_consistent(adapter->pcidev, 2926 pci_free_consistent(adapter->pcidev,
2926 sizeof(SXG_EVENT_RING) * RssIds, 2927 sizeof(SXG_EVENT_RING) * RssIds,
@@ -2947,17 +2948,17 @@ void SxgFreeResources(p_adapter_t adapter)
2947 SXG_FREE_PACKET_POOL(adapter->PacketPoolHandle); 2948 SXG_FREE_PACKET_POOL(adapter->PacketPoolHandle);
2948 SXG_FREE_BUFFER_POOL(adapter->BufferPoolHandle); 2949 SXG_FREE_BUFFER_POOL(adapter->BufferPoolHandle);
2949 2950
2950 // Unmap register spaces 2951 /* Unmap register spaces */
2951 SxgUnmapResources(adapter); 2952 SxgUnmapResources(adapter);
2952 2953
2953 // Deregister DMA 2954 /* Deregister DMA */
2954 if (adapter->DmaHandle) { 2955 if (adapter->DmaHandle) {
2955 SXG_DEREGISTER_DMA(adapter->DmaHandle); 2956 SXG_DEREGISTER_DMA(adapter->DmaHandle);
2956 } 2957 }
2957 // Deregister interrupt 2958 /* Deregister interrupt */
2958 SxgDeregisterInterrupt(adapter); 2959 SxgDeregisterInterrupt(adapter);
2959 2960
2960 // Possibly free system info (5.2 only) 2961 /* Possibly free system info (5.2 only) */
2961 SXG_RELEASE_SYSTEM_INFO(adapter); 2962 SXG_RELEASE_SYSTEM_INFO(adapter);
2962 2963
2963 SxgDiagFreeResources(adapter); 2964 SxgDiagFreeResources(adapter);
@@ -3047,23 +3048,23 @@ static int sxg_allocate_buffer_memory(p_adapter_t adapter,
3047 3048
3048 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocMem", 3049 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocMem",
3049 adapter, Size, BufferType, 0); 3050 adapter, Size, BufferType, 0);
3050 // Grab the adapter lock and check the state. 3051 /* Grab the adapter lock and check the state. */
3051 // If we're in anything other than INITIALIZING or 3052 /* If we're in anything other than INITIALIZING or */
3052 // RUNNING state, fail. This is to prevent 3053 /* RUNNING state, fail. This is to prevent */
3053 // allocations in an improper driver state 3054 /* allocations in an improper driver state */
3054 spin_lock(&adapter->AdapterLock); 3055 spin_lock(&adapter->AdapterLock);
3055 3056
3056 // Increment the AllocationsPending count while holding 3057 /* Increment the AllocationsPending count while holding */
3057 // the lock. Pause processing relies on this 3058 /* the lock. Pause processing relies on this */
3058 ++adapter->AllocationsPending; 3059 ++adapter->AllocationsPending;
3059 spin_unlock(&adapter->AdapterLock); 3060 spin_unlock(&adapter->AdapterLock);
3060 3061
3061 // At initialization time allocate resources synchronously. 3062 /* At initialization time allocate resources synchronously. */
3062 Buffer = pci_alloc_consistent(adapter->pcidev, Size, &pBuffer); 3063 Buffer = pci_alloc_consistent(adapter->pcidev, Size, &pBuffer);
3063 if (Buffer == NULL) { 3064 if (Buffer == NULL) {
3064 spin_lock(&adapter->AdapterLock); 3065 spin_lock(&adapter->AdapterLock);
3065 // Decrement the AllocationsPending count while holding 3066 /* Decrement the AllocationsPending count while holding */
3066 // the lock. Pause processing relies on this 3067 /* the lock. Pause processing relies on this */
3067 --adapter->AllocationsPending; 3068 --adapter->AllocationsPending;
3068 spin_unlock(&adapter->AdapterLock); 3069 spin_unlock(&adapter->AdapterLock);
3069 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlcMemF1", 3070 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlcMemF1",
@@ -3113,10 +3114,10 @@ static void sxg_allocate_rcvblock_complete(p_adapter_t adapter,
3113 ASSERT((BufferSize == SXG_RCV_DATA_BUFFER_SIZE) || 3114 ASSERT((BufferSize == SXG_RCV_DATA_BUFFER_SIZE) ||
3114 (BufferSize == SXG_RCV_JUMBO_BUFFER_SIZE)); 3115 (BufferSize == SXG_RCV_JUMBO_BUFFER_SIZE));
3115 ASSERT(Length == SXG_RCV_BLOCK_SIZE(BufferSize)); 3116 ASSERT(Length == SXG_RCV_BLOCK_SIZE(BufferSize));
3116 // First, initialize the contained pool of receive data 3117 /* First, initialize the contained pool of receive data */
3117 // buffers. This initialization requires NBL/NB/MDL allocations, 3118 /* buffers. This initialization requires NBL/NB/MDL allocations, */
3118 // If any of them fail, free the block and return without 3119 /* If any of them fail, free the block and return without */
3119 // queueing the shared memory 3120 /* queueing the shared memory */
3120 RcvDataBuffer = RcvBlock; 3121 RcvDataBuffer = RcvBlock;
3121#if 0 3122#if 0
3122 for (i = 0, Paddr = *PhysicalAddress; 3123 for (i = 0, Paddr = *PhysicalAddress;
@@ -3126,14 +3127,14 @@ static void sxg_allocate_rcvblock_complete(p_adapter_t adapter,
3126 for (i = 0, Paddr = PhysicalAddress; 3127 for (i = 0, Paddr = PhysicalAddress;
3127 i < SXG_RCV_DESCRIPTORS_PER_BLOCK; 3128 i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
3128 i++, Paddr += BufferSize, RcvDataBuffer += BufferSize) { 3129 i++, Paddr += BufferSize, RcvDataBuffer += BufferSize) {
3129 // 3130 /* */
3130 RcvDataBufferHdr = 3131 RcvDataBufferHdr =
3131 (PSXG_RCV_DATA_BUFFER_HDR) (RcvDataBuffer + 3132 (PSXG_RCV_DATA_BUFFER_HDR) (RcvDataBuffer +
3132 SXG_RCV_DATA_BUFFER_HDR_OFFSET 3133 SXG_RCV_DATA_BUFFER_HDR_OFFSET
3133 (BufferSize)); 3134 (BufferSize));
3134 RcvDataBufferHdr->VirtualAddress = RcvDataBuffer; 3135 RcvDataBufferHdr->VirtualAddress = RcvDataBuffer;
3135 RcvDataBufferHdr->PhysicalAddress = Paddr; 3136 RcvDataBufferHdr->PhysicalAddress = Paddr;
3136 RcvDataBufferHdr->State = SXG_BUFFER_UPSTREAM; // For FREE macro assertion 3137 RcvDataBufferHdr->State = SXG_BUFFER_UPSTREAM; /* For FREE macro assertion */
3137 RcvDataBufferHdr->Size = 3138 RcvDataBufferHdr->Size =
3138 SXG_RCV_BUFFER_DATA_SIZE(BufferSize); 3139 SXG_RCV_BUFFER_DATA_SIZE(BufferSize);
3139 3140
@@ -3143,8 +3144,8 @@ static void sxg_allocate_rcvblock_complete(p_adapter_t adapter,
3143 3144
3144 } 3145 }
3145 3146
3146 // Place this entire block of memory on the AllRcvBlocks queue so it can be 3147 /* Place this entire block of memory on the AllRcvBlocks queue so it can be */
3147 // free later 3148 /* free later */
3148 RcvBlockHdr = 3149 RcvBlockHdr =
3149 (PSXG_RCV_BLOCK_HDR) ((unsigned char *)RcvBlock + 3150 (PSXG_RCV_BLOCK_HDR) ((unsigned char *)RcvBlock +
3150 SXG_RCV_BLOCK_HDR_OFFSET(BufferSize)); 3151 SXG_RCV_BLOCK_HDR_OFFSET(BufferSize));
@@ -3155,7 +3156,7 @@ static void sxg_allocate_rcvblock_complete(p_adapter_t adapter,
3155 InsertTailList(&adapter->AllRcvBlocks, &RcvBlockHdr->AllList); 3156 InsertTailList(&adapter->AllRcvBlocks, &RcvBlockHdr->AllList);
3156 spin_unlock(&adapter->RcvQLock); 3157 spin_unlock(&adapter->RcvQLock);
3157 3158
3158 // Now free the contained receive data buffers that we initialized above 3159 /* Now free the contained receive data buffers that we initialized above */
3159 RcvDataBuffer = RcvBlock; 3160 RcvDataBuffer = RcvBlock;
3160 for (i = 0, Paddr = PhysicalAddress; 3161 for (i = 0, Paddr = PhysicalAddress;
3161 i < SXG_RCV_DESCRIPTORS_PER_BLOCK; 3162 i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
@@ -3168,7 +3169,7 @@ static void sxg_allocate_rcvblock_complete(p_adapter_t adapter,
3168 spin_unlock(&adapter->RcvQLock); 3169 spin_unlock(&adapter->RcvQLock);
3169 } 3170 }
3170 3171
3171 // Locate the descriptor block and put it on a separate free queue 3172 /* Locate the descriptor block and put it on a separate free queue */
3172 RcvDescriptorBlock = 3173 RcvDescriptorBlock =
3173 (PSXG_RCV_DESCRIPTOR_BLOCK) ((unsigned char *)RcvBlock + 3174 (PSXG_RCV_DESCRIPTOR_BLOCK) ((unsigned char *)RcvBlock +
3174 SXG_RCV_DESCRIPTOR_BLOCK_OFFSET 3175 SXG_RCV_DESCRIPTOR_BLOCK_OFFSET
@@ -3186,7 +3187,7 @@ static void sxg_allocate_rcvblock_complete(p_adapter_t adapter,
3186 adapter, RcvBlock, Length, 0); 3187 adapter, RcvBlock, Length, 0);
3187 return; 3188 return;
3188 fail: 3189 fail:
3189 // Free any allocated resources 3190 /* Free any allocated resources */
3190 if (RcvBlock) { 3191 if (RcvBlock) {
3191 RcvDataBuffer = RcvBlock; 3192 RcvDataBuffer = RcvBlock;
3192 for (i = 0; i < SXG_RCV_DESCRIPTORS_PER_BLOCK; 3193 for (i = 0; i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
@@ -3200,7 +3201,7 @@ static void sxg_allocate_rcvblock_complete(p_adapter_t adapter,
3200 pci_free_consistent(adapter->pcidev, 3201 pci_free_consistent(adapter->pcidev,
3201 Length, RcvBlock, PhysicalAddress); 3202 Length, RcvBlock, PhysicalAddress);
3202 } 3203 }
3203 DBG_ERROR("%s: OUT OF RESOURCES\n", __FUNCTION__); 3204 DBG_ERROR("%s: OUT OF RESOURCES\n", __func__);
3204 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "RcvAFail", 3205 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "RcvAFail",
3205 adapter, adapter->FreeRcvBufferCount, 3206 adapter, adapter->FreeRcvBufferCount,
3206 adapter->FreeRcvBlockCount, adapter->AllRcvBlockCount); 3207 adapter->FreeRcvBlockCount, adapter->AllRcvBlockCount);
@@ -3230,7 +3231,7 @@ static void sxg_allocate_sgl_buffer_complete(p_adapter_t adapter,
3230 adapter->AllSglBufferCount++; 3231 adapter->AllSglBufferCount++;
3231 memset(SxgSgl, 0, sizeof(SXG_SCATTER_GATHER)); 3232 memset(SxgSgl, 0, sizeof(SXG_SCATTER_GATHER));
3232 SxgSgl->PhysicalAddress = PhysicalAddress; /* *PhysicalAddress; */ 3233 SxgSgl->PhysicalAddress = PhysicalAddress; /* *PhysicalAddress; */
3233 SxgSgl->adapter = adapter; // Initialize backpointer once 3234 SxgSgl->adapter = adapter; /* Initialize backpointer once */
3234 InsertTailList(&adapter->AllSglBuffers, &SxgSgl->AllList); 3235 InsertTailList(&adapter->AllSglBuffers, &SxgSgl->AllList);
3235 spin_unlock(&adapter->SglQLock); 3236 spin_unlock(&adapter->SglQLock);
3236 SxgSgl->State = SXG_BUFFER_BUSY; 3237 SxgSgl->State = SXG_BUFFER_BUSY;
@@ -3244,14 +3245,14 @@ static unsigned char temp_mac_address[6] =
3244 3245
3245static void sxg_adapter_set_hwaddr(p_adapter_t adapter) 3246static void sxg_adapter_set_hwaddr(p_adapter_t adapter)
3246{ 3247{
3247// DBG_ERROR ("%s ENTER card->config_set[%x] port[%d] physport[%d] funct#[%d]\n", __FUNCTION__, 3248/* DBG_ERROR ("%s ENTER card->config_set[%x] port[%d] physport[%d] funct#[%d]\n", __func__, */
3248// card->config_set, adapter->port, adapter->physport, adapter->functionnumber); 3249/* card->config_set, adapter->port, adapter->physport, adapter->functionnumber); */
3249// 3250/* */
3250// sxg_dbg_macaddrs(adapter); 3251/* sxg_dbg_macaddrs(adapter); */
3251 3252
3252 memcpy(adapter->macaddr, temp_mac_address, sizeof(SXG_CONFIG_MAC)); 3253 memcpy(adapter->macaddr, temp_mac_address, sizeof(SXG_CONFIG_MAC));
3253// DBG_ERROR ("%s AFTER copying from config.macinfo into currmacaddr\n", __FUNCTION__); 3254/* DBG_ERROR ("%s AFTER copying from config.macinfo into currmacaddr\n", __func__); */
3254// sxg_dbg_macaddrs(adapter); 3255/* sxg_dbg_macaddrs(adapter); */
3255 if (!(adapter->currmacaddr[0] || 3256 if (!(adapter->currmacaddr[0] ||
3256 adapter->currmacaddr[1] || 3257 adapter->currmacaddr[1] ||
3257 adapter->currmacaddr[2] || 3258 adapter->currmacaddr[2] ||
@@ -3262,18 +3263,18 @@ static void sxg_adapter_set_hwaddr(p_adapter_t adapter)
3262 if (adapter->netdev) { 3263 if (adapter->netdev) {
3263 memcpy(adapter->netdev->dev_addr, adapter->currmacaddr, 6); 3264 memcpy(adapter->netdev->dev_addr, adapter->currmacaddr, 6);
3264 } 3265 }
3265// DBG_ERROR ("%s EXIT port %d\n", __FUNCTION__, adapter->port); 3266/* DBG_ERROR ("%s EXIT port %d\n", __func__, adapter->port); */
3266 sxg_dbg_macaddrs(adapter); 3267 sxg_dbg_macaddrs(adapter);
3267 3268
3268} 3269}
3269 3270
3271#if XXXTODO
3270static int sxg_mac_set_address(p_net_device dev, void *ptr) 3272static int sxg_mac_set_address(p_net_device dev, void *ptr)
3271{ 3273{
3272#if XXXTODO
3273 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev); 3274 p_adapter_t adapter = (p_adapter_t) netdev_priv(dev);
3274 struct sockaddr *addr = ptr; 3275 struct sockaddr *addr = ptr;
3275 3276
3276 DBG_ERROR("%s ENTER (%s)\n", __FUNCTION__, adapter->netdev->name); 3277 DBG_ERROR("%s ENTER (%s)\n", __func__, adapter->netdev->name);
3277 3278
3278 if (netif_running(dev)) { 3279 if (netif_running(dev)) {
3279 return -EBUSY; 3280 return -EBUSY;
@@ -3282,22 +3283,22 @@ static int sxg_mac_set_address(p_net_device dev, void *ptr)
3282 return -EBUSY; 3283 return -EBUSY;
3283 } 3284 }
3284 DBG_ERROR("sxg: %s (%s) curr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n", 3285 DBG_ERROR("sxg: %s (%s) curr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
3285 __FUNCTION__, adapter->netdev->name, adapter->currmacaddr[0], 3286 __func__, adapter->netdev->name, adapter->currmacaddr[0],
3286 adapter->currmacaddr[1], adapter->currmacaddr[2], 3287 adapter->currmacaddr[1], adapter->currmacaddr[2],
3287 adapter->currmacaddr[3], adapter->currmacaddr[4], 3288 adapter->currmacaddr[3], adapter->currmacaddr[4],
3288 adapter->currmacaddr[5]); 3289 adapter->currmacaddr[5]);
3289 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 3290 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3290 memcpy(adapter->currmacaddr, addr->sa_data, dev->addr_len); 3291 memcpy(adapter->currmacaddr, addr->sa_data, dev->addr_len);
3291 DBG_ERROR("sxg: %s (%s) new %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n", 3292 DBG_ERROR("sxg: %s (%s) new %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
3292 __FUNCTION__, adapter->netdev->name, adapter->currmacaddr[0], 3293 __func__, adapter->netdev->name, adapter->currmacaddr[0],
3293 adapter->currmacaddr[1], adapter->currmacaddr[2], 3294 adapter->currmacaddr[1], adapter->currmacaddr[2],
3294 adapter->currmacaddr[3], adapter->currmacaddr[4], 3295 adapter->currmacaddr[3], adapter->currmacaddr[4],
3295 adapter->currmacaddr[5]); 3296 adapter->currmacaddr[5]);
3296 3297
3297 sxg_config_set(adapter, TRUE); 3298 sxg_config_set(adapter, TRUE);
3298#endif
3299 return 0; 3299 return 0;
3300} 3300}
3301#endif
3301 3302
3302/*****************************************************************************/ 3303/*****************************************************************************/
3303/************* SXG DRIVER FUNCTIONS (below) ********************************/ 3304/************* SXG DRIVER FUNCTIONS (below) ********************************/
@@ -3321,77 +3322,77 @@ static int sxg_initialize_adapter(p_adapter_t adapter)
3321 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "InitAdpt", 3322 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "InitAdpt",
3322 adapter, 0, 0, 0); 3323 adapter, 0, 0, 0);
3323 3324
3324 RssIds = 1; // XXXTODO SXG_RSS_CPU_COUNT(adapter); 3325 RssIds = 1; /* XXXTODO SXG_RSS_CPU_COUNT(adapter); */
3325 IsrCount = adapter->MsiEnabled ? RssIds : 1; 3326 IsrCount = adapter->MsiEnabled ? RssIds : 1;
3326 3327
3327 // Sanity check SXG_UCODE_REGS structure definition to 3328 /* Sanity check SXG_UCODE_REGS structure definition to */
3328 // make sure the length is correct 3329 /* make sure the length is correct */
3329 ASSERT(sizeof(SXG_UCODE_REGS) == SXG_REGISTER_SIZE_PER_CPU); 3330 ASSERT(sizeof(SXG_UCODE_REGS) == SXG_REGISTER_SIZE_PER_CPU);
3330 3331
3331 // Disable interrupts 3332 /* Disable interrupts */
3332 SXG_DISABLE_ALL_INTERRUPTS(adapter); 3333 SXG_DISABLE_ALL_INTERRUPTS(adapter);
3333 3334
3334 // Set MTU 3335 /* Set MTU */
3335 ASSERT((adapter->FrameSize == ETHERMAXFRAME) || 3336 ASSERT((adapter->FrameSize == ETHERMAXFRAME) ||
3336 (adapter->FrameSize == JUMBOMAXFRAME)); 3337 (adapter->FrameSize == JUMBOMAXFRAME));
3337 WRITE_REG(adapter->UcodeRegs[0].LinkMtu, adapter->FrameSize, TRUE); 3338 WRITE_REG(adapter->UcodeRegs[0].LinkMtu, adapter->FrameSize, TRUE);
3338 3339
3339 // Set event ring base address and size 3340 /* Set event ring base address and size */
3340 WRITE_REG64(adapter, 3341 WRITE_REG64(adapter,
3341 adapter->UcodeRegs[0].EventBase, adapter->PEventRings, 0); 3342 adapter->UcodeRegs[0].EventBase, adapter->PEventRings, 0);
3342 WRITE_REG(adapter->UcodeRegs[0].EventSize, EVENT_RING_SIZE, TRUE); 3343 WRITE_REG(adapter->UcodeRegs[0].EventSize, EVENT_RING_SIZE, TRUE);
3343 3344
3344 // Per-ISR initialization 3345 /* Per-ISR initialization */
3345 for (i = 0; i < IsrCount; i++) { 3346 for (i = 0; i < IsrCount; i++) {
3346 u64 Addr; 3347 u64 Addr;
3347 // Set interrupt status pointer 3348 /* Set interrupt status pointer */
3348 Addr = adapter->PIsr + (i * sizeof(u32)); 3349 Addr = adapter->PIsr + (i * sizeof(u32));
3349 WRITE_REG64(adapter, adapter->UcodeRegs[i].Isp, Addr, i); 3350 WRITE_REG64(adapter, adapter->UcodeRegs[i].Isp, Addr, i);
3350 } 3351 }
3351 3352
3352 // XMT ring zero index 3353 /* XMT ring zero index */
3353 WRITE_REG64(adapter, 3354 WRITE_REG64(adapter,
3354 adapter->UcodeRegs[0].SPSendIndex, 3355 adapter->UcodeRegs[0].SPSendIndex,
3355 adapter->PXmtRingZeroIndex, 0); 3356 adapter->PXmtRingZeroIndex, 0);
3356 3357
3357 // Per-RSS initialization 3358 /* Per-RSS initialization */
3358 for (i = 0; i < RssIds; i++) { 3359 for (i = 0; i < RssIds; i++) {
3359 // Release all event ring entries to the Microcode 3360 /* Release all event ring entries to the Microcode */
3360 WRITE_REG(adapter->UcodeRegs[i].EventRelease, EVENT_RING_SIZE, 3361 WRITE_REG(adapter->UcodeRegs[i].EventRelease, EVENT_RING_SIZE,
3361 TRUE); 3362 TRUE);
3362 } 3363 }
3363 3364
3364 // Transmit ring base and size 3365 /* Transmit ring base and size */
3365 WRITE_REG64(adapter, 3366 WRITE_REG64(adapter,
3366 adapter->UcodeRegs[0].XmtBase, adapter->PXmtRings, 0); 3367 adapter->UcodeRegs[0].XmtBase, adapter->PXmtRings, 0);
3367 WRITE_REG(adapter->UcodeRegs[0].XmtSize, SXG_XMT_RING_SIZE, TRUE); 3368 WRITE_REG(adapter->UcodeRegs[0].XmtSize, SXG_XMT_RING_SIZE, TRUE);
3368 3369
3369 // Receive ring base and size 3370 /* Receive ring base and size */
3370 WRITE_REG64(adapter, 3371 WRITE_REG64(adapter,
3371 adapter->UcodeRegs[0].RcvBase, adapter->PRcvRings, 0); 3372 adapter->UcodeRegs[0].RcvBase, adapter->PRcvRings, 0);
3372 WRITE_REG(adapter->UcodeRegs[0].RcvSize, SXG_RCV_RING_SIZE, TRUE); 3373 WRITE_REG(adapter->UcodeRegs[0].RcvSize, SXG_RCV_RING_SIZE, TRUE);
3373 3374
3374 // Populate the card with receive buffers 3375 /* Populate the card with receive buffers */
3375 sxg_stock_rcv_buffers(adapter); 3376 sxg_stock_rcv_buffers(adapter);
3376 3377
3377 // Initialize checksum offload capabilities. At the moment 3378 /* Initialize checksum offload capabilities. At the moment */
3378 // we always enable IP and TCP receive checksums on the card. 3379 /* we always enable IP and TCP receive checksums on the card. */
3379 // Depending on the checksum configuration specified by the 3380 /* Depending on the checksum configuration specified by the */
3380 // user, we can choose to report or ignore the checksum 3381 /* user, we can choose to report or ignore the checksum */
3381 // information provided by the card. 3382 /* information provided by the card. */
3382 WRITE_REG(adapter->UcodeRegs[0].ReceiveChecksum, 3383 WRITE_REG(adapter->UcodeRegs[0].ReceiveChecksum,
3383 SXG_RCV_TCP_CSUM_ENABLED | SXG_RCV_IP_CSUM_ENABLED, TRUE); 3384 SXG_RCV_TCP_CSUM_ENABLED | SXG_RCV_IP_CSUM_ENABLED, TRUE);
3384 3385
3385 // Initialize the MAC, XAUI 3386 /* Initialize the MAC, XAUI */
3386 DBG_ERROR("sxg: %s ENTER sxg_initialize_link\n", __FUNCTION__); 3387 DBG_ERROR("sxg: %s ENTER sxg_initialize_link\n", __func__);
3387 status = sxg_initialize_link(adapter); 3388 status = sxg_initialize_link(adapter);
3388 DBG_ERROR("sxg: %s EXIT sxg_initialize_link status[%x]\n", __FUNCTION__, 3389 DBG_ERROR("sxg: %s EXIT sxg_initialize_link status[%x]\n", __func__,
3389 status); 3390 status);
3390 if (status != STATUS_SUCCESS) { 3391 if (status != STATUS_SUCCESS) {
3391 return (status); 3392 return (status);
3392 } 3393 }
3393 // Initialize Dead to FALSE. 3394 /* Initialize Dead to FALSE. */
3394 // SlicCheckForHang or SlicDumpThread will take it from here. 3395 /* SlicCheckForHang or SlicDumpThread will take it from here. */
3395 adapter->Dead = FALSE; 3396 adapter->Dead = FALSE;
3396 adapter->PingOutstanding = FALSE; 3397 adapter->PingOutstanding = FALSE;
3397 3398
@@ -3428,14 +3429,14 @@ static int sxg_fill_descriptor_block(p_adapter_t adapter,
3428 3429
3429 ASSERT(RcvDescriptorBlockHdr); 3430 ASSERT(RcvDescriptorBlockHdr);
3430 3431
3431 // If we don't have the resources to fill the descriptor block, 3432 /* If we don't have the resources to fill the descriptor block, */
3432 // return failure 3433 /* return failure */
3433 if ((adapter->FreeRcvBufferCount < SXG_RCV_DESCRIPTORS_PER_BLOCK) || 3434 if ((adapter->FreeRcvBufferCount < SXG_RCV_DESCRIPTORS_PER_BLOCK) ||
3434 SXG_RING_FULL(RcvRingInfo)) { 3435 SXG_RING_FULL(RcvRingInfo)) {
3435 adapter->Stats.NoMem++; 3436 adapter->Stats.NoMem++;
3436 return (STATUS_FAILURE); 3437 return (STATUS_FAILURE);
3437 } 3438 }
3438 // Get a ring descriptor command 3439 /* Get a ring descriptor command */
3439 SXG_GET_CMD(RingZero, 3440 SXG_GET_CMD(RingZero,
3440 RcvRingInfo, RingDescriptorCmd, RcvDescriptorBlockHdr); 3441 RcvRingInfo, RingDescriptorCmd, RcvDescriptorBlockHdr);
3441 ASSERT(RingDescriptorCmd); 3442 ASSERT(RingDescriptorCmd);
@@ -3443,7 +3444,7 @@ static int sxg_fill_descriptor_block(p_adapter_t adapter,
3443 RcvDescriptorBlock = 3444 RcvDescriptorBlock =
3444 (PSXG_RCV_DESCRIPTOR_BLOCK) RcvDescriptorBlockHdr->VirtualAddress; 3445 (PSXG_RCV_DESCRIPTOR_BLOCK) RcvDescriptorBlockHdr->VirtualAddress;
3445 3446
3446 // Fill in the descriptor block 3447 /* Fill in the descriptor block */
3447 for (i = 0; i < SXG_RCV_DESCRIPTORS_PER_BLOCK; i++) { 3448 for (i = 0; i < SXG_RCV_DESCRIPTORS_PER_BLOCK; i++) {
3448 SXG_GET_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr); 3449 SXG_GET_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
3449 ASSERT(RcvDataBufferHdr); 3450 ASSERT(RcvDataBufferHdr);
@@ -3454,13 +3455,13 @@ static int sxg_fill_descriptor_block(p_adapter_t adapter,
3454 RcvDescriptorBlock->Descriptors[i].PhysicalAddress = 3455 RcvDescriptorBlock->Descriptors[i].PhysicalAddress =
3455 RcvDataBufferHdr->PhysicalAddress; 3456 RcvDataBufferHdr->PhysicalAddress;
3456 } 3457 }
3457 // Add the descriptor block to receive descriptor ring 0 3458 /* Add the descriptor block to receive descriptor ring 0 */
3458 RingDescriptorCmd->Sgl = RcvDescriptorBlockHdr->PhysicalAddress; 3459 RingDescriptorCmd->Sgl = RcvDescriptorBlockHdr->PhysicalAddress;
3459 3460
3460 // RcvBuffersOnCard is not protected via the receive lock (see 3461 /* RcvBuffersOnCard is not protected via the receive lock (see */
3461 // sxg_process_event_queue) We don't want to grap a lock every time a 3462 /* sxg_process_event_queue) We don't want to grap a lock every time a */
3462 // buffer is returned to us, so we use atomic interlocked functions 3463 /* buffer is returned to us, so we use atomic interlocked functions */
3463 // instead. 3464 /* instead. */
3464 adapter->RcvBuffersOnCard += SXG_RCV_DESCRIPTORS_PER_BLOCK; 3465 adapter->RcvBuffersOnCard += SXG_RCV_DESCRIPTORS_PER_BLOCK;
3465 3466
3466 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DscBlk", 3467 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DscBlk",
@@ -3490,10 +3491,10 @@ static void sxg_stock_rcv_buffers(p_adapter_t adapter)
3490 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "StockBuf", 3491 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "StockBuf",
3491 adapter, adapter->RcvBuffersOnCard, 3492 adapter, adapter->RcvBuffersOnCard,
3492 adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount); 3493 adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
3493 // First, see if we've got less than our minimum threshold of 3494 /* First, see if we've got less than our minimum threshold of */
3494 // receive buffers, there isn't an allocation in progress, and 3495 /* receive buffers, there isn't an allocation in progress, and */
3495 // we haven't exceeded our maximum.. get another block of buffers 3496 /* we haven't exceeded our maximum.. get another block of buffers */
3496 // None of this needs to be SMP safe. It's round numbers. 3497 /* None of this needs to be SMP safe. It's round numbers. */
3497 if ((adapter->FreeRcvBufferCount < SXG_MIN_RCV_DATA_BUFFERS) && 3498 if ((adapter->FreeRcvBufferCount < SXG_MIN_RCV_DATA_BUFFERS) &&
3498 (adapter->AllRcvBlockCount < SXG_MAX_RCV_BLOCKS) && 3499 (adapter->AllRcvBlockCount < SXG_MAX_RCV_BLOCKS) &&
3499 (adapter->AllocationsPending == 0)) { 3500 (adapter->AllocationsPending == 0)) {
@@ -3502,12 +3503,12 @@ static void sxg_stock_rcv_buffers(p_adapter_t adapter)
3502 ReceiveBufferSize), 3503 ReceiveBufferSize),
3503 SXG_BUFFER_TYPE_RCV); 3504 SXG_BUFFER_TYPE_RCV);
3504 } 3505 }
3505 // Now grab the RcvQLock lock and proceed 3506 /* Now grab the RcvQLock lock and proceed */
3506 spin_lock(&adapter->RcvQLock); 3507 spin_lock(&adapter->RcvQLock);
3507 while (adapter->RcvBuffersOnCard < SXG_RCV_DATA_BUFFERS) { 3508 while (adapter->RcvBuffersOnCard < SXG_RCV_DATA_BUFFERS) {
3508 PLIST_ENTRY _ple; 3509 PLIST_ENTRY _ple;
3509 3510
3510 // Get a descriptor block 3511 /* Get a descriptor block */
3511 RcvDescriptorBlockHdr = NULL; 3512 RcvDescriptorBlockHdr = NULL;
3512 if (adapter->FreeRcvBlockCount) { 3513 if (adapter->FreeRcvBlockCount) {
3513 _ple = RemoveHeadList(&adapter->FreeRcvBlocks); 3514 _ple = RemoveHeadList(&adapter->FreeRcvBlocks);
@@ -3519,14 +3520,14 @@ static void sxg_stock_rcv_buffers(p_adapter_t adapter)
3519 } 3520 }
3520 3521
3521 if (RcvDescriptorBlockHdr == NULL) { 3522 if (RcvDescriptorBlockHdr == NULL) {
3522 // Bail out.. 3523 /* Bail out.. */
3523 adapter->Stats.NoMem++; 3524 adapter->Stats.NoMem++;
3524 break; 3525 break;
3525 } 3526 }
3526 // Fill in the descriptor block and give it to the card 3527 /* Fill in the descriptor block and give it to the card */
3527 if (sxg_fill_descriptor_block(adapter, RcvDescriptorBlockHdr) == 3528 if (sxg_fill_descriptor_block(adapter, RcvDescriptorBlockHdr) ==
3528 STATUS_FAILURE) { 3529 STATUS_FAILURE) {
3529 // Free the descriptor block 3530 /* Free the descriptor block */
3530 SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter, 3531 SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter,
3531 RcvDescriptorBlockHdr); 3532 RcvDescriptorBlockHdr);
3532 break; 3533 break;
@@ -3560,15 +3561,15 @@ static void sxg_complete_descriptor_blocks(p_adapter_t adapter,
3560 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpRBlks", 3561 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpRBlks",
3561 adapter, Index, RcvRingInfo->Head, RcvRingInfo->Tail); 3562 adapter, Index, RcvRingInfo->Head, RcvRingInfo->Tail);
3562 3563
3563 // Now grab the RcvQLock lock and proceed 3564 /* Now grab the RcvQLock lock and proceed */
3564 spin_lock(&adapter->RcvQLock); 3565 spin_lock(&adapter->RcvQLock);
3565 ASSERT(Index != RcvRingInfo->Tail); 3566 ASSERT(Index != RcvRingInfo->Tail);
3566 while (RcvRingInfo->Tail != Index) { 3567 while (RcvRingInfo->Tail != Index) {
3567 // 3568 /* */
3568 // Locate the current Cmd (ring descriptor entry), and 3569 /* Locate the current Cmd (ring descriptor entry), and */
3569 // associated receive descriptor block, and advance 3570 /* associated receive descriptor block, and advance */
3570 // the tail 3571 /* the tail */
3571 // 3572 /* */
3572 SXG_RETURN_CMD(RingZero, 3573 SXG_RETURN_CMD(RingZero,
3573 RcvRingInfo, 3574 RcvRingInfo,
3574 RingDescriptorCmd, RcvDescriptorBlockHdr); 3575 RingDescriptorCmd, RcvDescriptorBlockHdr);
@@ -3576,12 +3577,12 @@ static void sxg_complete_descriptor_blocks(p_adapter_t adapter,
3576 RcvRingInfo->Head, RcvRingInfo->Tail, 3577 RcvRingInfo->Head, RcvRingInfo->Tail,
3577 RingDescriptorCmd, RcvDescriptorBlockHdr); 3578 RingDescriptorCmd, RcvDescriptorBlockHdr);
3578 3579
3579 // Clear the SGL field 3580 /* Clear the SGL field */
3580 RingDescriptorCmd->Sgl = 0; 3581 RingDescriptorCmd->Sgl = 0;
3581 // Attempt to refill it and hand it right back to the 3582 /* Attempt to refill it and hand it right back to the */
3582 // card. If we fail to refill it, free the descriptor block 3583 /* card. If we fail to refill it, free the descriptor block */
3583 // header. The card will be restocked later via the 3584 /* header. The card will be restocked later via the */
3584 // RcvBuffersOnCard test 3585 /* RcvBuffersOnCard test */
3585 if (sxg_fill_descriptor_block(adapter, RcvDescriptorBlockHdr) == 3586 if (sxg_fill_descriptor_block(adapter, RcvDescriptorBlockHdr) ==
3586 STATUS_FAILURE) { 3587 STATUS_FAILURE) {
3587 SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter, 3588 SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter,
diff --git a/drivers/staging/sxg/sxg_os.h b/drivers/staging/sxg/sxg_os.h
index 26fb0ffafa5c..01182689aaba 100644
--- a/drivers/staging/sxg/sxg_os.h
+++ b/drivers/staging/sxg/sxg_os.h
@@ -44,7 +44,6 @@
44#define FALSE (0) 44#define FALSE (0)
45#define TRUE (1) 45#define TRUE (1)
46 46
47
48typedef struct _LIST_ENTRY { 47typedef struct _LIST_ENTRY {
49 struct _LIST_ENTRY *nle_flink; 48 struct _LIST_ENTRY *nle_flink;
50 struct _LIST_ENTRY *nle_blink; 49 struct _LIST_ENTRY *nle_blink;
@@ -69,35 +68,32 @@ typedef struct _LIST_ENTRY {
69 68
70/* These two have to be inlined since they return things. */ 69/* These two have to be inlined since they return things. */
71 70
72static __inline PLIST_ENTRY 71static __inline PLIST_ENTRY RemoveHeadList(list_entry * l)
73RemoveHeadList(list_entry *l)
74{ 72{
75 list_entry *f; 73 list_entry *f;
76 list_entry *e; 74 list_entry *e;
77 75
78 e = l->nle_flink; 76 e = l->nle_flink;
79 f = e->nle_flink; 77 f = e->nle_flink;
80 l->nle_flink = f; 78 l->nle_flink = f;
81 f->nle_blink = l; 79 f->nle_blink = l;
82 80
83 return (e); 81 return (e);
84} 82}
85 83
86static __inline PLIST_ENTRY 84static __inline PLIST_ENTRY RemoveTailList(list_entry * l)
87RemoveTailList(list_entry *l)
88{ 85{
89 list_entry *b; 86 list_entry *b;
90 list_entry *e; 87 list_entry *e;
91 88
92 e = l->nle_blink; 89 e = l->nle_blink;
93 b = e->nle_blink; 90 b = e->nle_blink;
94 l->nle_blink = b; 91 l->nle_blink = b;
95 b->nle_flink = l; 92 b->nle_flink = l;
96 93
97 return (e); 94 return (e);
98} 95}
99 96
100
101#define InsertTailList(l, e) \ 97#define InsertTailList(l, e) \
102 do { \ 98 do { \
103 list_entry *b; \ 99 list_entry *b; \
@@ -120,7 +116,6 @@ RemoveTailList(list_entry *l)
120 (l)->nle_flink = (e); \ 116 (l)->nle_flink = (e); \
121 } while (0) 117 } while (0)
122 118
123
124#define ATK_DEBUG 1 119#define ATK_DEBUG 1
125 120
126#if ATK_DEBUG 121#if ATK_DEBUG
@@ -133,7 +128,6 @@ RemoveTailList(list_entry *l)
133#define SLIC_TIMESTAMP(value) 128#define SLIC_TIMESTAMP(value)
134#endif 129#endif
135 130
136
137/****************** SXG DEFINES *****************************************/ 131/****************** SXG DEFINES *****************************************/
138 132
139#ifdef ATKDBG 133#ifdef ATKDBG
@@ -150,5 +144,4 @@ RemoveTailList(list_entry *l)
150#define WRITE_REG64(a,reg,value,cpu) sxg_reg64_write((a),(&reg),(value),(cpu)) 144#define WRITE_REG64(a,reg,value,cpu) sxg_reg64_write((a),(&reg),(value),(cpu))
151#define READ_REG(reg,value) (value) = readl((void __iomem *)(&reg)) 145#define READ_REG(reg,value) (value) = readl((void __iomem *)(&reg))
152 146
153#endif /* _SLIC_OS_SPECIFIC_H_ */ 147#endif /* _SLIC_OS_SPECIFIC_H_ */
154
diff --git a/drivers/staging/sxg/sxgdbg.h b/drivers/staging/sxg/sxgdbg.h
index cfb6c7c77a9e..4522b8d71495 100644
--- a/drivers/staging/sxg/sxgdbg.h
+++ b/drivers/staging/sxg/sxgdbg.h
@@ -58,7 +58,7 @@
58 { \ 58 { \
59 if (!(a)) { \ 59 if (!(a)) { \
60 DBG_ERROR("ASSERT() Failure: file %s, function %s line %d\n",\ 60 DBG_ERROR("ASSERT() Failure: file %s, function %s line %d\n",\
61 __FILE__, __FUNCTION__, __LINE__); \ 61 __FILE__, __func__, __LINE__); \
62 } \ 62 } \
63 } 63 }
64#endif 64#endif
diff --git a/drivers/staging/sxg/sxghif.h b/drivers/staging/sxg/sxghif.h
index ed26ceaa1315..88bffbaa3be8 100644
--- a/drivers/staging/sxg/sxghif.h
+++ b/drivers/staging/sxg/sxghif.h
@@ -14,119 +14,119 @@
14 *******************************************************************************/ 14 *******************************************************************************/
15typedef struct _SXG_UCODE_REGS { 15typedef struct _SXG_UCODE_REGS {
16 // Address 0 - 0x3F = Command codes 0-15 for TCB 0. Excode 0 16 // Address 0 - 0x3F = Command codes 0-15 for TCB 0. Excode 0
17 u32 Icr; // Code = 0 (extended), ExCode = 0 - Int control 17 u32 Icr; // Code = 0 (extended), ExCode = 0 - Int control
18 u32 RsvdReg1; // Code = 1 - TOE -NA 18 u32 RsvdReg1; // Code = 1 - TOE -NA
19 u32 RsvdReg2; // Code = 2 - TOE -NA 19 u32 RsvdReg2; // Code = 2 - TOE -NA
20 u32 RsvdReg3; // Code = 3 - TOE -NA 20 u32 RsvdReg3; // Code = 3 - TOE -NA
21 u32 RsvdReg4; // Code = 4 - TOE -NA 21 u32 RsvdReg4; // Code = 4 - TOE -NA
22 u32 RsvdReg5; // Code = 5 - TOE -NA 22 u32 RsvdReg5; // Code = 5 - TOE -NA
23 u32 CardUp; // Code = 6 - Microcode initialized when 1 23 u32 CardUp; // Code = 6 - Microcode initialized when 1
24 u32 RsvdReg7; // Code = 7 - TOE -NA 24 u32 RsvdReg7; // Code = 7 - TOE -NA
25 u32 CodeNotUsed[8]; // Codes 8-15 not used. ExCode = 0 25 u32 CodeNotUsed[8]; // Codes 8-15 not used. ExCode = 0
26 // This brings us to ExCode 1 at address 0x40 = Interrupt status pointer 26 // This brings us to ExCode 1 at address 0x40 = Interrupt status pointer
27 u32 Isp; // Code = 0 (extended), ExCode = 1 27 u32 Isp; // Code = 0 (extended), ExCode = 1
28 u32 PadEx1[15]; // Codes 1-15 not used with extended codes 28 u32 PadEx1[15]; // Codes 1-15 not used with extended codes
29 // ExCode 2 = Interrupt Status Register 29 // ExCode 2 = Interrupt Status Register
30 u32 Isr; // Code = 0 (extended), ExCode = 2 30 u32 Isr; // Code = 0 (extended), ExCode = 2
31 u32 PadEx2[15]; 31 u32 PadEx2[15];
32 // ExCode 3 = Event base register. Location of event rings 32 // ExCode 3 = Event base register. Location of event rings
33 u32 EventBase; // Code = 0 (extended), ExCode = 3 33 u32 EventBase; // Code = 0 (extended), ExCode = 3
34 u32 PadEx3[15]; 34 u32 PadEx3[15];
35 // ExCode 4 = Event ring size 35 // ExCode 4 = Event ring size
36 u32 EventSize; // Code = 0 (extended), ExCode = 4 36 u32 EventSize; // Code = 0 (extended), ExCode = 4
37 u32 PadEx4[15]; 37 u32 PadEx4[15];
38 // ExCode 5 = TCB Buffers base address 38 // ExCode 5 = TCB Buffers base address
39 u32 TcbBase; // Code = 0 (extended), ExCode = 5 39 u32 TcbBase; // Code = 0 (extended), ExCode = 5
40 u32 PadEx5[15]; 40 u32 PadEx5[15];
41 // ExCode 6 = TCB Composite Buffers base address 41 // ExCode 6 = TCB Composite Buffers base address
42 u32 TcbCompBase; // Code = 0 (extended), ExCode = 6 42 u32 TcbCompBase; // Code = 0 (extended), ExCode = 6
43 u32 PadEx6[15]; 43 u32 PadEx6[15];
44 // ExCode 7 = Transmit ring base address 44 // ExCode 7 = Transmit ring base address
45 u32 XmtBase; // Code = 0 (extended), ExCode = 7 45 u32 XmtBase; // Code = 0 (extended), ExCode = 7
46 u32 PadEx7[15]; 46 u32 PadEx7[15];
47 // ExCode 8 = Transmit ring size 47 // ExCode 8 = Transmit ring size
48 u32 XmtSize; // Code = 0 (extended), ExCode = 8 48 u32 XmtSize; // Code = 0 (extended), ExCode = 8
49 u32 PadEx8[15]; 49 u32 PadEx8[15];
50 // ExCode 9 = Receive ring base address 50 // ExCode 9 = Receive ring base address
51 u32 RcvBase; // Code = 0 (extended), ExCode = 9 51 u32 RcvBase; // Code = 0 (extended), ExCode = 9
52 u32 PadEx9[15]; 52 u32 PadEx9[15];
53 // ExCode 10 = Receive ring size 53 // ExCode 10 = Receive ring size
54 u32 RcvSize; // Code = 0 (extended), ExCode = 10 54 u32 RcvSize; // Code = 0 (extended), ExCode = 10
55 u32 PadEx10[15]; 55 u32 PadEx10[15];
56 // ExCode 11 = Read EEPROM Config 56 // ExCode 11 = Read EEPROM Config
57 u32 Config; // Code = 0 (extended), ExCode = 11 57 u32 Config; // Code = 0 (extended), ExCode = 11
58 u32 PadEx11[15]; 58 u32 PadEx11[15];
59 // ExCode 12 = Multicast bits 31:0 59 // ExCode 12 = Multicast bits 31:0
60 u32 McastLow; // Code = 0 (extended), ExCode = 12 60 u32 McastLow; // Code = 0 (extended), ExCode = 12
61 u32 PadEx12[15]; 61 u32 PadEx12[15];
62 // ExCode 13 = Multicast bits 63:32 62 // ExCode 13 = Multicast bits 63:32
63 u32 McastHigh; // Code = 0 (extended), ExCode = 13 63 u32 McastHigh; // Code = 0 (extended), ExCode = 13
64 u32 PadEx13[15]; 64 u32 PadEx13[15];
65 // ExCode 14 = Ping 65 // ExCode 14 = Ping
66 u32 Ping; // Code = 0 (extended), ExCode = 14 66 u32 Ping; // Code = 0 (extended), ExCode = 14
67 u32 PadEx14[15]; 67 u32 PadEx14[15];
68 // ExCode 15 = Link MTU 68 // ExCode 15 = Link MTU
69 u32 LinkMtu; // Code = 0 (extended), ExCode = 15 69 u32 LinkMtu; // Code = 0 (extended), ExCode = 15
70 u32 PadEx15[15]; 70 u32 PadEx15[15];
71 // ExCode 16 = Download synchronization 71 // ExCode 16 = Download synchronization
72 u32 LoadSync; // Code = 0 (extended), ExCode = 16 72 u32 LoadSync; // Code = 0 (extended), ExCode = 16
73 u32 PadEx16[15]; 73 u32 PadEx16[15];
74 // ExCode 17 = Upper DRAM address bits on 32-bit systems 74 // ExCode 17 = Upper DRAM address bits on 32-bit systems
75 u32 Upper; // Code = 0 (extended), ExCode = 17 75 u32 Upper; // Code = 0 (extended), ExCode = 17
76 u32 PadEx17[15]; 76 u32 PadEx17[15];
77 // ExCode 18 = Slowpath Send Index Address 77 // ExCode 18 = Slowpath Send Index Address
78 u32 SPSendIndex; // Code = 0 (extended), ExCode = 18 78 u32 SPSendIndex; // Code = 0 (extended), ExCode = 18
79 u32 PadEx18[15]; 79 u32 PadEx18[15];
80 u32 RsvdXF; // Code = 0 (extended), ExCode = 19 80 u32 RsvdXF; // Code = 0 (extended), ExCode = 19
81 u32 PadEx19[15]; 81 u32 PadEx19[15];
82 // ExCode 20 = Aggregation 82 // ExCode 20 = Aggregation
83 u32 Aggregation; // Code = 0 (extended), ExCode = 20 83 u32 Aggregation; // Code = 0 (extended), ExCode = 20
84 u32 PadEx20[15]; 84 u32 PadEx20[15];
85 // ExCode 21 = Receive MDL push timer 85 // ExCode 21 = Receive MDL push timer
86 u32 PushTicks; // Code = 0 (extended), ExCode = 21 86 u32 PushTicks; // Code = 0 (extended), ExCode = 21
87 u32 PadEx21[15]; 87 u32 PadEx21[15];
88 // ExCode 22 = TOE NA 88 // ExCode 22 = TOE NA
89 u32 AckFrequency; // Code = 0 (extended), ExCode = 22 89 u32 AckFrequency; // Code = 0 (extended), ExCode = 22
90 u32 PadEx22[15]; 90 u32 PadEx22[15];
91 // ExCode 23 = TOE NA 91 // ExCode 23 = TOE NA
92 u32 RsvdReg23; 92 u32 RsvdReg23;
93 u32 PadEx23[15]; 93 u32 PadEx23[15];
94 // ExCode 24 = TOE NA 94 // ExCode 24 = TOE NA
95 u32 RsvdReg24; 95 u32 RsvdReg24;
96 u32 PadEx24[15]; 96 u32 PadEx24[15];
97 // ExCode 25 = TOE NA 97 // ExCode 25 = TOE NA
98 u32 RsvdReg25; // Code = 0 (extended), ExCode = 25 98 u32 RsvdReg25; // Code = 0 (extended), ExCode = 25
99 u32 PadEx25[15]; 99 u32 PadEx25[15];
100 // ExCode 26 = Receive checksum requirements 100 // ExCode 26 = Receive checksum requirements
101 u32 ReceiveChecksum; // Code = 0 (extended), ExCode = 26 101 u32 ReceiveChecksum; // Code = 0 (extended), ExCode = 26
102 u32 PadEx26[15]; 102 u32 PadEx26[15];
103 // ExCode 27 = RSS Requirements 103 // ExCode 27 = RSS Requirements
104 u32 Rss; // Code = 0 (extended), ExCode = 27 104 u32 Rss; // Code = 0 (extended), ExCode = 27
105 u32 PadEx27[15]; 105 u32 PadEx27[15];
106 // ExCode 28 = RSS Table 106 // ExCode 28 = RSS Table
107 u32 RssTable; // Code = 0 (extended), ExCode = 28 107 u32 RssTable; // Code = 0 (extended), ExCode = 28
108 u32 PadEx28[15]; 108 u32 PadEx28[15];
109 // ExCode 29 = Event ring release entries 109 // ExCode 29 = Event ring release entries
110 u32 EventRelease; // Code = 0 (extended), ExCode = 29 110 u32 EventRelease; // Code = 0 (extended), ExCode = 29
111 u32 PadEx29[15]; 111 u32 PadEx29[15];
112 // ExCode 30 = Number of receive bufferlist commands on ring 0 112 // ExCode 30 = Number of receive bufferlist commands on ring 0
113 u32 RcvCmd; // Code = 0 (extended), ExCode = 30 113 u32 RcvCmd; // Code = 0 (extended), ExCode = 30
114 u32 PadEx30[15]; 114 u32 PadEx30[15];
115 // ExCode 31 = slowpath transmit command - Data[31:0] = 1 115 // ExCode 31 = slowpath transmit command - Data[31:0] = 1
116 u32 XmtCmd; // Code = 0 (extended), ExCode = 31 116 u32 XmtCmd; // Code = 0 (extended), ExCode = 31
117 u32 PadEx31[15]; 117 u32 PadEx31[15];
118 // ExCode 32 = Dump command 118 // ExCode 32 = Dump command
119 u32 DumpCmd; // Code = 0 (extended), ExCode = 32 119 u32 DumpCmd; // Code = 0 (extended), ExCode = 32
120 u32 PadEx32[15]; 120 u32 PadEx32[15];
121 // ExCode 33 = Debug command 121 // ExCode 33 = Debug command
122 u32 DebugCmd; // Code = 0 (extended), ExCode = 33 122 u32 DebugCmd; // Code = 0 (extended), ExCode = 33
123 u32 PadEx33[15]; 123 u32 PadEx33[15];
124 // There are 128 possible extended commands - each of account for 16 124 // There are 128 possible extended commands - each of account for 16
125 // words (including the non-relevent base command codes 1-15). 125 // words (including the non-relevent base command codes 1-15).
126 // Pad for the remainder of these here to bring us to the next CPU 126 // Pad for the remainder of these here to bring us to the next CPU
127 // base. As extended codes are added, reduce the first array value in 127 // base. As extended codes are added, reduce the first array value in
128 // the following field 128 // the following field
129 u32 PadToNextCpu[94][16]; // 94 = 128 - 34 (34 = Excodes 0 - 33) 129 u32 PadToNextCpu[94][16]; // 94 = 128 - 34 (34 = Excodes 0 - 33)
130} SXG_UCODE_REGS, *PSXG_UCODE_REGS; 130} SXG_UCODE_REGS, *PSXG_UCODE_REGS;
131 131
132// Interrupt control register (0) values 132// Interrupt control register (0) values
@@ -141,7 +141,7 @@ typedef struct _SXG_UCODE_REGS {
141 141
142// The Microcode supports up to 16 RSS queues 142// The Microcode supports up to 16 RSS queues
143#define SXG_MAX_RSS 16 143#define SXG_MAX_RSS 16
144#define SXG_MAX_RSS_TABLE_SIZE 256 // 256-byte max 144#define SXG_MAX_RSS_TABLE_SIZE 256 // 256-byte max
145 145
146#define SXG_RSS_TCP6 0x00000001 // RSS TCP over IPv6 146#define SXG_RSS_TCP6 0x00000001 // RSS TCP over IPv6
147#define SXG_RSS_TCP4 0x00000002 // RSS TCP over IPv4 147#define SXG_RSS_TCP4 0x00000002 // RSS TCP over IPv4
@@ -170,16 +170,16 @@ typedef struct _SXG_UCODE_REGS {
170 * SXG_UCODE_REGS definition above 170 * SXG_UCODE_REGS definition above
171 */ 171 */
172typedef struct _SXG_TCB_REGS { 172typedef struct _SXG_TCB_REGS {
173 u32 ExCode; /* Extended codes - see SXG_UCODE_REGS */ 173 u32 ExCode; /* Extended codes - see SXG_UCODE_REGS */
174 u32 Xmt; /* Code = 1 - # of Xmt descriptors added to ring */ 174 u32 Xmt; /* Code = 1 - # of Xmt descriptors added to ring */
175 u32 Rcv; /* Code = 2 - # of Rcv descriptors added to ring */ 175 u32 Rcv; /* Code = 2 - # of Rcv descriptors added to ring */
176 u32 Rsvd1; /* Code = 3 - TOE NA */ 176 u32 Rsvd1; /* Code = 3 - TOE NA */
177 u32 Rsvd2; /* Code = 4 - TOE NA */ 177 u32 Rsvd2; /* Code = 4 - TOE NA */
178 u32 Rsvd3; /* Code = 5 - TOE NA */ 178 u32 Rsvd3; /* Code = 5 - TOE NA */
179 u32 Invalid; /* Code = 6 - Reserved for "CardUp" see above */ 179 u32 Invalid; /* Code = 6 - Reserved for "CardUp" see above */
180 u32 Rsvd4; /* Code = 7 - TOE NA */ 180 u32 Rsvd4; /* Code = 7 - TOE NA */
181 u32 Rsvd5; /* Code = 8 - TOE NA */ 181 u32 Rsvd5; /* Code = 8 - TOE NA */
182 u32 Pad[7]; /* Codes 8-15 - Not used. */ 182 u32 Pad[7]; /* Codes 8-15 - Not used. */
183} SXG_TCB_REGS, *PSXG_TCB_REGS; 183} SXG_TCB_REGS, *PSXG_TCB_REGS;
184 184
185/*************************************************************************** 185/***************************************************************************
@@ -273,27 +273,27 @@ typedef struct _SXG_TCB_REGS {
273 */ 273 */
274#pragma pack(push, 1) 274#pragma pack(push, 1)
275typedef struct _SXG_EVENT { 275typedef struct _SXG_EVENT {
276 u32 Pad[1]; // not used 276 u32 Pad[1]; // not used
277 u32 SndUna; // SndUna value 277 u32 SndUna; // SndUna value
278 u32 Resid; // receive MDL resid 278 u32 Resid; // receive MDL resid
279 union { 279 union {
280 void * HostHandle; // Receive host handle 280 void *HostHandle; // Receive host handle
281 u32 Rsvd1; // TOE NA 281 u32 Rsvd1; // TOE NA
282 struct { 282 struct {
283 u32 NotUsed; 283 u32 NotUsed;
284 u32 Rsvd2; // TOE NA 284 u32 Rsvd2; // TOE NA
285 } Flush; 285 } Flush;
286 }; 286 };
287 u32 Toeplitz; // RSS Toeplitz hash 287 u32 Toeplitz; // RSS Toeplitz hash
288 union { 288 union {
289 ushort Rsvd3; // TOE NA 289 ushort Rsvd3; // TOE NA
290 ushort HdrOffset; // Slowpath 290 ushort HdrOffset; // Slowpath
291 }; 291 };
292 ushort Length; // 292 ushort Length; //
293 unsigned char Rsvd4; // TOE NA 293 unsigned char Rsvd4; // TOE NA
294 unsigned char Code; // Event code 294 unsigned char Code; // Event code
295 unsigned char CommandIndex; // New ring index 295 unsigned char CommandIndex; // New ring index
296 unsigned char Status; // Event status 296 unsigned char Status; // Event status
297} SXG_EVENT, *PSXG_EVENT; 297} SXG_EVENT, *PSXG_EVENT;
298#pragma pack(pop) 298#pragma pack(pop)
299 299
@@ -318,12 +318,12 @@ typedef struct _SXG_EVENT {
318// Event ring 318// Event ring
319// Size must be power of 2, between 128 and 16k 319// Size must be power of 2, between 128 and 16k
320#define EVENT_RING_SIZE 4096 // ?? 320#define EVENT_RING_SIZE 4096 // ??
321#define EVENT_RING_BATCH 16 // Hand entries back 16 at a time. 321#define EVENT_RING_BATCH 16 // Hand entries back 16 at a time.
322#define EVENT_BATCH_LIMIT 256 // Stop processing events after 256 (16 * 16) 322#define EVENT_BATCH_LIMIT 256 // Stop processing events after 256 (16 * 16)
323 323
324typedef struct _SXG_EVENT_RING { 324typedef struct _SXG_EVENT_RING {
325 SXG_EVENT Ring[EVENT_RING_SIZE]; 325 SXG_EVENT Ring[EVENT_RING_SIZE];
326}SXG_EVENT_RING, *PSXG_EVENT_RING; 326} SXG_EVENT_RING, *PSXG_EVENT_RING;
327 327
328/*************************************************************************** 328/***************************************************************************
329 * 329 *
@@ -341,7 +341,7 @@ typedef struct _SXG_EVENT_RING {
341#define SXG_TCB_PER_BUCKET 16 341#define SXG_TCB_PER_BUCKET 16
342#define SXG_TCB_BUCKET_MASK 0xFF0 // Bucket portion of TCB ID 342#define SXG_TCB_BUCKET_MASK 0xFF0 // Bucket portion of TCB ID
343#define SXG_TCB_ELEMENT_MASK 0x00F // Element within bucket 343#define SXG_TCB_ELEMENT_MASK 0x00F // Element within bucket
344#define SXG_TCB_BUCKETS 256 // 256 * 16 = 4k 344#define SXG_TCB_BUCKETS 256 // 256 * 16 = 4k
345 345
346#define SXG_TCB_BUFFER_SIZE 512 // ASSERT format is correct 346#define SXG_TCB_BUFFER_SIZE 512 // ASSERT format is correct
347 347
@@ -368,7 +368,6 @@ typedef struct _SXG_EVENT_RING {
368 &(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.Ip : \ 368 &(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.Ip : \
369 &(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.Ip 369 &(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.Ip
370 370
371
372#if DBG 371#if DBG
373// Horrible kludge to distinguish dumb-nic, slowpath, and 372// Horrible kludge to distinguish dumb-nic, slowpath, and
374// fastpath traffic. Decrement the HopLimit by one 373// fastpath traffic. Decrement the HopLimit by one
@@ -396,16 +395,16 @@ typedef struct _SXG_EVENT_RING {
396 * Receive and transmit rings 395 * Receive and transmit rings
397 ***************************************************************************/ 396 ***************************************************************************/
398#define SXG_MAX_RING_SIZE 256 397#define SXG_MAX_RING_SIZE 256
399#define SXG_XMT_RING_SIZE 128 // Start with 128 398#define SXG_XMT_RING_SIZE 128 // Start with 128
400#define SXG_RCV_RING_SIZE 128 // Start with 128 399#define SXG_RCV_RING_SIZE 128 // Start with 128
401#define SXG_MAX_ENTRIES 4096 400#define SXG_MAX_ENTRIES 4096
402 401
403// Structure and macros to manage a ring 402// Structure and macros to manage a ring
404typedef struct _SXG_RING_INFO { 403typedef struct _SXG_RING_INFO {
405 unsigned char Head; // Where we add entries - Note unsigned char:RING_SIZE 404 unsigned char Head; // Where we add entries - Note unsigned char:RING_SIZE
406 unsigned char Tail; // Where we pull off completed entries 405 unsigned char Tail; // Where we pull off completed entries
407 ushort Size; // Ring size - Must be multiple of 2 406 ushort Size; // Ring size - Must be multiple of 2
408 void * Context[SXG_MAX_RING_SIZE]; // Shadow ring 407 void *Context[SXG_MAX_RING_SIZE]; // Shadow ring
409} SXG_RING_INFO, *PSXG_RING_INFO; 408} SXG_RING_INFO, *PSXG_RING_INFO;
410 409
411#define SXG_INITIALIZE_RING(_ring, _size) { \ 410#define SXG_INITIALIZE_RING(_ring, _size) { \
@@ -483,40 +482,40 @@ typedef struct _SXG_RING_INFO {
483 */ 482 */
484#pragma pack(push, 1) 483#pragma pack(push, 1)
485typedef struct _SXG_CMD { 484typedef struct _SXG_CMD {
486 dma_addr_t Sgl; // Physical address of SGL 485 dma_addr_t Sgl; // Physical address of SGL
487 union { 486 union {
488 struct { 487 struct {
489 dma64_addr_t FirstSgeAddress;// Address of first SGE 488 dma64_addr_t FirstSgeAddress; // Address of first SGE
490 u32 FirstSgeLength; // Length of first SGE 489 u32 FirstSgeLength; // Length of first SGE
491 union { 490 union {
492 u32 Rsvd1; // TOE NA 491 u32 Rsvd1; // TOE NA
493 u32 SgeOffset; // Slowpath - 2nd SGE offset 492 u32 SgeOffset; // Slowpath - 2nd SGE offset
494 u32 Resid; // MDL completion - clobbers update 493 u32 Resid; // MDL completion - clobbers update
495 }; 494 };
496 union { 495 union {
497 u32 TotalLength; // Total transfer length 496 u32 TotalLength; // Total transfer length
498 u32 Mss; // LSO MSS 497 u32 Mss; // LSO MSS
499 }; 498 };
500 } Buffer; 499 } Buffer;
501 }; 500 };
502 union { 501 union {
503 struct { 502 struct {
504 unsigned char Flags:4; // slowpath flags 503 unsigned char Flags:4; // slowpath flags
505 unsigned char IpHl:4; // Ip header length (>>2) 504 unsigned char IpHl:4; // Ip header length (>>2)
506 unsigned char MacLen; // Mac header len 505 unsigned char MacLen; // Mac header len
507 } CsumFlags; 506 } CsumFlags;
508 struct { 507 struct {
509 ushort Flags:4; // slowpath flags 508 ushort Flags:4; // slowpath flags
510 ushort TcpHdrOff:7; // TCP 509 ushort TcpHdrOff:7; // TCP
511 ushort MacLen:5; // Mac header len 510 ushort MacLen:5; // Mac header len
512 } LsoFlags; 511 } LsoFlags;
513 ushort Flags; // flags 512 ushort Flags; // flags
514 }; 513 };
515 union { 514 union {
516 ushort SgEntries; // SG entry count including first sge 515 ushort SgEntries; // SG entry count including first sge
517 struct { 516 struct {
518 unsigned char Status; // Copied from event status 517 unsigned char Status; // Copied from event status
519 unsigned char NotUsed; 518 unsigned char NotUsed;
520 } Status; 519 } Status;
521 }; 520 };
522} SXG_CMD, *PSXG_CMD; 521} SXG_CMD, *PSXG_CMD;
@@ -524,8 +523,8 @@ typedef struct _SXG_CMD {
524 523
525#pragma pack(push, 1) 524#pragma pack(push, 1)
526typedef struct _VLAN_HDR { 525typedef struct _VLAN_HDR {
527 ushort VlanTci; 526 ushort VlanTci;
528 ushort VlanTpid; 527 ushort VlanTpid;
529} VLAN_HDR, *PVLAN_HDR; 528} VLAN_HDR, *PVLAN_HDR;
530#pragma pack(pop) 529#pragma pack(pop)
531 530
@@ -561,16 +560,16 @@ typedef struct _VLAN_HDR {
561 * 560 *
562 */ 561 */
563// Slowpath CMD flags 562// Slowpath CMD flags
564#define SXG_SLOWCMD_CSUM_IP 0x01 // Checksum IP 563#define SXG_SLOWCMD_CSUM_IP 0x01 // Checksum IP
565#define SXG_SLOWCMD_CSUM_TCP 0x02 // Checksum TCP 564#define SXG_SLOWCMD_CSUM_TCP 0x02 // Checksum TCP
566#define SXG_SLOWCMD_LSO 0x04 // Large segment send 565#define SXG_SLOWCMD_LSO 0x04 // Large segment send
567 566
568typedef struct _SXG_XMT_RING { 567typedef struct _SXG_XMT_RING {
569 SXG_CMD Descriptors[SXG_XMT_RING_SIZE]; 568 SXG_CMD Descriptors[SXG_XMT_RING_SIZE];
570} SXG_XMT_RING, *PSXG_XMT_RING; 569} SXG_XMT_RING, *PSXG_XMT_RING;
571 570
572typedef struct _SXG_RCV_RING { 571typedef struct _SXG_RCV_RING {
573 SXG_CMD Descriptors[SXG_RCV_RING_SIZE]; 572 SXG_CMD Descriptors[SXG_RCV_RING_SIZE];
574} SXG_RCV_RING, *PSXG_RCV_RING; 573} SXG_RCV_RING, *PSXG_RCV_RING;
575 574
576/*************************************************************************** 575/***************************************************************************
@@ -578,8 +577,8 @@ typedef struct _SXG_RCV_RING {
578 * shared memory allocation 577 * shared memory allocation
579 ***************************************************************************/ 578 ***************************************************************************/
580typedef enum { 579typedef enum {
581 SXG_BUFFER_TYPE_RCV, // Receive buffer 580 SXG_BUFFER_TYPE_RCV, // Receive buffer
582 SXG_BUFFER_TYPE_SGL // SGL buffer 581 SXG_BUFFER_TYPE_SGL // SGL buffer
583} SXG_BUFFER_TYPE; 582} SXG_BUFFER_TYPE;
584 583
585// State for SXG buffers 584// State for SXG buffers
@@ -668,60 +667,60 @@ typedef enum {
668#define SXG_RCV_DATA_BUFFERS 4096 // Amount to give to the card 667#define SXG_RCV_DATA_BUFFERS 4096 // Amount to give to the card
669#define SXG_INITIAL_RCV_DATA_BUFFERS 8192 // Initial pool of buffers 668#define SXG_INITIAL_RCV_DATA_BUFFERS 8192 // Initial pool of buffers
670#define SXG_MIN_RCV_DATA_BUFFERS 2048 // Minimum amount and when to get more 669#define SXG_MIN_RCV_DATA_BUFFERS 2048 // Minimum amount and when to get more
671#define SXG_MAX_RCV_BLOCKS 128 // = 16384 receive buffers 670#define SXG_MAX_RCV_BLOCKS 128 // = 16384 receive buffers
672 671
673// Receive buffer header 672// Receive buffer header
674typedef struct _SXG_RCV_DATA_BUFFER_HDR { 673typedef struct _SXG_RCV_DATA_BUFFER_HDR {
675 dma_addr_t PhysicalAddress; // Buffer physical address 674 dma_addr_t PhysicalAddress; // Buffer physical address
676 // Note - DO NOT USE the VirtualAddress field to locate data. 675 // Note - DO NOT USE the VirtualAddress field to locate data.
677 // Use the sxg.h:SXG_RECEIVE_DATA_LOCATION macro instead. 676 // Use the sxg.h:SXG_RECEIVE_DATA_LOCATION macro instead.
678 void *VirtualAddress; // Start of buffer 677 void *VirtualAddress; // Start of buffer
679 LIST_ENTRY FreeList; // Free queue of buffers 678 LIST_ENTRY FreeList; // Free queue of buffers
680 struct _SXG_RCV_DATA_BUFFER_HDR *Next; // Fastpath data buffer queue 679 struct _SXG_RCV_DATA_BUFFER_HDR *Next; // Fastpath data buffer queue
681 u32 Size; // Buffer size 680 u32 Size; // Buffer size
682 u32 ByteOffset; // See SXG_RESTORE_MDL_OFFSET 681 u32 ByteOffset; // See SXG_RESTORE_MDL_OFFSET
683 unsigned char State; // See SXG_BUFFER state above 682 unsigned char State; // See SXG_BUFFER state above
684 unsigned char Status; // Event status (to log PUSH) 683 unsigned char Status; // Event status (to log PUSH)
685 struct sk_buff * skb; // Double mapped (nbl and pkt) 684 struct sk_buff *skb; // Double mapped (nbl and pkt)
686} SXG_RCV_DATA_BUFFER_HDR, *PSXG_RCV_DATA_BUFFER_HDR; 685} SXG_RCV_DATA_BUFFER_HDR, *PSXG_RCV_DATA_BUFFER_HDR;
687 686
688// SxgSlowReceive uses the PACKET (skb) contained 687// SxgSlowReceive uses the PACKET (skb) contained
689// in the SXG_RCV_DATA_BUFFER_HDR when indicating dumb-nic data 688// in the SXG_RCV_DATA_BUFFER_HDR when indicating dumb-nic data
690#define SxgDumbRcvPacket skb 689#define SxgDumbRcvPacket skb
691 690
692#define SXG_RCV_DATA_HDR_SIZE 256 // Space for SXG_RCV_DATA_BUFFER_HDR 691#define SXG_RCV_DATA_HDR_SIZE 256 // Space for SXG_RCV_DATA_BUFFER_HDR
693#define SXG_RCV_DATA_BUFFER_SIZE 2048 // Non jumbo = 2k including HDR 692#define SXG_RCV_DATA_BUFFER_SIZE 2048 // Non jumbo = 2k including HDR
694#define SXG_RCV_JUMBO_BUFFER_SIZE 10240 // jumbo = 10k including HDR 693#define SXG_RCV_JUMBO_BUFFER_SIZE 10240 // jumbo = 10k including HDR
695 694
696// Receive data descriptor 695// Receive data descriptor
697typedef struct _SXG_RCV_DATA_DESCRIPTOR { 696typedef struct _SXG_RCV_DATA_DESCRIPTOR {
698 union { 697 union {
699 struct sk_buff * VirtualAddress; // Host handle 698 struct sk_buff *VirtualAddress; // Host handle
700 u64 ForceTo8Bytes; // Force x86 to 8-byte boundary 699 u64 ForceTo8Bytes; // Force x86 to 8-byte boundary
701 }; 700 };
702 dma_addr_t PhysicalAddress; 701 dma_addr_t PhysicalAddress;
703} SXG_RCV_DATA_DESCRIPTOR, *PSXG_RCV_DATA_DESCRIPTOR; 702} SXG_RCV_DATA_DESCRIPTOR, *PSXG_RCV_DATA_DESCRIPTOR;
704 703
705// Receive descriptor block 704// Receive descriptor block
706#define SXG_RCV_DESCRIPTORS_PER_BLOCK 128 705#define SXG_RCV_DESCRIPTORS_PER_BLOCK 128
707#define SXG_RCV_DESCRIPTOR_BLOCK_SIZE 2048 // For sanity check 706#define SXG_RCV_DESCRIPTOR_BLOCK_SIZE 2048 // For sanity check
708typedef struct _SXG_RCV_DESCRIPTOR_BLOCK { 707typedef struct _SXG_RCV_DESCRIPTOR_BLOCK {
709 SXG_RCV_DATA_DESCRIPTOR Descriptors[SXG_RCV_DESCRIPTORS_PER_BLOCK]; 708 SXG_RCV_DATA_DESCRIPTOR Descriptors[SXG_RCV_DESCRIPTORS_PER_BLOCK];
710} SXG_RCV_DESCRIPTOR_BLOCK, *PSXG_RCV_DESCRIPTOR_BLOCK; 709} SXG_RCV_DESCRIPTOR_BLOCK, *PSXG_RCV_DESCRIPTOR_BLOCK;
711 710
712// Receive descriptor block header 711// Receive descriptor block header
713typedef struct _SXG_RCV_DESCRIPTOR_BLOCK_HDR { 712typedef struct _SXG_RCV_DESCRIPTOR_BLOCK_HDR {
714 void * VirtualAddress; // Start of 2k buffer 713 void *VirtualAddress; // Start of 2k buffer
715 dma_addr_t PhysicalAddress; // ..and it's physical address 714 dma_addr_t PhysicalAddress; // ..and it's physical address
716 LIST_ENTRY FreeList; // Free queue of descriptor blocks 715 LIST_ENTRY FreeList; // Free queue of descriptor blocks
717 unsigned char State; // See SXG_BUFFER state above 716 unsigned char State; // See SXG_BUFFER state above
718} SXG_RCV_DESCRIPTOR_BLOCK_HDR, *PSXG_RCV_DESCRIPTOR_BLOCK_HDR; 717} SXG_RCV_DESCRIPTOR_BLOCK_HDR, *PSXG_RCV_DESCRIPTOR_BLOCK_HDR;
719 718
720// Receive block header 719// Receive block header
721typedef struct _SXG_RCV_BLOCK_HDR { 720typedef struct _SXG_RCV_BLOCK_HDR {
722 void * VirtualAddress; // Start of virtual memory 721 void *VirtualAddress; // Start of virtual memory
723 dma_addr_t PhysicalAddress; // ..and it's physical address 722 dma_addr_t PhysicalAddress; // ..and it's physical address
724 LIST_ENTRY AllList; // Queue of all SXG_RCV_BLOCKS 723 LIST_ENTRY AllList; // Queue of all SXG_RCV_BLOCKS
725} SXG_RCV_BLOCK_HDR, *PSXG_RCV_BLOCK_HDR; 724} SXG_RCV_BLOCK_HDR, *PSXG_RCV_BLOCK_HDR;
726 725
727// Macros to determine data structure offsets into receive block 726// Macros to determine data structure offsets into receive block
@@ -747,8 +746,8 @@ typedef struct _SXG_RCV_BLOCK_HDR {
747// Use the miniport reserved portion of the NBL to locate 746// Use the miniport reserved portion of the NBL to locate
748// our SXG_RCV_DATA_BUFFER_HDR structure. 747// our SXG_RCV_DATA_BUFFER_HDR structure.
749typedef struct _SXG_RCV_NBL_RESERVED { 748typedef struct _SXG_RCV_NBL_RESERVED {
750 PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr; 749 PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr;
751 void * Available; 750 void *Available;
752} SXG_RCV_NBL_RESERVED, *PSXG_RCV_NBL_RESERVED; 751} SXG_RCV_NBL_RESERVED, *PSXG_RCV_NBL_RESERVED;
753 752
754#define SXG_RCV_NBL_BUFFER_HDR(_NBL) (((PSXG_RCV_NBL_RESERVED)NET_BUFFER_LIST_MINIPORT_RESERVED(_NBL))->RcvDataBufferHdr) 753#define SXG_RCV_NBL_BUFFER_HDR(_NBL) (((PSXG_RCV_NBL_RESERVED)NET_BUFFER_LIST_MINIPORT_RESERVED(_NBL))->RcvDataBufferHdr)
@@ -760,12 +759,11 @@ typedef struct _SXG_RCV_NBL_RESERVED {
760#define SXG_MIN_SGL_BUFFERS 2048 // Minimum amount and when to get more 759#define SXG_MIN_SGL_BUFFERS 2048 // Minimum amount and when to get more
761#define SXG_MAX_SGL_BUFFERS 16384 // Maximum to allocate (note ADAPT:ushort) 760#define SXG_MAX_SGL_BUFFERS 16384 // Maximum to allocate (note ADAPT:ushort)
762 761
763
764// Self identifying structure type 762// Self identifying structure type
765typedef enum _SXG_SGL_TYPE { 763typedef enum _SXG_SGL_TYPE {
766 SXG_SGL_DUMB, // Dumb NIC SGL 764 SXG_SGL_DUMB, // Dumb NIC SGL
767 SXG_SGL_SLOW, // Slowpath protocol header - see below 765 SXG_SGL_SLOW, // Slowpath protocol header - see below
768 SXG_SGL_CHIMNEY // Chimney offload SGL 766 SXG_SGL_CHIMNEY // Chimney offload SGL
769} SXG_SGL_TYPE, PSXG_SGL_TYPE; 767} SXG_SGL_TYPE, PSXG_SGL_TYPE;
770 768
771// Note - the description below is Microsoft specific 769// Note - the description below is Microsoft specific
@@ -774,14 +772,14 @@ typedef enum _SXG_SGL_TYPE {
774// for the SCATTER_GATHER_LIST portion of the SXG_SCATTER_GATHER data structure. 772// for the SCATTER_GATHER_LIST portion of the SXG_SCATTER_GATHER data structure.
775// The following considerations apply when setting this value: 773// The following considerations apply when setting this value:
776// - First, the Sahara card is designed to read the Microsoft SGL structure 774// - First, the Sahara card is designed to read the Microsoft SGL structure
777// straight out of host memory. This means that the SGL must reside in 775// straight out of host memory. This means that the SGL must reside in
778// shared memory. If the length here is smaller than the SGL for the 776// shared memory. If the length here is smaller than the SGL for the
779// NET_BUFFER, then NDIS will allocate its own buffer. The buffer 777// NET_BUFFER, then NDIS will allocate its own buffer. The buffer
780// that NDIS allocates is not in shared memory, so when this happens, 778// that NDIS allocates is not in shared memory, so when this happens,
781// the SGL will need to be copied to a set of SXG_SCATTER_GATHER buffers. 779// the SGL will need to be copied to a set of SXG_SCATTER_GATHER buffers.
782// In other words.. we don't want this value to be too small. 780// In other words.. we don't want this value to be too small.
783// - On the other hand.. we're allocating up to 16k of these things. If 781// - On the other hand.. we're allocating up to 16k of these things. If
784// we make this too big, we start to consume a ton of memory.. 782// we make this too big, we start to consume a ton of memory..
785// At the moment, I'm going to limit the number of SG entries to 150. 783// At the moment, I'm going to limit the number of SG entries to 150.
786// If each entry maps roughly 4k, then this should cover roughly 600kB 784// If each entry maps roughly 4k, then this should cover roughly 600kB
787// NET_BUFFERs. Furthermore, since each entry is 24 bytes, the total 785// NET_BUFFERs. Furthermore, since each entry is 24 bytes, the total
@@ -801,24 +799,23 @@ typedef enum _SXG_SGL_TYPE {
801// the SGL. The following structure defines an x64 799// the SGL. The following structure defines an x64
802// formatted SGL entry 800// formatted SGL entry
803typedef struct _SXG_X64_SGE { 801typedef struct _SXG_X64_SGE {
804 dma64_addr_t Address; // same as wdm.h 802 dma64_addr_t Address; // same as wdm.h
805 u32 Length; // same as wdm.h 803 u32 Length; // same as wdm.h
806 u32 CompilerPad;// The compiler pads to 8-bytes 804 u32 CompilerPad; // The compiler pads to 8-bytes
807 u64 Reserved; // u32 * in wdm.h. Force to 8 bytes 805 u64 Reserved; // u32 * in wdm.h. Force to 8 bytes
808} SXG_X64_SGE, *PSXG_X64_SGE; 806} SXG_X64_SGE, *PSXG_X64_SGE;
809 807
810typedef struct _SCATTER_GATHER_ELEMENT { 808typedef struct _SCATTER_GATHER_ELEMENT {
811 dma64_addr_t Address; // same as wdm.h 809 dma64_addr_t Address; // same as wdm.h
812 u32 Length; // same as wdm.h 810 u32 Length; // same as wdm.h
813 u32 CompilerPad;// The compiler pads to 8-bytes 811 u32 CompilerPad; // The compiler pads to 8-bytes
814 u64 Reserved; // u32 * in wdm.h. Force to 8 bytes 812 u64 Reserved; // u32 * in wdm.h. Force to 8 bytes
815} SCATTER_GATHER_ELEMENT, *PSCATTER_GATHER_ELEMENT; 813} SCATTER_GATHER_ELEMENT, *PSCATTER_GATHER_ELEMENT;
816 814
817
818typedef struct _SCATTER_GATHER_LIST { 815typedef struct _SCATTER_GATHER_LIST {
819 u32 NumberOfElements; 816 u32 NumberOfElements;
820 u32 * Reserved; 817 u32 *Reserved;
821 SCATTER_GATHER_ELEMENT Elements[]; 818 SCATTER_GATHER_ELEMENT Elements[];
822} SCATTER_GATHER_LIST, *PSCATTER_GATHER_LIST; 819} SCATTER_GATHER_LIST, *PSCATTER_GATHER_LIST;
823 820
824// The card doesn't care about anything except elements, so 821// The card doesn't care about anything except elements, so
@@ -826,26 +823,26 @@ typedef struct _SCATTER_GATHER_LIST {
826// SGL structure. But redefine from wdm.h:SCATTER_GATHER_LIST so 823// SGL structure. But redefine from wdm.h:SCATTER_GATHER_LIST so
827// we can specify SXG_X64_SGE and define a fixed number of elements 824// we can specify SXG_X64_SGE and define a fixed number of elements
828typedef struct _SXG_X64_SGL { 825typedef struct _SXG_X64_SGL {
829 u32 NumberOfElements; 826 u32 NumberOfElements;
830 u32 * Reserved; 827 u32 *Reserved;
831 SXG_X64_SGE Elements[SXG_SGL_ENTRIES]; 828 SXG_X64_SGE Elements[SXG_SGL_ENTRIES];
832} SXG_X64_SGL, *PSXG_X64_SGL; 829} SXG_X64_SGL, *PSXG_X64_SGL;
833 830
834typedef struct _SXG_SCATTER_GATHER { 831typedef struct _SXG_SCATTER_GATHER {
835 SXG_SGL_TYPE Type; // FIRST! Dumb-nic or offload 832 SXG_SGL_TYPE Type; // FIRST! Dumb-nic or offload
836 void * adapter; // Back pointer to adapter 833 void *adapter; // Back pointer to adapter
837 LIST_ENTRY FreeList; // Free SXG_SCATTER_GATHER blocks 834 LIST_ENTRY FreeList; // Free SXG_SCATTER_GATHER blocks
838 LIST_ENTRY AllList; // All SXG_SCATTER_GATHER blocks 835 LIST_ENTRY AllList; // All SXG_SCATTER_GATHER blocks
839 dma_addr_t PhysicalAddress;// physical address 836 dma_addr_t PhysicalAddress; // physical address
840 unsigned char State; // See SXG_BUFFER state above 837 unsigned char State; // See SXG_BUFFER state above
841 unsigned char CmdIndex; // Command ring index 838 unsigned char CmdIndex; // Command ring index
842 struct sk_buff * DumbPacket; // Associated Packet 839 struct sk_buff *DumbPacket; // Associated Packet
843 u32 Direction; // For asynchronous completions 840 u32 Direction; // For asynchronous completions
844 u32 CurOffset; // Current SGL offset 841 u32 CurOffset; // Current SGL offset
845 u32 SglRef; // SGL reference count 842 u32 SglRef; // SGL reference count
846 VLAN_HDR VlanTag; // VLAN tag to be inserted into SGL 843 VLAN_HDR VlanTag; // VLAN tag to be inserted into SGL
847 PSCATTER_GATHER_LIST pSgl; // SGL Addr. Possibly &Sgl 844 PSCATTER_GATHER_LIST pSgl; // SGL Addr. Possibly &Sgl
848 SXG_X64_SGL Sgl; // SGL handed to card 845 SXG_X64_SGL Sgl; // SGL handed to card
849} SXG_SCATTER_GATHER, *PSXG_SCATTER_GATHER; 846} SXG_SCATTER_GATHER, *PSXG_SCATTER_GATHER;
850 847
851#if defined(CONFIG_X86_64) 848#if defined(CONFIG_X86_64)
@@ -856,6 +853,5 @@ typedef struct _SXG_SCATTER_GATHER {
856#define SXG_SGL_BUFFER(_SxgSgl) NULL 853#define SXG_SGL_BUFFER(_SxgSgl) NULL
857#define SXG_SGL_BUF_SIZE 0 854#define SXG_SGL_BUF_SIZE 0
858#else 855#else
859 Stop Compilation; 856Stop Compilation;
860#endif 857#endif
861
diff --git a/drivers/staging/sxg/sxghw.h b/drivers/staging/sxg/sxghw.h
index 8f4f6effdd98..2222ae91fd97 100644
--- a/drivers/staging/sxg/sxghw.h
+++ b/drivers/staging/sxg/sxghw.h
@@ -13,11 +13,11 @@
13/******************************************************************************* 13/*******************************************************************************
14 * Configuration space 14 * Configuration space
15 *******************************************************************************/ 15 *******************************************************************************/
16// PCI Vendor ID 16/* PCI Vendor ID */
17#define SXG_VENDOR_ID 0x139A // Alacritech's Vendor ID 17#define SXG_VENDOR_ID 0x139A /* Alacritech's Vendor ID */
18 18
19// PCI Device ID 19// PCI Device ID
20#define SXG_DEVICE_ID 0x0009 // Sahara Device ID 20#define SXG_DEVICE_ID 0x0009 /* Sahara Device ID */
21 21
22// 22//
23// Subsystem IDs. 23// Subsystem IDs.
@@ -141,7 +141,7 @@ typedef struct _SXG_HW_REGS {
141#define SXG_REGISTER_SIZE_PER_CPU 0x00002000 // Used to sanity check UCODE_REGS structure 141#define SXG_REGISTER_SIZE_PER_CPU 0x00002000 // Used to sanity check UCODE_REGS structure
142 142
143// Sahara receive sequencer status values 143// Sahara receive sequencer status values
144#define SXG_RCV_STATUS_ATTN 0x80000000 // Attention 144#define SXG_RCV_STATUS_ATTN 0x80000000 // Attention
145#define SXG_RCV_STATUS_TRANSPORT_MASK 0x3F000000 // Transport mask 145#define SXG_RCV_STATUS_TRANSPORT_MASK 0x3F000000 // Transport mask
146#define SXG_RCV_STATUS_TRANSPORT_ERROR 0x20000000 // Transport error 146#define SXG_RCV_STATUS_TRANSPORT_ERROR 0x20000000 // Transport error
147#define SXG_RCV_STATUS_TRANSPORT_CSUM 0x23000000 // Transport cksum error 147#define SXG_RCV_STATUS_TRANSPORT_CSUM 0x23000000 // Transport cksum error
@@ -156,9 +156,9 @@ typedef struct _SXG_HW_REGS {
156#define SXG_RCV_STATUS_TRANSPORT_FTP 0x03000000 // Transport FTP 156#define SXG_RCV_STATUS_TRANSPORT_FTP 0x03000000 // Transport FTP
157#define SXG_RCV_STATUS_TRANSPORT_HTTP 0x02000000 // Transport HTTP 157#define SXG_RCV_STATUS_TRANSPORT_HTTP 0x02000000 // Transport HTTP
158#define SXG_RCV_STATUS_TRANSPORT_SMB 0x01000000 // Transport SMB 158#define SXG_RCV_STATUS_TRANSPORT_SMB 0x01000000 // Transport SMB
159#define SXG_RCV_STATUS_NETWORK_MASK 0x00FF0000 // Network mask 159#define SXG_RCV_STATUS_NETWORK_MASK 0x00FF0000 // Network mask
160#define SXG_RCV_STATUS_NETWORK_ERROR 0x00800000 // Network error 160#define SXG_RCV_STATUS_NETWORK_ERROR 0x00800000 // Network error
161#define SXG_RCV_STATUS_NETWORK_CSUM 0x00830000 // Network cksum error 161#define SXG_RCV_STATUS_NETWORK_CSUM 0x00830000 // Network cksum error
162#define SXG_RCV_STATUS_NETWORK_UFLOW 0x00820000 // Network underflow error 162#define SXG_RCV_STATUS_NETWORK_UFLOW 0x00820000 // Network underflow error
163#define SXG_RCV_STATUS_NETWORK_HDRLEN 0x00800000 // Network header length 163#define SXG_RCV_STATUS_NETWORK_HDRLEN 0x00800000 // Network header length
164#define SXG_RCV_STATUS_NETWORK_OFLOW 0x00400000 // Network overflow detected 164#define SXG_RCV_STATUS_NETWORK_OFLOW 0x00400000 // Network overflow detected
@@ -167,67 +167,67 @@ typedef struct _SXG_HW_REGS {
167#define SXG_RCV_STATUS_NETWORK_OFFSET 0x00080000 // Network offset detected 167#define SXG_RCV_STATUS_NETWORK_OFFSET 0x00080000 // Network offset detected
168#define SXG_RCV_STATUS_NETWORK_FRAGMENT 0x00040000 // Network fragment detected 168#define SXG_RCV_STATUS_NETWORK_FRAGMENT 0x00040000 // Network fragment detected
169#define SXG_RCV_STATUS_NETWORK_TRANS_MASK 0x00030000 // Network transport type mask 169#define SXG_RCV_STATUS_NETWORK_TRANS_MASK 0x00030000 // Network transport type mask
170#define SXG_RCV_STATUS_NETWORK_UDP 0x00020000 // UDP 170#define SXG_RCV_STATUS_NETWORK_UDP 0x00020000 // UDP
171#define SXG_RCV_STATUS_NETWORK_TCP 0x00010000 // TCP 171#define SXG_RCV_STATUS_NETWORK_TCP 0x00010000 // TCP
172#define SXG_RCV_STATUS_IPONLY 0x00008000 // IP-only not TCP 172#define SXG_RCV_STATUS_IPONLY 0x00008000 // IP-only not TCP
173#define SXG_RCV_STATUS_PKT_PRI 0x00006000 // Receive priority 173#define SXG_RCV_STATUS_PKT_PRI 0x00006000 // Receive priority
174#define SXG_RCV_STATUS_PKT_PRI_SHFT 13 // Receive priority shift 174#define SXG_RCV_STATUS_PKT_PRI_SHFT 13 // Receive priority shift
175#define SXG_RCV_STATUS_PARITY 0x00001000 // MAC Receive RAM parity error 175#define SXG_RCV_STATUS_PARITY 0x00001000 // MAC Receive RAM parity error
176#define SXG_RCV_STATUS_ADDRESS_MASK 0x00000F00 // Link address detection mask 176#define SXG_RCV_STATUS_ADDRESS_MASK 0x00000F00 // Link address detection mask
177#define SXG_RCV_STATUS_ADDRESS_D 0x00000B00 // Link address D 177#define SXG_RCV_STATUS_ADDRESS_D 0x00000B00 // Link address D
178#define SXG_RCV_STATUS_ADDRESS_C 0x00000A00 // Link address C 178#define SXG_RCV_STATUS_ADDRESS_C 0x00000A00 // Link address C
179#define SXG_RCV_STATUS_ADDRESS_B 0x00000900 // Link address B 179#define SXG_RCV_STATUS_ADDRESS_B 0x00000900 // Link address B
180#define SXG_RCV_STATUS_ADDRESS_A 0x00000800 // Link address A 180#define SXG_RCV_STATUS_ADDRESS_A 0x00000800 // Link address A
181#define SXG_RCV_STATUS_ADDRESS_BCAST 0x00000300 // Link address broadcast 181#define SXG_RCV_STATUS_ADDRESS_BCAST 0x00000300 // Link address broadcast
182#define SXG_RCV_STATUS_ADDRESS_MCAST 0x00000200 // Link address multicast 182#define SXG_RCV_STATUS_ADDRESS_MCAST 0x00000200 // Link address multicast
183#define SXG_RCV_STATUS_ADDRESS_CMCAST 0x00000100 // Link control multicast 183#define SXG_RCV_STATUS_ADDRESS_CMCAST 0x00000100 // Link control multicast
184#define SXG_RCV_STATUS_LINK_MASK 0x000000FF // Link status mask 184#define SXG_RCV_STATUS_LINK_MASK 0x000000FF // Link status mask
185#define SXG_RCV_STATUS_LINK_ERROR 0x00000080 // Link error 185#define SXG_RCV_STATUS_LINK_ERROR 0x00000080 // Link error
186#define SXG_RCV_STATUS_LINK_MASK 0x000000FF // Link status mask 186#define SXG_RCV_STATUS_LINK_MASK 0x000000FF // Link status mask
187#define SXG_RCV_STATUS_LINK_PARITY 0x00000087 // RcvMacQ parity error 187#define SXG_RCV_STATUS_LINK_PARITY 0x00000087 // RcvMacQ parity error
188#define SXG_RCV_STATUS_LINK_EARLY 0x00000086 // Data early 188#define SXG_RCV_STATUS_LINK_EARLY 0x00000086 // Data early
189#define SXG_RCV_STATUS_LINK_BUFOFLOW 0x00000085 // Buffer overflow 189#define SXG_RCV_STATUS_LINK_BUFOFLOW 0x00000085 // Buffer overflow
190#define SXG_RCV_STATUS_LINK_CODE 0x00000084 // Link code error 190#define SXG_RCV_STATUS_LINK_CODE 0x00000084 // Link code error
191#define SXG_RCV_STATUS_LINK_DRIBBLE 0x00000083 // Dribble nibble 191#define SXG_RCV_STATUS_LINK_DRIBBLE 0x00000083 // Dribble nibble
192#define SXG_RCV_STATUS_LINK_CRC 0x00000082 // CRC error 192#define SXG_RCV_STATUS_LINK_CRC 0x00000082 // CRC error
193#define SXG_RCV_STATUS_LINK_OFLOW 0x00000081 // Link overflow 193#define SXG_RCV_STATUS_LINK_OFLOW 0x00000081 // Link overflow
194#define SXG_RCV_STATUS_LINK_UFLOW 0x00000080 // Link underflow 194#define SXG_RCV_STATUS_LINK_UFLOW 0x00000080 // Link underflow
195#define SXG_RCV_STATUS_LINK_8023 0x00000020 // 802.3 195#define SXG_RCV_STATUS_LINK_8023 0x00000020 // 802.3
196#define SXG_RCV_STATUS_LINK_SNAP 0x00000010 // Snap 196#define SXG_RCV_STATUS_LINK_SNAP 0x00000010 // Snap
197#define SXG_RCV_STATUS_LINK_VLAN 0x00000008 // VLAN 197#define SXG_RCV_STATUS_LINK_VLAN 0x00000008 // VLAN
198#define SXG_RCV_STATUS_LINK_TYPE_MASK 0x00000007 // Network type mask 198#define SXG_RCV_STATUS_LINK_TYPE_MASK 0x00000007 // Network type mask
199#define SXG_RCV_STATUS_LINK_CONTROL 0x00000003 // Control packet 199#define SXG_RCV_STATUS_LINK_CONTROL 0x00000003 // Control packet
200#define SXG_RCV_STATUS_LINK_IPV6 0x00000002 // IPv6 packet 200#define SXG_RCV_STATUS_LINK_IPV6 0x00000002 // IPv6 packet
201#define SXG_RCV_STATUS_LINK_IPV4 0x00000001 // IPv4 packet 201#define SXG_RCV_STATUS_LINK_IPV4 0x00000001 // IPv4 packet
202 202
203/*************************************************************************** 203/***************************************************************************
204 * Sahara receive and transmit configuration registers 204 * Sahara receive and transmit configuration registers
205 ***************************************************************************/ 205 ***************************************************************************/
206#define RCV_CONFIG_RESET 0x80000000 // RcvConfig register reset 206#define RCV_CONFIG_RESET 0x80000000 // RcvConfig register reset
207#define RCV_CONFIG_ENABLE 0x40000000 // Enable the receive logic 207#define RCV_CONFIG_ENABLE 0x40000000 // Enable the receive logic
208#define RCV_CONFIG_ENPARSE 0x20000000 // Enable the receive parser 208#define RCV_CONFIG_ENPARSE 0x20000000 // Enable the receive parser
209#define RCV_CONFIG_SOCKET 0x10000000 // Enable the socket detector 209#define RCV_CONFIG_SOCKET 0x10000000 // Enable the socket detector
210#define RCV_CONFIG_RCVBAD 0x08000000 // Receive all bad frames 210#define RCV_CONFIG_RCVBAD 0x08000000 // Receive all bad frames
211#define RCV_CONFIG_CONTROL 0x04000000 // Receive all control frames 211#define RCV_CONFIG_CONTROL 0x04000000 // Receive all control frames
212#define RCV_CONFIG_RCVPAUSE 0x02000000 // Enable pause transmit when attn 212#define RCV_CONFIG_RCVPAUSE 0x02000000 // Enable pause transmit when attn
213#define RCV_CONFIG_TZIPV6 0x01000000 // Include TCP port w/ IPv6 toeplitz 213#define RCV_CONFIG_TZIPV6 0x01000000 // Include TCP port w/ IPv6 toeplitz
214#define RCV_CONFIG_TZIPV4 0x00800000 // Include TCP port w/ IPv4 toeplitz 214#define RCV_CONFIG_TZIPV4 0x00800000 // Include TCP port w/ IPv4 toeplitz
215#define RCV_CONFIG_FLUSH 0x00400000 // Flush buffers 215#define RCV_CONFIG_FLUSH 0x00400000 // Flush buffers
216#define RCV_CONFIG_PRIORITY_MASK 0x00300000 // Priority level 216#define RCV_CONFIG_PRIORITY_MASK 0x00300000 // Priority level
217#define RCV_CONFIG_HASH_MASK 0x00030000 // Hash depth 217#define RCV_CONFIG_HASH_MASK 0x00030000 // Hash depth
218#define RCV_CONFIG_HASH_8 0x00000000 // Hash depth 8 218#define RCV_CONFIG_HASH_8 0x00000000 // Hash depth 8
219#define RCV_CONFIG_HASH_16 0x00010000 // Hash depth 16 219#define RCV_CONFIG_HASH_16 0x00010000 // Hash depth 16
220#define RCV_CONFIG_HASH_4 0x00020000 // Hash depth 4 220#define RCV_CONFIG_HASH_4 0x00020000 // Hash depth 4
221#define RCV_CONFIG_HASH_2 0x00030000 // Hash depth 2 221#define RCV_CONFIG_HASH_2 0x00030000 // Hash depth 2
222#define RCV_CONFIG_BUFLEN_MASK 0x0000FFF0 // Buffer length bits 15:4. ie multiple of 16. 222#define RCV_CONFIG_BUFLEN_MASK 0x0000FFF0 // Buffer length bits 15:4. ie multiple of 16.
223#define RCV_CONFIG_SKT_DIS 0x00000008 // Disable socket detection on attn 223#define RCV_CONFIG_SKT_DIS 0x00000008 // Disable socket detection on attn
224// Macro to determine RCV_CONFIG_BUFLEN based on maximum frame size. 224// Macro to determine RCV_CONFIG_BUFLEN based on maximum frame size.
225// We add 18 bytes for Sahara receive status and padding, plus 4 bytes for CRC, 225// We add 18 bytes for Sahara receive status and padding, plus 4 bytes for CRC,
226// and round up to nearest 16 byte boundary 226// and round up to nearest 16 byte boundary
227#define RCV_CONFIG_BUFSIZE(_MaxFrame) ((((_MaxFrame) + 22) + 15) & RCV_CONFIG_BUFLEN_MASK) 227#define RCV_CONFIG_BUFSIZE(_MaxFrame) ((((_MaxFrame) + 22) + 15) & RCV_CONFIG_BUFLEN_MASK)
228 228
229#define XMT_CONFIG_RESET 0x80000000 // XmtConfig register reset 229#define XMT_CONFIG_RESET 0x80000000 // XmtConfig register reset
230#define XMT_CONFIG_ENABLE 0x40000000 // Enable transmit logic 230#define XMT_CONFIG_ENABLE 0x40000000 // Enable transmit logic
231#define XMT_CONFIG_MAC_PARITY 0x20000000 // Inhibit MAC RAM parity error 231#define XMT_CONFIG_MAC_PARITY 0x20000000 // Inhibit MAC RAM parity error
232#define XMT_CONFIG_BUF_PARITY 0x10000000 // Inhibit D2F buffer parity error 232#define XMT_CONFIG_BUF_PARITY 0x10000000 // Inhibit D2F buffer parity error
233#define XMT_CONFIG_MEM_PARITY 0x08000000 // Inhibit 1T SRAM parity error 233#define XMT_CONFIG_MEM_PARITY 0x08000000 // Inhibit 1T SRAM parity error
@@ -249,9 +249,9 @@ typedef struct _SXG_HW_REGS {
249 249
250// A-XGMAC Configuration Register 1 250// A-XGMAC Configuration Register 1
251#define AXGMAC_CFG1_XMT_PAUSE 0x80000000 // Allow the sending of Pause frames 251#define AXGMAC_CFG1_XMT_PAUSE 0x80000000 // Allow the sending of Pause frames
252#define AXGMAC_CFG1_XMT_EN 0x40000000 // Enable transmit 252#define AXGMAC_CFG1_XMT_EN 0x40000000 // Enable transmit
253#define AXGMAC_CFG1_RCV_PAUSE 0x20000000 // Allow the detection of Pause frames 253#define AXGMAC_CFG1_RCV_PAUSE 0x20000000 // Allow the detection of Pause frames
254#define AXGMAC_CFG1_RCV_EN 0x10000000 // Enable receive 254#define AXGMAC_CFG1_RCV_EN 0x10000000 // Enable receive
255#define AXGMAC_CFG1_XMT_STATE 0x04000000 // Current transmit state - READ ONLY 255#define AXGMAC_CFG1_XMT_STATE 0x04000000 // Current transmit state - READ ONLY
256#define AXGMAC_CFG1_RCV_STATE 0x01000000 // Current receive state - READ ONLY 256#define AXGMAC_CFG1_RCV_STATE 0x01000000 // Current receive state - READ ONLY
257#define AXGMAC_CFG1_XOFF_SHORT 0x00001000 // Only pause for 64 slot on XOFF 257#define AXGMAC_CFG1_XOFF_SHORT 0x00001000 // Only pause for 64 slot on XOFF
@@ -262,24 +262,24 @@ typedef struct _SXG_HW_REGS {
262#define AXGMAC_CFG1_RCV_FCS2 0x00000200 // Delay receive FCS 2 4-byte words 262#define AXGMAC_CFG1_RCV_FCS2 0x00000200 // Delay receive FCS 2 4-byte words
263#define AXGMAC_CFG1_RCV_FCS3 0x00000300 // Delay receive FCS 3 4-byte words 263#define AXGMAC_CFG1_RCV_FCS3 0x00000300 // Delay receive FCS 3 4-byte words
264#define AXGMAC_CFG1_PKT_OVERRIDE 0x00000080 // Per-packet override enable 264#define AXGMAC_CFG1_PKT_OVERRIDE 0x00000080 // Per-packet override enable
265#define AXGMAC_CFG1_SWAP 0x00000040 // Byte swap enable 265#define AXGMAC_CFG1_SWAP 0x00000040 // Byte swap enable
266#define AXGMAC_CFG1_SHORT_ASSERT 0x00000020 // ASSERT srdrpfrm on short frame (<64) 266#define AXGMAC_CFG1_SHORT_ASSERT 0x00000020 // ASSERT srdrpfrm on short frame (<64)
267#define AXGMAC_CFG1_RCV_STRICT 0x00000010 // RCV only 802.3AE when CLEAR 267#define AXGMAC_CFG1_RCV_STRICT 0x00000010 // RCV only 802.3AE when CLEAR
268#define AXGMAC_CFG1_CHECK_LEN 0x00000008 // Verify frame length 268#define AXGMAC_CFG1_CHECK_LEN 0x00000008 // Verify frame length
269#define AXGMAC_CFG1_GEN_FCS 0x00000004 // Generate FCS 269#define AXGMAC_CFG1_GEN_FCS 0x00000004 // Generate FCS
270#define AXGMAC_CFG1_PAD_MASK 0x00000003 // Mask for pad bits 270#define AXGMAC_CFG1_PAD_MASK 0x00000003 // Mask for pad bits
271#define AXGMAC_CFG1_PAD_64 0x00000001 // Pad frames to 64 bytes 271#define AXGMAC_CFG1_PAD_64 0x00000001 // Pad frames to 64 bytes
272#define AXGMAC_CFG1_PAD_VLAN 0x00000002 // Detect VLAN and pad to 68 bytes 272#define AXGMAC_CFG1_PAD_VLAN 0x00000002 // Detect VLAN and pad to 68 bytes
273#define AXGMAC_CFG1_PAD_68 0x00000003 // Pad to 68 bytes 273#define AXGMAC_CFG1_PAD_68 0x00000003 // Pad to 68 bytes
274 274
275// A-XGMAC Configuration Register 2 275// A-XGMAC Configuration Register 2
276#define AXGMAC_CFG2_GEN_PAUSE 0x80000000 // Generate single pause frame (test) 276#define AXGMAC_CFG2_GEN_PAUSE 0x80000000 // Generate single pause frame (test)
277#define AXGMAC_CFG2_LF_MANUAL 0x08000000 // Manual link fault sequence 277#define AXGMAC_CFG2_LF_MANUAL 0x08000000 // Manual link fault sequence
278#define AXGMAC_CFG2_LF_AUTO 0x04000000 // Auto link fault sequence 278#define AXGMAC_CFG2_LF_AUTO 0x04000000 // Auto link fault sequence
279#define AXGMAC_CFG2_LF_REMOTE 0x02000000 // Remote link fault (READ ONLY) 279#define AXGMAC_CFG2_LF_REMOTE 0x02000000 // Remote link fault (READ ONLY)
280#define AXGMAC_CFG2_LF_LOCAL 0x01000000 // Local link fault (READ ONLY) 280#define AXGMAC_CFG2_LF_LOCAL 0x01000000 // Local link fault (READ ONLY)
281#define AXGMAC_CFG2_IPG_MASK 0x001F0000 // Inter packet gap 281#define AXGMAC_CFG2_IPG_MASK 0x001F0000 // Inter packet gap
282#define AXGMAC_CFG2_IPG_SHIFT 16 282#define AXGMAC_CFG2_IPG_SHIFT 16
283#define AXGMAC_CFG2_PAUSE_XMT 0x00008000 // Pause transmit module 283#define AXGMAC_CFG2_PAUSE_XMT 0x00008000 // Pause transmit module
284#define AXGMAC_CFG2_IPG_EXTEN 0x00000020 // Enable IPG extension algorithm 284#define AXGMAC_CFG2_IPG_EXTEN 0x00000020 // Enable IPG extension algorithm
285#define AXGMAC_CFG2_IPGEX_MASK 0x0000001F // IPG extension 285#define AXGMAC_CFG2_IPGEX_MASK 0x0000001F // IPG extension
@@ -299,9 +299,9 @@ typedef struct _SXG_HW_REGS {
299#define AXGMAC_SARHIGH_OCTET_SIX 0x00FF0000 // Sixth octet 299#define AXGMAC_SARHIGH_OCTET_SIX 0x00FF0000 // Sixth octet
300 300
301// A-XGMAC Maximum frame length register 301// A-XGMAC Maximum frame length register
302#define AXGMAC_MAXFRAME_XMT 0x3FFF0000 // Maximum transmit frame length 302#define AXGMAC_MAXFRAME_XMT 0x3FFF0000 // Maximum transmit frame length
303#define AXGMAC_MAXFRAME_XMT_SHIFT 16 303#define AXGMAC_MAXFRAME_XMT_SHIFT 16
304#define AXGMAC_MAXFRAME_RCV 0x0000FFFF // Maximum receive frame length 304#define AXGMAC_MAXFRAME_RCV 0x0000FFFF // Maximum receive frame length
305// This register doesn't need to be written for standard MTU. 305// This register doesn't need to be written for standard MTU.
306// For jumbo, I'll just statically define the value here. This 306// For jumbo, I'll just statically define the value here. This
307// value sets the receive byte count to 9036 (0x234C) and the 307// value sets the receive byte count to 9036 (0x234C) and the
@@ -324,34 +324,34 @@ typedef struct _SXG_HW_REGS {
324 324
325// A-XGMAC AMIIM Field Register 325// A-XGMAC AMIIM Field Register
326#define AXGMAC_AMIIM_FIELD_ST 0xC0000000 // 2-bit ST field 326#define AXGMAC_AMIIM_FIELD_ST 0xC0000000 // 2-bit ST field
327#define AXGMAC_AMIIM_FIELD_ST_SHIFT 30 327#define AXGMAC_AMIIM_FIELD_ST_SHIFT 30
328#define AXGMAC_AMIIM_FIELD_OP 0x30000000 // 2-bit OP field 328#define AXGMAC_AMIIM_FIELD_OP 0x30000000 // 2-bit OP field
329#define AXGMAC_AMIIM_FIELD_OP_SHIFT 28 329#define AXGMAC_AMIIM_FIELD_OP_SHIFT 28
330#define AXGMAC_AMIIM_FIELD_PORT_ADDR 0x0F800000 // Port address field (hstphyadx in spec) 330#define AXGMAC_AMIIM_FIELD_PORT_ADDR 0x0F800000 // Port address field (hstphyadx in spec)
331#define AXGMAC_AMIIM_FIELD_PORT_SHIFT 23 331#define AXGMAC_AMIIM_FIELD_PORT_SHIFT 23
332#define AXGMAC_AMIIM_FIELD_DEV_ADDR 0x007C0000 // Device address field (hstregadx in spec) 332#define AXGMAC_AMIIM_FIELD_DEV_ADDR 0x007C0000 // Device address field (hstregadx in spec)
333#define AXGMAC_AMIIM_FIELD_DEV_SHIFT 18 333#define AXGMAC_AMIIM_FIELD_DEV_SHIFT 18
334#define AXGMAC_AMIIM_FIELD_TA 0x00030000 // 2-bit TA field 334#define AXGMAC_AMIIM_FIELD_TA 0x00030000 // 2-bit TA field
335#define AXGMAC_AMIIM_FIELD_TA_SHIFT 16 335#define AXGMAC_AMIIM_FIELD_TA_SHIFT 16
336#define AXGMAC_AMIIM_FIELD_DATA 0x0000FFFF // Data field 336#define AXGMAC_AMIIM_FIELD_DATA 0x0000FFFF // Data field
337 337
338// Values for the AXGMAC_AMIIM_FIELD_OP field in the A-XGMAC AMIIM Field Register 338// Values for the AXGMAC_AMIIM_FIELD_OP field in the A-XGMAC AMIIM Field Register
339#define MIIM_OP_ADDR 0 // MIIM Address set operation 339#define MIIM_OP_ADDR 0 // MIIM Address set operation
340#define MIIM_OP_WRITE 1 // MIIM Write register operation 340#define MIIM_OP_WRITE 1 // MIIM Write register operation
341#define MIIM_OP_READ 2 // MIIM Read register operation 341#define MIIM_OP_READ 2 // MIIM Read register operation
342#define MIIM_OP_ADDR_SHIFT (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT) 342#define MIIM_OP_ADDR_SHIFT (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT)
343 343
344// Values for the AXGMAC_AMIIM_FIELD_PORT_ADDR field in the A-XGMAC AMIIM Field Register 344// Values for the AXGMAC_AMIIM_FIELD_PORT_ADDR field in the A-XGMAC AMIIM Field Register
345#define MIIM_PORT_NUM 1 // All Sahara MIIM modules use port 1 345#define MIIM_PORT_NUM 1 // All Sahara MIIM modules use port 1
346 346
347// Values for the AXGMAC_AMIIM_FIELD_DEV_ADDR field in the A-XGMAC AMIIM Field Register 347// Values for the AXGMAC_AMIIM_FIELD_DEV_ADDR field in the A-XGMAC AMIIM Field Register
348#define MIIM_DEV_PHY_PMA 1 // PHY PMA/PMD module MIIM device number 348#define MIIM_DEV_PHY_PMA 1 // PHY PMA/PMD module MIIM device number
349#define MIIM_DEV_PHY_PCS 3 // PHY PCS module MIIM device number 349#define MIIM_DEV_PHY_PCS 3 // PHY PCS module MIIM device number
350#define MIIM_DEV_PHY_XS 4 // PHY XS module MIIM device number 350#define MIIM_DEV_PHY_XS 4 // PHY XS module MIIM device number
351#define MIIM_DEV_XGXS 5 // XGXS MIIM device number 351#define MIIM_DEV_XGXS 5 // XGXS MIIM device number
352 352
353// Values for the AXGMAC_AMIIM_FIELD_TA field in the A-XGMAC AMIIM Field Register 353// Values for the AXGMAC_AMIIM_FIELD_TA field in the A-XGMAC AMIIM Field Register
354#define MIIM_TA_10GB 2 // set to 2 for 10 GB operation 354#define MIIM_TA_10GB 2 // set to 2 for 10 GB operation
355 355
356// A-XGMAC AMIIM Configuration Register 356// A-XGMAC AMIIM Configuration Register
357#define AXGMAC_AMIIM_CFG_NOPREAM 0x00000080 // Bypass preamble of mngmt frame 357#define AXGMAC_AMIIM_CFG_NOPREAM 0x00000080 // Bypass preamble of mngmt frame
@@ -365,25 +365,25 @@ typedef struct _SXG_HW_REGS {
365#define AXGMAC_AMIIM_INDC_BUSY 0x00000001 // Set until cmd operation complete 365#define AXGMAC_AMIIM_INDC_BUSY 0x00000001 // Set until cmd operation complete
366 366
367// Link Status and Control Register 367// Link Status and Control Register
368#define LS_PHY_CLR_RESET 0x80000000 // Clear reset signal to PHY 368#define LS_PHY_CLR_RESET 0x80000000 // Clear reset signal to PHY
369#define LS_SERDES_POWER_DOWN 0x40000000 // Power down the Sahara Serdes 369#define LS_SERDES_POWER_DOWN 0x40000000 // Power down the Sahara Serdes
370#define LS_XGXS_ENABLE 0x20000000 // Enable the XAUI XGXS logic 370#define LS_XGXS_ENABLE 0x20000000 // Enable the XAUI XGXS logic
371#define LS_XGXS_CTL 0x10000000 // Hold XAUI XGXS logic reset until Serdes is up 371#define LS_XGXS_CTL 0x10000000 // Hold XAUI XGXS logic reset until Serdes is up
372#define LS_SERDES_DOWN 0x08000000 // When 0, XAUI Serdes is up and initialization is complete 372#define LS_SERDES_DOWN 0x08000000 // When 0, XAUI Serdes is up and initialization is complete
373#define LS_TRACE_DOWN 0x04000000 // When 0, Trace Serdes is up and initialization is complete 373#define LS_TRACE_DOWN 0x04000000 // When 0, Trace Serdes is up and initialization is complete
374#define LS_PHY_CLK_25MHZ 0x02000000 // Set PHY clock to 25 MHz (else 156.125 MHz) 374#define LS_PHY_CLK_25MHZ 0x02000000 // Set PHY clock to 25 MHz (else 156.125 MHz)
375#define LS_PHY_CLK_EN 0x01000000 // Enable clock to PHY 375#define LS_PHY_CLK_EN 0x01000000 // Enable clock to PHY
376#define LS_XAUI_LINK_UP 0x00000010 // XAUI link is up 376#define LS_XAUI_LINK_UP 0x00000010 // XAUI link is up
377#define LS_XAUI_LINK_CHNG 0x00000008 // XAUI link status has changed 377#define LS_XAUI_LINK_CHNG 0x00000008 // XAUI link status has changed
378#define LS_LINK_ALARM 0x00000004 // Link alarm pin 378#define LS_LINK_ALARM 0x00000004 // Link alarm pin
379#define LS_ATTN_CTRL_MASK 0x00000003 // Mask link attention control bits 379#define LS_ATTN_CTRL_MASK 0x00000003 // Mask link attention control bits
380#define LS_ATTN_ALARM 0x00000000 // 00 => Attn on link alarm 380#define LS_ATTN_ALARM 0x00000000 // 00 => Attn on link alarm
381#define LS_ATTN_ALARM_OR_STAT_CHNG 0x00000001 // 01 => Attn on link alarm or status change 381#define LS_ATTN_ALARM_OR_STAT_CHNG 0x00000001 // 01 => Attn on link alarm or status change
382#define LS_ATTN_STAT_CHNG 0x00000002 // 10 => Attn on link status change 382#define LS_ATTN_STAT_CHNG 0x00000002 // 10 => Attn on link status change
383#define LS_ATTN_NONE 0x00000003 // 11 => no Attn 383#define LS_ATTN_NONE 0x00000003 // 11 => no Attn
384 384
385// Link Address High Registers 385// Link Address High Registers
386#define LINK_ADDR_ENABLE 0x80000000 // Enable this link address 386#define LINK_ADDR_ENABLE 0x80000000 // Enable this link address
387 387
388 388
389/*************************************************************************** 389/***************************************************************************
@@ -396,7 +396,7 @@ typedef struct _SXG_HW_REGS {
396#define XGXS_ADDRESS_STATUS1 0x0001 // XS Status 1 396#define XGXS_ADDRESS_STATUS1 0x0001 // XS Status 1
397#define XGXS_ADDRESS_DEVID_LOW 0x0002 // XS Device ID (low) 397#define XGXS_ADDRESS_DEVID_LOW 0x0002 // XS Device ID (low)
398#define XGXS_ADDRESS_DEVID_HIGH 0x0003 // XS Device ID (high) 398#define XGXS_ADDRESS_DEVID_HIGH 0x0003 // XS Device ID (high)
399#define XGXS_ADDRESS_SPEED 0x0004 // XS Speed ability 399#define XGXS_ADDRESS_SPEED 0x0004 // XS Speed ability
400#define XGXS_ADDRESS_DEV_LOW 0x0005 // XS Devices in package 400#define XGXS_ADDRESS_DEV_LOW 0x0005 // XS Devices in package
401#define XGXS_ADDRESS_DEV_HIGH 0x0006 // XS Devices in package 401#define XGXS_ADDRESS_DEV_HIGH 0x0006 // XS Devices in package
402#define XGXS_ADDRESS_STATUS2 0x0008 // XS Status 2 402#define XGXS_ADDRESS_STATUS2 0x0008 // XS Status 2
@@ -410,27 +410,27 @@ typedef struct _SXG_HW_REGS {
410#define XGXS_ADDRESS_RESET_HI2 0x8003 // Vendor-Specific Reset Hi 2 410#define XGXS_ADDRESS_RESET_HI2 0x8003 // Vendor-Specific Reset Hi 2
411 411
412// XS Control 1 register bit definitions 412// XS Control 1 register bit definitions
413#define XGXS_CONTROL1_RESET 0x8000 // Reset - self clearing 413#define XGXS_CONTROL1_RESET 0x8000 // Reset - self clearing
414#define XGXS_CONTROL1_LOOPBACK 0x4000 // Enable loopback 414#define XGXS_CONTROL1_LOOPBACK 0x4000 // Enable loopback
415#define XGXS_CONTROL1_SPEED1 0x2000 // 0 = unspecified, 1 = 10Gb+ 415#define XGXS_CONTROL1_SPEED1 0x2000 // 0 = unspecified, 1 = 10Gb+
416#define XGXS_CONTROL1_LOWPOWER 0x0400 // 1 = Low power mode 416#define XGXS_CONTROL1_LOWPOWER 0x0400 // 1 = Low power mode
417#define XGXS_CONTROL1_SPEED2 0x0040 // Same as SPEED1 (?) 417#define XGXS_CONTROL1_SPEED2 0x0040 // Same as SPEED1 (?)
418#define XGXS_CONTROL1_SPEED 0x003C // Everything reserved except zero (?) 418#define XGXS_CONTROL1_SPEED 0x003C // Everything reserved except zero (?)
419 419
420// XS Status 1 register bit definitions 420// XS Status 1 register bit definitions
421#define XGXS_STATUS1_FAULT 0x0080 // Fault detected 421#define XGXS_STATUS1_FAULT 0x0080 // Fault detected
422#define XGXS_STATUS1_LINK 0x0004 // 1 = Link up 422#define XGXS_STATUS1_LINK 0x0004 // 1 = Link up
423#define XGXS_STATUS1_LOWPOWER 0x0002 // 1 = Low power supported 423#define XGXS_STATUS1_LOWPOWER 0x0002 // 1 = Low power supported
424 424
425// XS Speed register bit definitions 425// XS Speed register bit definitions
426#define XGXS_SPEED_10G 0x0001 // 1 = 10G capable 426#define XGXS_SPEED_10G 0x0001 // 1 = 10G capable
427 427
428// XS Devices register bit definitions 428// XS Devices register bit definitions
429#define XGXS_DEVICES_DTE 0x0020 // DTE XS Present 429#define XGXS_DEVICES_DTE 0x0020 // DTE XS Present
430#define XGXS_DEVICES_PHY 0x0010 // PHY XS Present 430#define XGXS_DEVICES_PHY 0x0010 // PHY XS Present
431#define XGXS_DEVICES_PCS 0x0008 // PCS Present 431#define XGXS_DEVICES_PCS 0x0008 // PCS Present
432#define XGXS_DEVICES_WIS 0x0004 // WIS Present 432#define XGXS_DEVICES_WIS 0x0004 // WIS Present
433#define XGXS_DEVICES_PMD 0x0002 // PMD/PMA Present 433#define XGXS_DEVICES_PMD 0x0002 // PMD/PMA Present
434#define XGXS_DEVICES_CLAUSE22 0x0001 // Clause 22 registers present 434#define XGXS_DEVICES_CLAUSE22 0x0001 // Clause 22 registers present
435 435
436// XS Devices High register bit definitions 436// XS Devices High register bit definitions
@@ -444,18 +444,18 @@ typedef struct _SXG_HW_REGS {
444#define XGXS_STATUS2_RCV_FAULT 0x0400 // Receive fault 444#define XGXS_STATUS2_RCV_FAULT 0x0400 // Receive fault
445 445
446// XS Package ID High register bit definitions 446// XS Package ID High register bit definitions
447#define XGXS_PKGID_HIGH_ORG 0xFC00 // Organizationally Unique 447#define XGXS_PKGID_HIGH_ORG 0xFC00 // Organizationally Unique
448#define XGXS_PKGID_HIGH_MFG 0x03F0 // Manufacturer Model 448#define XGXS_PKGID_HIGH_MFG 0x03F0 // Manufacturer Model
449#define XGXS_PKGID_HIGH_REV 0x000F // Revision Number 449#define XGXS_PKGID_HIGH_REV 0x000F // Revision Number
450 450
451// XS Lane Status register bit definitions 451// XS Lane Status register bit definitions
452#define XGXS_LANE_PHY 0x1000 // PHY/DTE lane alignment status 452#define XGXS_LANE_PHY 0x1000 // PHY/DTE lane alignment status
453#define XGXS_LANE_PATTERN 0x0800 // Pattern testing ability 453#define XGXS_LANE_PATTERN 0x0800 // Pattern testing ability
454#define XGXS_LANE_LOOPBACK 0x0400 // PHY loopback ability 454#define XGXS_LANE_LOOPBACK 0x0400 // PHY loopback ability
455#define XGXS_LANE_SYNC3 0x0008 // Lane 3 sync 455#define XGXS_LANE_SYNC3 0x0008 // Lane 3 sync
456#define XGXS_LANE_SYNC2 0x0004 // Lane 2 sync 456#define XGXS_LANE_SYNC2 0x0004 // Lane 2 sync
457#define XGXS_LANE_SYNC1 0x0002 // Lane 1 sync 457#define XGXS_LANE_SYNC1 0x0002 // Lane 1 sync
458#define XGXS_LANE_SYNC0 0x0001 // Lane 0 sync 458#define XGXS_LANE_SYNC0 0x0001 // Lane 0 sync
459 459
460// XS Test Control register bit definitions 460// XS Test Control register bit definitions
461#define XGXS_TEST_PATTERN_ENABLE 0x0004 // Test pattern enabled 461#define XGXS_TEST_PATTERN_ENABLE 0x0004 // Test pattern enabled
@@ -473,10 +473,10 @@ typedef struct _SXG_HW_REGS {
473// LASI (Link Alarm Status Interrupt) Registers (located in MIIM_DEV_PHY_PMA device) 473// LASI (Link Alarm Status Interrupt) Registers (located in MIIM_DEV_PHY_PMA device)
474#define LASI_RX_ALARM_CONTROL 0x9000 // LASI RX_ALARM Control 474#define LASI_RX_ALARM_CONTROL 0x9000 // LASI RX_ALARM Control
475#define LASI_TX_ALARM_CONTROL 0x9001 // LASI TX_ALARM Control 475#define LASI_TX_ALARM_CONTROL 0x9001 // LASI TX_ALARM Control
476#define LASI_CONTROL 0x9002 // LASI Control 476#define LASI_CONTROL 0x9002 // LASI Control
477#define LASI_RX_ALARM_STATUS 0x9003 // LASI RX_ALARM Status 477#define LASI_RX_ALARM_STATUS 0x9003 // LASI RX_ALARM Status
478#define LASI_TX_ALARM_STATUS 0x9004 // LASI TX_ALARM Status 478#define LASI_TX_ALARM_STATUS 0x9004 // LASI TX_ALARM Status
479#define LASI_STATUS 0x9005 // LASI Status 479#define LASI_STATUS 0x9005 // LASI Status
480 480
481// LASI_CONTROL bit definitions 481// LASI_CONTROL bit definitions
482#define LASI_CTL_RX_ALARM_ENABLE 0x0004 // Enable RX_ALARM interrupts 482#define LASI_CTL_RX_ALARM_ENABLE 0x0004 // Enable RX_ALARM interrupts
@@ -489,34 +489,34 @@ typedef struct _SXG_HW_REGS {
489#define LASI_STATUS_LS_ALARM 0x0001 // Link Status 489#define LASI_STATUS_LS_ALARM 0x0001 // Link Status
490 490
491// PHY registers - PMA/PMD (device 1) 491// PHY registers - PMA/PMD (device 1)
492#define PHY_PMA_CONTROL1 0x0000 // PMA/PMD Control 1 492#define PHY_PMA_CONTROL1 0x0000 // PMA/PMD Control 1
493#define PHY_PMA_STATUS1 0x0001 // PMA/PMD Status 1 493#define PHY_PMA_STATUS1 0x0001 // PMA/PMD Status 1
494#define PHY_PMA_RCV_DET 0x000A // PMA/PMD Receive Signal Detect 494#define PHY_PMA_RCV_DET 0x000A // PMA/PMD Receive Signal Detect
495 // other PMA/PMD registers exist and can be defined as needed 495 // other PMA/PMD registers exist and can be defined as needed
496 496
497// PHY registers - PCS (device 3) 497// PHY registers - PCS (device 3)
498#define PHY_PCS_CONTROL1 0x0000 // PCS Control 1 498#define PHY_PCS_CONTROL1 0x0000 // PCS Control 1
499#define PHY_PCS_STATUS1 0x0001 // PCS Status 1 499#define PHY_PCS_STATUS1 0x0001 // PCS Status 1
500#define PHY_PCS_10G_STATUS1 0x0020 // PCS 10GBASE-R Status 1 500#define PHY_PCS_10G_STATUS1 0x0020 // PCS 10GBASE-R Status 1
501 // other PCS registers exist and can be defined as needed 501 // other PCS registers exist and can be defined as needed
502 502
503// PHY registers - XS (device 4) 503// PHY registers - XS (device 4)
504#define PHY_XS_CONTROL1 0x0000 // XS Control 1 504#define PHY_XS_CONTROL1 0x0000 // XS Control 1
505#define PHY_XS_STATUS1 0x0001 // XS Status 1 505#define PHY_XS_STATUS1 0x0001 // XS Status 1
506#define PHY_XS_LANE_STATUS 0x0018 // XS Lane Status 506#define PHY_XS_LANE_STATUS 0x0018 // XS Lane Status
507 // other XS registers exist and can be defined as needed 507 // other XS registers exist and can be defined as needed
508 508
509// PHY_PMA_CONTROL1 register bit definitions 509// PHY_PMA_CONTROL1 register bit definitions
510#define PMA_CONTROL1_RESET 0x8000 // PMA/PMD reset 510#define PMA_CONTROL1_RESET 0x8000 // PMA/PMD reset
511 511
512// PHY_PMA_RCV_DET register bit definitions 512// PHY_PMA_RCV_DET register bit definitions
513#define PMA_RCV_DETECT 0x0001 // PMA/PMD receive signal detect 513#define PMA_RCV_DETECT 0x0001 // PMA/PMD receive signal detect
514 514
515// PHY_PCS_10G_STATUS1 register bit definitions 515// PHY_PCS_10G_STATUS1 register bit definitions
516#define PCS_10B_BLOCK_LOCK 0x0001 // PCS 10GBASE-R locked to receive blocks 516#define PCS_10B_BLOCK_LOCK 0x0001 // PCS 10GBASE-R locked to receive blocks
517 517
518// PHY_XS_LANE_STATUS register bit definitions 518// PHY_XS_LANE_STATUS register bit definitions
519#define XS_LANE_ALIGN 0x1000 // XS transmit lanes aligned 519#define XS_LANE_ALIGN 0x1000 // XS transmit lanes aligned
520 520
521// PHY Microcode download data structure 521// PHY Microcode download data structure
522typedef struct _PHY_UCODE { 522typedef struct _PHY_UCODE {
@@ -558,8 +558,8 @@ typedef struct _XMT_DESC {
558 // command codes 558 // command codes
559#define XMT_DESC_CMD_RAW_SEND 0 // raw send descriptor 559#define XMT_DESC_CMD_RAW_SEND 0 // raw send descriptor
560#define XMT_DESC_CMD_CSUM_INSERT 1 // checksum insert descriptor 560#define XMT_DESC_CMD_CSUM_INSERT 1 // checksum insert descriptor
561#define XMT_DESC_CMD_FORMAT 2 // format descriptor 561#define XMT_DESC_CMD_FORMAT 2 // format descriptor
562#define XMT_DESC_CMD_PRIME 3 // prime descriptor 562#define XMT_DESC_CMD_PRIME 3 // prime descriptor
563#define XMT_DESC_CMD_CODE_SHFT 6 // comand code shift (shift to bits [31:30] in word 0) 563#define XMT_DESC_CMD_CODE_SHFT 6 // comand code shift (shift to bits [31:30] in word 0)
564 // shifted command codes 564 // shifted command codes
565#define XMT_RAW_SEND (XMT_DESC_CMD_RAW_SEND << XMT_DESC_CMD_CODE_SHFT) 565#define XMT_RAW_SEND (XMT_DESC_CMD_RAW_SEND << XMT_DESC_CMD_CODE_SHFT)
@@ -569,22 +569,22 @@ typedef struct _XMT_DESC {
569 569
570// XMT_DESC Control Byte (XmtCtl) definitions 570// XMT_DESC Control Byte (XmtCtl) definitions
571// NOTE: These bits do not work on Sahara (Rev A)! 571// NOTE: These bits do not work on Sahara (Rev A)!
572#define XMT_CTL_PAUSE_FRAME 0x80 // current frame is a pause control frame (for statistics) 572#define XMT_CTL_PAUSE_FRAME 0x80 // current frame is a pause control frame (for statistics)
573#define XMT_CTL_CONTROL_FRAME 0x40 // current frame is a control frame (for statistics) 573#define XMT_CTL_CONTROL_FRAME 0x40 // current frame is a control frame (for statistics)
574#define XMT_CTL_PER_PKT_QUAL 0x20 // per packet qualifier 574#define XMT_CTL_PER_PKT_QUAL 0x20 // per packet qualifier
575#define XMT_CTL_PAD_MODE_NONE 0x00 // do not pad frame 575#define XMT_CTL_PAD_MODE_NONE 0x00 // do not pad frame
576#define XMT_CTL_PAD_MODE_64 0x08 // pad frame to 64 bytes 576#define XMT_CTL_PAD_MODE_64 0x08 // pad frame to 64 bytes
577#define XMT_CTL_PAD_MODE_VLAN_68 0x10 // pad frame to 64 bytes, and VLAN frames to 68 bytes 577#define XMT_CTL_PAD_MODE_VLAN_68 0x10 // pad frame to 64 bytes, and VLAN frames to 68 bytes
578#define XMT_CTL_PAD_MODE_68 0x18 // pad frame to 68 bytes 578#define XMT_CTL_PAD_MODE_68 0x18 // pad frame to 68 bytes
579#define XMT_CTL_GEN_FCS 0x04 // generate FCS (CRC) for this frame 579#define XMT_CTL_GEN_FCS 0x04 // generate FCS (CRC) for this frame
580#define XMT_CTL_DELAY_FCS_0 0x00 // do not delay FCS calcution 580#define XMT_CTL_DELAY_FCS_0 0x00 // do not delay FCS calcution
581#define XMT_CTL_DELAY_FCS_1 0x01 // delay FCS calculation by 1 (4-byte) word 581#define XMT_CTL_DELAY_FCS_1 0x01 // delay FCS calculation by 1 (4-byte) word
582#define XMT_CTL_DELAY_FCS_2 0x02 // delay FCS calculation by 2 (4-byte) words 582#define XMT_CTL_DELAY_FCS_2 0x02 // delay FCS calculation by 2 (4-byte) words
583#define XMT_CTL_DELAY_FCS_3 0x03 // delay FCS calculation by 3 (4-byte) words 583#define XMT_CTL_DELAY_FCS_3 0x03 // delay FCS calculation by 3 (4-byte) words
584 584
585// XMT_DESC XmtBufId definition 585// XMT_DESC XmtBufId definition
586#define XMT_BUF_ID_SHFT 8 // The Xmt buffer ID is formed by dividing 586#define XMT_BUF_ID_SHFT 8 // The Xmt buffer ID is formed by dividing
587 // the buffer (DRAM) address by 256 (or << 8) 587 // the buffer (DRAM) address by 256 (or << 8)
588 588
589/***************************************************************************** 589/*****************************************************************************
590 * Receiver Sequencer Definitions 590 * Receiver Sequencer Definitions
@@ -594,8 +594,8 @@ typedef struct _XMT_DESC {
594#define RCV_EVTQ_RBFID_MASK 0x0000FFFF // bit mask for the Receive Buffer ID 594#define RCV_EVTQ_RBFID_MASK 0x0000FFFF // bit mask for the Receive Buffer ID
595 595
596// Receive Buffer ID definition 596// Receive Buffer ID definition
597#define RCV_BUF_ID_SHFT 5 // The Rcv buffer ID is formed by dividing 597#define RCV_BUF_ID_SHFT 5 // The Rcv buffer ID is formed by dividing
598 // the buffer (DRAM) address by 32 (or << 5) 598 // the buffer (DRAM) address by 32 (or << 5)
599 599
600// Format of the 18 byte Receive Buffer returned by the 600// Format of the 18 byte Receive Buffer returned by the
601// Receive Sequencer for received packets 601// Receive Sequencer for received packets
@@ -623,48 +623,48 @@ typedef struct _RCV_BUF_HDR {
623 * Queue definitions 623 * Queue definitions
624 *****************************************************************************/ 624 *****************************************************************************/
625 625
626// Ingress (read only) queue numbers 626/* Ingress (read only) queue numbers */
627#define PXY_BUF_Q 0 // Proxy Buffer Queue 627#define PXY_BUF_Q 0 /* Proxy Buffer Queue */
628#define HST_EVT_Q 1 // Host Event Queue 628#define HST_EVT_Q 1 /* Host Event Queue */
629#define XMT_BUF_Q 2 // Transmit Buffer Queue 629#define XMT_BUF_Q 2 /* Transmit Buffer Queue */
630#define SKT_EVL_Q 3 // RcvSqr Socket Event Low Priority Queue 630#define SKT_EVL_Q 3 /* RcvSqr Socket Event Low Priority Queue */
631#define RCV_EVL_Q 4 // RcvSqr Rcv Event Low Priority Queue 631#define RCV_EVL_Q 4 /* RcvSqr Rcv Event Low Priority Queue */
632#define SKT_EVH_Q 5 // RcvSqr Socket Event High Priority Queue 632#define SKT_EVH_Q 5 /* RcvSqr Socket Event High Priority Queue */
633#define RCV_EVH_Q 6 // RcvSqr Rcv Event High Priority Queue 633#define RCV_EVH_Q 6 /* RcvSqr Rcv Event High Priority Queue */
634#define DMA_RSP_Q 7 // Dma Response Queue - one per CPU context 634#define DMA_RSP_Q 7 /* Dma Response Queue - one per CPU context */
635// Local (read/write) queue numbers 635/* Local (read/write) queue numbers */
636#define LOCAL_A_Q 8 // Spare local Queue 636#define LOCAL_A_Q 8 /* Spare local Queue */
637#define LOCAL_B_Q 9 // Spare local Queue 637#define LOCAL_B_Q 9 /* Spare local Queue */
638#define LOCAL_C_Q 10 // Spare local Queue 638#define LOCAL_C_Q 10 /* Spare local Queue */
639#define FSM_EVT_Q 11 // Finite-State-Machine Event Queue 639#define FSM_EVT_Q 11 /* Finite-State-Machine Event Queue */
640#define SBF_PAL_Q 12 // System Buffer Physical Address (low) Queue 640#define SBF_PAL_Q 12 /* System Buffer Physical Address (low) Queue */
641#define SBF_PAH_Q 13 // System Buffer Physical Address (high) Queue 641#define SBF_PAH_Q 13 /* System Buffer Physical Address (high) Queue */
642#define SBF_VAL_Q 14 // System Buffer Virtual Address (low) Queue 642#define SBF_VAL_Q 14 /* System Buffer Virtual Address (low) Queue */
643#define SBF_VAH_Q 15 // System Buffer Virtual Address (high) Queue 643#define SBF_VAH_Q 15 /* System Buffer Virtual Address (high) Queue */
644// Egress (write only) queue numbers 644/* Egress (write only) queue numbers */
645#define H2G_CMD_Q 16 // Host to GlbRam DMA Command Queue 645#define H2G_CMD_Q 16 /* Host to GlbRam DMA Command Queue */
646#define H2D_CMD_Q 17 // Host to DRAM DMA Command Queue 646#define H2D_CMD_Q 17 /* Host to DRAM DMA Command Queue */
647#define G2H_CMD_Q 18 // GlbRam to Host DMA Command Queue 647#define G2H_CMD_Q 18 /* GlbRam to Host DMA Command Queue */
648#define G2D_CMD_Q 19 // GlbRam to DRAM DMA Command Queue 648#define G2D_CMD_Q 19 /* GlbRam to DRAM DMA Command Queue */
649#define D2H_CMD_Q 20 // DRAM to Host DMA Command Queue 649#define D2H_CMD_Q 20 /* DRAM to Host DMA Command Queue */
650#define D2G_CMD_Q 21 // DRAM to GlbRam DMA Command Queue 650#define D2G_CMD_Q 21 /* DRAM to GlbRam DMA Command Queue */
651#define D2D_CMD_Q 22 // DRAM to DRAM DMA Command Queue 651#define D2D_CMD_Q 22 /* DRAM to DRAM DMA Command Queue */
652#define PXL_CMD_Q 23 // Low Priority Proxy Command Queue 652#define PXL_CMD_Q 23 /* Low Priority Proxy Command Queue */
653#define PXH_CMD_Q 24 // High Priority Proxy Command Queue 653#define PXH_CMD_Q 24 /* High Priority Proxy Command Queue */
654#define RSQ_CMD_Q 25 // Receive Sequencer Command Queue 654#define RSQ_CMD_Q 25 /* Receive Sequencer Command Queue */
655#define RCV_BUF_Q 26 // Receive Buffer Queue 655#define RCV_BUF_Q 26 /* Receive Buffer Queue */
656 656
657// Bit definitions for the Proxy Command queues (PXL_CMD_Q and PXH_CMD_Q) 657/* Bit definitions for the Proxy Command queues (PXL_CMD_Q and PXH_CMD_Q) */
658#define PXY_COPY_EN 0x00200000 // enable copy of xmt descriptor to xmt command queue 658#define PXY_COPY_EN 0x00200000 /* enable copy of xmt descriptor to xmt command queue */
659#define PXY_SIZE_16 0x00000000 // copy 16 bytes 659#define PXY_SIZE_16 0x00000000 /* copy 16 bytes */
660#define PXY_SIZE_32 0x00100000 // copy 32 bytes 660#define PXY_SIZE_32 0x00100000 /* copy 32 bytes */
661 661
662/***************************************************************************** 662/*****************************************************************************
663 * SXG EEPROM/Flash Configuration Definitions 663 * SXG EEPROM/Flash Configuration Definitions
664 *****************************************************************************/ 664 *****************************************************************************/
665#pragma pack(push, 1) 665#pragma pack(push, 1)
666 666
667// 667/* */
668typedef struct _HW_CFG_DATA { 668typedef struct _HW_CFG_DATA {
669 ushort Addr; 669 ushort Addr;
670 union { 670 union {
@@ -673,22 +673,22 @@ typedef struct _HW_CFG_DATA {
673 }; 673 };
674} HW_CFG_DATA, *PHW_CFG_DATA; 674} HW_CFG_DATA, *PHW_CFG_DATA;
675 675
676// 676/* */
677#define NUM_HW_CFG_ENTRIES ((128/sizeof(HW_CFG_DATA)) - 4) 677#define NUM_HW_CFG_ENTRIES ((128/sizeof(HW_CFG_DATA)) - 4)
678 678
679// MAC address 679/* MAC address */
680typedef struct _SXG_CONFIG_MAC { 680typedef struct _SXG_CONFIG_MAC {
681 unsigned char MacAddr[6]; // MAC Address 681 unsigned char MacAddr[6]; /* MAC Address */
682} SXG_CONFIG_MAC, *PSXG_CONFIG_MAC; 682} SXG_CONFIG_MAC, *PSXG_CONFIG_MAC;
683 683
684// 684/* */
685typedef struct _ATK_FRU { 685typedef struct _ATK_FRU {
686 unsigned char PartNum[6]; 686 unsigned char PartNum[6];
687 unsigned char Revision[2]; 687 unsigned char Revision[2];
688 unsigned char Serial[14]; 688 unsigned char Serial[14];
689} ATK_FRU, *PATK_FRU; 689} ATK_FRU, *PATK_FRU;
690 690
691// OEM FRU Format types 691/* OEM FRU Format types */
692#define ATK_FRU_FORMAT 0x0000 692#define ATK_FRU_FORMAT 0x0000
693#define CPQ_FRU_FORMAT 0x0001 693#define CPQ_FRU_FORMAT 0x0001
694#define DELL_FRU_FORMAT 0x0002 694#define DELL_FRU_FORMAT 0x0002
@@ -697,24 +697,24 @@ typedef struct _ATK_FRU {
697#define EMC_FRU_FORMAT 0x0005 697#define EMC_FRU_FORMAT 0x0005
698#define NO_FRU_FORMAT 0xFFFF 698#define NO_FRU_FORMAT 0xFFFF
699 699
700// EEPROM/Flash Format 700/* EEPROM/Flash Format */
701typedef struct _SXG_CONFIG { 701typedef struct _SXG_CONFIG {
702 // 702 /* */
703 // Section 1 (128 bytes) 703 /* Section 1 (128 bytes) */
704 // 704 /* */
705 ushort MagicWord; // EEPROM/FLASH Magic code 'A5A5' 705 ushort MagicWord; /* EEPROM/FLASH Magic code 'A5A5' */
706 ushort SpiClks; // SPI bus clock dividers 706 ushort SpiClks; /* SPI bus clock dividers */
707 HW_CFG_DATA HwCfg[NUM_HW_CFG_ENTRIES]; 707 HW_CFG_DATA HwCfg[NUM_HW_CFG_ENTRIES];
708 // 708 /* */
709 // 709 /* */
710 // 710 /* */
711 ushort Version; // EEPROM format version 711 ushort Version; /* EEPROM format version */
712 SXG_CONFIG_MAC MacAddr[4]; // space for 4 MAC addresses 712 SXG_CONFIG_MAC MacAddr[4]; /* space for 4 MAC addresses */
713 ATK_FRU AtkFru; // FRU information 713 ATK_FRU AtkFru; /* FRU information */
714 ushort OemFruFormat; // OEM FRU format type 714 ushort OemFruFormat; /* OEM FRU format type */
715 unsigned char OemFru[76]; // OEM FRU information (optional) 715 unsigned char OemFru[76]; /* OEM FRU information (optional) */
716 ushort Checksum; // Checksum of section 2 716 ushort Checksum; /* Checksum of section 2 */
717 // CS info XXXTODO 717 /* CS info XXXTODO */
718} SXG_CONFIG, *PSXG_CONFIG; 718} SXG_CONFIG, *PSXG_CONFIG;
719#pragma pack(pop) 719#pragma pack(pop)
720 720
@@ -723,12 +723,12 @@ typedef struct _SXG_CONFIG {
723 *****************************************************************************/ 723 *****************************************************************************/
724 724
725// Sahara (ASIC level) defines 725// Sahara (ASIC level) defines
726#define SAHARA_GRAM_SIZE 0x020000 // GRAM size - 128 KB 726#define SAHARA_GRAM_SIZE 0x020000 // GRAM size - 128 KB
727#define SAHARA_DRAM_SIZE 0x200000 // DRAM size - 2 MB 727#define SAHARA_DRAM_SIZE 0x200000 // DRAM size - 2 MB
728#define SAHARA_QRAM_SIZE 0x004000 // QRAM size - 16K entries (64 KB) 728#define SAHARA_QRAM_SIZE 0x004000 // QRAM size - 16K entries (64 KB)
729#define SAHARA_WCS_SIZE 0x002000 // WCS - 8K instructions (x 108 bits) 729#define SAHARA_WCS_SIZE 0x002000 // WCS - 8K instructions (x 108 bits)
730 730
731// Arabia (board level) defines 731// Arabia (board level) defines
732#define FLASH_SIZE 0x080000 // 512 KB (4 Mb) 732#define FLASH_SIZE 0x080000 // 512 KB (4 Mb)
733#define EEPROM_SIZE_XFMR 512 // true EEPROM size (bytes), including xfmr area 733#define EEPROM_SIZE_XFMR 512 // true EEPROM size (bytes), including xfmr area
734#define EEPROM_SIZE_NO_XFMR 256 // EEPROM size excluding xfmr area 734#define EEPROM_SIZE_NO_XFMR 256 // EEPROM size excluding xfmr area
diff --git a/drivers/staging/sxg/sxgphycode.h b/drivers/staging/sxg/sxgphycode.h
index 26b36c81eb1a..8dbaeda7eca4 100644
--- a/drivers/staging/sxg/sxgphycode.h
+++ b/drivers/staging/sxg/sxgphycode.h
@@ -34,7 +34,7 @@ static PHY_UCODE PhyUcode[] = {
34 */ 34 */
35 /* Addr, Data */ 35 /* Addr, Data */
36 {0xc017, 0xfeb0}, /* flip RX_LOS polarity (mandatory */ 36 {0xc017, 0xfeb0}, /* flip RX_LOS polarity (mandatory */
37 /* patch for SFP+ applications) */ 37 /* patch for SFP+ applications) */
38 {0xC001, 0x0428}, /* flip RX serial polarity */ 38 {0xC001, 0x0428}, /* flip RX serial polarity */
39 39
40 {0xc013, 0xf341}, /* invert lxmit clock (mandatory patch) */ 40 {0xc013, 0xf341}, /* invert lxmit clock (mandatory patch) */
@@ -43,7 +43,7 @@ static PHY_UCODE PhyUcode[] = {
43 {0xc210, 0x8000}, /* reset datapath (mandatory patch) */ 43 {0xc210, 0x8000}, /* reset datapath (mandatory patch) */
44 {0xc210, 0x0000}, /* reset datapath (mandatory patch) */ 44 {0xc210, 0x0000}, /* reset datapath (mandatory patch) */
45 {0x0000, 0x0032}, /* wait for 50ms for datapath reset to */ 45 {0x0000, 0x0032}, /* wait for 50ms for datapath reset to */
46 /* complete. (mandatory patch) */ 46 /* complete. (mandatory patch) */
47 47
48 /* Configure the LED's */ 48 /* Configure the LED's */
49 {0xc214, 0x0099}, /* configure the LED drivers */ 49 {0xc214, 0x0099}, /* configure the LED drivers */
@@ -52,15 +52,15 @@ static PHY_UCODE PhyUcode[] = {
52 52
53 /* Transceiver-specific MDIO Patches: */ 53 /* Transceiver-specific MDIO Patches: */
54 {0xc010, 0x448a}, /* (bit 14) mask out high BER input from the */ 54 {0xc010, 0x448a}, /* (bit 14) mask out high BER input from the */
55 /* LOS signal in 1.000A */ 55 /* LOS signal in 1.000A */
56 /* (mandatory patch for SR code)*/ 56 /* (mandatory patch for SR code) */
57 {0xc003, 0x0181}, /* (bit 7) enable the CDR inc setting in */ 57 {0xc003, 0x0181}, /* (bit 7) enable the CDR inc setting in */
58 /* 1.C005 (mandatory patch for SR code) */ 58 /* 1.C005 (mandatory patch for SR code) */
59 59
60 /* Transceiver-specific Microcontroller Initialization: */ 60 /* Transceiver-specific Microcontroller Initialization: */
61 {0xc04a, 0x5200}, /* activate microcontroller and pause */ 61 {0xc04a, 0x5200}, /* activate microcontroller and pause */
62 {0x0000, 0x0032}, /* wait 50ms for microcontroller before */ 62 {0x0000, 0x0032}, /* wait 50ms for microcontroller before */
63 /* writing in code. */ 63 /* writing in code. */
64 64
65 /* code block starts here: */ 65 /* code block starts here: */
66 {0xcc00, 0x2009}, 66 {0xcc00, 0x2009},
diff --git a/drivers/staging/usbip/usbip_common.c b/drivers/staging/usbip/usbip_common.c
index e64918f42ff7..72e209276ea7 100644
--- a/drivers/staging/usbip/usbip_common.c
+++ b/drivers/staging/usbip/usbip_common.c
@@ -221,7 +221,7 @@ static void usbip_dump_request_type(__u8 rt)
221static void usbip_dump_usb_ctrlrequest(struct usb_ctrlrequest *cmd) 221static void usbip_dump_usb_ctrlrequest(struct usb_ctrlrequest *cmd)
222{ 222{
223 if (!cmd) { 223 if (!cmd) {
224 printk(" %s : null pointer\n", __FUNCTION__); 224 printk(" %s : null pointer\n", __func__);
225 return; 225 return;
226 } 226 }
227 227
diff --git a/drivers/staging/usbip/vhci_rx.c b/drivers/staging/usbip/vhci_rx.c
index 933ccaf50afb..58e3995d0e2c 100644
--- a/drivers/staging/usbip/vhci_rx.c
+++ b/drivers/staging/usbip/vhci_rx.c
@@ -202,7 +202,7 @@ static void vhci_rx_pdu(struct usbip_device *ud)
202 ret = usbip_xmit(0, ud->tcp_socket, (char *) &pdu, sizeof(pdu), 0); 202 ret = usbip_xmit(0, ud->tcp_socket, (char *) &pdu, sizeof(pdu), 0);
203 if (ret != sizeof(pdu)) { 203 if (ret != sizeof(pdu)) {
204 uerr("receiving pdu failed! size is %d, should be %d\n", 204 uerr("receiving pdu failed! size is %d, should be %d\n",
205 ret, sizeof(pdu)); 205 ret, (unsigned int)sizeof(pdu));
206 usbip_event_add(ud, VDEV_EVENT_ERROR_TCP); 206 usbip_event_add(ud, VDEV_EVENT_ERROR_TCP);
207 return; 207 return;
208 } 208 }
diff --git a/drivers/staging/winbond/Kconfig b/drivers/staging/winbond/Kconfig
index 10d72bec88a9..425219ed7ab9 100644
--- a/drivers/staging/winbond/Kconfig
+++ b/drivers/staging/winbond/Kconfig
@@ -1,6 +1,6 @@
1config W35UND 1config W35UND
2 tristate "Winbond driver" 2 tristate "Winbond driver"
3 depends on MAC80211 && WLAN_80211 && EXPERIMENTAL && !4KSTACKS 3 depends on MAC80211 && WLAN_80211 && USB && EXPERIMENTAL && !4KSTACKS
4 default n 4 default n
5 ---help--- 5 ---help---
6 This is highly experimental driver for winbond wifi card on some Kohjinsha notebooks 6 This is highly experimental driver for winbond wifi card on some Kohjinsha notebooks
diff --git a/drivers/staging/winbond/README b/drivers/staging/winbond/README
index 707b6b354dc5..cb944e4bf174 100644
--- a/drivers/staging/winbond/README
+++ b/drivers/staging/winbond/README
@@ -5,6 +5,7 @@ TODO:
5 - remove typedefs 5 - remove typedefs
6 - remove unused ioctls 6 - remove unused ioctls
7 - use cfg80211 for regulatory stuff 7 - use cfg80211 for regulatory stuff
8 - fix 4k stack problems
8 9
9Please send patches to Greg Kroah-Hartman <greg@kroah.com> and 10Please send patches to Greg Kroah-Hartman <greg@kroah.com> and
10Pavel Machek <pavel@suse.cz> 11Pavel Machek <pavel@suse.cz>
diff --git a/drivers/staging/winbond/bss_f.h b/drivers/staging/winbond/bss_f.h
index c957bc94f08d..013183153993 100644
--- a/drivers/staging/winbond/bss_f.h
+++ b/drivers/staging/winbond/bss_f.h
@@ -24,7 +24,7 @@ void DesiredRate2InfoElement(PWB32_ADAPTER Adapter, u8 *addr, u16 *iFildOffset,
24 u8 *pBasicRateSet, u8 BasicRateCount, 24 u8 *pBasicRateSet, u8 BasicRateCount,
25 u8 *pOperationRateSet, u8 OperationRateCount); 25 u8 *pOperationRateSet, u8 OperationRateCount);
26void BSSAddIBSSdata(PWB32_ADAPTER Adapter, PWB_BSSDESCRIPTION psDesData); 26void BSSAddIBSSdata(PWB32_ADAPTER Adapter, PWB_BSSDESCRIPTION psDesData);
27unsigned char boCmpMacAddr( PUCHAR, PUCHAR ); 27unsigned char boCmpMacAddr( u8 *, u8 *);
28unsigned char boCmpSSID(struct SSID_Element *psSSID1, struct SSID_Element *psSSID2); 28unsigned char boCmpSSID(struct SSID_Element *psSSID1, struct SSID_Element *psSSID2);
29u16 wBSSfindSSID(PWB32_ADAPTER Adapter, struct SSID_Element *psSsid); 29u16 wBSSfindSSID(PWB32_ADAPTER Adapter, struct SSID_Element *psSsid);
30u16 wRoamingQuery(PWB32_ADAPTER Adapter); 30u16 wRoamingQuery(PWB32_ADAPTER Adapter);
@@ -42,11 +42,11 @@ void RateReSortForSRate(PWB32_ADAPTER Adapter, u8 *RateArray, u8 num);
42void Assemble_IE(PWB32_ADAPTER Adapter, u16 wBssIdx); 42void Assemble_IE(PWB32_ADAPTER Adapter, u16 wBssIdx);
43void SetMaxTxRate(PWB32_ADAPTER Adapter); 43void SetMaxTxRate(PWB32_ADAPTER Adapter);
44 44
45void CreateWpaIE(PWB32_ADAPTER Adapter, u16* iFildOffset, PUCHAR msg, struct Management_Frame* msgHeader, 45void CreateWpaIE(PWB32_ADAPTER Adapter, u16* iFildOffset, u8 *msg, struct Management_Frame* msgHeader,
46 struct Association_Request_Frame_Body* msgBody, u16 iMSindex); //added by WS 05/14/05 46 struct Association_Request_Frame_Body* msgBody, u16 iMSindex); //added by WS 05/14/05
47 47
48#ifdef _WPA2_ 48#ifdef _WPA2_
49void CreateRsnIE(PWB32_ADAPTER Adapter, u16* iFildOffset, PUCHAR msg, struct Management_Frame* msgHeader, 49void CreateRsnIE(PWB32_ADAPTER Adapter, u16* iFildOffset, u8 *msg, struct Management_Frame* msgHeader,
50 struct Association_Request_Frame_Body* msgBody, u16 iMSindex);//added by WS 05/14/05 50 struct Association_Request_Frame_Body* msgBody, u16 iMSindex);//added by WS 05/14/05
51 51
52u16 SearchPmkid(PWB32_ADAPTER Adapter, struct Management_Frame* msgHeader, 52u16 SearchPmkid(PWB32_ADAPTER Adapter, struct Management_Frame* msgHeader,
diff --git a/drivers/staging/winbond/ds_tkip.h b/drivers/staging/winbond/ds_tkip.h
index 29e5055b45a1..6841d66e7e8c 100644
--- a/drivers/staging/winbond/ds_tkip.h
+++ b/drivers/staging/winbond/ds_tkip.h
@@ -25,9 +25,9 @@ typedef struct tkip
25 s32 bytes_in_M; // # bytes in M 25 s32 bytes_in_M; // # bytes in M
26} tkip_t; 26} tkip_t;
27 27
28//void _append_data( PUCHAR pData, u16 size, tkip_t *p ); 28//void _append_data( u8 *pData, u16 size, tkip_t *p );
29void Mds_MicGet( void* Adapter, void* pRxLayer1, PUCHAR pKey, PUCHAR pMic ); 29void Mds_MicGet( void* Adapter, void* pRxLayer1, u8 *pKey, u8 *pMic );
30void Mds_MicFill( void* Adapter, void* pDes, PUCHAR XmitBufAddress ); 30void Mds_MicFill( void* Adapter, void* pDes, u8 *XmitBufAddress );
31 31
32 32
33 33
diff --git a/drivers/staging/winbond/linux/common.h b/drivers/staging/winbond/linux/common.h
index 6b00bad74f78..712a86cfa68b 100644
--- a/drivers/staging/winbond/linux/common.h
+++ b/drivers/staging/winbond/linux/common.h
@@ -39,14 +39,6 @@
39// Common type definition 39// Common type definition
40//=============================================================== 40//===============================================================
41 41
42typedef u8* PUCHAR;
43typedef s8* PCHAR;
44typedef u8* PBOOLEAN;
45typedef u16* PUSHORT;
46typedef u32* PULONG;
47typedef s16* PSHORT;
48
49
50//=========================================== 42//===========================================
51#define IGNORE 2 43#define IGNORE 2
52#define SUCCESS 1 44#define SUCCESS 1
@@ -110,16 +102,9 @@ typedef struct urb * PURB;
110#define OS_ATOMIC_READ( _A, _V ) _V 102#define OS_ATOMIC_READ( _A, _V ) _V
111#define OS_ATOMIC_INC( _A, _V ) EncapAtomicInc( _A, (void*)_V ) 103#define OS_ATOMIC_INC( _A, _V ) EncapAtomicInc( _A, (void*)_V )
112#define OS_ATOMIC_DEC( _A, _V ) EncapAtomicDec( _A, (void*)_V ) 104#define OS_ATOMIC_DEC( _A, _V ) EncapAtomicDec( _A, (void*)_V )
113#define OS_MEMORY_CLEAR( _A, _S ) memset( (PUCHAR)_A,0,_S) 105#define OS_MEMORY_CLEAR( _A, _S ) memset( (u8 *)_A,0,_S)
114#define OS_MEMORY_COMPARE( _A, _B, _S ) (memcmp(_A,_B,_S)? 0 : 1) // Definition is reverse with Ndis 1: the same 0: different 106#define OS_MEMORY_COMPARE( _A, _B, _S ) (memcmp(_A,_B,_S)? 0 : 1) // Definition is reverse with Ndis 1: the same 0: different
115 107
116
117#define OS_SPIN_LOCK spinlock_t
118#define OS_SPIN_LOCK_ALLOCATE( _S ) spin_lock_init( _S );
119#define OS_SPIN_LOCK_FREE( _S )
120#define OS_SPIN_LOCK_ACQUIRED( _S ) spin_lock_irq( _S )
121#define OS_SPIN_LOCK_RELEASED( _S ) spin_unlock_irq( _S );
122
123#define OS_TIMER struct timer_list 108#define OS_TIMER struct timer_list
124#define OS_TIMER_INITIAL( _T, _F, _P ) \ 109#define OS_TIMER_INITIAL( _T, _F, _P ) \
125{ \ 110{ \
diff --git a/drivers/staging/winbond/linux/wb35reg.c b/drivers/staging/winbond/linux/wb35reg.c
index 2c0b454e8cad..ebb6db5438a4 100644
--- a/drivers/staging/winbond/linux/wb35reg.c
+++ b/drivers/staging/winbond/linux/wb35reg.c
@@ -10,7 +10,7 @@ extern void phy_calibration_winbond(hw_data_t *phw_data, u32 frequency);
10// Flag : AUTO_INCREMENT - RegisterNo will auto increment 4 10// Flag : AUTO_INCREMENT - RegisterNo will auto increment 4
11// NO_INCREMENT - Function will write data into the same register 11// NO_INCREMENT - Function will write data into the same register
12unsigned char 12unsigned char
13Wb35Reg_BurstWrite(phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterData, u8 NumberOfData, u8 Flag) 13Wb35Reg_BurstWrite(phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterData, u8 NumberOfData, u8 Flag)
14{ 14{
15 PWB35REG pWb35Reg = &pHwData->Wb35Reg; 15 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
16 PURB pUrb = NULL; 16 PURB pUrb = NULL;
@@ -30,13 +30,13 @@ Wb35Reg_BurstWrite(phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterData, u8
30 if( pUrb && pRegQueue ) { 30 if( pUrb && pRegQueue ) {
31 pRegQueue->DIRECT = 2;// burst write register 31 pRegQueue->DIRECT = 2;// burst write register
32 pRegQueue->INDEX = RegisterNo; 32 pRegQueue->INDEX = RegisterNo;
33 pRegQueue->pBuffer = (PULONG)((PUCHAR)pRegQueue + sizeof(REG_QUEUE)); 33 pRegQueue->pBuffer = (u32 *)((u8 *)pRegQueue + sizeof(REG_QUEUE));
34 memcpy( pRegQueue->pBuffer, pRegisterData, DataSize ); 34 memcpy( pRegQueue->pBuffer, pRegisterData, DataSize );
35 //the function for reversing register data from little endian to big endian 35 //the function for reversing register data from little endian to big endian
36 for( i=0; i<NumberOfData ; i++ ) 36 for( i=0; i<NumberOfData ; i++ )
37 pRegQueue->pBuffer[i] = cpu_to_le32( pRegQueue->pBuffer[i] ); 37 pRegQueue->pBuffer[i] = cpu_to_le32( pRegQueue->pBuffer[i] );
38 38
39 dr = (struct usb_ctrlrequest *)((PUCHAR)pRegQueue + sizeof(REG_QUEUE) + DataSize); 39 dr = (struct usb_ctrlrequest *)((u8 *)pRegQueue + sizeof(REG_QUEUE) + DataSize);
40 dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE; 40 dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE;
41 dr->bRequest = 0x04; // USB or vendor-defined request code, burst mode 41 dr->bRequest = 0x04; // USB or vendor-defined request code, burst mode
42 dr->wValue = cpu_to_le16( Flag ); // 0: Register number auto-increment, 1: No auto increment 42 dr->wValue = cpu_to_le16( Flag ); // 0: Register number auto-increment, 1: No auto increment
@@ -46,14 +46,14 @@ Wb35Reg_BurstWrite(phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterData, u8
46 pRegQueue->pUsbReq = dr; 46 pRegQueue->pUsbReq = dr;
47 pRegQueue->pUrb = pUrb; 47 pRegQueue->pUrb = pUrb;
48 48
49 OS_SPIN_LOCK_ACQUIRED( &pWb35Reg->EP0VM_spin_lock ); 49 spin_lock_irq( &pWb35Reg->EP0VM_spin_lock );
50 if (pWb35Reg->pRegFirst == NULL) 50 if (pWb35Reg->pRegFirst == NULL)
51 pWb35Reg->pRegFirst = pRegQueue; 51 pWb35Reg->pRegFirst = pRegQueue;
52 else 52 else
53 pWb35Reg->pRegLast->Next = pRegQueue; 53 pWb35Reg->pRegLast->Next = pRegQueue;
54 pWb35Reg->pRegLast = pRegQueue; 54 pWb35Reg->pRegLast = pRegQueue;
55 55
56 OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock ); 56 spin_unlock_irq( &pWb35Reg->EP0VM_spin_lock );
57 57
58 // Start EP0VM 58 // Start EP0VM
59 Wb35Reg_EP0VM_start(pHwData); 59 Wb35Reg_EP0VM_start(pHwData);
@@ -181,7 +181,7 @@ Wb35Reg_Write( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue )
181 pRegQueue->INDEX = RegisterNo; 181 pRegQueue->INDEX = RegisterNo;
182 pRegQueue->VALUE = cpu_to_le32(RegisterValue); 182 pRegQueue->VALUE = cpu_to_le32(RegisterValue);
183 pRegQueue->RESERVED_VALID = FALSE; 183 pRegQueue->RESERVED_VALID = FALSE;
184 dr = (struct usb_ctrlrequest *)((PUCHAR)pRegQueue + sizeof(REG_QUEUE)); 184 dr = (struct usb_ctrlrequest *)((u8 *)pRegQueue + sizeof(REG_QUEUE));
185 dr->bRequestType = USB_TYPE_VENDOR|USB_DIR_OUT |USB_RECIP_DEVICE; 185 dr->bRequestType = USB_TYPE_VENDOR|USB_DIR_OUT |USB_RECIP_DEVICE;
186 dr->bRequest = 0x03; // USB or vendor-defined request code, burst mode 186 dr->bRequest = 0x03; // USB or vendor-defined request code, burst mode
187 dr->wValue = cpu_to_le16(0x0); 187 dr->wValue = cpu_to_le16(0x0);
@@ -193,14 +193,14 @@ Wb35Reg_Write( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue )
193 pRegQueue->pUsbReq = dr; 193 pRegQueue->pUsbReq = dr;
194 pRegQueue->pUrb = pUrb; 194 pRegQueue->pUrb = pUrb;
195 195
196 OS_SPIN_LOCK_ACQUIRED(&pWb35Reg->EP0VM_spin_lock ); 196 spin_lock_irq(&pWb35Reg->EP0VM_spin_lock );
197 if (pWb35Reg->pRegFirst == NULL) 197 if (pWb35Reg->pRegFirst == NULL)
198 pWb35Reg->pRegFirst = pRegQueue; 198 pWb35Reg->pRegFirst = pRegQueue;
199 else 199 else
200 pWb35Reg->pRegLast->Next = pRegQueue; 200 pWb35Reg->pRegLast->Next = pRegQueue;
201 pWb35Reg->pRegLast = pRegQueue; 201 pWb35Reg->pRegLast = pRegQueue;
202 202
203 OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock ); 203 spin_unlock_irq( &pWb35Reg->EP0VM_spin_lock );
204 204
205 // Start EP0VM 205 // Start EP0VM
206 Wb35Reg_EP0VM_start(pHwData); 206 Wb35Reg_EP0VM_start(pHwData);
@@ -220,7 +220,7 @@ Wb35Reg_Write( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue )
220// FALSE : register not support 220// FALSE : register not support
221unsigned char 221unsigned char
222Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue, 222Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue,
223 PCHAR pValue, s8 Len) 223 s8 *pValue, s8 Len)
224{ 224{
225 PWB35REG pWb35Reg = &pHwData->Wb35Reg; 225 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
226 struct usb_ctrlrequest *dr; 226 struct usb_ctrlrequest *dr;
@@ -243,7 +243,7 @@ Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData, u16 RegisterNo, u32 Register
243 //NOTE : Users must guarantee the size of value will not exceed the buffer size. 243 //NOTE : Users must guarantee the size of value will not exceed the buffer size.
244 memcpy(pRegQueue->RESERVED, pValue, Len); 244 memcpy(pRegQueue->RESERVED, pValue, Len);
245 pRegQueue->RESERVED_VALID = TRUE; 245 pRegQueue->RESERVED_VALID = TRUE;
246 dr = (struct usb_ctrlrequest *)((PUCHAR)pRegQueue + sizeof(REG_QUEUE)); 246 dr = (struct usb_ctrlrequest *)((u8 *)pRegQueue + sizeof(REG_QUEUE));
247 dr->bRequestType = USB_TYPE_VENDOR|USB_DIR_OUT |USB_RECIP_DEVICE; 247 dr->bRequestType = USB_TYPE_VENDOR|USB_DIR_OUT |USB_RECIP_DEVICE;
248 dr->bRequest = 0x03; // USB or vendor-defined request code, burst mode 248 dr->bRequest = 0x03; // USB or vendor-defined request code, burst mode
249 dr->wValue = cpu_to_le16(0x0); 249 dr->wValue = cpu_to_le16(0x0);
@@ -254,14 +254,14 @@ Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData, u16 RegisterNo, u32 Register
254 pRegQueue->Next = NULL; 254 pRegQueue->Next = NULL;
255 pRegQueue->pUsbReq = dr; 255 pRegQueue->pUsbReq = dr;
256 pRegQueue->pUrb = pUrb; 256 pRegQueue->pUrb = pUrb;
257 OS_SPIN_LOCK_ACQUIRED (&pWb35Reg->EP0VM_spin_lock ); 257 spin_lock_irq (&pWb35Reg->EP0VM_spin_lock );
258 if( pWb35Reg->pRegFirst == NULL ) 258 if( pWb35Reg->pRegFirst == NULL )
259 pWb35Reg->pRegFirst = pRegQueue; 259 pWb35Reg->pRegFirst = pRegQueue;
260 else 260 else
261 pWb35Reg->pRegLast->Next = pRegQueue; 261 pWb35Reg->pRegLast->Next = pRegQueue;
262 pWb35Reg->pRegLast = pRegQueue; 262 pWb35Reg->pRegLast = pRegQueue;
263 263
264 OS_SPIN_LOCK_RELEASED ( &pWb35Reg->EP0VM_spin_lock ); 264 spin_unlock_irq ( &pWb35Reg->EP0VM_spin_lock );
265 265
266 // Start EP0VM 266 // Start EP0VM
267 Wb35Reg_EP0VM_start(pHwData); 267 Wb35Reg_EP0VM_start(pHwData);
@@ -278,10 +278,10 @@ Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData, u16 RegisterNo, u32 Register
278// FALSE : register not support 278// FALSE : register not support
279// pRegisterValue : It must be a resident buffer due to asynchronous read register. 279// pRegisterValue : It must be a resident buffer due to asynchronous read register.
280unsigned char 280unsigned char
281Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterValue ) 281Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue )
282{ 282{
283 PWB35REG pWb35Reg = &pHwData->Wb35Reg; 283 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
284 PULONG pltmp = pRegisterValue; 284 u32 * pltmp = pRegisterValue;
285 int ret = -1; 285 int ret = -1;
286 286
287 // Module shutdown 287 // Module shutdown
@@ -327,7 +327,7 @@ Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterValue
327// FALSE : register not support 327// FALSE : register not support
328// pRegisterValue : It must be a resident buffer due to asynchronous read register. 328// pRegisterValue : It must be a resident buffer due to asynchronous read register.
329unsigned char 329unsigned char
330Wb35Reg_Read(phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterValue ) 330Wb35Reg_Read(phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue )
331{ 331{
332 PWB35REG pWb35Reg = &pHwData->Wb35Reg; 332 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
333 struct usb_ctrlrequest * dr; 333 struct usb_ctrlrequest * dr;
@@ -348,7 +348,7 @@ Wb35Reg_Read(phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterValue )
348 pRegQueue->DIRECT = 0;// read register 348 pRegQueue->DIRECT = 0;// read register
349 pRegQueue->INDEX = RegisterNo; 349 pRegQueue->INDEX = RegisterNo;
350 pRegQueue->pBuffer = pRegisterValue; 350 pRegQueue->pBuffer = pRegisterValue;
351 dr = (struct usb_ctrlrequest *)((PUCHAR)pRegQueue + sizeof(REG_QUEUE)); 351 dr = (struct usb_ctrlrequest *)((u8 *)pRegQueue + sizeof(REG_QUEUE));
352 dr->bRequestType = USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN; 352 dr->bRequestType = USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN;
353 dr->bRequest = 0x01; // USB or vendor-defined request code, burst mode 353 dr->bRequest = 0x01; // USB or vendor-defined request code, burst mode
354 dr->wValue = cpu_to_le16(0x0); 354 dr->wValue = cpu_to_le16(0x0);
@@ -359,14 +359,14 @@ Wb35Reg_Read(phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterValue )
359 pRegQueue->Next = NULL; 359 pRegQueue->Next = NULL;
360 pRegQueue->pUsbReq = dr; 360 pRegQueue->pUsbReq = dr;
361 pRegQueue->pUrb = pUrb; 361 pRegQueue->pUrb = pUrb;
362 OS_SPIN_LOCK_ACQUIRED ( &pWb35Reg->EP0VM_spin_lock ); 362 spin_lock_irq ( &pWb35Reg->EP0VM_spin_lock );
363 if( pWb35Reg->pRegFirst == NULL ) 363 if( pWb35Reg->pRegFirst == NULL )
364 pWb35Reg->pRegFirst = pRegQueue; 364 pWb35Reg->pRegFirst = pRegQueue;
365 else 365 else
366 pWb35Reg->pRegLast->Next = pRegQueue; 366 pWb35Reg->pRegLast->Next = pRegQueue;
367 pWb35Reg->pRegLast = pRegQueue; 367 pWb35Reg->pRegLast = pRegQueue;
368 368
369 OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock ); 369 spin_unlock_irq( &pWb35Reg->EP0VM_spin_lock );
370 370
371 // Start EP0VM 371 // Start EP0VM
372 Wb35Reg_EP0VM_start( pHwData ); 372 Wb35Reg_EP0VM_start( pHwData );
@@ -399,7 +399,7 @@ Wb35Reg_EP0VM(phw_data_t pHwData )
399 PWB35REG pWb35Reg = &pHwData->Wb35Reg; 399 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
400 PURB pUrb; 400 PURB pUrb;
401 struct usb_ctrlrequest *dr; 401 struct usb_ctrlrequest *dr;
402 PULONG pBuffer; 402 u32 * pBuffer;
403 int ret = -1; 403 int ret = -1;
404 PREG_QUEUE pRegQueue; 404 PREG_QUEUE pRegQueue;
405 405
@@ -411,9 +411,9 @@ Wb35Reg_EP0VM(phw_data_t pHwData )
411 goto cleanup; 411 goto cleanup;
412 412
413 // Get the register data and send to USB through Irp 413 // Get the register data and send to USB through Irp
414 OS_SPIN_LOCK_ACQUIRED( &pWb35Reg->EP0VM_spin_lock ); 414 spin_lock_irq( &pWb35Reg->EP0VM_spin_lock );
415 pRegQueue = pWb35Reg->pRegFirst; 415 pRegQueue = pWb35Reg->pRegFirst;
416 OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock ); 416 spin_unlock_irq( &pWb35Reg->EP0VM_spin_lock );
417 417
418 if (!pRegQueue) 418 if (!pRegQueue)
419 goto cleanup; 419 goto cleanup;
@@ -429,7 +429,7 @@ Wb35Reg_EP0VM(phw_data_t pHwData )
429 429
430 usb_fill_control_urb( pUrb, pHwData->WbUsb.udev, 430 usb_fill_control_urb( pUrb, pHwData->WbUsb.udev,
431 REG_DIRECTION(pHwData->WbUsb.udev,pRegQueue), 431 REG_DIRECTION(pHwData->WbUsb.udev,pRegQueue),
432 (PUCHAR)dr,pBuffer,cpu_to_le16(dr->wLength), 432 (u8 *)dr,pBuffer,cpu_to_le16(dr->wLength),
433 Wb35Reg_EP0VM_complete, (void*)pHwData); 433 Wb35Reg_EP0VM_complete, (void*)pHwData);
434 434
435 pWb35Reg->EP0vm_state = VM_RUNNING; 435 pWb35Reg->EP0vm_state = VM_RUNNING;
@@ -468,12 +468,12 @@ Wb35Reg_EP0VM_complete(PURB pUrb)
468 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Reg->RegFireCount ); 468 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Reg->RegFireCount );
469 } else { 469 } else {
470 // Complete to send, remove the URB from the first 470 // Complete to send, remove the URB from the first
471 OS_SPIN_LOCK_ACQUIRED( &pWb35Reg->EP0VM_spin_lock ); 471 spin_lock_irq( &pWb35Reg->EP0VM_spin_lock );
472 pRegQueue = pWb35Reg->pRegFirst; 472 pRegQueue = pWb35Reg->pRegFirst;
473 if (pRegQueue == pWb35Reg->pRegLast) 473 if (pRegQueue == pWb35Reg->pRegLast)
474 pWb35Reg->pRegLast = NULL; 474 pWb35Reg->pRegLast = NULL;
475 pWb35Reg->pRegFirst = pWb35Reg->pRegFirst->Next; 475 pWb35Reg->pRegFirst = pWb35Reg->pRegFirst->Next;
476 OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock ); 476 spin_unlock_irq( &pWb35Reg->EP0VM_spin_lock );
477 477
478 if (pWb35Reg->EP0VM_status) { 478 if (pWb35Reg->EP0VM_status) {
479#ifdef _PE_REG_DUMP_ 479#ifdef _PE_REG_DUMP_
@@ -513,7 +513,7 @@ Wb35Reg_destroy(phw_data_t pHwData)
513 OS_SLEEP(10000); // Delay for waiting function enter 940623.1.b 513 OS_SLEEP(10000); // Delay for waiting function enter 940623.1.b
514 514
515 // Release all the data in RegQueue 515 // Release all the data in RegQueue
516 OS_SPIN_LOCK_ACQUIRED( &pWb35Reg->EP0VM_spin_lock ); 516 spin_lock_irq( &pWb35Reg->EP0VM_spin_lock );
517 pRegQueue = pWb35Reg->pRegFirst; 517 pRegQueue = pWb35Reg->pRegFirst;
518 while (pRegQueue) { 518 while (pRegQueue) {
519 if (pRegQueue == pWb35Reg->pRegLast) 519 if (pRegQueue == pWb35Reg->pRegLast)
@@ -521,7 +521,7 @@ Wb35Reg_destroy(phw_data_t pHwData)
521 pWb35Reg->pRegFirst = pWb35Reg->pRegFirst->Next; 521 pWb35Reg->pRegFirst = pWb35Reg->pRegFirst->Next;
522 522
523 pUrb = pRegQueue->pUrb; 523 pUrb = pRegQueue->pUrb;
524 OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock ); 524 spin_unlock_irq( &pWb35Reg->EP0VM_spin_lock );
525 if (pUrb) { 525 if (pUrb) {
526 usb_free_urb(pUrb); 526 usb_free_urb(pUrb);
527 kfree(pRegQueue); 527 kfree(pRegQueue);
@@ -530,14 +530,11 @@ Wb35Reg_destroy(phw_data_t pHwData)
530 WBDEBUG(("EP0 queue release error\n")); 530 WBDEBUG(("EP0 queue release error\n"));
531 #endif 531 #endif
532 } 532 }
533 OS_SPIN_LOCK_ACQUIRED( &pWb35Reg->EP0VM_spin_lock ); 533 spin_lock_irq( &pWb35Reg->EP0VM_spin_lock );
534 534
535 pRegQueue = pWb35Reg->pRegFirst; 535 pRegQueue = pWb35Reg->pRegFirst;
536 } 536 }
537 OS_SPIN_LOCK_RELEASED( &pWb35Reg->EP0VM_spin_lock ); 537 spin_unlock_irq( &pWb35Reg->EP0VM_spin_lock );
538
539 // Free resource
540 OS_SPIN_LOCK_FREE( &pWb35Reg->EP0VM_spin_lock );
541} 538}
542 539
543//==================================================================================== 540//====================================================================================
@@ -550,7 +547,7 @@ unsigned char Wb35Reg_initial(phw_data_t pHwData)
550 u32 SoftwareSet, VCO_trim, TxVga, Region_ScanInterval; 547 u32 SoftwareSet, VCO_trim, TxVga, Region_ScanInterval;
551 548
552 // Spin lock is acquired for read and write IRP command 549 // Spin lock is acquired for read and write IRP command
553 OS_SPIN_LOCK_ALLOCATE( &pWb35Reg->EP0VM_spin_lock ); 550 spin_lock_init( &pWb35Reg->EP0VM_spin_lock );
554 551
555 // Getting RF module type from EEPROM ------------------------------------ 552 // Getting RF module type from EEPROM ------------------------------------
556 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x080d0000 ); // Start EEPROM access + Read + address(0x0d) 553 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x080d0000 ); // Start EEPROM access + Read + address(0x0d)
@@ -655,7 +652,7 @@ unsigned char Wb35Reg_initial(phw_data_t pHwData)
655// version in _GENREQ.ASM of the DWB NE1000/2000 driver. 652// version in _GENREQ.ASM of the DWB NE1000/2000 driver.
656//================================================================================== 653//==================================================================================
657u32 654u32
658CardComputeCrc(PUCHAR Buffer, u32 Length) 655CardComputeCrc(u8 * Buffer, u32 Length)
659{ 656{
660 u32 Crc, Carry; 657 u32 Crc, Carry;
661 u32 i, j; 658 u32 i, j;
diff --git a/drivers/staging/winbond/linux/wb35reg_f.h b/drivers/staging/winbond/linux/wb35reg_f.h
index 38e2906b51a7..3006cfe99ccd 100644
--- a/drivers/staging/winbond/linux/wb35reg_f.h
+++ b/drivers/staging/winbond/linux/wb35reg_f.h
@@ -29,16 +29,16 @@ void EEPROMTxVgaAdjust( phw_data_t pHwData ); // 20060619.5 Add
29 29
30void Wb35Reg_destroy( phw_data_t pHwData ); 30void Wb35Reg_destroy( phw_data_t pHwData );
31 31
32unsigned char Wb35Reg_Read( phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterValue ); 32unsigned char Wb35Reg_Read( phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue );
33unsigned char Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterValue ); 33unsigned char Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue );
34unsigned char Wb35Reg_Write( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue ); 34unsigned char Wb35Reg_Write( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue );
35unsigned char Wb35Reg_WriteSync( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue ); 35unsigned char Wb35Reg_WriteSync( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue );
36unsigned char Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData, 36unsigned char Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData,
37 u16 RegisterNo, 37 u16 RegisterNo,
38 u32 RegisterValue, 38 u32 RegisterValue,
39 PCHAR pValue, 39 s8 *pValue,
40 s8 Len); 40 s8 Len);
41unsigned char Wb35Reg_BurstWrite( phw_data_t pHwData, u16 RegisterNo, PULONG pRegisterData, u8 NumberOfData, u8 Flag ); 41unsigned char Wb35Reg_BurstWrite( phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterData, u8 NumberOfData, u8 Flag );
42 42
43void Wb35Reg_EP0VM( phw_data_t pHwData ); 43void Wb35Reg_EP0VM( phw_data_t pHwData );
44void Wb35Reg_EP0VM_start( phw_data_t pHwData ); 44void Wb35Reg_EP0VM_start( phw_data_t pHwData );
@@ -47,7 +47,7 @@ void Wb35Reg_EP0VM_complete( PURB pUrb );
47u32 BitReverse( u32 dwData, u32 DataLength); 47u32 BitReverse( u32 dwData, u32 DataLength);
48 48
49void CardGetMulticastBit( u8 Address[MAC_ADDR_LENGTH], u8 *Byte, u8 *Value ); 49void CardGetMulticastBit( u8 Address[MAC_ADDR_LENGTH], u8 *Byte, u8 *Value );
50u32 CardComputeCrc( PUCHAR Buffer, u32 Length ); 50u32 CardComputeCrc( u8 * Buffer, u32 Length );
51 51
52void Wb35Reg_phy_calibration( phw_data_t pHwData ); 52void Wb35Reg_phy_calibration( phw_data_t pHwData );
53void Wb35Reg_Update( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue ); 53void Wb35Reg_Update( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue );
diff --git a/drivers/staging/winbond/linux/wb35reg_s.h b/drivers/staging/winbond/linux/wb35reg_s.h
index a7595b1e7336..8b35b93f7f02 100644
--- a/drivers/staging/winbond/linux/wb35reg_s.h
+++ b/drivers/staging/winbond/linux/wb35reg_s.h
@@ -75,7 +75,7 @@ typedef struct _REG_QUEUE
75 union 75 union
76 { 76 {
77 u32 VALUE; 77 u32 VALUE;
78 PULONG pBuffer; 78 u32 * pBuffer;
79 }; 79 };
80 u8 RESERVED[4];// space reserved for communication 80 u8 RESERVED[4];// space reserved for communication
81 81
@@ -143,7 +143,7 @@ typedef struct _WB35REG
143 //------------------- 143 //-------------------
144 // VM 144 // VM
145 //------------------- 145 //-------------------
146 OS_SPIN_LOCK EP0VM_spin_lock; // 4B 146 spinlock_t EP0VM_spin_lock; // 4B
147 u32 EP0VM_status;//$$ 147 u32 EP0VM_status;//$$
148 PREG_QUEUE pRegFirst; 148 PREG_QUEUE pRegFirst;
149 PREG_QUEUE pRegLast; 149 PREG_QUEUE pRegLast;
diff --git a/drivers/staging/winbond/linux/wb35rx.c b/drivers/staging/winbond/linux/wb35rx.c
index 26157eb3d5a2..b4b9f5f371d9 100644
--- a/drivers/staging/winbond/linux/wb35rx.c
+++ b/drivers/staging/winbond/linux/wb35rx.c
@@ -27,7 +27,7 @@ void Wb35Rx_start(phw_data_t pHwData)
27void Wb35Rx( phw_data_t pHwData ) 27void Wb35Rx( phw_data_t pHwData )
28{ 28{
29 PWB35RX pWb35Rx = &pHwData->Wb35Rx; 29 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
30 PUCHAR pRxBufferAddress; 30 u8 * pRxBufferAddress;
31 PURB pUrb = (PURB)pWb35Rx->RxUrb; 31 PURB pUrb = (PURB)pWb35Rx->RxUrb;
32 int retv; 32 int retv;
33 u32 RxBufferId; 33 u32 RxBufferId;
@@ -35,51 +35,50 @@ void Wb35Rx( phw_data_t pHwData )
35 // 35 //
36 // Issuing URB 36 // Issuing URB
37 // 37 //
38 do { 38 if (pHwData->SurpriseRemove || pHwData->HwStop)
39 if (pHwData->SurpriseRemove || pHwData->HwStop) 39 goto error;
40 break;
41 40
42 if (pWb35Rx->rx_halt) 41 if (pWb35Rx->rx_halt)
43 break; 42 goto error;
44 43
45 // Get RxBuffer's ID 44 // Get RxBuffer's ID
46 RxBufferId = pWb35Rx->RxBufferId; 45 RxBufferId = pWb35Rx->RxBufferId;
47 if (!pWb35Rx->RxOwner[RxBufferId]) { 46 if (!pWb35Rx->RxOwner[RxBufferId]) {
48 // It's impossible to run here. 47 // It's impossible to run here.
49 #ifdef _PE_RX_DUMP_ 48 #ifdef _PE_RX_DUMP_
50 WBDEBUG(("Rx driver fifo unavailable\n")); 49 WBDEBUG(("Rx driver fifo unavailable\n"));
51 #endif 50 #endif
52 break; 51 goto error;
53 } 52 }
54 53
55 // Update buffer point, then start to bulkin the data from USB 54 // Update buffer point, then start to bulkin the data from USB
56 pWb35Rx->RxBufferId++; 55 pWb35Rx->RxBufferId++;
57 pWb35Rx->RxBufferId %= MAX_USB_RX_BUFFER_NUMBER; 56 pWb35Rx->RxBufferId %= MAX_USB_RX_BUFFER_NUMBER;
58 57
59 pWb35Rx->CurrentRxBufferId = RxBufferId; 58 pWb35Rx->CurrentRxBufferId = RxBufferId;
60 59
61 if (1 != OS_MEMORY_ALLOC((void* *)&pWb35Rx->pDRx, MAX_USB_RX_BUFFER)) { 60 if (1 != OS_MEMORY_ALLOC((void* *)&pWb35Rx->pDRx, MAX_USB_RX_BUFFER)) {
62 printk("w35und: Rx memory alloc failed\n"); 61 printk("w35und: Rx memory alloc failed\n");
63 break; 62 goto error;
64 } 63 }
65 pRxBufferAddress = pWb35Rx->pDRx; 64 pRxBufferAddress = pWb35Rx->pDRx;
66 65
67 usb_fill_bulk_urb(pUrb, pHwData->WbUsb.udev, 66 usb_fill_bulk_urb(pUrb, pHwData->WbUsb.udev,
68 usb_rcvbulkpipe(pHwData->WbUsb.udev, 3), 67 usb_rcvbulkpipe(pHwData->WbUsb.udev, 3),
69 pRxBufferAddress, MAX_USB_RX_BUFFER, 68 pRxBufferAddress, MAX_USB_RX_BUFFER,
70 Wb35Rx_Complete, pHwData); 69 Wb35Rx_Complete, pHwData);
71 70
72 pWb35Rx->EP3vm_state = VM_RUNNING; 71 pWb35Rx->EP3vm_state = VM_RUNNING;
73 72
74 retv = wb_usb_submit_urb(pUrb); 73 retv = wb_usb_submit_urb(pUrb);
75 74
76 if (retv != 0) { 75 if (retv != 0) {
77 printk("Rx URB sending error\n"); 76 printk("Rx URB sending error\n");
78 break; 77 goto error;
79 } 78 }
80 return; 79 return;
81 } while(FALSE);
82 80
81error:
83 // VM stop 82 // VM stop
84 pWb35Rx->EP3vm_state = VM_STOP; 83 pWb35Rx->EP3vm_state = VM_STOP;
85 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Rx->RxFireCounter ); 84 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Rx->RxFireCounter );
@@ -89,7 +88,7 @@ void Wb35Rx_Complete(PURB pUrb)
89{ 88{
90 phw_data_t pHwData = pUrb->context; 89 phw_data_t pHwData = pUrb->context;
91 PWB35RX pWb35Rx = &pHwData->Wb35Rx; 90 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
92 PUCHAR pRxBufferAddress; 91 u8 * pRxBufferAddress;
93 u32 SizeCheck; 92 u32 SizeCheck;
94 u16 BulkLength; 93 u16 BulkLength;
95 u32 RxBufferId; 94 u32 RxBufferId;
@@ -99,65 +98,63 @@ void Wb35Rx_Complete(PURB pUrb)
99 pWb35Rx->EP3vm_state = VM_COMPLETED; 98 pWb35Rx->EP3vm_state = VM_COMPLETED;
100 pWb35Rx->EP3VM_status = pUrb->status;//Store the last result of Irp 99 pWb35Rx->EP3VM_status = pUrb->status;//Store the last result of Irp
101 100
102 do { 101 RxBufferId = pWb35Rx->CurrentRxBufferId;
103 RxBufferId = pWb35Rx->CurrentRxBufferId;
104 102
105 pRxBufferAddress = pWb35Rx->pDRx; 103 pRxBufferAddress = pWb35Rx->pDRx;
106 BulkLength = (u16)pUrb->actual_length; 104 BulkLength = (u16)pUrb->actual_length;
107 105
108 // The IRP is completed 106 // The IRP is completed
109 pWb35Rx->EP3vm_state = VM_COMPLETED; 107 pWb35Rx->EP3vm_state = VM_COMPLETED;
110 108
111 if (pHwData->SurpriseRemove || pHwData->HwStop) // Must be here, or RxBufferId is invalid 109 if (pHwData->SurpriseRemove || pHwData->HwStop) // Must be here, or RxBufferId is invalid
112 break; 110 goto error;
113 111
114 if (pWb35Rx->rx_halt) 112 if (pWb35Rx->rx_halt)
115 break; 113 goto error;
116 114
117 // Start to process the data only in successful condition 115 // Start to process the data only in successful condition
118 pWb35Rx->RxOwner[ RxBufferId ] = 0; // Set the owner to driver 116 pWb35Rx->RxOwner[ RxBufferId ] = 0; // Set the owner to driver
119 R00.value = le32_to_cpu(*(PULONG)pRxBufferAddress); 117 R00.value = le32_to_cpu(*(u32 *)pRxBufferAddress);
120 118
121 // The URB is completed, check the result 119 // The URB is completed, check the result
122 if (pWb35Rx->EP3VM_status != 0) { 120 if (pWb35Rx->EP3VM_status != 0) {
123 #ifdef _PE_USB_STATE_DUMP_ 121 #ifdef _PE_USB_STATE_DUMP_
124 WBDEBUG(("EP3 IoCompleteRoutine return error\n")); 122 WBDEBUG(("EP3 IoCompleteRoutine return error\n"));
125 DebugUsbdStatusInformation( pWb35Rx->EP3VM_status ); 123 DebugUsbdStatusInformation( pWb35Rx->EP3VM_status );
126 #endif 124 #endif
127 pWb35Rx->EP3vm_state = VM_STOP; 125 pWb35Rx->EP3vm_state = VM_STOP;
128 break; 126 goto error;
129 } 127 }
130 128
131 // 20060220 For recovering. check if operating in single USB mode 129 // 20060220 For recovering. check if operating in single USB mode
132 if (!HAL_USB_MODE_BURST(pHwData)) { 130 if (!HAL_USB_MODE_BURST(pHwData)) {
133 SizeCheck = R00.R00_receive_byte_count; //20060926 anson's endian 131 SizeCheck = R00.R00_receive_byte_count; //20060926 anson's endian
134 if ((SizeCheck & 0x03) > 0) 132 if ((SizeCheck & 0x03) > 0)
135 SizeCheck -= 4; 133 SizeCheck -= 4;
136 SizeCheck = (SizeCheck + 3) & ~0x03; 134 SizeCheck = (SizeCheck + 3) & ~0x03;
137 SizeCheck += 12; // 8 + 4 badbeef 135 SizeCheck += 12; // 8 + 4 badbeef
138 if ((BulkLength > 1600) || 136 if ((BulkLength > 1600) ||
139 (SizeCheck > 1600) || 137 (SizeCheck > 1600) ||
140 (BulkLength != SizeCheck) || 138 (BulkLength != SizeCheck) ||
141 (BulkLength == 0)) { // Add for fail Urb 139 (BulkLength == 0)) { // Add for fail Urb
142 pWb35Rx->EP3vm_state = VM_STOP; 140 pWb35Rx->EP3vm_state = VM_STOP;
143 pWb35Rx->Ep3ErrorCount2++; 141 pWb35Rx->Ep3ErrorCount2++;
144 }
145 } 142 }
143 }
146 144
147 // Indicating the receiving data 145 // Indicating the receiving data
148 pWb35Rx->ByteReceived += BulkLength; 146 pWb35Rx->ByteReceived += BulkLength;
149 pWb35Rx->RxBufferSize[ RxBufferId ] = BulkLength; 147 pWb35Rx->RxBufferSize[ RxBufferId ] = BulkLength;
150
151 if (!pWb35Rx->RxOwner[ RxBufferId ])
152 Wb35Rx_indicate(pHwData);
153 148
154 kfree(pWb35Rx->pDRx); 149 if (!pWb35Rx->RxOwner[ RxBufferId ])
155 // Do the next receive 150 Wb35Rx_indicate(pHwData);
156 Wb35Rx(pHwData);
157 return;
158 151
159 } while(FALSE); 152 kfree(pWb35Rx->pDRx);
153 // Do the next receive
154 Wb35Rx(pHwData);
155 return;
160 156
157error:
161 pWb35Rx->RxOwner[ RxBufferId ] = 1; // Set the owner to hardware 158 pWb35Rx->RxOwner[ RxBufferId ] = 1; // Set the owner to hardware
162 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Rx->RxFireCounter ); 159 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Rx->RxFireCounter );
163 pWb35Rx->EP3vm_state = VM_STOP; 160 pWb35Rx->EP3vm_state = VM_STOP;
@@ -223,7 +220,7 @@ void Wb35Rx_reset_descriptor( phw_data_t pHwData )
223 220
224void Wb35Rx_adjust(PDESCRIPTOR pRxDes) 221void Wb35Rx_adjust(PDESCRIPTOR pRxDes)
225{ 222{
226 PULONG pRxBufferAddress; 223 u32 * pRxBufferAddress;
227 u32 DecryptionMethod; 224 u32 DecryptionMethod;
228 u32 i; 225 u32 i;
229 u16 BufferSize; 226 u16 BufferSize;
@@ -264,7 +261,7 @@ u16 Wb35Rx_indicate(phw_data_t pHwData)
264{ 261{
265 DESCRIPTOR RxDes; 262 DESCRIPTOR RxDes;
266 PWB35RX pWb35Rx = &pHwData->Wb35Rx; 263 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
267 PUCHAR pRxBufferAddress; 264 u8 * pRxBufferAddress;
268 u16 PacketSize; 265 u16 PacketSize;
269 u16 stmp, BufferSize, stmp2 = 0; 266 u16 stmp, BufferSize, stmp2 = 0;
270 u32 RxBufferId; 267 u32 RxBufferId;
@@ -283,13 +280,13 @@ u16 Wb35Rx_indicate(phw_data_t pHwData)
283 280
284 // Parse the bulkin buffer 281 // Parse the bulkin buffer
285 while (BufferSize >= 4) { 282 while (BufferSize >= 4) {
286 if ((cpu_to_le32(*(PULONG)pRxBufferAddress) & 0x0fffffff) == RX_END_TAG) //Is ending? 921002.9.a 283 if ((cpu_to_le32(*(u32 *)pRxBufferAddress) & 0x0fffffff) == RX_END_TAG) //Is ending? 921002.9.a
287 break; 284 break;
288 285
289 // Get the R00 R01 first 286 // Get the R00 R01 first
290 RxDes.R00.value = le32_to_cpu(*(PULONG)pRxBufferAddress); 287 RxDes.R00.value = le32_to_cpu(*(u32 *)pRxBufferAddress);
291 PacketSize = (u16)RxDes.R00.R00_receive_byte_count; 288 PacketSize = (u16)RxDes.R00.R00_receive_byte_count;
292 RxDes.R01.value = le32_to_cpu(*((PULONG)(pRxBufferAddress+4))); 289 RxDes.R01.value = le32_to_cpu(*((u32 *)(pRxBufferAddress+4)));
293 // For new DMA 4k 290 // For new DMA 4k
294 if ((PacketSize & 0x03) > 0) 291 if ((PacketSize & 0x03) > 0)
295 PacketSize -= 4; 292 PacketSize -= 4;
diff --git a/drivers/staging/winbond/linux/wb35rx_s.h b/drivers/staging/winbond/linux/wb35rx_s.h
index 53b831fdeb78..b90c269e6adb 100644
--- a/drivers/staging/winbond/linux/wb35rx_s.h
+++ b/drivers/staging/winbond/linux/wb35rx_s.h
@@ -41,7 +41,7 @@ typedef struct _WB35RX
41 u32 Ep3ErrorCount2; // 20060625.1 Usbd for Rx DMA error count 41 u32 Ep3ErrorCount2; // 20060625.1 Usbd for Rx DMA error count
42 42
43 int EP3VM_status; 43 int EP3VM_status;
44 PUCHAR pDRx; 44 u8 * pDRx;
45 45
46} WB35RX, *PWB35RX; 46} WB35RX, *PWB35RX;
47 47
diff --git a/drivers/staging/winbond/linux/wb35tx.c b/drivers/staging/winbond/linux/wb35tx.c
index cf19c3bc524a..ba9d51244e29 100644
--- a/drivers/staging/winbond/linux/wb35tx.c
+++ b/drivers/staging/winbond/linux/wb35tx.c
@@ -12,7 +12,7 @@
12 12
13 13
14unsigned char 14unsigned char
15Wb35Tx_get_tx_buffer(phw_data_t pHwData, PUCHAR *pBuffer ) 15Wb35Tx_get_tx_buffer(phw_data_t pHwData, u8 **pBuffer)
16{ 16{
17 PWB35TX pWb35Tx = &pHwData->Wb35Tx; 17 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
18 18
@@ -37,7 +37,7 @@ void Wb35Tx(phw_data_t pHwData)
37{ 37{
38 PWB35TX pWb35Tx = &pHwData->Wb35Tx; 38 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
39 PADAPTER Adapter = pHwData->Adapter; 39 PADAPTER Adapter = pHwData->Adapter;
40 PUCHAR pTxBufferAddress; 40 u8 *pTxBufferAddress;
41 PMDS pMds = &Adapter->Mds; 41 PMDS pMds = &Adapter->Mds;
42 struct urb * pUrb = (struct urb *)pWb35Tx->Tx4Urb; 42 struct urb * pUrb = (struct urb *)pWb35Tx->Tx4Urb;
43 int retv; 43 int retv;
@@ -100,25 +100,24 @@ void Wb35Tx_complete(struct urb * pUrb)
100 pWb35Tx->TxSendIndex++; 100 pWb35Tx->TxSendIndex++;
101 pWb35Tx->TxSendIndex %= MAX_USB_TX_BUFFER_NUMBER; 101 pWb35Tx->TxSendIndex %= MAX_USB_TX_BUFFER_NUMBER;
102 102
103 do { 103 if (pHwData->SurpriseRemove || pHwData->HwStop) // Let WbWlanHalt to handle surprise remove
104 if (pHwData->SurpriseRemove || pHwData->HwStop) // Let WbWlanHalt to handle surprise remove 104 goto error;
105 break;
106 105
107 if (pWb35Tx->tx_halt) 106 if (pWb35Tx->tx_halt)
108 break; 107 goto error;
109 108
110 // The URB is completed, check the result 109 // The URB is completed, check the result
111 if (pWb35Tx->EP4VM_status != 0) { 110 if (pWb35Tx->EP4VM_status != 0) {
112 printk("URB submission failed\n"); 111 printk("URB submission failed\n");
113 pWb35Tx->EP4vm_state = VM_STOP; 112 pWb35Tx->EP4vm_state = VM_STOP;
114 break; // Exit while(FALSE); 113 goto error;
115 } 114 }
116 115
117 Mds_Tx(Adapter); 116 Mds_Tx(Adapter);
118 Wb35Tx(pHwData); 117 Wb35Tx(pHwData);
119 return; 118 return;
120 } while(FALSE);
121 119
120error:
122 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxFireCounter ); 121 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxFireCounter );
123 pWb35Tx->EP4vm_state = VM_STOP; 122 pWb35Tx->EP4vm_state = VM_STOP;
124} 123}
@@ -225,36 +224,33 @@ void Wb35Tx_EP2VM(phw_data_t pHwData)
225{ 224{
226 PWB35TX pWb35Tx = &pHwData->Wb35Tx; 225 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
227 struct urb * pUrb = (struct urb *)pWb35Tx->Tx2Urb; 226 struct urb * pUrb = (struct urb *)pWb35Tx->Tx2Urb;
228 PULONG pltmp = (PULONG)pWb35Tx->EP2_buf; 227 u32 * pltmp = (u32 *)pWb35Tx->EP2_buf;
229 int retv; 228 int retv;
230 229
231 do { 230 if (pHwData->SurpriseRemove || pHwData->HwStop)
232 if (pHwData->SurpriseRemove || pHwData->HwStop) 231 goto error;
233 break;
234
235 if (pWb35Tx->tx_halt)
236 break;
237
238 //
239 // Issuing URB
240 //
241 usb_fill_int_urb( pUrb, pHwData->WbUsb.udev, usb_rcvintpipe(pHwData->WbUsb.udev,2),
242 pltmp, MAX_INTERRUPT_LENGTH, Wb35Tx_EP2VM_complete, pHwData, 32);
243 232
244 pWb35Tx->EP2vm_state = VM_RUNNING; 233 if (pWb35Tx->tx_halt)
245 retv = wb_usb_submit_urb( pUrb ); 234 goto error;
246 235
247 if(retv < 0) { 236 //
248 #ifdef _PE_TX_DUMP_ 237 // Issuing URB
249 WBDEBUG(("EP2 Tx Irp sending error\n")); 238 //
250 #endif 239 usb_fill_int_urb( pUrb, pHwData->WbUsb.udev, usb_rcvintpipe(pHwData->WbUsb.udev,2),
251 break; 240 pltmp, MAX_INTERRUPT_LENGTH, Wb35Tx_EP2VM_complete, pHwData, 32);
252 }
253 241
254 return; 242 pWb35Tx->EP2vm_state = VM_RUNNING;
243 retv = wb_usb_submit_urb( pUrb );
255 244
256 } while(FALSE); 245 if (retv < 0) {
246 #ifdef _PE_TX_DUMP_
247 WBDEBUG(("EP2 Tx Irp sending error\n"));
248 #endif
249 goto error;
250 }
257 251
252 return;
253error:
258 pWb35Tx->EP2vm_state = VM_STOP; 254 pWb35Tx->EP2vm_state = VM_STOP;
259 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxResultCount ); 255 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxResultCount );
260} 256}
@@ -266,7 +262,7 @@ void Wb35Tx_EP2VM_complete(struct urb * pUrb)
266 T02_DESCRIPTOR T02, TSTATUS; 262 T02_DESCRIPTOR T02, TSTATUS;
267 PADAPTER Adapter = (PADAPTER)pHwData->Adapter; 263 PADAPTER Adapter = (PADAPTER)pHwData->Adapter;
268 PWB35TX pWb35Tx = &pHwData->Wb35Tx; 264 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
269 PULONG pltmp = (PULONG)pWb35Tx->EP2_buf; 265 u32 * pltmp = (u32 *)pWb35Tx->EP2_buf;
270 u32 i; 266 u32 i;
271 u16 InterruptInLength; 267 u16 InterruptInLength;
272 268
@@ -275,38 +271,36 @@ void Wb35Tx_EP2VM_complete(struct urb * pUrb)
275 pWb35Tx->EP2vm_state = VM_COMPLETED; 271 pWb35Tx->EP2vm_state = VM_COMPLETED;
276 pWb35Tx->EP2VM_status = pUrb->status; 272 pWb35Tx->EP2VM_status = pUrb->status;
277 273
278 do { 274 // For Linux 2.4. Interrupt will always trigger
279 // For Linux 2.4. Interrupt will always trigger 275 if (pHwData->SurpriseRemove || pHwData->HwStop) // Let WbWlanHalt to handle surprise remove
280 if( pHwData->SurpriseRemove || pHwData->HwStop ) // Let WbWlanHalt to handle surprise remove 276 goto error;
281 break; 277
282 278 if (pWb35Tx->tx_halt)
283 if( pWb35Tx->tx_halt ) 279 goto error;
284 break; 280
285 281 //The Urb is completed, check the result
286 //The Urb is completed, check the result 282 if (pWb35Tx->EP2VM_status != 0) {
287 if (pWb35Tx->EP2VM_status != 0) { 283 WBDEBUG(("EP2 IoCompleteRoutine return error\n"));
288 WBDEBUG(("EP2 IoCompleteRoutine return error\n")); 284 pWb35Tx->EP2vm_state= VM_STOP;
289 pWb35Tx->EP2vm_state= VM_STOP; 285 goto error;
290 break; // Exit while(FALSE); 286 }
291 }
292
293 // Update the Tx result
294 InterruptInLength = pUrb->actual_length;
295 // Modify for minimum memory access and DWORD alignment.
296 T02.value = cpu_to_le32(pltmp[0]) >> 8; // [31:8] -> [24:0]
297 InterruptInLength -= 1;// 20051221.1.c Modify the follow for more stable
298 InterruptInLength >>= 2; // InterruptInLength/4
299 for (i=1; i<=InterruptInLength; i++) {
300 T02.value |= ((cpu_to_le32(pltmp[i]) & 0xff) << 24);
301
302 TSTATUS.value = T02.value; //20061009 anson's endian
303 Mds_SendComplete( Adapter, &TSTATUS );
304 T02.value = cpu_to_le32(pltmp[i]) >> 8;
305 }
306
307 return;
308 } while(FALSE);
309 287
288 // Update the Tx result
289 InterruptInLength = pUrb->actual_length;
290 // Modify for minimum memory access and DWORD alignment.
291 T02.value = cpu_to_le32(pltmp[0]) >> 8; // [31:8] -> [24:0]
292 InterruptInLength -= 1;// 20051221.1.c Modify the follow for more stable
293 InterruptInLength >>= 2; // InterruptInLength/4
294 for (i = 1; i <= InterruptInLength; i++) {
295 T02.value |= ((cpu_to_le32(pltmp[i]) & 0xff) << 24);
296
297 TSTATUS.value = T02.value; //20061009 anson's endian
298 Mds_SendComplete( Adapter, &TSTATUS );
299 T02.value = cpu_to_le32(pltmp[i]) >> 8;
300 }
301
302 return;
303error:
310 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxResultCount ); 304 OS_ATOMIC_DEC( pHwData->Adapter, &pWb35Tx->TxResultCount );
311 pWb35Tx->EP2vm_state = VM_STOP; 305 pWb35Tx->EP2vm_state = VM_STOP;
312} 306}
diff --git a/drivers/staging/winbond/linux/wb35tx_f.h b/drivers/staging/winbond/linux/wb35tx_f.h
index 7705a8454dcb..107b12918137 100644
--- a/drivers/staging/winbond/linux/wb35tx_f.h
+++ b/drivers/staging/winbond/linux/wb35tx_f.h
@@ -3,7 +3,7 @@
3//==================================== 3//====================================
4unsigned char Wb35Tx_initial( phw_data_t pHwData ); 4unsigned char Wb35Tx_initial( phw_data_t pHwData );
5void Wb35Tx_destroy( phw_data_t pHwData ); 5void Wb35Tx_destroy( phw_data_t pHwData );
6unsigned char Wb35Tx_get_tx_buffer( phw_data_t pHwData, PUCHAR *pBuffer ); 6unsigned char Wb35Tx_get_tx_buffer( phw_data_t pHwData, u8 **pBuffer );
7 7
8void Wb35Tx_EP2VM( phw_data_t pHwData ); 8void Wb35Tx_EP2VM( phw_data_t pHwData );
9void Wb35Tx_EP2VM_start( phw_data_t pHwData ); 9void Wb35Tx_EP2VM_start( phw_data_t pHwData );
diff --git a/drivers/staging/winbond/linux/wbusb.c b/drivers/staging/winbond/linux/wbusb.c
index cbad5fb05959..f4a7875f2389 100644
--- a/drivers/staging/winbond/linux/wbusb.c
+++ b/drivers/staging/winbond/linux/wbusb.c
@@ -6,42 +6,29 @@
6#include "sysdef.h" 6#include "sysdef.h"
7#include <net/mac80211.h> 7#include <net/mac80211.h>
8 8
9 9MODULE_AUTHOR(DRIVER_AUTHOR);
10MODULE_AUTHOR( DRIVER_AUTHOR ); 10MODULE_DESCRIPTION(DRIVER_DESC);
11MODULE_DESCRIPTION( DRIVER_DESC );
12MODULE_LICENSE("GPL"); 11MODULE_LICENSE("GPL");
13MODULE_VERSION("0.1"); 12MODULE_VERSION("0.1");
14 13
15 14static struct usb_device_id wb35_table[] __devinitdata = {
16//============================================================ 15 {USB_DEVICE(0x0416, 0x0035)},
17// vendor ID and product ID can into here for others 16 {USB_DEVICE(0x18E8, 0x6201)},
18//============================================================ 17 {USB_DEVICE(0x18E8, 0x6206)},
19static struct usb_device_id Id_Table[] = 18 {USB_DEVICE(0x18E8, 0x6217)},
20{ 19 {USB_DEVICE(0x18E8, 0x6230)},
21 {USB_DEVICE( 0x0416, 0x0035 )}, 20 {USB_DEVICE(0x18E8, 0x6233)},
22 {USB_DEVICE( 0x18E8, 0x6201 )}, 21 {USB_DEVICE(0x1131, 0x2035)},
23 {USB_DEVICE( 0x18E8, 0x6206 )}, 22 { 0, }
24 {USB_DEVICE( 0x18E8, 0x6217 )},
25 {USB_DEVICE( 0x18E8, 0x6230 )},
26 {USB_DEVICE( 0x18E8, 0x6233 )},
27 {USB_DEVICE( 0x1131, 0x2035 )},
28 { }
29}; 23};
30 24
31MODULE_DEVICE_TABLE(usb, Id_Table); 25MODULE_DEVICE_TABLE(usb, wb35_table);
32 26
33static struct usb_driver wb35_driver = { 27static struct ieee80211_rate wbsoft_rates[] = {
34 .name = "w35und",
35 .probe = wb35_probe,
36 .disconnect = wb35_disconnect,
37 .id_table = Id_Table,
38};
39
40static const struct ieee80211_rate wbsoft_rates[] = {
41 { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 28 { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
42}; 29};
43 30
44static const struct ieee80211_channel wbsoft_channels[] = { 31static struct ieee80211_channel wbsoft_channels[] = {
45 { .center_freq = 2412}, 32 { .center_freq = 2412},
46}; 33};
47 34
@@ -62,9 +49,22 @@ static void wbsoft_remove_interface(struct ieee80211_hw *dev,
62 printk("wbsoft_remove interface called\n"); 49 printk("wbsoft_remove interface called\n");
63} 50}
64 51
65static int wbsoft_nop(void) 52static void wbsoft_stop(struct ieee80211_hw *hw)
53{
54 printk(KERN_INFO "%s called\n", __func__);
55}
56
57static int wbsoft_get_stats(struct ieee80211_hw *hw,
58 struct ieee80211_low_level_stats *stats)
66{ 59{
67 printk("wbsoft_nop called\n"); 60 printk(KERN_INFO "%s called\n", __func__);
61 return 0;
62}
63
64static int wbsoft_get_tx_stats(struct ieee80211_hw *hw,
65 struct ieee80211_tx_queue_stats *stats)
66{
67 printk(KERN_INFO "%s called\n", __func__);
68 return 0; 68 return 0;
69} 69}
70 70
@@ -105,8 +105,7 @@ static void wbsoft_configure_filter(struct ieee80211_hw *dev,
105 *total_flags = new_flags; 105 *total_flags = new_flags;
106} 106}
107 107
108static int wbsoft_tx(struct ieee80211_hw *dev, struct sk_buff *skb, 108static int wbsoft_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
109 struct ieee80211_tx_control *control)
110{ 109{
111 char *buffer = kmalloc(skb->len, GFP_ATOMIC); 110 char *buffer = kmalloc(skb->len, GFP_ATOMIC);
112 printk("Sending frame %d bytes\n", skb->len); 111 printk("Sending frame %d bytes\n", skb->len);
@@ -136,7 +135,7 @@ static int wbsoft_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
136 hal_set_current_channel(&my_adapter->sHwData, ch); 135 hal_set_current_channel(&my_adapter->sHwData, ch);
137 hal_set_beacon_period(&my_adapter->sHwData, conf->beacon_int); 136 hal_set_beacon_period(&my_adapter->sHwData, conf->beacon_int);
138// hal_set_cap_info(&my_adapter->sHwData, ?? ); 137// hal_set_cap_info(&my_adapter->sHwData, ?? );
139// hal_set_ssid(phw_data_t pHwData, PUCHAR pssid, u8 ssid_len); ?? 138// hal_set_ssid(phw_data_t pHwData, u8 * pssid, u8 ssid_len); ??
140 hal_set_accept_broadcast(&my_adapter->sHwData, 1); 139 hal_set_accept_broadcast(&my_adapter->sHwData, 1);
141 hal_set_accept_promiscuous(&my_adapter->sHwData, 1); 140 hal_set_accept_promiscuous(&my_adapter->sHwData, 1);
142 hal_set_accept_multicast(&my_adapter->sHwData, 1); 141 hal_set_accept_multicast(&my_adapter->sHwData, 1);
@@ -148,7 +147,7 @@ static int wbsoft_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
148 147
149// hal_start_bss(&my_adapter->sHwData, WLAN_BSSTYPE_INFRASTRUCTURE); ?? 148// hal_start_bss(&my_adapter->sHwData, WLAN_BSSTYPE_INFRASTRUCTURE); ??
150 149
151//void hal_set_rates(phw_data_t pHwData, PUCHAR pbss_rates, 150//void hal_set_rates(phw_data_t pHwData, u8 * pbss_rates,
152// u8 length, unsigned char basic_rate_set) 151// u8 length, unsigned char basic_rate_set)
153 152
154 return 0; 153 return 0;
@@ -171,14 +170,14 @@ static u64 wbsoft_get_tsf(struct ieee80211_hw *dev)
171static const struct ieee80211_ops wbsoft_ops = { 170static const struct ieee80211_ops wbsoft_ops = {
172 .tx = wbsoft_tx, 171 .tx = wbsoft_tx,
173 .start = wbsoft_start, /* Start can be pretty much empty as we do WbWLanInitialize() during probe? */ 172 .start = wbsoft_start, /* Start can be pretty much empty as we do WbWLanInitialize() during probe? */
174 .stop = wbsoft_nop, 173 .stop = wbsoft_stop,
175 .add_interface = wbsoft_add_interface, 174 .add_interface = wbsoft_add_interface,
176 .remove_interface = wbsoft_remove_interface, 175 .remove_interface = wbsoft_remove_interface,
177 .config = wbsoft_config, 176 .config = wbsoft_config,
178 .config_interface = wbsoft_config_interface, 177 .config_interface = wbsoft_config_interface,
179 .configure_filter = wbsoft_configure_filter, 178 .configure_filter = wbsoft_configure_filter,
180 .get_stats = wbsoft_nop, 179 .get_stats = wbsoft_get_stats,
181 .get_tx_stats = wbsoft_nop, 180 .get_tx_stats = wbsoft_get_tx_stats,
182 .get_tsf = wbsoft_get_tsf, 181 .get_tsf = wbsoft_get_tsf,
183// conf_tx: hal_set_cwmin()/hal_set_cwmax; 182// conf_tx: hal_set_cwmin()/hal_set_cwmax;
184}; 183};
@@ -187,21 +186,6 @@ struct wbsoft_priv {
187}; 186};
188 187
189 188
190int __init wb35_init(void)
191{
192 printk("[w35und]driver init\n");
193 return usb_register(&wb35_driver);
194}
195
196void __exit wb35_exit(void)
197{
198 printk("[w35und]driver exit\n");
199 usb_deregister( &wb35_driver );
200}
201
202module_init(wb35_init);
203module_exit(wb35_exit);
204
205// Usb kernel subsystem will call this function when a new device is plugged into. 189// Usb kernel subsystem will call this function when a new device is plugged into.
206int wb35_probe(struct usb_interface *intf, const struct usb_device_id *id_table) 190int wb35_probe(struct usb_interface *intf, const struct usb_device_id *id_table)
207{ 191{
@@ -210,7 +194,7 @@ int wb35_probe(struct usb_interface *intf, const struct usb_device_id *id_table)
210 PWBUSB pWbUsb; 194 PWBUSB pWbUsb;
211 struct usb_host_interface *interface; 195 struct usb_host_interface *interface;
212 struct usb_endpoint_descriptor *endpoint; 196 struct usb_endpoint_descriptor *endpoint;
213 int i, ret = -1; 197 int ret = -1;
214 u32 ltmp; 198 u32 ltmp;
215 struct usb_device *udev = interface_to_usbdev(intf); 199 struct usb_device *udev = interface_to_usbdev(intf);
216 200
@@ -218,114 +202,95 @@ int wb35_probe(struct usb_interface *intf, const struct usb_device_id *id_table)
218 202
219 printk("[w35und]wb35_probe ->\n"); 203 printk("[w35und]wb35_probe ->\n");
220 204
221 do { 205 // 20060630.2 Check the device if it already be opened
222 for (i=0; i<(sizeof(Id_Table)/sizeof(struct usb_device_id)); i++ ) { 206 ret = usb_control_msg(udev, usb_rcvctrlpipe( udev, 0 ),
223 if ((udev->descriptor.idVendor == Id_Table[i].idVendor) && 207 0x01, USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN,
224 (udev->descriptor.idProduct == Id_Table[i].idProduct)) { 208 0x0, 0x400, &ltmp, 4, HZ*100 );
225 printk("[w35und]Found supported hardware\n"); 209 if (ret < 0)
226 break; 210 goto error;
227 }
228 }
229 if ((i == (sizeof(Id_Table)/sizeof(struct usb_device_id)))) {
230 #ifdef _PE_USB_INI_DUMP_
231 WBDEBUG(("[w35und] This is not the one we are interested about\n"));
232 #endif
233 return -ENODEV;
234 }
235
236 // 20060630.2 Check the device if it already be opened
237 ret = usb_control_msg(udev, usb_rcvctrlpipe( udev, 0 ),
238 0x01, USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN,
239 0x0, 0x400, &ltmp, 4, HZ*100 );
240 if( ret < 0 )
241 break;
242 211
243 ltmp = cpu_to_le32(ltmp); 212 ltmp = cpu_to_le32(ltmp);
244 if (ltmp) // Is already initialized? 213 if (ltmp) // Is already initialized?
245 break; 214 goto error;
246 215
216 Adapter = kzalloc(sizeof(ADAPTER), GFP_KERNEL);
247 217
248 Adapter = kzalloc(sizeof(ADAPTER), GFP_KERNEL); 218 my_adapter = Adapter;
219 pWbLinux = &Adapter->WbLinux;
220 pWbUsb = &Adapter->sHwData.WbUsb;
221 pWbUsb->udev = udev;
249 222
250 my_adapter = Adapter; 223 interface = intf->cur_altsetting;
251 pWbLinux = &Adapter->WbLinux; 224 endpoint = &interface->endpoint[0].desc;
252 pWbUsb = &Adapter->sHwData.WbUsb;
253 pWbUsb->udev = udev;
254 225
255 interface = intf->cur_altsetting; 226 if (endpoint[2].wMaxPacketSize == 512) {
256 endpoint = &interface->endpoint[0].desc; 227 printk("[w35und] Working on USB 2.0\n");
257 228 pWbUsb->IsUsb20 = 1;
258 if (endpoint[2].wMaxPacketSize == 512) { 229 }
259 printk("[w35und] Working on USB 2.0\n");
260 pWbUsb->IsUsb20 = 1;
261 }
262
263 if (!WbWLanInitialize(Adapter)) {
264 printk("[w35und]WbWLanInitialize fail\n");
265 break;
266 }
267 230
268 { 231 if (!WbWLanInitialize(Adapter)) {
269 struct wbsoft_priv *priv; 232 printk("[w35und]WbWLanInitialize fail\n");
270 struct ieee80211_hw *dev; 233 goto error;
271 int res; 234 }
272 235
273 dev = ieee80211_alloc_hw(sizeof(*priv), &wbsoft_ops); 236 {
237 struct wbsoft_priv *priv;
238 struct ieee80211_hw *dev;
239 static struct ieee80211_supported_band band;
240 int res;
274 241
275 if (!dev) { 242 dev = ieee80211_alloc_hw(sizeof(*priv), &wbsoft_ops);
276 printk("w35und: ieee80211 alloc failed\n" );
277 BUG();
278 }
279 243
280 my_dev = dev; 244 if (!dev) {
245 printk("w35und: ieee80211 alloc failed\n" );
246 BUG();
247 }
281 248
282 SET_IEEE80211_DEV(dev, &udev->dev); 249 my_dev = dev;
283 {
284 phw_data_t pHwData = &Adapter->sHwData;
285 unsigned char dev_addr[MAX_ADDR_LEN];
286 hal_get_permanent_address(pHwData, dev_addr);
287 SET_IEEE80211_PERM_ADDR(dev, dev_addr);
288 }
289 250
251 SET_IEEE80211_DEV(dev, &udev->dev);
252 {
253 phw_data_t pHwData = &Adapter->sHwData;
254 unsigned char dev_addr[MAX_ADDR_LEN];
255 hal_get_permanent_address(pHwData, dev_addr);
256 SET_IEEE80211_PERM_ADDR(dev, dev_addr);
257 }
290 258
291 dev->extra_tx_headroom = 12; /* FIXME */
292 dev->flags = 0;
293 259
294 dev->channel_change_time = 1000; 260 dev->extra_tx_headroom = 12; /* FIXME */
295// dev->max_rssi = 100; 261 dev->flags = 0;
296 262
297 dev->queues = 1; 263 dev->channel_change_time = 1000;
264// dev->max_rssi = 100;
298 265
299 static struct ieee80211_supported_band band; 266 dev->queues = 1;
300 267
301 band.channels = wbsoft_channels; 268 band.channels = wbsoft_channels;
302 band.n_channels = ARRAY_SIZE(wbsoft_channels); 269 band.n_channels = ARRAY_SIZE(wbsoft_channels);
303 band.bitrates = wbsoft_rates; 270 band.bitrates = wbsoft_rates;
304 band.n_bitrates = ARRAY_SIZE(wbsoft_rates); 271 band.n_bitrates = ARRAY_SIZE(wbsoft_rates);
305 272
306 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band; 273 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band;
307#if 0 274#if 0
308 wbsoft_modes[0].num_channels = 1; 275 wbsoft_modes[0].num_channels = 1;
309 wbsoft_modes[0].channels = wbsoft_channels; 276 wbsoft_modes[0].channels = wbsoft_channels;
310 wbsoft_modes[0].mode = MODE_IEEE80211B; 277 wbsoft_modes[0].mode = MODE_IEEE80211B;
311 wbsoft_modes[0].num_rates = ARRAY_SIZE(wbsoft_rates); 278 wbsoft_modes[0].num_rates = ARRAY_SIZE(wbsoft_rates);
312 wbsoft_modes[0].rates = wbsoft_rates; 279 wbsoft_modes[0].rates = wbsoft_rates;
313 280
314 res = ieee80211_register_hwmode(dev, &wbsoft_modes[0]); 281 res = ieee80211_register_hwmode(dev, &wbsoft_modes[0]);
315 BUG_ON(res); 282 BUG_ON(res);
316#endif 283#endif
317 284
318 res = ieee80211_register_hw(dev); 285 res = ieee80211_register_hw(dev);
319 BUG_ON(res); 286 BUG_ON(res);
320 } 287 }
321
322 usb_set_intfdata( intf, Adapter );
323
324 printk("[w35und] _probe OK\n");
325 return 0;
326 288
327 } while(FALSE); 289 usb_set_intfdata( intf, Adapter );
328 290
291 printk("[w35und] _probe OK\n");
292 return 0;
293error:
329 return -ENOMEM; 294 return -ENOMEM;
330} 295}
331 296
@@ -401,4 +366,22 @@ void wb35_disconnect(struct usb_interface *intf)
401 366
402} 367}
403 368
369static struct usb_driver wb35_driver = {
370 .name = "w35und",
371 .id_table = wb35_table,
372 .probe = wb35_probe,
373 .disconnect = wb35_disconnect,
374};
404 375
376static int __init wb35_init(void)
377{
378 return usb_register(&wb35_driver);
379}
380
381static void __exit wb35_exit(void)
382{
383 usb_deregister(&wb35_driver);
384}
385
386module_init(wb35_init);
387module_exit(wb35_exit);
diff --git a/drivers/staging/winbond/mds.c b/drivers/staging/winbond/mds.c
index 8ce6389c4135..f1de813f9c76 100644
--- a/drivers/staging/winbond/mds.c
+++ b/drivers/staging/winbond/mds.c
@@ -40,7 +40,7 @@ Mds_Tx(PADAPTER Adapter)
40 PMDS pMds = &Adapter->Mds; 40 PMDS pMds = &Adapter->Mds;
41 DESCRIPTOR TxDes; 41 DESCRIPTOR TxDes;
42 PDESCRIPTOR pTxDes = &TxDes; 42 PDESCRIPTOR pTxDes = &TxDes;
43 PUCHAR XmitBufAddress; 43 u8 *XmitBufAddress;
44 u16 XmitBufSize, PacketSize, stmp, CurrentSize, FragmentThreshold; 44 u16 XmitBufSize, PacketSize, stmp, CurrentSize, FragmentThreshold;
45 u8 FillIndex, TxDesIndex, FragmentCount, FillCount; 45 u8 FillIndex, TxDesIndex, FragmentCount, FillCount;
46 unsigned char BufferFilled = FALSE, MICAdd = 0; 46 unsigned char BufferFilled = FALSE, MICAdd = 0;
@@ -90,7 +90,7 @@ Mds_Tx(PADAPTER Adapter)
90 BufferFilled = TRUE; 90 BufferFilled = TRUE;
91 91
92 /* Leaves first u8 intact */ 92 /* Leaves first u8 intact */
93 memset((PUCHAR)pTxDes + 1, 0, sizeof(DESCRIPTOR) - 1); 93 memset((u8 *)pTxDes + 1, 0, sizeof(DESCRIPTOR) - 1);
94 94
95 TxDesIndex = pMds->TxDesIndex;//Get the current ID 95 TxDesIndex = pMds->TxDesIndex;//Get the current ID
96 pTxDes->Descriptor_ID = TxDesIndex; 96 pTxDes->Descriptor_ID = TxDesIndex;
@@ -229,10 +229,10 @@ Mds_SendComplete(PADAPTER Adapter, PT02_DESCRIPTOR pT02)
229} 229}
230 230
231void 231void
232Mds_HeaderCopy(PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer) 232Mds_HeaderCopy(PADAPTER Adapter, PDESCRIPTOR pDes, u8 *TargetBuffer)
233{ 233{
234 PMDS pMds = &Adapter->Mds; 234 PMDS pMds = &Adapter->Mds;
235 PUCHAR src_buffer = pDes->buffer_address[0];//931130.5.g 235 u8 *src_buffer = pDes->buffer_address[0];//931130.5.g
236 PT00_DESCRIPTOR pT00; 236 PT00_DESCRIPTOR pT00;
237 PT01_DESCRIPTOR pT01; 237 PT01_DESCRIPTOR pT01;
238 u16 stmp; 238 u16 stmp;
@@ -276,7 +276,7 @@ Mds_HeaderCopy(PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer)
276 // 276 //
277 // Set tx rate 277 // Set tx rate
278 // 278 //
279 stmp = *(PUSHORT)(TargetBuffer+30); // 2n alignment address 279 stmp = *(u16 *)(TargetBuffer+30); // 2n alignment address
280 280
281 //Use basic rate 281 //Use basic rate
282 ctmp1 = ctmpf = CURRENT_TX_RATE_FOR_MNG; 282 ctmp1 = ctmpf = CURRENT_TX_RATE_FOR_MNG;
@@ -326,11 +326,13 @@ Mds_HeaderCopy(PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer)
326 326
327// The function return the 4n size of usb pk 327// The function return the 4n size of usb pk
328u16 328u16
329Mds_BodyCopy(PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer) 329Mds_BodyCopy(PADAPTER Adapter, PDESCRIPTOR pDes, u8 *TargetBuffer)
330{ 330{
331 PT00_DESCRIPTOR pT00; 331 PT00_DESCRIPTOR pT00;
332 PMDS pMds = &Adapter->Mds; 332 PMDS pMds = &Adapter->Mds;
333 PUCHAR buffer, src_buffer, pctmp; 333 u8 *buffer;
334 u8 *src_buffer;
335 u8 *pctmp;
334 u16 Size = 0; 336 u16 Size = 0;
335 u16 SizeLeft, CopySize, CopyLeft, stmp; 337 u16 SizeLeft, CopySize, CopyLeft, stmp;
336 u8 buf_index, FragmentCount = 0; 338 u8 buf_index, FragmentCount = 0;
@@ -354,7 +356,7 @@ Mds_BodyCopy(PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer)
354 SizeLeft -= CopySize; 356 SizeLeft -= CopySize;
355 357
356 // 1 Byte operation 358 // 1 Byte operation
357 pctmp = (PUCHAR)( buffer + 8 + DOT_11_SEQUENCE_OFFSET ); 359 pctmp = (u8 *)( buffer + 8 + DOT_11_SEQUENCE_OFFSET );
358 *pctmp &= 0xf0; 360 *pctmp &= 0xf0;
359 *pctmp |= FragmentCount;//931130.5.m 361 *pctmp |= FragmentCount;//931130.5.m
360 if( !FragmentCount ) 362 if( !FragmentCount )
@@ -379,7 +381,7 @@ Mds_BodyCopy(PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer)
379 buf_index++; 381 buf_index++;
380 buf_index %= MAX_DESCRIPTOR_BUFFER_INDEX; 382 buf_index %= MAX_DESCRIPTOR_BUFFER_INDEX;
381 } else { 383 } else {
382 PUCHAR pctmp = pDes->buffer_address[buf_index]; 384 u8 *pctmp = pDes->buffer_address[buf_index];
383 pctmp += CopySize; 385 pctmp += CopySize;
384 pDes->buffer_address[buf_index] = pctmp; 386 pDes->buffer_address[buf_index] = pctmp;
385 pDes->buffer_size[buf_index] -= CopySize; 387 pDes->buffer_size[buf_index] -= CopySize;
@@ -419,7 +421,7 @@ Mds_BodyCopy(PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer)
419 421
420 pT00->T00_last_mpdu = 1; 422 pT00->T00_last_mpdu = 1;
421 pT00->T00_IsLastMpdu = 1; 423 pT00->T00_IsLastMpdu = 1;
422 buffer = (PUCHAR)pT00 + 8; // +8 for USB hdr 424 buffer = (u8 *)pT00 + 8; // +8 for USB hdr
423 buffer[1] &= ~0x04; // Clear more frag bit of 802.11 frame control 425 buffer[1] &= ~0x04; // Clear more frag bit of 802.11 frame control
424 pDes->FragmentCount = FragmentCount; // Update the correct fragment number 426 pDes->FragmentCount = FragmentCount; // Update the correct fragment number
425 return Size; 427 return Size;
@@ -427,7 +429,7 @@ Mds_BodyCopy(PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer)
427 429
428 430
429void 431void
430Mds_DurationSet( PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR buffer ) 432Mds_DurationSet( PADAPTER Adapter, PDESCRIPTOR pDes, u8 *buffer )
431{ 433{
432 PT00_DESCRIPTOR pT00; 434 PT00_DESCRIPTOR pT00;
433 PT01_DESCRIPTOR pT01; 435 PT01_DESCRIPTOR pT01;
@@ -435,7 +437,7 @@ Mds_DurationSet( PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR buffer )
435 u8 Rate, i; 437 u8 Rate, i;
436 unsigned char CTS_on = FALSE, RTS_on = FALSE; 438 unsigned char CTS_on = FALSE, RTS_on = FALSE;
437 PT00_DESCRIPTOR pNextT00; 439 PT00_DESCRIPTOR pNextT00;
438 u16 BodyLen; 440 u16 BodyLen = 0;
439 unsigned char boGroupAddr = FALSE; 441 unsigned char boGroupAddr = FALSE;
440 442
441 443
@@ -574,7 +576,7 @@ Mds_DurationSet( PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR buffer )
574 DEFAULT_SIFSTIME*3 ); 576 DEFAULT_SIFSTIME*3 );
575 } 577 }
576 578
577 ((PUSHORT)buffer)[5] = cpu_to_le16(Duration);// 4 USHOR for skip 8B USB, 2USHORT=FC + Duration 579 ((u16 *)buffer)[5] = cpu_to_le16(Duration);// 4 USHOR for skip 8B USB, 2USHORT=FC + Duration
578 580
579 //----20061009 add by anson's endian 581 //----20061009 add by anson's endian
580 pNextT00->value = cpu_to_le32(pNextT00->value); 582 pNextT00->value = cpu_to_le32(pNextT00->value);
@@ -615,7 +617,7 @@ Mds_DurationSet( PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR buffer )
615 } 617 }
616 } 618 }
617 619
618 ((PUSHORT)buffer)[5] = cpu_to_le16(Duration);// 4 USHOR for skip 8B USB, 2USHORT=FC + Duration 620 ((u16 *)buffer)[5] = cpu_to_le16(Duration);// 4 USHOR for skip 8B USB, 2USHORT=FC + Duration
619 pT00->value = cpu_to_le32(pT00->value); 621 pT00->value = cpu_to_le32(pT00->value);
620 pT01->value = cpu_to_le32(pT01->value); 622 pT01->value = cpu_to_le32(pT01->value);
621 //--end 20061009 add 623 //--end 20061009 add
diff --git a/drivers/staging/winbond/mds_f.h b/drivers/staging/winbond/mds_f.h
index 651188be1065..7a682d4cfbdc 100644
--- a/drivers/staging/winbond/mds_f.h
+++ b/drivers/staging/winbond/mds_f.h
@@ -1,9 +1,9 @@
1unsigned char Mds_initial( PADAPTER Adapter ); 1unsigned char Mds_initial( PADAPTER Adapter );
2void Mds_Destroy( PADAPTER Adapter ); 2void Mds_Destroy( PADAPTER Adapter );
3void Mds_Tx( PADAPTER Adapter ); 3void Mds_Tx( PADAPTER Adapter );
4void Mds_HeaderCopy( PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer ); 4void Mds_HeaderCopy( PADAPTER Adapter, PDESCRIPTOR pDes, u8 *TargetBuffer );
5u16 Mds_BodyCopy( PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer ); 5u16 Mds_BodyCopy( PADAPTER Adapter, PDESCRIPTOR pDes, u8 *TargetBuffer );
6void Mds_DurationSet( PADAPTER Adapter, PDESCRIPTOR pDes, PUCHAR TargetBuffer ); 6void Mds_DurationSet( PADAPTER Adapter, PDESCRIPTOR pDes, u8 *TargetBuffer );
7void Mds_SendComplete( PADAPTER Adapter, PT02_DESCRIPTOR pT02 ); 7void Mds_SendComplete( PADAPTER Adapter, PT02_DESCRIPTOR pT02 );
8void Mds_MpduProcess( PADAPTER Adapter, PDESCRIPTOR pRxDes ); 8void Mds_MpduProcess( PADAPTER Adapter, PDESCRIPTOR pRxDes );
9void Mds_reset_descriptor( PADAPTER Adapter ); 9void Mds_reset_descriptor( PADAPTER Adapter );
diff --git a/drivers/staging/winbond/mds_s.h b/drivers/staging/winbond/mds_s.h
index 4738279d5f39..9df2e0936bf8 100644
--- a/drivers/staging/winbond/mds_s.h
+++ b/drivers/staging/winbond/mds_s.h
@@ -86,7 +86,7 @@ typedef struct _MDS
86{ 86{
87 // For Tx usage 87 // For Tx usage
88 u8 TxOwner[ ((MAX_USB_TX_BUFFER_NUMBER + 3) & ~0x03) ]; 88 u8 TxOwner[ ((MAX_USB_TX_BUFFER_NUMBER + 3) & ~0x03) ];
89 PUCHAR pTxBuffer; 89 u8 *pTxBuffer;
90 u16 TxBufferSize[ ((MAX_USB_TX_BUFFER_NUMBER + 1) & ~0x01) ]; 90 u16 TxBufferSize[ ((MAX_USB_TX_BUFFER_NUMBER + 1) & ~0x01) ];
91 u8 TxDesFrom[ ((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03) ];//931130.4.u // 1: MLME 2: NDIS control 3: NDIS data 91 u8 TxDesFrom[ ((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03) ];//931130.4.u // 1: MLME 2: NDIS control 3: NDIS data
92 u8 TxCountInBuffer[ ((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03) ]; // 20060928 92 u8 TxCountInBuffer[ ((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03) ]; // 20060928
@@ -103,7 +103,7 @@ typedef struct _MDS
103 u16 TxResult[ ((MAX_USB_TX_DESCRIPTOR + 1) & ~0x01) ];//Collect the sending result of Mpdu 103 u16 TxResult[ ((MAX_USB_TX_DESCRIPTOR + 1) & ~0x01) ];//Collect the sending result of Mpdu
104 104
105 u8 MicRedundant[8]; // For tmp use 105 u8 MicRedundant[8]; // For tmp use
106 PUCHAR MicWriteAddress[2]; //The start address to fill the Mic, use 2 point due to Mic maybe fragment 106 u8 *MicWriteAddress[2]; //The start address to fill the Mic, use 2 point due to Mic maybe fragment
107 107
108 u16 MicWriteSize[2]; //931130.4.x 108 u16 MicWriteSize[2]; //931130.4.x
109 109
@@ -144,7 +144,7 @@ typedef struct _MDS
144 144
145typedef struct _RxBuffer 145typedef struct _RxBuffer
146{ 146{
147 PUCHAR pBufferAddress; // Pointer the received data buffer. 147 u8 * pBufferAddress; // Pointer the received data buffer.
148 u16 BufferSize; 148 u16 BufferSize;
149 u8 RESERVED; 149 u8 RESERVED;
150 u8 BufferIndex;// Only 1 byte 150 u8 BufferIndex;// Only 1 byte
@@ -176,7 +176,7 @@ typedef struct _RXLAYER1
176 ///////////////////////////////////////////////////////////////////////////////////////////// 176 /////////////////////////////////////////////////////////////////////////////////////////////
177 // For brand-new Rx system 177 // For brand-new Rx system
178 u8 ReservedBuffer[ 2400 ];//If Buffer ID is reserved one, it must copy the data into this area 178 u8 ReservedBuffer[ 2400 ];//If Buffer ID is reserved one, it must copy the data into this area
179 PUCHAR ReservedBufferPoint;// Point to the next availabe address of reserved buffer 179 u8 *ReservedBufferPoint;// Point to the next availabe address of reserved buffer
180 180
181}RXLAYER1, * PRXLAYER1; 181}RXLAYER1, * PRXLAYER1;
182 182
diff --git a/drivers/staging/winbond/mlme_s.h b/drivers/staging/winbond/mlme_s.h
index 58094f61c032..039fd408ba62 100644
--- a/drivers/staging/winbond/mlme_s.h
+++ b/drivers/staging/winbond/mlme_s.h
@@ -125,12 +125,12 @@
125typedef struct _MLME_FRAME 125typedef struct _MLME_FRAME
126{ 126{
127 //NDIS_PACKET MLME_Packet; 127 //NDIS_PACKET MLME_Packet;
128 PCHAR pMMPDU; 128 s8 * pMMPDU;
129 u16 len; 129 u16 len;
130 u8 DataType; 130 u8 DataType;
131 u8 IsInUsed; 131 u8 IsInUsed;
132 132
133 OS_SPIN_LOCK MLMESpinLock; 133 spinlock_t MLMESpinLock;
134 134
135 u8 TxMMPDU[MAX_NUM_TX_MMPDU][MAX_MMPDU_SIZE]; 135 u8 TxMMPDU[MAX_NUM_TX_MMPDU][MAX_MMPDU_SIZE];
136 u8 TxMMPDUInUse[ (MAX_NUM_TX_MMPDU+3) & ~0x03 ]; 136 u8 TxMMPDUInUse[ (MAX_NUM_TX_MMPDU+3) & ~0x03 ];
diff --git a/drivers/staging/winbond/mlmetxrx.c b/drivers/staging/winbond/mlmetxrx.c
index 46b091e96794..e8533b8d1976 100644
--- a/drivers/staging/winbond/mlmetxrx.c
+++ b/drivers/staging/winbond/mlmetxrx.c
@@ -113,13 +113,13 @@ MLME_GetNextPacket(PADAPTER Adapter, PDESCRIPTOR pDes)
113 pDes->Type = Adapter->sMlmeFrame.DataType; 113 pDes->Type = Adapter->sMlmeFrame.DataType;
114} 114}
115 115
116void MLMEfreeMMPDUBuffer(PWB32_ADAPTER Adapter, PCHAR pData) 116void MLMEfreeMMPDUBuffer(PWB32_ADAPTER Adapter, s8 *pData)
117{ 117{
118 int i; 118 int i;
119 119
120 // Reclaim the data buffer 120 // Reclaim the data buffer
121 for (i = 0; i < MAX_NUM_TX_MMPDU; i++) { 121 for (i = 0; i < MAX_NUM_TX_MMPDU; i++) {
122 if (pData == (PCHAR)&(Adapter->sMlmeFrame.TxMMPDU[i])) 122 if (pData == (s8 *)&(Adapter->sMlmeFrame.TxMMPDU[i]))
123 break; 123 break;
124 } 124 }
125 if (Adapter->sMlmeFrame.TxMMPDUInUse[i]) 125 if (Adapter->sMlmeFrame.TxMMPDUInUse[i])
diff --git a/drivers/staging/winbond/mlmetxrx_f.h b/drivers/staging/winbond/mlmetxrx_f.h
index d74e225be215..24cd5f308d9f 100644
--- a/drivers/staging/winbond/mlmetxrx_f.h
+++ b/drivers/staging/winbond/mlmetxrx_f.h
@@ -20,7 +20,7 @@ MLMEGetMMPDUBuffer(
20 PWB32_ADAPTER Adapter 20 PWB32_ADAPTER Adapter
21 ); 21 );
22 22
23void MLMEfreeMMPDUBuffer( PWB32_ADAPTER Adapter, PCHAR pData); 23void MLMEfreeMMPDUBuffer( PWB32_ADAPTER Adapter, s8 * pData);
24 24
25void MLME_GetNextPacket( PADAPTER Adapter, PDESCRIPTOR pDes ); 25void MLME_GetNextPacket( PADAPTER Adapter, PDESCRIPTOR pDes );
26u8 MLMESendFrame( PWB32_ADAPTER Adapter, 26u8 MLMESendFrame( PWB32_ADAPTER Adapter,
@@ -42,7 +42,7 @@ MLMERcvFrame(
42void 42void
43MLMEReturnPacket( 43MLMEReturnPacket(
44 PWB32_ADAPTER Adapter, 44 PWB32_ADAPTER Adapter,
45 PUCHAR pRxBufer 45 u8 * pRxBufer
46 ); 46 );
47#ifdef _IBSS_BEACON_SEQ_STICK_ 47#ifdef _IBSS_BEACON_SEQ_STICK_
48s8 SendBCNullData(PWB32_ADAPTER Adapter, u16 wIdx); 48s8 SendBCNullData(PWB32_ADAPTER Adapter, u16 wIdx);
diff --git a/drivers/staging/winbond/reg.c b/drivers/staging/winbond/reg.c
index b475c7a7c424..57af5b831509 100644
--- a/drivers/staging/winbond/reg.c
+++ b/drivers/staging/winbond/reg.c
@@ -922,16 +922,16 @@ Uxx_ReadEthernetAddress( phw_data_t pHwData )
922 // Only unplug and plug again can make hardware read EEPROM again. 20060727 922 // Only unplug and plug again can make hardware read EEPROM again. 20060727
923 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08000000 ); // Start EEPROM access + Read + address(0x0d) 923 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08000000 ); // Start EEPROM access + Read + address(0x0d)
924 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp ); 924 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
925 *(PUSHORT)pHwData->PermanentMacAddress = cpu_to_le16((u16)ltmp); //20060926 anson's endian 925 *(u16 *)pHwData->PermanentMacAddress = cpu_to_le16((u16)ltmp); //20060926 anson's endian
926 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08010000 ); // Start EEPROM access + Read + address(0x0d) 926 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08010000 ); // Start EEPROM access + Read + address(0x0d)
927 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp ); 927 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
928 *(PUSHORT)(pHwData->PermanentMacAddress + 2) = cpu_to_le16((u16)ltmp); //20060926 anson's endian 928 *(u16 *)(pHwData->PermanentMacAddress + 2) = cpu_to_le16((u16)ltmp); //20060926 anson's endian
929 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08020000 ); // Start EEPROM access + Read + address(0x0d) 929 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08020000 ); // Start EEPROM access + Read + address(0x0d)
930 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp ); 930 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
931 *(PUSHORT)(pHwData->PermanentMacAddress + 4) = cpu_to_le16((u16)ltmp); //20060926 anson's endian 931 *(u16 *)(pHwData->PermanentMacAddress + 4) = cpu_to_le16((u16)ltmp); //20060926 anson's endian
932 *(PUSHORT)(pHwData->PermanentMacAddress + 6) = 0; 932 *(u16 *)(pHwData->PermanentMacAddress + 6) = 0;
933 Wb35Reg_WriteSync( pHwData, 0x03e8, cpu_to_le32(*(PULONG)pHwData->PermanentMacAddress) ); //20060926 anson's endian 933 Wb35Reg_WriteSync( pHwData, 0x03e8, cpu_to_le32(*(u32 *)pHwData->PermanentMacAddress) ); //20060926 anson's endian
934 Wb35Reg_WriteSync( pHwData, 0x03ec, cpu_to_le32(*(PULONG)(pHwData->PermanentMacAddress+4)) ); //20060926 anson's endian 934 Wb35Reg_WriteSync( pHwData, 0x03ec, cpu_to_le32(*(u32 *)(pHwData->PermanentMacAddress+4)) ); //20060926 anson's endian
935} 935}
936 936
937 937
@@ -1038,7 +1038,7 @@ void
1038RFSynthesizer_initial(phw_data_t pHwData) 1038RFSynthesizer_initial(phw_data_t pHwData)
1039{ 1039{
1040 u32 altmp[32]; 1040 u32 altmp[32];
1041 PULONG pltmp = altmp; 1041 u32 * pltmp = altmp;
1042 u32 ltmp; 1042 u32 ltmp;
1043 u8 number=0x00; // The number of register vale 1043 u8 number=0x00; // The number of register vale
1044 u8 i; 1044 u8 i;
@@ -2358,11 +2358,11 @@ void Mxx_initial( phw_data_t pHwData )
2358 pltmp[2] = pWb35Reg->M2C_MacControl; 2358 pltmp[2] = pWb35Reg->M2C_MacControl;
2359 2359
2360 // M30 BSSID 2360 // M30 BSSID
2361 pltmp[3] = *(PULONG)pHwData->bssid; 2361 pltmp[3] = *(u32 *)pHwData->bssid;
2362 2362
2363 // M34 2363 // M34
2364 pHwData->AID = DEFAULT_AID; 2364 pHwData->AID = DEFAULT_AID;
2365 tmp = *(PUSHORT)(pHwData->bssid+4); 2365 tmp = *(u16 *)(pHwData->bssid+4);
2366 tmp |= DEFAULT_AID << 16; 2366 tmp |= DEFAULT_AID << 16;
2367 pltmp[4] = tmp; 2367 pltmp[4] = tmp;
2368 2368
@@ -2428,7 +2428,7 @@ void GetTxVgaFromEEPROM( phw_data_t pHwData )
2428{ 2428{
2429 u32 i, j, ltmp; 2429 u32 i, j, ltmp;
2430 u16 Value[MAX_TXVGA_EEPROM]; 2430 u16 Value[MAX_TXVGA_EEPROM];
2431 PUCHAR pctmp; 2431 u8 *pctmp;
2432 u8 ctmp=0; 2432 u8 ctmp=0;
2433 2433
2434 // Get the entire TxVga setting in EEPROM 2434 // Get the entire TxVga setting in EEPROM
@@ -2441,7 +2441,7 @@ void GetTxVgaFromEEPROM( phw_data_t pHwData )
2441 } 2441 }
2442 2442
2443 // Adjust the filed which fills with reserved value. 2443 // Adjust the filed which fills with reserved value.
2444 pctmp = (PUCHAR)Value; 2444 pctmp = (u8 *)Value;
2445 for( i=0; i<(MAX_TXVGA_EEPROM*2); i++ ) 2445 for( i=0; i<(MAX_TXVGA_EEPROM*2); i++ )
2446 { 2446 {
2447 if( pctmp[i] != 0xff ) 2447 if( pctmp[i] != 0xff )
@@ -2480,7 +2480,7 @@ void GetTxVgaFromEEPROM( phw_data_t pHwData )
2480// This function will use default TxVgaSettingInEEPROM data to calculate new TxVga. 2480// This function will use default TxVgaSettingInEEPROM data to calculate new TxVga.
2481void EEPROMTxVgaAdjust( phw_data_t pHwData ) // 20060619.5 Add 2481void EEPROMTxVgaAdjust( phw_data_t pHwData ) // 20060619.5 Add
2482{ 2482{
2483 PUCHAR pTxVga = pHwData->TxVgaSettingInEEPROM; 2483 u8 * pTxVga = pHwData->TxVgaSettingInEEPROM;
2484 s16 i, stmp; 2484 s16 i, stmp;
2485 2485
2486 //-- 2.4G -- 20060704.2 Request from Tiger 2486 //-- 2.4G -- 20060704.2 Request from Tiger
diff --git a/drivers/staging/winbond/sme_api.c b/drivers/staging/winbond/sme_api.c
index 40e93b7600eb..31c9673ea865 100644
--- a/drivers/staging/winbond/sme_api.c
+++ b/drivers/staging/winbond/sme_api.c
@@ -10,4 +10,5 @@
10s8 sme_get_rssi(void *pcore_data, s32 *prssi) 10s8 sme_get_rssi(void *pcore_data, s32 *prssi)
11{ 11{
12 BUG(); 12 BUG();
13 return 0;
13} 14}
diff --git a/drivers/staging/winbond/sme_api.h b/drivers/staging/winbond/sme_api.h
index 016b225ca4a4..745eb376bc70 100644
--- a/drivers/staging/winbond/sme_api.h
+++ b/drivers/staging/winbond/sme_api.h
@@ -208,7 +208,7 @@ s8 sme_set_tx_antenna(void *pcore_data, u32 TxAntenna);
208s8 sme_set_IBSS_chan(void *pcore_data, ChanInfo chan); 208s8 sme_set_IBSS_chan(void *pcore_data, ChanInfo chan);
209 209
210//20061108 WPS 210//20061108 WPS
211s8 sme_set_IE_append(void *pcore_data, PUCHAR buffer, u16 buf_len); 211s8 sme_set_IE_append(void *pcore_data, u8 *buffer, u16 buf_len);
212 212
213 213
214 214
diff --git a/drivers/staging/winbond/wbhal.c b/drivers/staging/winbond/wbhal.c
index daf442247558..5d68ecec34c7 100644
--- a/drivers/staging/winbond/wbhal.c
+++ b/drivers/staging/winbond/wbhal.c
@@ -1,13 +1,13 @@
1#include "os_common.h" 1#include "os_common.h"
2 2
3void hal_get_ethernet_address( phw_data_t pHwData, PUCHAR current_address ) 3void hal_get_ethernet_address( phw_data_t pHwData, u8 *current_address )
4{ 4{
5 if( pHwData->SurpriseRemove ) return; 5 if( pHwData->SurpriseRemove ) return;
6 6
7 memcpy( current_address, pHwData->CurrentMacAddress, ETH_LENGTH_OF_ADDRESS ); 7 memcpy( current_address, pHwData->CurrentMacAddress, ETH_LENGTH_OF_ADDRESS );
8} 8}
9 9
10void hal_set_ethernet_address( phw_data_t pHwData, PUCHAR current_address ) 10void hal_set_ethernet_address( phw_data_t pHwData, u8 *current_address )
11{ 11{
12 u32 ltmp[2]; 12 u32 ltmp[2];
13 13
@@ -15,13 +15,13 @@ void hal_set_ethernet_address( phw_data_t pHwData, PUCHAR current_address )
15 15
16 memcpy( pHwData->CurrentMacAddress, current_address, ETH_LENGTH_OF_ADDRESS ); 16 memcpy( pHwData->CurrentMacAddress, current_address, ETH_LENGTH_OF_ADDRESS );
17 17
18 ltmp[0]= cpu_to_le32( *(PULONG)pHwData->CurrentMacAddress ); 18 ltmp[0]= cpu_to_le32( *(u32 *)pHwData->CurrentMacAddress );
19 ltmp[1]= cpu_to_le32( *(PULONG)(pHwData->CurrentMacAddress + 4) ) & 0xffff; 19 ltmp[1]= cpu_to_le32( *(u32 *)(pHwData->CurrentMacAddress + 4) ) & 0xffff;
20 20
21 Wb35Reg_BurstWrite( pHwData, 0x03e8, ltmp, 2, AUTO_INCREMENT ); 21 Wb35Reg_BurstWrite( pHwData, 0x03e8, ltmp, 2, AUTO_INCREMENT );
22} 22}
23 23
24void hal_get_permanent_address( phw_data_t pHwData, PUCHAR pethernet_address ) 24void hal_get_permanent_address( phw_data_t pHwData, u8 *pethernet_address )
25{ 25{
26 if( pHwData->SurpriseRemove ) return; 26 if( pHwData->SurpriseRemove ) return;
27 27
@@ -89,7 +89,7 @@ void hal_halt(phw_data_t pHwData, void *ppa_data)
89} 89}
90 90
91//--------------------------------------------------------------------------------------------------- 91//---------------------------------------------------------------------------------------------------
92void hal_set_rates(phw_data_t pHwData, PUCHAR pbss_rates, 92void hal_set_rates(phw_data_t pHwData, u8 *pbss_rates,
93 u8 length, unsigned char basic_rate_set) 93 u8 length, unsigned char basic_rate_set)
94{ 94{
95 PWB35REG pWb35Reg = &pHwData->Wb35Reg; 95 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
@@ -158,13 +158,13 @@ void hal_set_rates(phw_data_t pHwData, PUCHAR pbss_rates,
158 // Fill data into support rate until buffer full 158 // Fill data into support rate until buffer full
159 //---20060926 add by anson's endian 159 //---20060926 add by anson's endian
160 for (i=0; i<4; i++) 160 for (i=0; i<4; i++)
161 *(PULONG)(SupportedRate+(i<<2)) = cpu_to_le32( *(PULONG)(SupportedRate+(i<<2)) ); 161 *(u32 *)(SupportedRate+(i<<2)) = cpu_to_le32( *(u32 *)(SupportedRate+(i<<2)) );
162 //--- end 20060926 add by anson's endian 162 //--- end 20060926 add by anson's endian
163 Wb35Reg_BurstWrite( pHwData,0x087c, (PULONG)SupportedRate, 4, AUTO_INCREMENT ); 163 Wb35Reg_BurstWrite( pHwData,0x087c, (u32 *)SupportedRate, 4, AUTO_INCREMENT );
164 pWb35Reg->M7C_MacControl = ((PULONG)SupportedRate)[0]; 164 pWb35Reg->M7C_MacControl = ((u32 *)SupportedRate)[0];
165 pWb35Reg->M80_MacControl = ((PULONG)SupportedRate)[1]; 165 pWb35Reg->M80_MacControl = ((u32 *)SupportedRate)[1];
166 pWb35Reg->M84_MacControl = ((PULONG)SupportedRate)[2]; 166 pWb35Reg->M84_MacControl = ((u32 *)SupportedRate)[2];
167 pWb35Reg->M88_MacControl = ((PULONG)SupportedRate)[3]; 167 pWb35Reg->M88_MacControl = ((u32 *)SupportedRate)[3];
168 168
169 // Fill length 169 // Fill length
170 tmp = Count1<<28 | Count2<<24; 170 tmp = Count1<<28 | Count2<<24;
@@ -206,7 +206,7 @@ void hal_set_current_channel_ex( phw_data_t pHwData, ChanInfo channel )
206 pWb35Reg->M28_MacControl &= ~0xff; // Clean channel information field 206 pWb35Reg->M28_MacControl &= ~0xff; // Clean channel information field
207 pWb35Reg->M28_MacControl |= channel.ChanNo; 207 pWb35Reg->M28_MacControl |= channel.ChanNo;
208 Wb35Reg_WriteWithCallbackValue( pHwData, 0x0828, pWb35Reg->M28_MacControl, 208 Wb35Reg_WriteWithCallbackValue( pHwData, 0x0828, pWb35Reg->M28_MacControl,
209 (PCHAR)&channel, sizeof(ChanInfo)); 209 (s8 *)&channel, sizeof(ChanInfo));
210} 210}
211//--------------------------------------------------------------------------------------------------- 211//---------------------------------------------------------------------------------------------------
212void hal_set_current_channel( phw_data_t pHwData, ChanInfo channel ) 212void hal_set_current_channel( phw_data_t pHwData, ChanInfo channel )
@@ -277,7 +277,7 @@ void hal_set_accept_beacon( phw_data_t pHwData, u8 enable )
277 Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl ); 277 Wb35Reg_Write( pHwData, 0x0800, pWb35Reg->M00_MacControl );
278} 278}
279//--------------------------------------------------------------------------------------------------- 279//---------------------------------------------------------------------------------------------------
280void hal_set_multicast_address( phw_data_t pHwData, PUCHAR address, u8 number ) 280void hal_set_multicast_address( phw_data_t pHwData, u8 *address, u8 number )
281{ 281{
282 PWB35REG pWb35Reg = &pHwData->Wb35Reg; 282 PWB35REG pWb35Reg = &pHwData->Wb35Reg;
283 u8 Byte, Bit; 283 u8 Byte, Bit;
@@ -297,7 +297,7 @@ void hal_set_multicast_address( phw_data_t pHwData, PUCHAR address, u8 number )
297 } 297 }
298 298
299 // Updating register 299 // Updating register
300 Wb35Reg_BurstWrite( pHwData, 0x0804, (PULONG)pWb35Reg->Multicast, 2, AUTO_INCREMENT ); 300 Wb35Reg_BurstWrite( pHwData, 0x0804, (u32 *)pWb35Reg->Multicast, 2, AUTO_INCREMENT );
301} 301}
302//--------------------------------------------------------------------------------------------------- 302//---------------------------------------------------------------------------------------------------
303u8 hal_get_accept_beacon( phw_data_t pHwData ) 303u8 hal_get_accept_beacon( phw_data_t pHwData )
@@ -806,7 +806,7 @@ u8 hal_get_hw_radio_off( phw_data_t pHwData )
806 } 806 }
807} 807}
808 808
809unsigned char hal_get_dxx_reg( phw_data_t pHwData, u16 number, PULONG pValue ) 809unsigned char hal_get_dxx_reg( phw_data_t pHwData, u16 number, u32 * pValue )
810{ 810{
811 if( number < 0x1000 ) 811 if( number < 0x1000 )
812 number += 0x1000; 812 number += 0x1000;
diff --git a/drivers/staging/winbond/wbhal_f.h b/drivers/staging/winbond/wbhal_f.h
index fe25f97af724..ea9531ac8474 100644
--- a/drivers/staging/winbond/wbhal_f.h
+++ b/drivers/staging/winbond/wbhal_f.h
@@ -16,23 +16,23 @@
16//==================================================================================== 16//====================================================================================
17// Function declaration 17// Function declaration
18//==================================================================================== 18//====================================================================================
19void hal_remove_mapping_key( phw_data_t pHwData, PUCHAR pmac_addr ); 19void hal_remove_mapping_key( phw_data_t pHwData, u8 *pmac_addr );
20void hal_remove_default_key( phw_data_t pHwData, u32 index ); 20void hal_remove_default_key( phw_data_t pHwData, u32 index );
21unsigned char hal_set_mapping_key( phw_data_t Adapter, PUCHAR pmac_addr, u8 null_key, u8 wep_on, PUCHAR ptx_tsc, PUCHAR prx_tsc, u8 key_type, u8 key_len, PUCHAR pkey_data ); 21unsigned char hal_set_mapping_key( phw_data_t Adapter, u8 *pmac_addr, u8 null_key, u8 wep_on, u8 *ptx_tsc, u8 *prx_tsc, u8 key_type, u8 key_len, u8 *pkey_data );
22unsigned char hal_set_default_key( phw_data_t Adapter, u8 index, u8 null_key, u8 wep_on, PUCHAR ptx_tsc, PUCHAR prx_tsc, u8 key_type, u8 key_len, PUCHAR pkey_data ); 22unsigned char hal_set_default_key( phw_data_t Adapter, u8 index, u8 null_key, u8 wep_on, u8 *ptx_tsc, u8 *prx_tsc, u8 key_type, u8 key_len, u8 *pkey_data );
23void hal_clear_all_default_key( phw_data_t pHwData ); 23void hal_clear_all_default_key( phw_data_t pHwData );
24void hal_clear_all_group_key( phw_data_t pHwData ); 24void hal_clear_all_group_key( phw_data_t pHwData );
25void hal_clear_all_mapping_key( phw_data_t pHwData ); 25void hal_clear_all_mapping_key( phw_data_t pHwData );
26void hal_clear_all_key( phw_data_t pHwData ); 26void hal_clear_all_key( phw_data_t pHwData );
27void hal_get_ethernet_address( phw_data_t pHwData, PUCHAR current_address ); 27void hal_get_ethernet_address( phw_data_t pHwData, u8 *current_address );
28void hal_set_ethernet_address( phw_data_t pHwData, PUCHAR current_address ); 28void hal_set_ethernet_address( phw_data_t pHwData, u8 *current_address );
29void hal_get_permanent_address( phw_data_t pHwData, PUCHAR pethernet_address ); 29void hal_get_permanent_address( phw_data_t pHwData, u8 *pethernet_address );
30unsigned char hal_init_hardware( phw_data_t pHwData, PADAPTER Adapter ); 30unsigned char hal_init_hardware( phw_data_t pHwData, PADAPTER Adapter );
31void hal_set_power_save_mode( phw_data_t pHwData, unsigned char power_save, unsigned char wakeup, unsigned char dtim ); 31void hal_set_power_save_mode( phw_data_t pHwData, unsigned char power_save, unsigned char wakeup, unsigned char dtim );
32void hal_get_power_save_mode( phw_data_t pHwData, PBOOLEAN pin_pwr_save ); 32void hal_get_power_save_mode( phw_data_t pHwData, u8 *pin_pwr_save );
33void hal_set_slot_time( phw_data_t pHwData, u8 type ); 33void hal_set_slot_time( phw_data_t pHwData, u8 type );
34#define hal_set_atim_window( _A, _ATM ) 34#define hal_set_atim_window( _A, _ATM )
35void hal_set_rates( phw_data_t pHwData, PUCHAR pbss_rates, u8 length, unsigned char basic_rate_set ); 35void hal_set_rates( phw_data_t pHwData, u8 *pbss_rates, u8 length, unsigned char basic_rate_set );
36#define hal_set_basic_rates( _A, _R, _L ) hal_set_rates( _A, _R, _L, TRUE ) 36#define hal_set_basic_rates( _A, _R, _L ) hal_set_rates( _A, _R, _L, TRUE )
37#define hal_set_op_rates( _A, _R, _L ) hal_set_rates( _A, _R, _L, FALSE ) 37#define hal_set_op_rates( _A, _R, _L ) hal_set_rates( _A, _R, _L, FALSE )
38void hal_start_bss( phw_data_t pHwData, u8 mac_op_mode ); 38void hal_start_bss( phw_data_t pHwData, u8 mac_op_mode );
@@ -40,19 +40,19 @@ void hal_join_request( phw_data_t pHwData, u8 bss_type ); // 0:BSS STA 1:IBSS
40void hal_stop_sync_bss( phw_data_t pHwData ); 40void hal_stop_sync_bss( phw_data_t pHwData );
41void hal_resume_sync_bss( phw_data_t pHwData); 41void hal_resume_sync_bss( phw_data_t pHwData);
42void hal_set_aid( phw_data_t pHwData, u16 aid ); 42void hal_set_aid( phw_data_t pHwData, u16 aid );
43void hal_set_bssid( phw_data_t pHwData, PUCHAR pbssid ); 43void hal_set_bssid( phw_data_t pHwData, u8 *pbssid );
44void hal_get_bssid( phw_data_t pHwData, PUCHAR pbssid ); 44void hal_get_bssid( phw_data_t pHwData, u8 *pbssid );
45void hal_set_beacon_period( phw_data_t pHwData, u16 beacon_period ); 45void hal_set_beacon_period( phw_data_t pHwData, u16 beacon_period );
46void hal_set_listen_interval( phw_data_t pHwData, u16 listen_interval ); 46void hal_set_listen_interval( phw_data_t pHwData, u16 listen_interval );
47void hal_set_cap_info( phw_data_t pHwData, u16 capability_info ); 47void hal_set_cap_info( phw_data_t pHwData, u16 capability_info );
48void hal_set_ssid( phw_data_t pHwData, PUCHAR pssid, u8 ssid_len ); 48void hal_set_ssid( phw_data_t pHwData, u8 *pssid, u8 ssid_len );
49void hal_set_current_channel( phw_data_t pHwData, ChanInfo channel ); 49void hal_set_current_channel( phw_data_t pHwData, ChanInfo channel );
50void hal_set_current_channel_ex( phw_data_t pHwData, ChanInfo channel ); 50void hal_set_current_channel_ex( phw_data_t pHwData, ChanInfo channel );
51void hal_get_current_channel( phw_data_t pHwData, ChanInfo *channel ); 51void hal_get_current_channel( phw_data_t pHwData, ChanInfo *channel );
52void hal_set_accept_broadcast( phw_data_t pHwData, u8 enable ); 52void hal_set_accept_broadcast( phw_data_t pHwData, u8 enable );
53void hal_set_accept_multicast( phw_data_t pHwData, u8 enable ); 53void hal_set_accept_multicast( phw_data_t pHwData, u8 enable );
54void hal_set_accept_beacon( phw_data_t pHwData, u8 enable ); 54void hal_set_accept_beacon( phw_data_t pHwData, u8 enable );
55void hal_set_multicast_address( phw_data_t pHwData, PUCHAR address, u8 number ); 55void hal_set_multicast_address( phw_data_t pHwData, u8 *address, u8 number );
56u8 hal_get_accept_beacon( phw_data_t pHwData ); 56u8 hal_get_accept_beacon( phw_data_t pHwData );
57void hal_stop( phw_data_t pHwData ); 57void hal_stop( phw_data_t pHwData );
58void hal_halt( phw_data_t pHwData, void *ppa_data ); 58void hal_halt( phw_data_t pHwData, void *ppa_data );
@@ -97,7 +97,7 @@ void hal_surprise_remove( phw_data_t pHwData );
97 97
98 98
99void hal_rate_change( phw_data_t pHwData ); // Notify the HAL rate is changing 20060613.1 99void hal_rate_change( phw_data_t pHwData ); // Notify the HAL rate is changing 20060613.1
100unsigned char hal_get_dxx_reg( phw_data_t pHwData, u16 number, PULONG pValue ); 100unsigned char hal_get_dxx_reg( phw_data_t pHwData, u16 number, u32 * pValue );
101unsigned char hal_set_dxx_reg( phw_data_t pHwData, u16 number, u32 value ); 101unsigned char hal_set_dxx_reg( phw_data_t pHwData, u16 number, u32 value );
102#define hal_get_time_count( _P ) (_P->time_count/10) // return 100ms count 102#define hal_get_time_count( _P ) (_P->time_count/10) // return 100ms count
103#define hal_detect_error( _P ) (_P->WbUsb.DetectCount) 103#define hal_detect_error( _P ) (_P->WbUsb.DetectCount)
@@ -116,7 +116,7 @@ unsigned char hal_idle( phw_data_t pHwData );
116#define pa_stall_execution( _A ) //OS_SLEEP( 1 ) 116#define pa_stall_execution( _A ) //OS_SLEEP( 1 )
117#define hw_get_cxx_reg( _A, _B, _C ) 117#define hw_get_cxx_reg( _A, _B, _C )
118#define hw_set_cxx_reg( _A, _B, _C ) 118#define hw_set_cxx_reg( _A, _B, _C )
119#define hw_get_dxx_reg( _A, _B, _C ) hal_get_dxx_reg( _A, _B, (PULONG)_C ) 119#define hw_get_dxx_reg( _A, _B, _C ) hal_get_dxx_reg( _A, _B, (u32 *)_C )
120#define hw_set_dxx_reg( _A, _B, _C ) hal_set_dxx_reg( _A, _B, (u32)_C ) 120#define hw_set_dxx_reg( _A, _B, _C ) hal_set_dxx_reg( _A, _B, (u32)_C )
121 121
122 122
diff --git a/drivers/staging/winbond/wbhal_s.h b/drivers/staging/winbond/wbhal_s.h
index 5b862ff357bd..2ee3f0fc1ad8 100644
--- a/drivers/staging/winbond/wbhal_s.h
+++ b/drivers/staging/winbond/wbhal_s.h
@@ -461,7 +461,7 @@ typedef struct _HW_DATA_T
461 //===================================================================== 461 //=====================================================================
462 // Definition for 802.11 462 // Definition for 802.11
463 //===================================================================== 463 //=====================================================================
464 PUCHAR bssid_pointer; // Used by hal_get_bssid for return value 464 u8 *bssid_pointer; // Used by hal_get_bssid for return value
465 u8 bssid[8];// Only 6 byte will be used. 8 byte is required for read buffer 465 u8 bssid[8];// Only 6 byte will be used. 8 byte is required for read buffer
466 u8 ssid[32];// maximum ssid length is 32 byte 466 u8 ssid[32];// maximum ssid length is 32 byte
467 467
@@ -486,7 +486,7 @@ typedef struct _HW_DATA_T
486 u32 CurrentRadioSw; // 20060320.2 0:On 1:Off 486 u32 CurrentRadioSw; // 20060320.2 0:On 1:Off
487 u32 CurrentRadioHw; // 20060825 0:On 1:Off 487 u32 CurrentRadioHw; // 20060825 0:On 1:Off
488 488
489 PUCHAR power_save_point; // Used by hal_get_power_save_mode for return value 489 u8 *power_save_point; // Used by hal_get_power_save_mode for return value
490 u8 cwmin; 490 u8 cwmin;
491 u8 desired_power_save; 491 u8 desired_power_save;
492 u8 dtim;// Is running dtim 492 u8 dtim;// Is running dtim
diff --git a/drivers/staging/winbond/wblinux.c b/drivers/staging/winbond/wblinux.c
index 2eade5a47b19..4ed45e488318 100644
--- a/drivers/staging/winbond/wblinux.c
+++ b/drivers/staging/winbond/wblinux.c
@@ -25,11 +25,11 @@ EncapAtomicInc(PADAPTER Adapter, void* pAtomic)
25{ 25{
26 PWBLINUX pWbLinux = &Adapter->WbLinux; 26 PWBLINUX pWbLinux = &Adapter->WbLinux;
27 u32 ltmp; 27 u32 ltmp;
28 PULONG pltmp = (PULONG)pAtomic; 28 u32 * pltmp = (u32 *)pAtomic;
29 OS_SPIN_LOCK_ACQUIRED( &pWbLinux->AtomicSpinLock ); 29 spin_lock_irq( &pWbLinux->AtomicSpinLock );
30 (*pltmp)++; 30 (*pltmp)++;
31 ltmp = (*pltmp); 31 ltmp = (*pltmp);
32 OS_SPIN_LOCK_RELEASED( &pWbLinux->AtomicSpinLock ); 32 spin_unlock_irq( &pWbLinux->AtomicSpinLock );
33 return ltmp; 33 return ltmp;
34} 34}
35 35
@@ -38,11 +38,11 @@ EncapAtomicDec(PADAPTER Adapter, void* pAtomic)
38{ 38{
39 PWBLINUX pWbLinux = &Adapter->WbLinux; 39 PWBLINUX pWbLinux = &Adapter->WbLinux;
40 u32 ltmp; 40 u32 ltmp;
41 PULONG pltmp = (PULONG)pAtomic; 41 u32 * pltmp = (u32 *)pAtomic;
42 OS_SPIN_LOCK_ACQUIRED( &pWbLinux->AtomicSpinLock ); 42 spin_lock_irq( &pWbLinux->AtomicSpinLock );
43 (*pltmp)--; 43 (*pltmp)--;
44 ltmp = (*pltmp); 44 ltmp = (*pltmp);
45 OS_SPIN_LOCK_RELEASED( &pWbLinux->AtomicSpinLock ); 45 spin_unlock_irq( &pWbLinux->AtomicSpinLock );
46 return ltmp; 46 return ltmp;
47} 47}
48 48
@@ -51,8 +51,8 @@ WBLINUX_Initial(PADAPTER Adapter)
51{ 51{
52 PWBLINUX pWbLinux = &Adapter->WbLinux; 52 PWBLINUX pWbLinux = &Adapter->WbLinux;
53 53
54 OS_SPIN_LOCK_ALLOCATE( &pWbLinux->SpinLock ); 54 spin_lock_init( &pWbLinux->SpinLock );
55 OS_SPIN_LOCK_ALLOCATE( &pWbLinux->AtomicSpinLock ); 55 spin_lock_init( &pWbLinux->AtomicSpinLock );
56 return TRUE; 56 return TRUE;
57} 57}
58 58
@@ -79,7 +79,6 @@ void
79WBLINUX_Destroy(PADAPTER Adapter) 79WBLINUX_Destroy(PADAPTER Adapter)
80{ 80{
81 WBLINUX_stop( Adapter ); 81 WBLINUX_stop( Adapter );
82 OS_SPIN_LOCK_FREE( &pWbNdis->SpinLock );
83#ifdef _PE_USB_INI_DUMP_ 82#ifdef _PE_USB_INI_DUMP_
84 WBDEBUG(("[w35und] unregister_netdev!\n")); 83 WBDEBUG(("[w35und] unregister_netdev!\n"));
85#endif 84#endif
@@ -142,119 +141,118 @@ unsigned char
142WbWLanInitialize(PADAPTER Adapter) 141WbWLanInitialize(PADAPTER Adapter)
143{ 142{
144 phw_data_t pHwData; 143 phw_data_t pHwData;
145 PUCHAR pMacAddr, pMacAddr2; 144 u8 *pMacAddr;
145 u8 *pMacAddr2;
146 u32 InitStep = 0; 146 u32 InitStep = 0;
147 u8 EEPROM_region; 147 u8 EEPROM_region;
148 u8 HwRadioOff; 148 u8 HwRadioOff;
149 149
150 do { 150 //
151 // 151 // Setting default value for Linux
152 // Setting default value for Linux 152 //
153 // 153 Adapter->sLocalPara.region_INF = REGION_AUTO;
154 Adapter->sLocalPara.region_INF = REGION_AUTO; 154 Adapter->sLocalPara.TxRateMode = RATE_AUTO;
155 Adapter->sLocalPara.TxRateMode = RATE_AUTO; 155 psLOCAL->bMacOperationMode = MODE_802_11_BG; // B/G mode
156 psLOCAL->bMacOperationMode = MODE_802_11_BG; // B/G mode 156 Adapter->Mds.TxRTSThreshold = DEFAULT_RTSThreshold;
157 Adapter->Mds.TxRTSThreshold = DEFAULT_RTSThreshold; 157 Adapter->Mds.TxFragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD;
158 Adapter->Mds.TxFragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; 158 hal_set_phy_type( &Adapter->sHwData, RF_WB_242_1 );
159 hal_set_phy_type( &Adapter->sHwData, RF_WB_242_1 ); 159 Adapter->sLocalPara.MTUsize = MAX_ETHERNET_PACKET_SIZE;
160 Adapter->sLocalPara.MTUsize = MAX_ETHERNET_PACKET_SIZE; 160 psLOCAL->bPreambleMode = AUTO_MODE;
161 psLOCAL->bPreambleMode = AUTO_MODE; 161 Adapter->sLocalPara.RadioOffStatus.boSwRadioOff = FALSE;
162 Adapter->sLocalPara.RadioOffStatus.boSwRadioOff = FALSE; 162 pHwData = &Adapter->sHwData;
163 pHwData = &Adapter->sHwData; 163 hal_set_phy_type( pHwData, RF_DECIDE_BY_INF );
164 hal_set_phy_type( pHwData, RF_DECIDE_BY_INF ); 164
165 165 //
166 // 166 // Initial each module and variable
167 // Initial each module and variable 167 //
168 // 168 if (!WBLINUX_Initial(Adapter)) {
169 if (!WBLINUX_Initial(Adapter)) {
170#ifdef _PE_USB_INI_DUMP_ 169#ifdef _PE_USB_INI_DUMP_
171 WBDEBUG(("[w35und]WBNDIS initialization failed\n")); 170 WBDEBUG(("[w35und]WBNDIS initialization failed\n"));
172#endif 171#endif
173 break; 172 goto error;
174 } 173 }
175 174
176 // Initial Software variable 175 // Initial Software variable
177 Adapter->sLocalPara.ShutDowned = FALSE; 176 Adapter->sLocalPara.ShutDowned = FALSE;
178 177
179 //added by ws for wep key error detection 178 //added by ws for wep key error detection
180 Adapter->sLocalPara.bWepKeyError= FALSE; 179 Adapter->sLocalPara.bWepKeyError= FALSE;
181 Adapter->sLocalPara.bToSelfPacketReceived = FALSE; 180 Adapter->sLocalPara.bToSelfPacketReceived = FALSE;
182 Adapter->sLocalPara.WepKeyDetectTimerCount= 2 * 100; /// 2 seconds 181 Adapter->sLocalPara.WepKeyDetectTimerCount= 2 * 100; /// 2 seconds
183 182
184 // Initial USB hal 183 // Initial USB hal
185 InitStep = 1; 184 InitStep = 1;
186 pHwData = &Adapter->sHwData; 185 pHwData = &Adapter->sHwData;
187 if (!hal_init_hardware(pHwData, Adapter)) 186 if (!hal_init_hardware(pHwData, Adapter))
188 break; 187 goto error;
189 188
190 EEPROM_region = hal_get_region_from_EEPROM( pHwData ); 189 EEPROM_region = hal_get_region_from_EEPROM( pHwData );
191 if (EEPROM_region != REGION_AUTO) 190 if (EEPROM_region != REGION_AUTO)
192 psLOCAL->region = EEPROM_region; 191 psLOCAL->region = EEPROM_region;
193 else { 192 else {
194 if (psLOCAL->region_INF != REGION_AUTO) 193 if (psLOCAL->region_INF != REGION_AUTO)
195 psLOCAL->region = psLOCAL->region_INF; 194 psLOCAL->region = psLOCAL->region_INF;
196 else 195 else
197 psLOCAL->region = REGION_USA; //default setting 196 psLOCAL->region = REGION_USA; //default setting
198 } 197 }
199 198
200 // Get Software setting flag from hal 199 // Get Software setting flag from hal
201 Adapter->sLocalPara.boAntennaDiversity = FALSE; 200 Adapter->sLocalPara.boAntennaDiversity = FALSE;
202 if (hal_software_set(pHwData) & 0x00000001) 201 if (hal_software_set(pHwData) & 0x00000001)
203 Adapter->sLocalPara.boAntennaDiversity = TRUE; 202 Adapter->sLocalPara.boAntennaDiversity = TRUE;
204 203
205 // 204 //
206 // For TS module 205 // For TS module
207 // 206 //
208 InitStep = 2; 207 InitStep = 2;
209 208
210 // For MDS module 209 // For MDS module
211 InitStep = 3; 210 InitStep = 3;
212 Mds_initial(Adapter); 211 Mds_initial(Adapter);
213 212
214 //======================================= 213 //=======================================
215 // Initialize the SME, SCAN, MLME, ROAM 214 // Initialize the SME, SCAN, MLME, ROAM
216 //======================================= 215 //=======================================
217 InitStep = 4; 216 InitStep = 4;
218 InitStep = 5; 217 InitStep = 5;
219 InitStep = 6; 218 InitStep = 6;
220 219
221 // If no user-defined address in the registry, use the addresss "burned" on the NIC instead. 220 // If no user-defined address in the registry, use the addresss "burned" on the NIC instead.
222 pMacAddr = Adapter->sLocalPara.ThisMacAddress; 221 pMacAddr = Adapter->sLocalPara.ThisMacAddress;
223 pMacAddr2 = Adapter->sLocalPara.PermanentAddress; 222 pMacAddr2 = Adapter->sLocalPara.PermanentAddress;
224 hal_get_permanent_address( pHwData, Adapter->sLocalPara.PermanentAddress );// Reading ethernet address from EEPROM 223 hal_get_permanent_address( pHwData, Adapter->sLocalPara.PermanentAddress );// Reading ethernet address from EEPROM
225 if (OS_MEMORY_COMPARE(pMacAddr, "\x00\x00\x00\x00\x00\x00", MAC_ADDR_LENGTH )) // Is equal 224 if (OS_MEMORY_COMPARE(pMacAddr, "\x00\x00\x00\x00\x00\x00", MAC_ADDR_LENGTH )) // Is equal
226 { 225 {
227 memcpy( pMacAddr, pMacAddr2, MAC_ADDR_LENGTH ); 226 memcpy( pMacAddr, pMacAddr2, MAC_ADDR_LENGTH );
228 } else { 227 } else {
229 // Set the user define MAC address 228 // Set the user define MAC address
230 hal_set_ethernet_address( pHwData, Adapter->sLocalPara.ThisMacAddress ); 229 hal_set_ethernet_address( pHwData, Adapter->sLocalPara.ThisMacAddress );
231 } 230 }
232 231
233 //get current antenna 232 //get current antenna
234 psLOCAL->bAntennaNo = hal_get_antenna_number(pHwData); 233 psLOCAL->bAntennaNo = hal_get_antenna_number(pHwData);
235#ifdef _PE_STATE_DUMP_ 234#ifdef _PE_STATE_DUMP_
236 WBDEBUG(("Driver init, antenna no = %d\n", psLOCAL->bAntennaNo)); 235 WBDEBUG(("Driver init, antenna no = %d\n", psLOCAL->bAntennaNo));
237#endif 236#endif
238 hal_get_hw_radio_off( pHwData ); 237 hal_get_hw_radio_off( pHwData );
239 238
240 // Waiting for HAL setting OK 239 // Waiting for HAL setting OK
241 while (!hal_idle(pHwData)) 240 while (!hal_idle(pHwData))
242 OS_SLEEP(10000); 241 OS_SLEEP(10000);
243 242
244 MTO_Init(Adapter); 243 MTO_Init(Adapter);
245 244
246 HwRadioOff = hal_get_hw_radio_off( pHwData ); 245 HwRadioOff = hal_get_hw_radio_off( pHwData );
247 psLOCAL->RadioOffStatus.boHwRadioOff = !!HwRadioOff; 246 psLOCAL->RadioOffStatus.boHwRadioOff = !!HwRadioOff;
248 247
249 hal_set_radio_mode( pHwData, (unsigned char)(psLOCAL->RadioOffStatus.boSwRadioOff || psLOCAL->RadioOffStatus.boHwRadioOff) ); 248 hal_set_radio_mode( pHwData, (unsigned char)(psLOCAL->RadioOffStatus.boSwRadioOff || psLOCAL->RadioOffStatus.boHwRadioOff) );
250 249
251 hal_driver_init_OK(pHwData) = 1; // Notify hal that the driver is ready now. 250 hal_driver_init_OK(pHwData) = 1; // Notify hal that the driver is ready now.
252 //set a tx power for reference..... 251 //set a tx power for reference.....
253// sme_set_tx_power_level(Adapter, 12); FIXME? 252// sme_set_tx_power_level(Adapter, 12); FIXME?
254 return TRUE; 253 return TRUE;
255 }
256 while(FALSE);
257 254
255error:
258 switch (InitStep) { 256 switch (InitStep) {
259 case 5: 257 case 5:
260 case 4: 258 case 4:
diff --git a/drivers/staging/winbond/wblinux_s.h b/drivers/staging/winbond/wblinux_s.h
index 97e9167ab839..fd2bb43bf3cf 100644
--- a/drivers/staging/winbond/wblinux_s.h
+++ b/drivers/staging/winbond/wblinux_s.h
@@ -24,8 +24,8 @@
24 24
25typedef struct _WBLINUX 25typedef struct _WBLINUX
26{ 26{
27 OS_SPIN_LOCK AtomicSpinLock; 27 spinlock_t AtomicSpinLock;
28 OS_SPIN_LOCK SpinLock; 28 spinlock_t SpinLock;
29 u32 shutdown; 29 u32 shutdown;
30 30
31 OS_ATOMIC ThreadCount; 31 OS_ATOMIC ThreadCount;
diff --git a/drivers/staging/wlan-ng/Kconfig b/drivers/staging/wlan-ng/Kconfig
index 10b1f0f634d3..2425d860dcaf 100644
--- a/drivers/staging/wlan-ng/Kconfig
+++ b/drivers/staging/wlan-ng/Kconfig
@@ -1,6 +1,6 @@
1config PRISM2_USB 1config PRISM2_USB
2 tristate "Prism2.5 USB driver" 2 tristate "Prism2.5 USB driver"
3 depends on USB 3 depends on WLAN_80211 && USB
4 default n 4 default n
5 ---help--- 5 ---help---
6 This is the wlan-ng prism 2.5 USB driver for a wide range of 6 This is the wlan-ng prism 2.5 USB driver for a wide range of
diff --git a/drivers/staging/wlan-ng/hfa384x.h b/drivers/staging/wlan-ng/hfa384x.h
index a2054639d24b..0dfb8ce9aae7 100644
--- a/drivers/staging/wlan-ng/hfa384x.h
+++ b/drivers/staging/wlan-ng/hfa384x.h
@@ -824,7 +824,7 @@ PD Record codes
824#define HFA384x_CMD_MACPORT_SET(value) ((UINT16)HFA384x_CMD_AINFO_SET(value)) 824#define HFA384x_CMD_MACPORT_SET(value) ((UINT16)HFA384x_CMD_AINFO_SET(value))
825#define HFA384x_CMD_ISRECL(value) ((UINT16)(HFA384x_CMD_AINFO_GET((UINT16)(value) & HFA384x_CMD_RECL))) 825#define HFA384x_CMD_ISRECL(value) ((UINT16)(HFA384x_CMD_AINFO_GET((UINT16)(value) & HFA384x_CMD_RECL)))
826#define HFA384x_CMD_RECL_SET(value) ((UINT16)HFA384x_CMD_AINFO_SET(value)) 826#define HFA384x_CMD_RECL_SET(value) ((UINT16)HFA384x_CMD_AINFO_SET(value))
827#define HFA384x_CMD_QOS_GET(value) ((UINT16((((UINT16)(value))&((UINT16)0x3000)) >> 12)) 827#define HFA384x_CMD_QOS_GET(value) ((UINT16)((((UINT16)(value))&((UINT16)0x3000)) >> 12))
828#define HFA384x_CMD_QOS_SET(value) ((UINT16)((((UINT16)(value)) << 12) & 0x3000)) 828#define HFA384x_CMD_QOS_SET(value) ((UINT16)((((UINT16)(value)) << 12) & 0x3000))
829#define HFA384x_CMD_ISWRITE(value) ((UINT16)(HFA384x_CMD_AINFO_GET((UINT16)(value) & HFA384x_CMD_WRITE))) 829#define HFA384x_CMD_ISWRITE(value) ((UINT16)(HFA384x_CMD_AINFO_GET((UINT16)(value) & HFA384x_CMD_WRITE)))
830#define HFA384x_CMD_WRITE_SET(value) ((UINT16)HFA384x_CMD_AINFO_SET((UINT16)value)) 830#define HFA384x_CMD_WRITE_SET(value) ((UINT16)HFA384x_CMD_AINFO_SET((UINT16)value))
diff --git a/drivers/staging/wlan-ng/p80211wep.c b/drivers/staging/wlan-ng/p80211wep.c
index 53fe2985971f..11a50c7fbfc8 100644
--- a/drivers/staging/wlan-ng/p80211wep.c
+++ b/drivers/staging/wlan-ng/p80211wep.c
@@ -64,7 +64,6 @@
64/*================================================================*/ 64/*================================================================*/
65/* Project Includes */ 65/* Project Includes */
66 66
67#include "version.h"
68#include "p80211hdr.h" 67#include "p80211hdr.h"
69#include "p80211types.h" 68#include "p80211types.h"
70#include "p80211msg.h" 69#include "p80211msg.h"
diff --git a/drivers/staging/wlan-ng/prism2mib.c b/drivers/staging/wlan-ng/prism2mib.c
index 268fd9bba1ef..eac06f793d81 100644
--- a/drivers/staging/wlan-ng/prism2mib.c
+++ b/drivers/staging/wlan-ng/prism2mib.c
@@ -90,8 +90,6 @@
90#include <linux/usb.h> 90#include <linux/usb.h>
91//#endif 91//#endif
92 92
93#include "wlan_compat.h"
94
95/*================================================================*/ 93/*================================================================*/
96/* Project Includes */ 94/* Project Includes */
97 95
diff --git a/drivers/staging/wlan-ng/wlan_compat.h b/drivers/staging/wlan-ng/wlan_compat.h
index 17026570708f..59dfa8f84cbe 100644
--- a/drivers/staging/wlan-ng/wlan_compat.h
+++ b/drivers/staging/wlan-ng/wlan_compat.h
@@ -245,11 +245,11 @@ typedef int64_t INT64;
245# define preempt_count() (0UL) 245# define preempt_count() (0UL)
246#endif 246#endif
247 247
248#define WLAN_LOG_ERROR(x,args...) printk(KERN_ERR "%s: " x , __FUNCTION__ , ##args); 248#define WLAN_LOG_ERROR(x,args...) printk(KERN_ERR "%s: " x , __func__ , ##args);
249 249
250#define WLAN_LOG_WARNING(x,args...) printk(KERN_WARNING "%s: " x , __FUNCTION__ , ##args); 250#define WLAN_LOG_WARNING(x,args...) printk(KERN_WARNING "%s: " x , __func__ , ##args);
251 251
252#define WLAN_LOG_NOTICE(x,args...) printk(KERN_NOTICE "%s: " x , __FUNCTION__ , ##args); 252#define WLAN_LOG_NOTICE(x,args...) printk(KERN_NOTICE "%s: " x , __func__ , ##args);
253 253
254#define WLAN_LOG_INFO(args... ) printk(KERN_INFO args) 254#define WLAN_LOG_INFO(args... ) printk(KERN_INFO args)
255 255
@@ -265,7 +265,7 @@ typedef int64_t INT64;
265 #define DBFENTER { if ( WLAN_DBVAR >= 5 ){ WLAN_LOG_DEBUG(3,"---->\n"); } } 265 #define DBFENTER { if ( WLAN_DBVAR >= 5 ){ WLAN_LOG_DEBUG(3,"---->\n"); } }
266 #define DBFEXIT { if ( WLAN_DBVAR >= 5 ){ WLAN_LOG_DEBUG(3,"<----\n"); } } 266 #define DBFEXIT { if ( WLAN_DBVAR >= 5 ){ WLAN_LOG_DEBUG(3,"<----\n"); } }
267 267
268 #define WLAN_LOG_DEBUG(l,x,args...) if ( WLAN_DBVAR >= (l)) printk(KERN_DEBUG "%s(%lu): " x , __FUNCTION__, (preempt_count() & PREEMPT_MASK), ##args ); 268 #define WLAN_LOG_DEBUG(l,x,args...) if ( WLAN_DBVAR >= (l)) printk(KERN_DEBUG "%s(%lu): " x , __func__, (preempt_count() & PREEMPT_MASK), ##args );
269#else 269#else
270 #define WLAN_ASSERT(c) 270 #define WLAN_ASSERT(c)
271 #define WLAN_HEX_DUMP( l, s, p, n) 271 #define WLAN_HEX_DUMP( l, s, p, n)