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-rw-r--r--arch/Kconfig14
-rw-r--r--arch/x86/oprofile/op_model_amd.c31
2 files changed, 1 insertions, 44 deletions
diff --git a/arch/Kconfig b/arch/Kconfig
index d67787241813..06a13729c8df 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -15,20 +15,6 @@ config OPROFILE
15 15
16 If unsure, say N. 16 If unsure, say N.
17 17
18config OPROFILE_IBS
19 bool "OProfile AMD IBS support (EXPERIMENTAL)"
20 default n
21 depends on OPROFILE && SMP && X86
22 help
23 Instruction-Based Sampling (IBS) is a new profiling
24 technique that provides rich, precise program performance
25 information. IBS is introduced by AMD Family10h processors
26 (AMD Opteron Quad-Core processor "Barcelona") to overcome
27 the limitations of conventional performance counter
28 sampling.
29
30 If unsure, say N.
31
32config OPROFILE_EVENT_MULTIPLEX 18config OPROFILE_EVENT_MULTIPLEX
33 bool "OProfile multiplexing support (EXPERIMENTAL)" 19 bool "OProfile multiplexing support (EXPERIMENTAL)"
34 default n 20 default n
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index 39686c29f03a..2b9c68d868ed 100644
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -22,6 +22,7 @@
22#include <asm/ptrace.h> 22#include <asm/ptrace.h>
23#include <asm/msr.h> 23#include <asm/msr.h>
24#include <asm/nmi.h> 24#include <asm/nmi.h>
25#include <asm/apic.h>
25 26
26#include "op_x86_model.h" 27#include "op_x86_model.h"
27#include "op_counter.h" 28#include "op_counter.h"
@@ -43,8 +44,6 @@
43 44
44static unsigned long reset_value[NUM_VIRT_COUNTERS]; 45static unsigned long reset_value[NUM_VIRT_COUNTERS];
45 46
46#ifdef CONFIG_OPROFILE_IBS
47
48/* IbsFetchCtl bits/masks */ 47/* IbsFetchCtl bits/masks */
49#define IBS_FETCH_RAND_EN (1ULL<<57) 48#define IBS_FETCH_RAND_EN (1ULL<<57)
50#define IBS_FETCH_VAL (1ULL<<49) 49#define IBS_FETCH_VAL (1ULL<<49)
@@ -72,8 +71,6 @@ struct op_ibs_config {
72 71
73static struct op_ibs_config ibs_config; 72static struct op_ibs_config ibs_config;
74 73
75#endif
76
77#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX 74#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
78 75
79static void op_mux_fill_in_addresses(struct op_msrs * const msrs) 76static void op_mux_fill_in_addresses(struct op_msrs * const msrs)
@@ -185,8 +182,6 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
185 } 182 }
186} 183}
187 184
188#ifdef CONFIG_OPROFILE_IBS
189
190static inline void 185static inline void
191op_amd_handle_ibs(struct pt_regs * const regs, 186op_amd_handle_ibs(struct pt_regs * const regs,
192 struct op_msrs const * const msrs) 187 struct op_msrs const * const msrs)
@@ -272,15 +267,6 @@ static void op_amd_stop_ibs(void)
272 wrmsrl(MSR_AMD64_IBSOPCTL, 0); 267 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
273} 268}
274 269
275#else
276
277static inline void op_amd_handle_ibs(struct pt_regs * const regs,
278 struct op_msrs const * const msrs) { }
279static inline void op_amd_start_ibs(void) { }
280static inline void op_amd_stop_ibs(void) { }
281
282#endif
283
284static int op_amd_check_ctrs(struct pt_regs * const regs, 270static int op_amd_check_ctrs(struct pt_regs * const regs,
285 struct op_msrs const * const msrs) 271 struct op_msrs const * const msrs)
286{ 272{
@@ -355,8 +341,6 @@ static void op_amd_shutdown(struct op_msrs const * const msrs)
355 } 341 }
356} 342}
357 343
358#ifdef CONFIG_OPROFILE_IBS
359
360static u8 ibs_eilvt_off; 344static u8 ibs_eilvt_off;
361 345
362static inline void apic_init_ibs_nmi_per_cpu(void *arg) 346static inline void apic_init_ibs_nmi_per_cpu(void *arg)
@@ -507,19 +491,6 @@ static void op_amd_exit(void)
507 ibs_exit(); 491 ibs_exit();
508} 492}
509 493
510#else
511
512/* no IBS support */
513
514static int op_amd_init(struct oprofile_operations *ops)
515{
516 return 0;
517}
518
519static void op_amd_exit(void) {}
520
521#endif /* CONFIG_OPROFILE_IBS */
522
523struct op_x86_model_spec op_amd_spec = { 494struct op_x86_model_spec op_amd_spec = {
524 .num_counters = NUM_COUNTERS, 495 .num_counters = NUM_COUNTERS,
525 .num_controls = NUM_CONTROLS, 496 .num_controls = NUM_CONTROLS,