diff options
| -rw-r--r-- | drivers/net/wireless/b43/nphy.h | 210 |
1 files changed, 210 insertions, 0 deletions
diff --git a/drivers/net/wireless/b43/nphy.h b/drivers/net/wireless/b43/nphy.h index 11be7ff0ce0b..71446dc7420d 100644 --- a/drivers/net/wireless/b43/nphy.h +++ b/drivers/net/wireless/b43/nphy.h | |||
| @@ -699,6 +699,216 @@ | |||
| 699 | #define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0 | 699 | #define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0 |
| 700 | 700 | ||
| 701 | 701 | ||
| 702 | |||
| 703 | /* Broadcom 2055 radio registers */ | ||
| 704 | |||
| 705 | #define B2055_GEN_SPARE 0x00 /* GEN spare */ | ||
| 706 | #define B2055_SP_PINPD 0x02 /* SP PIN PD */ | ||
| 707 | #define B2055_C1_SP_RSSI 0x03 /* SP RSSI Core 1 */ | ||
| 708 | #define B2055_C1_SP_PDMISC 0x04 /* SP PD MISC Core 1 */ | ||
| 709 | #define B2055_C2_SP_RSSI 0x05 /* SP RSSI Core 2 */ | ||
| 710 | #define B2055_C2_SP_PDMISC 0x06 /* SP PD MISC Core 2 */ | ||
| 711 | #define B2055_C1_SP_RXGC1 0x07 /* SP RX GC1 Core 1 */ | ||
| 712 | #define B2055_C1_SP_RXGC2 0x08 /* SP RX GC2 Core 1 */ | ||
| 713 | #define B2055_C2_SP_RXGC1 0x09 /* SP RX GC1 Core 2 */ | ||
| 714 | #define B2055_C2_SP_RXGC2 0x0A /* SP RX GC2 Core 2 */ | ||
| 715 | #define B2055_C1_SP_LPFBWSEL 0x0B /* SP LPF BW select Core 1 */ | ||
| 716 | #define B2055_C2_SP_LPFBWSEL 0x0C /* SP LPF BW select Core 2 */ | ||
| 717 | #define B2055_C1_SP_TXGC1 0x0D /* SP TX GC1 Core 1 */ | ||
| 718 | #define B2055_C1_SP_TXGC2 0x0E /* SP TX GC2 Core 1 */ | ||
| 719 | #define B2055_C2_SP_TXGC1 0x0F /* SP TX GC1 Core 2 */ | ||
| 720 | #define B2055_C2_SP_TXGC2 0x10 /* SP TX GC2 Core 2 */ | ||
| 721 | #define B2055_MASTER1 0x11 /* Master control 1 */ | ||
| 722 | #define B2055_MASTER2 0x12 /* Master control 2 */ | ||
| 723 | #define B2055_PD_LGEN 0x13 /* PD LGEN */ | ||
| 724 | #define B2055_PD_PLLTS 0x14 /* PD PLL TS */ | ||
| 725 | #define B2055_C1_PD_LGBUF 0x15 /* PD Core 1 LGBUF */ | ||
| 726 | #define B2055_C1_PD_TX 0x16 /* PD Core 1 TX */ | ||
| 727 | #define B2055_C1_PD_RXTX 0x17 /* PD Core 1 RXTX */ | ||
| 728 | #define B2055_C1_PD_RSSIMISC 0x18 /* PD Core 1 RSSI MISC */ | ||
| 729 | #define B2055_C2_PD_LGBUF 0x19 /* PD Core 2 LGBUF */ | ||
| 730 | #define B2055_C2_PD_TX 0x1A /* PD Core 2 TX */ | ||
| 731 | #define B2055_C2_PD_RXTX 0x1B /* PD Core 2 RXTX */ | ||
| 732 | #define B2055_C2_PD_RSSIMISC 0x1C /* PD Core 2 RSSI MISC */ | ||
| 733 | #define B2055_PWRDET_LGEN 0x1D /* PWRDET LGEN */ | ||
| 734 | #define B2055_C1_PWRDET_LGBUF 0x1E /* PWRDET LGBUF Core 1 */ | ||
| 735 | #define B2055_C1_PWRDET_RXTX 0x1F /* PWRDET RXTX Core 1 */ | ||
| 736 | #define B2055_C2_PWRDET_LGBUF 0x20 /* PWRDET LGBUF Core 2 */ | ||
| 737 | #define B2055_C2_PWRDET_RXTX 0x21 /* PWRDET RXTX Core 2 */ | ||
| 738 | #define B2055_RRCCAL_CS 0x22 /* RRCCAL Control spare */ | ||
| 739 | #define B2055_RRCCAL_NOPTSEL 0x23 /* RRCCAL N OPT SEL */ | ||
| 740 | #define B2055_CAL_MISC 0x24 /* CAL MISC */ | ||
| 741 | #define B2055_CAL_COUT 0x25 /* CAL Counter out */ | ||
| 742 | #define B2055_CAL_COUT2 0x26 /* CAL Counter out 2 */ | ||
| 743 | #define B2055_CAL_CVARCTL 0x27 /* CAL CVAR Control */ | ||
| 744 | #define B2055_CAL_RVARCTL 0x28 /* CAL RVAR Control */ | ||
| 745 | #define B2055_CAL_LPOCTL 0x29 /* CAL LPO Control */ | ||
| 746 | #define B2055_CAL_TS 0x2A /* CAL TS */ | ||
| 747 | #define B2055_CAL_RCCALRTS 0x2B /* CAL RCCAL READ TS */ | ||
| 748 | #define B2055_CAL_RCALRTS 0x2C /* CAL RCAL READ TS */ | ||
| 749 | #define B2055_PADDRV 0x2D /* PAD driver */ | ||
| 750 | #define B2055_XOCTL1 0x2E /* XO Control 1 */ | ||
| 751 | #define B2055_XOCTL2 0x2F /* XO Control 2 */ | ||
| 752 | #define B2055_XOREGUL 0x30 /* XO Regulator */ | ||
| 753 | #define B2055_XOMISC 0x31 /* XO misc */ | ||
| 754 | #define B2055_PLL_LFC1 0x32 /* PLL LF C1 */ | ||
| 755 | #define B2055_PLL_CALVTH 0x33 /* PLL CAL VTH */ | ||
| 756 | #define B2055_PLL_LFC2 0x34 /* PLL LF C2 */ | ||
| 757 | #define B2055_PLL_REF 0x35 /* PLL reference */ | ||
| 758 | #define B2055_PLL_LFR1 0x36 /* PLL LF R1 */ | ||
| 759 | #define B2055_PLL_PFDCP 0x37 /* PLL PFD CP */ | ||
| 760 | #define B2055_PLL_IDAC_CPOPAMP 0x38 /* PLL IDAC CPOPAMP */ | ||
| 761 | #define B2055_PLL_CPREG 0x39 /* PLL CP Regulator */ | ||
| 762 | #define B2055_PLL_RCAL 0x3A /* PLL RCAL */ | ||
| 763 | #define B2055_RF_PLLMOD0 0x3B /* RF PLL MOD0 */ | ||
| 764 | #define B2055_RF_PLLMOD1 0x3C /* RF PLL MOD1 */ | ||
| 765 | #define B2055_RF_MMDIDAC1 0x3D /* RF MMD IDAC 1 */ | ||
| 766 | #define B2055_RF_MMDIDAC0 0x3E /* RF MMD IDAC 0 */ | ||
| 767 | #define B2055_RF_MMDSP 0x3F /* RF MMD spare */ | ||
| 768 | #define B2055_VCO_CAL1 0x40 /* VCO cal 1 */ | ||
| 769 | #define B2055_VCO_CAL2 0x41 /* VCO cal 2 */ | ||
| 770 | #define B2055_VCO_CAL3 0x42 /* VCO cal 3 */ | ||
| 771 | #define B2055_VCO_CAL4 0x43 /* VCO cal 4 */ | ||
| 772 | #define B2055_VCO_CAL5 0x44 /* VCO cal 5 */ | ||
| 773 | #define B2055_VCO_CAL6 0x45 /* VCO cal 6 */ | ||
| 774 | #define B2055_VCO_CAL7 0x46 /* VCO cal 7 */ | ||
| 775 | #define B2055_VCO_CAL8 0x47 /* VCO cal 8 */ | ||
| 776 | #define B2055_VCO_CAL9 0x48 /* VCO cal 9 */ | ||
| 777 | #define B2055_VCO_CAL10 0x49 /* VCO cal 10 */ | ||
| 778 | #define B2055_VCO_CAL11 0x4A /* VCO cal 11 */ | ||
| 779 | #define B2055_VCO_CAL12 0x4B /* VCO cal 12 */ | ||
| 780 | #define B2055_VCO_CAL13 0x4C /* VCO cal 13 */ | ||
| 781 | #define B2055_VCO_CAL14 0x4D /* VCO cal 14 */ | ||
| 782 | #define B2055_VCO_CAL15 0x4E /* VCO cal 15 */ | ||
| 783 | #define B2055_VCO_CAL16 0x4F /* VCO cal 16 */ | ||
| 784 | #define B2055_VCO_KVCO 0x50 /* VCO KVCO */ | ||
| 785 | #define B2055_VCO_CAPTAIL 0x51 /* VCO CAP TAIL */ | ||
| 786 | #define B2055_VCO_IDACVCO 0x52 /* VCO IDAC VCO */ | ||
| 787 | #define B2055_VCO_REG 0x53 /* VCO Regulator */ | ||
| 788 | #define B2055_PLL_RFVTH 0x54 /* PLL RF VTH */ | ||
| 789 | #define B2055_LGBUF_CENBUF 0x55 /* LGBUF CEN BUF */ | ||
| 790 | #define B2055_LGEN_TUNE1 0x56 /* LGEN tune 1 */ | ||
| 791 | #define B2055_LGEN_TUNE2 0x57 /* LGEN tune 2 */ | ||
| 792 | #define B2055_LGEN_IDAC1 0x58 /* LGEN IDAC 1 */ | ||
| 793 | #define B2055_LGEN_IDAC2 0x59 /* LGEN IDAC 2 */ | ||
| 794 | #define B2055_LGEN_BIASC 0x5A /* LGEN BIAS counter */ | ||
| 795 | #define B2055_LGEN_BIASIDAC 0x5B /* LGEN BIAS IDAC */ | ||
| 796 | #define B2055_LGEN_RCAL 0x5C /* LGEN RCAL */ | ||
| 797 | #define B2055_LGEN_DIV 0x5D /* LGEN div */ | ||
| 798 | #define B2055_LGEN_SPARE2 0x5E /* LGEN spare 2 */ | ||
| 799 | #define B2055_C1_LGBUF_ATUNE 0x5F /* Core 1 LGBUF A tune */ | ||
| 800 | #define B2055_C1_LGBUF_GTUNE 0x60 /* Core 1 LGBUF G tune */ | ||
| 801 | #define B2055_C1_LGBUF_DIV 0x61 /* Core 1 LGBUF div */ | ||
| 802 | #define B2055_C1_LGBUF_AIDAC 0x62 /* Core 1 LGBUF A IDAC */ | ||
| 803 | #define B2055_C1_LGBUF_GIDAC 0x63 /* Core 1 LGBUF G IDAC */ | ||
| 804 | #define B2055_C1_LGBUF_IDACFO 0x64 /* Core 1 LGBUF IDAC filter override */ | ||
| 805 | #define B2055_C1_LGBUF_SPARE 0x65 /* Core 1 LGBUF spare */ | ||
| 806 | #define B2055_C1_RX_RFSPC1 0x66 /* Core 1 RX RF SPC1 */ | ||
| 807 | #define B2055_C1_RX_RFR1 0x67 /* Core 1 RX RF reg 1 */ | ||
| 808 | #define B2055_C1_RX_RFR2 0x68 /* Core 1 RX RF reg 2 */ | ||
| 809 | #define B2055_C1_RX_RFRCAL 0x69 /* Core 1 RX RF RCAL */ | ||
| 810 | #define B2055_C1_RX_BB_BLCMP 0x6A /* Core 1 RX Baseband BUFI LPF CMP */ | ||
| 811 | #define B2055_C1_RX_BB_LPF 0x6B /* Core 1 RX Baseband LPF */ | ||
| 812 | #define B2055_C1_RX_BB_MIDACHP 0x6C /* Core 1 RX Baseband MIDAC High-pass */ | ||
| 813 | #define B2055_C1_RX_BB_VGA1IDAC 0x6D /* Core 1 RX Baseband VGA1 IDAC */ | ||
| 814 | #define B2055_C1_RX_BB_VGA2IDAC 0x6E /* Core 1 RX Baseband VGA2 IDAC */ | ||
| 815 | #define B2055_C1_RX_BB_VGA3IDAC 0x6F /* Core 1 RX Baseband VGA3 IDAC */ | ||
| 816 | #define B2055_C1_RX_BB_BUFOCTL 0x70 /* Core 1 RX Baseband BUFO Control */ | ||
| 817 | #define B2055_C1_RX_BB_RCCALCTL 0x71 /* Core 1 RX Baseband RCCAL Control */ | ||
| 818 | #define B2055_C1_RX_BB_RSSICTL1 0x72 /* Core 1 RX Baseband RSSI Control 1 */ | ||
| 819 | #define B2055_C1_RX_BB_RSSICTL2 0x73 /* Core 1 RX Baseband RSSI Control 2 */ | ||
| 820 | #define B2055_C1_RX_BB_RSSICTL3 0x74 /* Core 1 RX Baseband RSSI Control 3 */ | ||
| 821 | #define B2055_C1_RX_BB_RSSICTL4 0x75 /* Core 1 RX Baseband RSSI Control 4 */ | ||
| 822 | #define B2055_C1_RX_BB_RSSICTL5 0x76 /* Core 1 RX Baseband RSSI Control 5 */ | ||
| 823 | #define B2055_C1_RX_BB_REG 0x77 /* Core 1 RX Baseband Regulator */ | ||
| 824 | #define B2055_C1_RX_BB_SPARE1 0x78 /* Core 1 RX Baseband spare 1 */ | ||
| 825 | #define B2055_C1_RX_TXBBRCAL 0x79 /* Core 1 RX TX BB RCAL */ | ||
| 826 | #define B2055_C1_TX_RF_SPGA 0x7A /* Core 1 TX RF SGM PGA */ | ||
| 827 | #define B2055_C1_TX_RF_SPAD 0x7B /* Core 1 TX RF SGM PAD */ | ||
| 828 | #define B2055_C1_TX_RF_CNTPGA1 0x7C /* Core 1 TX RF counter PGA 1 */ | ||
| 829 | #define B2055_C1_TX_RF_CNTPAD1 0x7D /* Core 1 TX RF counter PAD 1 */ | ||
| 830 | #define B2055_C1_TX_RF_PGAIDAC 0x7E /* Core 1 TX RF PGA IDAC */ | ||
| 831 | #define B2055_C1_TX_PGAPADTN 0x7F /* Core 1 TX PGA PAD TN */ | ||
| 832 | #define B2055_C1_TX_PADIDAC1 0x80 /* Core 1 TX PAD IDAC 1 */ | ||
| 833 | #define B2055_C1_TX_PADIDAC2 0x81 /* Core 1 TX PAD IDAC 2 */ | ||
| 834 | #define B2055_C1_TX_MXBGTRIM 0x82 /* Core 1 TX MX B/G TRIM */ | ||
| 835 | #define B2055_C1_TX_RF_RCAL 0x83 /* Core 1 TX RF RCAL */ | ||
| 836 | #define B2055_C1_TX_RF_PADTSSI1 0x84 /* Core 1 TX RF PAD TSSI1 */ | ||
| 837 | #define B2055_C1_TX_RF_PADTSSI2 0x85 /* Core 1 TX RF PAD TSSI2 */ | ||
| 838 | #define B2055_C1_TX_RF_SPARE 0x86 /* Core 1 TX RF spare */ | ||
| 839 | #define B2055_C1_TX_RF_IQCAL1 0x87 /* Core 1 TX RF I/Q CAL 1 */ | ||
| 840 | #define B2055_C1_TX_RF_IQCAL2 0x88 /* Core 1 TX RF I/Q CAL 2 */ | ||
| 841 | #define B2055_C1_TXBB_RCCAL 0x89 /* Core 1 TXBB RC CAL Control */ | ||
| 842 | #define B2055_C1_TXBB_LPF1 0x8A /* Core 1 TXBB LPF 1 */ | ||
| 843 | #define B2055_C1_TX_VOSCNCL 0x8B /* Core 1 TX VOS CNCL */ | ||
| 844 | #define B2055_C1_TX_LPF_MXGMIDAC 0x8C /* Core 1 TX LPF MXGM IDAC */ | ||
| 845 | #define B2055_C1_TX_BB_MXGM 0x8D /* Core 1 TX BB MXGM */ | ||
| 846 | #define B2055_C2_LGBUF_ATUNE 0x8E /* Core 2 LGBUF A tune */ | ||
| 847 | #define B2055_C2_LGBUF_GTUNE 0x8F /* Core 2 LGBUF G tune */ | ||
| 848 | #define B2055_C2_LGBUF_DIV 0x90 /* Core 2 LGBUF div */ | ||
| 849 | #define B2055_C2_LGBUF_AIDAC 0x91 /* Core 2 LGBUF A IDAC */ | ||
| 850 | #define B2055_C2_LGBUF_GIDAC 0x92 /* Core 2 LGBUF G IDAC */ | ||
| 851 | #define B2055_C2_LGBUF_IDACFO 0x93 /* Core 2 LGBUF IDAC filter override */ | ||
| 852 | #define B2055_C2_LGBUF_SPARE 0x94 /* Core 2 LGBUF spare */ | ||
| 853 | #define B2055_C2_RX_RFSPC1 0x95 /* Core 2 RX RF SPC1 */ | ||
| 854 | #define B2055_C2_RX_RFR1 0x96 /* Core 2 RX RF reg 1 */ | ||
| 855 | #define B2055_C2_RX_RFR2 0x97 /* Core 2 RX RF reg 2 */ | ||
| 856 | #define B2055_C2_RX_RFRCAL 0x98 /* Core 2 RX RF RCAL */ | ||
| 857 | #define B2055_C2_RX_BB_BLCMP 0x99 /* Core 2 RX Baseband BUFI LPF CMP */ | ||
| 858 | #define B2055_C2_RX_BB_LPF 0x9A /* Core 2 RX Baseband LPF */ | ||
| 859 | #define B2055_C2_RX_BB_MIDACHP 0x9B /* Core 2 RX Baseband MIDAC High-pass */ | ||
| 860 | #define B2055_C2_RX_BB_VGA1IDAC 0x9C /* Core 2 RX Baseband VGA1 IDAC */ | ||
| 861 | #define B2055_C2_RX_BB_VGA2IDAC 0x9D /* Core 2 RX Baseband VGA2 IDAC */ | ||
| 862 | #define B2055_C2_RX_BB_VGA3IDAC 0x9E /* Core 2 RX Baseband VGA3 IDAC */ | ||
| 863 | #define B2055_C2_RX_BB_BUFOCTL 0x9F /* Core 2 RX Baseband BUFO Control */ | ||
| 864 | #define B2055_C2_RX_BB_RCCALCTL 0xA0 /* Core 2 RX Baseband RCCAL Control */ | ||
| 865 | #define B2055_C2_RX_BB_RSSICTL1 0xA1 /* Core 2 RX Baseband RSSI Control 1 */ | ||
| 866 | #define B2055_C2_RX_BB_RSSICTL2 0xA2 /* Core 2 RX Baseband RSSI Control 2 */ | ||
| 867 | #define B2055_C2_RX_BB_RSSICTL3 0xA3 /* Core 2 RX Baseband RSSI Control 3 */ | ||
| 868 | #define B2055_C2_RX_BB_RSSICTL4 0xA4 /* Core 2 RX Baseband RSSI Control 4 */ | ||
| 869 | #define B2055_C2_RX_BB_RSSICTL5 0xA5 /* Core 2 RX Baseband RSSI Control 5 */ | ||
| 870 | #define B2055_C2_RX_BB_REG 0xA6 /* Core 2 RX Baseband Regulator */ | ||
| 871 | #define B2055_C2_RX_BB_SPARE1 0xA7 /* Core 2 RX Baseband spare 1 */ | ||
| 872 | #define B2055_C2_RX_TXBBRCAL 0xA8 /* Core 2 RX TX BB RCAL */ | ||
| 873 | #define B2055_C2_TX_RF_SPGA 0xA9 /* Core 2 TX RF SGM PGA */ | ||
| 874 | #define B2055_C2_TX_RF_SPAD 0xAA /* Core 2 TX RF SGM PAD */ | ||
| 875 | #define B2055_C2_TX_RF_CNTPGA1 0xAB /* Core 2 TX RF counter PGA 1 */ | ||
| 876 | #define B2055_C2_TX_RF_CNTPAD1 0xAC /* Core 2 TX RF counter PAD 1 */ | ||
| 877 | #define B2055_C2_TX_RF_PGAIDAC 0xAD /* Core 2 TX RF PGA IDAC */ | ||
| 878 | #define B2055_C2_TX_PGAPADTN 0xAE /* Core 2 TX PGA PAD TN */ | ||
| 879 | #define B2055_C2_TX_PADIDAC1 0xAF /* Core 2 TX PAD IDAC 1 */ | ||
| 880 | #define B2055_C2_TX_PADIDAC2 0xB0 /* Core 2 TX PAD IDAC 2 */ | ||
| 881 | #define B2055_C2_TX_MXBGTRIM 0xB1 /* Core 2 TX MX B/G TRIM */ | ||
| 882 | #define B2055_C2_TX_RF_RCAL 0xB2 /* Core 2 TX RF RCAL */ | ||
| 883 | #define B2055_C2_TX_RF_PADTSSI1 0xB3 /* Core 2 TX RF PAD TSSI1 */ | ||
| 884 | #define B2055_C2_TX_RF_PADTSSI2 0xB4 /* Core 2 TX RF PAD TSSI2 */ | ||
| 885 | #define B2055_C2_TX_RF_SPARE 0xB5 /* Core 2 TX RF spare */ | ||
| 886 | #define B2055_C2_TX_RF_IQCAL1 0xB6 /* Core 2 TX RF I/Q CAL 1 */ | ||
| 887 | #define B2055_C2_TX_RF_IQCAL2 0xB7 /* Core 2 TX RF I/Q CAL 2 */ | ||
| 888 | #define B2055_C2_TXBB_RCCAL 0xB8 /* Core 2 TXBB RC CAL Control */ | ||
| 889 | #define B2055_C2_TXBB_LPF1 0xB9 /* Core 2 TXBB LPF 1 */ | ||
| 890 | #define B2055_C2_TX_VOSCNCL 0xBA /* Core 2 TX VOS CNCL */ | ||
| 891 | #define B2055_C2_TX_LPF_MXGMIDAC 0xBB /* Core 2 TX LPF MXGM IDAC */ | ||
| 892 | #define B2055_C2_TX_BB_MXGM 0xBC /* Core 2 TX BB MXGM */ | ||
| 893 | #define B2055_PRG_GCHP21 0xBD /* PRG GC HPVGA23 21 */ | ||
| 894 | #define B2055_PRG_GCHP22 0xBE /* PRG GC HPVGA23 22 */ | ||
| 895 | #define B2055_PRG_GCHP23 0xBF /* PRG GC HPVGA23 23 */ | ||
| 896 | #define B2055_PRG_GCHP24 0xC0 /* PRG GC HPVGA23 24 */ | ||
| 897 | #define B2055_PRG_GCHP25 0xC1 /* PRG GC HPVGA23 25 */ | ||
| 898 | #define B2055_PRG_GCHP26 0xC2 /* PRG GC HPVGA23 26 */ | ||
| 899 | #define B2055_PRG_GCHP27 0xC3 /* PRG GC HPVGA23 27 */ | ||
| 900 | #define B2055_PRG_GCHP28 0xC4 /* PRG GC HPVGA23 28 */ | ||
| 901 | #define B2055_PRG_GCHP29 0xC5 /* PRG GC HPVGA23 29 */ | ||
| 902 | #define B2055_PRG_GCHP30 0xC6 /* PRG GC HPVGA23 30 */ | ||
| 903 | #define B2055_C1_LNA_GAINBST 0xCD /* Core 1 LNA GAINBST */ | ||
| 904 | #define B2055_C1_B0NB_RSSIVCM 0xD2 /* Core 1 B0 narrow-band RSSI VCM */ | ||
| 905 | #define B2055_C1_GENSPARE2 0xD6 /* Core 1 GEN spare 2 */ | ||
| 906 | #define B2055_C2_LNA_GAINBST 0xD9 /* Core 2 LNA GAINBST */ | ||
| 907 | #define B2055_C2_B0NB_RSSIVCM 0xDE /* Core 2 B0 narrow-band RSSI VCM */ | ||
| 908 | #define B2055_C2_GENSPARE2 0xE2 /* Core 2 GEN spare 2 */ | ||
| 909 | |||
| 910 | |||
| 911 | |||
| 702 | struct b43_wldev; | 912 | struct b43_wldev; |
| 703 | 913 | ||
| 704 | int b43_phy_initn(struct b43_wldev *dev); | 914 | int b43_phy_initn(struct b43_wldev *dev); |