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-rw-r--r--drivers/net/bnx2x.h2
-rw-r--r--drivers/net/bnx2x_link.c78
-rw-r--r--drivers/net/bnx2x_main.c14
3 files changed, 51 insertions, 43 deletions
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 3b09ae623359..e15ecfbfc85e 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -924,7 +924,7 @@ struct bnx2x {
924void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 924void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
925void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 925void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
926 u32 len32); 926 u32 len32);
927int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode); 927int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
928 928
929static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 929static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
930 int wait) 930 int wait)
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
index 36fa356c74fa..c9cffa6d47b6 100644
--- a/drivers/net/bnx2x_link.c
+++ b/drivers/net/bnx2x_link.c
@@ -1842,15 +1842,15 @@ static u8 bnx2x_emac_program(struct link_params *params,
1842} 1842}
1843 1843
1844/*****************************************************************************/ 1844/*****************************************************************************/
1845/* External Phy section */ 1845/* External Phy section */
1846/*****************************************************************************/ 1846/*****************************************************************************/
1847static void bnx2x_hw_reset(struct bnx2x *bp) 1847static void bnx2x_hw_reset(struct bnx2x *bp, u8 port)
1848{ 1848{
1849 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 1849 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1850 MISC_REGISTERS_GPIO_OUTPUT_LOW); 1850 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
1851 msleep(1); 1851 msleep(1);
1852 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 1852 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1853 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1853 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
1854} 1854}
1855 1855
1856static void bnx2x_ext_phy_reset(struct link_params *params, 1856static void bnx2x_ext_phy_reset(struct link_params *params,
@@ -1879,10 +1879,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
1879 1879
1880 /* Restore normal power mode*/ 1880 /* Restore normal power mode*/
1881 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 1881 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1882 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1882 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1883 params->port);
1883 1884
1884 /* HW reset */ 1885 /* HW reset */
1885 bnx2x_hw_reset(bp); 1886 bnx2x_hw_reset(bp, params->port);
1886 1887
1887 bnx2x_cl45_write(bp, params->port, 1888 bnx2x_cl45_write(bp, params->port,
1888 ext_phy_type, 1889 ext_phy_type,
@@ -1894,7 +1895,8 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
1894 /* Unset Low Power Mode and SW reset */ 1895 /* Unset Low Power Mode and SW reset */
1895 /* Restore normal power mode*/ 1896 /* Restore normal power mode*/
1896 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 1897 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1897 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1898 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1899 params->port);
1898 1900
1899 DP(NETIF_MSG_LINK, "XGXS 8072\n"); 1901 DP(NETIF_MSG_LINK, "XGXS 8072\n");
1900 bnx2x_cl45_write(bp, params->port, 1902 bnx2x_cl45_write(bp, params->port,
@@ -1912,19 +1914,14 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
1912 1914
1913 /* Restore normal power mode*/ 1915 /* Restore normal power mode*/
1914 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 1916 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1915 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1917 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1918 params->port);
1916 1919
1917 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 1920 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1918 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1921 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1922 params->port);
1919 1923
1920 DP(NETIF_MSG_LINK, "XGXS 8073\n"); 1924 DP(NETIF_MSG_LINK, "XGXS 8073\n");
1921 bnx2x_cl45_write(bp,
1922 params->port,
1923 ext_phy_type,
1924 ext_phy_addr,
1925 MDIO_PMA_DEVAD,
1926 MDIO_PMA_REG_CTRL,
1927 1<<15);
1928 } 1925 }
1929 break; 1926 break;
1930 1927
@@ -1933,10 +1930,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
1933 1930
1934 /* Restore normal power mode*/ 1931 /* Restore normal power mode*/
1935 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 1932 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1936 MISC_REGISTERS_GPIO_OUTPUT_HIGH); 1933 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1934 params->port);
1937 1935
1938 /* HW reset */ 1936 /* HW reset */
1939 bnx2x_hw_reset(bp); 1937 bnx2x_hw_reset(bp, params->port);
1940 1938
1941 break; 1939 break;
1942 1940
@@ -1959,7 +1957,7 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
1959 1957
1960 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482: 1958 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
1961 DP(NETIF_MSG_LINK, "SerDes 5482\n"); 1959 DP(NETIF_MSG_LINK, "SerDes 5482\n");
1962 bnx2x_hw_reset(bp); 1960 bnx2x_hw_reset(bp, params->port);
1963 break; 1961 break;
1964 1962
1965 default: 1963 default:
@@ -3286,12 +3284,14 @@ static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr,
3286 3284
3287 /* take ext phy out of reset */ 3285 /* take ext phy out of reset */
3288 bnx2x_set_gpio(bp, 3286 bnx2x_set_gpio(bp,
3289 MISC_REGISTERS_GPIO_2, 3287 MISC_REGISTERS_GPIO_2,
3290 MISC_REGISTERS_GPIO_HIGH); 3288 MISC_REGISTERS_GPIO_HIGH,
3289 port);
3291 3290
3292 bnx2x_set_gpio(bp, 3291 bnx2x_set_gpio(bp,
3293 MISC_REGISTERS_GPIO_1, 3292 MISC_REGISTERS_GPIO_1,
3294 MISC_REGISTERS_GPIO_HIGH); 3293 MISC_REGISTERS_GPIO_HIGH,
3294 port);
3295 3295
3296 /* wait for 5ms */ 3296 /* wait for 5ms */
3297 msleep(5); 3297 msleep(5);
@@ -3311,13 +3311,17 @@ static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr,
3311 } 3311 }
3312} 3312}
3313 3313
3314static void bnx2x_turn_off_sf(struct bnx2x *bp) 3314static void bnx2x_turn_off_sf(struct bnx2x *bp, u8 port)
3315{ 3315{
3316 /* put sf to reset */ 3316 /* put sf to reset */
3317 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, MISC_REGISTERS_GPIO_LOW);
3318 bnx2x_set_gpio(bp, 3317 bnx2x_set_gpio(bp,
3319 MISC_REGISTERS_GPIO_2, 3318 MISC_REGISTERS_GPIO_1,
3320 MISC_REGISTERS_GPIO_LOW); 3319 MISC_REGISTERS_GPIO_LOW,
3320 port);
3321 bnx2x_set_gpio(bp,
3322 MISC_REGISTERS_GPIO_2,
3323 MISC_REGISTERS_GPIO_LOW,
3324 port);
3321} 3325}
3322 3326
3323u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, 3327u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
@@ -3371,7 +3375,7 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3371 version[4] = '\0'; 3375 version[4] = '\0';
3372 3376
3373 if (!driver_loaded) 3377 if (!driver_loaded)
3374 bnx2x_turn_off_sf(bp); 3378 bnx2x_turn_off_sf(bp, params->port);
3375 break; 3379 break;
3376 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: 3380 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3377 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 3381 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
@@ -4013,10 +4017,12 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars)
4013 /* HW reset */ 4017 /* HW reset */
4014 4018
4015 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 4019 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4016 MISC_REGISTERS_GPIO_OUTPUT_LOW); 4020 MISC_REGISTERS_GPIO_OUTPUT_LOW,
4021 port);
4017 4022
4018 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 4023 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4019 MISC_REGISTERS_GPIO_OUTPUT_LOW); 4024 MISC_REGISTERS_GPIO_OUTPUT_LOW,
4025 port);
4020 4026
4021 DP(NETIF_MSG_LINK, "reset external PHY\n"); 4027 DP(NETIF_MSG_LINK, "reset external PHY\n");
4022 } else if (ext_phy_type == 4028 } else if (ext_phy_type ==
@@ -4025,7 +4031,8 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars)
4025 "low power mode\n", 4031 "low power mode\n",
4026 port); 4032 port);
4027 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 4033 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4028 MISC_REGISTERS_GPIO_OUTPUT_LOW); 4034 MISC_REGISTERS_GPIO_OUTPUT_LOW,
4035 port);
4029 } 4036 }
4030 } 4037 }
4031 /* reset the SerDes/XGXS */ 4038 /* reset the SerDes/XGXS */
@@ -4271,7 +4278,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
4271 and issuing a reset.*/ 4278 and issuing a reset.*/
4272 4279
4273 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 4280 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4274 MISC_REGISTERS_GPIO_HIGH); 4281 MISC_REGISTERS_GPIO_HIGH, port);
4275 4282
4276 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr); 4283 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
4277 4284
@@ -4503,7 +4510,8 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
4503 } 4510 }
4504 4511
4505 /* DSP Remove Download Mode */ 4512 /* DSP Remove Download Mode */
4506 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, MISC_REGISTERS_GPIO_LOW); 4513 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4514 MISC_REGISTERS_GPIO_LOW, port);
4507 4515
4508 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr); 4516 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
4509 4517
@@ -4511,7 +4519,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
4511 for (cnt = 0; cnt < 100; cnt++) 4519 for (cnt = 0; cnt < 100; cnt++)
4512 msleep(5); 4520 msleep(5);
4513 4521
4514 bnx2x_hw_reset(bp); 4522 bnx2x_hw_reset(bp, port);
4515 4523
4516 for (cnt = 0; cnt < 100; cnt++) 4524 for (cnt = 0; cnt < 100; cnt++)
4517 msleep(5); 4525 msleep(5);
@@ -4586,7 +4594,7 @@ u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
4586 rc = bnx2x_sfx7101_flash_download(bp, port, ext_phy_addr, 4594 rc = bnx2x_sfx7101_flash_download(bp, port, ext_phy_addr,
4587 data, size); 4595 data, size);
4588 if (!driver_loaded) 4596 if (!driver_loaded)
4589 bnx2x_turn_off_sf(bp); 4597 bnx2x_turn_off_sf(bp, port);
4590 break; 4598 break;
4591 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 4599 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
4592 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 4600 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index a37549b5bc1c..85ea799a0539 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -1788,11 +1788,11 @@ static void bnx2x_release_phy_lock(struct bnx2x *bp)
1788 mutex_unlock(&bp->port.phy_mutex); 1788 mutex_unlock(&bp->port.phy_mutex);
1789} 1789}
1790 1790
1791int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode) 1791int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1792{ 1792{
1793 /* The GPIO should be swapped if swap register is set and active */ 1793 /* The GPIO should be swapped if swap register is set and active */
1794 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1794 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1795 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ BP_PORT(bp); 1795 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1796 int gpio_shift = gpio_num + 1796 int gpio_shift = gpio_num +
1797 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1797 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1798 u32 gpio_mask = (1 << gpio_shift); 1798 u32 gpio_mask = (1 << gpio_shift);
@@ -1824,7 +1824,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
1824 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 1824 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1825 break; 1825 break;
1826 1826
1827 case MISC_REGISTERS_GPIO_INPUT_HI_Z : 1827 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1828 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", 1828 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1829 gpio_num, gpio_shift); 1829 gpio_num, gpio_shift);
1830 /* set FLOAT */ 1830 /* set FLOAT */
@@ -2553,12 +2553,12 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2553 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G: 2553 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
2554 /* Fan failure attention */ 2554 /* Fan failure attention */
2555 2555
2556 /* The PHY reset is controled by GPIO 1 */ 2556 /* The PHY reset is controlled by GPIO 1 */
2557 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 2557 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2558 MISC_REGISTERS_GPIO_OUTPUT_LOW); 2558 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2559 /* Low power mode is controled by GPIO 2 */ 2559 /* Low power mode is controlled by GPIO 2 */
2560 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 2560 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2561 MISC_REGISTERS_GPIO_OUTPUT_LOW); 2561 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2562 /* mark the failure */ 2562 /* mark the failure */
2563 bp->link_params.ext_phy_config &= 2563 bp->link_params.ext_phy_config &=
2564 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 2564 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 13:46:48 -0500