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-rw-r--r--drivers/char/Kconfig4
-rw-r--r--drivers/char/Makefile1
-rw-r--r--drivers/char/vr41xx_giu.c743
-rw-r--r--include/asm-mips/vr41xx/giu.h69
-rw-r--r--include/asm-mips/vr41xx/vr41xx.h35
5 files changed, 817 insertions, 35 deletions
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 5ed6515ae01f..7ccf871d3c9d 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -929,6 +929,10 @@ config SCx200_GPIO
929 929
930 If compiled as a module, it will be called scx200_gpio. 930 If compiled as a module, it will be called scx200_gpio.
931 931
932config GPIO_VR41XX
933 tristate "NEC VR4100 series General-purpose I/O Unit support"
934 depends on CPU_VR41XX
935
932config RAW_DRIVER 936config RAW_DRIVER
933 tristate "RAW driver (/dev/raw/rawN) (OBSOLETE)" 937 tristate "RAW driver (/dev/raw/rawN) (OBSOLETE)"
934 help 938 help
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index e3f5c32aac55..1aff819f3832 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -80,6 +80,7 @@ obj-$(CONFIG_PPDEV) += ppdev.o
80obj-$(CONFIG_NWBUTTON) += nwbutton.o 80obj-$(CONFIG_NWBUTTON) += nwbutton.o
81obj-$(CONFIG_NWFLASH) += nwflash.o 81obj-$(CONFIG_NWFLASH) += nwflash.o
82obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o 82obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o
83obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o
83obj-$(CONFIG_TANBAC_TB0219) += tb0219.o 84obj-$(CONFIG_TANBAC_TB0219) += tb0219.o
84 85
85obj-$(CONFIG_WATCHDOG) += watchdog/ 86obj-$(CONFIG_WATCHDOG) += watchdog/
diff --git a/drivers/char/vr41xx_giu.c b/drivers/char/vr41xx_giu.c
new file mode 100644
index 000000000000..683278bc5241
--- /dev/null
+++ b/drivers/char/vr41xx_giu.c
@@ -0,0 +1,743 @@
1/*
2 * Driver for NEC VR4100 series General-purpose I/O Unit.
3 *
4 * Copyright (C) 2002 MontaVista Software Inc.
5 * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6 * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22#include <linux/device.h>
23#include <linux/errno.h>
24#include <linux/fs.h>
25#include <linux/init.h>
26#include <linux/irq.h>
27#include <linux/interrupt.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <linux/types.h>
32
33#include <asm/cpu.h>
34#include <asm/io.h>
35#include <asm/vr41xx/giu.h>
36#include <asm/vr41xx/vr41xx.h>
37
38MODULE_AUTHOR("Yoichi Yuasa <yuasa@hh.iij4u.or.jp>");
39MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver");
40MODULE_LICENSE("GPL");
41
42static int major; /* default is dynamic major device number */
43module_param(major, int, 0);
44MODULE_PARM_DESC(major, "Major device number");
45
46#define GIU_TYPE1_START 0x0b000100UL
47#define GIU_TYPE1_SIZE 0x20UL
48
49#define GIU_TYPE2_START 0x0f000140UL
50#define GIU_TYPE2_SIZE 0x20UL
51
52#define GIU_TYPE3_START 0x0f000140UL
53#define GIU_TYPE3_SIZE 0x28UL
54
55#define GIU_PULLUPDOWN_START 0x0b0002e0UL
56#define GIU_PULLUPDOWN_SIZE 0x04UL
57
58#define GIUIOSELL 0x00
59#define GIUIOSELH 0x02
60#define GIUPIODL 0x04
61#define GIUPIODH 0x06
62#define GIUINTSTATL 0x08
63#define GIUINTSTATH 0x0a
64#define GIUINTENL 0x0c
65#define GIUINTENH 0x0e
66#define GIUINTTYPL 0x10
67#define GIUINTTYPH 0x12
68#define GIUINTALSELL 0x14
69#define GIUINTALSELH 0x16
70#define GIUINTHTSELL 0x18
71#define GIUINTHTSELH 0x1a
72#define GIUPODATL 0x1c
73#define GIUPODATEN 0x1c
74#define GIUPODATH 0x1e
75 #define PIOEN0 0x0100
76 #define PIOEN1 0x0200
77#define GIUPODAT 0x1e
78#define GIUFEDGEINHL 0x20
79#define GIUFEDGEINHH 0x22
80#define GIUREDGEINHL 0x24
81#define GIUREDGEINHH 0x26
82
83#define GIUUSEUPDN 0x1e0
84#define GIUTERMUPDN 0x1e2
85
86#define GPIO_HAS_PULLUPDOWN_IO 0x0001
87#define GPIO_HAS_OUTPUT_ENABLE 0x0002
88#define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100
89
90static spinlock_t giu_lock;
91static struct resource *giu_resource1;
92static struct resource *giu_resource2;
93static unsigned long giu_flags;
94static unsigned int giu_nr_pins;
95
96static void __iomem *giu_base;
97
98#define giu_read(offset) readw(giu_base + (offset))
99#define giu_write(offset, value) writew((value), giu_base + (offset))
100
101#define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE)
102#define GIUINT_HIGH_OFFSET 16
103#define GIUINT_HIGH_MAX 32
104
105static inline uint16_t giu_set(uint16_t offset, uint16_t set)
106{
107 uint16_t data;
108
109 data = giu_read(offset);
110 data |= set;
111 giu_write(offset, data);
112
113 return data;
114}
115
116static inline uint16_t giu_clear(uint16_t offset, uint16_t clear)
117{
118 uint16_t data;
119
120 data = giu_read(offset);
121 data &= ~clear;
122 giu_write(offset, data);
123
124 return data;
125}
126
127static unsigned int startup_giuint_low_irq(unsigned int irq)
128{
129 unsigned int pin;
130
131 pin = GPIO_PIN_OF_IRQ(irq);
132 giu_write(GIUINTSTATL, 1 << pin);
133 giu_set(GIUINTENL, 1 << pin);
134
135 return 0;
136}
137
138static void shutdown_giuint_low_irq(unsigned int irq)
139{
140 giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
141}
142
143static void enable_giuint_low_irq(unsigned int irq)
144{
145 giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
146}
147
148#define disable_giuint_low_irq shutdown_giuint_low_irq
149
150static void ack_giuint_low_irq(unsigned int irq)
151{
152 unsigned int pin;
153
154 pin = GPIO_PIN_OF_IRQ(irq);
155 giu_clear(GIUINTENL, 1 << pin);
156 giu_write(GIUINTSTATL, 1 << pin);
157}
158
159static void end_giuint_low_irq(unsigned int irq)
160{
161 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
162 giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
163}
164
165static struct hw_interrupt_type giuint_low_irq_type = {
166 .typename = "GIUINTL",
167 .startup = startup_giuint_low_irq,
168 .shutdown = shutdown_giuint_low_irq,
169 .enable = enable_giuint_low_irq,
170 .disable = disable_giuint_low_irq,
171 .ack = ack_giuint_low_irq,
172 .end = end_giuint_low_irq,
173};
174
175static unsigned int startup_giuint_high_irq(unsigned int irq)
176{
177 unsigned int pin;
178
179 pin = GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET;
180 giu_write(GIUINTSTATH, 1 << pin);
181 giu_set(GIUINTENH, 1 << pin);
182
183 return 0;
184}
185
186static void shutdown_giuint_high_irq(unsigned int irq)
187{
188 giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
189}
190
191static void enable_giuint_high_irq(unsigned int irq)
192{
193 giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
194}
195
196#define disable_giuint_high_irq shutdown_giuint_high_irq
197
198static void ack_giuint_high_irq(unsigned int irq)
199{
200 unsigned int pin;
201
202 pin = GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET;
203 giu_clear(GIUINTENH, 1 << pin);
204 giu_write(GIUINTSTATH, 1 << pin);
205}
206
207static void end_giuint_high_irq(unsigned int irq)
208{
209 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
210 giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
211}
212
213static struct hw_interrupt_type giuint_high_irq_type = {
214 .typename = "GIUINTH",
215 .startup = startup_giuint_high_irq,
216 .shutdown = shutdown_giuint_high_irq,
217 .enable = enable_giuint_high_irq,
218 .disable = disable_giuint_high_irq,
219 .ack = ack_giuint_high_irq,
220 .end = end_giuint_high_irq,
221};
222
223static int giu_get_irq(unsigned int irq, struct pt_regs *regs)
224{
225 uint16_t pendl, pendh, maskl, maskh;
226 int i;
227
228 pendl = giu_read(GIUINTSTATL);
229 pendh = giu_read(GIUINTSTATH);
230 maskl = giu_read(GIUINTENL);
231 maskh = giu_read(GIUINTENH);
232
233 maskl &= pendl;
234 maskh &= pendh;
235
236 if (maskl) {
237 for (i = 0; i < 16; i++) {
238 if (maskl & (1 << i))
239 return GIU_IRQ(i);
240 }
241 } else if (maskh) {
242 for (i = 0; i < 16; i++) {
243 if (maskh & (1 << i))
244 return GIU_IRQ(i + GIUINT_HIGH_OFFSET);
245 }
246 }
247
248 printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
249 maskl, pendl, maskh, pendh);
250
251 atomic_inc(&irq_err_count);
252
253 return -EINVAL;
254}
255
256void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_t signal)
257{
258 uint16_t mask;
259
260 if (pin < GIUINT_HIGH_OFFSET) {
261 mask = 1 << pin;
262 if (trigger != IRQ_TRIGGER_LEVEL) {
263 giu_set(GIUINTTYPL, mask);
264 if (signal == IRQ_SIGNAL_HOLD)
265 giu_set(GIUINTHTSELL, mask);
266 else
267 giu_clear(GIUINTHTSELL, mask);
268 if (current_cpu_data.cputype == CPU_VR4133) {
269 switch (trigger) {
270 case IRQ_TRIGGER_EDGE_FALLING:
271 giu_set(GIUFEDGEINHL, mask);
272 giu_clear(GIUREDGEINHL, mask);
273 break;
274 case IRQ_TRIGGER_EDGE_RISING:
275 giu_clear(GIUFEDGEINHL, mask);
276 giu_set(GIUREDGEINHL, mask);
277 break;
278 default:
279 giu_set(GIUFEDGEINHL, mask);
280 giu_set(GIUREDGEINHL, mask);
281 break;
282 }
283 }
284 } else {
285 giu_clear(GIUINTTYPL, mask);
286 giu_clear(GIUINTHTSELL, mask);
287 }
288 giu_write(GIUINTSTATL, mask);
289 } else if (pin < GIUINT_HIGH_MAX) {
290 mask = 1 << (pin - GIUINT_HIGH_OFFSET);
291 if (trigger != IRQ_TRIGGER_LEVEL) {
292 giu_set(GIUINTTYPH, mask);
293 if (signal == IRQ_SIGNAL_HOLD)
294 giu_set(GIUINTHTSELH, mask);
295 else
296 giu_clear(GIUINTHTSELH, mask);
297 if (current_cpu_data.cputype == CPU_VR4133) {
298 switch (trigger) {
299 case IRQ_TRIGGER_EDGE_FALLING:
300 giu_set(GIUFEDGEINHH, mask);
301 giu_clear(GIUREDGEINHH, mask);
302 break;
303 case IRQ_TRIGGER_EDGE_RISING:
304 giu_clear(GIUFEDGEINHH, mask);
305 giu_set(GIUREDGEINHH, mask);
306 break;
307 default:
308 giu_set(GIUFEDGEINHH, mask);
309 giu_set(GIUREDGEINHH, mask);
310 break;
311 }
312 }
313 } else {
314 giu_clear(GIUINTTYPH, mask);
315 giu_clear(GIUINTHTSELH, mask);
316 }
317 giu_write(GIUINTSTATH, mask);
318 }
319}
320
321EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger);
322
323void vr41xx_set_irq_level(unsigned int pin, irq_level_t level)
324{
325 uint16_t mask;
326
327 if (pin < GIUINT_HIGH_OFFSET) {
328 mask = 1 << pin;
329 if (level == IRQ_LEVEL_HIGH)
330 giu_set(GIUINTALSELL, mask);
331 else
332 giu_clear(GIUINTALSELL, mask);
333 giu_write(GIUINTSTATL, mask);
334 } else if (pin < GIUINT_HIGH_MAX) {
335 mask = 1 << (pin - GIUINT_HIGH_OFFSET);
336 if (level == IRQ_LEVEL_HIGH)
337 giu_set(GIUINTALSELH, mask);
338 else
339 giu_clear(GIUINTALSELH, mask);
340 giu_write(GIUINTSTATH, mask);
341 }
342}
343
344EXPORT_SYMBOL_GPL(vr41xx_set_irq_level);
345
346gpio_data_t vr41xx_gpio_get_pin(unsigned int pin)
347{
348 uint16_t reg, mask;
349
350 if (pin >= giu_nr_pins)
351 return GPIO_DATA_INVAL;
352
353 if (pin < 16) {
354 reg = giu_read(GIUPIODL);
355 mask = (uint16_t)1 << pin;
356 } else if (pin < 32) {
357 reg = giu_read(GIUPIODH);
358 mask = (uint16_t)1 << (pin - 16);
359 } else if (pin < 48) {
360 reg = giu_read(GIUPODATL);
361 mask = (uint16_t)1 << (pin - 32);
362 } else {
363 reg = giu_read(GIUPODATH);
364 mask = (uint16_t)1 << (pin - 48);
365 }
366
367 if (reg & mask)
368 return GPIO_DATA_HIGH;
369
370 return GPIO_DATA_LOW;
371}
372
373EXPORT_SYMBOL_GPL(vr41xx_gpio_get_pin);
374
375int vr41xx_gpio_set_pin(unsigned int pin, gpio_data_t data)
376{
377 uint16_t offset, mask, reg;
378 unsigned long flags;
379
380 if (pin >= giu_nr_pins)
381 return -EINVAL;
382
383 if (pin < 16) {
384 offset = GIUPIODL;
385 mask = (uint16_t)1 << pin;
386 } else if (pin < 32) {
387 offset = GIUPIODH;
388 mask = (uint16_t)1 << (pin - 16);
389 } else if (pin < 48) {
390 offset = GIUPODATL;
391 mask = (uint16_t)1 << (pin - 32);
392 } else {
393 offset = GIUPODATH;
394 mask = (uint16_t)1 << (pin - 48);
395 }
396
397 spin_lock_irqsave(&giu_lock, flags);
398
399 reg = giu_read(offset);
400 if (data == GPIO_DATA_HIGH)
401 reg |= mask;
402 else
403 reg &= ~mask;
404 giu_write(offset, reg);
405
406 spin_unlock_irqrestore(&giu_lock, flags);
407
408 return 0;
409}
410
411EXPORT_SYMBOL_GPL(vr41xx_gpio_set_pin);
412
413int vr41xx_gpio_set_direction(unsigned int pin, gpio_direction_t dir)
414{
415 uint16_t offset, mask, reg;
416 unsigned long flags;
417
418 if (pin >= giu_nr_pins)
419 return -EINVAL;
420
421 if (pin < 16) {
422 offset = GIUIOSELL;
423 mask = (uint16_t)1 << pin;
424 } else if (pin < 32) {
425 offset = GIUIOSELH;
426 mask = (uint16_t)1 << (pin - 16);
427 } else {
428 if (giu_flags & GPIO_HAS_OUTPUT_ENABLE) {
429 offset = GIUPODATEN;
430 mask = (uint16_t)1 << (pin - 32);
431 } else {
432 switch (pin) {
433 case 48:
434 offset = GIUPODATH;
435 mask = PIOEN0;
436 break;
437 case 49:
438 offset = GIUPODATH;
439 mask = PIOEN1;
440 break;
441 default:
442 return -EINVAL;
443 }
444 }
445 }
446
447 spin_lock_irqsave(&giu_lock, flags);
448
449 reg = giu_read(offset);
450 if (dir == GPIO_OUTPUT)
451 reg |= mask;
452 else
453 reg &= ~mask;
454 giu_write(offset, reg);
455
456 spin_unlock_irqrestore(&giu_lock, flags);
457
458 return 0;
459}
460
461EXPORT_SYMBOL_GPL(vr41xx_gpio_set_direction);
462
463int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull)
464{
465 uint16_t reg, mask;
466 unsigned long flags;
467
468 if ((giu_flags & GPIO_HAS_PULLUPDOWN_IO) != GPIO_HAS_PULLUPDOWN_IO)
469 return -EPERM;
470
471 if (pin >= 15)
472 return -EINVAL;
473
474 mask = (uint16_t)1 << pin;
475
476 spin_lock_irqsave(&giu_lock, flags);
477
478 if (pull == GPIO_PULL_UP || pull == GPIO_PULL_DOWN) {
479 reg = giu_read(GIUTERMUPDN);
480 if (pull == GPIO_PULL_UP)
481 reg |= mask;
482 else
483 reg &= ~mask;
484 giu_write(GIUTERMUPDN, reg);
485
486 reg = giu_read(GIUUSEUPDN);
487 reg |= mask;
488 giu_write(GIUUSEUPDN, reg);
489 } else {
490 reg = giu_read(GIUUSEUPDN);
491 reg &= ~mask;
492 giu_write(GIUUSEUPDN, reg);
493 }
494
495 spin_unlock_irqrestore(&giu_lock, flags);
496
497 return 0;
498}
499
500EXPORT_SYMBOL_GPL(vr41xx_gpio_pullupdown);
501
502static ssize_t gpio_read(struct file *file, char __user *buf, size_t len,
503 loff_t *ppos)
504{
505 unsigned int pin;
506 char value = '0';
507
508 pin = iminor(file->f_dentry->d_inode);
509 if (pin >= giu_nr_pins)
510 return -EBADF;
511
512 if (vr41xx_gpio_get_pin(pin) == GPIO_DATA_HIGH)
513 value = '1';
514
515 if (len <= 0)
516 return -EFAULT;
517
518 if (put_user(value, buf))
519 return -EFAULT;
520
521 return 1;
522}
523
524static ssize_t gpio_write(struct file *file, const char __user *data,
525 size_t len, loff_t *ppos)
526{
527 unsigned int pin;
528 size_t i;
529 char c;
530 int retval = 0;
531
532 pin = iminor(file->f_dentry->d_inode);
533 if (pin >= giu_nr_pins)
534 return -EBADF;
535
536 for (i = 0; i < len; i++) {
537 if (get_user(c, data + i))
538 return -EFAULT;
539
540 switch (c) {
541 case '0':
542 retval = vr41xx_gpio_set_pin(pin, GPIO_DATA_LOW);
543 break;
544 case '1':
545 retval = vr41xx_gpio_set_pin(pin, GPIO_DATA_HIGH);
546 break;
547 case 'D':
548 printk(KERN_INFO "GPIO%d: pull down\n", pin);
549 retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DOWN);
550 break;
551 case 'd':
552 printk(KERN_INFO "GPIO%d: pull up/down disable\n", pin);
553 retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DISABLE);
554 break;
555 case 'I':
556 printk(KERN_INFO "GPIO%d: input\n", pin);
557 retval = vr41xx_gpio_set_direction(pin, GPIO_INPUT);
558 break;
559 case 'O':
560 printk(KERN_INFO "GPIO%d: output\n", pin);
561 retval = vr41xx_gpio_set_direction(pin, GPIO_OUTPUT);
562 break;
563 case 'o':
564 printk(KERN_INFO "GPIO%d: output disable\n", pin);
565 retval = vr41xx_gpio_set_direction(pin, GPIO_OUTPUT_DISABLE);
566 break;
567 case 'P':
568 printk(KERN_INFO "GPIO%d: pull up\n", pin);
569 retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_UP);
570 break;
571 case 'p':
572 printk(KERN_INFO "GPIO%d: pull up/down disable\n", pin);
573 retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DISABLE);
574 break;
575 default:
576 break;
577 }
578
579 if (retval < 0)
580 break;
581 }
582
583 return i;
584}
585
586static int gpio_open(struct inode *inode, struct file *file)
587{
588 unsigned int pin;
589
590 pin = iminor(inode);
591 if (pin >= giu_nr_pins)
592 return -EBADF;
593
594 return nonseekable_open(inode, file);
595}
596
597static int gpio_release(struct inode *inode, struct file *file)
598{
599 unsigned int pin;
600
601 pin = iminor(inode);
602 if (pin >= giu_nr_pins)
603 return -EBADF;
604
605 return 0;
606}
607
608static struct file_operations gpio_fops = {
609 .owner = THIS_MODULE,
610 .read = gpio_read,
611 .write = gpio_write,
612 .open = gpio_open,
613 .release = gpio_release,
614};
615
616static int giu_probe(struct device *dev)
617{
618 unsigned long start, size, flags = 0;
619 unsigned int nr_pins = 0;
620 struct resource *res1, *res2 = NULL;
621 void *base;
622 int retval, i;
623
624 switch (current_cpu_data.cputype) {
625 case CPU_VR4111:
626 case CPU_VR4121:
627 start = GIU_TYPE1_START;
628 size = GIU_TYPE1_SIZE;
629 flags = GPIO_HAS_PULLUPDOWN_IO;
630 nr_pins = 50;
631 break;
632 case CPU_VR4122:
633 case CPU_VR4131:
634 start = GIU_TYPE2_START;
635 size = GIU_TYPE2_SIZE;
636 nr_pins = 36;
637 break;
638 case CPU_VR4133:
639 start = GIU_TYPE3_START;
640 size = GIU_TYPE3_SIZE;
641 flags = GPIO_HAS_INTERRUPT_EDGE_SELECT;
642 nr_pins = 48;
643 break;
644 default:
645 return -ENODEV;
646 }
647
648 res1 = request_mem_region(start, size, "GIU");
649 if (res1 == NULL)
650 return -EBUSY;
651
652 base = ioremap(start, size);
653 if (base == NULL) {
654 release_resource(res1);
655 return -ENOMEM;
656 }
657
658 if (flags & GPIO_HAS_PULLUPDOWN_IO) {
659 res2 = request_mem_region(GIU_PULLUPDOWN_START, GIU_PULLUPDOWN_SIZE, "GIU");
660 if (res2 == NULL) {
661 iounmap(base);
662 release_resource(res1);
663 return -EBUSY;
664 }
665 }
666
667 retval = register_chrdev(major, "GIU", &gpio_fops);
668 if (retval < 0) {
669 iounmap(base);
670 release_resource(res1);
671 release_resource(res2);
672 return retval;
673 }
674
675 if (major == 0) {
676 major = retval;
677 printk(KERN_INFO "GIU: major number %d\n", major);
678 }
679
680 spin_lock_init(&giu_lock);
681 giu_base = base;
682 giu_resource1 = res1;
683 giu_resource2 = res2;
684 giu_flags = flags;
685 giu_nr_pins = nr_pins;
686
687 giu_write(GIUINTENL, 0);
688 giu_write(GIUINTENH, 0);
689
690 for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
691 if (i < GIU_IRQ(GIUINT_HIGH_OFFSET))
692 irq_desc[i].handler = &giuint_low_irq_type;
693 else
694 irq_desc[i].handler = &giuint_high_irq_type;
695 }
696
697 return cascade_irq(GIUINT_IRQ, giu_get_irq);
698}
699
700static int giu_remove(struct device *dev)
701{
702 iounmap(giu_base);
703
704 release_resource(giu_resource1);
705 if (giu_flags & GPIO_HAS_PULLUPDOWN_IO)
706 release_resource(giu_resource2);
707
708 return 0;
709}
710
711static struct platform_device *giu_platform_device;
712
713static struct device_driver giu_device_driver = {
714 .name = "GIU",
715 .bus = &platform_bus_type,
716 .probe = giu_probe,
717 .remove = giu_remove,
718};
719
720static int __devinit vr41xx_giu_init(void)
721{
722 int retval;
723
724 giu_platform_device = platform_device_register_simple("GIU", -1, NULL, 0);
725 if (IS_ERR(giu_platform_device))
726 return PTR_ERR(giu_platform_device);
727
728 retval = driver_register(&giu_device_driver);
729 if (retval < 0)
730 platform_device_unregister(giu_platform_device);
731
732 return retval;
733}
734
735static void __devexit vr41xx_giu_exit(void)
736{
737 driver_unregister(&giu_device_driver);
738
739 platform_device_unregister(giu_platform_device);
740}
741
742module_init(vr41xx_giu_init);
743module_exit(vr41xx_giu_exit);
diff --git a/include/asm-mips/vr41xx/giu.h b/include/asm-mips/vr41xx/giu.h
new file mode 100644
index 000000000000..8590885a7638
--- /dev/null
+++ b/include/asm-mips/vr41xx/giu.h
@@ -0,0 +1,69 @@
1/*
2 * Include file for NEC VR4100 series General-purpose I/O Unit.
3 *
4 * Copyright (C) 2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __NEC_VR41XX_GIU_H
21#define __NEC_VR41XX_GIU_H
22
23typedef enum {
24 IRQ_TRIGGER_LEVEL,
25 IRQ_TRIGGER_EDGE,
26 IRQ_TRIGGER_EDGE_FALLING,
27 IRQ_TRIGGER_EDGE_RISING,
28} irq_trigger_t;
29
30typedef enum {
31 IRQ_SIGNAL_THROUGH,
32 IRQ_SIGNAL_HOLD,
33} irq_signal_t;
34
35extern void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_t signal);
36
37typedef enum {
38 IRQ_LEVEL_LOW,
39 IRQ_LEVEL_HIGH,
40} irq_level_t;
41
42extern void vr41xx_set_irq_level(unsigned int pin, irq_level_t level);
43
44typedef enum {
45 GPIO_DATA_LOW,
46 GPIO_DATA_HIGH,
47 GPIO_DATA_INVAL,
48} gpio_data_t;
49
50extern gpio_data_t vr41xx_gpio_get_pin(unsigned int pin);
51extern int vr41xx_gpio_set_pin(unsigned int pin, gpio_data_t data);
52
53typedef enum {
54 GPIO_INPUT,
55 GPIO_OUTPUT,
56 GPIO_OUTPUT_DISABLE,
57} gpio_direction_t;
58
59extern int vr41xx_gpio_set_direction(unsigned int pin, gpio_direction_t dir);
60
61typedef enum {
62 GPIO_PULL_DOWN,
63 GPIO_PULL_UP,
64 GPIO_PULL_DISABLE,
65} gpio_pull_t;
66
67extern int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull);
68
69#endif /* __NEC_VR41XX_GIU_H */
diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h
index ad0d1ea144f0..7d41e44463f9 100644
--- a/include/asm-mips/vr41xx/vr41xx.h
+++ b/include/asm-mips/vr41xx/vr41xx.h
@@ -126,7 +126,6 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock);
126#define GIU_IRQ_BASE 40 126#define GIU_IRQ_BASE 40
127#define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */ 127#define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */
128#define GIU_IRQ_LAST GIU_IRQ(31) 128#define GIU_IRQ_LAST GIU_IRQ(31)
129#define GIU_IRQ_TO_PIN(x) ((x) - GIU_IRQ_BASE) /* Pin 0-31 */
130 129
131extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign); 130extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
132extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq)); 131extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq));
@@ -197,38 +196,4 @@ extern void vr41xx_disable_csiint(uint16_t mask);
197extern void vr41xx_enable_bcuint(void); 196extern void vr41xx_enable_bcuint(void);
198extern void vr41xx_disable_bcuint(void); 197extern void vr41xx_disable_bcuint(void);
199 198
200/*
201 * General-Purpose I/O Unit
202 */
203enum {
204 TRIGGER_LEVEL,
205 TRIGGER_EDGE,
206 TRIGGER_EDGE_FALLING,
207 TRIGGER_EDGE_RISING
208};
209
210enum {
211 SIGNAL_THROUGH,
212 SIGNAL_HOLD
213};
214
215extern void vr41xx_set_irq_trigger(int pin, int trigger, int hold);
216
217enum {
218 LEVEL_LOW,
219 LEVEL_HIGH
220};
221
222extern void vr41xx_set_irq_level(int pin, int level);
223
224enum {
225 PIO_INPUT,
226 PIO_OUTPUT
227};
228
229enum {
230 DATA_LOW,
231 DATA_HIGH
232};
233
234#endif /* __NEC_VR41XX_H */ 199#endif /* __NEC_VR41XX_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 22:36:48 -0500