147 files changed, 3346 insertions, 788 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index fbe0dca1c0ed..57c07c20af40 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -457,7 +457,7 @@ S:	Maintained
 
 ARM/HP JORNADA 7XX MACHINE SUPPORT
 P:      Kristoffer Ericson
-M:      kristoffer_e1@hotmail.com
+M:      kristoffer.ericson@gmail.com
 W:      www.jlime.com
 S:      Maintained
 
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a44c6da9bf83..85016313bd11 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -324,6 +324,12 @@ config ARCH_NS9XXX
 
           <http://www.digi.com/products/microprocessors/index.jsp>
 
+config ARCH_MXC
+        bool "Freescale MXC/iMX-based"
+        select ARCH_MTD_XIP
+        help
+          Support for Freescale MXC/iMX-based family of processors
+
 config ARCH_PNX4008
         bool "Philips Nexperia PNX4008 Mobile"
         help
@@ -432,6 +438,7 @@ source "arch/arm/mach-omap1/Kconfig"
 source "arch/arm/mach-omap2/Kconfig"
 
 source "arch/arm/plat-s3c24xx/Kconfig"
+source "arch/arm/plat-s3c/Kconfig"
 
 if ARCH_S3C2410
 source "arch/arm/mach-s3c2400/Kconfig"
@@ -456,6 +463,8 @@ source "arch/arm/mach-realview/Kconfig"
 
 source "arch/arm/mach-at91/Kconfig"
 
+source "arch/arm/plat-mxc/Kconfig"
+
 source "arch/arm/mach-netx/Kconfig"
 
 source "arch/arm/mach-ns9xxx/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 40c5eb1f55c7..18101f5f5f24 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -82,24 +82,24 @@ config DEBUG_CLPS711X_UART2
           output to the second serial port on these devices.  Saying N will
           cause the debug messages to appear on the first serial port.
 
-config DEBUG_S3C2410_PORT
-        depends on DEBUG_LL && ARCH_S3C2410
-        bool "Kernel low-level debugging messages via S3C2410 UART"
+config DEBUG_S3C_PORT
+        depends on DEBUG_LL && PLAT_S3C
+        bool "Kernel low-level debugging messages via S3C UART"
         help
           Say Y here if you want debug print routines to go to one of the
-          S3C2410 internal UARTs. The chosen UART must have been configured
+          S3C internal UARTs. The chosen UART must have been configured
           before it is used.
 
-config DEBUG_S3C2410_UART
-        depends on ARCH_S3C2410
-        int "S3C2410 UART to use for low-level debug"
+config DEBUG_S3C_UART
+        depends on PLAT_S3C
+        int "S3C UART to use for low-level debug"
         default "0"
         help
-          Choice for UART for kernel low-level using S3C2410 UARTS,
+          Choice for UART for kernel low-level using S3C UARTS,
           should be between zero and two. The port must have been
           initialised by the boot-loader before use.
 
           The uncompressor code port configuration is now handled
-          by CONFIG_S3C2410_LOWLEVEL_UART_PORT.
+          by CONFIG_S3C_LOWLEVEL_UART_PORT.
 
 endmenu
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index cbd5010d3bc3..fa4ea9ff0797 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -137,6 +137,8 @@ endif
  textofs-$(CONFIG_ARCH_NS9XXX)     := 0x00108000
  machine-$(CONFIG_ARCH_DAVINCI)    := davinci
  machine-$(CONFIG_ARCH_KS8695)     := ks8695
+  incdir-$(CONFIG_ARCH_MXC)        := mxc
+ machine-$(CONFIG_ARCH_MX3)        := mx3
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 # This is what happens if you forget the IOCS16 line.
@@ -183,6 +185,7 @@ core-$(CONFIG_VFP)		+= arch/arm/vfp/
 core-$(CONFIG_PLAT_IOP)         += arch/arm/plat-iop/
 core-$(CONFIG_ARCH_OMAP)        += arch/arm/plat-omap/
 core-$(CONFIG_PLAT_S3C24XX)             += arch/arm/plat-s3c24xx/
+core-$(CONFIG_ARCH_MXC)         += arch/arm/plat-mxc/
 
 drivers-$(CONFIG_OPROFILE)      += arch/arm/oprofile/
 drivers-$(CONFIG_ARCH_CLPS7500) += drivers/acorn/char/
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index ec9c400c7f82..25f12303b106 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -91,4 +91,12 @@ zinstall: $(obj)/zImage
         $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
         $(obj)/zImage System.map "$(INSTALL_PATH)"
 
+zi:
+        $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+        $(obj)/zImage System.map "$(INSTALL_PATH)"
+
+i:
+        $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+        $(obj)/Image System.map "$(INSTALL_PATH)"
+
 subdir-     := bootp compressed
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index a1f1691b67fe..6b8cbd69f249 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -73,7 +73,7 @@ SEDFLAGS	= s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/
 
 targets       := vmlinux vmlinux.lds piggy.gz piggy.o font.o font.c \
                  head.o misc.o $(OBJS)
-EXTRA_CFLAGS  := -fpic
+EXTRA_CFLAGS  := -fpic -fno-builtin
 EXTRA_AFLAGS  :=
 
 # Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index d7fb5ee1637e..b9b03eda70e5 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -55,7 +55,7 @@
 #elif defined(CONFIG_ARCH_S3C2410)
                 .macro loadsp, rb
                 mov     \rb, #0x50000000
-                add     \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT
+                add     \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
                 .endm
 #else
                 .macro  loadsp, rb
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
index 1d5150e4d6b3..f8a1645b3d4a 100644
--- a/arch/arm/configs/s3c2410_defconfig
+++ b/arch/arm/configs/s3c2410_defconfig
@@ -138,11 +138,11 @@ CONFIG_ARCH_S3C2410=y
 CONFIG_PLAT_S3C24XX=y
 CONFIG_CPU_S3C244X=y
 CONFIG_PM_SIMTEC=y
-# CONFIG_S3C2410_BOOT_WATCHDOG is not set
-# CONFIG_S3C2410_BOOT_ERROR_RESET is not set
+# CONFIG_S3C_BOOT_WATCHDOG is not set
+# CONFIG_S3C_BOOT_ERROR_RESET is not set
 # CONFIG_S3C2410_PM_DEBUG is not set
 # CONFIG_S3C2410_PM_CHECK is not set
-CONFIG_S3C2410_LOWLEVEL_UART_PORT=0
+CONFIG_S3C_LOWLEVEL_UART_PORT=0
 CONFIG_S3C2410_DMA=y
 # CONFIG_S3C2410_DMA_DEBUG is not set
 CONFIG_MACH_SMDK=y
@@ -1392,8 +1392,8 @@ CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
-CONFIG_DEBUG_S3C2410_PORT=y
-CONFIG_DEBUG_S3C2410_UART=0
+CONFIG_DEBUG_S3C_PORT=y
+CONFIG_DEBUG_S3C_UART=0
 
 #
 # Security options
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 70599bcf451c..0417c165d50d 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -477,7 +477,7 @@ void __init at91_add_device_i2c(void) {}
  *  SPI
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE)
+#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
 static u64 spi_dmamask = 0xffffffffUL;
 
 static struct resource spi_resources[] = {
@@ -494,7 +494,7 @@ static struct resource spi_resources[] = {
 };
 
 static struct platform_device at91rm9200_spi_device = {
-        .name           = "at91_spi",
+        .name           = "atmel_spi",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &spi_dmamask,
@@ -522,18 +522,14 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
                 else
                         cs_pin = spi_standard_cs[devices[i].chip_select];
 
-#ifdef CONFIG_SPI_AT91_MANUAL_CS
+                /* enable chip-select pin */
                 at91_set_gpio_output(cs_pin, 1);
-#else
-                at91_set_A_periph(cs_pin, 0);
-#endif
 
                 /* pass chip-select pin to driver */
                 devices[i].controller_data = (void *) cs_pin;
         }
 
         spi_register_board_info(devices, nr_devices);
-        at91_clock_associate("spi_clk", &at91rm9200_spi_device.dev, "spi");
         platform_device_register(&at91rm9200_spi_device);
 }
 #else
diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig
index 9bb02b6d7ae1..dbe07c9472ed 100644
--- a/arch/arm/mach-iop32x/Kconfig
+++ b/arch/arm/mach-iop32x/Kconfig
@@ -42,6 +42,13 @@ config IOP3XX_ATU
           Say N if the IOP is an add in card, the host system owns the PCI
           bus in this case.
 
+config MACH_EM7210
+        bool "Enable support for the Lanner EM7210"
+        help
+          Say Y here if you want to run your kernel on the Lanner EM7210
+          board. Say also Y here if you have a SS4000e Baxter Creek NAS
+          appliance."
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-iop32x/Makefile b/arch/arm/mach-iop32x/Makefile
index 7b05b37e1f94..cfdf8a137c2b 100644
--- a/arch/arm/mach-iop32x/Makefile
+++ b/arch/arm/mach-iop32x/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_MACH_GLANTANK) += glantank.o
 obj-$(CONFIG_ARCH_IQ80321) += iq80321.o
 obj-$(CONFIG_ARCH_IQ31244) += iq31244.o
 obj-$(CONFIG_MACH_N2100) += n2100.o
+obj-$(CONFIG_MACH_EM7210) += em7210.o
diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c
new file mode 100644
index 000000000000..c947152f9a3c
--- /dev/null
+++ b/arch/arm/mach-iop32x/em7210.c
@@ -0,0 +1,215 @@
+/*
+ * arch/arm/mach-iop32x/em7210.c
+ *
+ * Board support code for the Lanner EM7210 platforms.
+ *
+ * Based on arch/arm/mach-iop32x/iq31244.c file.
+ *
+ * Copyright (C) 2007 Arnaud Patard <arnaud.patard@rtp-net.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/pm.h>
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+#include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <asm/hardware.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/pci.h>
+#include <asm/mach/time.h>
+#include <asm/mach-types.h>
+#include <asm/arch/time.h>
+
+static void __init em7210_timer_init(void)
+{
+        /* http://www.kwaak.net/fotos/fotos-nas/slide_24.html */
+        /* 33.333 MHz crystal.                                */
+        iop_init_time(200000000);
+}
+
+static struct sys_timer em7210_timer = {
+        .init           = em7210_timer_init,
+        .offset         = iop_gettimeoffset,
+};
+
+/*
+ * EM7210 RTC
+ */
+static struct i2c_board_info __initdata em7210_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("rtc-rs5c372", 0x32),
+                .type = "rs5c372a",
+        },
+};
+
+/*
+ * EM7210 I/O
+ */
+static struct map_desc em7210_io_desc[] __initdata = {
+        {       /* on-board devices */
+                .virtual        = IQ31244_UART,
+                .pfn            = __phys_to_pfn(IQ31244_UART),
+                .length         = 0x00100000,
+                .type           = MT_DEVICE,
+        },
+};
+
+void __init em7210_map_io(void)
+{
+        iop3xx_map_io();
+        iotable_init(em7210_io_desc, ARRAY_SIZE(em7210_io_desc));
+}
+
+
+/*
+ * EM7210 PCI
+ */
+#define INTA    IRQ_IOP32X_XINT0
+#define INTB    IRQ_IOP32X_XINT1
+#define INTC    IRQ_IOP32X_XINT2
+#define INTD    IRQ_IOP32X_XINT3
+
+static int __init
+em7210_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        static int pci_irq_table[][4] = {
+                /*
+                 * PCI IDSEL/INTPIN->INTLINE
+                 * A       B       C       D
+                 */
+                {INTB, INTB, INTB, INTB}, /* console / uart */
+                {INTA, INTA, INTA, INTA}, /* 1st 82541      */
+                {INTD, INTD, INTD, INTD}, /* 2nd 82541      */
+                {INTC, INTC, INTC, INTC}, /* GD31244        */
+                {INTD, INTA, INTA, INTA}, /* mini-PCI       */
+                {INTD, INTC, INTA, INTA}, /* NEC USB        */
+        };
+
+        if (pin < 1 || pin > 4)
+                return -1;
+
+        return pci_irq_table[slot % 6][pin - 1];
+}
+
+static struct hw_pci em7210_pci __initdata = {
+        .swizzle        = pci_std_swizzle,
+        .nr_controllers = 1,
+        .setup          = iop3xx_pci_setup,
+        .preinit        = iop3xx_pci_preinit,
+        .scan           = iop3xx_pci_scan_bus,
+        .map_irq        = em7210_pci_map_irq,
+};
+
+static int __init em7210_pci_init(void)
+{
+        if (machine_is_em7210())
+                pci_common_init(&em7210_pci);
+
+        return 0;
+}
+
+subsys_initcall(em7210_pci_init);
+
+
+/*
+ * EM7210 Flash
+ */
+static struct physmap_flash_data em7210_flash_data = {
+        .width          = 2,
+};
+
+static struct resource em7210_flash_resource = {
+        .start          = 0xf0000000,
+        .end            = 0xf1ffffff,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device em7210_flash_device = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &em7210_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &em7210_flash_resource,
+};
+
+
+/*
+ * EM7210 UART
+ * The physical address of the serial port is 0xfe800000,
+ * so it can be used for physical and virtual address.
+ */
+static struct plat_serial8250_port em7210_serial_port[] = {
+        {
+                .mapbase        = IQ31244_UART,
+                .membase        = (char *)IQ31244_UART,
+                .irq            = IRQ_IOP32X_XINT1,
+                .flags          = UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+                .regshift       = 0,
+                .uartclk        = 1843200,
+        },
+        { },
+};
+
+static struct resource em7210_uart_resource = {
+        .start          = IQ31244_UART,
+        .end            = IQ31244_UART + 7,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device em7210_serial_device = {
+        .name           = "serial8250",
+        .id             = PLAT8250_DEV_PLATFORM,
+        .dev            = {
+                .platform_data          = em7210_serial_port,
+        },
+        .num_resources  = 1,
+        .resource       = &em7210_uart_resource,
+};
+
+void em7210_power_off(void)
+{
+        *IOP3XX_GPOE &= 0xfe;
+        *IOP3XX_GPOD |= 0x01;
+}
+
+static void __init em7210_init_machine(void)
+{
+        platform_device_register(&em7210_serial_device);
+        platform_device_register(&iop3xx_i2c0_device);
+        platform_device_register(&iop3xx_i2c1_device);
+        platform_device_register(&em7210_flash_device);
+        platform_device_register(&iop3xx_dma_0_channel);
+        platform_device_register(&iop3xx_dma_1_channel);
+
+        i2c_register_board_info(0, em7210_i2c_devices,
+                ARRAY_SIZE(em7210_i2c_devices));
+
+
+        pm_power_off = em7210_power_off;
+}
+
+MACHINE_START(EM7210, "Lanner EM7210")
+        .phys_io        = IQ31244_UART,
+        .io_pg_offst    = ((IQ31244_UART) >> 18) & 0xfffc,
+        .boot_params    = 0xa0000100,
+        .map_io         = em7210_map_io,
+        .init_irq       = iop32x_init_irq,
+        .timer          = &em7210_timer,
+        .init_machine   = em7210_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index c971171c2905..55cf0162e8c1 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -63,7 +63,8 @@ void __init iop32x_init_irq(void)
         if (machine_is_glantank() ||
             machine_is_iq80321() ||
             machine_is_iq31244() ||
-            machine_is_n2100())
+            machine_is_n2100() ||
+            machine_is_em7210())
                 *IOP3XX_PCIIRSR = 0x0f;
 
         for (i = 0; i < NR_IRQS; i++) {
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 8112f726ffa0..4c54a86eda3a 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -188,7 +188,7 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
         *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
 
         /* Configure the line as an input */
-        gpio_line_config(line, IXP4XX_GPIO_IN);
+        gpio_line_config(irq2gpio[irq], IXP4XX_GPIO_IN);
 
         return 0;
 }
diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c
index 2407bba00547..4c3ab43e1046 100644
--- a/arch/arm/mach-ks8695/irq.c
+++ b/arch/arm/mach-ks8695/irq.c
@@ -23,7 +23,6 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
-#include <linux/ptrace.h>
 #include <linux/sysdev.h>
 
 #include <asm/hardware.h>
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
new file mode 100644
index 000000000000..5fe8606cac08
--- /dev/null
+++ b/arch/arm/mach-mx3/Kconfig
@@ -0,0 +1,12 @@
+menu "MX3 Options"
+        depends on ARCH_MX3
+
+config MACH_MX31ADS
+        bool "Support MX31ADS platforms"
+        default y
+        help
+          Include support for MX31ADS platform. This includes specific
+          configurations for the board and its peripherals.
+
+endmenu
+
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
new file mode 100644
index 000000000000..cbec997f332a
--- /dev/null
+++ b/arch/arm/mach-mx3/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-y                   := mm.o time.o
+obj-$(CONFIG_MACH_MX31ADS)      += mx31ads.o
diff --git a/arch/arm/mach-mx3/Makefile.boot b/arch/arm/mach-mx3/Makefile.boot
new file mode 100644
index 000000000000..e1dd366f836b
--- /dev/null
+++ b/arch/arm/mach-mx3/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x80008000
+params_phys-y   := 0x80000100
+initrd_phys-y   := 0x80800000
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
new file mode 100644
index 000000000000..41dad485ded9
--- /dev/null
+++ b/arch/arm/mach-mx3/mm.c
@@ -0,0 +1,64 @@
+/*
+ *  Copyright (C) 1999,2000 Arm Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - add MX31 specific definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <asm/hardware.h>
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+#include <asm/arch/common.h>
+
+/*!
+ * @file mm.c
+ *
+ * @brief This file creates static virtual to physical mappings, common to all MX3 boards.
+ *
+ * @ingroup Memory
+ */
+
+/*!
+ * This table defines static virtual address mappings for I/O regions.
+ * These are the mappings common across all MX3 boards.
+ */
+static struct map_desc mxc_io_desc[] __initdata = {
+        {
+                .virtual        = X_MEMC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(X_MEMC_BASE_ADDR),
+                .length         = X_MEMC_SIZE,
+                .type           = MT_DEVICE
+        }, {
+                .virtual        = AVIC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(AVIC_BASE_ADDR),
+                .length         = AVIC_SIZE,
+                .type           = MT_NONSHARED_DEVICE
+        },
+};
+
+/*!
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory mappings
+ * for the IO modules.
+ */
+void __init mxc_map_io(void)
+{
+        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+}
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
new file mode 100644
index 000000000000..7e89bdc23a9f
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -0,0 +1,142 @@
+/*
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/memory.h>
+#include <asm/mach/map.h>
+#include <asm/arch/common.h>
+
+/*!
+ * @file mx31ads.c
+ *
+ * @brief This file contains the board-specific initialization routines.
+ *
+ * @ingroup System
+ */
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+/*!
+ * The serial port definition structure.
+ */
+static struct plat_serial8250_port serial_platform_data[] = {
+        {
+                .membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
+                .mapbase  = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA),
+                .irq      = EXPIO_INT_XUART_INTA,
+                .uartclk  = 14745600,
+                .regshift = 0,
+                .iotype   = UPIO_MEM,
+                .flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
+        }, {
+                .membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
+                .mapbase  = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB),
+                .irq      = EXPIO_INT_XUART_INTB,
+                .uartclk  = 14745600,
+                .regshift = 0,
+                .iotype   = UPIO_MEM,
+                .flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
+        },
+        {},
+};
+
+static struct platform_device serial_device = {
+        .name   = "serial8250",
+        .id     = 0,
+        .dev    = {
+                .platform_data = serial_platform_data,
+        },
+};
+
+static int __init mxc_init_extuart(void)
+{
+        return platform_device_register(&serial_device);
+}
+#else
+static inline int mxc_init_extuart(void)
+{
+        return 0;
+}
+#endif
+
+/*!
+ * This structure defines static mappings for the i.MX31ADS board.
+ */
+static struct map_desc mx31ads_io_desc[] __initdata = {
+        {
+                .virtual        = AIPS1_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(AIPS1_BASE_ADDR),
+                .length         = AIPS1_SIZE,
+                .type           = MT_NONSHARED_DEVICE
+        }, {
+                .virtual        = SPBA0_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(SPBA0_BASE_ADDR),
+                .length         = SPBA0_SIZE,
+                .type           = MT_NONSHARED_DEVICE
+        }, {
+                .virtual        = AIPS2_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(AIPS2_BASE_ADDR),
+                .length         = AIPS2_SIZE,
+                .type           = MT_NONSHARED_DEVICE
+        }, {
+                .virtual        = CS4_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(CS4_BASE_ADDR),
+                .length         = CS4_SIZE / 2,
+                .type           = MT_DEVICE
+        },
+};
+
+/*!
+ * Set up static virtual mappings.
+ */
+void __init mx31ads_map_io(void)
+{
+        mxc_map_io();
+        iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
+}
+
+/*!
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+        mxc_init_extuart();
+}
+
+/*
+ * The following uses standard kernel macros defined in arch.h in order to
+ * initialize __mach_desc_MX31ADS data structure.
+ */
+MACHINE_START(MX31ADS, "Freescale MX31ADS")
+        /* Maintainer: Freescale Semiconductor, Inc. */
+        .phys_io        = AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx31ads_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = mxc_board_init,
+        .timer          = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/time.c b/arch/arm/mach-mx3/time.c
new file mode 100644
index 000000000000..e81fb5c5d7c3
--- /dev/null
+++ b/arch/arm/mach-mx3/time.c
@@ -0,0 +1,152 @@
+/*
+ * System Timer Interrupt reconfigured to run in free-run mode.
+ * Author: Vitaly Wool
+ * Copyright 2004 MontaVista Software Inc.
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*!
+ * @file time.c
+ * @brief This file contains OS tick and wdog timer implementations.
+ *
+ * This file contains OS tick and wdog timer implementations.
+ *
+ * @ingroup Timers
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <asm/hardware.h>
+#include <asm/mach/time.h>
+#include <asm/io.h>
+#include <asm/arch/common.h>
+
+/*!
+ * This is the timer interrupt service routine to do required tasks.
+ * It also services the WDOG timer at the frequency of twice per WDOG
+ * timeout value. For example, if the WDOG's timeout value is 4 (2
+ * seconds since the WDOG runs at 0.5Hz), it will be serviced once
+ * every 2/2=1 second.
+ *
+ * @param  irq          GPT interrupt source number (not used)
+ * @param  dev_id       this parameter is not used
+ * @return always returns \b IRQ_HANDLED as defined in
+ *         include/linux/interrupt.h.
+ */
+static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
+{
+        unsigned int next_match;
+
+        write_seqlock(&xtime_lock);
+
+        if (__raw_readl(MXC_GPT_GPTSR) & GPTSR_OF1) {
+                do {
+                        timer_tick();
+                        next_match = __raw_readl(MXC_GPT_GPTOCR1) + LATCH;
+                        __raw_writel(GPTSR_OF1, MXC_GPT_GPTSR);
+                        __raw_writel(next_match, MXC_GPT_GPTOCR1);
+                } while ((signed long)(next_match -
+                                       __raw_readl(MXC_GPT_GPTCNT)) <= 0);
+        }
+
+        write_sequnlock(&xtime_lock);
+
+        return IRQ_HANDLED;
+}
+
+/*!
+ * This function is used to obtain the number of microseconds since the last
+ * timer interrupt. Note that interrupts is disabled by do_gettimeofday().
+ *
+ * @return the number of microseconds since the last timer interrupt.
+ */
+static unsigned long mxc_gettimeoffset(void)
+{
+        unsigned long ticks_to_match, elapsed, usec, tick_usec, i;
+
+        /* Get ticks before next timer match */
+        ticks_to_match =
+            __raw_readl(MXC_GPT_GPTOCR1) - __raw_readl(MXC_GPT_GPTCNT);
+
+        /* We need elapsed ticks since last match */
+        elapsed = LATCH - ticks_to_match;
+
+        /* Now convert them to usec */
+        /* Insure no overflow when calculating the usec below */
+        for (i = 1, tick_usec = tick_nsec / 1000;; i *= 2) {
+                tick_usec /= i;
+                if ((0xFFFFFFFF / tick_usec) > elapsed)
+                        break;
+        }
+        usec = (unsigned long)(elapsed * tick_usec) / (LATCH / i);
+
+        return usec;
+}
+
+/*!
+ * The OS tick timer interrupt structure.
+ */
+static struct irqaction timer_irq = {
+        .name = "MXC Timer Tick",
+        .flags = IRQF_DISABLED | IRQF_TIMER,
+        .handler = mxc_timer_interrupt
+};
+
+/*!
+ * This function is used to initialize the GPT to produce an interrupt
+ * based on HZ.  It is called by start_kernel() during system startup.
+ */
+void __init mxc_init_time(void)
+{
+        u32 reg, v;
+        reg = __raw_readl(MXC_GPT_GPTCR);
+        reg &= ~GPTCR_ENABLE;
+        __raw_writel(reg, MXC_GPT_GPTCR);
+        reg |= GPTCR_SWR;
+        __raw_writel(reg, MXC_GPT_GPTCR);
+
+        while ((__raw_readl(MXC_GPT_GPTCR) & GPTCR_SWR) != 0)
+                cpu_relax();
+
+        reg = GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ;
+        __raw_writel(reg, MXC_GPT_GPTCR);
+
+        /* TODO: get timer rate from clk driver */
+        v = 66500000;
+
+        __raw_writel((v / CLOCK_TICK_RATE) - 1, MXC_GPT_GPTPR);
+
+        if ((v % CLOCK_TICK_RATE) != 0) {
+                pr_info("\nWARNING: Can't generate CLOCK_TICK_RATE at %d Hz\n",
+                        CLOCK_TICK_RATE);
+        }
+        pr_info("Actual CLOCK_TICK_RATE is %d Hz\n",
+                v / ((__raw_readl(MXC_GPT_GPTPR) & 0xFFF) + 1));
+
+        reg = __raw_readl(MXC_GPT_GPTCNT);
+        reg += LATCH;
+        __raw_writel(reg, MXC_GPT_GPTOCR1);
+
+        setup_irq(MXC_INT_GPT, &timer_irq);
+
+        reg = __raw_readl(MXC_GPT_GPTCR);
+        reg =
+            GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ | GPTCR_STOPEN | GPTCR_DOZEN |
+            GPTCR_WAITEN | GPTCR_ENMOD | GPTCR_ENABLE;
+        __raw_writel(reg, MXC_GPT_GPTCR);
+
+        __raw_writel(GPTIR_OF1IE, MXC_GPT_GPTIR);
+}
+
+struct sys_timer mxc_timer = {
+        .init = mxc_init_time,
+        .offset = mxc_gettimeoffset,
+};
diff --git a/arch/arm/mach-ns9xxx/Makefile b/arch/arm/mach-ns9xxx/Makefile
index 53213a69f601..4476411b8140 100644
--- a/arch/arm/mach-ns9xxx/Makefile
+++ b/arch/arm/mach-ns9xxx/Makefile
@@ -1,6 +1,7 @@
 obj-y := irq.o time.o generic.o
 
 obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o
+obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o
 
 obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o
 obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
index 25289884a607..925048e7adfe 100644
--- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c
+++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
@@ -77,7 +77,7 @@ static void a9m9750dev_fpga_demux_handler(unsigned int irq,
 
                 desc = irq_desc + FPGA_IRQ(irqno);
 
-                desc_handle_irq(irqno, desc);
+                desc_handle_irq(FPGA_IRQ(irqno), desc);
         }
 }
 
@@ -91,7 +91,7 @@ void __init board_a9m9750dev_init_irq(void)
          * use GPIO 11, because GPIO 32 is used for the LCD
          */
         /* XXX: proper GPIO handling */
-        BBU_GC(2) &= ~0x2000;
+        BBU_GCONFb1(1) &= ~0x2000;
 
         for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
                 set_irq_chip(i, &a9m9750dev_fpga_chip);
@@ -178,7 +178,7 @@ void __init board_a9m9750dev_init_machine(void)
 
         /* setup static CS0: memory configuration */
         reg = MEM_SMC(0);
-        REGSET(reg, MEM_SMC, WSMC, OFF);
+        REGSET(reg, MEM_SMC, PSMC, OFF);
         REGSET(reg, MEM_SMC, BSMC, OFF);
         REGSET(reg, MEM_SMC, EW, OFF);
         REGSET(reg, MEM_SMC, PB, 1);
@@ -196,4 +196,3 @@ void __init board_a9m9750dev_init_machine(void)
         platform_add_devices(board_a9m9750dev_devices,
                         ARRAY_SIZE(board_a9m9750dev_devices));
 }
-
diff --git a/arch/arm/mach-ns9xxx/generic.c b/arch/arm/mach-ns9xxx/generic.c
index 83e2b6532b22..d742c921e34d 100644
--- a/arch/arm/mach-ns9xxx/generic.c
+++ b/arch/arm/mach-ns9xxx/generic.c
@@ -18,6 +18,8 @@
 #include <asm/arch-ns9xxx/regs-mem.h>
 #include <asm/arch-ns9xxx/board.h>
 
+#include "generic.h"
+
 static struct map_desc standard_io_desc[] __initdata = {
         { /* BBus */
                 .virtual = io_p2v(0x90000000),
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c
index 83d92724a971..b8c7b00522e6 100644
--- a/arch/arm/mach-ns9xxx/irq.c
+++ b/arch/arm/mach-ns9xxx/irq.c
@@ -21,6 +21,15 @@ static void ns9xxx_ack_irq_timer(unsigned int irq)
 {
         u32 tc = SYS_TC(irq - IRQ_TIMER0);
 
+        /*
+         * If the timer is programmed to halt on terminal count, the
+         * timer must be disabled before clearing the interrupt.
+         */
+        if (REGGET(tc, SYS_TCx, REN) == 0) {
+                REGSET(tc, SYS_TCx, TEN, DIS);
+                SYS_TC(irq - IRQ_TIMER0) = tc;
+        }
+
         REGSET(tc, SYS_TCx, INTC, SET);
         SYS_TC(irq - IRQ_TIMER0) = tc;
 
@@ -28,7 +37,7 @@ static void ns9xxx_ack_irq_timer(unsigned int irq)
         SYS_TC(irq - IRQ_TIMER0) = tc;
 }
 
-void (*ns9xxx_ack_irq_functions[NR_IRQS])(unsigned int) = {
+static void (*ns9xxx_ack_irq_functions[NR_IRQS])(unsigned int) = {
         [IRQ_TIMER0] = ns9xxx_ack_irq_timer,
         [IRQ_TIMER1] = ns9xxx_ack_irq_timer,
         [IRQ_TIMER2] = ns9xxx_ack_irq_timer,
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
index d09d5fa5620a..85c8b41105c9 100644
--- a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
+++ b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
@@ -20,7 +20,7 @@ static void __init mach_cc9p9360js_init_machine(void)
         board_jscc9p9360_init_machine();
 }
 
-MACHINE_START(CC9P9360DEV, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard")
+MACHINE_START(CC9P9360JS, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard")
         .map_io = ns9xxx_map_io,
         .init_irq = ns9xxx_init_irq,
         .init_machine = mach_cc9p9360js_init_machine,
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index 570cf937e73b..a454451c97c3 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -87,7 +87,7 @@ static void __init rpc_map_io(void)
         /*
          * Turn off floppy.
          */
-        outb(0xc, 0x3f2);
+        writeb(0xc, PCIO_BASE + (0x3f2 << 2));
 
         /*
          * RiscPC can't handle half-word loads and stores
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index d4b013b283c3..e2079cf9266f 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -9,6 +9,7 @@ config CPU_S3C2410
         depends on ARCH_S3C2410
         select S3C2410_CLOCK
         select S3C2410_GPIO
+        select CPU_LLSERIAL_S3C2410
         select S3C2410_PM if PM
         help
           Support for S3C2410 and S3C2410A family from the S3C24XX line
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
index 5b4831c4c1d8..cab9d6265e9e 100644
--- a/arch/arm/mach-s3c2410/clock.c
+++ b/arch/arm/mach-s3c2410/clock.c
@@ -37,7 +37,7 @@
 #include <asm/hardware.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-gpio.h>
 
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 67d1ad363973..80d83739ab9f 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -23,14 +23,14 @@
 #include <asm/plat-s3c24xx/cpu.h>
 #include <asm/plat-s3c24xx/dma.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-ac97.h>
+#include <asm/plat-s3c/regs-ac97.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-sdi.h>
-#include <asm/arch/regs-iis.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-iis.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 
 static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
         [DMACH_XD0] = {
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 435adcce6482..43bb5e106302 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -48,7 +48,7 @@
 #include <asm/mach-types.h>
 #include <asm/arch/fb.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-gpio.h>
 
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 8b52ea95d4f6..bc926992b4e4 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -36,13 +36,13 @@
 #include <asm/mach-types.h>
 
 //#include <asm/debug-ll.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 
-#include <asm/arch/nand.h>
-#include <asm/arch/iic.h>
+#include <asm/plat-s3c/nand.h>
+#include <asm/plat-s3c/iic.h>
 #include <asm/arch/fb.h>
 
 #include <linux/mtd/mtd.h>
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 5c9bcea74767..9a172b4ad720 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -30,7 +30,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-clock.h>
@@ -38,7 +38,7 @@
 #include <asm/arch/h1940.h>
 #include <asm/arch/h1940-latch.h>
 #include <asm/arch/fb.h>
-#include <asm/arch/udc.h>
+#include <asm/plat-s3c24xx/udc.h>
 
 #include <asm/plat-s3c24xx/clock.h>
 #include <asm/plat-s3c24xx/devs.h>
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 412e50c3d28a..621f548da610 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -33,9 +33,9 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/iic.h>
+#include <asm/plat-s3c/iic.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/clock.h>
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c
index 1f899fa588df..717af40e4477 100644
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c2410/mach-otom.c
@@ -29,7 +29,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index d86e6f18bac9..e670b1e1631b 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -49,10 +49,10 @@
 
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/leds-gpio.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/fb.h>
-#include <asm/arch/nand.h>
-#include <asm/arch/udc.h>
+#include <asm/plat-s3c/nand.h>
+#include <asm/plat-s3c24xx/udc.h>
 #include <asm/arch/spi.h>
 #include <asm/arch/spi-gpio.h>
 
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c
index 5852d300d52f..226550504c85 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
@@ -47,7 +47,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 #include <asm/plat-s3c24xx/devs.h>
 #include <asm/plat-s3c24xx/cpu.h>
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 7b624bb00490..9f43f3f124f5 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -39,7 +39,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/leds-gpio.h>
 
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index 1a86a9803753..e580303cb0ab 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -29,7 +29,7 @@
 #include <asm/irq.h>
 
 #include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/cpu.h>
@@ -40,7 +40,6 @@
 
 static struct map_desc s3c2410_iodesc[] __initdata = {
         IODESC_ENT(CLKPWR),
-        IODESC_ENT(LCD),
         IODESC_ENT(TIMER),
         IODESC_ENT(WATCHDOG),
 };
diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
index d1eeed2ad47c..8a9c5a2bb252 100644
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c2410/sleep.S
@@ -32,7 +32,7 @@
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
         /* s3c2410_cpu_suspend
          *
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index d5be5d053264..8e8fe48ea47f 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -7,6 +7,7 @@
 config CPU_S3C2412
         bool
         depends on ARCH_S3C2410
+        select CPU_LLSERIAL_S3C2440
         select S3C2412_PM if PM
         select S3C2412_DMA if S3C2410_DMA
         help
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 6a8e4448770b..8543dd6df391 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -37,7 +37,7 @@
 #include <asm/hardware.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-gpio.h>
 
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 668cccefe7b0..4b9425c1bf72 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -24,14 +24,14 @@
 #include <asm/plat-s3c24xx/dma.h>
 #include <asm/plat-s3c24xx/cpu.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-ac97.h>
+#include <asm/plat-s3c/regs-ac97.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-sdi.h>
-#include <asm/arch/regs-iis.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-iis.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 
 #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
 
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index 063af09f899d..b126a530daa6 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -32,12 +32,12 @@
 #include <asm/mach-types.h>
 
 //#include <asm/debug-ll.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-lcd.h>
 
 #include <asm/arch/idle.h>
-#include <asm/arch/udc.h>
+#include <asm/plat-s3c24xx/udc.h>
 #include <asm/arch/fb.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index f2fbd65956ac..32982547cd63 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -33,14 +33,14 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-lcd.h>
 
 #include <asm/arch/idle.h>
 #include <asm/arch/fb.h>
 
-#include <asm/arch/nand.h>
+#include <asm/plat-s3c/nand.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/s3c2412.h>
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index 782b5814ced2..e0ccb404623f 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -34,12 +34,12 @@
 #include <asm/arch/idle.h>
 
 #include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-power.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-gpioj.h>
 #include <asm/arch/regs-dsc.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 #include <asm/arch/regs-s3c2412.h>
 
 #include <asm/plat-s3c24xx/s3c2412.h>
@@ -63,7 +63,6 @@ static inline void s3c2412_init_gpio2(void)
 
 static struct map_desc s3c2412_iodesc[] __initdata = {
         IODESC_ENT(CLKPWR),
-        IODESC_ENT(LCD),
         IODESC_ENT(TIMER),
         IODESC_ENT(WATCHDOG),
 };
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index e3bfda098c0f..f1915bd61d15 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -12,6 +12,7 @@ config CPU_S3C2440
         select S3C2410_GPIO
         select S3C2440_DMA if S3C2410_DMA
         select CPU_S3C244X
+        select CPU_LLSERIAL_S3C2440
         help
           Support for S3C2440 Samsung Mobile CPU based systems.
 
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index cd035a3ec878..f509f062e749 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -23,14 +23,14 @@
 #include <asm/plat-s3c24xx/dma.h>
 #include <asm/plat-s3c24xx/cpu.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-ac97.h>
+#include <asm/plat-s3c/regs-ac97.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-sdi.h>
-#include <asm/arch/regs-iis.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-iis.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 
 static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
         [DMACH_XD0] = {
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 29c163d300d4..3d3dfa95db8e 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -34,11 +34,11 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
-#include <asm/arch/nand.h>
+#include <asm/plat-s3c/nand.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 5e61f2166c76..afe0d7b7e389 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -36,7 +36,7 @@
 
 //#include <asm/debug-ll.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/s3c2440.h>
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 89f4c9c5777b..0ba7e9060c7b 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -31,11 +31,11 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
-#include <asm/arch/nand.h>
+#include <asm/plat-s3c/nand.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index 866ff71c01dd..b59e6d39f2f2 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -38,12 +38,12 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-lcd.h>
 
 #include <asm/arch/h1940.h>
-#include <asm/arch/nand.h>
+#include <asm/plat-s3c/nand.h>
 #include <asm/arch/fb.h>
 
 #include <asm/plat-s3c24xx/clock.h>
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index e167254e232e..670115b8a12e 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -31,7 +31,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-lcd.h>
 
diff --git a/arch/arm/mach-s3c2442/Kconfig b/arch/arm/mach-s3c2442/Kconfig
index bf8d87abfab3..88d5fd34fe3b 100644
--- a/arch/arm/mach-s3c2442/Kconfig
+++ b/arch/arm/mach-s3c2442/Kconfig
@@ -11,6 +11,7 @@ config CPU_S3C2442
         select S3C2410_GPIO
         select S3C2410_PM if PM
         select CPU_S3C244X
+        select CPU_LLSERIAL_S3C2440
         help
           Support for S3C2442 Samsung Mobile CPU based systems.
 
diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig
index c649bb2e7ce8..14252f573754 100644
--- a/arch/arm/mach-s3c2443/Kconfig
+++ b/arch/arm/mach-s3c2443/Kconfig
@@ -8,6 +8,7 @@ config CPU_S3C2443
         bool
         depends on ARCH_S3C2410
         select S3C2443_DMA if S3C2410_DMA
+        select CPU_LLSERIAL_S3C2440
         help
           Support for the S3C2443 SoC from the S3C24XX line
 
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index f70e8ccffc3d..fc3ede82af8f 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -24,14 +24,14 @@
 #include <asm/plat-s3c24xx/dma.h>
 #include <asm/plat-s3c24xx/cpu.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-ac97.h>
+#include <asm/plat-s3c/regs-ac97.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-sdi.h>
-#include <asm/arch/regs-iis.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-iis.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 
 #define MAP(x) { \
                 [0]     = (x) | DMA_CH_VALID,   \
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index b1eb709ee65a..8cd93130ef36 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -31,7 +31,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-lcd.h>
 
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index cd67ab1b217b..f99d9013905f 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -101,6 +101,16 @@ config SA1100_JORNADA720
           handheld computer.  See <http://www.hp.com/jornada/products/720>
           for details.
 
+config SA1100_JORNADA720_SSP
+        bool "HP Jornada 720 Extended SSP driver"
+        select SA1100_SSP
+        depends on SA1100_JORNADA720
+        help
+          Say Y here if you have a HP Jornada 7xx handheld computer and you
+          want to access devices connected to the MCU. Those include the
+          keyboard, touchscreen, backlight and battery. This driver also activates
+          the generic SSP which it extends.
+
 config SA1100_HACKKIT
         bool "HackKit Core CPU Board"
         help
@@ -145,8 +155,7 @@ config SA1100_SSP
         help
           Say Y here to enable support for the generic PIO SSP driver.
           This isn't for audio support, but for attached sensors and
-          other devices, eg for BadgePAD 4 sensor support, or Jornada
-          720 touchscreen support.
+          other devices, eg for BadgePAD 4 sensor support.
 
 config H3600_SLEEVE
         tristate "Compaq iPAQ Handheld sleeve support"
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index e27f15042a22..7a61e8d33ab7 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_SA1100_HACKKIT)		+= hackkit.o
 led-$(CONFIG_SA1100_HACKKIT)            += leds-hackkit.o
 
 obj-$(CONFIG_SA1100_JORNADA720)         += jornada720.o
+obj-$(CONFIG_SA1100_JORNADA720_SSP)     += jornada720_ssp.o
 
 obj-$(CONFIG_SA1100_LART)               += lart.o
 led-$(CONFIG_SA1100_LART)               += leds-lart.o
@@ -51,3 +52,4 @@ obj-$(CONFIG_LEDS) += $(led-y)
 # Miscelaneous functions
 obj-$(CONFIG_PM)                        += pm.o sleep.o
 obj-$(CONFIG_SA1100_SSP)                += ssp.o
+
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
new file mode 100644
index 000000000000..0a45e1ac8ad6
--- /dev/null
+++ b/arch/arm/mach-sa1100/jornada720_ssp.c
@@ -0,0 +1,201 @@
+/**
+ *  arch/arm/mac-sa1100/jornada720_ssp.c
+ *
+ *  Copyright (C) 2006/2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
+ *   Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  SSP driver for the HP Jornada 710/720/728
+ */
+
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+
+#include <asm/hardware.h>
+#include <asm/hardware/ssp.h>
+#include <asm/arch/jornada720.h>
+
+static DEFINE_SPINLOCK(jornada_ssp_lock);
+static unsigned long jornada_ssp_flags;
+
+/**
+ * jornada_ssp_reverse - reverses input byte
+ *
+ * we need to reverse all data we recieve from the mcu due to its physical location
+ * returns : 01110111 -> 11101110
+ */
+u8 inline jornada_ssp_reverse(u8 byte)
+{
+        return
+                ((0x80 & byte) >> 7) |
+                ((0x40 & byte) >> 5) |
+                ((0x20 & byte) >> 3) |
+                ((0x10 & byte) >> 1) |
+                ((0x08 & byte) << 1) |
+                ((0x04 & byte) << 3) |
+                ((0x02 & byte) << 5) |
+                ((0x01 & byte) << 7);
+};
+EXPORT_SYMBOL(jornada_ssp_reverse);
+
+/**
+ * jornada_ssp_byte - waits for ready ssp bus and sends byte
+ *
+ * waits for fifo buffer to clear and then transmits, if it doesn't then we will
+ * timeout after <timeout> rounds. Needs mcu running before its called.
+ *
+ * returns : %mcu output on success
+ *         : %-ETIMEOUT on timeout
+ */
+int jornada_ssp_byte(u8 byte)
+{
+        int timeout = 400000;
+        u16 ret;
+
+        while ((GPLR & GPIO_GPIO10)) {
+                if (!--timeout) {
+                        printk(KERN_WARNING "SSP: timeout while waiting for transmit\n");
+                        return -ETIMEDOUT;
+                }
+                cpu_relax();
+        }
+
+        ret = jornada_ssp_reverse(byte) << 8;
+
+        ssp_write_word(ret);
+        ssp_read_word(&ret);
+
+        return jornada_ssp_reverse(ret);
+};
+EXPORT_SYMBOL(jornada_ssp_byte);
+
+/**
+ * jornada_ssp_inout - decide if input is command or trading byte
+ *
+ * returns : (jornada_ssp_byte(byte)) on success
+ *         : %-ETIMEOUT on timeout failure
+ */
+int jornada_ssp_inout(u8 byte)
+{
+        int ret, i;
+
+        /* true means command byte */
+        if (byte != TXDUMMY) {
+                ret = jornada_ssp_byte(byte);
+                /* Proper return to commands is TxDummy */
+                if (ret != TXDUMMY) {
+                        for (i = 0; i < 256; i++)/* flushing bus */
+                                if (jornada_ssp_byte(TXDUMMY) == -1)
+                                        break;
+                        return -ETIMEDOUT;
+                }
+        } else /* Exchange TxDummy for data */
+                ret = jornada_ssp_byte(TXDUMMY);
+
+        return ret;
+};
+EXPORT_SYMBOL(jornada_ssp_inout);
+
+/**
+ * jornada_ssp_start - enable mcu
+ *
+ */
+int jornada_ssp_start()
+{
+        spin_lock_irqsave(&jornada_ssp_lock, jornada_ssp_flags);
+        GPCR = GPIO_GPIO25;
+        udelay(50);
+        return 0;
+};
+EXPORT_SYMBOL(jornada_ssp_start);
+
+/**
+ * jornada_ssp_end - disable mcu and turn off lock
+ *
+ */
+int jornada_ssp_end()
+{
+        GPSR = GPIO_GPIO25;
+        spin_unlock_irqrestore(&jornada_ssp_lock, jornada_ssp_flags);
+        return 0;
+};
+EXPORT_SYMBOL(jornada_ssp_end);
+
+static int __init jornada_ssp_probe(struct platform_device *dev)
+{
+        int ret;
+
+        GPSR = GPIO_GPIO25;
+
+        ret = ssp_init();
+
+        /* worked fine, lets not bother with anything else */
+        if (!ret) {
+                printk(KERN_INFO "SSP: device initialized with irq\n");
+                return ret;
+        }
+
+        printk(KERN_WARNING "SSP: initialization failed, trying non-irq solution \n");
+
+        /* init of Serial 4 port */
+        Ser4MCCR0 = 0;
+        Ser4SSCR0 = 0x0387;
+        Ser4SSCR1 = 0x18;
+
+        /* clear out any left over data */
+        ssp_flush();
+
+        /* enable MCU */
+        jornada_ssp_start();
+
+        /* see if return value makes sense */
+        ret = jornada_ssp_inout(GETBRIGHTNESS);
+
+        /* seems like it worked, just feed it with TxDummy to get rid of data */
+        if (ret == TxDummy)
+                jornada_ssp_inout(TXDUMMY);
+
+        jornada_ssp_end();
+
+        /* failed, lets just kill everything */
+        if (ret == -ETIMEDOUT) {
+                printk(KERN_WARNING "SSP: attempts failed, bailing\n");
+                ssp_exit();
+                return -ENODEV;
+        }
+
+        /* all fine */
+        printk(KERN_INFO "SSP: device initialized\n");
+        return 0;
+};
+
+static int jornada_ssp_remove(struct platform_device *dev)
+{
+        /* Note that this doesnt actually remove the driver, since theres nothing to remove
+         * It just makes sure everything is turned off */
+        GPSR = GPIO_GPIO25;
+        ssp_exit();
+        return 0;
+};
+
+struct platform_driver jornadassp_driver = {
+        .probe  = jornada_ssp_probe,
+        .remove = jornada_ssp_remove,
+        .driver = {
+                .name   = "jornada_ssp",
+        },
+};
+
+static int __init jornada_ssp_init(void)
+{
+        return platform_driver_register(&jornadassp_driver);
+}
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index 3a0a1ee2542d..9f1ed1509301 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -292,6 +292,8 @@ static struct platform_device *devices[] __initdata = {
         &smc91x_device,
 };
 
+extern void sa1110_mb_disable(void);
+
 static int __init neponset_init(void)
 {
         platform_driver_register(&neponset_device_driver);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e7904bc92c73..12161ae445da 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -345,13 +345,14 @@ config CPU_XSC3
 # ARMv6
 config CPU_V6
         bool "Support ARM V6 processor"
-        depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
+        depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3
+        default y if ARCH_MX3
         select CPU_32v6
         select CPU_ABRT_EV6
         select CPU_CACHE_V6
         select CPU_CACHE_VIPT
         select CPU_CP15_MMU
-        select CPU_HAS_ASID
+        select CPU_HAS_ASID if MMU
         select CPU_COPY_V6 if MMU
         select CPU_TLB_V6 if MMU
 
@@ -359,7 +360,7 @@ config CPU_V6
 config CPU_32v6K
         bool "Support ARM V6K processor extensions" if !SMP
         depends on CPU_V6
-        default y if SMP
+        default y if SMP && !ARCH_MX3
         help
           Say Y here if your ARMv6 processor supports the 'K' extension.
           This enables the kernel to use some instructions not present
@@ -377,7 +378,7 @@ config CPU_V7
         select CPU_CACHE_V7
         select CPU_CACHE_VIPT
         select CPU_CP15_MMU
-        select CPU_HAS_ASID
+        select CPU_HAS_ASID if MMU
         select CPU_COPY_V6 if MMU
         select CPU_TLB_V7 if MMU
 
@@ -405,6 +406,7 @@ config CPU_32v5
 
 config CPU_32v6
         bool
+        select TLS_REG_EMUL if !CPU_32v6K && !MMU
 
 config CPU_32v7
         bool
@@ -598,7 +600,7 @@ config CPU_DCACHE_SIZE
 
 config CPU_DCACHE_WRITETHROUGH
         bool "Force write through D-cache"
-        depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
+        depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
         default y if CPU_ARM925T
         help
           Say Y here to use the data cache in writethrough mode. Unless you
@@ -611,12 +613,6 @@ config CPU_CACHE_ROUND_ROBIN
           Say Y here to use the predictable round-robin cache replacement
           policy.  Unless you specifically require this or are unsure, say N.
 
-config CPU_L2CACHE_DISABLE
-        bool "Disable level 2 cache"
-        depends on CPU_V7
-        help
-          Say Y here to disable the level 2 cache.  If unsure, say N.
-
 config CPU_BPREDICT_DISABLE
         bool "Disable branch prediction"
         depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 08a36f1b35d2..b4e9b734e0bd 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -17,6 +17,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
 #include <linux/init.h>
+#include <linux/spinlock.h>
 
 #include <asm/cacheflush.h>
 #include <asm/io.h>
@@ -25,14 +26,19 @@
 #define CACHE_LINE_SIZE         32
 
 static void __iomem *l2x0_base;
+static DEFINE_SPINLOCK(l2x0_lock);
 
 static inline void sync_writel(unsigned long val, unsigned long reg,
                                unsigned long complete_mask)
 {
+        unsigned long flags;
+
+        spin_lock_irqsave(&l2x0_lock, flags);
         writel(val, l2x0_base + reg);
         /* wait for the operation to complete */
         while (readl(l2x0_base + reg) & complete_mask)
                 ;
+        spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
 static inline void cache_sync(void)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 3b5e47dc0c97..e5d61ee3d4a1 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -114,6 +114,10 @@ static void __init early_cachepolicy(char **p)
         }
         if (i == ARRAY_SIZE(cache_policies))
                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
+        if (cpu_architecture() >= CPU_ARCH_ARMv6) {
+                printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
+                cachepolicy = CPOLICY_WRITEBACK;
+        }
         flush_cache_all();
         set_cr(cr_alignment);
 }
@@ -252,13 +256,15 @@ static void __init build_mem_type_table(void)
         int cpu_arch = cpu_architecture();
         int i;
 
+        if (cpu_arch < CPU_ARCH_ARMv6) {
 #if defined(CONFIG_CPU_DCACHE_DISABLE)
-        if (cachepolicy > CPOLICY_BUFFERED)
-                cachepolicy = CPOLICY_BUFFERED;
+                if (cachepolicy > CPOLICY_BUFFERED)
+                        cachepolicy = CPOLICY_BUFFERED;
 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
-        if (cachepolicy > CPOLICY_WRITETHROUGH)
-                cachepolicy = CPOLICY_WRITETHROUGH;
+                if (cachepolicy > CPOLICY_WRITETHROUGH)
+                        cachepolicy = CPOLICY_WRITETHROUGH;
 #endif
+        }
         if (cpu_arch < CPU_ARCH_ARMv5) {
                 if (cachepolicy >= CPOLICY_WRITEALLOC)
                         cachepolicy = CPOLICY_WRITEBACK;
diff --git a/arch/arm/mm/proc-syms.c b/arch/arm/mm/proc-syms.c
index 9f396b4fa0b7..2b5ba396e3a6 100644
--- a/arch/arm/mm/proc-syms.c
+++ b/arch/arm/mm/proc-syms.c
@@ -31,12 +31,14 @@ EXPORT_SYMBOL(__cpuc_coherent_kern_range);
 EXPORT_SYMBOL(cpu_cache);
 #endif
 
+#ifdef CONFIG_MMU
 #ifndef MULTI_USER
 EXPORT_SYMBOL(__cpu_clear_user_page);
 EXPORT_SYMBOL(__cpu_copy_user_page);
 #else
 EXPORT_SYMBOL(cpu_user);
 #endif
+#endif
 
 /*
  * No module should need to touch the TLB (and currently
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 718f4782ee8b..e0acc5ae6f6f 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -77,6 +77,7 @@ ENTRY(cpu_v7_dcache_clean_area)
  *      - we are not using split page tables
  */
 ENTRY(cpu_v7_switch_mm)
+#ifdef CONFIG_MMU
         mov     r2, #0
         ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
         orr     r0, r0, #TTB_RGN_OC_WB          @ mark PTWs outer cacheable, WB
@@ -86,6 +87,7 @@ ENTRY(cpu_v7_switch_mm)
         isb
         mcr     p15, 0, r1, c13, c0, 1          @ set context ID
         isb
+#endif
         mov     pc, lr
 
 /*
@@ -109,6 +111,7 @@ ENTRY(cpu_v7_switch_mm)
  *        1111   0   1   1      r/w     r/w
  */
 ENTRY(cpu_v7_set_pte_ext)
+#ifdef CONFIG_MMU
         str     r1, [r0], #-2048                @ linux version
 
         bic     r3, r1, #0x000003f0
@@ -136,6 +139,7 @@ ENTRY(cpu_v7_set_pte_ext)
 
         str     r3, [r0]
         mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
+#endif
         mov     pc, lr
 
 cpu_v7_name:
@@ -169,6 +173,7 @@ __v7_setup:
         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
 #endif
         dsb
+#ifdef CONFIG_MMU
         mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
         mcr     p15, 0, r10, c2, c0, 2          @ TTB control register
         orr     r4, r4, #TTB_RGN_OC_WB          @ mark PTWs outer cacheable, WB
@@ -176,21 +181,12 @@ __v7_setup:
         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
         mov     r10, #0x1f                      @ domains 0, 1 = manager
         mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
-#ifndef CONFIG_CPU_L2CACHE_DISABLE
-        @ L2 cache configuration in the L2 aux control register
-        mrc     p15, 1, r10, c9, c0, 2
-        bic     r10, r10, #(1 << 16)            @ L2 outer cache
-        mcr     p15, 1, r10, c9, c0, 2
-        @ L2 cache is enabled in the aux control register
-        mrc     p15, 0, r10, c1, c0, 1
-        orr     r10, r10, #2
-        mcr     p15, 0, r10, c1, c0, 1
 #endif
-        mrc     p15, 0, r0, c1, c0, 0           @ read control register
-        ldr     r10, cr1_clear                  @ get mask for bits to clear
-        bic     r0, r0, r10                     @ clear bits them
-        ldr     r10, cr1_set                    @ get mask for bits to set
-        orr     r0, r0, r10                     @ set them
+        adr     r5, v7_crval
+        ldmia   r5, {r5, r6}
+        mrc     p15, 0, r0, c1, c0, 0           @ read control register
+        bic     r0, r0, r5                      @ clear bits them
+        orr     r0, r0, r6                      @ set them
         mov     pc, lr                          @ return to head.S:__ret
 
         /*
@@ -199,12 +195,9 @@ __v7_setup:
          * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
          *         0 110       0011 1.00 .111 1101 < we want
          */
-        .type   cr1_clear, #object
-        .type   cr1_set, #object
-cr1_clear:
-        .word   0x0120c302
-cr1_set:
-        .word   0x00c0387d
+        .type   v7_crval, #object
+v7_crval:
+        crval   clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c
 
 __v7_setup_stack:
         .space  4 * 11                          @ 11 registers
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 100d57ad98ed..ba3d21d8fba3 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -78,6 +78,13 @@ static struct irqaction iop_timer_irq = {
         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 };
 
+static unsigned long iop_tick_rate;
+unsigned long get_iop_tick_rate(void)
+{
+        return iop_tick_rate;
+}
+EXPORT_SYMBOL(get_iop_tick_rate);
+
 void __init iop_init_time(unsigned long tick_rate)
 {
         u32 timer_ctl;
@@ -85,6 +92,7 @@ void __init iop_init_time(unsigned long tick_rate)
         ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
         ticks_per_usec = tick_rate / 1000000;
         next_jiffy_time = 0xffffffff;
+        iop_tick_rate = tick_rate;
 
         timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
                         IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
new file mode 100644
index 000000000000..03a65c0dfb60
--- /dev/null
+++ b/arch/arm/plat-mxc/Kconfig
@@ -0,0 +1,20 @@
+if ARCH_MXC
+
+menu "Freescale MXC Implementations"
+
+choice
+        prompt "MXC/iMX System Type"
+        default 0
+
+config ARCH_MX3
+        bool "MX3-based"
+        help
+          This enables support for systems based on the Freescale i.MX3 family
+
+endchoice
+
+source "arch/arm/mach-mx3/Kconfig"
+
+endmenu
+
+endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
new file mode 100644
index 000000000000..66ad9c2b6d64
--- /dev/null
+++ b/arch/arm/plat-mxc/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Common support
+obj-y := irq.o
+
+obj-m :=
+obj-n :=
+obj-  :=
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
new file mode 100644
index 000000000000..87d253bc3d3c
--- /dev/null
+++ b/arch/arm/plat-mxc/irq.c
@@ -0,0 +1,83 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+#include <asm/arch/common.h>
+
+/*!
+ * Disable interrupt number "irq" in the AVIC
+ *
+ * @param  irq          interrupt source number
+ */
+static void mxc_mask_irq(unsigned int irq)
+{
+        __raw_writel(irq, AVIC_INTDISNUM);
+}
+
+/*!
+ * Enable interrupt number "irq" in the AVIC
+ *
+ * @param  irq          interrupt source number
+ */
+static void mxc_unmask_irq(unsigned int irq)
+{
+        __raw_writel(irq, AVIC_INTENNUM);
+}
+
+static struct irq_chip mxc_avic_chip = {
+        .mask_ack = mxc_mask_irq,
+        .mask = mxc_mask_irq,
+        .unmask = mxc_unmask_irq,
+};
+
+/*!
+ * This function initializes the AVIC hardware and disables all the
+ * interrupts. It registers the interrupt enable and disable functions
+ * to the kernel for each interrupt source.
+ */
+void __init mxc_init_irq(void)
+{
+        int i;
+        u32 reg;
+
+        /* put the AVIC into the reset value with
+         * all interrupts disabled
+         */
+        __raw_writel(0, AVIC_INTCNTL);
+        __raw_writel(0x1f, AVIC_NIMASK);
+
+        /* disable all interrupts */
+        __raw_writel(0, AVIC_INTENABLEH);
+        __raw_writel(0, AVIC_INTENABLEL);
+
+        /* all IRQ no FIQ */
+        __raw_writel(0, AVIC_INTTYPEH);
+        __raw_writel(0, AVIC_INTTYPEL);
+        for (i = 0; i < MXC_MAX_INT_LINES; i++) {
+                set_irq_chip(i, &mxc_avic_chip);
+                set_irq_handler(i, handle_level_irq);
+                set_irq_flags(i, IRQF_VALID);
+        }
+
+        /* Set WDOG2's interrupt the highest priority level (bit 28-31) */
+        reg = __raw_readl(AVIC_NIPRIORITY6);
+        reg |= (0xF << 28);
+        __raw_writel(reg, AVIC_NIPRIORITY6);
+
+        printk(KERN_INFO "MXC IRQ initialized\n");
+}
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig
new file mode 100644
index 000000000000..31656c33e05e
--- /dev/null
+++ b/arch/arm/plat-s3c/Kconfig
@@ -0,0 +1,104 @@
+# arch/arm/plat-s3c/Kconfig
+#
+# Copyright 2007 Simtec Electronics
+#
+# Licensed under GPLv2
+
+config PLAT_S3C
+        bool
+        depends on ARCH_S3C2410
+        default y if ARCH_S3C2410
+        select NO_IOPORT
+        help
+          Base platform code for any Samsung S3C device
+
+# low-level serial option nodes
+
+config CPU_LLSERIAL_S3C2410_ONLY
+        bool
+        depends on ARCH_S3C2410
+        default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
+
+config CPU_LLSERIAL_S3C2440_ONLY
+        bool
+        depends on ARCH_S3C2410
+        default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
+
+config CPU_LLSERIAL_S3C2410
+        bool
+        depends on ARCH_S3C2410
+        help
+          Selected if there is an S3C2410 (or register compatible) serial
+          low-level implementation needed
+
+config CPU_LLSERIAL_S3C2440
+        bool
+        depends on ARCH_S3C2410
+        help
+          Selected if there is an S3C2440 (or register compatible) serial
+          low-level implementation needed
+
+# boot configurations
+
+comment "Boot options"
+
+config S3C_BOOT_WATCHDOG
+        bool "S3C Initialisation watchdog"
+        depends on PLAT_S3C && S3C2410_WATCHDOG
+        help
+          Say y to enable the watchdog during the kernel decompression
+          stage. If the kernel fails to uncompress, then the watchdog
+          will trigger a reset and the system should restart.
+
+config S3C_BOOT_ERROR_RESET
+        bool "S3C Reboot on decompression error"
+        depends on PLAT_S3C
+        help
+          Say y here to use the watchdog to reset the system if the
+          kernel decompressor detects an error during decompression.
+
+comment "Power management"
+
+config S3C2410_PM_DEBUG
+        bool "S3C2410 PM Suspend debug"
+        depends on PLAT_S3C && PM
+        help
+          Say Y here if you want verbose debugging from the PM Suspend and
+          Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
+          for more information.
+
+config S3C2410_PM_CHECK
+        bool "S3C2410 PM Suspend Memory CRC"
+        depends on PLAT_S3C && PM && CRC32
+        help
+          Enable the PM code's memory area checksum over sleep. This option
+          will generate CRCs of all blocks of memory, and store them before
+          going to sleep. The blocks are then checked on resume for any
+          errors.
+
+          Note, this can take several seconds depending on memory size
+          and CPU speed.
+
+          See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
+
+config S3C2410_PM_CHECK_CHUNKSIZE
+        int "S3C2410 PM Suspend CRC Chunksize (KiB)"
+        depends on PLAT_S3C && PM && S3C2410_PM_CHECK
+        default 64
+        help
+          Set the chunksize in Kilobytes of the CRC for checking memory
+          corruption over suspend and resume. A smaller value will mean that
+          the CRC data block will take more memory, but wil identify any
+          faults with better precision.
+
+          See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
+
+config S3C_LOWLEVEL_UART_PORT
+        int "S3C UART to use for low-level messages"
+        depends on PLAT_S3C
+        default 0
+        help
+          Choice of which UART port to use for the low-level messages,
+          such as the `Uncompressing...` at start time. The value of
+          this configuration should be between zero and two. The port
+          must have been initialised by the boot-loader before use.
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index b972f36d547c..b66fb3c4e228 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -10,7 +10,7 @@ config PLAT_S3C24XX
         default y if ARCH_S3C2410
         select NO_IOPORT
         help
-          Base platform code for any Samsung S3C device
+          Base platform code for any Samsung S3C24XX device
 
 if PLAT_S3C24XX
 
@@ -26,64 +26,6 @@ config PM_SIMTEC
           Common power management code for systems that are
           compatible with the Simtec style of power management
 
-config S3C2410_BOOT_WATCHDOG
-        bool "S3C2410 Initialisation watchdog"
-        depends on ARCH_S3C2410 && S3C2410_WATCHDOG
-        help
-          Say y to enable the watchdog during the kernel decompression
-          stage. If the kernel fails to uncompress, then the watchdog
-          will trigger a reset and the system should restart.
-
-config S3C2410_BOOT_ERROR_RESET
-        bool "S3C2410 Reboot on decompression error"
-        depends on ARCH_S3C2410
-        help
-          Say y here to use the watchdog to reset the system if the
-          kernel decompressor detects an error during decompression.
-
-config S3C2410_PM_DEBUG
-        bool "S3C2410 PM Suspend debug"
-        depends on ARCH_S3C2410 && PM
-        help
-          Say Y here if you want verbose debugging from the PM Suspend and
-          Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
-          for more information.
-
-config S3C2410_PM_CHECK
-        bool "S3C2410 PM Suspend Memory CRC"
-        depends on ARCH_S3C2410 && PM && CRC32
-        help
-          Enable the PM code's memory area checksum over sleep. This option
-          will generate CRCs of all blocks of memory, and store them before
-          going to sleep. The blocks are then checked on resume for any
-          errors.
-
-          Note, this can take several seconds depending on memory size
-          and CPU speed.
-
-          See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
-
-config S3C2410_PM_CHECK_CHUNKSIZE
-        int "S3C2410 PM Suspend CRC Chunksize (KiB)"
-        depends on ARCH_S3C2410 && PM && S3C2410_PM_CHECK
-        default 64
-        help
-          Set the chunksize in Kilobytes of the CRC for checking memory
-          corruption over suspend and resume. A smaller value will mean that
-          the CRC data block will take more memory, but wil identify any
-          faults with better precision.
-
-          See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
-
-config S3C2410_LOWLEVEL_UART_PORT
-        int "S3C2410 UART to use for low-level messages"
-        default 0
-        help
-          Choice of which UART port to use for the low-level messages,
-          such as the `Uncompressing...` at start time. The value of
-          this configuration should be between zero and two. The port
-          must have been initialised by the boot-loader before use.
-
 config S3C2410_DMA
         bool "S3C2410 DMA support"
         depends on ARCH_S3C2410
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 7ed19b23ce56..398c7ac25296 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -38,7 +38,7 @@
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/leds-gpio.h>
 
-#include <asm/arch/nand.h>
+#include <asm/plat-s3c/nand.h>
 
 #include <asm/plat-s3c24xx/common-smdk.h>
 #include <asm/plat-s3c24xx/devs.h>
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 8ce4904d3131..f513ab083b8f 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -38,7 +38,7 @@
 #include <asm/mach/map.h>
 
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 #include <asm/plat-s3c24xx/cpu.h>
 #include <asm/plat-s3c24xx/devs.h>
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 5875da0ae0eb..e546e933b3f7 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -28,12 +28,12 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include <asm/arch/regs-serial.h>
-#include <asm/arch/udc.h>
+#include <asm/plat-s3c/regs-serial.h>
+#include <asm/plat-s3c24xx/udc.h>
 
 #include <asm/plat-s3c24xx/devs.h>
 #include <asm/plat-s3c24xx/cpu.h>
-#include <asm/arch/regs-spi.h>
+#include <asm/plat-s3c24xx/regs-spi.h>
 
 /* Serial port registrations */
 
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 5692eccdf4d1..eab1850616d8 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -40,7 +40,7 @@
 #include <asm/hardware.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-mem.h>
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c
index 767f2e9a3a55..3444b13afac5 100644
--- a/arch/arm/plat-s3c24xx/s3c244x.c
+++ b/arch/arm/plat-s3c24xx/s3c244x.c
@@ -30,7 +30,7 @@
 #include <asm/irq.h>
 
 #include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-gpioj.h>
 #include <asm/arch/regs-dsc.h>
@@ -47,7 +47,6 @@ static struct map_desc s3c244x_iodesc[] __initdata = {
         IODESC_ENT(CLKPWR),
         IODESC_ENT(TIMER),
         IODESC_ENT(WATCHDOG),
-        IODESC_ENT(LCD),
 };
 
 /* uart initialisation */
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
index 7b7ae790b00d..d47113bbc34c 100644
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -32,7 +32,7 @@
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 /* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
  * reset the UART configuration, only enable if you really need this!
diff --git a/arch/arm/plat-s3c24xx/time.c b/arch/arm/plat-s3c24xx/time.c
index b7667375bcec..2ec1daaa0e53 100644
--- a/arch/arm/plat-s3c24xx/time.c
+++ b/arch/arm/plat-s3c24xx/time.c
@@ -33,7 +33,7 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/arch/map.h>
-#include <asm/arch/regs-timer.h>
+#include <asm/plat-s3c/regs-timer.h>
 #include <asm/arch/regs-irq.h>
 #include <asm/mach/time.h>
 
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index d4b7b229631d..0ac022f800a1 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -74,14 +74,14 @@ vfp_support_entry:
 
         VFPFMRX r1, FPEXC               @ Is the VFP enabled?
         DBGSTR1 "fpexc %08x", r1
-        tst     r1, #FPEXC_ENABLE
+        tst     r1, #FPEXC_EN
         bne     look_for_VFP_exceptions @ VFP is already enabled
 
         DBGSTR1 "enable %x", r10
         ldr     r3, last_VFP_context_address
-        orr     r1, r1, #FPEXC_ENABLE   @ user FPEXC has the enable bit set
+        orr     r1, r1, #FPEXC_EN       @ user FPEXC has the enable bit set
         ldr     r4, [r3, r11, lsl #2]   @ last_VFP_context pointer
-        bic     r5, r1, #FPEXC_EXCEPTION @ make sure exceptions are disabled
+        bic     r5, r1, #FPEXC_EX       @ make sure exceptions are disabled
         cmp     r4, r10
         beq     check_for_exception     @ we are returning to the same
                                         @ process, so the registers are
@@ -124,7 +124,7 @@ no_old_VFP_process:
         VFPFMXR FPSCR, r5               @ restore status
 
 check_for_exception:
-        tst     r1, #FPEXC_EXCEPTION
+        tst     r1, #FPEXC_EX
         bne     process_exception       @ might as well handle the pending
                                         @ exception before retrying branch
                                         @ out before setting an FPEXC that
@@ -136,10 +136,10 @@ check_for_exception:
 
 
 look_for_VFP_exceptions:
-        tst     r1, #FPEXC_EXCEPTION
+        tst     r1, #FPEXC_EX
         bne     process_exception
         VFPFMRX r5, FPSCR
-        tst     r5, #FPSCR_IXE          @ IXE doesn't set FPEXC_EXCEPTION !
+        tst     r5, #FPSCR_IXE          @ IXE doesn't set FPEXC_EX !
         bne     process_exception
 
         @ Fall into hand on to next handler - appropriate coproc instr
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 1106b5f9cf19..04ddab2bd876 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -53,7 +53,7 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
                  * case the thread migrates to a different CPU. The
                  * restoring is done lazily.
                  */
-                if ((fpexc & FPEXC_ENABLE) && last_VFP_context[cpu]) {
+                if ((fpexc & FPEXC_EN) && last_VFP_context[cpu]) {
                         vfp_save_state(last_VFP_context[cpu], fpexc);
                         last_VFP_context[cpu]->hard.cpu = cpu;
                 }
@@ -70,7 +70,7 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
                  * Always disable VFP so we can lazily save/restore the
                  * old state.
                  */
-                fmxr(FPEXC, fpexc & ~FPEXC_ENABLE);
+                fmxr(FPEXC, fpexc & ~FPEXC_EN);
                 return NOTIFY_DONE;
         }
 
@@ -81,13 +81,13 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
                  */
                 memset(vfp, 0, sizeof(union vfp_state));
 
-                vfp->hard.fpexc = FPEXC_ENABLE;
+                vfp->hard.fpexc = FPEXC_EN;
                 vfp->hard.fpscr = FPSCR_ROUND_NEAREST;
 
                 /*
                  * Disable VFP to ensure we initialise it first.
                  */
-                fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_ENABLE);
+                fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
         }
 
         /* flush and release case: Per-thread VFP cleanup. */
@@ -229,7 +229,7 @@ void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
         /*
          * Enable access to the VFP so we can handle the bounce.
          */
-        fmxr(FPEXC, fpexc & ~(FPEXC_EXCEPTION|FPEXC_INV|FPEXC_UFC|FPEXC_IOC));
+        fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_INV|FPEXC_UFC|FPEXC_IOC));
 
         orig_fpscr = fpscr = fmrx(FPSCR);
 
@@ -248,7 +248,7 @@ void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
         /*
          * Modify fpscr to indicate the number of iterations remaining
          */
-        if (fpexc & FPEXC_EXCEPTION) {
+        if (fpexc & FPEXC_EX) {
                 u32 len;
 
                 len = fpexc + (1 << FPEXC_LENGTH_BIT);
diff --git a/drivers/char/watchdog/Kconfig b/drivers/char/watchdog/Kconfig
index 2f48ba329961..a4d81cda479e 100644
--- a/drivers/char/watchdog/Kconfig
+++ b/drivers/char/watchdog/Kconfig
@@ -187,6 +187,22 @@ config PNX4008_WATCHDOG
 
           Say N if you are unsure.
 
+config IOP_WATCHDOG
+        tristate "IOP Watchdog"
+        depends on WATCHDOG && PLAT_IOP
+        select WATCHDOG_NOWAYOUT if (ARCH_IOP32X || ARCH_IOP33X)
+        help
+          Say Y here if to include support for the watchdog timer
+          in the Intel IOP3XX & IOP13XX I/O Processors.  This driver can
+          be built as a module by choosing M. The module will
+          be called iop_wdt.
+
+          Note: The IOP13XX watchdog does an Internal Bus Reset which will
+          affect both cores and the peripherals of the IOP.  The ATU-X
+          and/or ATUe configuration registers will remain intact, but if
+          operating as an Root Complex and/or Central Resource, the PCI-X
+          and/or PCIe busses will also be reset.  THIS IS A VERY BIG HAMMER.
+
 # AVR32 Architecture
 
 config AT32AP700X_WDT
diff --git a/drivers/char/watchdog/Makefile b/drivers/char/watchdog/Makefile
index 3907ec04a4e5..bdb9d5e3bb41 100644
--- a/drivers/char/watchdog/Makefile
+++ b/drivers/char/watchdog/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_SA1100_WATCHDOG) += sa1100_wdt.o
 obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o
 obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o
 obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
+obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
 
 # AVR32 Architecture
 obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
diff --git a/drivers/char/watchdog/iop_wdt.c b/drivers/char/watchdog/iop_wdt.c
new file mode 100644
index 000000000000..bbbd91af754d
--- /dev/null
+++ b/drivers/char/watchdog/iop_wdt.c
@@ -0,0 +1,262 @@
+/*
+ * drivers/char/watchdog/iop_wdt.c
+ *
+ * WDT driver for Intel I/O Processors
+ * Copyright (C) 2005, Intel Corporation.
+ *
+ * Based on ixp4xx driver, Copyright 2004 (c) MontaVista, Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ *      Curt E Bruns <curt.e.bruns@intel.com>
+ *      Peter Milne <peter.milne@d-tacq.com>
+ *      Dan Williams <dan.j.williams@intel.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/uaccess.h>
+#include <asm/hardware.h>
+
+static int nowayout = WATCHDOG_NOWAYOUT;
+static unsigned long wdt_status;
+static unsigned long boot_status;
+
+#define WDT_IN_USE              0
+#define WDT_OK_TO_CLOSE         1
+#define WDT_ENABLED             2
+
+static unsigned long iop_watchdog_timeout(void)
+{
+        return (0xffffffffUL / get_iop_tick_rate());
+}
+
+/**
+ * wdt_supports_disable - determine if we are accessing a iop13xx watchdog
+ * or iop3xx by whether it has a disable command
+ */
+static int wdt_supports_disable(void)
+{
+        int can_disable;
+
+        if (IOP_WDTCR_EN_ARM != IOP_WDTCR_DIS_ARM)
+                can_disable = 1;
+        else
+                can_disable = 0;
+
+        return can_disable;
+}
+
+static void wdt_enable(void)
+{
+        /* Arm and enable the Timer to starting counting down from 0xFFFF.FFFF
+         * Takes approx. 10.7s to timeout
+         */
+        write_wdtcr(IOP_WDTCR_EN_ARM);
+        write_wdtcr(IOP_WDTCR_EN);
+}
+
+/* returns 0 if the timer was successfully disabled */
+static int wdt_disable(void)
+{
+        /* Stop Counting */
+        if (wdt_supports_disable()) {
+                write_wdtcr(IOP_WDTCR_DIS_ARM);
+                write_wdtcr(IOP_WDTCR_DIS);
+                clear_bit(WDT_ENABLED, &wdt_status);
+                printk(KERN_INFO "WATCHDOG: Disabled\n");
+                return 0;
+        } else
+                return 1;
+}
+
+static int iop_wdt_open(struct inode *inode, struct file *file)
+{
+        if (test_and_set_bit(WDT_IN_USE, &wdt_status))
+                return -EBUSY;
+
+        clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
+
+        wdt_enable();
+
+        set_bit(WDT_ENABLED, &wdt_status);
+
+        return nonseekable_open(inode, file);
+}
+
+static ssize_t
+iop_wdt_write(struct file *file, const char *data, size_t len,
+                  loff_t *ppos)
+{
+        if (len) {
+                if (!nowayout) {
+                        size_t i;
+
+                        clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
+
+                        for (i = 0; i != len; i++) {
+                                char c;
+
+                                if (get_user(c, data + i))
+                                        return -EFAULT;
+                                if (c == 'V')
+                                        set_bit(WDT_OK_TO_CLOSE, &wdt_status);
+                        }
+                }
+                wdt_enable();
+        }
+
+        return len;
+}
+
+static struct watchdog_info ident = {
+        .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
+        .identity = "iop watchdog",
+};
+
+static int
+iop_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
+                  unsigned long arg)
+{
+        int options;
+        int ret = -ENOTTY;
+
+        switch (cmd) {
+        case WDIOC_GETSUPPORT:
+                if (copy_to_user
+                    ((struct watchdog_info *)arg, &ident, sizeof ident))
+                        ret = -EFAULT;
+                else
+                        ret = 0;
+                break;
+
+        case WDIOC_GETSTATUS:
+                ret = put_user(0, (int *)arg);
+                break;
+
+        case WDIOC_GETBOOTSTATUS:
+                ret = put_user(boot_status, (int *)arg);
+                break;
+
+        case WDIOC_GETTIMEOUT:
+                ret = put_user(iop_watchdog_timeout(), (int *)arg);
+                break;
+
+        case WDIOC_KEEPALIVE:
+                wdt_enable();
+                ret = 0;
+                break;
+
+        case WDIOC_SETOPTIONS:
+                if (get_user(options, (int *)arg))
+                        return -EFAULT;
+
+                if (options & WDIOS_DISABLECARD) {
+                        if (!nowayout) {
+                                if (wdt_disable() == 0) {
+                                        set_bit(WDT_OK_TO_CLOSE, &wdt_status);
+                                        ret = 0;
+                                } else
+                                        ret = -ENXIO;
+                        } else
+                                ret = 0;
+                }
+
+                if (options & WDIOS_ENABLECARD) {
+                        wdt_enable();
+                        ret = 0;
+                }
+                break;
+        }
+
+        return ret;
+}
+
+static int iop_wdt_release(struct inode *inode, struct file *file)
+{
+        int state = 1;
+        if (test_bit(WDT_OK_TO_CLOSE, &wdt_status))
+                if (test_bit(WDT_ENABLED, &wdt_status))
+                        state = wdt_disable();
+
+        /* if the timer is not disbaled reload and notify that we are still
+         * going down
+         */
+        if (state != 0) {
+                wdt_enable();
+                printk(KERN_CRIT "WATCHDOG: Device closed unexpectedly - "
+                       "reset in %lu seconds\n", iop_watchdog_timeout());
+        }
+
+        clear_bit(WDT_IN_USE, &wdt_status);
+        clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
+
+        return 0;
+}
+
+static const struct file_operations iop_wdt_fops = {
+        .owner = THIS_MODULE,
+        .llseek = no_llseek,
+        .write = iop_wdt_write,
+        .ioctl = iop_wdt_ioctl,
+        .open = iop_wdt_open,
+        .release = iop_wdt_release,
+};
+
+static struct miscdevice iop_wdt_miscdev = {
+        .minor = WATCHDOG_MINOR,
+        .name = "watchdog",
+        .fops = &iop_wdt_fops,
+};
+
+static int __init iop_wdt_init(void)
+{
+        int ret;
+
+        ret = misc_register(&iop_wdt_miscdev);
+        if (ret == 0)
+                printk("iop watchdog timer: timeout %lu sec\n",
+                       iop_watchdog_timeout());
+
+        /* check if the reset was caused by the watchdog timer */
+        boot_status = (read_rcsr() & IOP_RCSR_WDT) ? WDIOF_CARDRESET : 0;
+
+        /* Configure Watchdog Timeout to cause an Internal Bus (IB) Reset
+         * NOTE: An IB Reset will Reset both cores in the IOP342
+         */
+        write_wdtsr(IOP13XX_WDTCR_IB_RESET);
+
+        return ret;
+}
+
+static void __exit iop_wdt_exit(void)
+{
+        misc_deregister(&iop_wdt_miscdev);
+}
+
+module_init(iop_wdt_init);
+module_exit(iop_wdt_exit);
+
+module_param(nowayout, int, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
+
+MODULE_AUTHOR("Curt E Bruns <curt.e.bruns@intel.com>");
+MODULE_DESCRIPTION("iop watchdog timer driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
diff --git a/drivers/net/arm/ether1.c b/drivers/net/arm/ether1.c
index f21148e7b579..80f33b6d5713 100644
--- a/drivers/net/arm/ether1.c
+++ b/drivers/net/arm/ether1.c
@@ -36,7 +36,6 @@
 #include <linux/types.h>
 #include <linux/fcntl.h>
 #include <linux/interrupt.h>
-#include <linux/ptrace.h>
 #include <linux/ioport.h>
 #include <linux/in.h>
 #include <linux/slab.h>
@@ -75,7 +74,7 @@ static void ether1_timeout(struct net_device *dev);
 
 /* ------------------------------------------------------------------------- */
 
-static char version[] __initdata = "ether1 ethernet driver (c) 2000 Russell King v1.07\n";
+static char version[] __devinitdata = "ether1 ethernet driver (c) 2000 Russell King v1.07\n";
 
 #define BUS_16 16
 #define BUS_8  8
diff --git a/drivers/net/arm/ether3.c b/drivers/net/arm/ether3.c
index a7cac695a9bd..3805506a3ab8 100644
--- a/drivers/net/arm/ether3.c
+++ b/drivers/net/arm/ether3.c
@@ -51,7 +51,6 @@
 #include <linux/types.h>
 #include <linux/fcntl.h>
 #include <linux/interrupt.h>
-#include <linux/ptrace.h>
 #include <linux/ioport.h>
 #include <linux/in.h>
 #include <linux/slab.h>
@@ -69,7 +68,7 @@
 #include <asm/ecard.h>
 #include <asm/io.h>
 
-static char version[] __initdata = "ether3 ethernet driver (c) 1995-2000 R.M.King v1.17\n";
+static char version[] __devinitdata = "ether3 ethernet driver (c) 1995-2000 R.M.King v1.17\n";
 
 #include "ether3.h"
 
diff --git a/drivers/net/arm/etherh.c b/drivers/net/arm/etherh.c
index 769ba69451f4..0d37d9d1fd78 100644
--- a/drivers/net/arm/etherh.c
+++ b/drivers/net/arm/etherh.c
@@ -31,7 +31,6 @@
 #include <linux/types.h>
 #include <linux/fcntl.h>
 #include <linux/interrupt.h>
-#include <linux/ptrace.h>
 #include <linux/ioport.h>
 #include <linux/in.h>
 #include <linux/slab.h>
diff --git a/drivers/scsi/arm/cumana_1.c b/drivers/scsi/arm/cumana_1.c
index cf9a21cea6d9..49d838e90a24 100644
--- a/drivers/scsi/arm/cumana_1.c
+++ b/drivers/scsi/arm/cumana_1.c
@@ -24,7 +24,7 @@
 
 #define CUMANASCSI_PUBLIC_RELEASE 1
 
-#define NCR5380_implementation_fields   int port, ctrl
+#define priv(host)                      ((struct NCR5380_hostdata *)(host)->hostdata)
 #define NCR5380_local_declare()         struct Scsi_Host *_instance
 #define NCR5380_setup(instance)         _instance = instance
 #define NCR5380_read(reg)               cumanascsi_read(_instance, reg)
@@ -33,6 +33,11 @@
 #define NCR5380_queue_command           cumanascsi_queue_command
 #define NCR5380_proc_info               cumanascsi_proc_info
 
+#define NCR5380_implementation_fields   \
+        unsigned ctrl;                  \
+        void __iomem *base;             \
+        void __iomem *dma
+
 #define BOARD_NORMAL    0
 #define BOARD_NCR53C400 1
 
@@ -47,192 +52,162 @@ const char *cumanascsi_info(struct Scsi_Host *spnt)
         return "";
 }
 
-#ifdef NOT_EFFICIENT
-#define CTRL(p,v)     outb(*ctrl = (v), (p) - 577)
-#define STAT(p)       inb((p)+1)
-#define IN(p)         inb((p))
-#define OUT(v,p)      outb((v), (p))
-#else
-#define CTRL(p,v)       (p[-2308] = (*ctrl = (v)))
-#define STAT(p)         (p[4])
-#define IN(p)           (*(p))
-#define IN2(p)          ((unsigned short)(*(volatile unsigned long *)(p)))
-#define OUT(v,p)        (*(p) = (v))
-#define OUT2(v,p)       (*((volatile unsigned long *)(p)) = (v))
-#endif
-#define L(v)            (((v)<<16)|((v) & 0x0000ffff))
-#define H(v)            (((v)>>16)|((v) & 0xffff0000))
+#define CTRL    0x16fc
+#define STAT    0x2004
+#define L(v)    (((v)<<16)|((v) & 0x0000ffff))
+#define H(v)    (((v)>>16)|((v) & 0xffff0000))
 
 static inline int
-NCR5380_pwrite(struct Scsi_Host *instance, unsigned char *addr, int len)
+NCR5380_pwrite(struct Scsi_Host *host, unsigned char *addr, int len)
 {
-  int *ctrl = &((struct NCR5380_hostdata *)instance->hostdata)->ctrl;
-  int oldctrl = *ctrl;
   unsigned long *laddr;
-#ifdef NOT_EFFICIENT
-  int iobase = instance->io_port;
-  int dma_io = iobase & ~(0x3C0000>>2);
-#else
-  volatile unsigned char *iobase = (unsigned char *)ioaddr(instance->io_port);
-  volatile unsigned char *dma_io = (unsigned char *)((int)iobase & ~0x3C0000);
-#endif
+  void __iomem *dma = priv(host)->dma + 0x2000;
 
   if(!len) return 0;
 
-  CTRL(iobase, 0x02);
+  writeb(0x02, priv(host)->base + CTRL);
   laddr = (unsigned long *)addr;
   while(len >= 32)
   {
-    int status;
+    unsigned int status;
     unsigned long v;
-    status = STAT(iobase);
+    status = readb(priv(host)->base + STAT);
     if(status & 0x80)
       goto end;
     if(!(status & 0x40))
       continue;
-    v=*laddr++; OUT2(L(v),dma_io); OUT2(H(v),dma_io);
-    v=*laddr++; OUT2(L(v),dma_io); OUT2(H(v),dma_io);
-    v=*laddr++; OUT2(L(v),dma_io); OUT2(H(v),dma_io);
-    v=*laddr++; OUT2(L(v),dma_io); OUT2(H(v),dma_io);
-    v=*laddr++; OUT2(L(v),dma_io); OUT2(H(v),dma_io);
-    v=*laddr++; OUT2(L(v),dma_io); OUT2(H(v),dma_io);
-    v=*laddr++; OUT2(L(v),dma_io); OUT2(H(v),dma_io);
-    v=*laddr++; OUT2(L(v),dma_io); OUT2(H(v),dma_io);
+    v=*laddr++; writew(L(v), dma); writew(H(v), dma);
+    v=*laddr++; writew(L(v), dma); writew(H(v), dma);
+    v=*laddr++; writew(L(v), dma); writew(H(v), dma);
+    v=*laddr++; writew(L(v), dma); writew(H(v), dma);
+    v=*laddr++; writew(L(v), dma); writew(H(v), dma);
+    v=*laddr++; writew(L(v), dma); writew(H(v), dma);
+    v=*laddr++; writew(L(v), dma); writew(H(v), dma);
+    v=*laddr++; writew(L(v), dma); writew(H(v), dma);
     len -= 32;
     if(len == 0)
       break;
   }
 
   addr = (unsigned char *)laddr;
-  CTRL(iobase, 0x12);
+  writeb(0x12, priv(host)->base + CTRL);
+
   while(len > 0)
   {
-    int status;
-    status = STAT(iobase);
+    unsigned int status;
+    status = readb(priv(host)->base + STAT);
     if(status & 0x80)
       goto end;
     if(status & 0x40)
     {
-      OUT(*addr++, dma_io);
+      writeb(*addr++, dma);
       if(--len == 0)
         break;
     }
 
-    status = STAT(iobase);
+    status = readb(priv(host)->base + STAT);
     if(status & 0x80)
       goto end;
     if(status & 0x40)
     {
-      OUT(*addr++, dma_io);
+      writeb(*addr++, dma);
       if(--len == 0)
         break;
     }
   }
 end:
-  CTRL(iobase, oldctrl|0x40);
+  writeb(priv(host)->ctrl | 0x40, priv(host)->base + CTRL);
   return len;
 }
 
 static inline int
-NCR5380_pread(struct Scsi_Host *instance, unsigned char *addr, int len)
+NCR5380_pread(struct Scsi_Host *host, unsigned char *addr, int len)
 {
-  int *ctrl = &((struct NCR5380_hostdata *)instance->hostdata)->ctrl;
-  int oldctrl = *ctrl;
   unsigned long *laddr;
-#ifdef NOT_EFFICIENT
-  int iobase = instance->io_port;
-  int dma_io = iobase & ~(0x3C0000>>2);
-#else
-  volatile unsigned char *iobase = (unsigned char *)ioaddr(instance->io_port);
-  volatile unsigned char *dma_io = (unsigned char *)((int)iobase & ~0x3C0000);
-#endif
+  void __iomem *dma = priv(host)->dma + 0x2000;
 
   if(!len) return 0;
 
-  CTRL(iobase, 0x00);
+  writeb(0x00, priv(host)->base + CTRL);
   laddr = (unsigned long *)addr;
   while(len >= 32)
   {
-    int status;
-    status = STAT(iobase);
+    unsigned int status;
+    status = readb(priv(host)->base + STAT);
     if(status & 0x80)
       goto end;
     if(!(status & 0x40))
       continue;
-    *laddr++ = IN2(dma_io)|(IN2(dma_io)<<16);
-    *laddr++ = IN2(dma_io)|(IN2(dma_io)<<16);
-    *laddr++ = IN2(dma_io)|(IN2(dma_io)<<16);
-    *laddr++ = IN2(dma_io)|(IN2(dma_io)<<16);
-    *laddr++ = IN2(dma_io)|(IN2(dma_io)<<16);
-    *laddr++ = IN2(dma_io)|(IN2(dma_io)<<16);
-    *laddr++ = IN2(dma_io)|(IN2(dma_io)<<16);
-    *laddr++ = IN2(dma_io)|(IN2(dma_io)<<16);
+    *laddr++ = readw(dma) | (readw(dma) << 16);
+    *laddr++ = readw(dma) | (readw(dma) << 16);
+    *laddr++ = readw(dma) | (readw(dma) << 16);
+    *laddr++ = readw(dma) | (readw(dma) << 16);
+    *laddr++ = readw(dma) | (readw(dma) << 16);
+    *laddr++ = readw(dma) | (readw(dma) << 16);
+    *laddr++ = readw(dma) | (readw(dma) << 16);
+    *laddr++ = readw(dma) | (readw(dma) << 16);
     len -= 32;
     if(len == 0)
       break;
   }
 
   addr = (unsigned char *)laddr;
-  CTRL(iobase, 0x10);
+  writeb(0x10, priv(host)->base + CTRL);
+
   while(len > 0)
   {
-    int status;
-    status = STAT(iobase);
+    unsigned int status;
+    status = readb(priv(host)->base + STAT);
     if(status & 0x80)
       goto end;
     if(status & 0x40)
     {
-      *addr++ = IN(dma_io);
+      *addr++ = readb(dma);
       if(--len == 0)
         break;
     }
 
-    status = STAT(iobase);
+    status = readb(priv(host)->base + STAT);
     if(status & 0x80)
       goto end;
     if(status & 0x40)
     {
-      *addr++ = IN(dma_io);
+      *addr++ = readb(dma);
       if(--len == 0)
         break;
     }
   }
 end:
-  CTRL(iobase, oldctrl|0x40);
+  writeb(priv(host)->ctrl | 0x40, priv(host)->base + CTRL);
   return len;
 }
 
-#undef STAT
-#undef CTRL
-#undef IN
-#undef OUT
+static unsigned char cumanascsi_read(struct Scsi_Host *host, unsigned int reg)
+{
+        void __iomem *base = priv(host)->base;
+        unsigned char val;
 
-#define CTRL(p,v) outb(*ctrl = (v), (p) - 577)
+        writeb(0, base + CTRL);
 
-static char cumanascsi_read(struct Scsi_Host *instance, int reg)
-{
-        unsigned int iobase = instance->io_port;
-        int i;
-        int *ctrl = &((struct NCR5380_hostdata *)instance->hostdata)->ctrl;
+        val = readb(base + 0x2100 + (reg << 2));
 
-        CTRL(iobase, 0);
-        i = inb(iobase + 64 + reg);
-        CTRL(iobase, 0x40);
+        priv(host)->ctrl = 0x40;
+        writeb(0x40, base + CTRL);
 
-        return i;
+        return val;
 }
 
-static void cumanascsi_write(struct Scsi_Host *instance, int reg, int value)
+static void cumanascsi_write(struct Scsi_Host *host, unsigned int reg, unsigned int value)
 {
-        int iobase = instance->io_port;
-        int *ctrl = &((struct NCR5380_hostdata *)instance->hostdata)->ctrl;
+        void __iomem *base = priv(host)->base;
 
-        CTRL(iobase, 0);
-        outb(value, iobase + 64 + reg);
-        CTRL(iobase, 0x40);
-}
+        writeb(0, base + CTRL);
 
-#undef CTRL
+        writeb(value, base + 0x2100 + (reg << 2));
+
+        priv(host)->ctrl = 0x40;
+        writeb(0x40, base + CTRL);
+}
 
 #include "../NCR5380.c"
 
@@ -256,32 +231,46 @@ static int __devinit
 cumanascsi1_probe(struct expansion_card *ec, const struct ecard_id *id)
 {
         struct Scsi_Host *host;
-        int ret = -ENOMEM;
+        int ret;
 
-        host = scsi_host_alloc(&cumanascsi_template, sizeof(struct NCR5380_hostdata));
-        if (!host)
+        ret = ecard_request_resources(ec);
+        if (ret)
                 goto out;
 
-        host->io_port = ecard_address(ec, ECARD_IOC, ECARD_SLOW) + 0x800;
+        host = scsi_host_alloc(&cumanascsi_template, sizeof(struct NCR5380_hostdata));
+        if (!host) {
+                ret = -ENOMEM;
+                goto out_release;
+        }
+
+        priv(host)->base = ioremap(ecard_resource_start(ec, ECARD_RES_IOCSLOW),
+                                   ecard_resource_len(ec, ECARD_RES_IOCSLOW));
+        priv(host)->dma = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC),
+                                  ecard_resource_len(ec, ECARD_RES_MEMC));
+        if (!priv(host)->base || !priv(host)->dma) {
+                ret = -ENOMEM;
+                goto out_unmap;
+        }
+
         host->irq = ec->irq;
 
         NCR5380_init(host, 0);
 
+        priv(host)->ctrl = 0;
+        writeb(0, priv(host)->base + CTRL);
+
         host->n_io_port = 255;
         if (!(request_region(host->io_port, host->n_io_port, "CumanaSCSI-1"))) {
                 ret = -EBUSY;
-                goto out_free;
+                goto out_unmap;
         }
 
-        ((struct NCR5380_hostdata *)host->hostdata)->ctrl = 0;
-        outb(0x00, host->io_port - 577);
-
         ret = request_irq(host->irq, cumanascsi_intr, IRQF_DISABLED,
                           "CumanaSCSI-1", host);
         if (ret) {
                 printk("scsi%d: IRQ%d not free: %d\n",
                     host->host_no, host->irq, ret);
-                goto out_release;
+                goto out_unmap;
         }
 
         printk("scsi%d: at port 0x%08lx irq %d",
@@ -301,10 +290,12 @@ cumanascsi1_probe(struct expansion_card *ec, const struct ecard_id *id)
 
  out_free_irq:
         free_irq(host->irq, host);
- out_release:
-        release_region(host->io_port, host->n_io_port);
- out_free:
+ out_unmap:
+        iounmap(priv(host)->base);
+        iounmap(priv(host)->dma);
         scsi_host_put(host);
+ out_release:
+        ecard_release_resources(ec);
  out:
         return ret;
 }
@@ -318,8 +309,10 @@ static void __devexit cumanascsi1_remove(struct expansion_card *ec)
         scsi_remove_host(host);
         free_irq(host->irq, host);
         NCR5380_exit(host);
-        release_region(host->io_port, host->n_io_port);
+        iounmap(priv(host)->base);
+        iounmap(priv(host)->dma);
         scsi_host_put(host);
+        ecard_release_resources(ec);
 }
 
 static const struct ecard_id cumanascsi1_cids[] = {
diff --git a/drivers/scsi/arm/ecoscsi.c b/drivers/scsi/arm/ecoscsi.c
index 378e7af0c5d6..5265a9884338 100644
--- a/drivers/scsi/arm/ecoscsi.c
+++ b/drivers/scsi/arm/ecoscsi.c
@@ -34,35 +34,25 @@
 #include "../scsi.h"
 #include <scsi/scsi_host.h>
 
-#define NCR5380_implementation_fields   int port, ctrl
-#define NCR5380_local_declare()         struct Scsi_Host *_instance
-#define NCR5380_setup(instance)         _instance = instance
+#define priv(host)                      ((struct NCR5380_hostdata *)(host)->hostdata)
 
-#define NCR5380_read(reg)               ecoscsi_read(_instance, reg)
-#define NCR5380_write(reg, value)       ecoscsi_write(_instance, reg, value)
+#define NCR5380_local_declare()         void __iomem *_base
+#define NCR5380_setup(host)             _base = priv(host)->base
+
+#define NCR5380_read(reg)               ({ writeb(reg | 8, _base); readb(_base + 4); })
+#define NCR5380_write(reg, value)       ({ writeb(reg | 8, _base); writeb(value, _base + 4); })
 
 #define NCR5380_intr                    ecoscsi_intr
 #define NCR5380_queue_command           ecoscsi_queue_command
 #define NCR5380_proc_info               ecoscsi_proc_info
 
+#define NCR5380_implementation_fields   \
+        void __iomem *base
+
 #include "../NCR5380.h"
 
 #define ECOSCSI_PUBLIC_RELEASE 1
 
-static char ecoscsi_read(struct Scsi_Host *instance, int reg)
-{
-  int iobase = instance->io_port;
-  outb(reg | 8, iobase);
-  return inb(iobase + 1);
-}
-
-static void ecoscsi_write(struct Scsi_Host *instance, int reg, int value)
-{
-  int iobase = instance->io_port;
-  outb(reg | 8, iobase);
-  outb(value, iobase + 1);
-}
-
 /*
  * Function : ecoscsi_setup(char *str, int *ints)
  *
@@ -82,73 +72,6 @@ const char * ecoscsi_info (struct Scsi_Host *spnt)
         return "";
 }
 
-#if 0
-#define STAT(p) inw(p + 144)
-
-static inline int NCR5380_pwrite(struct Scsi_Host *host, unsigned char *addr,
-              int len)
-{
-  int iobase = host->io_port;
-printk("writing %p len %d\n",addr, len);
-  if(!len) return -1;
-
-  while(1)
-  {
-    int status;
-    while(((status = STAT(iobase)) & 0x100)==0);
-  }
-}
-
-static inline int NCR5380_pread(struct Scsi_Host *host, unsigned char *addr,
-              int len)
-{
-  int iobase = host->io_port;
-  int iobase2= host->io_port + 0x100;
-  unsigned char *start = addr;
-  int s;
-printk("reading %p len %d\n",addr, len);
-  outb(inb(iobase + 128), iobase + 135);
-  while(len > 0)
-  {
-    int status,b,i, timeout;
-    timeout = 0x07FFFFFF;
-    while(((status = STAT(iobase)) & 0x100)==0)
-    {
-      timeout--;
-      if(status & 0x200 || !timeout)
-      {
-        printk("status = %p\n",status);
-        outb(0, iobase + 135);
-        return 1;
-      }
-    }
-    if(len >= 128)
-    {
-      for(i=0; i<64; i++)
-      {
-        b = inw(iobase + 136);
-        *addr++ = b;
-        *addr++ = b>>8;
-      }
-      len -= 128;
-    }
-    else
-    {
-      b = inw(iobase + 136);
-      *addr ++ = b;
-      len -= 1;
-      if(len)
-        *addr ++ = b>>8;
-      len -= 1;
-    }
-  }
-  outb(0, iobase + 135);
-  printk("first bytes = %02X %02X %02X %20X %02X %02X %02X\n",*start, start[1], start[2], start[3], start[4], start[5], start[6]);
-  return 1;
-}
-#endif
-#undef STAT
-
 #define BOARD_NORMAL    0
 #define BOARD_NCR53C400 1
 
@@ -173,25 +96,36 @@ static struct Scsi_Host *host;
 
 static int __init ecoscsi_init(void)
 {
+        void __iomem *_base;
+        int ret;
 
-        host = scsi_host_alloc(tpnt, sizeof(struct NCR5380_hostdata));
-        if (!host)
-                return 0;
+        if (!request_mem_region(0x33a0000, 4096, "ecoscsi")) {
+                ret = -EBUSY;
+                goto out;
+        }
 
-        host->io_port = 0x80ce8000;
-        host->n_io_port = 144;
-        host->irq = IRQ_NONE;
+        _base = ioremap(0x33a0000, 4096);
+        if (!_base) {
+                ret = -ENOMEM;
+                goto out_release;
+        }
 
-        if (!(request_region(host->io_port, host->n_io_port, "ecoscsi")) )
-                goto unregister_scsi;
+        NCR5380_write(MODE_REG, 0x20);          /* Is it really SCSI? */
+        if (NCR5380_read(MODE_REG) != 0x20)     /* Write to a reg.    */
+                goto out_unmap;
 
-        ecoscsi_write(host, MODE_REG, 0x20);            /* Is it really SCSI? */
-        if (ecoscsi_read(host, MODE_REG) != 0x20) /* Write to a reg.    */
-                goto release_reg;
+        NCR5380_write(MODE_REG, 0x00);          /* it back.           */
+        if (NCR5380_read(MODE_REG) != 0x00)
+                goto out_unmap;
 
-        ecoscsi_write(host, MODE_REG, 0x00 );           /* it back.           */
-        if (ecoscsi_read(host, MODE_REG) != 0x00)
-                goto release_reg;
+        host = scsi_host_alloc(tpnt, sizeof(struct NCR5380_hostdata));
+        if (!host) {
+                ret = -ENOMEM;
+                goto out_unmap;
+        }
+
+        priv(host)->base = _base;
+        host->irq = IRQ_NONE;
 
         NCR5380_init(host, 0);
 
@@ -206,24 +140,20 @@ static int __init ecoscsi_init(void)
         scsi_scan_host(host);
         return 0;
 
-release_reg:
-        release_region(host->io_port, host->n_io_port);
-unregister_scsi:
-        scsi_host_put(host);
-        return -ENODEV;
+ out_unmap:
+        iounmap(_base);
+ out_release:
+        release_mem_region(0x33a0000, 4096);
+ out:
+        return ret;
 }
 
 static void __exit ecoscsi_exit(void)
 {
         scsi_remove_host(host);
-
-        if (shpnt->irq != IRQ_NONE)
-                free_irq(shpnt->irq, NULL);
         NCR5380_exit(host);
-        if (shpnt->io_port)
-                release_region(shpnt->io_port, shpnt->n_io_port);
-
         scsi_host_put(host);
+        release_mem_region(0x33a0000, 4096);
         return 0;
 }
 
diff --git a/drivers/scsi/arm/oak.c b/drivers/scsi/arm/oak.c
index c21b8392c928..849cdf89f7bb 100644
--- a/drivers/scsi/arm/oak.c
+++ b/drivers/scsi/arm/oak.c
@@ -23,15 +23,18 @@
 
 #define OAKSCSI_PUBLIC_RELEASE 1
 
-#define NCR5380_read(reg)               oakscsi_read(_instance, reg)
-#define NCR5380_write(reg, value)       oakscsi_write(_instance, reg, value)
+#define priv(host)                      ((struct NCR5380_hostdata *)(host)->hostdata)
+#define NCR5380_local_declare()         void __iomem *_base
+#define NCR5380_setup(host)             _base = priv(host)->base
+
+#define NCR5380_read(reg)               readb(_base + ((reg) << 2))
+#define NCR5380_write(reg, value)       writeb(value, _base + ((reg) << 2))
 #define NCR5380_intr                    oakscsi_intr
 #define NCR5380_queue_command           oakscsi_queue_command
 #define NCR5380_proc_info               oakscsi_proc_info
 
-#define NCR5380_implementation_fields   int port, ctrl
-#define NCR5380_local_declare()         struct Scsi_Host *_instance
-#define NCR5380_setup(instance)         _instance = instance
+#define NCR5380_implementation_fields   \
+        void __iomem *base
 
 #define BOARD_NORMAL    0
 #define BOARD_NCR53C400 1
@@ -39,60 +42,62 @@
 #include "../NCR5380.h"
 
 #undef START_DMA_INITIATOR_RECEIVE_REG
-#define START_DMA_INITIATOR_RECEIVE_REG (7 + 128)
+#define START_DMA_INITIATOR_RECEIVE_REG (128 + 7)
 
 const char * oakscsi_info (struct Scsi_Host *spnt)
 {
         return "";
 }
 
-#define STAT(p)   inw(p + 144)
-extern void inswb(int from, void *to, int len);
+#define STAT    ((128 + 16) << 2)
+#define DATA    ((128 + 8) << 2)
 
 static inline int NCR5380_pwrite(struct Scsi_Host *instance, unsigned char *addr,
               int len)
 {
-  int iobase = instance->io_port;
+  void __iomem *base = priv(instance)->base;
+
 printk("writing %p len %d\n",addr, len);
   if(!len) return -1;
 
   while(1)
   {
     int status;
-    while(((status = STAT(iobase)) & 0x100)==0);
+    while (((status = readw(base + STAT)) & 0x100)==0);
   }
 }
 
 static inline int NCR5380_pread(struct Scsi_Host *instance, unsigned char *addr,
               int len)
 {
-  int iobase = instance->io_port;
+  void __iomem *base = priv(instance)->base;
 printk("reading %p len %d\n", addr, len);
   while(len > 0)
   {
-    int status, timeout;
+    unsigned int status, timeout;
     unsigned long b;
     
     timeout = 0x01FFFFFF;
     
-    while(((status = STAT(iobase)) & 0x100)==0)
+    while (((status = readw(base + STAT)) & 0x100)==0)
     {
       timeout--;
       if(status & 0x200 || !timeout)
       {
-        printk("status = %08X\n",status);
+        printk("status = %08X\n", status);
         return 1;
       }
     }
+
     if(len >= 128)
     {
-      inswb(iobase + 136, addr, 128);
+      readsw(base + DATA, addr, 128);
       addr += 128;
       len -= 128;
     }
     else
     {
-      b = (unsigned long) inw(iobase + 136);
+      b = (unsigned long) readw(base + DATA);
       *addr ++ = b;
       len -= 1;
       if(len)
@@ -103,10 +108,8 @@ printk("reading %p len %d\n", addr, len);
   return 0;
 }
 
-#define oakscsi_read(instance,reg)      (inb((instance)->io_port + (reg)))
-#define oakscsi_write(instance,reg,val) (outb((val), (instance)->io_port + (reg)))
-
 #undef STAT
+#undef DATA
 
 #include "../NCR5380.c"
 
@@ -132,18 +135,26 @@ oakscsi_probe(struct expansion_card *ec, const struct ecard_id *id)
         struct Scsi_Host *host;
         int ret = -ENOMEM;
 
-        host = scsi_host_alloc(&oakscsi_template, sizeof(struct NCR5380_hostdata));
-        if (!host)
+        ret = ecard_request_resources(ec);
+        if (ret)
                 goto out;
 
-        host->io_port = ecard_address(ec, ECARD_MEMC, 0);
+        host = scsi_host_alloc(&oakscsi_template, sizeof(struct NCR5380_hostdata));
+        if (!host) {
+                ret = -ENOMEM;
+                goto release;
+        }
+
+        priv(host)->base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC),
+                                   ecard_resource_len(ec, ECARD_RES_MEMC));
+        if (!priv(host)->base) {
+                ret = -ENOMEM;
+                goto unreg;
+        }
+
         host->irq = IRQ_NONE;
         host->n_io_port = 255;
 
-        ret = -EBUSY;
-        if (!request_region (host->io_port, host->n_io_port, "Oak SCSI"))
-                goto unreg;
-
         NCR5380_init(host, 0);
 
         printk("scsi%d: at port 0x%08lx irqs disabled",
@@ -156,15 +167,17 @@ oakscsi_probe(struct expansion_card *ec, const struct ecard_id *id)
 
         ret = scsi_add_host(host, &ec->dev);
         if (ret)
-                goto out_release;
+                goto out_unmap;
 
         scsi_scan_host(host);
         goto out;
 
- out_release:
-        release_region(host->io_port, host->n_io_port);
+ out_unmap:
+        iounmap(priv(host)->base);
  unreg:
         scsi_host_put(host);
+ release:
+        ecard_release_resources(ec);
  out:
         return ret;
 }
@@ -177,8 +190,9 @@ static void __devexit oakscsi_remove(struct expansion_card *ec)
         scsi_remove_host(host);
 
         NCR5380_exit(host);
-        release_region(host->io_port, host->n_io_port);
+        iounmap(priv(host)->base);
         scsi_host_put(host);
+        ecard_release_resources(ec);
 }
 
 static const struct ecard_id oakscsi_cids[] = {
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c
index e42faa4e4282..dc1967176fe2 100644
--- a/drivers/serial/imx.c
+++ b/drivers/serial/imx.c
@@ -1114,8 +1114,8 @@ static int __init imx_serial_init(void)
 
 static void __exit imx_serial_exit(void)
 {
-        uart_unregister_driver(&imx_reg);
         platform_driver_unregister(&serial_imx_driver);
+        uart_unregister_driver(&imx_reg);
 }
 
 module_init(imx_serial_init);
diff --git a/drivers/serial/s3c2410.c b/drivers/serial/s3c2410.c
index 10bc0209cd66..3f26c4b2f322 100644
--- a/drivers/serial/s3c2410.c
+++ b/drivers/serial/s3c2410.c
@@ -78,7 +78,7 @@
 
 #include <asm/hardware.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 
 /* structures */
diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h
index 40a9876b661a..c2e11cc374ba 100644
--- a/include/asm-arm/arch-at91/at91_mci.h
+++ b/include/asm-arm/arch-at91/at91_mci.h
@@ -26,6 +26,9 @@
 #define AT91_MCI_MR             0x04            /* Mode Register */
 #define         AT91_MCI_CLKDIV         (0xff  <<  0)   /* Clock Divider */
 #define         AT91_MCI_PWSDIV         (7     <<  8)   /* Power Saving Divider */
+#define         AT91_MCI_RDPROOF        (1     << 11)   /* Read Proof Enable [SAM926[03] only] */
+#define         AT91_MCI_WRPROOF        (1     << 12)   /* Write Proof Enable [SAM926[03] only] */
+#define         AT91_MCI_PDCFBYTE       (1     << 13)   /* PDC Force Byte Transfer [SAM926[03] only] */
 #define         AT91_MCI_PDCPADV        (1     << 14)   /* PDC Padding Value */
 #define         AT91_MCI_PDCMODE        (1     << 15)   /* PDC-orientated Mode */
 #define         AT91_MCI_BLKLEN         (0xfff << 18)   /* Data Block Length */
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
index d4e4f828577c..52b7fab7ef60 100644
--- a/include/asm-arm/arch-iop13xx/iop13xx.h
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -19,6 +19,39 @@ static inline int iop13xx_cpu_id(void)
         return id;
 }
 
+/* WDTCR CP6 R7 Page 9 */
+static inline u32 read_wdtcr(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
+        return val;
+}
+static inline void write_wdtcr(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
+}
+
+/* WDTSR CP6 R8 Page 9 */
+static inline u32 read_wdtsr(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
+        return val;
+}
+static inline void write_wdtsr(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
+}
+
+/* RCSR - Reset Cause Status Register  */
+static inline u32 read_rcsr(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val));
+        return val;
+}
+
+extern unsigned long get_iop_tick_rate(void);
 #endif
 
 /*
@@ -480,4 +513,14 @@ static inline int iop13xx_cpu_id(void)
 #define IOP13XX_PBI_LR1                 IOP13XX_PBI_OFFSET(0x14)
 
 #define IOP13XX_PROCESSOR_FREQ          IOP13XX_REG_ADDR32(0x2180)
+
+/* Watchdog timer definitions */
+#define IOP_WDTCR_EN_ARM        0x1e1e1e1e
+#define IOP_WDTCR_EN            0xe1e1e1e1
+#define IOP_WDTCR_DIS_ARM       0x1f1f1f1f
+#define IOP_WDTCR_DIS           0xf1f1f1f1
+#define IOP_RCSR_WDT            (1 << 5) /* reset caused by watchdog timer */
+#define IOP13XX_WDTSR_WRITE_EN  (1 << 31) /* used to speed up reset requests */
+#define IOP13XX_WDTCR_IB_RESET  (1 << 0)
+
 #endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h
index 127827058e1f..8575af8db78c 100644
--- a/include/asm-arm/arch-iop13xx/system.h
+++ b/include/asm-arm/arch-iop13xx/system.h
@@ -13,43 +13,13 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-/* WDTCR CP6 R7 Page 9 */
-static inline u32 read_wdtcr(void)
-{
-        u32 val;
-        asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
-        return val;
-}
-static inline void write_wdtcr(u32 val)
-{
-        asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
-}
-
-/* WDTSR CP6 R8 Page 9 */
-static inline u32 read_wdtsr(void)
-{
-        u32 val;
-        asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
-        return val;
-}
-static inline void write_wdtsr(u32 val)
-{
-        asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
-}
-
-#define IOP13XX_WDTCR_EN_ARM    0x1e1e1e1e
-#define IOP13XX_WDTCR_EN        0xe1e1e1e1
-#define IOP13XX_WDTCR_DIS_ARM   0x1f1f1f1f
-#define IOP13XX_WDTCR_DIS       0xf1f1f1f1
-#define IOP13XX_WDTSR_WRITE_EN  (1 << 31)
-#define IOP13XX_WDTCR_IB_RESET  (1 << 0)
 static inline void arch_reset(char mode)
 {
         /*
          * Reset the internal bus (warning both cores are reset)
          */
-        write_wdtcr(IOP13XX_WDTCR_EN_ARM);
-        write_wdtcr(IOP13XX_WDTCR_EN);
+        write_wdtcr(IOP_WDTCR_EN_ARM);
+        write_wdtcr(IOP_WDTCR_EN);
         write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
         write_wdtcr(0x1000);
 
diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h
index b9525d59b7ad..dd9c2934190e 100644
--- a/include/asm-arm/arch-iop13xx/uncompress.h
+++ b/include/asm-arm/arch-iop13xx/uncompress.h
@@ -1,7 +1,6 @@
 #include <asm/types.h>
 #include <linux/serial_reg.h>
 #include <asm/hardware.h>
-#include <asm/processor.h>
 
 #define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
 #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
@@ -9,7 +8,7 @@
 static inline void putc(char c)
 {
         while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
-                cpu_relax();
+                barrier();
         UART_BASE[UART_TX] = c;
 }
 
diff --git a/include/asm-arm/arch-iop32x/uncompress.h b/include/asm-arm/arch-iop32x/uncompress.h
index e64f52bf2bce..070f15818fe7 100644
--- a/include/asm-arm/arch-iop32x/uncompress.h
+++ b/include/asm-arm/arch-iop32x/uncompress.h
@@ -26,7 +26,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 {
         if (machine_is_iq80321())
                 uart_base = (volatile u8 *)IQ80321_UART;
-        else if (machine_is_iq31244())
+        else if (machine_is_iq31244() || machine_is_em7210())
                 uart_base = (volatile u8 *)IQ31244_UART;
         else
                 uart_base = (volatile u8 *)0xfe800000;
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h
new file mode 100644
index 000000000000..be29b83ad4ae
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx31ads.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
+#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
+
+/*!
+ * @name PBC Controller parameters
+ */
+/*! @{ */
+/*!
+ * Base address of PBC controller
+ */
+#define PBC_BASE_ADDRESS        IO_ADDRESS(CS4_BASE_ADDR)
+/* Offsets for the PBC Controller register */
+/*!
+ * PBC Board status register offset
+ */
+#define PBC_BSTAT               0x000002
+/*!
+ * PBC Board control register 1 set address.
+ */
+#define PBC_BCTRL1_SET          0x000004
+/*!
+ * PBC Board control register 1 clear address.
+ */
+#define PBC_BCTRL1_CLEAR        0x000006
+/*!
+ * PBC Board control register 2 set address.
+ */
+#define PBC_BCTRL2_SET          0x000008
+/*!
+ * PBC Board control register 2 clear address.
+ */
+#define PBC_BCTRL2_CLEAR        0x00000A
+/*!
+ * PBC Board control register 3 set address.
+ */
+#define PBC_BCTRL3_SET          0x00000C
+/*!
+ * PBC Board control register 3 clear address.
+ */
+#define PBC_BCTRL3_CLEAR        0x00000E
+/*!
+ * PBC Board control register 4 set address.
+ */
+#define PBC_BCTRL4_SET          0x000010
+/*!
+ * PBC Board control register 4 clear address.
+ */
+#define PBC_BCTRL4_CLEAR        0x000012
+/*!
+ * PBC Board status register 1.
+ */
+#define PBC_BSTAT1              0x000014
+/*!
+ * PBC Board interrupt status register.
+ */
+#define PBC_INTSTATUS           0x000016
+/*!
+ * PBC Board interrupt current status register.
+ */
+#define PBC_INTCURR_STATUS      0x000018
+/*!
+ * PBC Interrupt mask register set address.
+ */
+#define PBC_INTMASK_SET         0x00001A
+/*!
+ * PBC Interrupt mask register clear address.
+ */
+#define PBC_INTMASK_CLEAR       0x00001C
+
+/*!
+ * External UART A.
+ */
+#define PBC_SC16C652_UARTA      0x010000
+/*!
+ * External UART B.
+ */
+#define PBC_SC16C652_UARTB      0x010010
+/*!
+ * Ethernet Controller IO base address.
+ */
+#define PBC_CS8900A_IOBASE      0x020000
+/*!
+ * Ethernet Controller Memory base address.
+ */
+#define PBC_CS8900A_MEMBASE     0x021000
+/*!
+ * Ethernet Controller DMA base address.
+ */
+#define PBC_CS8900A_DMABASE     0x022000
+/*!
+ * External chip select 0.
+ */
+#define PBC_XCS0                0x040000
+/*!
+ * LCD Display enable.
+ */
+#define PBC_LCD_EN_B            0x060000
+/*!
+ * Code test debug enable.
+ */
+#define PBC_CODE_B              0x070000
+/*!
+ * PSRAM memory select.
+ */
+#define PBC_PSRAM_B             0x5000000
+
+#define PBC_INTSTATUS_REG       (PBC_INTSTATUS + PBC_BASE_ADDRESS)
+#define PBC_INTCURR_STATUS_REG  (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_SET_REG     (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
+#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
+
+#define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 0)
+#define EXPIO_INT_PB_IRQ        (MXC_EXP_IO_BASE + 1)
+#define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
+#define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
+#define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
+#define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
+#define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
+#define EXPIO_INT_RES7          (MXC_EXP_IO_BASE + 7)
+#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
+#define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
+#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_XUART_INTB    (MXC_EXP_IO_BASE + 11)
+#define EXPIO_INT_SYNTH_IRQ     (MXC_EXP_IO_BASE + 12)
+#define EXPIO_INT_CE_INT1       (MXC_EXP_IO_BASE + 13)
+#define EXPIO_INT_CE_INT2       (MXC_EXP_IO_BASE + 14)
+#define EXPIO_INT_RES15         (MXC_EXP_IO_BASE + 15)
+
+#define MXC_MAX_EXP_IO_LINES    16
+
+#endif                          /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/common.h b/include/asm-arm/arch-mxc/common.h
new file mode 100644
index 000000000000..23b4350edbd6
--- /dev/null
+++ b/include/asm-arm/arch-mxc/common.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_COMMON_H__
+#define __ASM_ARCH_MXC_COMMON_H__
+
+struct sys_timer;
+
+extern void mxc_map_io(void);
+extern void mxc_init_irq(void);
+extern struct sys_timer mxc_timer;
+
+#endif
diff --git a/include/asm-arm/arch-mxc/dma.h b/include/asm-arm/arch-mxc/dma.h
new file mode 100644
index 000000000000..65e639d51d2b
--- /dev/null
+++ b/include/asm-arm/arch-mxc/dma.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_DMA_H__
+#define __ASM_ARCH_MXC_DMA_H__
+
+/*!
+ * @file dma.h
+ * @brief This file contains Unified DMA API for all MXC platforms.
+ * The API is platform independent.
+ *
+ * @ingroup SDMA
+ */
+#endif
diff --git a/include/asm-arm/arch-mxc/entry-macro.S b/include/asm-arm/arch-mxc/entry-macro.S
new file mode 100644
index 000000000000..b542433afb1b
--- /dev/null
+++ b/include/asm-arm/arch-mxc/entry-macro.S
@@ -0,0 +1,39 @@
+/*
+ *  Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+        @ this macro disables fast irq (not implemented)
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        @ this macro checks which interrupt occured
+        @ and returns its number in irqnr
+        @ and returns if an interrupt occured in irqstat
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
+        @ Load offset & priority of the highest priority
+        @ interrupt pending from AVIC_NIVECSR
+        ldr     \irqstat, [\base, #0x40]
+        @ Shift to get the decoded IRQ number, using ASR so
+        @ 'no interrupt pending' becomes 0xffffffff
+        mov     \irqnr, \irqstat, asr #16
+        @ set zero flag if IRQ + 1 == 0
+        adds    \tmp, \irqnr, #1
+        .endm
+
+        @ irq priority table (not used)
+        .macro  irq_prio_table
+        .endm
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h
new file mode 100644
index 000000000000..3c09b92fef0d
--- /dev/null
+++ b/include/asm-arm/arch-mxc/hardware.h
@@ -0,0 +1,52 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*!
+ * @file hardware.h
+ * @brief This file contains the hardware definitions of the board.
+ *
+ * @ingroup System
+ */
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#define __ASM_ARCH_MXC_HARDWARE_H__
+
+#include <asm/sizes.h>
+
+#include <asm/arch/mx31.h>
+
+#include <asm/arch/mxc.h>
+
+#define MXC_MAX_GPIO_LINES      (GPIO_NUM_PIN * GPIO_PORT_NUM)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Board specific defines
+ * ---------------------------------------------------------------------------
+ */
+#define MXC_EXP_IO_BASE         (MXC_GPIO_INT_BASE + MXC_MAX_GPIO_LINES)
+
+#include <asm/arch/board-mx31ads.h>
+
+#ifndef MXC_MAX_EXP_IO_LINES
+#define MXC_MAX_EXP_IO_LINES 0
+#endif
+
+#define MXC_MAX_VIRTUAL_INTS    16
+#define MXC_VIRTUAL_INTS_BASE   (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
+#define MXC_SDIO1_CARD_IRQ      MXC_VIRTUAL_INTS_BASE
+#define MXC_SDIO2_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 1)
+#define MXC_SDIO3_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 2)
+
+#define MXC_MAX_INTS            (MXC_MAX_INT_LINES + \
+                                MXC_MAX_GPIO_LINES + \
+                                MXC_MAX_EXP_IO_LINES + \
+                                MXC_MAX_VIRTUAL_INTS)
+
+#endif                          /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/io.h b/include/asm-arm/arch-mxc/io.h
new file mode 100644
index 000000000000..cf6c83a4b9f7
--- /dev/null
+++ b/include/asm-arm/arch-mxc/io.h
@@ -0,0 +1,33 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*!
+ * @file io.h
+ * @brief This file contains some memory mapping macros.
+ * @note There is no real ISA or PCI buses. But have to define these macros
+ * for some drivers to compile.
+ *
+ * @ingroup System
+ */
+
+#ifndef __ASM_ARCH_MXC_IO_H__
+#define __ASM_ARCH_MXC_IO_H__
+
+/*! Allow IO space to be anywhere in the memory */
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*!
+ * io address mapping macro
+ */
+#define __io(a)                 ((void __iomem *)(a))
+
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
new file mode 100644
index 000000000000..e4686c6bc4bf
--- /dev/null
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -0,0 +1,38 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_IRQS_H__
+#define __ASM_ARCH_MXC_IRQS_H__
+
+#include <asm/hardware.h>
+
+/*!
+ * @file irqs.h
+ * @brief This file defines the number of normal interrupts and fast interrupts
+ *
+ * @ingroup Interrupt
+ */
+
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
+
+#define MXC_IRQ_TO_GPIO(irq)    ((irq) - MXC_GPIO_INT_BASE)
+#define MXC_GPIO_TO_IRQ(x)      (MXC_GPIO_INT_BASE + x)
+
+/*!
+ * Number of normal interrupts
+ */
+#define NR_IRQS         MXC_MAX_INTS
+
+/*!
+ * Number of fast interrupts
+ */
+#define NR_FIQS         MXC_MAX_INTS
+
+#endif                          /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/memory.h b/include/asm-arm/arch-mxc/memory.h
new file mode 100644
index 000000000000..c89aac83a407
--- /dev/null
+++ b/include/asm-arm/arch-mxc/memory.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_MEMORY_H__
+#define __ASM_ARCH_MXC_MEMORY_H__
+
+#include <asm/hardware.h>
+
+/*!
+ * @file memory.h
+ * @brief This file contains macros needed by the Linux kernel and drivers.
+ *
+ * @ingroup Memory
+ */
+
+/*!
+ * Virtual view <-> DMA view memory address translations
+ * This macro is used to translate the virtual address to an address
+ * suitable to be passed to set_dma_addr()
+ */
+#define __virt_to_bus(a)        __virt_to_phys(a)
+
+/*!
+ * Used to convert an address for DMA operations to an address that the
+ * kernel can use.
+ */
+#define __bus_to_virt(a)        __phys_to_virt(a)
+
+#endif                          /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
new file mode 100644
index 000000000000..85c49c9e5d15
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mx31.h
@@ -0,0 +1,335 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_MX31_H__
+#define __ASM_ARCH_MXC_MX31_H__
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+
+/*!
+ * defines the hardware clock tick rate
+ */
+#define CLOCK_TICK_RATE         16625000
+
+/*
+ * MX31 memory map:
+ *
+ * Virt         Phys            Size    What
+ * ---------------------------------------------------------------------------
+ * F8000000     1FFC0000        16K     IRAM
+ * F9000000     30000000        256M    L2CC
+ * FC000000     43F00000        1M      AIPS 1
+ * FC100000     50000000        1M      SPBA
+ * FC200000     53F00000        1M      AIPS 2
+ * FC500000     60000000        128M    ROMPATCH
+ * FC400000     68000000        128M    AVIC
+ *              70000000        256M    IPU (MAX M2)
+ *              80000000        256M    CSD0 SDRAM/DDR
+ *              90000000        256M    CSD1 SDRAM/DDR
+ *              A0000000        128M    CS0 Flash
+ *              A8000000        128M    CS1 Flash
+ *              B0000000        32M     CS2
+ *              B2000000        32M     CS3
+ * F4000000     B4000000        32M     CS4
+ *              B6000000        32M     CS5
+ * FC320000     B8000000        64K     NAND, SDRAM, WEIM, M3IF, EMI controllers
+ *              C0000000        64M     PCMCIA/CF
+ */
+
+#define CS0_BASE_ADDR           0xA0000000
+#define CS1_BASE_ADDR           0xA8000000
+#define CS2_BASE_ADDR           0xB0000000
+#define CS3_BASE_ADDR           0xB2000000
+
+#define CS4_BASE_ADDR           0xB4000000
+#define CS4_BASE_ADDR_VIRT      0xF4000000
+#define CS4_SIZE                SZ_32M
+
+#define CS5_BASE_ADDR           0xB6000000
+#define PCMCIA_MEM_BASE_ADDR    0xBC000000
+
+/*
+ * IRAM
+ */
+#define IRAM_BASE_ADDR          0x1FFC0000      /* internal ram */
+#define IRAM_BASE_ADDR_VIRT     0xF8000000
+#define IRAM_SIZE               SZ_16K
+
+/*
+ * L2CC
+ */
+#define L2CC_BASE_ADDR          0x30000000
+#define L2CC_BASE_ADDR_VIRT     0xF9000000
+#define L2CC_SIZE               SZ_1M
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR         0x43F00000
+#define AIPS1_BASE_ADDR_VIRT    0xFC000000
+#define AIPS1_SIZE              SZ_1M
+
+#define MAX_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00004000)
+#define EVTMON_BASE_ADDR        (AIPS1_BASE_ADDR + 0x00008000)
+#define CLKCTL_BASE_ADDR        (AIPS1_BASE_ADDR + 0x0000C000)
+#define ETB_SLOT4_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00010000)
+#define ETB_SLOT5_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00014000)
+#define ECT_CTIO_BASE_ADDR      (AIPS1_BASE_ADDR + 0x00018000)
+#define I2C_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00080000)
+#define I2C3_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00084000)
+#define OTG_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00088000)
+#define ATA_BASE_ADDR           (AIPS1_BASE_ADDR + 0x0008C000)
+#define UART1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00090000)
+#define UART2_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00094000)
+#define I2C2_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00098000)
+#define OWIRE_BASE_ADDR         (AIPS1_BASE_ADDR + 0x0009C000)
+#define SSI1_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000A0000)
+#define CSPI1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000A4000)
+#define KPP_BASE_ADDR           (AIPS1_BASE_ADDR + 0x000A8000)
+#define IOMUXC_BASE_ADDR        (AIPS1_BASE_ADDR + 0x000AC000)
+#define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B0000)
+#define UART5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B4000)
+#define ECT_IP1_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000B8000)
+#define ECT_IP2_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000BC000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define SPBA0_BASE_ADDR         0x50000000
+#define SPBA0_BASE_ADDR_VIRT    0xFC100000
+#define SPBA0_SIZE              SZ_1M
+
+#define MMC_SDHC1_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00004000)
+#define MMC_SDHC2_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00008000)
+#define UART3_BASE_ADDR         (SPBA0_BASE_ADDR + 0x0000C000)
+#define CSPI2_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00010000)
+#define SSI2_BASE_ADDR          (SPBA0_BASE_ADDR + 0x00014000)
+#define SIM1_BASE_ADDR          (SPBA0_BASE_ADDR + 0x00018000)
+#define IIM_BASE_ADDR           (SPBA0_BASE_ADDR + 0x0001C000)
+#define ATA_DMA_BASE_ADDR       (SPBA0_BASE_ADDR + 0x00020000)
+#define MSHC1_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00024000)
+#define MSHC2_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00024000)
+#define SPBA_CTRL_BASE_ADDR     (SPBA0_BASE_ADDR + 0x0003C000)
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR         0x53F00000
+#define AIPS2_BASE_ADDR_VIRT    0xFC200000
+#define AIPS2_SIZE              SZ_1M
+#define CCM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x00080000)
+#define CSPI3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00084000)
+#define FIRI_BASE_ADDR          (AIPS2_BASE_ADDR + 0x0008C000)
+#define GPT1_BASE_ADDR          (AIPS2_BASE_ADDR + 0x00090000)
+#define EPIT1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00094000)
+#define EPIT2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00098000)
+#define GPIO3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000A4000)
+#define SCC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AC000)
+#define SCM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AE000)
+#define SMN_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AF000)
+#define RNGA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000B0000)
+#define IPU_CTRL_BASE_ADDR      (AIPS2_BASE_ADDR + 0x000C0000)
+#define AUDMUX_BASE_ADDR        (AIPS2_BASE_ADDR + 0x000C4000)
+#define MPEG4_ENC_BASE_ADDR     (AIPS2_BASE_ADDR + 0x000C8000)
+#define GPIO1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000CC000)
+#define GPIO2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000D0000)
+#define SDMA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000D4000)
+#define RTC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000D8000)
+#define WDOG_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000DC000)
+#define PWM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000E0000)
+#define RTIC_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000EC000)
+
+/*
+ * ROMP and AVIC
+ */
+#define ROMP_BASE_ADDR          0x60000000
+#define ROMP_BASE_ADDR_VIRT     0xFC500000
+#define ROMP_SIZE               SZ_1M
+
+#define AVIC_BASE_ADDR          0x68000000
+#define AVIC_BASE_ADDR_VIRT     0xFC400000
+#define AVIC_SIZE               SZ_1M
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define X_MEMC_BASE_ADDR        0xB8000000
+#define X_MEMC_BASE_ADDR_VIRT   0xFC320000
+#define X_MEMC_SIZE             SZ_64K
+
+#define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR + 0x0000)
+#define ESDCTL_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
+#define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
+#define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
+#define EMI_CTL_BASE_ADDR       (X_MEMC_BASE_ADDR + 0x4000)
+#define PCMCIA_CTL_BASE_ADDR    EMI_CTL_BASE_ADDR
+
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE_ADDR       0x70000000
+#define CSD0_BASE_ADDR          0x80000000
+#define CSD1_BASE_ADDR          0x90000000
+#define CS0_BASE_ADDR           0xA0000000
+#define CS1_BASE_ADDR           0xA8000000
+#define CS2_BASE_ADDR           0xB0000000
+#define CS3_BASE_ADDR           0xB2000000
+
+#define CS4_BASE_ADDR           0xB4000000
+#define CS4_BASE_ADDR_VIRT      0xF4000000
+#define CS4_SIZE                SZ_32M
+
+#define CS5_BASE_ADDR           0xB6000000
+#define PCMCIA_MEM_BASE_ADDR    0xBC000000
+
+/*!
+ * This macro defines the physical to virtual address mapping for all the
+ * peripheral modules. It is used by passing in the physical address as x
+ * and returning the virtual address. If the physical address is not mapped,
+ * it returns 0xDEADBEEF
+ */
+#define IO_ADDRESS(x)   \
+        (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
+        ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
+        ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
+        ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
+        ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
+        ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
+        ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
+        ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
+        ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
+        0xDEADBEEF)
+
+/*
+ * define the address mapping macros: in physical address order
+ */
+
+#define IRAM_IO_ADDRESS(x)  \
+        (((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT)
+
+#define L2CC_IO_ADDRESS(x)  \
+        (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
+
+#define AIPS1_IO_ADDRESS(x)  \
+        (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
+
+#define SPBA0_IO_ADDRESS(x)  \
+        (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
+
+#define AIPS2_IO_ADDRESS(x)  \
+        (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
+
+#define ROMP_IO_ADDRESS(x)  \
+        (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
+
+#define AVIC_IO_ADDRESS(x)  \
+        (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
+
+#define CS4_IO_ADDRESS(x)  \
+        (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
+
+#define X_MEMC_IO_ADDRESS(x)  \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+#define PCMCIA_IO_ADDRESS(x) \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+/* Start of physical RAM - On many MX31 platforms, this is the first SDRAM bank (CSD0) */
+#define PHYS_OFFSET             CSD0_BASE_ADDR
+
+/*
+ * Interrupt numbers
+ */
+#define MXC_INT_PEN_ADS7843     0
+#define MXC_INT_RESV1           1
+#define MXC_INT_CS8900A         2
+#define MXC_INT_I2C3            3
+#define MXC_INT_I2C2            4
+#define MXC_INT_MPEG4_ENCODER   5
+#define MXC_INT_RTIC            6
+#define MXC_INT_FIRI            7
+#define MXC_INT_MMC_SDHC2       8
+#define MXC_INT_MMC_SDHC1       9
+#define MXC_INT_I2C             10
+#define MXC_INT_SSI2            11
+#define MXC_INT_SSI1            12
+#define MXC_INT_CSPI2           13
+#define MXC_INT_CSPI1           14
+#define MXC_INT_ATA             15
+#define MXC_INT_MBX             16
+#define MXC_INT_CSPI3           17
+#define MXC_INT_UART3           18
+#define MXC_INT_IIM             19
+#define MXC_INT_SIM2            20
+#define MXC_INT_SIM1            21
+#define MXC_INT_RNGA            22
+#define MXC_INT_EVTMON          23
+#define MXC_INT_KPP             24
+#define MXC_INT_RTC             25
+#define MXC_INT_PWM             26
+#define MXC_INT_EPIT2           27
+#define MXC_INT_EPIT1           28
+#define MXC_INT_GPT             29
+#define MXC_INT_RESV30          30
+#define MXC_INT_RESV31          31
+#define MXC_INT_UART2           32
+#define MXC_INT_NANDFC          33
+#define MXC_INT_SDMA            34
+#define MXC_INT_USB1            35
+#define MXC_INT_USB2            36
+#define MXC_INT_USB3            37
+#define MXC_INT_USB4            38
+#define MXC_INT_MSHC1           39
+#define MXC_INT_MSHC2           40
+#define MXC_INT_IPU_ERR         41
+#define MXC_INT_IPU_SYN         42
+#define MXC_INT_RESV43          43
+#define MXC_INT_RESV44          44
+#define MXC_INT_UART1           45
+#define MXC_INT_UART4           46
+#define MXC_INT_UART5           47
+#define MXC_INT_ECT             48
+#define MXC_INT_SCC_SCM         49
+#define MXC_INT_SCC_SMN         50
+#define MXC_INT_GPIO2           51
+#define MXC_INT_GPIO1           52
+#define MXC_INT_CCM             53
+#define MXC_INT_PCMCIA          54
+#define MXC_INT_WDOG            55
+#define MXC_INT_GPIO3           56
+#define MXC_INT_RESV57          57
+#define MXC_INT_EXT_POWER       58
+#define MXC_INT_EXT_TEMPER      59
+#define MXC_INT_EXT_SENSOR60    60
+#define MXC_INT_EXT_SENSOR61    61
+#define MXC_INT_EXT_WDOG        62
+#define MXC_INT_EXT_TV          63
+
+#define MXC_MAX_INT_LINES       64
+
+#define MXC_GPIO_INT_BASE       MXC_MAX_INT_LINES
+
+/*!
+ * Number of GPIO port as defined in the IC Spec
+ */
+#define GPIO_PORT_NUM           3
+/*!
+ * Number of GPIO pins per port
+ */
+#define GPIO_NUM_PIN            32
+
+#define PROD_SIGNATURE          0x1     /* For MX31 */
+
+#define SYSTEM_REV_MIN          CHIP_REV_1_0
+#define SYSTEM_REV_NUM          3
+
+#endif                  /*  __ASM_ARCH_MXC_MX31_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
new file mode 100644
index 000000000000..0837f1f9ca31
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_H__
+#define __ASM_ARCH_MXC_H__
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+
+/*
+ *****************************************
+ * GPT  Register definitions             *
+ *****************************************
+ */
+#define MXC_GPT_GPTCR           IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
+#define MXC_GPT_GPTPR           IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
+#define MXC_GPT_GPTSR           IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
+#define MXC_GPT_GPTIR           IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
+#define MXC_GPT_GPTOCR1         IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
+#define MXC_GPT_GPTOCR2         IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
+#define MXC_GPT_GPTOCR3         IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
+#define MXC_GPT_GPTICR1         IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
+#define MXC_GPT_GPTICR2         IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
+#define MXC_GPT_GPTCNT          IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
+
+/*!
+ * GPT Control register bit definitions
+ */
+#define GPTCR_FO3                       (1 << 31)
+#define GPTCR_FO2                       (1 << 30)
+#define GPTCR_FO1                       (1 << 29)
+
+#define GPTCR_OM3_SHIFT                 26
+#define GPTCR_OM3_MASK                  (7 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_DISCONNECTED          (0 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_TOGGLE                (1 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_CLEAR                 (2 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_SET                   (3 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_GENERATE_LOW          (7 << GPTCR_OM3_SHIFT)
+
+#define GPTCR_OM2_SHIFT                 23
+#define GPTCR_OM2_MASK                  (7 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_DISCONNECTED          (0 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_TOGGLE                (1 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_CLEAR                 (2 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_SET                   (3 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_GENERATE_LOW          (7 << GPTCR_OM2_SHIFT)
+
+#define GPTCR_OM1_SHIFT                 20
+#define GPTCR_OM1_MASK                  (7 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_DISCONNECTED          (0 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_TOGGLE                (1 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_CLEAR                 (2 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_SET                   (3 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_GENERATE_LOW          (7 << GPTCR_OM1_SHIFT)
+
+#define GPTCR_IM2_SHIFT                 18
+#define GPTCR_IM2_MASK                  (3 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM2_CAPTURE_DISABLE       (0 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM2_CAPTURE_RISING        (1 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM2_CAPTURE_FALLING       (2 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM2_CAPTURE_BOTH          (3 << GPTCR_IM2_SHIFT)
+
+#define GPTCR_IM1_SHIFT                 16
+#define GPTCR_IM1_MASK                  (3 << GPTCR_IM1_SHIFT)
+#define GPTCR_IM1_CAPTURE_DISABLE       (0 << GPTCR_IM1_SHIFT)
+#define GPTCR_IM1_CAPTURE_RISING        (1 << GPTCR_IM1_SHIFT)
+#define GPTCR_IM1_CAPTURE_FALLING       (2 << GPTCR_IM1_SHIFT)
+#define GPTCR_IM1_CAPTURE_BOTH          (3 << GPTCR_IM1_SHIFT)
+
+#define GPTCR_SWR                       (1 << 15)
+#define GPTCR_FRR                       (1 << 9)
+
+#define GPTCR_CLKSRC_SHIFT              6
+#define GPTCR_CLKSRC_MASK               (7 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_NOCLOCK            (0 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_HIGHFREQ           (2 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_CLKIN              (3 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_CLK32K             (7 << GPTCR_CLKSRC_SHIFT)
+
+#define GPTCR_STOPEN                    (1 << 5)
+#define GPTCR_DOZEN                     (1 << 4)
+#define GPTCR_WAITEN                    (1 << 3)
+#define GPTCR_DBGEN                     (1 << 2)
+
+#define GPTCR_ENMOD                     (1 << 1)
+#define GPTCR_ENABLE                    (1 << 0)
+
+#define GPTSR_OF1                       (1 << 0)
+#define GPTSR_OF2                       (1 << 1)
+#define GPTSR_OF3                       (1 << 2)
+#define GPTSR_IF1                       (1 << 3)
+#define GPTSR_IF2                       (1 << 4)
+#define GPTSR_ROV                       (1 << 5)
+
+#define GPTIR_OF1IE                     GPTSR_OF1
+#define GPTIR_OF2IE                     GPTSR_OF2
+#define GPTIR_OF3IE                     GPTSR_OF3
+#define GPTIR_IF1IE                     GPTSR_IF1
+#define GPTIR_IF2IE                     GPTSR_IF2
+#define GPTIR_ROVIE                     GPTSR_ROV
+
+/*
+ *****************************************
+ * AVIC Registers                        *
+ *****************************************
+ */
+#define AVIC_BASE               IO_ADDRESS(AVIC_BASE_ADDR)
+#define AVIC_INTCNTL            (AVIC_BASE + 0x00)      /* int control reg */
+#define AVIC_NIMASK             (AVIC_BASE + 0x04)      /* int mask reg */
+#define AVIC_INTENNUM           (AVIC_BASE + 0x08)      /* int enable number reg */
+#define AVIC_INTDISNUM          (AVIC_BASE + 0x0C)      /* int disable number reg */
+#define AVIC_INTENABLEH         (AVIC_BASE + 0x10)      /* int enable reg high */
+#define AVIC_INTENABLEL         (AVIC_BASE + 0x14)      /* int enable reg low */
+#define AVIC_INTTYPEH           (AVIC_BASE + 0x18)      /* int type reg high */
+#define AVIC_INTTYPEL           (AVIC_BASE + 0x1C)      /* int type reg low */
+#define AVIC_NIPRIORITY7        (AVIC_BASE + 0x20)      /* norm int priority lvl7 */
+#define AVIC_NIPRIORITY6        (AVIC_BASE + 0x24)      /* norm int priority lvl6 */
+#define AVIC_NIPRIORITY5        (AVIC_BASE + 0x28)      /* norm int priority lvl5 */
+#define AVIC_NIPRIORITY4        (AVIC_BASE + 0x2C)      /* norm int priority lvl4 */
+#define AVIC_NIPRIORITY3        (AVIC_BASE + 0x30)      /* norm int priority lvl3 */
+#define AVIC_NIPRIORITY2        (AVIC_BASE + 0x34)      /* norm int priority lvl2 */
+#define AVIC_NIPRIORITY1        (AVIC_BASE + 0x38)      /* norm int priority lvl1 */
+#define AVIC_NIPRIORITY0        (AVIC_BASE + 0x3C)      /* norm int priority lvl0 */
+#define AVIC_NIVECSR            (AVIC_BASE + 0x40)      /* norm int vector/status */
+#define AVIC_FIVECSR            (AVIC_BASE + 0x44)      /* fast int vector/status */
+#define AVIC_INTSRCH            (AVIC_BASE + 0x48)      /* int source reg high */
+#define AVIC_INTSRCL            (AVIC_BASE + 0x4C)      /* int source reg low */
+#define AVIC_INTFRCH            (AVIC_BASE + 0x50)      /* int force reg high */
+#define AVIC_INTFRCL            (AVIC_BASE + 0x54)      /* int force reg low */
+#define AVIC_NIPNDH             (AVIC_BASE + 0x58)      /* norm int pending high */
+#define AVIC_NIPNDL             (AVIC_BASE + 0x5C)      /* norm int pending low */
+#define AVIC_FIPNDH             (AVIC_BASE + 0x60)      /* fast int pending high */
+#define AVIC_FIPNDL             (AVIC_BASE + 0x64)      /* fast int pending low */
+
+#define SYSTEM_PREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x20)
+#define SYSTEM_SREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x24)
+#define IIM_PROD_REV_SH         3
+#define IIM_PROD_REV_LEN        5
+
+#endif                          /*  __ASM_ARCH_MXC_H__ */
diff --git a/include/asm-arm/arch-mxc/system.h b/include/asm-arm/arch-mxc/system.h
new file mode 100644
index 000000000000..109956b41aca
--- /dev/null
+++ b/include/asm-arm/arch-mxc/system.h
@@ -0,0 +1,50 @@
+/*
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_MXC_SYSTEM_H__
+#define __ASM_ARCH_MXC_SYSTEM_H__
+
+/*!
+ * @file system.h
+ * @brief This file contains idle and reset functions.
+ *
+ * @ingroup System
+ */
+
+/*!
+ * This function puts the CPU into idle mode. It is called by default_idle()
+ * in process.c file.
+ */
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+/*
+ * This function resets the system. It is called by machine_restart().
+ *
+ * @param  mode         indicates different kinds of resets
+ */
+static inline void arch_reset(char mode)
+{
+        cpu_reset(0);
+}
+
+#endif                          /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/include/asm-arm/arch-mxc/timex.h b/include/asm-arm/arch-mxc/timex.h
new file mode 100644
index 000000000000..59019fa58f82
--- /dev/null
+++ b/include/asm-arm/arch-mxc/timex.h
@@ -0,0 +1,25 @@
+/*
+ *  Copyright (C) 1999 ARM Limited
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_MXC_TIMEX_H__
+#define __ASM_ARCH_MXC_TIMEX_H__
+
+#include <asm/hardware.h>       /* for CLOCK_TICK_RATE */
+
+#endif                          /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/include/asm-arm/arch-mxc/uncompress.h b/include/asm-arm/arch-mxc/uncompress.h
new file mode 100644
index 000000000000..ec5787d0e78c
--- /dev/null
+++ b/include/asm-arm/arch-mxc/uncompress.h
@@ -0,0 +1,79 @@
+/*
+ *  include/asm-arm/arch-mxc/uncompress.h
+ *
+ *
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
+#define __ASM_ARCH_MXC_UNCOMPRESS_H__
+
+#define __MXC_BOOT_UNCOMPRESS
+
+#include <asm/hardware.h>
+#include <asm/processor.h>
+
+#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
+
+#define USR2 0x98
+#define USR2_TXFE (1<<14)
+#define TXR  0x40
+#define UCR1 0x80
+#define UCR1_UARTEN 1
+
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  We search for the first enabled
+ * port in the most probable order.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
+ * This does not append a newline
+ */
+
+static void putc(int ch)
+{
+        static unsigned long serial_port = 0;
+
+        if (unlikely(serial_port == 0)) {
+                do {
+                        serial_port = UART1_BASE_ADDR;
+                        if (UART(UCR1) & UCR1_UARTEN)
+                                break;
+                        serial_port = UART2_BASE_ADDR;
+                        if (UART(UCR1) & UCR1_UARTEN)
+                                break;
+                        return;
+                } while (0);
+        }
+
+        while (!(UART(USR2) & USR2_TXFE))
+                cpu_relax();
+
+        UART(TXR) = ch;
+}
+
+#define flush() do { } while (0)
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
+
+#endif                          /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
diff --git a/include/asm-arm/arch-mxc/vmalloc.h b/include/asm-arm/arch-mxc/vmalloc.h
new file mode 100644
index 000000000000..83a73da895eb
--- /dev/null
+++ b/include/asm-arm/arch-mxc/vmalloc.h
@@ -0,0 +1,36 @@
+/*
+ *  Copyright (C) 2000 Russell King.
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_MXC_VMALLOC_H__
+#define __ASM_ARCH_MXC_VMALLOC_H__
+
+/*!
+ * @file vmalloc.h
+ *
+ * @brief This file contains platform specific macros for vmalloc.
+ *
+ * @ingroup System
+ */
+
+/*!
+ * vmalloc ending address
+ */
+#define VMALLOC_END       0xF4000000
+
+#endif                          /* __ASM_ARCH_MXC_VMALLOC_H__ */
diff --git a/include/asm-arm/arch-ns9xxx/regs-bbu.h b/include/asm-arm/arch-ns9xxx/regs-bbu.h
index e26269546240..7ee194dc6354 100644
--- a/include/asm-arm/arch-ns9xxx/regs-bbu.h
+++ b/include/asm-arm/arch-ns9xxx/regs-bbu.h
@@ -15,7 +15,31 @@
 
 /* BBus Utility */
 
-/* GPIO Configuration Register */
-#define BBU_GC(x)       __REG2(0x9060000c, (x))
+/* GPIO Configuration Registers block 1 */
+/* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is
+ * at 0 for each block.  That is, BBU_GCONFb1(0) is GPIO Configuration Register
+ * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */
+#define BBU_GCONFb1(x)  __REG2(0x90600010, (x))
+#define BBU_GCONFb2(x)  __REG2(0x90600100, (x))
+
+#define BBU_GCONFx_DIR(m)       __REGBIT(3 + (((m) & 7) << 2))
+#define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0)
+#define BBU_GCONFx_DIR_OUTPUT(m)        __REGVAL(BBU_GCONFx_DIR(m), 1)
+#define BBU_GCONFx_INV(m)       __REGBIT(2 + (((m) & 7) << 2))
+#define BBU_GCONFx_INV_NO(m)            __REGVAL(BBU_GCONFx_INV(m), 0)
+#define BBU_GCONFx_INV_YES(m)           __REGVAL(BBU_GCONFx_INV(m), 1)
+#define BBU_GCONFx_FUNC(m)      __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2)
+#define BBU_GCONFx_FUNC_0(m)            __REGVAL(BBU_GCONFx_FUNC(m), 0)
+#define BBU_GCONFx_FUNC_1(m)            __REGVAL(BBU_GCONFx_FUNC(m), 1)
+#define BBU_GCONFx_FUNC_2(m)            __REGVAL(BBU_GCONFx_FUNC(m), 2)
+#define BBU_GCONFx_FUNC_3(m)            __REGVAL(BBU_GCONFx_FUNC(m), 3)
+
+#define BBU_GCTRL1      __REG(0x90600030)
+#define BBU_GCTRL2      __REG(0x90600034)
+#define BBU_GCTRL3      __REG(0x90600120)
+
+#define BBU_GSTAT1      __REG(0x90600040)
+#define BBU_GSTAT2      __REG(0x90600044)
+#define BBU_GSTAT3      __REG(0x90600130)
 
 #endif /* ifndef __ASM_ARCH_REGSBBU_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-mem.h b/include/asm-arm/arch-ns9xxx/regs-mem.h
index 8ed8448767b9..fb455a0ed845 100644
--- a/include/asm-arm/arch-ns9xxx/regs-mem.h
+++ b/include/asm-arm/arch-ns9xxx/regs-mem.h
@@ -79,9 +79,9 @@
 #define MEM_SMC(x)      __REG2(0xa0700200, (x) << 3)
 
 /* Static Memory Configuration Register x: Write protect */
-#define MEM_SMC_WSMC            __REGBIT(20)
-#define MEM_SMC_WSMC_OFF                __REGVAL(MEM_SMC_WSMC, 0)
-#define MEM_SMC_WSMC_ON                 __REGVAL(MEM_SMC_WSMC, 1)
+#define MEM_SMC_PSMC            __REGBIT(20)
+#define MEM_SMC_PSMC_OFF                __REGVAL(MEM_SMC_PSMC, 0)
+#define MEM_SMC_PSMC_ON                 __REGVAL(MEM_SMC_PSMC, 1)
 
 /* Static Memory Configuration Register x: Buffer enable */
 #define MEM_SMC_BSMC            __REGBIT(19)
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys.h b/include/asm-arm/arch-ns9xxx/regs-sys.h
index a42546aeb92a..749262f86204 100644
--- a/include/asm-arm/arch-ns9xxx/regs-sys.h
+++ b/include/asm-arm/arch-ns9xxx/regs-sys.h
@@ -64,7 +64,7 @@
 
 /* Timer x Control register: Timer enable */
 #define SYS_TCx_TEN             __REGBIT(15)
-#define SYS_TCx_TEN_DIS                 __REGVAL(SYS_TCx_TEN, 1)
+#define SYS_TCx_TEN_DIS                 __REGVAL(SYS_TCx_TEN, 0)
 #define SYS_TCx_TEN_EN                  __REGVAL(SYS_TCx_TEN, 1)
 
 /* Timer x Control register: CPU debug mode */
diff --git a/include/asm-arm/arch-s3c2400/map.h b/include/asm-arm/arch-s3c2400/map.h
new file mode 100644
index 000000000000..1184d907b31e
--- /dev/null
+++ b/include/asm-arm/arch-s3c2400/map.h
@@ -0,0 +1,66 @@
+/* linux/include/asm-arm/arch-s3c2400/map.h
+ *
+ * Copyright 2003,2007  Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Copyright 2003, Lucas Correia Villa Real
+ *
+ * S3C2400 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C2400_PA_MEMCTRL      (0x14000000)
+#define S3C2400_PA_USBHOST      (0x14200000)
+#define S3C2400_PA_IRQ          (0x14400000)
+#define S3C2400_PA_DMA          (0x14600000)
+#define S3C2400_PA_CLKPWR       (0x14800000)
+#define S3C2400_PA_LCD          (0x14A00000)
+#define S3C2400_PA_UART         (0x15000000)
+#define S3C2400_PA_TIMER        (0x15100000)
+#define S3C2400_PA_USBDEV       (0x15200140)
+#define S3C2400_PA_WATCHDOG     (0x15300000)
+#define S3C2400_PA_IIC          (0x15400000)
+#define S3C2400_PA_IIS          (0x15508000)
+#define S3C2400_PA_GPIO         (0x15600000)
+#define S3C2400_PA_RTC          (0x15700040)
+#define S3C2400_PA_ADC          (0x15800000)
+#define S3C2400_PA_SPI          (0x15900000)
+
+#define S3C2400_PA_MMC          (0x15A00000)
+#define S3C2400_SZ_MMC          SZ_1M
+
+/* physical addresses of all the chip-select areas */
+
+#define S3C2400_CS0     (0x00000000)
+#define S3C2400_CS1     (0x02000000)
+#define S3C2400_CS2     (0x04000000)
+#define S3C2400_CS3     (0x06000000)
+#define S3C2400_CS4     (0x08000000)
+#define S3C2400_CS5     (0x0A000000)
+#define S3C2400_CS6     (0x0C000000)
+#define S3C2400_CS7     (0x0E000000)
+
+#define S3C2400_SDRAM_PA    (S3C2400_CS6)
+
+/* Use a single interface for common resources between S3C24XX cpus */
+
+#define S3C24XX_PA_IRQ          S3C2400_PA_IRQ
+#define S3C24XX_PA_MEMCTRL      S3C2400_PA_MEMCTRL
+#define S3C24XX_PA_USBHOST      S3C2400_PA_USBHOST
+#define S3C24XX_PA_DMA          S3C2400_PA_DMA
+#define S3C24XX_PA_CLKPWR       S3C2400_PA_CLKPWR
+#define S3C24XX_PA_LCD          S3C2400_PA_LCD
+#define S3C24XX_PA_UART         S3C2400_PA_UART
+#define S3C24XX_PA_TIMER        S3C2400_PA_TIMER
+#define S3C24XX_PA_USBDEV       S3C2400_PA_USBDEV
+#define S3C24XX_PA_WATCHDOG     S3C2400_PA_WATCHDOG
+#define S3C24XX_PA_IIC          S3C2400_PA_IIC
+#define S3C24XX_PA_IIS          S3C2400_PA_IIS
+#define S3C24XX_PA_GPIO         S3C2400_PA_GPIO
+#define S3C24XX_PA_RTC          S3C2400_PA_RTC
+#define S3C24XX_PA_ADC          S3C2400_PA_ADC
+#define S3C24XX_PA_SPI          S3C2400_PA_SPI
diff --git a/include/asm-arm/arch-s3c2400/memory.h b/include/asm-arm/arch-s3c2400/memory.h
new file mode 100644
index 000000000000..fb0381dde704
--- /dev/null
+++ b/include/asm-arm/arch-s3c2400/memory.h
@@ -0,0 +1,23 @@
+/* linux/include/asm-arm/arch-s3c2400/memory.h
+ *  from linux/include/asm-arm/arch-rpc/memory.h
+ *
+ *  Copyright 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ *  Copyright (C) 1996,1997,1998 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET     UL(0x0C000000)
+
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
index 93064860e0e5..9c8cd9abb82b 100644
--- a/include/asm-arm/arch-s3c2410/debug-macro.S
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -13,32 +13,23 @@
 */
 
 #include <asm/arch/map.h>
-#include <asm/arch/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 #define S3C2410_UART1_OFF (0x4000)
 #define SHIFT_2440TXF (14-9)
 
-                .macro addruart, rx
+        .macro addruart, rx
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1
                 ldreq   \rx, = S3C24XX_PA_UART
                 ldrne   \rx, = S3C24XX_VA_UART
-#if CONFIG_DEBUG_S3C2410_UART != 0
-                add     \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C2410_UART)
+#if CONFIG_DEBUG_S3C_UART != 0
+                add     \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
 #endif
-                .endm
+        .endm
 
-                .macro  senduart,rd,rx
-                strb    \rd, [\rx, # S3C2410_UTXH ]
-                .endm
-
-                .macro  busyuart, rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFCON ]
-                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
-                beq     1001f                           @
-                @ FIFO enabled...
-1003:
+        .macro fifo_full_s3c24xx rd, rx
                 @ check for arm920 vs arm926. currently assume all arm926
                 @ devices have an 64 byte FIFO identical to the s3c2440
                 mrc     p15, 0, \rd, c0, c0
@@ -57,25 +48,22 @@
                 ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
                 moveq   \rd, \rd, lsr #SHIFT_2440TXF
                 tst     \rd, #S3C2410_UFSTAT_TXFULL
-                bne     1003b
-                b       1002f
-
-1001:
-                @ busy waiting for non fifo
-                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
-                tst     \rd, #S3C2410_UTRSTAT_TXFE
-                beq     1001b
+        .endm
 
-1002:           @ exit busyuart
-                .endm
+        .macro  fifo_full_s3c2410 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                tst     \rd, #S3C2410_UFSTAT_TXFULL
+        .endm
 
-                .macro  waituart,rd,rx
+/* fifo level reading */
 
-                ldr     \rd, [ \rx, # S3C2410_UFCON ]
-                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
-                beq     1001f                           @
-                @ FIFO enabled...
-1003:
+        .macro fifo_level_s3c24xx rd, rx
+                @ check for arm920 vs arm926. currently assume all arm926
+                @ devices have an 64 byte FIFO identical to the s3c2440
+                mrc     p15, 0, \rd, c0, c0
+                and     \rd, \rd, #0xff0
+                teq     \rd, #0x260
+                beq     10000f
                 mrc     p15, 0, \rd, c1, c0
                 tst     \rd, #1
                 addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
@@ -85,18 +73,32 @@
                 and     \rd, \rd, #0x00ff0000
                 teq     \rd, #0x00440000                @ is it 2440?
 
+10000:
                 ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
                 andne   \rd, \rd, #S3C2410_UFSTAT_TXMASK
                 andeq   \rd, \rd, #S3C2440_UFSTAT_TXMASK
-                teq     \rd, #0
-                bne     1003b
-                b       1002f
+        .endm
+
+        .macro fifo_level_s3c2410 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                and     \rd, \rd, #S3C2410_UFSTAT_TXMASK
+        .endm
+
+/* Select the correct implementation depending on the configuration. The
+ * S3C2440 will get selected by default, as these are the most widely
+ * used variants of these
+*/
+
+#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
+#define fifo_full  fifo_full_s3c2410
+#define fifo_level fifo_level_s3c2410
+#warning 2410only
+#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
+#define fifo_full  fifo_full_s3c24xx
+#define fifo_level fifo_level_s3c24xx
+#warning generic
+#endif
 
-1001:
-                @ idle waiting for non fifo
-                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
-                tst     \rd, #S3C2410_UTRSTAT_TXFE
-                beq     1001b
+/* include the reset of the code which will do the work */
 
-1002:           @ exit busyuart
-                .endm
+#include <asm/plat-s3c/debug-macro.S>
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
index 19e77f038042..b33ed3b05ef5 100644
--- a/include/asm-arm/arch-s3c2410/map.h
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -13,58 +13,36 @@
 #ifndef __ASM_ARCH_MAP_H
 #define __ASM_ARCH_MAP_H
 
-/* we have a bit of a tight squeeze to fit all our registers from
- * 0xF00000000 upwards, since we use all of the nGCS space in some
- * capacity, and also need to fit the S3C2410 registers in as well...
- *
- * we try to ensure stuff like the IRQ registers are available for
- * an single MOVS instruction (ie, only 8 bits of set data)
- *
- * Note, we are trying to remove some of these from the implementation
- * as they are only useful to certain drivers...
- */
-
-#ifndef __ASSEMBLY__
-#define S3C2410_ADDR(x)   ((void __iomem __force *)0xF0000000 + (x))
-#else
-#define S3C2410_ADDR(x)   (0xF0000000 + (x))
-#endif
+#include <asm/plat-s3c/map.h>
 
-#define S3C2400_ADDR(x)   S3C2410_ADDR(x)
+#define S3C2410_ADDR(x)         S3C_ADDR(x)
 
 /* interrupt controller is the first thing we put in, to make
  * the assembly code for the irq detection easier
  */
-#define S3C24XX_VA_IRQ     S3C2410_ADDR(0x00000000)
-#define S3C2400_PA_IRQ     (0x14400000)
+#define S3C24XX_VA_IRQ     S3C_VA_IRQ
 #define S3C2410_PA_IRQ     (0x4A000000)
 #define S3C24XX_SZ_IRQ     SZ_1M
 
 /* memory controller registers */
-#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)
-#define S3C2400_PA_MEMCTRL (0x14000000)
+#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
 #define S3C2410_PA_MEMCTRL (0x48000000)
 #define S3C24XX_SZ_MEMCTRL SZ_1M
 
 /* USB host controller */
-#define S3C2400_PA_USBHOST (0x14200000)
 #define S3C2410_PA_USBHOST (0x49000000)
 #define S3C24XX_SZ_USBHOST SZ_1M
 
 /* DMA controller */
-#define S3C2400_PA_DMA     (0x14600000)
 #define S3C2410_PA_DMA     (0x4B000000)
 #define S3C24XX_SZ_DMA     SZ_1M
 
 /* Clock and Power management */
-#define S3C24XX_VA_CLKPWR  S3C2410_ADDR(0x00200000)
-#define S3C2400_PA_CLKPWR  (0x14800000)
+#define S3C24XX_VA_CLKPWR  S3C_VA_SYS
 #define S3C2410_PA_CLKPWR  (0x4C000000)
 #define S3C24XX_SZ_CLKPWR  SZ_1M
 
 /* LCD controller */
-#define S3C24XX_VA_LCD     S3C2410_ADDR(0x00300000)
-#define S3C2400_PA_LCD     (0x14A00000)
 #define S3C2410_PA_LCD     (0x4D000000)
 #define S3C24XX_SZ_LCD     SZ_1M
 
@@ -72,41 +50,30 @@
 #define S3C2410_PA_NAND    (0x4E000000)
 #define S3C24XX_SZ_NAND    SZ_1M
 
-/* MMC controller - available on the S3C2400 */
-#define S3C2400_PA_MMC     (0x15A00000)
-#define S3C2400_SZ_MMC     SZ_1M
-
 /* UARTs */
-#define S3C24XX_VA_UART    S3C2410_ADDR(0x00400000)
-#define S3C2400_PA_UART    (0x15000000)
+#define S3C24XX_VA_UART    S3C_VA_UART
 #define S3C2410_PA_UART    (0x50000000)
 #define S3C24XX_SZ_UART    SZ_1M
 
 /* Timers */
-#define S3C24XX_VA_TIMER   S3C2410_ADDR(0x00500000)
-#define S3C2400_PA_TIMER   (0x15100000)
+#define S3C24XX_VA_TIMER   S3C_VA_TIMER
 #define S3C2410_PA_TIMER   (0x51000000)
 #define S3C24XX_SZ_TIMER   SZ_1M
 
 /* USB Device port */
-#define S3C24XX_VA_USBDEV  S3C2410_ADDR(0x00600000)
-#define S3C2400_PA_USBDEV  (0x15200140)
 #define S3C2410_PA_USBDEV  (0x52000000)
 #define S3C24XX_SZ_USBDEV  SZ_1M
 
 /* Watchdog */
-#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000)
-#define S3C2400_PA_WATCHDOG (0x15300000)
+#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
 #define S3C2410_PA_WATCHDOG (0x53000000)
 #define S3C24XX_SZ_WATCHDOG SZ_1M
 
 /* IIC hardware controller */
-#define S3C2400_PA_IIC     (0x15400000)
 #define S3C2410_PA_IIC     (0x54000000)
 #define S3C24XX_SZ_IIC     SZ_1M
 
 /* IIS controller */
-#define S3C2400_PA_IIS     (0x15508000)
 #define S3C2410_PA_IIS     (0x55000000)
 #define S3C24XX_SZ_IIS     SZ_1M
 
@@ -116,27 +83,23 @@
  * it is the same distance apart from the UART in the
  * phsyical address space, as the initial mapping for the IO
  * is done as a 1:1 maping. This puts it (currently) at
- * 0xF6800000, which is not in the way of any current mapping
+ * 0xFA800000, which is not in the way of any current mapping
  * by the base system.
 */
 
-#define S3C2400_PA_GPIO    (0x15600000)
 #define S3C2410_PA_GPIO    (0x56000000)
 #define S3C24XX_VA_GPIO    ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
 #define S3C24XX_SZ_GPIO    SZ_1M
 
 /* RTC */
-#define S3C2400_PA_RTC     (0x15700040)
 #define S3C2410_PA_RTC     (0x57000000)
 #define S3C24XX_SZ_RTC     SZ_1M
 
 /* ADC */
-#define S3C2400_PA_ADC     (0x15800000)
 #define S3C2410_PA_ADC     (0x58000000)
 #define S3C24XX_SZ_ADC     SZ_1M
 
 /* SPI */
-#define S3C2400_PA_SPI     (0x15900000)
 #define S3C2410_PA_SPI     (0x59000000)
 #define S3C24XX_SZ_SPI     SZ_1M
 
@@ -177,37 +140,8 @@
 
 #define S3C2410_SDRAM_PA    (S3C2410_CS6)
 
-#define S3C2400_CS0 (0x00000000)
-#define S3C2400_CS1 (0x02000000)
-#define S3C2400_CS2 (0x04000000)
-#define S3C2400_CS3 (0x06000000)
-#define S3C2400_CS4 (0x08000000)
-#define S3C2400_CS5 (0x0A000000)
-#define S3C2400_CS6 (0x0C000000)
-#define S3C2400_CS7 (0x0E000000)
-
-#define S3C2400_SDRAM_PA    (S3C2400_CS6)
-
 /* Use a single interface for common resources between S3C24XX cpus */
 
-#ifdef CONFIG_CPU_S3C2400
-#define S3C24XX_PA_IRQ      S3C2400_PA_IRQ
-#define S3C24XX_PA_MEMCTRL  S3C2400_PA_MEMCTRL
-#define S3C24XX_PA_USBHOST  S3C2400_PA_USBHOST
-#define S3C24XX_PA_DMA      S3C2400_PA_DMA
-#define S3C24XX_PA_CLKPWR   S3C2400_PA_CLKPWR
-#define S3C24XX_PA_LCD      S3C2400_PA_LCD
-#define S3C24XX_PA_UART     S3C2400_PA_UART
-#define S3C24XX_PA_TIMER    S3C2400_PA_TIMER
-#define S3C24XX_PA_USBDEV   S3C2400_PA_USBDEV
-#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
-#define S3C24XX_PA_IIC      S3C2400_PA_IIC
-#define S3C24XX_PA_IIS      S3C2400_PA_IIS
-#define S3C24XX_PA_GPIO     S3C2400_PA_GPIO
-#define S3C24XX_PA_RTC      S3C2400_PA_RTC
-#define S3C24XX_PA_ADC      S3C2400_PA_ADC
-#define S3C24XX_PA_SPI      S3C2400_PA_SPI
-#else
 #define S3C24XX_PA_IRQ      S3C2410_PA_IRQ
 #define S3C24XX_PA_MEMCTRL  S3C2410_PA_MEMCTRL
 #define S3C24XX_PA_USBHOST  S3C2410_PA_USBHOST
@@ -224,7 +158,6 @@
 #define S3C24XX_PA_RTC      S3C2410_PA_RTC
 #define S3C24XX_PA_ADC      S3C2410_PA_ADC
 #define S3C24XX_PA_SPI      S3C2410_PA_SPI
-#endif
 
 /* deal with the registers that move under the 2412/2413 */
 
diff --git a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h
index 4be6a74c4303..533e2436e707 100644
--- a/include/asm-arm/arch-s3c2410/memory.h
+++ b/include/asm-arm/arch-s3c2410/memory.h
@@ -11,20 +11,7 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
 
-/*
- * DRAM starts at 0x30000000 for S3C2410/S3C2440
- * and at 0x0C000000 for S3C2400
- */
-#ifdef CONFIG_CPU_S3C2400
-#define PHYS_OFFSET     UL(0x0C000000)
-#else
 #define PHYS_OFFSET     UL(0x30000000)
-#endif
-
-/*
- * These are exactly the same on the S3C2410 as the
- * physical memory view.
-*/
 
 #define __virt_to_bus(x) __virt_to_phys(x)
 #define __bus_to_virt(x) __phys_to_virt(x)
diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h
index b7faeb04c0ff..76fe5f693426 100644
--- a/include/asm-arm/arch-s3c2410/regs-lcd.h
+++ b/include/asm-arm/arch-s3c2410/regs-lcd.h
@@ -12,7 +12,7 @@
 #ifndef ___ASM_ARCH_REGS_LCD_H
 #define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $"
 
-#define S3C2410_LCDREG(x) ((x) + S3C24XX_VA_LCD)
+#define S3C2410_LCDREG(x)       (x)
 
 /* LCD control registers */
 #define S3C2410_LCDCON1     S3C2410_LCDREG(0x00)
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
index 1c74ef17da33..63891786dfa0 100644
--- a/include/asm-arm/arch-s3c2410/system.h
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -17,7 +17,7 @@
 #include <asm/arch/idle.h>
 #include <asm/arch/reset.h>
 
-#include <asm/arch/regs-watchdog.h>
+#include <asm/plat-s3c/regs-watchdog.h>
 #include <asm/arch/regs-clock.h>
 
 void (*s3c24xx_idle)(void);
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
index dcb2cef38f50..48a5731ee988 100644
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -1,6 +1,7 @@
 /* linux/include/asm-arm/arch-s3c2410/uncompress.h
  *
- * Copyright (c) 2003 Simtec Electronics
+ * Copyright (c) 2003, 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
  *      Ben Dooks <ben@simtec.co.uk>
  *
  * S3C2410 - uncompress code
@@ -13,153 +14,39 @@
 #ifndef __ASM_ARCH_UNCOMPRESS_H
 #define __ASM_ARCH_UNCOMPRESS_H
 
-typedef unsigned int upf_t;     /* cannot include linux/serial_core.h */
-
-/* defines for UART registers */
-#include "asm/arch/regs-serial.h"
-#include "asm/arch/regs-gpio.h"
-#include "asm/arch/regs-watchdog.h"
-
+#include <asm/arch/regs-gpio.h>
 #include <asm/arch/map.h>
 
 /* working in physical space... */
 #undef S3C2410_GPIOREG
-#undef S3C2410_WDOGREG
-
 #define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
-#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
 
-/* how many bytes we allow into the FIFO at a time in FIFO mode */
-#define FIFO_MAX         (14)
+#include <asm/plat-s3c/uncompress.h>
 
-#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C2410_LOWLEVEL_UART_PORT)
-
-static __inline__ void
-uart_wr(unsigned int reg, unsigned int val)
+static inline int is_arm926(void)
 {
-        volatile unsigned int *ptr;
-
-        ptr = (volatile unsigned int *)(reg + uart_base);
-        *ptr = val;
-}
+        unsigned int cpuid;
 
-static __inline__ unsigned int
-uart_rd(unsigned int reg)
-{
-        volatile unsigned int *ptr;
+        asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid));
 
-        ptr = (volatile unsigned int *)(reg + uart_base);
-        return *ptr;
+        return ((cpuid & 0xff0) == 0x260);
 }
 
-
-/* we can deal with the case the UARTs are being run
- * in FIFO mode, so that we don't hold up our execution
- * waiting for tx to happen...
-*/
-
-static void putc(int ch)
+static void arch_detect_cpu(void)
 {
-        int cpuid = S3C2410_GSTATUS1_2410;
+        unsigned int cpuid;
 
-#ifndef CONFIG_CPU_S3C2400
         cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
         cpuid &= S3C2410_GSTATUS1_IDMASK;
-#endif
-
-        if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
-                int level;
-
-                while (1) {
-                        level = uart_rd(S3C2410_UFSTAT);
-
-                        if (cpuid == S3C2410_GSTATUS1_2440 ||
-                            cpuid == S3C2410_GSTATUS1_2442) {
-                                level &= S3C2440_UFSTAT_TXMASK;
-                                level >>= S3C2440_UFSTAT_TXSHIFT;
-                        } else {
-                                level &= S3C2410_UFSTAT_TXMASK;
-                                level >>= S3C2410_UFSTAT_TXSHIFT;
-                        }
-
-                        if (level < FIFO_MAX)
-                                break;
-                }
 
+        if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
+            cpuid == S3C2410_GSTATUS1_2442) {
+                fifo_mask = S3C2440_UFSTAT_TXMASK;
+                fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
         } else {
-                /* not using fifos */
-
-                while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
-                        barrier();
+                fifo_mask = S3C2410_UFSTAT_TXMASK;
+                fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
         }
-
-        /* write byte to transmission register */
-        uart_wr(S3C2410_UTXH, ch);
 }
 
-static inline void flush(void)
-{
-}
-
-#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
-
-/* CONFIG_S3C2410_BOOT_WATCHDOG
- *
- * Simple boot-time watchdog setup, to reboot the system if there is
- * any problem with the boot process
-*/
-
-#ifdef CONFIG_S3C2410_BOOT_WATCHDOG
-
-#define WDOG_COUNT (0xff00)
-
-static inline void arch_decomp_wdog(void)
-{
-        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-}
-
-static void arch_decomp_wdog_start(void)
-{
-        __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
-        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
-}
-
-#else
-#define arch_decomp_wdog_start()
-#define arch_decomp_wdog()
-#endif
-
-#ifdef CONFIG_S3C2410_BOOT_ERROR_RESET
-
-static void arch_decomp_error(const char *x)
-{
-        putstr("\n\n");
-        putstr(x);
-        putstr("\n\n -- System resetting\n");
-
-        __raw_writel(0x4000, S3C2410_WTDAT);
-        __raw_writel(0x4000, S3C2410_WTCNT);
-        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
-
-        while(1);
-}
-
-#define arch_error arch_decomp_error
-#endif
-
-static void error(char *err);
-
-static void
-arch_decomp_setup(void)
-{
-        /* we may need to setup the uart(s) here if we are not running
-         * on an BAST... the BAST will have left the uarts configured
-         * after calling linux.
-         */
-
-        arch_decomp_wdog_start();
-}
-
-
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/include/asm-arm/arch-sa1100/jornada720.h b/include/asm-arm/arch-sa1100/jornada720.h
new file mode 100644
index 000000000000..45d2bb59f9d0
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/jornada720.h
@@ -0,0 +1,27 @@
+/*
+ * include/asm-arm/arch-sa1100/jornada720.h
+ *
+ * This file contains SSP/MCU communication definitions for HP Jornada 710/720/728
+ *
+ * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
+ *  Copyright (C) 2000 John Ankcorn <jca@lcs.mit.edu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+ /* HP Jornada 7xx microprocessor commands */
+#define GETBATTERYDATA          0xc0
+#define GETSCANKEYCODE          0x90
+#define GETTOUCHSAMPLES         0xa0
+#define GETCONTRAST             0xD0
+#define SETCONTRAST             0xD1
+#define GETBRIGHTNESS           0xD2
+#define SETBRIGHTNESS           0xD3
+#define CONTRASTOFF             0xD8
+#define BRIGHTNESSOFF           0xD9
+#define PWMOFF                  0xDF
+#define TXDUMMY                 0x11
+#define ERRORCODE               0x00
diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h
index d7a777f05088..ec1c685562ce 100644
--- a/include/asm-arm/elf.h
+++ b/include/asm-arm/elf.h
@@ -1,13 +1,14 @@
 #ifndef __ASMARM_ELF_H
 #define __ASMARM_ELF_H
 
+#include <asm/hwcap.h>
+
 #ifndef __ASSEMBLY__
 /*
  * ELF register definitions..
  */
 #include <asm/ptrace.h>
 #include <asm/user.h>
-#include <asm/hwcap.h>
 
 typedef unsigned long elf_greg_t;
 typedef unsigned long elf_freg_t[3];
diff --git a/include/asm-arm/floppy.h b/include/asm-arm/floppy.h
index 54b5ae44ed94..d595c15166a4 100644
--- a/include/asm-arm/floppy.h
+++ b/include/asm-arm/floppy.h
@@ -30,15 +30,21 @@
 #define fd_disable_irq()        disable_irq(IRQ_FLOPPYDISK)
 #define fd_enable_irq()         enable_irq(IRQ_FLOPPYDISK)
 
+static inline int fd_dma_setup(void *data, unsigned int length,
+                               unsigned int mode, unsigned long addr)
+{
+        set_dma_mode(DMA_FLOPPY, mode);
+        __set_dma_addr(DMA_FLOPPY, data);
+        set_dma_count(DMA_FLOPPY, length);
+        virtual_dma_port = addr;
+        enable_dma(DMA_FLOPPY);
+        return 0;
+}
+#define fd_dma_setup            fd_dma_setup
+
 #define fd_request_dma()        request_dma(DMA_FLOPPY,"floppy")
 #define fd_free_dma()           free_dma(DMA_FLOPPY)
 #define fd_disable_dma()        disable_dma(DMA_FLOPPY)
-#define fd_enable_dma()         enable_dma(DMA_FLOPPY)
-#define fd_clear_dma_ff()       clear_dma_ff(DMA_FLOPPY)
-#define fd_set_dma_mode(mode)   set_dma_mode(DMA_FLOPPY, (mode))
-#define fd_set_dma_addr(addr)   set_dma_addr(DMA_FLOPPY, virt_to_bus((addr)))
-#define fd_set_dma_count(len)   set_dma_count(DMA_FLOPPY, (len))
-#define fd_cacheflush(addr,sz)
 
 /* need to clean up dma.h */
 #define DMA_FLOPPYDISK          DMA_FLOPPY
diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h
index 81ca5d3e2bff..fb90b421f31c 100644
--- a/include/asm-arm/hardware/iop3xx.h
+++ b/include/asm-arm/hardware/iop3xx.h
@@ -194,6 +194,13 @@ extern int init_atu;
 #define IOP_TMR_PRIVILEGED 0x08
 #define IOP_TMR_RATIO_1_1  0x00
 
+/* Watchdog timer definitions */
+#define IOP_WDTCR_EN_ARM        0x1e1e1e1e
+#define IOP_WDTCR_EN            0xe1e1e1e1
+/* iop3xx does not support stopping the watchdog, so we just re-arm */
+#define IOP_WDTCR_DIS_ARM       (IOP_WDTCR_EN_ARM)
+#define IOP_WDTCR_DIS           (IOP_WDTCR_EN)
+
 /* Application accelerator unit  */
 #define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
 #define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)
@@ -274,6 +281,32 @@ static inline void write_tisr(u32 val)
         asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
 }
 
+static inline u32 read_wdtcr(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val));
+        return val;
+}
+static inline void write_wdtcr(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val));
+}
+
+extern unsigned long get_iop_tick_rate(void);
+
+/* only iop13xx has these registers, we define these to present a
+ * common register interface for the iop_wdt driver.
+ */
+#define IOP_RCSR_WDT    (0)
+static inline u32 read_rcsr(void)
+{
+        return 0;
+}
+static inline void write_wdtsr(u32 val)
+{
+        do { } while (0);
+}
+
 extern struct platform_device iop3xx_dma_0_channel;
 extern struct platform_device iop3xx_dma_1_channel;
 extern struct platform_device iop3xx_aau_channel;
diff --git a/include/asm-arm/pgtable-nommu.h b/include/asm-arm/pgtable-nommu.h
index 0c8be19fd66b..b186bc820e30 100644
--- a/include/asm-arm/pgtable-nommu.h
+++ b/include/asm-arm/pgtable-nommu.h
@@ -102,7 +102,8 @@ extern int is_in_rom(unsigned long);
 #define v4_tlb_fns      (0)
 #define v4wb_tlb_fns    (0)
 #define v4wbi_tlb_fns   (0)
-#define v6_tlb_fns      (0)
+#define v6wbi_tlb_fns   (0)
+#define v7wbi_tlb_fns   (0)
 
 #define v3_user_fns     (0)
 #define v4_user_fns     (0)
diff --git a/include/asm-arm/plat-s3c/debug-macro.S b/include/asm-arm/plat-s3c/debug-macro.S
new file mode 100644
index 000000000000..84c40b847da8
--- /dev/null
+++ b/include/asm-arm/plat-s3c/debug-macro.S
@@ -0,0 +1,75 @@
+/* linux/include/asm-arm/plat-s3c/debug-macro.S
+ *
+ * Copyright 2005, 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <asm/plat-s3c/regs-serial.h>
+
+/* The S3C2440 implementations are used by default as they are the
+ * most widely re-used */
+
+        .macro fifo_level_s3c2440 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                and     \rd, \rd, #S3C2440_UFSTAT_TXMASK
+        .endm
+
+#ifndef fifo_level
+#define fifo_level fifo_level_s3c2410
+#endif
+
+        .macro  fifo_full_s3c2440 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                tst     \rd, #S3C2440_UFSTAT_TXFULL
+        .endm
+
+#ifndef fifo_full
+#define fifo_full fifo_full_s3c2440
+#endif
+
+        .macro  senduart,rd,rx
+                strb    \rd, [\rx, # S3C2410_UTXH ]
+        .endm
+
+        .macro  busyuart, rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFCON ]
+                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
+                beq     1001f                           @
+                @ FIFO enabled...
+1003:
+                fifo_full \rd, \rx
+                bne     1003b
+                b       1002f
+
+1001:
+                @ busy waiting for non fifo
+                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
+                tst     \rd, #S3C2410_UTRSTAT_TXFE
+                beq     1001b
+
+1002:           @ exit busyuart
+        .endm
+
+        .macro  waituart,rd,rx
+                ldr     \rd, [ \rx, # S3C2410_UFCON ]
+                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
+                beq     1001f                           @
+                @ FIFO enabled...
+1003:
+                fifo_level \rd, \rx
+                teq     \rd, #0
+                bne     1003b
+                b       1002f
+1001:
+                @ idle waiting for non fifo
+                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
+                tst     \rd, #S3C2410_UTRSTAT_TXFE
+                beq     1001b
+
+1002:           @ exit busyuart
+        .endm
diff --git a/include/asm-arm/arch-s3c2410/iic.h b/include/asm-arm/plat-s3c/iic.h
index 71211c8b5384..71211c8b5384 100644
--- a/include/asm-arm/arch-s3c2410/iic.h
+++ b/include/asm-arm/plat-s3c/iic.h
diff --git a/include/asm-arm/plat-s3c/map.h b/include/asm-arm/plat-s3c/map.h
new file mode 100644
index 000000000000..95a82b0e84a1
--- /dev/null
+++ b/include/asm-arm/plat-s3c/map.h
@@ -0,0 +1,40 @@
+/* linux/include/asm-arm/plat-s3c/map.h
+ *
+ * Copyright 2003, 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - Memory map definitions (virtual addresses)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_MAP_H
+#define __ASM_PLAT_MAP_H __FILE__
+
+/* Fit all our registers in at 0xF4000000 upwards, trying to use as
+ * little of the VA space as possible so vmalloc and friends have a
+ * better chance of getting memory.
+ *
+ * we try to ensure stuff like the IRQ registers are available for
+ * an single MOVS instruction (ie, only 8 bits of set data)
+ */
+
+#define S3C_ADDR_BASE   (0xF4000000)
+
+#ifndef __ASSEMBLY__
+#define S3C_ADDR(x)     ((void __iomem __force *)S3C_ADDR_BASE + (x))
+#else
+#define S3C_ADDR(x)     (S3C_ADDR_BASE + (x))
+#endif
+
+#define S3C_VA_IRQ      S3C_ADDR(0x000000000)   /* irq controller(s) */
+#define S3C_VA_SYS      S3C_ADDR(0x001000000)   /* system control */
+#define S3C_VA_MEM      S3C_ADDR(0x002000000)   /* system control */
+#define S3C_VA_TIMER    S3C_ADDR(0x003000000)   /* timer block */
+#define S3C_VA_WATCHDOG S3C_ADDR(0x004000000)   /* watchdog */
+#define S3C_VA_UART     S3C_ADDR(0x010000000)   /* UART */
+
+#endif /* __ASM_PLAT_MAP_H */
diff --git a/include/asm-arm/arch-s3c2410/nand.h b/include/asm-arm/plat-s3c/nand.h
index 8816f7f9cee1..8816f7f9cee1 100644
--- a/include/asm-arm/arch-s3c2410/nand.h
+++ b/include/asm-arm/plat-s3c/nand.h
diff --git a/include/asm-arm/arch-s3c2410/regs-ac97.h b/include/asm-arm/plat-s3c/regs-ac97.h
index b004dee6bcaf..b004dee6bcaf 100644
--- a/include/asm-arm/arch-s3c2410/regs-ac97.h
+++ b/include/asm-arm/plat-s3c/regs-ac97.h
diff --git a/include/asm-arm/arch-s3c2410/regs-adc.h b/include/asm-arm/plat-s3c/regs-adc.h
index c7f231963e76..c7f231963e76 100644
--- a/include/asm-arm/arch-s3c2410/regs-adc.h
+++ b/include/asm-arm/plat-s3c/regs-adc.h
diff --git a/include/asm-arm/arch-s3c2410/regs-iic.h b/include/asm-arm/plat-s3c/regs-iic.h
index 2ae29522f253..2ae29522f253 100644
--- a/include/asm-arm/arch-s3c2410/regs-iic.h
+++ b/include/asm-arm/plat-s3c/regs-iic.h
diff --git a/include/asm-arm/arch-s3c2410/regs-nand.h b/include/asm-arm/plat-s3c/regs-nand.h
index b824d371ae0b..b824d371ae0b 100644
--- a/include/asm-arm/arch-s3c2410/regs-nand.h
+++ b/include/asm-arm/plat-s3c/regs-nand.h
diff --git a/include/asm-arm/arch-s3c2410/regs-rtc.h b/include/asm-arm/plat-s3c/regs-rtc.h
index 93b03c49710a..93b03c49710a 100644
--- a/include/asm-arm/arch-s3c2410/regs-rtc.h
+++ b/include/asm-arm/plat-s3c/regs-rtc.h
diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/plat-s3c/regs-serial.h
index 8946702a87f5..923e114db663 100644
--- a/include/asm-arm/arch-s3c2410/regs-serial.h
+++ b/include/asm-arm/plat-s3c/regs-serial.h
@@ -32,10 +32,10 @@
 #ifndef __ASM_ARM_REGS_SERIAL_H
 #define __ASM_ARM_REGS_SERIAL_H
 
-#define S3C24XX_VA_UART0      (S3C24XX_VA_UART)
-#define S3C24XX_VA_UART1      (S3C24XX_VA_UART + 0x4000 )
-#define S3C24XX_VA_UART2      (S3C24XX_VA_UART + 0x8000 )
-#define S3C24XX_VA_UART3      (S3C24XX_VA_UART + 0xC000 )
+#define S3C24XX_VA_UART0      (S3C_VA_UART)
+#define S3C24XX_VA_UART1      (S3C_VA_UART + 0x4000 )
+#define S3C24XX_VA_UART2      (S3C_VA_UART + 0x8000 )
+#define S3C24XX_VA_UART3      (S3C_VA_UART + 0xC000 )
 
 #define S3C2410_PA_UART0      (S3C24XX_PA_UART)
 #define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
diff --git a/include/asm-arm/arch-s3c2410/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h
index 6f8fe432fe3a..8b0d594397b1 100644
--- a/include/asm-arm/arch-s3c2410/regs-timer.h
+++ b/include/asm-arm/plat-s3c/regs-timer.h
@@ -14,12 +14,12 @@
 #ifndef __ASM_ARCH_REGS_TIMER_H
 #define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"
 
-#define S3C2410_TIMERREG(x) (S3C24XX_VA_TIMER + (x))
-#define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c))
+#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
+#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
 
-#define S3C2410_TCFG0         S3C2410_TIMERREG(0x00)
-#define S3C2410_TCFG1         S3C2410_TIMERREG(0x04)
-#define S3C2410_TCON          S3C2410_TIMERREG(0x08)
+#define S3C2410_TCFG0         S3C_TIMERREG(0x00)
+#define S3C2410_TCFG1         S3C_TIMERREG(0x04)
+#define S3C2410_TCON          S3C_TIMERREG(0x08)
 
 #define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
 #define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
@@ -71,9 +71,9 @@
 
 /* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
 
-#define S3C2410_TCNTB(tmr)    S3C2410_TIMERREG2(tmr, 0x00)
-#define S3C2410_TCMPB(tmr)    S3C2410_TIMERREG2(tmr, 0x04)
-#define S3C2410_TCNTO(tmr)    S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
+#define S3C2410_TCNTB(tmr)    S3C_TIMERREG2(tmr, 0x00)
+#define S3C2410_TCMPB(tmr)    S3C_TIMERREG2(tmr, 0x04)
+#define S3C2410_TCNTO(tmr)    S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
 
 #define S3C2410_TCON_T4RELOAD     (1<<22)
 #define S3C2410_TCON_T4MANUALUPD  (1<<21)
diff --git a/include/asm-arm/arch-s3c2410/regs-watchdog.h b/include/asm-arm/plat-s3c/regs-watchdog.h
index a9c5d491bdb6..56c4193b7a46 100644
--- a/include/asm-arm/arch-s3c2410/regs-watchdog.h
+++ b/include/asm-arm/plat-s3c/regs-watchdog.h
@@ -14,11 +14,11 @@
 #ifndef __ASM_ARCH_REGS_WATCHDOG_H
 #define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"
 
-#define S3C2410_WDOGREG(x) ((x) + S3C24XX_VA_WATCHDOG)
+#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
 
-#define S3C2410_WTCON      S3C2410_WDOGREG(0x00)
-#define S3C2410_WTDAT      S3C2410_WDOGREG(0x04)
-#define S3C2410_WTCNT      S3C2410_WDOGREG(0x08)
+#define S3C2410_WTCON      S3C_WDOGREG(0x00)
+#define S3C2410_WTDAT      S3C_WDOGREG(0x04)
+#define S3C2410_WTCNT      S3C_WDOGREG(0x08)
 
 /* the watchdog can either generate a reset pulse, or an
  * interrupt.
diff --git a/include/asm-arm/plat-s3c/uncompress.h b/include/asm-arm/plat-s3c/uncompress.h
new file mode 100644
index 000000000000..b5e6208175d1
--- /dev/null
+++ b/include/asm-arm/plat-s3c/uncompress.h
@@ -0,0 +1,155 @@
+/* linux/include/asm-arm/plat-s3c/uncompress.h
+ *
+ * Copyright 2003, 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - uncompress code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_UNCOMPRESS_H
+#define __ASM_PLAT_UNCOMPRESS_H
+
+typedef unsigned int upf_t;     /* cannot include linux/serial_core.h */
+
+/* uart setup */
+
+static unsigned int fifo_mask;
+static unsigned int fifo_max;
+
+/* forward declerations */
+
+static void arch_detect_cpu(void);
+
+/* defines for UART registers */
+
+#include "asm/plat-s3c/regs-serial.h"
+#include "asm/plat-s3c/regs-watchdog.h"
+
+/* working in physical space... */
+#undef S3C2410_WDOGREG
+#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
+
+/* how many bytes we allow into the FIFO at a time in FIFO mode */
+#define FIFO_MAX         (14)
+
+#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
+
+static __inline__ void
+uart_wr(unsigned int reg, unsigned int val)
+{
+        volatile unsigned int *ptr;
+
+        ptr = (volatile unsigned int *)(reg + uart_base);
+        *ptr = val;
+}
+
+static __inline__ unsigned int
+uart_rd(unsigned int reg)
+{
+        volatile unsigned int *ptr;
+
+        ptr = (volatile unsigned int *)(reg + uart_base);
+        return *ptr;
+}
+
+/* we can deal with the case the UARTs are being run
+ * in FIFO mode, so that we don't hold up our execution
+ * waiting for tx to happen...
+*/
+
+static void putc(int ch)
+{
+        if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
+                int level;
+
+                while (1) {
+                        level = uart_rd(S3C2410_UFSTAT);
+                        level &= fifo_mask;
+
+                        if (level < fifo_max)
+                                break;
+                }
+
+        } else {
+                /* not using fifos */
+
+                while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
+                        barrier();
+        }
+
+        /* write byte to transmission register */
+        uart_wr(S3C2410_UTXH, ch);
+}
+
+static inline void flush(void)
+{
+}
+
+#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
+
+/* CONFIG_S3C_BOOT_WATCHDOG
+ *
+ * Simple boot-time watchdog setup, to reboot the system if there is
+ * any problem with the boot process
+*/
+
+#ifdef CONFIG_S3C_BOOT_WATCHDOG
+
+#define WDOG_COUNT (0xff00)
+
+static inline void arch_decomp_wdog(void)
+{
+        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
+}
+
+static void arch_decomp_wdog_start(void)
+{
+        __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
+        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
+}
+
+#else
+#define arch_decomp_wdog_start()
+#define arch_decomp_wdog()
+#endif
+
+#ifdef CONFIG_S3C_BOOT_ERROR_RESET
+
+static void arch_decomp_error(const char *x)
+{
+        putstr("\n\n");
+        putstr(x);
+        putstr("\n\n -- System resetting\n");
+
+        __raw_writel(0x4000, S3C2410_WTDAT);
+        __raw_writel(0x4000, S3C2410_WTCNT);
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
+
+        while(1);
+}
+
+#define arch_error arch_decomp_error
+#endif
+
+static void error(char *err);
+
+static void
+arch_decomp_setup(void)
+{
+        /* we may need to setup the uart(s) here if we are not running
+         * on an BAST... the BAST will have left the uarts configured
+         * after calling linux.
+         */
+
+        arch_detect_cpu();
+        arch_decomp_wdog_start();
+}
+
+
+#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/plat-s3c24xx/regs-iis.h
index eaf77916a602..eaf77916a602 100644
--- a/include/asm-arm/arch-s3c2410/regs-iis.h
+++ b/include/asm-arm/plat-s3c24xx/regs-iis.h
diff --git a/include/asm-arm/arch-s3c2410/regs-spi.h b/include/asm-arm/plat-s3c24xx/regs-spi.h
index 4a499a138256..4a499a138256 100644
--- a/include/asm-arm/arch-s3c2410/regs-spi.h
+++ b/include/asm-arm/plat-s3c24xx/regs-spi.h
diff --git a/include/asm-arm/arch-s3c2410/regs-udc.h b/include/asm-arm/plat-s3c24xx/regs-udc.h
index e1e9805d2d9a..e1e9805d2d9a 100644
--- a/include/asm-arm/arch-s3c2410/regs-udc.h
+++ b/include/asm-arm/plat-s3c24xx/regs-udc.h
diff --git a/include/asm-arm/arch-s3c2410/udc.h b/include/asm-arm/plat-s3c24xx/udc.h
index b8aa6cb69b58..b8aa6cb69b58 100644
--- a/include/asm-arm/arch-s3c2410/udc.h
+++ b/include/asm-arm/plat-s3c24xx/udc.h
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index eae85b09db2e..69c65d56a6ac 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -24,7 +24,6 @@
 struct task_struct;
 struct exec_domain;
 
-#include <asm/ptrace.h>
 #include <asm/types.h>
 #include <asm/domain.h>
 
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index bfdbebebdc1b..d327b25c986c 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -441,7 +441,6 @@
 /*
  * Unimplemented (or alternatively implemented) syscalls
  */
-#define __IGNORE_sync_file_range        1
 #define __IGNORE_fadvise64_64           1
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-arm/vfp.h b/include/asm-arm/vfp.h
index 14c5e0946c47..bd6be9d7f772 100644
--- a/include/asm-arm/vfp.h
+++ b/include/asm-arm/vfp.h
@@ -26,8 +26,8 @@
 #define FPSID_REV_MASK          (0xF  << FPSID_REV_BIT)
 
 /* FPEXC bits */
-#define FPEXC_EXCEPTION         (1<<31)
-#define FPEXC_ENABLE            (1<<30)
+#define FPEXC_EX                (1 << 31)
+#define FPEXC_EN                (1 << 30)
 
 /* FPSCR bits */
 #define FPSCR_DEFAULT_NAN       (1<<25)