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-rw-r--r--drivers/gpu/drm/radeon/radeon_cursor.c28
1 files changed, 12 insertions, 16 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
index 5731fc9b1ae3..3eef567b0421 100644
--- a/drivers/gpu/drm/radeon/radeon_cursor.c
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
@@ -203,6 +203,7 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
203 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 203 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
204 struct radeon_device *rdev = crtc->dev->dev_private; 204 struct radeon_device *rdev = crtc->dev->dev_private;
205 int xorigin = 0, yorigin = 0; 205 int xorigin = 0, yorigin = 0;
206 int w = radeon_crtc->cursor_width;
206 207
207 if (x < 0) 208 if (x < 0)
208 xorigin = -x + 1; 209 xorigin = -x + 1;
@@ -213,22 +214,7 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
213 if (yorigin >= CURSOR_HEIGHT) 214 if (yorigin >= CURSOR_HEIGHT)
214 yorigin = CURSOR_HEIGHT - 1; 215 yorigin = CURSOR_HEIGHT - 1;
215 216
216 radeon_lock_cursor(crtc, true); 217 if (ASIC_IS_AVIVO(rdev)) {
217 if (ASIC_IS_DCE4(rdev)) {
218 /* cursors are offset into the total surface */
219 x += crtc->x;
220 y += crtc->y;
221 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
222
223 /* XXX: check if evergreen has the same issues as avivo chips */
224 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset,
225 ((xorigin ? 0 : x) << 16) |
226 (yorigin ? 0 : y));
227 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
228 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
229 ((radeon_crtc->cursor_width - 1) << 16) | (radeon_crtc->cursor_height - 1));
230 } else if (ASIC_IS_AVIVO(rdev)) {
231 int w = radeon_crtc->cursor_width;
232 int i = 0; 218 int i = 0;
233 struct drm_crtc *crtc_p; 219 struct drm_crtc *crtc_p;
234 220
@@ -260,7 +246,17 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
260 if (w <= 0) 246 if (w <= 0)
261 w = 1; 247 w = 1;
262 } 248 }
249 }
263 250
251 radeon_lock_cursor(crtc, true);
252 if (ASIC_IS_DCE4(rdev)) {
253 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset,
254 ((xorigin ? 0 : x) << 16) |
255 (yorigin ? 0 : y));
256 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
257 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
258 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
259 } else if (ASIC_IS_AVIVO(rdev)) {
264 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, 260 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
265 ((xorigin ? 0 : x) << 16) | 261 ((xorigin ? 0 : x) << 16) |
266 (yorigin ? 0 : y)); 262 (yorigin ? 0 : y));