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-rw-r--r--drivers/net/tg3.c23
1 files changed, 12 insertions, 11 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 25f85fb9df46..fee0e6e5ff1e 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -9284,8 +9284,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
9284 static struct pci_device_id write_reorder_chipsets[] = { 9284 static struct pci_device_id write_reorder_chipsets[] = {
9285 { PCI_DEVICE(PCI_VENDOR_ID_AMD, 9285 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
9286 PCI_DEVICE_ID_AMD_FE_GATE_700C) }, 9286 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
9287 { PCI_DEVICE(PCI_VENDOR_ID_AMD, 9287 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
9288 PCI_DEVICE_ID_AMD_K8_NB) }, 9288 PCI_DEVICE_ID_VIA_8385_0) },
9289 { }, 9289 { },
9290 }; 9290 };
9291 u32 misc_ctrl_reg; 9291 u32 misc_ctrl_reg;
@@ -9300,15 +9300,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
9300 tp->tg3_flags2 |= TG3_FLG2_SUN_570X; 9300 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
9301#endif 9301#endif
9302 9302
9303 /* If we have an AMD 762 or K8 chipset, write
9304 * reordering to the mailbox registers done by the host
9305 * controller can cause major troubles. We read back from
9306 * every mailbox register write to force the writes to be
9307 * posted to the chip in order.
9308 */
9309 if (pci_dev_present(write_reorder_chipsets))
9310 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
9311
9312 /* Force memory write invalidate off. If we leave it on, 9303 /* Force memory write invalidate off. If we leave it on,
9313 * then on 5700_BX chips we have to enable a workaround. 9304 * then on 5700_BX chips we have to enable a workaround.
9314 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary 9305 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
@@ -9439,6 +9430,16 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
9439 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0) 9430 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
9440 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; 9431 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
9441 9432
9433 /* If we have an AMD 762 or VIA K8T800 chipset, write
9434 * reordering to the mailbox registers done by the host
9435 * controller can cause major troubles. We read back from
9436 * every mailbox register write to force the writes to be
9437 * posted to the chip in order.
9438 */
9439 if (pci_dev_present(write_reorder_chipsets) &&
9440 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9441 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
9442
9442 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && 9443 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9443 tp->pci_lat_timer < 64) { 9444 tp->pci_lat_timer < 64) {
9444 tp->pci_lat_timer = 64; 9445 tp->pci_lat_timer = 64;