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-rw-r--r--arch/mips/Kconfig16
-rw-r--r--arch/mips/Makefile7
-rw-r--r--arch/mips/bcm63xx/Kconfig25
-rw-r--r--arch/mips/bcm63xx/Makefile7
-rw-r--r--arch/mips/bcm63xx/boards/Kconfig11
-rw-r--r--arch/mips/bcm63xx/boards/Makefile3
-rw-r--r--arch/mips/bcm63xx/boards/board_bcm963xx.c837
-rw-r--r--arch/mips/bcm63xx/clk.c226
-rw-r--r--arch/mips/bcm63xx/cpu.c345
-rw-r--r--arch/mips/bcm63xx/cs.c144
-rw-r--r--arch/mips/bcm63xx/dev-dsp.c56
-rw-r--r--arch/mips/bcm63xx/early_printk.c30
-rw-r--r--arch/mips/bcm63xx/gpio.c134
-rw-r--r--arch/mips/bcm63xx/irq.c253
-rw-r--r--arch/mips/bcm63xx/prom.c55
-rw-r--r--arch/mips/bcm63xx/setup.c125
-rw-r--r--arch/mips/bcm63xx/timer.c205
-rw-r--r--arch/mips/configs/bcm63xx_defconfig972
-rw-r--r--arch/mips/include/asm/fixmap.h4
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h12
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h11
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h538
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h10
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h13
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h45
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h6
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h22
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h93
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h15
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h773
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h11
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h60
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h51
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/gpio.h15
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/war.h25
-rw-r--r--arch/mips/pci/Makefile2
-rw-r--r--arch/mips/pci/fixup-bcm63xx.c21
-rw-r--r--arch/mips/pci/ops-bcm63xx.c467
-rw-r--r--arch/mips/pci/pci-bcm63xx.c224
-rw-r--r--arch/mips/pci/pci-bcm63xx.h27
40 files changed, 5896 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 224e548f0fc8..705a7a9170f3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -80,6 +80,21 @@ config BCM47XX
80 help 80 help
81 Support for BCM47XX based boards 81 Support for BCM47XX based boards
82 82
83config BCM63XX
84 bool "Broadcom BCM63XX based boards"
85 select CEVT_R4K
86 select CSRC_R4K
87 select DMA_NONCOHERENT
88 select IRQ_CPU
89 select SYS_HAS_CPU_MIPS32_R1
90 select SYS_SUPPORTS_32BIT_KERNEL
91 select SYS_SUPPORTS_BIG_ENDIAN
92 select SYS_HAS_EARLY_PRINTK
93 select SWAP_IO_SPACE
94 select ARCH_REQUIRE_GPIOLIB
95 help
96 Support for BCM63XX based boards
97
83config MIPS_COBALT 98config MIPS_COBALT
84 bool "Cobalt Server" 99 bool "Cobalt Server"
85 select CEVT_R4K 100 select CEVT_R4K
@@ -645,6 +660,7 @@ endchoice
645 660
646source "arch/mips/alchemy/Kconfig" 661source "arch/mips/alchemy/Kconfig"
647source "arch/mips/basler/excite/Kconfig" 662source "arch/mips/basler/excite/Kconfig"
663source "arch/mips/bcm63xx/Kconfig"
648source "arch/mips/jazz/Kconfig" 664source "arch/mips/jazz/Kconfig"
649source "arch/mips/lasat/Kconfig" 665source "arch/mips/lasat/Kconfig"
650source "arch/mips/pmc-sierra/Kconfig" 666source "arch/mips/pmc-sierra/Kconfig"
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 1efa9aa64880..c825b14b4ed0 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -565,6 +565,13 @@ cflags-$(CONFIG_BCM47XX) += -I$(srctree)/arch/mips/include/asm/mach-bcm47xx
565load-$(CONFIG_BCM47XX) := 0xffffffff80001000 565load-$(CONFIG_BCM47XX) := 0xffffffff80001000
566 566
567# 567#
568# Broadcom BCM63XX boards
569#
570core-$(CONFIG_BCM63XX) += arch/mips/bcm63xx/
571cflags-$(CONFIG_BCM63XX) += -I$(srctree)/arch/mips/include/asm/mach-bcm63xx/
572load-$(CONFIG_BCM63XX) := 0xffffffff80010000
573
574#
568# SNI RM 575# SNI RM
569# 576#
570core-$(CONFIG_SNI_RM) += arch/mips/sni/ 577core-$(CONFIG_SNI_RM) += arch/mips/sni/
diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
new file mode 100644
index 000000000000..fb177d6df066
--- /dev/null
+++ b/arch/mips/bcm63xx/Kconfig
@@ -0,0 +1,25 @@
1menu "CPU support"
2 depends on BCM63XX
3
4config BCM63XX_CPU_6338
5 bool "support 6338 CPU"
6 select HW_HAS_PCI
7 select USB_ARCH_HAS_OHCI
8 select USB_OHCI_BIG_ENDIAN_DESC
9 select USB_OHCI_BIG_ENDIAN_MMIO
10
11config BCM63XX_CPU_6345
12 bool "support 6345 CPU"
13 select USB_OHCI_BIG_ENDIAN_DESC
14 select USB_OHCI_BIG_ENDIAN_MMIO
15
16config BCM63XX_CPU_6348
17 bool "support 6348 CPU"
18 select HW_HAS_PCI
19
20config BCM63XX_CPU_6358
21 bool "support 6358 CPU"
22 select HW_HAS_PCI
23endmenu
24
25source "arch/mips/bcm63xx/boards/Kconfig"
diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
new file mode 100644
index 000000000000..99bbc8753a21
--- /dev/null
+++ b/arch/mips/bcm63xx/Makefile
@@ -0,0 +1,7 @@
1obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
2 dev-dsp.o
3obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
4
5obj-y += boards/
6
7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/bcm63xx/boards/Kconfig b/arch/mips/bcm63xx/boards/Kconfig
new file mode 100644
index 000000000000..c6aed33d893e
--- /dev/null
+++ b/arch/mips/bcm63xx/boards/Kconfig
@@ -0,0 +1,11 @@
1choice
2 prompt "Board support"
3 depends on BCM63XX
4 default BOARD_BCM963XX
5
6config BOARD_BCM963XX
7 bool "Generic Broadcom 963xx boards"
8 select SSB
9 help
10
11endchoice
diff --git a/arch/mips/bcm63xx/boards/Makefile b/arch/mips/bcm63xx/boards/Makefile
new file mode 100644
index 000000000000..e5cc86dc1da8
--- /dev/null
+++ b/arch/mips/bcm63xx/boards/Makefile
@@ -0,0 +1,3 @@
1obj-$(CONFIG_BOARD_BCM963XX) += board_bcm963xx.o
2
3EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
new file mode 100644
index 000000000000..fd77f548207a
--- /dev/null
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -0,0 +1,837 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
8 */
9
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/string.h>
13#include <linux/platform_device.h>
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/partitions.h>
16#include <linux/mtd/physmap.h>
17#include <linux/ssb/ssb.h>
18#include <asm/addrspace.h>
19#include <bcm63xx_board.h>
20#include <bcm63xx_cpu.h>
21#include <bcm63xx_regs.h>
22#include <bcm63xx_io.h>
23#include <bcm63xx_board.h>
24#include <bcm63xx_dev_pci.h>
25#include <bcm63xx_dev_enet.h>
26#include <bcm63xx_dev_dsp.h>
27#include <board_bcm963xx.h>
28
29#define PFX "board_bcm963xx: "
30
31static struct bcm963xx_nvram nvram;
32static unsigned int mac_addr_used;
33static struct board_info board;
34
35/*
36 * known 6338 boards
37 */
38#ifdef CONFIG_BCM63XX_CPU_6338
39static struct board_info __initdata board_96338gw = {
40 .name = "96338GW",
41 .expected_cpu_id = 0x6338,
42
43 .has_enet0 = 1,
44 .enet0 = {
45 .force_speed_100 = 1,
46 .force_duplex_full = 1,
47 },
48
49 .has_ohci0 = 1,
50
51 .leds = {
52 {
53 .name = "adsl",
54 .gpio = 3,
55 .active_low = 1,
56 },
57 {
58 .name = "ses",
59 .gpio = 5,
60 .active_low = 1,
61 },
62 {
63 .name = "ppp-fail",
64 .gpio = 4,
65 .active_low = 1,
66 },
67 {
68 .name = "power",
69 .gpio = 0,
70 .active_low = 1,
71 .default_trigger = "default-on",
72 },
73 {
74 .name = "stop",
75 .gpio = 1,
76 .active_low = 1,
77 }
78 },
79};
80
81static struct board_info __initdata board_96338w = {
82 .name = "96338W",
83 .expected_cpu_id = 0x6338,
84
85 .has_enet0 = 1,
86 .enet0 = {
87 .force_speed_100 = 1,
88 .force_duplex_full = 1,
89 },
90
91 .leds = {
92 {
93 .name = "adsl",
94 .gpio = 3,
95 .active_low = 1,
96 },
97 {
98 .name = "ses",
99 .gpio = 5,
100 .active_low = 1,
101 },
102 {
103 .name = "ppp-fail",
104 .gpio = 4,
105 .active_low = 1,
106 },
107 {
108 .name = "power",
109 .gpio = 0,
110 .active_low = 1,
111 .default_trigger = "default-on",
112 },
113 {
114 .name = "stop",
115 .gpio = 1,
116 .active_low = 1,
117 },
118 },
119};
120#endif
121
122/*
123 * known 6345 boards
124 */
125#ifdef CONFIG_BCM63XX_CPU_6345
126static struct board_info __initdata board_96345gw2 = {
127 .name = "96345GW2",
128 .expected_cpu_id = 0x6345,
129};
130#endif
131
132/*
133 * known 6348 boards
134 */
135#ifdef CONFIG_BCM63XX_CPU_6348
136static struct board_info __initdata board_96348r = {
137 .name = "96348R",
138 .expected_cpu_id = 0x6348,
139
140 .has_enet0 = 1,
141 .has_pci = 1,
142
143 .enet0 = {
144 .has_phy = 1,
145 .use_internal_phy = 1,
146 },
147
148 .leds = {
149 {
150 .name = "adsl-fail",
151 .gpio = 2,
152 .active_low = 1,
153 },
154 {
155 .name = "ppp",
156 .gpio = 3,
157 .active_low = 1,
158 },
159 {
160 .name = "ppp-fail",
161 .gpio = 4,
162 .active_low = 1,
163 },
164 {
165 .name = "power",
166 .gpio = 0,
167 .active_low = 1,
168 .default_trigger = "default-on",
169
170 },
171 {
172 .name = "stop",
173 .gpio = 1,
174 .active_low = 1,
175 },
176 },
177};
178
179static struct board_info __initdata board_96348gw_10 = {
180 .name = "96348GW-10",
181 .expected_cpu_id = 0x6348,
182
183 .has_enet0 = 1,
184 .has_enet1 = 1,
185 .has_pci = 1,
186
187 .enet0 = {
188 .has_phy = 1,
189 .use_internal_phy = 1,
190 },
191 .enet1 = {
192 .force_speed_100 = 1,
193 .force_duplex_full = 1,
194 },
195
196 .has_ohci0 = 1,
197 .has_pccard = 1,
198 .has_ehci0 = 1,
199
200 .has_dsp = 1,
201 .dsp = {
202 .gpio_rst = 6,
203 .gpio_int = 34,
204 .cs = 2,
205 .ext_irq = 2,
206 },
207
208 .leds = {
209 {
210 .name = "adsl-fail",
211 .gpio = 2,
212 .active_low = 1,
213 },
214 {
215 .name = "ppp",
216 .gpio = 3,
217 .active_low = 1,
218 },
219 {
220 .name = "ppp-fail",
221 .gpio = 4,
222 .active_low = 1,
223 },
224 {
225 .name = "power",
226 .gpio = 0,
227 .active_low = 1,
228 .default_trigger = "default-on",
229 },
230 {
231 .name = "stop",
232 .gpio = 1,
233 .active_low = 1,
234 },
235 },
236};
237
238static struct board_info __initdata board_96348gw_11 = {
239 .name = "96348GW-11",
240 .expected_cpu_id = 0x6348,
241
242 .has_enet0 = 1,
243 .has_enet1 = 1,
244 .has_pci = 1,
245
246 .enet0 = {
247 .has_phy = 1,
248 .use_internal_phy = 1,
249 },
250
251 .enet1 = {
252 .force_speed_100 = 1,
253 .force_duplex_full = 1,
254 },
255
256
257 .has_ohci0 = 1,
258 .has_pccard = 1,
259 .has_ehci0 = 1,
260
261 .leds = {
262 {
263 .name = "adsl-fail",
264 .gpio = 2,
265 .active_low = 1,
266 },
267 {
268 .name = "ppp",
269 .gpio = 3,
270 .active_low = 1,
271 },
272 {
273 .name = "ppp-fail",
274 .gpio = 4,
275 .active_low = 1,
276 },
277 {
278 .name = "power",
279 .gpio = 0,
280 .active_low = 1,
281 .default_trigger = "default-on",
282 },
283 {
284 .name = "stop",
285 .gpio = 1,
286 .active_low = 1,
287 },
288 },
289};
290
291static struct board_info __initdata board_96348gw = {
292 .name = "96348GW",
293 .expected_cpu_id = 0x6348,
294
295 .has_enet0 = 1,
296 .has_enet1 = 1,
297 .has_pci = 1,
298
299 .enet0 = {
300 .has_phy = 1,
301 .use_internal_phy = 1,
302 },
303 .enet1 = {
304 .force_speed_100 = 1,
305 .force_duplex_full = 1,
306 },
307
308 .has_ohci0 = 1,
309
310 .has_dsp = 1,
311 .dsp = {
312 .gpio_rst = 6,
313 .gpio_int = 34,
314 .ext_irq = 2,
315 .cs = 2,
316 },
317
318 .leds = {
319 {
320 .name = "adsl-fail",
321 .gpio = 2,
322 .active_low = 1,
323 },
324 {
325 .name = "ppp",
326 .gpio = 3,
327 .active_low = 1,
328 },
329 {
330 .name = "ppp-fail",
331 .gpio = 4,
332 .active_low = 1,
333 },
334 {
335 .name = "power",
336 .gpio = 0,
337 .active_low = 1,
338 .default_trigger = "default-on",
339 },
340 {
341 .name = "stop",
342 .gpio = 1,
343 .active_low = 1,
344 },
345 },
346};
347
348static struct board_info __initdata board_FAST2404 = {
349 .name = "F@ST2404",
350 .expected_cpu_id = 0x6348,
351
352 .has_enet0 = 1,
353 .has_enet1 = 1,
354 .has_pci = 1,
355
356 .enet0 = {
357 .has_phy = 1,
358 .use_internal_phy = 1,
359 },
360
361 .enet1 = {
362 .force_speed_100 = 1,
363 .force_duplex_full = 1,
364 },
365
366
367 .has_ohci0 = 1,
368 .has_pccard = 1,
369 .has_ehci0 = 1,
370};
371
372static struct board_info __initdata board_DV201AMR = {
373 .name = "DV201AMR",
374 .expected_cpu_id = 0x6348,
375
376 .has_pci = 1,
377 .has_ohci0 = 1,
378
379 .has_enet0 = 1,
380 .has_enet1 = 1,
381 .enet0 = {
382 .has_phy = 1,
383 .use_internal_phy = 1,
384 },
385 .enet1 = {
386 .force_speed_100 = 1,
387 .force_duplex_full = 1,
388 },
389};
390
391static struct board_info __initdata board_96348gw_a = {
392 .name = "96348GW-A",
393 .expected_cpu_id = 0x6348,
394
395 .has_enet0 = 1,
396 .has_enet1 = 1,
397 .has_pci = 1,
398
399 .enet0 = {
400 .has_phy = 1,
401 .use_internal_phy = 1,
402 },
403 .enet1 = {
404 .force_speed_100 = 1,
405 .force_duplex_full = 1,
406 },
407
408 .has_ohci0 = 1,
409};
410#endif
411
412/*
413 * known 6358 boards
414 */
415#ifdef CONFIG_BCM63XX_CPU_6358
416static struct board_info __initdata board_96358vw = {
417 .name = "96358VW",
418 .expected_cpu_id = 0x6358,
419
420 .has_enet0 = 1,
421 .has_enet1 = 1,
422 .has_pci = 1,
423
424 .enet0 = {
425 .has_phy = 1,
426 .use_internal_phy = 1,
427 },
428
429 .enet1 = {
430 .force_speed_100 = 1,
431 .force_duplex_full = 1,
432 },
433
434
435 .has_ohci0 = 1,
436 .has_pccard = 1,
437 .has_ehci0 = 1,
438
439 .leds = {
440 {
441 .name = "adsl-fail",
442 .gpio = 15,
443 .active_low = 1,
444 },
445 {
446 .name = "ppp",
447 .gpio = 22,
448 .active_low = 1,
449 },
450 {
451 .name = "ppp-fail",
452 .gpio = 23,
453 .active_low = 1,
454 },
455 {
456 .name = "power",
457 .gpio = 4,
458 .default_trigger = "default-on",
459 },
460 {
461 .name = "stop",
462 .gpio = 5,
463 },
464 },
465};
466
467static struct board_info __initdata board_96358vw2 = {
468 .name = "96358VW2",
469 .expected_cpu_id = 0x6358,
470
471 .has_enet0 = 1,
472 .has_enet1 = 1,
473 .has_pci = 1,
474
475 .enet0 = {
476 .has_phy = 1,
477 .use_internal_phy = 1,
478 },
479
480 .enet1 = {
481 .force_speed_100 = 1,
482 .force_duplex_full = 1,
483 },
484
485
486 .has_ohci0 = 1,
487 .has_pccard = 1,
488 .has_ehci0 = 1,
489
490 .leds = {
491 {
492 .name = "adsl",
493 .gpio = 22,
494 .active_low = 1,
495 },
496 {
497 .name = "ppp-fail",
498 .gpio = 23,
499 },
500 {
501 .name = "power",
502 .gpio = 5,
503 .active_low = 1,
504 .default_trigger = "default-on",
505 },
506 {
507 .name = "stop",
508 .gpio = 4,
509 .active_low = 1,
510 },
511 },
512};
513
514static struct board_info __initdata board_AGPFS0 = {
515 .name = "AGPF-S0",
516 .expected_cpu_id = 0x6358,
517
518 .has_enet0 = 1,
519 .has_enet1 = 1,
520 .has_pci = 1,
521
522 .enet0 = {
523 .has_phy = 1,
524 .use_internal_phy = 1,
525 },
526
527 .enet1 = {
528 .force_speed_100 = 1,
529 .force_duplex_full = 1,
530 },
531
532 .has_ohci0 = 1,
533 .has_ehci0 = 1,
534};
535#endif
536
537/*
538 * all boards
539 */
540static const struct board_info __initdata *bcm963xx_boards[] = {
541#ifdef CONFIG_BCM63XX_CPU_6338
542 &board_96338gw,
543 &board_96338w,
544#endif
545#ifdef CONFIG_BCM63XX_CPU_6345
546 &board_96345gw2,
547#endif
548#ifdef CONFIG_BCM63XX_CPU_6348
549 &board_96348r,
550 &board_96348gw,
551 &board_96348gw_10,
552 &board_96348gw_11,
553 &board_FAST2404,
554 &board_DV201AMR,
555 &board_96348gw_a,
556#endif
557
558#ifdef CONFIG_BCM63XX_CPU_6358
559 &board_96358vw,
560 &board_96358vw2,
561 &board_AGPFS0,
562#endif
563};
564
565/*
566 * early init callback, read nvram data from flash and checksum it
567 */
568void __init board_prom_init(void)
569{
570 unsigned int check_len, i;
571 u8 *boot_addr, *cfe, *p;
572 char cfe_version[32];
573 u32 val;
574
575 /* read base address of boot chip select (0)
576 * 6345 does not have MPI but boots from standard
577 * MIPS Flash address */
578 if (BCMCPU_IS_6345())
579 val = 0x1fc00000;
580 else {
581 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
582 val &= MPI_CSBASE_BASE_MASK;
583 }
584 boot_addr = (u8 *)KSEG1ADDR(val);
585
586 /* dump cfe version */
587 cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET;
588 if (!memcmp(cfe, "cfe-v", 5))
589 snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u",
590 cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]);
591 else
592 strcpy(cfe_version, "unknown");
593 printk(KERN_INFO PFX "CFE version: %s\n", cfe_version);
594
595 /* extract nvram data */
596 memcpy(&nvram, boot_addr + BCM963XX_NVRAM_OFFSET, sizeof(nvram));
597
598 /* check checksum before using data */
599 if (nvram.version <= 4)
600 check_len = offsetof(struct bcm963xx_nvram, checksum_old);
601 else
602 check_len = sizeof(nvram);
603 val = 0;
604 p = (u8 *)&nvram;
605 while (check_len--)
606 val += *p;
607 if (val) {
608 printk(KERN_ERR PFX "invalid nvram checksum\n");
609 return;
610 }
611
612 /* find board by name */
613 for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) {
614 if (strncmp(nvram.name, bcm963xx_boards[i]->name,
615 sizeof(nvram.name)))
616 continue;
617 /* copy, board desc array is marked initdata */
618 memcpy(&board, bcm963xx_boards[i], sizeof(board));
619 break;
620 }
621
622 /* bail out if board is not found, will complain later */
623 if (!board.name[0]) {
624 char name[17];
625 memcpy(name, nvram.name, 16);
626 name[16] = 0;
627 printk(KERN_ERR PFX "unknown bcm963xx board: %s\n",
628 name);
629 return;
630 }
631
632 /* setup pin multiplexing depending on board enabled device,
633 * this has to be done this early since PCI init is done
634 * inside arch_initcall */
635 val = 0;
636
637#ifdef CONFIG_PCI
638 if (board.has_pci) {
639 bcm63xx_pci_enabled = 1;
640 if (BCMCPU_IS_6348())
641 val |= GPIO_MODE_6348_G2_PCI;
642 }
643#endif
644
645 if (board.has_pccard) {
646 if (BCMCPU_IS_6348())
647 val |= GPIO_MODE_6348_G1_MII_PCCARD;
648 }
649
650 if (board.has_enet0 && !board.enet0.use_internal_phy) {
651 if (BCMCPU_IS_6348())
652 val |= GPIO_MODE_6348_G3_EXT_MII |
653 GPIO_MODE_6348_G0_EXT_MII;
654 }
655
656 if (board.has_enet1 && !board.enet1.use_internal_phy) {
657 if (BCMCPU_IS_6348())
658 val |= GPIO_MODE_6348_G3_EXT_MII |
659 GPIO_MODE_6348_G0_EXT_MII;
660 }
661
662 bcm_gpio_writel(val, GPIO_MODE_REG);
663}
664
665/*
666 * second stage init callback, good time to panic if we couldn't
667 * identify on which board we're running since early printk is working
668 */
669void __init board_setup(void)
670{
671 if (!board.name[0])
672 panic("unable to detect bcm963xx board");
673 printk(KERN_INFO PFX "board name: %s\n", board.name);
674
675 /* make sure we're running on expected cpu */
676 if (bcm63xx_get_cpu_id() != board.expected_cpu_id)
677 panic("unexpected CPU for bcm963xx board");
678}
679
680/*
681 * return board name for /proc/cpuinfo
682 */
683const char *board_get_name(void)
684{
685 return board.name;
686}
687
688/*
689 * register & return a new board mac address
690 */
691static int board_get_mac_address(u8 *mac)
692{
693 u8 *p;
694 int count;
695
696 if (mac_addr_used >= nvram.mac_addr_count) {
697 printk(KERN_ERR PFX "not enough mac address\n");
698 return -ENODEV;
699 }
700
701 memcpy(mac, nvram.mac_addr_base, ETH_ALEN);
702 p = mac + ETH_ALEN - 1;
703 count = mac_addr_used;
704
705 while (count--) {
706 do {
707 (*p)++;
708 if (*p != 0)
709 break;
710 p--;
711 } while (p != mac);
712 }
713
714 if (p == mac) {
715 printk(KERN_ERR PFX "unable to fetch mac address\n");
716 return -ENODEV;
717 }
718
719 mac_addr_used++;
720 return 0;
721}
722
723static struct mtd_partition mtd_partitions[] = {
724 {
725 .name = "cfe",
726 .offset = 0x0,
727 .size = 0x40000,
728 }
729};
730
731static struct physmap_flash_data flash_data = {
732 .width = 2,
733 .nr_parts = ARRAY_SIZE(mtd_partitions),
734 .parts = mtd_partitions,
735};
736
737static struct resource mtd_resources[] = {
738 {
739 .start = 0, /* filled at runtime */
740 .end = 0, /* filled at runtime */
741 .flags = IORESOURCE_MEM,
742 }
743};
744
745static struct platform_device mtd_dev = {
746 .name = "physmap-flash",
747 .resource = mtd_resources,
748 .num_resources = ARRAY_SIZE(mtd_resources),
749 .dev = {
750 .platform_data = &flash_data,
751 },
752};
753
754/*
755 * Register a sane SPROMv2 to make the on-board
756 * bcm4318 WLAN work
757 */
758#ifdef CONFIG_SSB_PCIHOST
759static struct ssb_sprom bcm63xx_sprom = {
760 .revision = 0x02,
761 .board_rev = 0x17,
762 .country_code = 0x0,
763 .ant_available_bg = 0x3,
764 .pa0b0 = 0x15ae,
765 .pa0b1 = 0xfa85,
766 .pa0b2 = 0xfe8d,
767 .pa1b0 = 0xffff,
768 .pa1b1 = 0xffff,
769 .pa1b2 = 0xffff,
770 .gpio0 = 0xff,
771 .gpio1 = 0xff,
772 .gpio2 = 0xff,
773 .gpio3 = 0xff,
774 .maxpwr_bg = 0x004c,
775 .itssi_bg = 0x00,
776 .boardflags_lo = 0x2848,
777 .boardflags_hi = 0x0000,
778};
779#endif
780
781static struct gpio_led_platform_data bcm63xx_led_data;
782
783static struct platform_device bcm63xx_gpio_leds = {
784 .name = "leds-gpio",
785 .id = 0,
786 .dev.platform_data = &bcm63xx_led_data,
787};
788
789/*
790 * third stage init callback, register all board devices.
791 */
792int __init board_register_devices(void)
793{
794 u32 val;
795
796 if (board.has_enet0 &&
797 !board_get_mac_address(board.enet0.mac_addr))
798 bcm63xx_enet_register(0, &board.enet0);
799
800 if (board.has_enet1 &&
801 !board_get_mac_address(board.enet1.mac_addr))
802 bcm63xx_enet_register(1, &board.enet1);
803
804 if (board.has_dsp)
805 bcm63xx_dsp_register(&board.dsp);
806
807 /* Generate MAC address for WLAN and
808 * register our SPROM */
809#ifdef CONFIG_SSB_PCIHOST
810 if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
811 memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
812 memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
813 if (ssb_arch_set_fallback_sprom(&bcm63xx_sprom) < 0)
814 printk(KERN_ERR "failed to register fallback SPROM\n");
815 }
816#endif
817
818 /* read base address of boot chip select (0) */
819 if (BCMCPU_IS_6345())
820 val = 0x1fc00000;
821 else {
822 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
823 val &= MPI_CSBASE_BASE_MASK;
824 }
825 mtd_resources[0].start = val;
826 mtd_resources[0].end = 0x1FFFFFFF;
827
828 platform_device_register(&mtd_dev);
829
830 bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds);
831 bcm63xx_led_data.leds = board.leds;
832
833 platform_device_register(&bcm63xx_gpio_leds);
834
835 return 0;
836}
837
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
new file mode 100644
index 000000000000..2c68ee9ccee2
--- /dev/null
+++ b/arch/mips/bcm63xx/clk.c
@@ -0,0 +1,226 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/module.h>
10#include <linux/mutex.h>
11#include <linux/err.h>
12#include <linux/clk.h>
13#include <bcm63xx_cpu.h>
14#include <bcm63xx_io.h>
15#include <bcm63xx_regs.h>
16#include <bcm63xx_clk.h>
17
18static DEFINE_MUTEX(clocks_mutex);
19
20
21static void clk_enable_unlocked(struct clk *clk)
22{
23 if (clk->set && (clk->usage++) == 0)
24 clk->set(clk, 1);
25}
26
27static void clk_disable_unlocked(struct clk *clk)
28{
29 if (clk->set && (--clk->usage) == 0)
30 clk->set(clk, 0);
31}
32
33static void bcm_hwclock_set(u32 mask, int enable)
34{
35 u32 reg;
36
37 reg = bcm_perf_readl(PERF_CKCTL_REG);
38 if (enable)
39 reg |= mask;
40 else
41 reg &= ~mask;
42 bcm_perf_writel(reg, PERF_CKCTL_REG);
43}
44
45/*
46 * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
47 */
48static void enet_misc_set(struct clk *clk, int enable)
49{
50 u32 mask;
51
52 if (BCMCPU_IS_6338())
53 mask = CKCTL_6338_ENET_EN;
54 else if (BCMCPU_IS_6345())
55 mask = CKCTL_6345_ENET_EN;
56 else if (BCMCPU_IS_6348())
57 mask = CKCTL_6348_ENET_EN;
58 else
59 /* BCMCPU_IS_6358 */
60 mask = CKCTL_6358_EMUSB_EN;
61 bcm_hwclock_set(mask, enable);
62}
63
64static struct clk clk_enet_misc = {
65 .set = enet_misc_set,
66};
67
68/*
69 * Ethernet MAC clocks: only revelant on 6358, silently enable misc
70 * clocks
71 */
72static void enetx_set(struct clk *clk, int enable)
73{
74 if (enable)
75 clk_enable_unlocked(&clk_enet_misc);
76 else
77 clk_disable_unlocked(&clk_enet_misc);
78
79 if (BCMCPU_IS_6358()) {
80 u32 mask;
81
82 if (clk->id == 0)
83 mask = CKCTL_6358_ENET0_EN;
84 else
85 mask = CKCTL_6358_ENET1_EN;
86 bcm_hwclock_set(mask, enable);
87 }
88}
89
90static struct clk clk_enet0 = {
91 .id = 0,
92 .set = enetx_set,
93};
94
95static struct clk clk_enet1 = {
96 .id = 1,
97 .set = enetx_set,
98};
99
100/*
101 * Ethernet PHY clock
102 */
103static void ephy_set(struct clk *clk, int enable)
104{
105 if (!BCMCPU_IS_6358())
106 return;
107 bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
108}
109
110
111static struct clk clk_ephy = {
112 .set = ephy_set,
113};
114
115/*
116 * PCM clock
117 */
118static void pcm_set(struct clk *clk, int enable)
119{
120 if (!BCMCPU_IS_6358())
121 return;
122 bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
123}
124
125static struct clk clk_pcm = {
126 .set = pcm_set,
127};
128
129/*
130 * USB host clock
131 */
132static void usbh_set(struct clk *clk, int enable)
133{
134 if (!BCMCPU_IS_6348())
135 return;
136 bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
137}
138
139static struct clk clk_usbh = {
140 .set = usbh_set,
141};
142
143/*
144 * SPI clock
145 */
146static void spi_set(struct clk *clk, int enable)
147{
148 u32 mask;
149
150 if (BCMCPU_IS_6338())
151 mask = CKCTL_6338_SPI_EN;
152 else if (BCMCPU_IS_6348())
153 mask = CKCTL_6348_SPI_EN;
154 else
155 /* BCMCPU_IS_6358 */
156 mask = CKCTL_6358_SPI_EN;
157 bcm_hwclock_set(mask, enable);
158}
159
160static struct clk clk_spi = {
161 .set = spi_set,
162};
163
164/*
165 * Internal peripheral clock
166 */
167static struct clk clk_periph = {
168 .rate = (50 * 1000 * 1000),
169};
170
171
172/*
173 * Linux clock API implementation
174 */
175int clk_enable(struct clk *clk)
176{
177 mutex_lock(&clocks_mutex);
178 clk_enable_unlocked(clk);
179 mutex_unlock(&clocks_mutex);
180 return 0;
181}
182
183EXPORT_SYMBOL(clk_enable);
184
185void clk_disable(struct clk *clk)
186{
187 mutex_lock(&clocks_mutex);
188 clk_disable_unlocked(clk);
189 mutex_unlock(&clocks_mutex);
190}
191
192EXPORT_SYMBOL(clk_disable);
193
194unsigned long clk_get_rate(struct clk *clk)
195{
196 return clk->rate;
197}
198
199EXPORT_SYMBOL(clk_get_rate);
200
201struct clk *clk_get(struct device *dev, const char *id)
202{
203 if (!strcmp(id, "enet0"))
204 return &clk_enet0;
205 if (!strcmp(id, "enet1"))
206 return &clk_enet1;
207 if (!strcmp(id, "ephy"))
208 return &clk_ephy;
209 if (!strcmp(id, "usbh"))
210 return &clk_usbh;
211 if (!strcmp(id, "spi"))
212 return &clk_spi;
213 if (!strcmp(id, "periph"))
214 return &clk_periph;
215 if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
216 return &clk_pcm;
217 return ERR_PTR(-ENOENT);
218}
219
220EXPORT_SYMBOL(clk_get);
221
222void clk_put(struct clk *clk)
223{
224}
225
226EXPORT_SYMBOL(clk_put);
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
new file mode 100644
index 000000000000..6dc43f0483e8
--- /dev/null
+++ b/arch/mips/bcm63xx/cpu.c
@@ -0,0 +1,345 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/cpu.h>
13#include <bcm63xx_cpu.h>
14#include <bcm63xx_regs.h>
15#include <bcm63xx_io.h>
16#include <bcm63xx_irq.h>
17
18const unsigned long *bcm63xx_regs_base;
19EXPORT_SYMBOL(bcm63xx_regs_base);
20
21const int *bcm63xx_irqs;
22EXPORT_SYMBOL(bcm63xx_irqs);
23
24static u16 bcm63xx_cpu_id;
25static u16 bcm63xx_cpu_rev;
26static unsigned int bcm63xx_cpu_freq;
27static unsigned int bcm63xx_memory_size;
28
29/*
30 * 6338 register sets and irqs
31 */
32static const unsigned long bcm96338_regs_base[] = {
33 [RSET_DSL_LMEM] = BCM_6338_DSL_LMEM_BASE,
34 [RSET_PERF] = BCM_6338_PERF_BASE,
35 [RSET_TIMER] = BCM_6338_TIMER_BASE,
36 [RSET_WDT] = BCM_6338_WDT_BASE,
37 [RSET_UART0] = BCM_6338_UART0_BASE,
38 [RSET_GPIO] = BCM_6338_GPIO_BASE,
39 [RSET_SPI] = BCM_6338_SPI_BASE,
40 [RSET_OHCI0] = BCM_6338_OHCI0_BASE,
41 [RSET_OHCI_PRIV] = BCM_6338_OHCI_PRIV_BASE,
42 [RSET_USBH_PRIV] = BCM_6338_USBH_PRIV_BASE,
43 [RSET_UDC0] = BCM_6338_UDC0_BASE,
44 [RSET_MPI] = BCM_6338_MPI_BASE,
45 [RSET_PCMCIA] = BCM_6338_PCMCIA_BASE,
46 [RSET_SDRAM] = BCM_6338_SDRAM_BASE,
47 [RSET_DSL] = BCM_6338_DSL_BASE,
48 [RSET_ENET0] = BCM_6338_ENET0_BASE,
49 [RSET_ENET1] = BCM_6338_ENET1_BASE,
50 [RSET_ENETDMA] = BCM_6338_ENETDMA_BASE,
51 [RSET_MEMC] = BCM_6338_MEMC_BASE,
52 [RSET_DDR] = BCM_6338_DDR_BASE,
53};
54
55static const int bcm96338_irqs[] = {
56 [IRQ_TIMER] = BCM_6338_TIMER_IRQ,
57 [IRQ_UART0] = BCM_6338_UART0_IRQ,
58 [IRQ_DSL] = BCM_6338_DSL_IRQ,
59 [IRQ_ENET0] = BCM_6338_ENET0_IRQ,
60 [IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ,
61 [IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ,
62 [IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ,
63};
64
65/*
66 * 6345 register sets and irqs
67 */
68static const unsigned long bcm96345_regs_base[] = {
69 [RSET_DSL_LMEM] = BCM_6345_DSL_LMEM_BASE,
70 [RSET_PERF] = BCM_6345_PERF_BASE,
71 [RSET_TIMER] = BCM_6345_TIMER_BASE,
72 [RSET_WDT] = BCM_6345_WDT_BASE,
73 [RSET_UART0] = BCM_6345_UART0_BASE,
74 [RSET_GPIO] = BCM_6345_GPIO_BASE,
75 [RSET_SPI] = BCM_6345_SPI_BASE,
76 [RSET_UDC0] = BCM_6345_UDC0_BASE,
77 [RSET_OHCI0] = BCM_6345_OHCI0_BASE,
78 [RSET_OHCI_PRIV] = BCM_6345_OHCI_PRIV_BASE,
79 [RSET_USBH_PRIV] = BCM_6345_USBH_PRIV_BASE,
80 [RSET_MPI] = BCM_6345_MPI_BASE,
81 [RSET_PCMCIA] = BCM_6345_PCMCIA_BASE,
82 [RSET_DSL] = BCM_6345_DSL_BASE,
83 [RSET_ENET0] = BCM_6345_ENET0_BASE,
84 [RSET_ENET1] = BCM_6345_ENET1_BASE,
85 [RSET_ENETDMA] = BCM_6345_ENETDMA_BASE,
86 [RSET_EHCI0] = BCM_6345_EHCI0_BASE,
87 [RSET_SDRAM] = BCM_6345_SDRAM_BASE,
88 [RSET_MEMC] = BCM_6345_MEMC_BASE,
89 [RSET_DDR] = BCM_6345_DDR_BASE,
90};
91
92static const int bcm96345_irqs[] = {
93 [IRQ_TIMER] = BCM_6345_TIMER_IRQ,
94 [IRQ_UART0] = BCM_6345_UART0_IRQ,
95 [IRQ_DSL] = BCM_6345_DSL_IRQ,
96 [IRQ_ENET0] = BCM_6345_ENET0_IRQ,
97 [IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ,
98 [IRQ_ENET0_RXDMA] = BCM_6345_ENET0_RXDMA_IRQ,
99 [IRQ_ENET0_TXDMA] = BCM_6345_ENET0_TXDMA_IRQ,
100};
101
102/*
103 * 6348 register sets and irqs
104 */
105static const unsigned long bcm96348_regs_base[] = {
106 [RSET_DSL_LMEM] = BCM_6348_DSL_LMEM_BASE,
107 [RSET_PERF] = BCM_6348_PERF_BASE,
108 [RSET_TIMER] = BCM_6348_TIMER_BASE,
109 [RSET_WDT] = BCM_6348_WDT_BASE,
110 [RSET_UART0] = BCM_6348_UART0_BASE,
111 [RSET_GPIO] = BCM_6348_GPIO_BASE,
112 [RSET_SPI] = BCM_6348_SPI_BASE,
113 [RSET_OHCI0] = BCM_6348_OHCI0_BASE,
114 [RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE,
115 [RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE,
116 [RSET_MPI] = BCM_6348_MPI_BASE,
117 [RSET_PCMCIA] = BCM_6348_PCMCIA_BASE,
118 [RSET_SDRAM] = BCM_6348_SDRAM_BASE,
119 [RSET_DSL] = BCM_6348_DSL_BASE,
120 [RSET_ENET0] = BCM_6348_ENET0_BASE,
121 [RSET_ENET1] = BCM_6348_ENET1_BASE,
122 [RSET_ENETDMA] = BCM_6348_ENETDMA_BASE,
123 [RSET_MEMC] = BCM_6348_MEMC_BASE,
124 [RSET_DDR] = BCM_6348_DDR_BASE,
125};
126
127static const int bcm96348_irqs[] = {
128 [IRQ_TIMER] = BCM_6348_TIMER_IRQ,
129 [IRQ_UART0] = BCM_6348_UART0_IRQ,
130 [IRQ_DSL] = BCM_6348_DSL_IRQ,
131 [IRQ_ENET0] = BCM_6348_ENET0_IRQ,
132 [IRQ_ENET1] = BCM_6348_ENET1_IRQ,
133 [IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ,
134 [IRQ_OHCI0] = BCM_6348_OHCI0_IRQ,
135 [IRQ_PCMCIA] = BCM_6348_PCMCIA_IRQ,
136 [IRQ_ENET0_RXDMA] = BCM_6348_ENET0_RXDMA_IRQ,
137 [IRQ_ENET0_TXDMA] = BCM_6348_ENET0_TXDMA_IRQ,
138 [IRQ_ENET1_RXDMA] = BCM_6348_ENET1_RXDMA_IRQ,
139 [IRQ_ENET1_TXDMA] = BCM_6348_ENET1_TXDMA_IRQ,
140 [IRQ_PCI] = BCM_6348_PCI_IRQ,
141};
142
143/*
144 * 6358 register sets and irqs
145 */
146static const unsigned long bcm96358_regs_base[] = {
147 [RSET_DSL_LMEM] = BCM_6358_DSL_LMEM_BASE,
148 [RSET_PERF] = BCM_6358_PERF_BASE,
149 [RSET_TIMER] = BCM_6358_TIMER_BASE,
150 [RSET_WDT] = BCM_6358_WDT_BASE,
151 [RSET_UART0] = BCM_6358_UART0_BASE,
152 [RSET_GPIO] = BCM_6358_GPIO_BASE,
153 [RSET_SPI] = BCM_6358_SPI_BASE,
154 [RSET_OHCI0] = BCM_6358_OHCI0_BASE,
155 [RSET_EHCI0] = BCM_6358_EHCI0_BASE,
156 [RSET_OHCI_PRIV] = BCM_6358_OHCI_PRIV_BASE,
157 [RSET_USBH_PRIV] = BCM_6358_USBH_PRIV_BASE,
158 [RSET_MPI] = BCM_6358_MPI_BASE,
159 [RSET_PCMCIA] = BCM_6358_PCMCIA_BASE,
160 [RSET_SDRAM] = BCM_6358_SDRAM_BASE,
161 [RSET_DSL] = BCM_6358_DSL_BASE,
162 [RSET_ENET0] = BCM_6358_ENET0_BASE,
163 [RSET_ENET1] = BCM_6358_ENET1_BASE,
164 [RSET_ENETDMA] = BCM_6358_ENETDMA_BASE,
165 [RSET_MEMC] = BCM_6358_MEMC_BASE,
166 [RSET_DDR] = BCM_6358_DDR_BASE,
167};
168
169static const int bcm96358_irqs[] = {
170 [IRQ_TIMER] = BCM_6358_TIMER_IRQ,
171 [IRQ_UART0] = BCM_6358_UART0_IRQ,
172 [IRQ_DSL] = BCM_6358_DSL_IRQ,
173 [IRQ_ENET0] = BCM_6358_ENET0_IRQ,
174 [IRQ_ENET1] = BCM_6358_ENET1_IRQ,
175 [IRQ_ENET_PHY] = BCM_6358_ENET_PHY_IRQ,
176 [IRQ_OHCI0] = BCM_6358_OHCI0_IRQ,
177 [IRQ_EHCI0] = BCM_6358_EHCI0_IRQ,
178 [IRQ_PCMCIA] = BCM_6358_PCMCIA_IRQ,
179 [IRQ_ENET0_RXDMA] = BCM_6358_ENET0_RXDMA_IRQ,
180 [IRQ_ENET0_TXDMA] = BCM_6358_ENET0_TXDMA_IRQ,
181 [IRQ_ENET1_RXDMA] = BCM_6358_ENET1_RXDMA_IRQ,
182 [IRQ_ENET1_TXDMA] = BCM_6358_ENET1_TXDMA_IRQ,
183 [IRQ_PCI] = BCM_6358_PCI_IRQ,
184};
185
186u16 __bcm63xx_get_cpu_id(void)
187{
188 return bcm63xx_cpu_id;
189}
190
191EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
192
193u16 bcm63xx_get_cpu_rev(void)
194{
195 return bcm63xx_cpu_rev;
196}
197
198EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
199
200unsigned int bcm63xx_get_cpu_freq(void)
201{
202 return bcm63xx_cpu_freq;
203}
204
205unsigned int bcm63xx_get_memory_size(void)
206{
207 return bcm63xx_memory_size;
208}
209
210static unsigned int detect_cpu_clock(void)
211{
212 unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
213
214 /* BCM6338 has a fixed 240 Mhz frequency */
215 if (BCMCPU_IS_6338())
216 return 240000000;
217
218 /* BCM6345 has a fixed 140Mhz frequency */
219 if (BCMCPU_IS_6345())
220 return 140000000;
221
222 /*
223 * frequency depends on PLL configuration:
224 */
225 if (BCMCPU_IS_6348()) {
226 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
227 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
228 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
229 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
230 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
231 n1 += 1;
232 n2 += 2;
233 m1 += 1;
234 }
235
236 if (BCMCPU_IS_6358()) {
237 /* 16MHz * N1 * N2 / M1_CPU */
238 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
239 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
240 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
241 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
242 }
243
244 return (16 * 1000000 * n1 * n2) / m1;
245}
246
247/*
248 * attempt to detect the amount of memory installed
249 */
250static unsigned int detect_memory_size(void)
251{
252 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
253 u32 val;
254
255 if (BCMCPU_IS_6345())
256 return (8 * 1024 * 1024);
257
258 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
259 val = bcm_sdram_readl(SDRAM_CFG_REG);
260 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
261 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
262 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
263 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
264 }
265
266 if (BCMCPU_IS_6358()) {
267 val = bcm_memc_readl(MEMC_CFG_REG);
268 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
269 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
270 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
271 banks = 2;
272 }
273
274 /* 0 => 11 address bits ... 2 => 13 address bits */
275 rows += 11;
276
277 /* 0 => 8 address bits ... 2 => 10 address bits */
278 cols += 8;
279
280 return 1 << (cols + rows + (is_32bits + 1) + banks);
281}
282
283void __init bcm63xx_cpu_init(void)
284{
285 unsigned int tmp, expected_cpu_id;
286 struct cpuinfo_mips *c = &current_cpu_data;
287
288 /* soc registers location depends on cpu type */
289 expected_cpu_id = 0;
290
291 switch (c->cputype) {
292 /*
293 * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c
294 */
295 case CPU_BCM3302:
296 expected_cpu_id = BCM6338_CPU_ID;
297 bcm63xx_regs_base = bcm96338_regs_base;
298 bcm63xx_irqs = bcm96338_irqs;
299 break;
300 case CPU_BCM6345:
301 expected_cpu_id = BCM6345_CPU_ID;
302 bcm63xx_regs_base = bcm96345_regs_base;
303 bcm63xx_irqs = bcm96345_irqs;
304 break;
305 case CPU_BCM6348:
306 expected_cpu_id = BCM6348_CPU_ID;
307 bcm63xx_regs_base = bcm96348_regs_base;
308 bcm63xx_irqs = bcm96348_irqs;
309 break;
310 case CPU_BCM6358:
311 expected_cpu_id = BCM6358_CPU_ID;
312 bcm63xx_regs_base = bcm96358_regs_base;
313 bcm63xx_irqs = bcm96358_irqs;
314 break;
315 }
316
317 /*
318 * really early to panic, but delaying panic would not help since we
319 * will never get any working console
320 */
321 if (!expected_cpu_id)
322 panic("unsupported Broadcom CPU");
323
324 /*
325 * bcm63xx_regs_base is set, we can access soc registers
326 */
327
328 /* double check CPU type */
329 tmp = bcm_perf_readl(PERF_REV_REG);
330 bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
331 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
332
333 if (bcm63xx_cpu_id != expected_cpu_id)
334 panic("bcm63xx CPU id mismatch");
335
336 bcm63xx_cpu_freq = detect_cpu_clock();
337 bcm63xx_memory_size = detect_memory_size();
338
339 printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
340 bcm63xx_cpu_id, bcm63xx_cpu_rev);
341 printk(KERN_INFO "CPU frequency is %u MHz\n",
342 bcm63xx_cpu_freq / 1000000);
343 printk(KERN_INFO "%uMB of RAM installed\n",
344 bcm63xx_memory_size >> 20);
345}
diff --git a/arch/mips/bcm63xx/cs.c b/arch/mips/bcm63xx/cs.c
new file mode 100644
index 000000000000..50d8190bbf7b
--- /dev/null
+++ b/arch/mips/bcm63xx/cs.c
@@ -0,0 +1,144 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/spinlock.h>
12#include <linux/log2.h>
13#include <bcm63xx_cpu.h>
14#include <bcm63xx_io.h>
15#include <bcm63xx_regs.h>
16#include <bcm63xx_cs.h>
17
18static DEFINE_SPINLOCK(bcm63xx_cs_lock);
19
20/*
21 * check if given chip select exists
22 */
23static int is_valid_cs(unsigned int cs)
24{
25 if (cs > 6)
26 return 0;
27 return 1;
28}
29
30/*
31 * Configure chipselect base address and size (bytes).
32 * Size must be a power of two between 8k and 256M.
33 */
34int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size)
35{
36 unsigned long flags;
37 u32 val;
38
39 if (!is_valid_cs(cs))
40 return -EINVAL;
41
42 /* sanity check on size */
43 if (size != roundup_pow_of_two(size))
44 return -EINVAL;
45
46 if (size < 8 * 1024 || size > 256 * 1024 * 1024)
47 return -EINVAL;
48
49 val = (base & MPI_CSBASE_BASE_MASK);
50 /* 8k => 0 - 256M => 15 */
51 val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT;
52
53 spin_lock_irqsave(&bcm63xx_cs_lock, flags);
54 bcm_mpi_writel(val, MPI_CSBASE_REG(cs));
55 spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
56
57 return 0;
58}
59
60EXPORT_SYMBOL(bcm63xx_set_cs_base);
61
62/*
63 * configure chipselect timing (ns)
64 */
65int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
66 unsigned int setup, unsigned int hold)
67{
68 unsigned long flags;
69 u32 val;
70
71 if (!is_valid_cs(cs))
72 return -EINVAL;
73
74 spin_lock_irqsave(&bcm63xx_cs_lock, flags);
75 val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
76 val &= ~(MPI_CSCTL_WAIT_MASK);
77 val &= ~(MPI_CSCTL_SETUP_MASK);
78 val &= ~(MPI_CSCTL_HOLD_MASK);
79 val |= wait << MPI_CSCTL_WAIT_SHIFT;
80 val |= setup << MPI_CSCTL_SETUP_SHIFT;
81 val |= hold << MPI_CSCTL_HOLD_SHIFT;
82 bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
83 spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
84
85 return 0;
86}
87
88EXPORT_SYMBOL(bcm63xx_set_cs_timing);
89
90/*
91 * configure other chipselect parameter (data bus size, ...)
92 */
93int bcm63xx_set_cs_param(unsigned int cs, u32 params)
94{
95 unsigned long flags;
96 u32 val;
97
98 if (!is_valid_cs(cs))
99 return -EINVAL;
100
101 /* none of this fields apply to pcmcia */
102 if (cs == MPI_CS_PCMCIA_COMMON ||
103 cs == MPI_CS_PCMCIA_ATTR ||
104 cs == MPI_CS_PCMCIA_IO)
105 return -EINVAL;
106
107 spin_lock_irqsave(&bcm63xx_cs_lock, flags);
108 val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
109 val &= ~(MPI_CSCTL_DATA16_MASK);
110 val &= ~(MPI_CSCTL_SYNCMODE_MASK);
111 val &= ~(MPI_CSCTL_TSIZE_MASK);
112 val &= ~(MPI_CSCTL_ENDIANSWAP_MASK);
113 val |= params;
114 bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
115 spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
116
117 return 0;
118}
119
120EXPORT_SYMBOL(bcm63xx_set_cs_param);
121
122/*
123 * set cs status (enable/disable)
124 */
125int bcm63xx_set_cs_status(unsigned int cs, int enable)
126{
127 unsigned long flags;
128 u32 val;
129
130 if (!is_valid_cs(cs))
131 return -EINVAL;
132
133 spin_lock_irqsave(&bcm63xx_cs_lock, flags);
134 val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
135 if (enable)
136 val |= MPI_CSCTL_ENABLE_MASK;
137 else
138 val &= ~MPI_CSCTL_ENABLE_MASK;
139 bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
140 spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
141 return 0;
142}
143
144EXPORT_SYMBOL(bcm63xx_set_cs_status);
diff --git a/arch/mips/bcm63xx/dev-dsp.c b/arch/mips/bcm63xx/dev-dsp.c
new file mode 100644
index 000000000000..da46d1d3c77c
--- /dev/null
+++ b/arch/mips/bcm63xx/dev-dsp.c
@@ -0,0 +1,56 @@
1/*
2 * Broadcom BCM63xx VoIP DSP registration
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
9 */
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/platform_device.h>
14
15#include <bcm63xx_cpu.h>
16#include <bcm63xx_dev_dsp.h>
17#include <bcm63xx_regs.h>
18#include <bcm63xx_io.h>
19
20static struct resource voip_dsp_resources[] = {
21 {
22 .start = -1, /* filled at runtime */
23 .end = -1, /* filled at runtime */
24 .flags = IORESOURCE_MEM,
25 },
26 {
27 .start = -1, /* filled at runtime */
28 .flags = IORESOURCE_IRQ,
29 },
30};
31
32static struct platform_device bcm63xx_voip_dsp_device = {
33 .name = "bcm63xx-voip-dsp",
34 .id = 0,
35 .num_resources = ARRAY_SIZE(voip_dsp_resources),
36 .resource = voip_dsp_resources,
37};
38
39int __init bcm63xx_dsp_register(const struct bcm63xx_dsp_platform_data *pd)
40{
41 struct bcm63xx_dsp_platform_data *dpd;
42 u32 val;
43
44 /* Get the memory window */
45 val = bcm_mpi_readl(MPI_CSBASE_REG(pd->cs - 1));
46 val &= MPI_CSBASE_BASE_MASK;
47 voip_dsp_resources[0].start = val;
48 voip_dsp_resources[0].end = val + 0xFFFFFFF;
49 voip_dsp_resources[1].start = pd->ext_irq;
50
51 /* copy given platform data */
52 dpd = bcm63xx_voip_dsp_device.dev.platform_data;
53 memcpy(dpd, pd, sizeof (*pd));
54
55 return platform_device_register(&bcm63xx_voip_dsp_device);
56}
diff --git a/arch/mips/bcm63xx/early_printk.c b/arch/mips/bcm63xx/early_printk.c
new file mode 100644
index 000000000000..bf353c937df2
--- /dev/null
+++ b/arch/mips/bcm63xx/early_printk.c
@@ -0,0 +1,30 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/init.h>
10#include <bcm63xx_io.h>
11#include <bcm63xx_regs.h>
12
13static void __init wait_xfered(void)
14{
15 unsigned int val;
16
17 /* wait for any previous char to be transmitted */
18 do {
19 val = bcm_uart0_readl(UART_IR_REG);
20 if (val & UART_IR_STAT(UART_IR_TXEMPTY))
21 break;
22 } while (1);
23}
24
25void __init prom_putchar(char c)
26{
27 wait_xfered();
28 bcm_uart0_writel(c, UART_FIFO_REG);
29 wait_xfered();
30}
diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c
new file mode 100644
index 000000000000..87ca39046334
--- /dev/null
+++ b/arch/mips/bcm63xx/gpio.c
@@ -0,0 +1,134 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/spinlock.h>
13#include <linux/platform_device.h>
14#include <linux/gpio.h>
15
16#include <bcm63xx_cpu.h>
17#include <bcm63xx_gpio.h>
18#include <bcm63xx_io.h>
19#include <bcm63xx_regs.h>
20
21static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
22static u32 gpio_out_low, gpio_out_high;
23
24static void bcm63xx_gpio_set(struct gpio_chip *chip,
25 unsigned gpio, int val)
26{
27 u32 reg;
28 u32 mask;
29 u32 *v;
30 unsigned long flags;
31
32 if (gpio >= chip->ngpio)
33 BUG();
34
35 if (gpio < 32) {
36 reg = GPIO_DATA_LO_REG;
37 mask = 1 << gpio;
38 v = &gpio_out_low;
39 } else {
40 reg = GPIO_DATA_HI_REG;
41 mask = 1 << (gpio - 32);
42 v = &gpio_out_high;
43 }
44
45 spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
46 if (val)
47 *v |= mask;
48 else
49 *v &= ~mask;
50 bcm_gpio_writel(*v, reg);
51 spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
52}
53
54static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio)
55{
56 u32 reg;
57 u32 mask;
58
59 if (gpio >= chip->ngpio)
60 BUG();
61
62 if (gpio < 32) {
63 reg = GPIO_DATA_LO_REG;
64 mask = 1 << gpio;
65 } else {
66 reg = GPIO_DATA_HI_REG;
67 mask = 1 << (gpio - 32);
68 }
69
70 return !!(bcm_gpio_readl(reg) & mask);
71}
72
73static int bcm63xx_gpio_set_direction(struct gpio_chip *chip,
74 unsigned gpio, int dir)
75{
76 u32 reg;
77 u32 mask;
78 u32 tmp;
79 unsigned long flags;
80
81 if (gpio >= chip->ngpio)
82 BUG();
83
84 if (gpio < 32) {
85 reg = GPIO_CTL_LO_REG;
86 mask = 1 << gpio;
87 } else {
88 reg = GPIO_CTL_HI_REG;
89 mask = 1 << (gpio - 32);
90 }
91
92 spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
93 tmp = bcm_gpio_readl(reg);
94 if (dir == GPIO_DIR_IN)
95 tmp &= ~mask;
96 else
97 tmp |= mask;
98 bcm_gpio_writel(tmp, reg);
99 spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
100
101 return 0;
102}
103
104static int bcm63xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
105{
106 return bcm63xx_gpio_set_direction(chip, gpio, GPIO_DIR_IN);
107}
108
109static int bcm63xx_gpio_direction_output(struct gpio_chip *chip,
110 unsigned gpio, int value)
111{
112 bcm63xx_gpio_set(chip, gpio, value);
113 return bcm63xx_gpio_set_direction(chip, gpio, GPIO_DIR_OUT);
114}
115
116
117static struct gpio_chip bcm63xx_gpio_chip = {
118 .label = "bcm63xx-gpio",
119 .direction_input = bcm63xx_gpio_direction_input,
120 .direction_output = bcm63xx_gpio_direction_output,
121 .get = bcm63xx_gpio_get,
122 .set = bcm63xx_gpio_set,
123 .base = 0,
124};
125
126int __init bcm63xx_gpio_init(void)
127{
128 bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count();
129 pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio);
130
131 return gpiochip_add(&bcm63xx_gpio_chip);
132}
133
134arch_initcall(bcm63xx_gpio_init);
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
new file mode 100644
index 000000000000..a0c5cd18c192
--- /dev/null
+++ b/arch/mips/bcm63xx/irq.c
@@ -0,0 +1,253 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
8 */
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/module.h>
14#include <asm/irq_cpu.h>
15#include <asm/mipsregs.h>
16#include <bcm63xx_cpu.h>
17#include <bcm63xx_regs.h>
18#include <bcm63xx_io.h>
19#include <bcm63xx_irq.h>
20
21/*
22 * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
23 * prioritize any interrupt relatively to another. the static counter
24 * will resume the loop where it ended the last time we left this
25 * function.
26 */
27static void bcm63xx_irq_dispatch_internal(void)
28{
29 u32 pending;
30 static int i;
31
32 pending = bcm_perf_readl(PERF_IRQMASK_REG) &
33 bcm_perf_readl(PERF_IRQSTAT_REG);
34
35 if (!pending)
36 return ;
37
38 while (1) {
39 int to_call = i;
40
41 i = (i + 1) & 0x1f;
42 if (pending & (1 << to_call)) {
43 do_IRQ(to_call + IRQ_INTERNAL_BASE);
44 break;
45 }
46 }
47}
48
49asmlinkage void plat_irq_dispatch(void)
50{
51 u32 cause;
52
53 do {
54 cause = read_c0_cause() & read_c0_status() & ST0_IM;
55
56 if (!cause)
57 break;
58
59 if (cause & CAUSEF_IP7)
60 do_IRQ(7);
61 if (cause & CAUSEF_IP2)
62 bcm63xx_irq_dispatch_internal();
63 if (cause & CAUSEF_IP3)
64 do_IRQ(IRQ_EXT_0);
65 if (cause & CAUSEF_IP4)
66 do_IRQ(IRQ_EXT_1);
67 if (cause & CAUSEF_IP5)
68 do_IRQ(IRQ_EXT_2);
69 if (cause & CAUSEF_IP6)
70 do_IRQ(IRQ_EXT_3);
71 } while (1);
72}
73
74/*
75 * internal IRQs operations: only mask/unmask on PERF irq mask
76 * register.
77 */
78static inline void bcm63xx_internal_irq_mask(unsigned int irq)
79{
80 u32 mask;
81
82 irq -= IRQ_INTERNAL_BASE;
83 mask = bcm_perf_readl(PERF_IRQMASK_REG);
84 mask &= ~(1 << irq);
85 bcm_perf_writel(mask, PERF_IRQMASK_REG);
86}
87
88static void bcm63xx_internal_irq_unmask(unsigned int irq)
89{
90 u32 mask;
91
92 irq -= IRQ_INTERNAL_BASE;
93 mask = bcm_perf_readl(PERF_IRQMASK_REG);
94 mask |= (1 << irq);
95 bcm_perf_writel(mask, PERF_IRQMASK_REG);
96}
97
98static unsigned int bcm63xx_internal_irq_startup(unsigned int irq)
99{
100 bcm63xx_internal_irq_unmask(irq);
101 return 0;
102}
103
104/*
105 * external IRQs operations: mask/unmask and clear on PERF external
106 * irq control register.
107 */
108static void bcm63xx_external_irq_mask(unsigned int irq)
109{
110 u32 reg;
111
112 irq -= IRQ_EXT_BASE;
113 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
114 reg &= ~EXTIRQ_CFG_MASK(irq);
115 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
116}
117
118static void bcm63xx_external_irq_unmask(unsigned int irq)
119{
120 u32 reg;
121
122 irq -= IRQ_EXT_BASE;
123 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
124 reg |= EXTIRQ_CFG_MASK(irq);
125 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
126}
127
128static void bcm63xx_external_irq_clear(unsigned int irq)
129{
130 u32 reg;
131
132 irq -= IRQ_EXT_BASE;
133 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
134 reg |= EXTIRQ_CFG_CLEAR(irq);
135 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
136}
137
138static unsigned int bcm63xx_external_irq_startup(unsigned int irq)
139{
140 set_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
141 irq_enable_hazard();
142 bcm63xx_external_irq_unmask(irq);
143 return 0;
144}
145
146static void bcm63xx_external_irq_shutdown(unsigned int irq)
147{
148 bcm63xx_external_irq_mask(irq);
149 clear_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
150 irq_disable_hazard();
151}
152
153static int bcm63xx_external_irq_set_type(unsigned int irq,
154 unsigned int flow_type)
155{
156 u32 reg;
157 struct irq_desc *desc = irq_desc + irq;
158
159 irq -= IRQ_EXT_BASE;
160
161 flow_type &= IRQ_TYPE_SENSE_MASK;
162
163 if (flow_type == IRQ_TYPE_NONE)
164 flow_type = IRQ_TYPE_LEVEL_LOW;
165
166 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
167 switch (flow_type) {
168 case IRQ_TYPE_EDGE_BOTH:
169 reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
170 reg |= EXTIRQ_CFG_BOTHEDGE(irq);
171 break;
172
173 case IRQ_TYPE_EDGE_RISING:
174 reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
175 reg |= EXTIRQ_CFG_SENSE(irq);
176 reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
177 break;
178
179 case IRQ_TYPE_EDGE_FALLING:
180 reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
181 reg &= ~EXTIRQ_CFG_SENSE(irq);
182 reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
183 break;
184
185 case IRQ_TYPE_LEVEL_HIGH:
186 reg |= EXTIRQ_CFG_LEVELSENSE(irq);
187 reg |= EXTIRQ_CFG_SENSE(irq);
188 break;
189
190 case IRQ_TYPE_LEVEL_LOW:
191 reg |= EXTIRQ_CFG_LEVELSENSE(irq);
192 reg &= ~EXTIRQ_CFG_SENSE(irq);
193 break;
194
195 default:
196 printk(KERN_ERR "bogus flow type combination given !\n");
197 return -EINVAL;
198 }
199 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
200
201 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
202 desc->status |= IRQ_LEVEL;
203 desc->handle_irq = handle_level_irq;
204 } else {
205 desc->handle_irq = handle_edge_irq;
206 }
207
208 return 0;
209}
210
211static struct irq_chip bcm63xx_internal_irq_chip = {
212 .name = "bcm63xx_ipic",
213 .startup = bcm63xx_internal_irq_startup,
214 .shutdown = bcm63xx_internal_irq_mask,
215
216 .mask = bcm63xx_internal_irq_mask,
217 .mask_ack = bcm63xx_internal_irq_mask,
218 .unmask = bcm63xx_internal_irq_unmask,
219};
220
221static struct irq_chip bcm63xx_external_irq_chip = {
222 .name = "bcm63xx_epic",
223 .startup = bcm63xx_external_irq_startup,
224 .shutdown = bcm63xx_external_irq_shutdown,
225
226 .ack = bcm63xx_external_irq_clear,
227
228 .mask = bcm63xx_external_irq_mask,
229 .unmask = bcm63xx_external_irq_unmask,
230
231 .set_type = bcm63xx_external_irq_set_type,
232};
233
234static struct irqaction cpu_ip2_cascade_action = {
235 .handler = no_action,
236 .name = "cascade_ip2",
237};
238
239void __init arch_init_irq(void)
240{
241 int i;
242
243 mips_cpu_irq_init();
244 for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
245 set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip,
246 handle_level_irq);
247
248 for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
249 set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip,
250 handle_edge_irq);
251
252 setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
253}
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
new file mode 100644
index 000000000000..fb284fbc5853
--- /dev/null
+++ b/arch/mips/bcm63xx/prom.c
@@ -0,0 +1,55 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/init.h>
10#include <linux/bootmem.h>
11#include <asm/bootinfo.h>
12#include <bcm63xx_board.h>
13#include <bcm63xx_cpu.h>
14#include <bcm63xx_io.h>
15#include <bcm63xx_regs.h>
16#include <bcm63xx_gpio.h>
17
18void __init prom_init(void)
19{
20 u32 reg, mask;
21
22 bcm63xx_cpu_init();
23
24 /* stop any running watchdog */
25 bcm_wdt_writel(WDT_STOP_1, WDT_CTL_REG);
26 bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
27
28 /* disable all hardware blocks clock for now */
29 if (BCMCPU_IS_6338())
30 mask = CKCTL_6338_ALL_SAFE_EN;
31 else if (BCMCPU_IS_6345())
32 mask = CKCTL_6345_ALL_SAFE_EN;
33 else if (BCMCPU_IS_6348())
34 mask = CKCTL_6348_ALL_SAFE_EN;
35 else
36 /* BCMCPU_IS_6358() */
37 mask = CKCTL_6358_ALL_SAFE_EN;
38
39 reg = bcm_perf_readl(PERF_CKCTL_REG);
40 reg &= ~mask;
41 bcm_perf_writel(reg, PERF_CKCTL_REG);
42
43 /* assign command line from kernel config */
44 strcpy(arcs_cmdline, CONFIG_CMDLINE);
45
46 /* register gpiochip */
47 bcm63xx_gpio_init();
48
49 /* do low level board init */
50 board_prom_init();
51}
52
53void __init prom_free_prom_memory(void)
54{
55}
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
new file mode 100644
index 000000000000..b18a0ca926fa
--- /dev/null
+++ b/arch/mips/bcm63xx/setup.c
@@ -0,0 +1,125 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/bootmem.h>
13#include <linux/ioport.h>
14#include <linux/pm.h>
15#include <asm/bootinfo.h>
16#include <asm/time.h>
17#include <asm/reboot.h>
18#include <asm/cacheflush.h>
19#include <bcm63xx_board.h>
20#include <bcm63xx_cpu.h>
21#include <bcm63xx_regs.h>
22#include <bcm63xx_io.h>
23
24void bcm63xx_machine_halt(void)
25{
26 printk(KERN_INFO "System halted\n");
27 while (1)
28 ;
29}
30
31static void bcm6348_a1_reboot(void)
32{
33 u32 reg;
34
35 /* soft reset all blocks */
36 printk(KERN_INFO "soft-reseting all blocks ...\n");
37 reg = bcm_perf_readl(PERF_SOFTRESET_REG);
38 reg &= ~SOFTRESET_6348_ALL;
39 bcm_perf_writel(reg, PERF_SOFTRESET_REG);
40 mdelay(10);
41
42 reg = bcm_perf_readl(PERF_SOFTRESET_REG);
43 reg |= SOFTRESET_6348_ALL;
44 bcm_perf_writel(reg, PERF_SOFTRESET_REG);
45 mdelay(10);
46
47 /* Jump to the power on address. */
48 printk(KERN_INFO "jumping to reset vector.\n");
49 /* set high vectors (base at 0xbfc00000 */
50 set_c0_status(ST0_BEV | ST0_ERL);
51 /* run uncached in kseg0 */
52 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
53 __flush_cache_all();
54 /* remove all wired TLB entries */
55 write_c0_wired(0);
56 __asm__ __volatile__(
57 "jr\t%0"
58 :
59 : "r" (0xbfc00000));
60 while (1)
61 ;
62}
63
64void bcm63xx_machine_reboot(void)
65{
66 u32 reg;
67
68 /* mask and clear all external irq */
69 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
70 reg &= ~EXTIRQ_CFG_MASK_ALL;
71 reg |= EXTIRQ_CFG_CLEAR_ALL;
72 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
73
74 if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
75 bcm6348_a1_reboot();
76
77 printk(KERN_INFO "triggering watchdog soft-reset...\n");
78 bcm_perf_writel(SYS_PLL_SOFT_RESET, PERF_SYS_PLL_CTL_REG);
79 while (1)
80 ;
81}
82
83static void __bcm63xx_machine_reboot(char *p)
84{
85 bcm63xx_machine_reboot();
86}
87
88/*
89 * return system type in /proc/cpuinfo
90 */
91const char *get_system_type(void)
92{
93 static char buf[128];
94 snprintf(buf, sizeof(buf), "bcm63xx/%s (0x%04x/0x%04X)",
95 board_get_name(),
96 bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev());
97 return buf;
98}
99
100void __init plat_time_init(void)
101{
102 mips_hpt_frequency = bcm63xx_get_cpu_freq() / 2;
103}
104
105void __init plat_mem_setup(void)
106{
107 add_memory_region(0, bcm63xx_get_memory_size(), BOOT_MEM_RAM);
108
109 _machine_halt = bcm63xx_machine_halt;
110 _machine_restart = __bcm63xx_machine_reboot;
111 pm_power_off = bcm63xx_machine_halt;
112
113 set_io_port_base(0);
114 ioport_resource.start = 0;
115 ioport_resource.end = ~0;
116
117 board_setup();
118}
119
120int __init bcm63xx_register_devices(void)
121{
122 return board_register_devices();
123}
124
125arch_initcall(bcm63xx_register_devices);
diff --git a/arch/mips/bcm63xx/timer.c b/arch/mips/bcm63xx/timer.c
new file mode 100644
index 000000000000..ba522bdcde4b
--- /dev/null
+++ b/arch/mips/bcm63xx/timer.c
@@ -0,0 +1,205 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/kernel.h>
10#include <linux/err.h>
11#include <linux/module.h>
12#include <linux/spinlock.h>
13#include <linux/interrupt.h>
14#include <linux/clk.h>
15#include <bcm63xx_cpu.h>
16#include <bcm63xx_io.h>
17#include <bcm63xx_timer.h>
18#include <bcm63xx_regs.h>
19
20static DEFINE_SPINLOCK(timer_reg_lock);
21static DEFINE_SPINLOCK(timer_data_lock);
22static struct clk *periph_clk;
23
24static struct timer_data {
25 void (*cb)(void *);
26 void *data;
27} timer_data[BCM63XX_TIMER_COUNT];
28
29static irqreturn_t timer_interrupt(int irq, void *dev_id)
30{
31 u32 stat;
32 int i;
33
34 spin_lock(&timer_reg_lock);
35 stat = bcm_timer_readl(TIMER_IRQSTAT_REG);
36 bcm_timer_writel(stat, TIMER_IRQSTAT_REG);
37 spin_unlock(&timer_reg_lock);
38
39 for (i = 0; i < BCM63XX_TIMER_COUNT; i++) {
40 if (!(stat & TIMER_IRQSTAT_TIMER_CAUSE(i)))
41 continue;
42
43 spin_lock(&timer_data_lock);
44 if (!timer_data[i].cb) {
45 spin_unlock(&timer_data_lock);
46 continue;
47 }
48
49 timer_data[i].cb(timer_data[i].data);
50 spin_unlock(&timer_data_lock);
51 }
52
53 return IRQ_HANDLED;
54}
55
56int bcm63xx_timer_enable(int id)
57{
58 u32 reg;
59 unsigned long flags;
60
61 if (id >= BCM63XX_TIMER_COUNT)
62 return -EINVAL;
63
64 spin_lock_irqsave(&timer_reg_lock, flags);
65
66 reg = bcm_timer_readl(TIMER_CTLx_REG(id));
67 reg |= TIMER_CTL_ENABLE_MASK;
68 bcm_timer_writel(reg, TIMER_CTLx_REG(id));
69
70 reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
71 reg |= TIMER_IRQSTAT_TIMER_IR_EN(id);
72 bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
73
74 spin_unlock_irqrestore(&timer_reg_lock, flags);
75 return 0;
76}
77
78EXPORT_SYMBOL(bcm63xx_timer_enable);
79
80int bcm63xx_timer_disable(int id)
81{
82 u32 reg;
83 unsigned long flags;
84
85 if (id >= BCM63XX_TIMER_COUNT)
86 return -EINVAL;
87
88 spin_lock_irqsave(&timer_reg_lock, flags);
89
90 reg = bcm_timer_readl(TIMER_CTLx_REG(id));
91 reg &= ~TIMER_CTL_ENABLE_MASK;
92 bcm_timer_writel(reg, TIMER_CTLx_REG(id));
93
94 reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
95 reg &= ~TIMER_IRQSTAT_TIMER_IR_EN(id);
96 bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
97
98 spin_unlock_irqrestore(&timer_reg_lock, flags);
99 return 0;
100}
101
102EXPORT_SYMBOL(bcm63xx_timer_disable);
103
104int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data)
105{
106 unsigned long flags;
107 int ret;
108
109 if (id >= BCM63XX_TIMER_COUNT || !callback)
110 return -EINVAL;
111
112 ret = 0;
113 spin_lock_irqsave(&timer_data_lock, flags);
114 if (timer_data[id].cb) {
115 ret = -EBUSY;
116 goto out;
117 }
118
119 timer_data[id].cb = callback;
120 timer_data[id].data = data;
121
122out:
123 spin_unlock_irqrestore(&timer_data_lock, flags);
124 return ret;
125}
126
127EXPORT_SYMBOL(bcm63xx_timer_register);
128
129void bcm63xx_timer_unregister(int id)
130{
131 unsigned long flags;
132
133 if (id >= BCM63XX_TIMER_COUNT)
134 return;
135
136 spin_lock_irqsave(&timer_data_lock, flags);
137 timer_data[id].cb = NULL;
138 spin_unlock_irqrestore(&timer_data_lock, flags);
139}
140
141EXPORT_SYMBOL(bcm63xx_timer_unregister);
142
143unsigned int bcm63xx_timer_countdown(unsigned int countdown_us)
144{
145 return (clk_get_rate(periph_clk) / (1000 * 1000)) * countdown_us;
146}
147
148EXPORT_SYMBOL(bcm63xx_timer_countdown);
149
150int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us)
151{
152 u32 reg, countdown;
153 unsigned long flags;
154
155 if (id >= BCM63XX_TIMER_COUNT)
156 return -EINVAL;
157
158 countdown = bcm63xx_timer_countdown(countdown_us);
159 if (countdown & ~TIMER_CTL_COUNTDOWN_MASK)
160 return -EINVAL;
161
162 spin_lock_irqsave(&timer_reg_lock, flags);
163 reg = bcm_timer_readl(TIMER_CTLx_REG(id));
164
165 if (monotonic)
166 reg &= ~TIMER_CTL_MONOTONIC_MASK;
167 else
168 reg |= TIMER_CTL_MONOTONIC_MASK;
169
170 reg &= ~TIMER_CTL_COUNTDOWN_MASK;
171 reg |= countdown;
172 bcm_timer_writel(reg, TIMER_CTLx_REG(id));
173
174 spin_unlock_irqrestore(&timer_reg_lock, flags);
175 return 0;
176}
177
178EXPORT_SYMBOL(bcm63xx_timer_set);
179
180int bcm63xx_timer_init(void)
181{
182 int ret, irq;
183 u32 reg;
184
185 reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
186 reg &= ~TIMER_IRQSTAT_TIMER0_IR_EN;
187 reg &= ~TIMER_IRQSTAT_TIMER1_IR_EN;
188 reg &= ~TIMER_IRQSTAT_TIMER2_IR_EN;
189 bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
190
191 periph_clk = clk_get(NULL, "periph");
192 if (IS_ERR(periph_clk))
193 return -ENODEV;
194
195 irq = bcm63xx_get_irq_number(IRQ_TIMER);
196 ret = request_irq(irq, timer_interrupt, 0, "bcm63xx_timer", NULL);
197 if (ret) {
198 printk(KERN_ERR "bcm63xx_timer: failed to register irq\n");
199 return ret;
200 }
201
202 return 0;
203}
204
205arch_initcall(bcm63xx_timer_init);
diff --git a/arch/mips/configs/bcm63xx_defconfig b/arch/mips/configs/bcm63xx_defconfig
new file mode 100644
index 000000000000..ea00c18d1f7b
--- /dev/null
+++ b/arch/mips/configs/bcm63xx_defconfig
@@ -0,0 +1,972 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.30-rc6
4# Sun May 31 20:17:18 2009
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set
14CONFIG_BCM63XX=y
15# CONFIG_MIPS_COBALT is not set
16# CONFIG_MACH_DECSTATION is not set
17# CONFIG_MACH_JAZZ is not set
18# CONFIG_LASAT is not set
19# CONFIG_LEMOTE_FULONG is not set
20# CONFIG_MIPS_MALTA is not set
21# CONFIG_MIPS_SIM is not set
22# CONFIG_NEC_MARKEINS is not set
23# CONFIG_MACH_VR41XX is not set
24# CONFIG_NXP_STB220 is not set
25# CONFIG_NXP_STB225 is not set
26# CONFIG_PNX8550_JBS is not set
27# CONFIG_PNX8550_STB810 is not set
28# CONFIG_PMC_MSP is not set
29# CONFIG_PMC_YOSEMITE is not set
30# CONFIG_SGI_IP22 is not set
31# CONFIG_SGI_IP27 is not set
32# CONFIG_SGI_IP28 is not set
33# CONFIG_SGI_IP32 is not set
34# CONFIG_SIBYTE_CRHINE is not set
35# CONFIG_SIBYTE_CARMEL is not set
36# CONFIG_SIBYTE_CRHONE is not set
37# CONFIG_SIBYTE_RHONE is not set
38# CONFIG_SIBYTE_SWARM is not set
39# CONFIG_SIBYTE_LITTLESUR is not set
40# CONFIG_SIBYTE_SENTOSA is not set
41# CONFIG_SIBYTE_BIGSUR is not set
42# CONFIG_SNI_RM is not set
43# CONFIG_MACH_TX39XX is not set
44# CONFIG_MACH_TX49XX is not set
45# CONFIG_MIKROTIK_RB532 is not set
46# CONFIG_WR_PPMC is not set
47# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
48# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
49
50#
51# CPU support
52#
53CONFIG_BCM63XX_CPU_6348=y
54CONFIG_BCM63XX_CPU_6358=y
55CONFIG_BOARD_BCM963XX=y
56CONFIG_RWSEM_GENERIC_SPINLOCK=y
57# CONFIG_ARCH_HAS_ILOG2_U32 is not set
58# CONFIG_ARCH_HAS_ILOG2_U64 is not set
59CONFIG_ARCH_SUPPORTS_OPROFILE=y
60CONFIG_GENERIC_FIND_NEXT_BIT=y
61CONFIG_GENERIC_HWEIGHT=y
62CONFIG_GENERIC_CALIBRATE_DELAY=y
63CONFIG_GENERIC_CLOCKEVENTS=y
64CONFIG_GENERIC_TIME=y
65CONFIG_GENERIC_CMOS_UPDATE=y
66CONFIG_SCHED_OMIT_FRAME_POINTER=y
67CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
68CONFIG_CEVT_R4K_LIB=y
69CONFIG_CEVT_R4K=y
70CONFIG_CSRC_R4K_LIB=y
71CONFIG_CSRC_R4K=y
72CONFIG_DMA_NONCOHERENT=y
73CONFIG_DMA_NEED_PCI_MAP_STATE=y
74CONFIG_EARLY_PRINTK=y
75CONFIG_SYS_HAS_EARLY_PRINTK=y
76# CONFIG_HOTPLUG_CPU is not set
77# CONFIG_NO_IOPORT is not set
78CONFIG_GENERIC_GPIO=y
79CONFIG_CPU_BIG_ENDIAN=y
80# CONFIG_CPU_LITTLE_ENDIAN is not set
81CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
82CONFIG_IRQ_CPU=y
83CONFIG_SWAP_IO_SPACE=y
84CONFIG_MIPS_L1_CACHE_SHIFT=5
85
86#
87# CPU selection
88#
89# CONFIG_CPU_LOONGSON2 is not set
90CONFIG_CPU_MIPS32_R1=y
91# CONFIG_CPU_MIPS32_R2 is not set
92# CONFIG_CPU_MIPS64_R1 is not set
93# CONFIG_CPU_MIPS64_R2 is not set
94# CONFIG_CPU_R3000 is not set
95# CONFIG_CPU_TX39XX is not set
96# CONFIG_CPU_VR41XX is not set
97# CONFIG_CPU_R4300 is not set
98# CONFIG_CPU_R4X00 is not set
99# CONFIG_CPU_TX49XX is not set
100# CONFIG_CPU_R5000 is not set
101# CONFIG_CPU_R5432 is not set
102# CONFIG_CPU_R5500 is not set
103# CONFIG_CPU_R6000 is not set
104# CONFIG_CPU_NEVADA is not set
105# CONFIG_CPU_R8000 is not set
106# CONFIG_CPU_R10000 is not set
107# CONFIG_CPU_RM7000 is not set
108# CONFIG_CPU_RM9000 is not set
109# CONFIG_CPU_SB1 is not set
110# CONFIG_CPU_CAVIUM_OCTEON is not set
111CONFIG_SYS_HAS_CPU_MIPS32_R1=y
112CONFIG_CPU_MIPS32=y
113CONFIG_CPU_MIPSR1=y
114CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
115CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
116CONFIG_HARDWARE_WATCHPOINTS=y
117
118#
119# Kernel type
120#
121CONFIG_32BIT=y
122# CONFIG_64BIT is not set
123CONFIG_PAGE_SIZE_4KB=y
124# CONFIG_PAGE_SIZE_8KB is not set
125# CONFIG_PAGE_SIZE_16KB is not set
126# CONFIG_PAGE_SIZE_32KB is not set
127# CONFIG_PAGE_SIZE_64KB is not set
128CONFIG_CPU_HAS_PREFETCH=y
129CONFIG_MIPS_MT_DISABLED=y
130# CONFIG_MIPS_MT_SMP is not set
131# CONFIG_MIPS_MT_SMTC is not set
132CONFIG_CPU_HAS_LLSC=y
133CONFIG_CPU_HAS_SYNC=y
134CONFIG_GENERIC_HARDIRQS=y
135CONFIG_GENERIC_IRQ_PROBE=y
136CONFIG_CPU_SUPPORTS_HIGHMEM=y
137CONFIG_ARCH_FLATMEM_ENABLE=y
138CONFIG_ARCH_POPULATES_NODE_MAP=y
139CONFIG_SELECT_MEMORY_MODEL=y
140CONFIG_FLATMEM_MANUAL=y
141# CONFIG_DISCONTIGMEM_MANUAL is not set
142# CONFIG_SPARSEMEM_MANUAL is not set
143CONFIG_FLATMEM=y
144CONFIG_FLAT_NODE_MEM_MAP=y
145CONFIG_PAGEFLAGS_EXTENDED=y
146CONFIG_SPLIT_PTLOCK_CPUS=4
147# CONFIG_PHYS_ADDR_T_64BIT is not set
148CONFIG_ZONE_DMA_FLAG=0
149CONFIG_VIRT_TO_BUS=y
150CONFIG_UNEVICTABLE_LRU=y
151CONFIG_HAVE_MLOCK=y
152CONFIG_HAVE_MLOCKED_PAGE_BIT=y
153CONFIG_TICK_ONESHOT=y
154CONFIG_NO_HZ=y
155# CONFIG_HIGH_RES_TIMERS is not set
156CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
157# CONFIG_HZ_48 is not set
158# CONFIG_HZ_100 is not set
159# CONFIG_HZ_128 is not set
160CONFIG_HZ_250=y
161# CONFIG_HZ_256 is not set
162# CONFIG_HZ_1000 is not set
163# CONFIG_HZ_1024 is not set
164CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
165CONFIG_HZ=250
166CONFIG_PREEMPT_NONE=y
167# CONFIG_PREEMPT_VOLUNTARY is not set
168# CONFIG_PREEMPT is not set
169# CONFIG_KEXEC is not set
170# CONFIG_SECCOMP is not set
171CONFIG_LOCKDEP_SUPPORT=y
172CONFIG_STACKTRACE_SUPPORT=y
173CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
174
175#
176# General setup
177#
178CONFIG_EXPERIMENTAL=y
179CONFIG_BROKEN_ON_SMP=y
180CONFIG_INIT_ENV_ARG_LIMIT=32
181CONFIG_LOCALVERSION=""
182# CONFIG_LOCALVERSION_AUTO is not set
183# CONFIG_SWAP is not set
184# CONFIG_SYSVIPC is not set
185# CONFIG_POSIX_MQUEUE is not set
186# CONFIG_BSD_PROCESS_ACCT is not set
187# CONFIG_TASKSTATS is not set
188# CONFIG_AUDIT is not set
189
190#
191# RCU Subsystem
192#
193CONFIG_CLASSIC_RCU=y
194# CONFIG_TREE_RCU is not set
195# CONFIG_PREEMPT_RCU is not set
196# CONFIG_TREE_RCU_TRACE is not set
197# CONFIG_PREEMPT_RCU_TRACE is not set
198# CONFIG_IKCONFIG is not set
199CONFIG_LOG_BUF_SHIFT=17
200# CONFIG_GROUP_SCHED is not set
201# CONFIG_CGROUPS is not set
202CONFIG_SYSFS_DEPRECATED=y
203CONFIG_SYSFS_DEPRECATED_V2=y
204# CONFIG_RELAY is not set
205# CONFIG_NAMESPACES is not set
206# CONFIG_BLK_DEV_INITRD is not set
207CONFIG_CC_OPTIMIZE_FOR_SIZE=y
208CONFIG_SYSCTL=y
209CONFIG_EMBEDDED=y
210CONFIG_SYSCTL_SYSCALL=y
211CONFIG_KALLSYMS=y
212# CONFIG_KALLSYMS_EXTRA_PASS is not set
213# CONFIG_STRIP_ASM_SYMS is not set
214CONFIG_HOTPLUG=y
215CONFIG_PRINTK=y
216CONFIG_BUG=y
217CONFIG_ELF_CORE=y
218# CONFIG_PCSPKR_PLATFORM is not set
219CONFIG_BASE_FULL=y
220# CONFIG_FUTEX is not set
221# CONFIG_EPOLL is not set
222# CONFIG_SIGNALFD is not set
223# CONFIG_TIMERFD is not set
224# CONFIG_EVENTFD is not set
225# CONFIG_SHMEM is not set
226# CONFIG_AIO is not set
227# CONFIG_VM_EVENT_COUNTERS is not set
228CONFIG_PCI_QUIRKS=y
229# CONFIG_SLUB_DEBUG is not set
230CONFIG_COMPAT_BRK=y
231# CONFIG_SLAB is not set
232CONFIG_SLUB=y
233# CONFIG_SLOB is not set
234# CONFIG_PROFILING is not set
235# CONFIG_MARKERS is not set
236CONFIG_HAVE_OPROFILE=y
237# CONFIG_SLOW_WORK is not set
238# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
239CONFIG_BASE_SMALL=0
240# CONFIG_MODULES is not set
241CONFIG_BLOCK=y
242# CONFIG_LBD is not set
243# CONFIG_BLK_DEV_BSG is not set
244# CONFIG_BLK_DEV_INTEGRITY is not set
245
246#
247# IO Schedulers
248#
249CONFIG_IOSCHED_NOOP=y
250# CONFIG_IOSCHED_AS is not set
251# CONFIG_IOSCHED_DEADLINE is not set
252# CONFIG_IOSCHED_CFQ is not set
253# CONFIG_DEFAULT_AS is not set
254# CONFIG_DEFAULT_DEADLINE is not set
255# CONFIG_DEFAULT_CFQ is not set
256CONFIG_DEFAULT_NOOP=y
257CONFIG_DEFAULT_IOSCHED="noop"
258# CONFIG_FREEZER is not set
259
260#
261# Bus options (PCI, PCMCIA, EISA, ISA, TC)
262#
263CONFIG_HW_HAS_PCI=y
264CONFIG_PCI=y
265CONFIG_PCI_DOMAINS=y
266# CONFIG_ARCH_SUPPORTS_MSI is not set
267# CONFIG_PCI_LEGACY is not set
268# CONFIG_PCI_STUB is not set
269# CONFIG_PCI_IOV is not set
270CONFIG_MMU=y
271CONFIG_PCCARD=y
272# CONFIG_PCMCIA_DEBUG is not set
273CONFIG_PCMCIA=y
274CONFIG_PCMCIA_LOAD_CIS=y
275CONFIG_PCMCIA_IOCTL=y
276CONFIG_CARDBUS=y
277
278#
279# PC-card bridges
280#
281# CONFIG_YENTA is not set
282# CONFIG_PD6729 is not set
283# CONFIG_I82092 is not set
284CONFIG_PCMCIA_BCM63XX=y
285# CONFIG_HOTPLUG_PCI is not set
286
287#
288# Executable file formats
289#
290CONFIG_BINFMT_ELF=y
291# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
292# CONFIG_HAVE_AOUT is not set
293# CONFIG_BINFMT_MISC is not set
294CONFIG_TRAD_SIGNALS=y
295
296#
297# Power management options
298#
299CONFIG_ARCH_SUSPEND_POSSIBLE=y
300# CONFIG_PM is not set
301CONFIG_NET=y
302
303#
304# Networking options
305#
306# CONFIG_PACKET is not set
307CONFIG_UNIX=y
308# CONFIG_NET_KEY is not set
309CONFIG_INET=y
310# CONFIG_IP_MULTICAST is not set
311# CONFIG_IP_ADVANCED_ROUTER is not set
312CONFIG_IP_FIB_HASH=y
313# CONFIG_IP_PNP is not set
314# CONFIG_NET_IPIP is not set
315# CONFIG_NET_IPGRE is not set
316# CONFIG_ARPD is not set
317# CONFIG_SYN_COOKIES is not set
318# CONFIG_INET_AH is not set
319# CONFIG_INET_ESP is not set
320# CONFIG_INET_IPCOMP is not set
321# CONFIG_INET_XFRM_TUNNEL is not set
322# CONFIG_INET_TUNNEL is not set
323# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
324# CONFIG_INET_XFRM_MODE_TUNNEL is not set
325# CONFIG_INET_XFRM_MODE_BEET is not set
326# CONFIG_INET_LRO is not set
327# CONFIG_INET_DIAG is not set
328# CONFIG_TCP_CONG_ADVANCED is not set
329CONFIG_TCP_CONG_CUBIC=y
330CONFIG_DEFAULT_TCP_CONG="cubic"
331# CONFIG_TCP_MD5SIG is not set
332# CONFIG_IPV6 is not set
333# CONFIG_NETWORK_SECMARK is not set
334# CONFIG_NETFILTER is not set
335# CONFIG_IP_DCCP is not set
336# CONFIG_IP_SCTP is not set
337# CONFIG_TIPC is not set
338# CONFIG_ATM is not set
339# CONFIG_BRIDGE is not set
340# CONFIG_NET_DSA is not set
341# CONFIG_VLAN_8021Q is not set
342# CONFIG_DECNET is not set
343# CONFIG_LLC2 is not set
344# CONFIG_IPX is not set
345# CONFIG_ATALK is not set
346# CONFIG_X25 is not set
347# CONFIG_LAPB is not set
348# CONFIG_ECONET is not set
349# CONFIG_WAN_ROUTER is not set
350# CONFIG_PHONET is not set
351# CONFIG_NET_SCHED is not set
352# CONFIG_DCB is not set
353
354#
355# Network testing
356#
357# CONFIG_NET_PKTGEN is not set
358# CONFIG_HAMRADIO is not set
359# CONFIG_CAN is not set
360# CONFIG_IRDA is not set
361# CONFIG_BT is not set
362# CONFIG_AF_RXRPC is not set
363# CONFIG_WIRELESS is not set
364# CONFIG_WIMAX is not set
365# CONFIG_RFKILL is not set
366# CONFIG_NET_9P is not set
367
368#
369# Device Drivers
370#
371
372#
373# Generic Driver Options
374#
375CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
376# CONFIG_STANDALONE is not set
377# CONFIG_PREVENT_FIRMWARE_BUILD is not set
378CONFIG_FW_LOADER=y
379CONFIG_FIRMWARE_IN_KERNEL=y
380CONFIG_EXTRA_FIRMWARE=""
381# CONFIG_SYS_HYPERVISOR is not set
382# CONFIG_CONNECTOR is not set
383CONFIG_MTD=y
384# CONFIG_MTD_DEBUG is not set
385# CONFIG_MTD_CONCAT is not set
386CONFIG_MTD_PARTITIONS=y
387# CONFIG_MTD_REDBOOT_PARTS is not set
388# CONFIG_MTD_CMDLINE_PARTS is not set
389# CONFIG_MTD_AR7_PARTS is not set
390
391#
392# User Modules And Translation Layers
393#
394# CONFIG_MTD_CHAR is not set
395# CONFIG_MTD_BLKDEVS is not set
396# CONFIG_MTD_BLOCK is not set
397# CONFIG_MTD_BLOCK_RO is not set
398# CONFIG_FTL is not set
399# CONFIG_NFTL is not set
400# CONFIG_INFTL is not set
401# CONFIG_RFD_FTL is not set
402# CONFIG_SSFDC is not set
403# CONFIG_MTD_OOPS is not set
404
405#
406# RAM/ROM/Flash chip drivers
407#
408CONFIG_MTD_CFI=y
409# CONFIG_MTD_JEDECPROBE is not set
410CONFIG_MTD_GEN_PROBE=y
411# CONFIG_MTD_CFI_ADV_OPTIONS is not set
412CONFIG_MTD_MAP_BANK_WIDTH_1=y
413CONFIG_MTD_MAP_BANK_WIDTH_2=y
414CONFIG_MTD_MAP_BANK_WIDTH_4=y
415# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
416# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
417# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
418CONFIG_MTD_CFI_I1=y
419CONFIG_MTD_CFI_I2=y
420# CONFIG_MTD_CFI_I4 is not set
421# CONFIG_MTD_CFI_I8 is not set
422CONFIG_MTD_CFI_INTELEXT=y
423CONFIG_MTD_CFI_AMDSTD=y
424# CONFIG_MTD_CFI_STAA is not set
425CONFIG_MTD_CFI_UTIL=y
426# CONFIG_MTD_RAM is not set
427# CONFIG_MTD_ROM is not set
428# CONFIG_MTD_ABSENT is not set
429
430#
431# Mapping drivers for chip access
432#
433# CONFIG_MTD_COMPLEX_MAPPINGS is not set
434CONFIG_MTD_PHYSMAP=y
435# CONFIG_MTD_PHYSMAP_COMPAT is not set
436# CONFIG_MTD_INTEL_VR_NOR is not set
437# CONFIG_MTD_PLATRAM is not set
438
439#
440# Self-contained MTD device drivers
441#
442# CONFIG_MTD_PMC551 is not set
443# CONFIG_MTD_SLRAM is not set
444# CONFIG_MTD_PHRAM is not set
445# CONFIG_MTD_MTDRAM is not set
446# CONFIG_MTD_BLOCK2MTD is not set
447
448#
449# Disk-On-Chip Device Drivers
450#
451# CONFIG_MTD_DOC2000 is not set
452# CONFIG_MTD_DOC2001 is not set
453# CONFIG_MTD_DOC2001PLUS is not set
454# CONFIG_MTD_NAND is not set
455# CONFIG_MTD_ONENAND is not set
456
457#
458# LPDDR flash memory drivers
459#
460# CONFIG_MTD_LPDDR is not set
461
462#
463# UBI - Unsorted block images
464#
465# CONFIG_MTD_UBI is not set
466# CONFIG_PARPORT is not set
467# CONFIG_BLK_DEV is not set
468# CONFIG_MISC_DEVICES is not set
469CONFIG_HAVE_IDE=y
470# CONFIG_IDE is not set
471
472#
473# SCSI device support
474#
475# CONFIG_RAID_ATTRS is not set
476# CONFIG_SCSI is not set
477# CONFIG_SCSI_DMA is not set
478# CONFIG_SCSI_NETLINK is not set
479# CONFIG_ATA is not set
480# CONFIG_MD is not set
481# CONFIG_FUSION is not set
482
483#
484# IEEE 1394 (FireWire) support
485#
486
487#
488# Enable only one of the two stacks, unless you know what you are doing
489#
490# CONFIG_FIREWIRE is not set
491# CONFIG_IEEE1394 is not set
492# CONFIG_I2O is not set
493CONFIG_NETDEVICES=y
494CONFIG_COMPAT_NET_DEV_OPS=y
495# CONFIG_DUMMY is not set
496# CONFIG_BONDING is not set
497# CONFIG_MACVLAN is not set
498# CONFIG_EQUALIZER is not set
499# CONFIG_TUN is not set
500# CONFIG_VETH is not set
501# CONFIG_ARCNET is not set
502CONFIG_PHYLIB=y
503
504#
505# MII PHY device drivers
506#
507# CONFIG_MARVELL_PHY is not set
508# CONFIG_DAVICOM_PHY is not set
509# CONFIG_QSEMI_PHY is not set
510# CONFIG_LXT_PHY is not set
511# CONFIG_CICADA_PHY is not set
512# CONFIG_VITESSE_PHY is not set
513# CONFIG_SMSC_PHY is not set
514# CONFIG_BROADCOM_PHY is not set
515CONFIG_BCM63XX_PHY=y
516# CONFIG_ICPLUS_PHY is not set
517# CONFIG_REALTEK_PHY is not set
518# CONFIG_NATIONAL_PHY is not set
519# CONFIG_STE10XP is not set
520# CONFIG_LSI_ET1011C_PHY is not set
521# CONFIG_FIXED_PHY is not set
522# CONFIG_MDIO_BITBANG is not set
523CONFIG_NET_ETHERNET=y
524CONFIG_MII=y
525# CONFIG_AX88796 is not set
526# CONFIG_HAPPYMEAL is not set
527# CONFIG_SUNGEM is not set
528# CONFIG_CASSINI is not set
529# CONFIG_NET_VENDOR_3COM is not set
530# CONFIG_SMC91X is not set
531# CONFIG_DM9000 is not set
532# CONFIG_ETHOC is not set
533# CONFIG_DNET is not set
534# CONFIG_NET_TULIP is not set
535# CONFIG_HP100 is not set
536# CONFIG_IBM_NEW_EMAC_ZMII is not set
537# CONFIG_IBM_NEW_EMAC_RGMII is not set
538# CONFIG_IBM_NEW_EMAC_TAH is not set
539# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
540# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
541# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
542# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
543# CONFIG_NET_PCI is not set
544# CONFIG_B44 is not set
545# CONFIG_ATL2 is not set
546CONFIG_BCM63XX_ENET=y
547# CONFIG_NETDEV_1000 is not set
548# CONFIG_NETDEV_10000 is not set
549# CONFIG_TR is not set
550
551#
552# Wireless LAN
553#
554# CONFIG_WLAN_PRE80211 is not set
555# CONFIG_WLAN_80211 is not set
556
557#
558# Enable WiMAX (Networking options) to see the WiMAX drivers
559#
560
561#
562# USB Network Adapters
563#
564# CONFIG_USB_CATC is not set
565# CONFIG_USB_KAWETH is not set
566# CONFIG_USB_PEGASUS is not set
567# CONFIG_USB_RTL8150 is not set
568# CONFIG_USB_USBNET is not set
569# CONFIG_NET_PCMCIA is not set
570# CONFIG_WAN is not set
571# CONFIG_FDDI is not set
572# CONFIG_HIPPI is not set
573# CONFIG_PPP is not set
574# CONFIG_SLIP is not set
575# CONFIG_NETCONSOLE is not set
576# CONFIG_NETPOLL is not set
577# CONFIG_NET_POLL_CONTROLLER is not set
578# CONFIG_ISDN is not set
579# CONFIG_PHONE is not set
580
581#
582# Input device support
583#
584# CONFIG_INPUT is not set
585
586#
587# Hardware I/O ports
588#
589# CONFIG_SERIO is not set
590# CONFIG_GAMEPORT is not set
591
592#
593# Character devices
594#
595# CONFIG_VT is not set
596# CONFIG_DEVKMEM is not set
597# CONFIG_SERIAL_NONSTANDARD is not set
598# CONFIG_NOZOMI is not set
599
600#
601# Serial drivers
602#
603# CONFIG_SERIAL_8250 is not set
604
605#
606# Non-8250 serial port support
607#
608CONFIG_SERIAL_CORE=y
609CONFIG_SERIAL_CORE_CONSOLE=y
610# CONFIG_SERIAL_JSM is not set
611CONFIG_SERIAL_BCM63XX=y
612CONFIG_SERIAL_BCM63XX_CONSOLE=y
613# CONFIG_UNIX98_PTYS is not set
614CONFIG_LEGACY_PTYS=y
615CONFIG_LEGACY_PTY_COUNT=256
616# CONFIG_IPMI_HANDLER is not set
617# CONFIG_HW_RANDOM is not set
618# CONFIG_R3964 is not set
619# CONFIG_APPLICOM is not set
620
621#
622# PCMCIA character devices
623#
624# CONFIG_SYNCLINK_CS is not set
625# CONFIG_CARDMAN_4000 is not set
626# CONFIG_CARDMAN_4040 is not set
627# CONFIG_IPWIRELESS is not set
628# CONFIG_RAW_DRIVER is not set
629# CONFIG_TCG_TPM is not set
630CONFIG_DEVPORT=y
631# CONFIG_I2C is not set
632# CONFIG_SPI is not set
633CONFIG_ARCH_REQUIRE_GPIOLIB=y
634CONFIG_GPIOLIB=y
635# CONFIG_GPIO_SYSFS is not set
636
637#
638# Memory mapped GPIO expanders:
639#
640
641#
642# I2C GPIO expanders:
643#
644
645#
646# PCI GPIO expanders:
647#
648# CONFIG_GPIO_BT8XX is not set
649
650#
651# SPI GPIO expanders:
652#
653# CONFIG_W1 is not set
654# CONFIG_POWER_SUPPLY is not set
655# CONFIG_HWMON is not set
656# CONFIG_THERMAL is not set
657# CONFIG_THERMAL_HWMON is not set
658# CONFIG_WATCHDOG is not set
659CONFIG_SSB_POSSIBLE=y
660
661#
662# Sonics Silicon Backplane
663#
664CONFIG_SSB=y
665CONFIG_SSB_SPROM=y
666CONFIG_SSB_PCIHOST_POSSIBLE=y
667CONFIG_SSB_PCIHOST=y
668# CONFIG_SSB_B43_PCI_BRIDGE is not set
669CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
670# CONFIG_SSB_PCMCIAHOST is not set
671# CONFIG_SSB_SILENT is not set
672# CONFIG_SSB_DEBUG is not set
673CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
674# CONFIG_SSB_DRIVER_PCICORE is not set
675# CONFIG_SSB_DRIVER_MIPS is not set
676
677#
678# Multifunction device drivers
679#
680# CONFIG_MFD_CORE is not set
681# CONFIG_MFD_SM501 is not set
682# CONFIG_HTC_PASIC3 is not set
683# CONFIG_MFD_TMIO is not set
684# CONFIG_REGULATOR is not set
685
686#
687# Multimedia devices
688#
689
690#
691# Multimedia core support
692#
693# CONFIG_VIDEO_DEV is not set
694# CONFIG_DVB_CORE is not set
695# CONFIG_VIDEO_MEDIA is not set
696
697#
698# Multimedia drivers
699#
700# CONFIG_DAB is not set
701
702#
703# Graphics support
704#
705# CONFIG_DRM is not set
706# CONFIG_VGASTATE is not set
707# CONFIG_VIDEO_OUTPUT_CONTROL is not set
708# CONFIG_FB is not set
709# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
710
711#
712# Display device support
713#
714CONFIG_DISPLAY_SUPPORT=y
715
716#
717# Display hardware drivers
718#
719# CONFIG_SOUND is not set
720CONFIG_USB_SUPPORT=y
721CONFIG_USB_ARCH_HAS_HCD=y
722CONFIG_USB_ARCH_HAS_OHCI=y
723CONFIG_USB_ARCH_HAS_EHCI=y
724CONFIG_USB=y
725# CONFIG_USB_DEBUG is not set
726# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
727
728#
729# Miscellaneous USB options
730#
731# CONFIG_USB_DEVICEFS is not set
732# CONFIG_USB_DEVICE_CLASS is not set
733# CONFIG_USB_DYNAMIC_MINORS is not set
734# CONFIG_USB_OTG is not set
735# CONFIG_USB_OTG_WHITELIST is not set
736# CONFIG_USB_OTG_BLACKLIST_HUB is not set
737# CONFIG_USB_MON is not set
738# CONFIG_USB_WUSB is not set
739# CONFIG_USB_WUSB_CBAF is not set
740
741#
742# USB Host Controller Drivers
743#
744# CONFIG_USB_C67X00_HCD is not set
745CONFIG_USB_EHCI_HCD=y
746# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
747# CONFIG_USB_EHCI_TT_NEWSCHED is not set
748CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
749# CONFIG_USB_OXU210HP_HCD is not set
750# CONFIG_USB_ISP116X_HCD is not set
751# CONFIG_USB_ISP1760_HCD is not set
752CONFIG_USB_OHCI_HCD=y
753# CONFIG_USB_OHCI_HCD_SSB is not set
754CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
755CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
756CONFIG_USB_OHCI_LITTLE_ENDIAN=y
757# CONFIG_USB_UHCI_HCD is not set
758# CONFIG_USB_SL811_HCD is not set
759# CONFIG_USB_R8A66597_HCD is not set
760# CONFIG_USB_WHCI_HCD is not set
761# CONFIG_USB_HWA_HCD is not set
762
763#
764# USB Device Class drivers
765#
766# CONFIG_USB_ACM is not set
767# CONFIG_USB_PRINTER is not set
768# CONFIG_USB_WDM is not set
769# CONFIG_USB_TMC is not set
770
771#
772# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
773#
774
775#
776# also be needed; see USB_STORAGE Help for more info
777#
778# CONFIG_USB_LIBUSUAL is not set
779
780#
781# USB Imaging devices
782#
783# CONFIG_USB_MDC800 is not set
784
785#
786# USB port drivers
787#
788# CONFIG_USB_SERIAL is not set
789
790#
791# USB Miscellaneous drivers
792#
793# CONFIG_USB_EMI62 is not set
794# CONFIG_USB_EMI26 is not set
795# CONFIG_USB_ADUTUX is not set
796# CONFIG_USB_SEVSEG is not set
797# CONFIG_USB_RIO500 is not set
798# CONFIG_USB_LEGOTOWER is not set
799# CONFIG_USB_LCD is not set
800# CONFIG_USB_BERRY_CHARGE is not set
801# CONFIG_USB_LED is not set
802# CONFIG_USB_CYPRESS_CY7C63 is not set
803# CONFIG_USB_CYTHERM is not set
804# CONFIG_USB_IDMOUSE is not set
805# CONFIG_USB_FTDI_ELAN is not set
806# CONFIG_USB_APPLEDISPLAY is not set
807# CONFIG_USB_SISUSBVGA is not set
808# CONFIG_USB_LD is not set
809# CONFIG_USB_TRANCEVIBRATOR is not set
810# CONFIG_USB_IOWARRIOR is not set
811# CONFIG_USB_ISIGHTFW is not set
812# CONFIG_USB_VST is not set
813# CONFIG_USB_GADGET is not set
814
815#
816# OTG and related infrastructure
817#
818# CONFIG_USB_GPIO_VBUS is not set
819# CONFIG_NOP_USB_XCEIV is not set
820# CONFIG_UWB is not set
821# CONFIG_MMC is not set
822# CONFIG_MEMSTICK is not set
823# CONFIG_NEW_LEDS is not set
824# CONFIG_ACCESSIBILITY is not set
825# CONFIG_INFINIBAND is not set
826CONFIG_RTC_LIB=y
827# CONFIG_RTC_CLASS is not set
828# CONFIG_DMADEVICES is not set
829# CONFIG_AUXDISPLAY is not set
830# CONFIG_UIO is not set
831# CONFIG_STAGING is not set
832
833#
834# File systems
835#
836# CONFIG_EXT2_FS is not set
837# CONFIG_EXT3_FS is not set
838# CONFIG_EXT4_FS is not set
839# CONFIG_REISERFS_FS is not set
840# CONFIG_JFS_FS is not set
841# CONFIG_FS_POSIX_ACL is not set
842# CONFIG_FILE_LOCKING is not set
843# CONFIG_XFS_FS is not set
844# CONFIG_OCFS2_FS is not set
845# CONFIG_BTRFS_FS is not set
846# CONFIG_DNOTIFY is not set
847# CONFIG_INOTIFY is not set
848# CONFIG_QUOTA is not set
849# CONFIG_AUTOFS_FS is not set
850# CONFIG_AUTOFS4_FS is not set
851# CONFIG_FUSE_FS is not set
852
853#
854# Caches
855#
856# CONFIG_FSCACHE is not set
857
858#
859# CD-ROM/DVD Filesystems
860#
861# CONFIG_ISO9660_FS is not set
862# CONFIG_UDF_FS is not set
863
864#
865# DOS/FAT/NT Filesystems
866#
867# CONFIG_MSDOS_FS is not set
868# CONFIG_VFAT_FS is not set
869# CONFIG_NTFS_FS is not set
870
871#
872# Pseudo filesystems
873#
874CONFIG_PROC_FS=y
875CONFIG_PROC_KCORE=y
876CONFIG_PROC_SYSCTL=y
877CONFIG_PROC_PAGE_MONITOR=y
878CONFIG_SYSFS=y
879CONFIG_TMPFS=y
880# CONFIG_TMPFS_POSIX_ACL is not set
881# CONFIG_HUGETLB_PAGE is not set
882# CONFIG_CONFIGFS_FS is not set
883CONFIG_MISC_FILESYSTEMS=y
884# CONFIG_ADFS_FS is not set
885# CONFIG_AFFS_FS is not set
886# CONFIG_HFS_FS is not set
887# CONFIG_HFSPLUS_FS is not set
888# CONFIG_BEFS_FS is not set
889# CONFIG_BFS_FS is not set
890# CONFIG_EFS_FS is not set
891# CONFIG_JFFS2_FS is not set
892# CONFIG_CRAMFS is not set
893# CONFIG_SQUASHFS is not set
894# CONFIG_VXFS_FS is not set
895# CONFIG_MINIX_FS is not set
896# CONFIG_OMFS_FS is not set
897# CONFIG_HPFS_FS is not set
898# CONFIG_QNX4FS_FS is not set
899# CONFIG_ROMFS_FS is not set
900# CONFIG_SYSV_FS is not set
901# CONFIG_UFS_FS is not set
902# CONFIG_NILFS2_FS is not set
903# CONFIG_NETWORK_FILESYSTEMS is not set
904
905#
906# Partition Types
907#
908# CONFIG_PARTITION_ADVANCED is not set
909CONFIG_MSDOS_PARTITION=y
910# CONFIG_NLS is not set
911# CONFIG_DLM is not set
912
913#
914# Kernel hacking
915#
916CONFIG_TRACE_IRQFLAGS_SUPPORT=y
917# CONFIG_PRINTK_TIME is not set
918CONFIG_ENABLE_WARN_DEPRECATED=y
919CONFIG_ENABLE_MUST_CHECK=y
920CONFIG_FRAME_WARN=1024
921CONFIG_MAGIC_SYSRQ=y
922# CONFIG_UNUSED_SYMBOLS is not set
923# CONFIG_DEBUG_FS is not set
924# CONFIG_HEADERS_CHECK is not set
925# CONFIG_DEBUG_KERNEL is not set
926# CONFIG_DEBUG_MEMORY_INIT is not set
927# CONFIG_RCU_CPU_STALL_DETECTOR is not set
928CONFIG_SYSCTL_SYSCALL_CHECK=y
929CONFIG_TRACING_SUPPORT=y
930
931#
932# Tracers
933#
934# CONFIG_IRQSOFF_TRACER is not set
935# CONFIG_SCHED_TRACER is not set
936# CONFIG_CONTEXT_SWITCH_TRACER is not set
937# CONFIG_EVENT_TRACER is not set
938# CONFIG_BOOT_TRACER is not set
939# CONFIG_TRACE_BRANCH_PROFILING is not set
940# CONFIG_KMEMTRACE is not set
941# CONFIG_WORKQUEUE_TRACER is not set
942# CONFIG_BLK_DEV_IO_TRACE is not set
943# CONFIG_SAMPLES is not set
944CONFIG_HAVE_ARCH_KGDB=y
945CONFIG_CMDLINE="console=ttyS0,115200"
946
947#
948# Security options
949#
950# CONFIG_KEYS is not set
951# CONFIG_SECURITY is not set
952# CONFIG_SECURITYFS is not set
953# CONFIG_SECURITY_FILE_CAPABILITIES is not set
954# CONFIG_CRYPTO is not set
955# CONFIG_BINARY_PRINTF is not set
956
957#
958# Library routines
959#
960CONFIG_BITREVERSE=y
961CONFIG_GENERIC_FIND_LAST_BIT=y
962# CONFIG_CRC_CCITT is not set
963# CONFIG_CRC16 is not set
964# CONFIG_CRC_T10DIF is not set
965# CONFIG_CRC_ITU_T is not set
966CONFIG_CRC32=y
967# CONFIG_CRC7 is not set
968# CONFIG_LIBCRC32C is not set
969CONFIG_HAS_IOMEM=y
970CONFIG_HAS_IOPORT=y
971CONFIG_HAS_DMA=y
972CONFIG_NLATTR=y
diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h
index 0f5caa1307f1..efeddc8db8b1 100644
--- a/arch/mips/include/asm/fixmap.h
+++ b/arch/mips/include/asm/fixmap.h
@@ -67,11 +67,15 @@ enum fixed_addresses {
67 * the start of the fixmap, and leave one page empty 67 * the start of the fixmap, and leave one page empty
68 * at the top of mem.. 68 * at the top of mem..
69 */ 69 */
70#ifdef CONFIG_BCM63XX
71#define FIXADDR_TOP ((unsigned long)(long)(int)0xff000000)
72#else
70#if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX) 73#if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX)
71#define FIXADDR_TOP ((unsigned long)(long)(int)(0xff000000 - 0x20000)) 74#define FIXADDR_TOP ((unsigned long)(long)(int)(0xff000000 - 0x20000))
72#else 75#else
73#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000) 76#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
74#endif 77#endif
78#endif
75#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) 79#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
76#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 80#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
77 81
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h
new file mode 100644
index 000000000000..fa3e7e617b09
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h
@@ -0,0 +1,12 @@
1#ifndef BCM63XX_BOARD_H_
2#define BCM63XX_BOARD_H_
3
4const char *board_get_name(void);
5
6void board_prom_init(void);
7
8void board_setup(void);
9
10int board_register_devices(void);
11
12#endif /* ! BCM63XX_BOARD_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h
new file mode 100644
index 000000000000..8fcf8df4418a
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h
@@ -0,0 +1,11 @@
1#ifndef BCM63XX_CLK_H_
2#define BCM63XX_CLK_H_
3
4struct clk {
5 void (*set)(struct clk *, int);
6 unsigned int rate;
7 unsigned int usage;
8 int id;
9};
10
11#endif /* ! BCM63XX_CLK_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
new file mode 100644
index 000000000000..b12c4aca2cc9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -0,0 +1,538 @@
1#ifndef BCM63XX_CPU_H_
2#define BCM63XX_CPU_H_
3
4#include <linux/types.h>
5#include <linux/init.h>
6
7/*
8 * Macro to fetch bcm63xx cpu id and revision, should be optimized at
9 * compile time if only one CPU support is enabled (idea stolen from
10 * arm mach-types)
11 */
12#define BCM6338_CPU_ID 0x6338
13#define BCM6345_CPU_ID 0x6345
14#define BCM6348_CPU_ID 0x6348
15#define BCM6358_CPU_ID 0x6358
16
17void __init bcm63xx_cpu_init(void);
18u16 __bcm63xx_get_cpu_id(void);
19u16 bcm63xx_get_cpu_rev(void);
20unsigned int bcm63xx_get_cpu_freq(void);
21
22#ifdef CONFIG_BCM63XX_CPU_6338
23# ifdef bcm63xx_get_cpu_id
24# undef bcm63xx_get_cpu_id
25# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
26# define BCMCPU_RUNTIME_DETECT
27# else
28# define bcm63xx_get_cpu_id() BCM6338_CPU_ID
29# endif
30# define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
31#else
32# define BCMCPU_IS_6338() (0)
33#endif
34
35#ifdef CONFIG_BCM63XX_CPU_6345
36# ifdef bcm63xx_get_cpu_id
37# undef bcm63xx_get_cpu_id
38# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
39# define BCMCPU_RUNTIME_DETECT
40# else
41# define bcm63xx_get_cpu_id() BCM6345_CPU_ID
42# endif
43# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
44#else
45# define BCMCPU_IS_6345() (0)
46#endif
47
48#ifdef CONFIG_BCM63XX_CPU_6348
49# ifdef bcm63xx_get_cpu_id
50# undef bcm63xx_get_cpu_id
51# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
52# define BCMCPU_RUNTIME_DETECT
53# else
54# define bcm63xx_get_cpu_id() BCM6348_CPU_ID
55# endif
56# define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
57#else
58# define BCMCPU_IS_6348() (0)
59#endif
60
61#ifdef CONFIG_BCM63XX_CPU_6358
62# ifdef bcm63xx_get_cpu_id
63# undef bcm63xx_get_cpu_id
64# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
65# define BCMCPU_RUNTIME_DETECT
66# else
67# define bcm63xx_get_cpu_id() BCM6358_CPU_ID
68# endif
69# define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
70#else
71# define BCMCPU_IS_6358() (0)
72#endif
73
74#ifndef bcm63xx_get_cpu_id
75#error "No CPU support configured"
76#endif
77
78/*
79 * While registers sets are (mostly) the same across 63xx CPU, base
80 * address of these sets do change.
81 */
82enum bcm63xx_regs_set {
83 RSET_DSL_LMEM = 0,
84 RSET_PERF,
85 RSET_TIMER,
86 RSET_WDT,
87 RSET_UART0,
88 RSET_GPIO,
89 RSET_SPI,
90 RSET_UDC0,
91 RSET_OHCI0,
92 RSET_OHCI_PRIV,
93 RSET_USBH_PRIV,
94 RSET_MPI,
95 RSET_PCMCIA,
96 RSET_DSL,
97 RSET_ENET0,
98 RSET_ENET1,
99 RSET_ENETDMA,
100 RSET_EHCI0,
101 RSET_SDRAM,
102 RSET_MEMC,
103 RSET_DDR,
104};
105
106#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
107#define RSET_DSL_SIZE 4096
108#define RSET_WDT_SIZE 12
109#define RSET_ENET_SIZE 2048
110#define RSET_ENETDMA_SIZE 2048
111#define RSET_UART_SIZE 24
112#define RSET_UDC_SIZE 256
113#define RSET_OHCI_SIZE 256
114#define RSET_EHCI_SIZE 256
115#define RSET_PCMCIA_SIZE 12
116
117/*
118 * 6338 register sets base address
119 */
120#define BCM_6338_DSL_LMEM_BASE (0xfff00000)
121#define BCM_6338_PERF_BASE (0xfffe0000)
122#define BCM_6338_BB_BASE (0xfffe0100)
123#define BCM_6338_TIMER_BASE (0xfffe0200)
124#define BCM_6338_WDT_BASE (0xfffe021c)
125#define BCM_6338_UART0_BASE (0xfffe0300)
126#define BCM_6338_GPIO_BASE (0xfffe0400)
127#define BCM_6338_SPI_BASE (0xfffe0c00)
128#define BCM_6338_UDC0_BASE (0xdeadbeef)
129#define BCM_6338_USBDMA_BASE (0xfffe2400)
130#define BCM_6338_OHCI0_BASE (0xdeadbeef)
131#define BCM_6338_OHCI_PRIV_BASE (0xfffe3000)
132#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
133#define BCM_6338_MPI_BASE (0xfffe3160)
134#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
135#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
136#define BCM_6338_DSL_BASE (0xfffe1000)
137#define BCM_6338_SAR_BASE (0xfffe2000)
138#define BCM_6338_UBUS_BASE (0xdeadbeef)
139#define BCM_6338_ENET0_BASE (0xfffe2800)
140#define BCM_6338_ENET1_BASE (0xdeadbeef)
141#define BCM_6338_ENETDMA_BASE (0xfffe2400)
142#define BCM_6338_EHCI0_BASE (0xdeadbeef)
143#define BCM_6338_SDRAM_BASE (0xfffe3100)
144#define BCM_6338_MEMC_BASE (0xdeadbeef)
145#define BCM_6338_DDR_BASE (0xdeadbeef)
146
147/*
148 * 6345 register sets base address
149 */
150#define BCM_6345_DSL_LMEM_BASE (0xfff00000)
151#define BCM_6345_PERF_BASE (0xfffe0000)
152#define BCM_6345_BB_BASE (0xfffe0100)
153#define BCM_6345_TIMER_BASE (0xfffe0200)
154#define BCM_6345_WDT_BASE (0xfffe021c)
155#define BCM_6345_UART0_BASE (0xfffe0300)
156#define BCM_6345_GPIO_BASE (0xfffe0400)
157#define BCM_6345_SPI_BASE (0xdeadbeef)
158#define BCM_6345_UDC0_BASE (0xdeadbeef)
159#define BCM_6345_USBDMA_BASE (0xfffe2800)
160#define BCM_6345_ENET0_BASE (0xfffe1800)
161#define BCM_6345_ENETDMA_BASE (0xfffe2800)
162#define BCM_6345_PCMCIA_BASE (0xfffe2028)
163#define BCM_6345_MPI_BASE (0xdeadbeef)
164#define BCM_6345_OHCI0_BASE (0xfffe2100)
165#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
166#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
167#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
168#define BCM_6345_DSL_BASE (0xdeadbeef)
169#define BCM_6345_SAR_BASE (0xdeadbeef)
170#define BCM_6345_UBUS_BASE (0xdeadbeef)
171#define BCM_6345_ENET1_BASE (0xdeadbeef)
172#define BCM_6345_EHCI0_BASE (0xdeadbeef)
173#define BCM_6345_SDRAM_BASE (0xfffe2300)
174#define BCM_6345_MEMC_BASE (0xdeadbeef)
175#define BCM_6345_DDR_BASE (0xdeadbeef)
176
177/*
178 * 6348 register sets base address
179 */
180#define BCM_6348_DSL_LMEM_BASE (0xfff00000)
181#define BCM_6348_PERF_BASE (0xfffe0000)
182#define BCM_6348_TIMER_BASE (0xfffe0200)
183#define BCM_6348_WDT_BASE (0xfffe021c)
184#define BCM_6348_UART0_BASE (0xfffe0300)
185#define BCM_6348_GPIO_BASE (0xfffe0400)
186#define BCM_6348_SPI_BASE (0xfffe0c00)
187#define BCM_6348_UDC0_BASE (0xfffe1000)
188#define BCM_6348_OHCI0_BASE (0xfffe1b00)
189#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
190#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
191#define BCM_6348_MPI_BASE (0xfffe2000)
192#define BCM_6348_PCMCIA_BASE (0xfffe2054)
193#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
194#define BCM_6348_DSL_BASE (0xfffe3000)
195#define BCM_6348_ENET0_BASE (0xfffe6000)
196#define BCM_6348_ENET1_BASE (0xfffe6800)
197#define BCM_6348_ENETDMA_BASE (0xfffe7000)
198#define BCM_6348_EHCI0_BASE (0xdeadbeef)
199#define BCM_6348_SDRAM_BASE (0xfffe2300)
200#define BCM_6348_MEMC_BASE (0xdeadbeef)
201#define BCM_6348_DDR_BASE (0xdeadbeef)
202
203/*
204 * 6358 register sets base address
205 */
206#define BCM_6358_DSL_LMEM_BASE (0xfff00000)
207#define BCM_6358_PERF_BASE (0xfffe0000)
208#define BCM_6358_TIMER_BASE (0xfffe0040)
209#define BCM_6358_WDT_BASE (0xfffe005c)
210#define BCM_6358_UART0_BASE (0xfffe0100)
211#define BCM_6358_GPIO_BASE (0xfffe0080)
212#define BCM_6358_SPI_BASE (0xdeadbeef)
213#define BCM_6358_UDC0_BASE (0xfffe0800)
214#define BCM_6358_OHCI0_BASE (0xfffe1400)
215#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
216#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
217#define BCM_6358_MPI_BASE (0xfffe1000)
218#define BCM_6358_PCMCIA_BASE (0xfffe1054)
219#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
220#define BCM_6358_DSL_BASE (0xfffe3000)
221#define BCM_6358_ENET0_BASE (0xfffe4000)
222#define BCM_6358_ENET1_BASE (0xfffe4800)
223#define BCM_6358_ENETDMA_BASE (0xfffe5000)
224#define BCM_6358_EHCI0_BASE (0xfffe1300)
225#define BCM_6358_SDRAM_BASE (0xdeadbeef)
226#define BCM_6358_MEMC_BASE (0xfffe1200)
227#define BCM_6358_DDR_BASE (0xfffe12a0)
228
229
230extern const unsigned long *bcm63xx_regs_base;
231
232static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
233{
234#ifdef BCMCPU_RUNTIME_DETECT
235 return bcm63xx_regs_base[set];
236#else
237#ifdef CONFIG_BCM63XX_CPU_6338
238 switch (set) {
239 case RSET_DSL_LMEM:
240 return BCM_6338_DSL_LMEM_BASE;
241 case RSET_PERF:
242 return BCM_6338_PERF_BASE;
243 case RSET_TIMER:
244 return BCM_6338_TIMER_BASE;
245 case RSET_WDT:
246 return BCM_6338_WDT_BASE;
247 case RSET_UART0:
248 return BCM_6338_UART0_BASE;
249 case RSET_GPIO:
250 return BCM_6338_GPIO_BASE;
251 case RSET_SPI:
252 return BCM_6338_SPI_BASE;
253 case RSET_UDC0:
254 return BCM_6338_UDC0_BASE;
255 case RSET_OHCI0:
256 return BCM_6338_OHCI0_BASE;
257 case RSET_OHCI_PRIV:
258 return BCM_6338_OHCI_PRIV_BASE;
259 case RSET_USBH_PRIV:
260 return BCM_6338_USBH_PRIV_BASE;
261 case RSET_MPI:
262 return BCM_6338_MPI_BASE;
263 case RSET_PCMCIA:
264 return BCM_6338_PCMCIA_BASE;
265 case RSET_DSL:
266 return BCM_6338_DSL_BASE;
267 case RSET_ENET0:
268 return BCM_6338_ENET0_BASE;
269 case RSET_ENET1:
270 return BCM_6338_ENET1_BASE;
271 case RSET_ENETDMA:
272 return BCM_6338_ENETDMA_BASE;
273 case RSET_EHCI0:
274 return BCM_6338_EHCI0_BASE;
275 case RSET_SDRAM:
276 return BCM_6338_SDRAM_BASE;
277 case RSET_MEMC:
278 return BCM_6338_MEMC_BASE;
279 case RSET_DDR:
280 return BCM_6338_DDR_BASE;
281 }
282#endif
283#ifdef CONFIG_BCM63XX_CPU_6345
284 switch (set) {
285 case RSET_DSL_LMEM:
286 return BCM_6345_DSL_LMEM_BASE;
287 case RSET_PERF:
288 return BCM_6345_PERF_BASE;
289 case RSET_TIMER:
290 return BCM_6345_TIMER_BASE;
291 case RSET_WDT:
292 return BCM_6345_WDT_BASE;
293 case RSET_UART0:
294 return BCM_6345_UART0_BASE;
295 case RSET_GPIO:
296 return BCM_6345_GPIO_BASE;
297 case RSET_SPI:
298 return BCM_6345_SPI_BASE;
299 case RSET_UDC0:
300 return BCM_6345_UDC0_BASE;
301 case RSET_OHCI0:
302 return BCM_6345_OHCI0_BASE;
303 case RSET_OHCI_PRIV:
304 return BCM_6345_OHCI_PRIV_BASE;
305 case RSET_USBH_PRIV:
306 return BCM_6345_USBH_PRIV_BASE;
307 case RSET_MPI:
308 return BCM_6345_MPI_BASE;
309 case RSET_PCMCIA:
310 return BCM_6345_PCMCIA_BASE;
311 case RSET_DSL:
312 return BCM_6345_DSL_BASE;
313 case RSET_ENET0:
314 return BCM_6345_ENET0_BASE;
315 case RSET_ENET1:
316 return BCM_6345_ENET1_BASE;
317 case RSET_ENETDMA:
318 return BCM_6345_ENETDMA_BASE;
319 case RSET_EHCI0:
320 return BCM_6345_EHCI0_BASE;
321 case RSET_SDRAM:
322 return BCM_6345_SDRAM_BASE;
323 case RSET_MEMC:
324 return BCM_6345_MEMC_BASE;
325 case RSET_DDR:
326 return BCM_6345_DDR_BASE;
327 }
328#endif
329#ifdef CONFIG_BCM63XX_CPU_6348
330 switch (set) {
331 case RSET_DSL_LMEM:
332 return BCM_6348_DSL_LMEM_BASE;
333 case RSET_PERF:
334 return BCM_6348_PERF_BASE;
335 case RSET_TIMER:
336 return BCM_6348_TIMER_BASE;
337 case RSET_WDT:
338 return BCM_6348_WDT_BASE;
339 case RSET_UART0:
340 return BCM_6348_UART0_BASE;
341 case RSET_GPIO:
342 return BCM_6348_GPIO_BASE;
343 case RSET_SPI:
344 return BCM_6348_SPI_BASE;
345 case RSET_UDC0:
346 return BCM_6348_UDC0_BASE;
347 case RSET_OHCI0:
348 return BCM_6348_OHCI0_BASE;
349 case RSET_OHCI_PRIV:
350 return BCM_6348_OHCI_PRIV_BASE;
351 case RSET_USBH_PRIV:
352 return BCM_6348_USBH_PRIV_BASE;
353 case RSET_MPI:
354 return BCM_6348_MPI_BASE;
355 case RSET_PCMCIA:
356 return BCM_6348_PCMCIA_BASE;
357 case RSET_DSL:
358 return BCM_6348_DSL_BASE;
359 case RSET_ENET0:
360 return BCM_6348_ENET0_BASE;
361 case RSET_ENET1:
362 return BCM_6348_ENET1_BASE;
363 case RSET_ENETDMA:
364 return BCM_6348_ENETDMA_BASE;
365 case RSET_EHCI0:
366 return BCM_6348_EHCI0_BASE;
367 case RSET_SDRAM:
368 return BCM_6348_SDRAM_BASE;
369 case RSET_MEMC:
370 return BCM_6348_MEMC_BASE;
371 case RSET_DDR:
372 return BCM_6348_DDR_BASE;
373 }
374#endif
375#ifdef CONFIG_BCM63XX_CPU_6358
376 switch (set) {
377 case RSET_DSL_LMEM:
378 return BCM_6358_DSL_LMEM_BASE;
379 case RSET_PERF:
380 return BCM_6358_PERF_BASE;
381 case RSET_TIMER:
382 return BCM_6358_TIMER_BASE;
383 case RSET_WDT:
384 return BCM_6358_WDT_BASE;
385 case RSET_UART0:
386 return BCM_6358_UART0_BASE;
387 case RSET_GPIO:
388 return BCM_6358_GPIO_BASE;
389 case RSET_SPI:
390 return BCM_6358_SPI_BASE;
391 case RSET_UDC0:
392 return BCM_6358_UDC0_BASE;
393 case RSET_OHCI0:
394 return BCM_6358_OHCI0_BASE;
395 case RSET_OHCI_PRIV:
396 return BCM_6358_OHCI_PRIV_BASE;
397 case RSET_USBH_PRIV:
398 return BCM_6358_USBH_PRIV_BASE;
399 case RSET_MPI:
400 return BCM_6358_MPI_BASE;
401 case RSET_PCMCIA:
402 return BCM_6358_PCMCIA_BASE;
403 case RSET_ENET0:
404 return BCM_6358_ENET0_BASE;
405 case RSET_ENET1:
406 return BCM_6358_ENET1_BASE;
407 case RSET_ENETDMA:
408 return BCM_6358_ENETDMA_BASE;
409 case RSET_DSL:
410 return BCM_6358_DSL_BASE;
411 case RSET_EHCI0:
412 return BCM_6358_EHCI0_BASE;
413 case RSET_SDRAM:
414 return BCM_6358_SDRAM_BASE;
415 case RSET_MEMC:
416 return BCM_6358_MEMC_BASE;
417 case RSET_DDR:
418 return BCM_6358_DDR_BASE;
419 }
420#endif
421#endif
422 /* unreached */
423 return 0;
424}
425
426/*
427 * IRQ number changes across CPU too
428 */
429enum bcm63xx_irq {
430 IRQ_TIMER = 0,
431 IRQ_UART0,
432 IRQ_DSL,
433 IRQ_ENET0,
434 IRQ_ENET1,
435 IRQ_ENET_PHY,
436 IRQ_OHCI0,
437 IRQ_EHCI0,
438 IRQ_PCMCIA0,
439 IRQ_ENET0_RXDMA,
440 IRQ_ENET0_TXDMA,
441 IRQ_ENET1_RXDMA,
442 IRQ_ENET1_TXDMA,
443 IRQ_PCI,
444 IRQ_PCMCIA,
445};
446
447/*
448 * 6338 irqs
449 */
450#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
451#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
452#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
453#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4)
454#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
455#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
456#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
457#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
458#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
459#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10)
460#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11)
461#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
462#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
463#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
464#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
465#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
466#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
467
468/*
469 * 6345 irqs
470 */
471#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
472#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
473#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
474#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
475#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
476#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
477#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
478#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
479#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
480#define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5)
481#define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6)
482#define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9)
483#define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10)
484#define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13)
485#define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14)
486#define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15)
487#define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16)
488#define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17)
489#define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18)
490
491/*
492 * 6348 irqs
493 */
494#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
495#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
496#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
497#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
498#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
499#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
500#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
501#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
502#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
503#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
504#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
505#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
506#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
507
508/*
509 * 6358 irqs
510 */
511#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
512#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
513#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
514#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
515#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
516#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
517#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
518#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
519#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
520#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
521#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
522#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
523#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
524#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
525
526extern const int *bcm63xx_irqs;
527
528static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
529{
530 return bcm63xx_irqs[irq];
531}
532
533/*
534 * return installed memory size
535 */
536unsigned int bcm63xx_get_memory_size(void);
537
538#endif /* !BCM63XX_CPU_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h
new file mode 100644
index 000000000000..b1821c866e53
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h
@@ -0,0 +1,10 @@
1#ifndef BCM63XX_CS_H
2#define BCM63XX_CS_H
3
4int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size);
5int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
6 unsigned int setup, unsigned int hold);
7int bcm63xx_set_cs_param(unsigned int cs, u32 flags);
8int bcm63xx_set_cs_status(unsigned int cs, int enable);
9
10#endif /* !BCM63XX_CS_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h
new file mode 100644
index 000000000000..b587d45c3045
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h
@@ -0,0 +1,13 @@
1#ifndef __BCM63XX_DSP_H
2#define __BCM63XX_DSP_H
3
4struct bcm63xx_dsp_platform_data {
5 unsigned gpio_rst;
6 unsigned gpio_int;
7 unsigned cs;
8 unsigned ext_irq;
9};
10
11int __init bcm63xx_dsp_register(const struct bcm63xx_dsp_platform_data *pd);
12
13#endif /* __BCM63XX_DSP_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
new file mode 100644
index 000000000000..d53f611184b9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
@@ -0,0 +1,45 @@
1#ifndef BCM63XX_DEV_ENET_H_
2#define BCM63XX_DEV_ENET_H_
3
4#include <linux/if_ether.h>
5#include <linux/init.h>
6
7/*
8 * on board ethernet platform data
9 */
10struct bcm63xx_enet_platform_data {
11 char mac_addr[ETH_ALEN];
12
13 int has_phy;
14
15 /* if has_phy, then set use_internal_phy */
16 int use_internal_phy;
17
18 /* or fill phy info to use an external one */
19 int phy_id;
20 int has_phy_interrupt;
21 int phy_interrupt;
22
23 /* if has_phy, use autonegociated pause parameters or force
24 * them */
25 int pause_auto;
26 int pause_rx;
27 int pause_tx;
28
29 /* if !has_phy, set desired forced speed/duplex */
30 int force_speed_100;
31 int force_duplex_full;
32
33 /* if !has_phy, set callback to perform mii device
34 * init/remove */
35 int (*mii_config)(struct net_device *dev, int probe,
36 int (*mii_read)(struct net_device *dev,
37 int phy_id, int reg),
38 void (*mii_write)(struct net_device *dev,
39 int phy_id, int reg, int val));
40};
41
42int __init bcm63xx_enet_register(int unit,
43 const struct bcm63xx_enet_platform_data *pd);
44
45#endif /* ! BCM63XX_DEV_ENET_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h
new file mode 100644
index 000000000000..c549344b70ad
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h
@@ -0,0 +1,6 @@
1#ifndef BCM63XX_DEV_PCI_H_
2#define BCM63XX_DEV_PCI_H_
3
4extern int bcm63xx_pci_enabled;
5
6#endif /* BCM63XX_DEV_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
new file mode 100644
index 000000000000..76a0b7216af5
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -0,0 +1,22 @@
1#ifndef BCM63XX_GPIO_H
2#define BCM63XX_GPIO_H
3
4#include <linux/init.h>
5
6int __init bcm63xx_gpio_init(void);
7
8static inline unsigned long bcm63xx_gpio_count(void)
9{
10 switch (bcm63xx_get_cpu_id()) {
11 case BCM6358_CPU_ID:
12 return 40;
13 case BCM6348_CPU_ID:
14 default:
15 return 37;
16 }
17}
18
19#define GPIO_DIR_OUT 0x0
20#define GPIO_DIR_IN 0x1
21
22#endif /* !BCM63XX_GPIO_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
new file mode 100644
index 000000000000..91180fac6ed9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -0,0 +1,93 @@
1#ifndef BCM63XX_IO_H_
2#define BCM63XX_IO_H_
3
4#include "bcm63xx_cpu.h"
5
6/*
7 * Physical memory map, RAM is mapped at 0x0.
8 *
9 * Note that size MUST be a power of two.
10 */
11#define BCM_PCMCIA_COMMON_BASE_PA (0x20000000)
12#define BCM_PCMCIA_COMMON_SIZE (16 * 1024 * 1024)
13#define BCM_PCMCIA_COMMON_END_PA (BCM_PCMCIA_COMMON_BASE_PA + \
14 BCM_PCMCIA_COMMON_SIZE - 1)
15
16#define BCM_PCMCIA_ATTR_BASE_PA (0x21000000)
17#define BCM_PCMCIA_ATTR_SIZE (16 * 1024 * 1024)
18#define BCM_PCMCIA_ATTR_END_PA (BCM_PCMCIA_ATTR_BASE_PA + \
19 BCM_PCMCIA_ATTR_SIZE - 1)
20
21#define BCM_PCMCIA_IO_BASE_PA (0x22000000)
22#define BCM_PCMCIA_IO_SIZE (64 * 1024)
23#define BCM_PCMCIA_IO_END_PA (BCM_PCMCIA_IO_BASE_PA + \
24 BCM_PCMCIA_IO_SIZE - 1)
25
26#define BCM_PCI_MEM_BASE_PA (0x30000000)
27#define BCM_PCI_MEM_SIZE (128 * 1024 * 1024)
28#define BCM_PCI_MEM_END_PA (BCM_PCI_MEM_BASE_PA + \
29 BCM_PCI_MEM_SIZE - 1)
30
31#define BCM_PCI_IO_BASE_PA (0x08000000)
32#define BCM_PCI_IO_SIZE (64 * 1024)
33#define BCM_PCI_IO_END_PA (BCM_PCI_IO_BASE_PA + \
34 BCM_PCI_IO_SIZE - 1)
35#define BCM_PCI_IO_HALF_PA (BCM_PCI_IO_BASE_PA + \
36 (BCM_PCI_IO_SIZE / 2) - 1)
37
38#define BCM_CB_MEM_BASE_PA (0x38000000)
39#define BCM_CB_MEM_SIZE (128 * 1024 * 1024)
40#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \
41 BCM_CB_MEM_SIZE - 1)
42
43
44/*
45 * Internal registers are accessed through KSEG3
46 */
47#define BCM_REGS_VA(x) ((void __iomem *)(x))
48
49#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a))
50#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a))
51#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a))
52#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
53#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
54#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
55
56/*
57 * IO helpers to access register set for current CPU
58 */
59#define bcm_rset_readb(s, o) bcm_readb(bcm63xx_regset_address(s) + (o))
60#define bcm_rset_readw(s, o) bcm_readw(bcm63xx_regset_address(s) + (o))
61#define bcm_rset_readl(s, o) bcm_readl(bcm63xx_regset_address(s) + (o))
62#define bcm_rset_writeb(s, v, o) bcm_writeb((v), \
63 bcm63xx_regset_address(s) + (o))
64#define bcm_rset_writew(s, v, o) bcm_writew((v), \
65 bcm63xx_regset_address(s) + (o))
66#define bcm_rset_writel(s, v, o) bcm_writel((v), \
67 bcm63xx_regset_address(s) + (o))
68
69/*
70 * helpers for frequently used register sets
71 */
72#define bcm_perf_readl(o) bcm_rset_readl(RSET_PERF, (o))
73#define bcm_perf_writel(v, o) bcm_rset_writel(RSET_PERF, (v), (o))
74#define bcm_timer_readl(o) bcm_rset_readl(RSET_TIMER, (o))
75#define bcm_timer_writel(v, o) bcm_rset_writel(RSET_TIMER, (v), (o))
76#define bcm_wdt_readl(o) bcm_rset_readl(RSET_WDT, (o))
77#define bcm_wdt_writel(v, o) bcm_rset_writel(RSET_WDT, (v), (o))
78#define bcm_gpio_readl(o) bcm_rset_readl(RSET_GPIO, (o))
79#define bcm_gpio_writel(v, o) bcm_rset_writel(RSET_GPIO, (v), (o))
80#define bcm_uart0_readl(o) bcm_rset_readl(RSET_UART0, (o))
81#define bcm_uart0_writel(v, o) bcm_rset_writel(RSET_UART0, (v), (o))
82#define bcm_mpi_readl(o) bcm_rset_readl(RSET_MPI, (o))
83#define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o))
84#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o))
85#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
86#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o))
87#define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o))
88#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o))
89#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o))
90#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o))
91#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
92
93#endif /* ! BCM63XX_IO_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
new file mode 100644
index 000000000000..5f95577c8213
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
@@ -0,0 +1,15 @@
1#ifndef BCM63XX_IRQ_H_
2#define BCM63XX_IRQ_H_
3
4#include <bcm63xx_cpu.h>
5
6#define IRQ_MIPS_BASE 0
7#define IRQ_INTERNAL_BASE 8
8
9#define IRQ_EXT_BASE (IRQ_MIPS_BASE + 3)
10#define IRQ_EXT_0 (IRQ_EXT_BASE + 0)
11#define IRQ_EXT_1 (IRQ_EXT_BASE + 1)
12#define IRQ_EXT_2 (IRQ_EXT_BASE + 2)
13#define IRQ_EXT_3 (IRQ_EXT_BASE + 3)
14
15#endif /* ! BCM63XX_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
new file mode 100644
index 000000000000..ed4ccec87dd4
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -0,0 +1,773 @@
1#ifndef BCM63XX_REGS_H_
2#define BCM63XX_REGS_H_
3
4/*************************************************************************
5 * _REG relative to RSET_PERF
6 *************************************************************************/
7
8/* Chip Identifier / Revision register */
9#define PERF_REV_REG 0x0
10#define REV_CHIPID_SHIFT 16
11#define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
12#define REV_REVID_SHIFT 0
13#define REV_REVID_MASK (0xffff << REV_REVID_SHIFT)
14
15/* Clock Control register */
16#define PERF_CKCTL_REG 0x4
17
18#define CKCTL_6338_ADSLPHY_EN (1 << 0)
19#define CKCTL_6338_MPI_EN (1 << 1)
20#define CKCTL_6338_DRAM_EN (1 << 2)
21#define CKCTL_6338_ENET_EN (1 << 4)
22#define CKCTL_6338_USBS_EN (1 << 4)
23#define CKCTL_6338_SAR_EN (1 << 5)
24#define CKCTL_6338_SPI_EN (1 << 9)
25
26#define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \
27 CKCTL_6338_MPI_EN | \
28 CKCTL_6338_ENET_EN | \
29 CKCTL_6338_SAR_EN | \
30 CKCTL_6338_SPI_EN)
31
32#define CKCTL_6345_CPU_EN (1 << 0)
33#define CKCTL_6345_BUS_EN (1 << 1)
34#define CKCTL_6345_EBI_EN (1 << 2)
35#define CKCTL_6345_UART_EN (1 << 3)
36#define CKCTL_6345_ADSLPHY_EN (1 << 4)
37#define CKCTL_6345_ENET_EN (1 << 7)
38#define CKCTL_6345_USBH_EN (1 << 8)
39
40#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
41 CKCTL_6345_USBH_EN | \
42 CKCTL_6345_ADSLPHY_EN)
43
44#define CKCTL_6348_ADSLPHY_EN (1 << 0)
45#define CKCTL_6348_MPI_EN (1 << 1)
46#define CKCTL_6348_SDRAM_EN (1 << 2)
47#define CKCTL_6348_M2M_EN (1 << 3)
48#define CKCTL_6348_ENET_EN (1 << 4)
49#define CKCTL_6348_SAR_EN (1 << 5)
50#define CKCTL_6348_USBS_EN (1 << 6)
51#define CKCTL_6348_USBH_EN (1 << 8)
52#define CKCTL_6348_SPI_EN (1 << 9)
53
54#define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \
55 CKCTL_6348_M2M_EN | \
56 CKCTL_6348_ENET_EN | \
57 CKCTL_6348_SAR_EN | \
58 CKCTL_6348_USBS_EN | \
59 CKCTL_6348_USBH_EN | \
60 CKCTL_6348_SPI_EN)
61
62#define CKCTL_6358_ENET_EN (1 << 4)
63#define CKCTL_6358_ADSLPHY_EN (1 << 5)
64#define CKCTL_6358_PCM_EN (1 << 8)
65#define CKCTL_6358_SPI_EN (1 << 9)
66#define CKCTL_6358_USBS_EN (1 << 10)
67#define CKCTL_6358_SAR_EN (1 << 11)
68#define CKCTL_6358_EMUSB_EN (1 << 17)
69#define CKCTL_6358_ENET0_EN (1 << 18)
70#define CKCTL_6358_ENET1_EN (1 << 19)
71#define CKCTL_6358_USBSU_EN (1 << 20)
72#define CKCTL_6358_EPHY_EN (1 << 21)
73
74#define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \
75 CKCTL_6358_ADSLPHY_EN | \
76 CKCTL_6358_PCM_EN | \
77 CKCTL_6358_SPI_EN | \
78 CKCTL_6358_USBS_EN | \
79 CKCTL_6358_SAR_EN | \
80 CKCTL_6358_EMUSB_EN | \
81 CKCTL_6358_ENET0_EN | \
82 CKCTL_6358_ENET1_EN | \
83 CKCTL_6358_USBSU_EN | \
84 CKCTL_6358_EPHY_EN)
85
86/* System PLL Control register */
87#define PERF_SYS_PLL_CTL_REG 0x8
88#define SYS_PLL_SOFT_RESET 0x1
89
90/* Interrupt Mask register */
91#define PERF_IRQMASK_REG 0xc
92#define PERF_IRQSTAT_REG 0x10
93
94/* Interrupt Status register */
95#define PERF_IRQSTAT_REG 0x10
96
97/* External Interrupt Configuration register */
98#define PERF_EXTIRQ_CFG_REG 0x14
99#define EXTIRQ_CFG_SENSE(x) (1 << (x))
100#define EXTIRQ_CFG_STAT(x) (1 << (x + 5))
101#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10))
102#define EXTIRQ_CFG_MASK(x) (1 << (x + 15))
103#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20))
104#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25))
105
106#define EXTIRQ_CFG_CLEAR_ALL (0xf << 10)
107#define EXTIRQ_CFG_MASK_ALL (0xf << 15)
108
109/* Soft Reset register */
110#define PERF_SOFTRESET_REG 0x28
111
112#define SOFTRESET_6338_SPI_MASK (1 << 0)
113#define SOFTRESET_6338_ENET_MASK (1 << 2)
114#define SOFTRESET_6338_USBH_MASK (1 << 3)
115#define SOFTRESET_6338_USBS_MASK (1 << 4)
116#define SOFTRESET_6338_ADSL_MASK (1 << 5)
117#define SOFTRESET_6338_DMAMEM_MASK (1 << 6)
118#define SOFTRESET_6338_SAR_MASK (1 << 7)
119#define SOFTRESET_6338_ACLC_MASK (1 << 8)
120#define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
121#define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \
122 SOFTRESET_6338_ENET_MASK | \
123 SOFTRESET_6338_USBH_MASK | \
124 SOFTRESET_6338_USBS_MASK | \
125 SOFTRESET_6338_ADSL_MASK | \
126 SOFTRESET_6338_DMAMEM_MASK | \
127 SOFTRESET_6338_SAR_MASK | \
128 SOFTRESET_6338_ACLC_MASK | \
129 SOFTRESET_6338_ADSLMIPSPLL_MASK)
130
131#define SOFTRESET_6348_SPI_MASK (1 << 0)
132#define SOFTRESET_6348_ENET_MASK (1 << 2)
133#define SOFTRESET_6348_USBH_MASK (1 << 3)
134#define SOFTRESET_6348_USBS_MASK (1 << 4)
135#define SOFTRESET_6348_ADSL_MASK (1 << 5)
136#define SOFTRESET_6348_DMAMEM_MASK (1 << 6)
137#define SOFTRESET_6348_SAR_MASK (1 << 7)
138#define SOFTRESET_6348_ACLC_MASK (1 << 8)
139#define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
140
141#define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \
142 SOFTRESET_6348_ENET_MASK | \
143 SOFTRESET_6348_USBH_MASK | \
144 SOFTRESET_6348_USBS_MASK | \
145 SOFTRESET_6348_ADSL_MASK | \
146 SOFTRESET_6348_DMAMEM_MASK | \
147 SOFTRESET_6348_SAR_MASK | \
148 SOFTRESET_6348_ACLC_MASK | \
149 SOFTRESET_6348_ADSLMIPSPLL_MASK)
150
151/* MIPS PLL control register */
152#define PERF_MIPSPLLCTL_REG 0x34
153#define MIPSPLLCTL_N1_SHIFT 20
154#define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT)
155#define MIPSPLLCTL_N2_SHIFT 15
156#define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT)
157#define MIPSPLLCTL_M1REF_SHIFT 12
158#define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT)
159#define MIPSPLLCTL_M2REF_SHIFT 9
160#define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT)
161#define MIPSPLLCTL_M1CPU_SHIFT 6
162#define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
163#define MIPSPLLCTL_M1BUS_SHIFT 3
164#define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
165#define MIPSPLLCTL_M2BUS_SHIFT 0
166#define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
167
168/* ADSL PHY PLL Control register */
169#define PERF_ADSLPLLCTL_REG 0x38
170#define ADSLPLLCTL_N1_SHIFT 20
171#define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT)
172#define ADSLPLLCTL_N2_SHIFT 15
173#define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT)
174#define ADSLPLLCTL_M1REF_SHIFT 12
175#define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT)
176#define ADSLPLLCTL_M2REF_SHIFT 9
177#define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT)
178#define ADSLPLLCTL_M1CPU_SHIFT 6
179#define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
180#define ADSLPLLCTL_M1BUS_SHIFT 3
181#define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
182#define ADSLPLLCTL_M2BUS_SHIFT 0
183#define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
184
185#define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \
186 (((n1) << ADSLPLLCTL_N1_SHIFT) | \
187 ((n2) << ADSLPLLCTL_N2_SHIFT) | \
188 ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \
189 ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \
190 ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \
191 ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \
192 ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
193
194
195/*************************************************************************
196 * _REG relative to RSET_TIMER
197 *************************************************************************/
198
199#define BCM63XX_TIMER_COUNT 4
200#define TIMER_T0_ID 0
201#define TIMER_T1_ID 1
202#define TIMER_T2_ID 2
203#define TIMER_WDT_ID 3
204
205/* Timer irqstat register */
206#define TIMER_IRQSTAT_REG 0
207#define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x))
208#define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0)
209#define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1)
210#define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2)
211#define TIMER_IRQSTAT_WDT_CAUSE (1 << 3)
212#define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8))
213#define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8)
214#define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
215#define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
216
217/* Timer control register */
218#define TIMER_CTLx_REG(x) (0x4 + (x * 4))
219#define TIMER_CTL0_REG 0x4
220#define TIMER_CTL1_REG 0x8
221#define TIMER_CTL2_REG 0xC
222#define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff)
223#define TIMER_CTL_MONOTONIC_MASK (1 << 30)
224#define TIMER_CTL_ENABLE_MASK (1 << 31)
225
226
227/*************************************************************************
228 * _REG relative to RSET_WDT
229 *************************************************************************/
230
231/* Watchdog default count register */
232#define WDT_DEFVAL_REG 0x0
233
234/* Watchdog control register */
235#define WDT_CTL_REG 0x4
236
237/* Watchdog control register constants */
238#define WDT_START_1 (0xff00)
239#define WDT_START_2 (0x00ff)
240#define WDT_STOP_1 (0xee00)
241#define WDT_STOP_2 (0x00ee)
242
243/* Watchdog reset length register */
244#define WDT_RSTLEN_REG 0x8
245
246
247/*************************************************************************
248 * _REG relative to RSET_UARTx
249 *************************************************************************/
250
251/* UART Control Register */
252#define UART_CTL_REG 0x0
253#define UART_CTL_RXTMOUTCNT_SHIFT 0
254#define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
255#define UART_CTL_RSTTXDN_SHIFT 5
256#define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
257#define UART_CTL_RSTRXFIFO_SHIFT 6
258#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
259#define UART_CTL_RSTTXFIFO_SHIFT 7
260#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
261#define UART_CTL_STOPBITS_SHIFT 8
262#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
263#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
264#define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
265#define UART_CTL_BITSPERSYM_SHIFT 12
266#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
267#define UART_CTL_XMITBRK_SHIFT 14
268#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
269#define UART_CTL_RSVD_SHIFT 15
270#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
271#define UART_CTL_RXPAREVEN_SHIFT 16
272#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
273#define UART_CTL_RXPAREN_SHIFT 17
274#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
275#define UART_CTL_TXPAREVEN_SHIFT 18
276#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
277#define UART_CTL_TXPAREN_SHIFT 18
278#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
279#define UART_CTL_LOOPBACK_SHIFT 20
280#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
281#define UART_CTL_RXEN_SHIFT 21
282#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
283#define UART_CTL_TXEN_SHIFT 22
284#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
285#define UART_CTL_BRGEN_SHIFT 23
286#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
287
288/* UART Baudword register */
289#define UART_BAUD_REG 0x4
290
291/* UART Misc Control register */
292#define UART_MCTL_REG 0x8
293#define UART_MCTL_DTR_SHIFT 0
294#define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
295#define UART_MCTL_RTS_SHIFT 1
296#define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
297#define UART_MCTL_RXFIFOTHRESH_SHIFT 8
298#define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
299#define UART_MCTL_TXFIFOTHRESH_SHIFT 12
300#define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
301#define UART_MCTL_RXFIFOFILL_SHIFT 16
302#define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
303#define UART_MCTL_TXFIFOFILL_SHIFT 24
304#define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
305
306/* UART External Input Configuration register */
307#define UART_EXTINP_REG 0xc
308#define UART_EXTINP_RI_SHIFT 0
309#define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
310#define UART_EXTINP_CTS_SHIFT 1
311#define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
312#define UART_EXTINP_DCD_SHIFT 2
313#define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
314#define UART_EXTINP_DSR_SHIFT 3
315#define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
316#define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
317#define UART_EXTINP_IRMASK(x) (1 << (x + 8))
318#define UART_EXTINP_IR_RI 0
319#define UART_EXTINP_IR_CTS 1
320#define UART_EXTINP_IR_DCD 2
321#define UART_EXTINP_IR_DSR 3
322#define UART_EXTINP_RI_NOSENSE_SHIFT 16
323#define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
324#define UART_EXTINP_CTS_NOSENSE_SHIFT 17
325#define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
326#define UART_EXTINP_DCD_NOSENSE_SHIFT 18
327#define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
328#define UART_EXTINP_DSR_NOSENSE_SHIFT 19
329#define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
330
331/* UART Interrupt register */
332#define UART_IR_REG 0x10
333#define UART_IR_MASK(x) (1 << (x + 16))
334#define UART_IR_STAT(x) (1 << (x))
335#define UART_IR_EXTIP 0
336#define UART_IR_TXUNDER 1
337#define UART_IR_TXOVER 2
338#define UART_IR_TXTRESH 3
339#define UART_IR_TXRDLATCH 4
340#define UART_IR_TXEMPTY 5
341#define UART_IR_RXUNDER 6
342#define UART_IR_RXOVER 7
343#define UART_IR_RXTIMEOUT 8
344#define UART_IR_RXFULL 9
345#define UART_IR_RXTHRESH 10
346#define UART_IR_RXNOTEMPTY 11
347#define UART_IR_RXFRAMEERR 12
348#define UART_IR_RXPARERR 13
349#define UART_IR_RXBRK 14
350#define UART_IR_TXDONE 15
351
352/* UART Fifo register */
353#define UART_FIFO_REG 0x14
354#define UART_FIFO_VALID_SHIFT 0
355#define UART_FIFO_VALID_MASK 0xff
356#define UART_FIFO_FRAMEERR_SHIFT 8
357#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
358#define UART_FIFO_PARERR_SHIFT 9
359#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
360#define UART_FIFO_BRKDET_SHIFT 10
361#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
362#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
363 UART_FIFO_PARERR_MASK | \
364 UART_FIFO_BRKDET_MASK)
365
366
367/*************************************************************************
368 * _REG relative to RSET_GPIO
369 *************************************************************************/
370
371/* GPIO registers */
372#define GPIO_CTL_HI_REG 0x0
373#define GPIO_CTL_LO_REG 0x4
374#define GPIO_DATA_HI_REG 0x8
375#define GPIO_DATA_LO_REG 0xC
376
377/* GPIO mux registers and constants */
378#define GPIO_MODE_REG 0x18
379
380#define GPIO_MODE_6348_G4_DIAG 0x00090000
381#define GPIO_MODE_6348_G4_UTOPIA 0x00080000
382#define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000
383#define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000
384#define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000
385#define GPIO_MODE_6348_G3_DIAG 0x00009000
386#define GPIO_MODE_6348_G3_UTOPIA 0x00008000
387#define GPIO_MODE_6348_G3_EXT_MII 0x00007000
388#define GPIO_MODE_6348_G2_DIAG 0x00000900
389#define GPIO_MODE_6348_G2_PCI 0x00000500
390#define GPIO_MODE_6348_G1_DIAG 0x00000090
391#define GPIO_MODE_6348_G1_UTOPIA 0x00000080
392#define GPIO_MODE_6348_G1_SPI_UART 0x00000060
393#define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060
394#define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040
395#define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020
396#define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010
397#define GPIO_MODE_6348_G0_DIAG 0x00000009
398#define GPIO_MODE_6348_G0_EXT_MII 0x00000007
399
400#define GPIO_MODE_6358_EXTRACS (1 << 5)
401#define GPIO_MODE_6358_UART1 (1 << 6)
402#define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
403#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
404#define GPIO_MODE_6358_UTOPIA (1 << 12)
405
406
407/*************************************************************************
408 * _REG relative to RSET_ENET
409 *************************************************************************/
410
411/* Receiver Configuration register */
412#define ENET_RXCFG_REG 0x0
413#define ENET_RXCFG_ALLMCAST_SHIFT 1
414#define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT)
415#define ENET_RXCFG_PROMISC_SHIFT 3
416#define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT)
417#define ENET_RXCFG_LOOPBACK_SHIFT 4
418#define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT)
419#define ENET_RXCFG_ENFLOW_SHIFT 5
420#define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT)
421
422/* Receive Maximum Length register */
423#define ENET_RXMAXLEN_REG 0x4
424#define ENET_RXMAXLEN_SHIFT 0
425#define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT)
426
427/* Transmit Maximum Length register */
428#define ENET_TXMAXLEN_REG 0x8
429#define ENET_TXMAXLEN_SHIFT 0
430#define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT)
431
432/* MII Status/Control register */
433#define ENET_MIISC_REG 0x10
434#define ENET_MIISC_MDCFREQDIV_SHIFT 0
435#define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
436#define ENET_MIISC_PREAMBLEEN_SHIFT 7
437#define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
438
439/* MII Data register */
440#define ENET_MIIDATA_REG 0x14
441#define ENET_MIIDATA_DATA_SHIFT 0
442#define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT)
443#define ENET_MIIDATA_TA_SHIFT 16
444#define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT)
445#define ENET_MIIDATA_REG_SHIFT 18
446#define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT)
447#define ENET_MIIDATA_PHYID_SHIFT 23
448#define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT)
449#define ENET_MIIDATA_OP_READ_MASK (0x6 << 28)
450#define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28)
451
452/* Ethernet Interrupt Mask register */
453#define ENET_IRMASK_REG 0x18
454
455/* Ethernet Interrupt register */
456#define ENET_IR_REG 0x1c
457#define ENET_IR_MII (1 << 0)
458#define ENET_IR_MIB (1 << 1)
459#define ENET_IR_FLOWC (1 << 2)
460
461/* Ethernet Control register */
462#define ENET_CTL_REG 0x2c
463#define ENET_CTL_ENABLE_SHIFT 0
464#define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT)
465#define ENET_CTL_DISABLE_SHIFT 1
466#define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT)
467#define ENET_CTL_SRESET_SHIFT 2
468#define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT)
469#define ENET_CTL_EPHYSEL_SHIFT 3
470#define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT)
471
472/* Transmit Control register */
473#define ENET_TXCTL_REG 0x30
474#define ENET_TXCTL_FD_SHIFT 0
475#define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT)
476
477/* Transmit Watermask register */
478#define ENET_TXWMARK_REG 0x34
479#define ENET_TXWMARK_WM_SHIFT 0
480#define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT)
481
482/* MIB Control register */
483#define ENET_MIBCTL_REG 0x38
484#define ENET_MIBCTL_RDCLEAR_SHIFT 0
485#define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
486
487/* Perfect Match Data Low register */
488#define ENET_PML_REG(x) (0x58 + (x) * 8)
489#define ENET_PMH_REG(x) (0x5c + (x) * 8)
490#define ENET_PMH_DATAVALID_SHIFT 16
491#define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT)
492
493/* MIB register */
494#define ENET_MIB_REG(x) (0x200 + (x) * 4)
495#define ENET_MIB_REG_COUNT 55
496
497
498/*************************************************************************
499 * _REG relative to RSET_ENETDMA
500 *************************************************************************/
501
502/* Controller Configuration Register */
503#define ENETDMA_CFG_REG (0x0)
504#define ENETDMA_CFG_EN_SHIFT 0
505#define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT)
506#define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
507
508/* Flow Control Descriptor Low Threshold register */
509#define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6)
510
511/* Flow Control Descriptor High Threshold register */
512#define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6)
513
514/* Flow Control Descriptor Buffer Alloca Threshold register */
515#define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6)
516#define ENETDMA_BUFALLOC_FORCE_SHIFT 31
517#define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
518
519/* Channel Configuration register */
520#define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
521#define ENETDMA_CHANCFG_EN_SHIFT 0
522#define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
523#define ENETDMA_CHANCFG_PKTHALT_SHIFT 1
524#define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
525
526/* Interrupt Control/Status register */
527#define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10)
528#define ENETDMA_IR_BUFDONE_MASK (1 << 0)
529#define ENETDMA_IR_PKTDONE_MASK (1 << 1)
530#define ENETDMA_IR_NOTOWNER_MASK (1 << 2)
531
532/* Interrupt Mask register */
533#define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10)
534
535/* Maximum Burst Length */
536#define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10)
537
538/* Ring Start Address register */
539#define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10)
540
541/* State Ram Word 2 */
542#define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10)
543
544/* State Ram Word 3 */
545#define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10)
546
547/* State Ram Word 4 */
548#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
549
550
551/*************************************************************************
552 * _REG relative to RSET_OHCI_PRIV
553 *************************************************************************/
554
555#define OHCI_PRIV_REG 0x0
556#define OHCI_PRIV_PORT1_HOST_SHIFT 0
557#define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
558#define OHCI_PRIV_REG_SWAP_SHIFT 3
559#define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT)
560
561
562/*************************************************************************
563 * _REG relative to RSET_USBH_PRIV
564 *************************************************************************/
565
566#define USBH_PRIV_SWAP_REG 0x0
567#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
568#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
569#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
570#define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
571#define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1
572#define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
573#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
574#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
575
576#define USBH_PRIV_TEST_REG 0x24
577
578
579/*************************************************************************
580 * _REG relative to RSET_MPI
581 *************************************************************************/
582
583/* well known (hard wired) chip select */
584#define MPI_CS_PCMCIA_COMMON 4
585#define MPI_CS_PCMCIA_ATTR 5
586#define MPI_CS_PCMCIA_IO 6
587
588/* Chip select base register */
589#define MPI_CSBASE_REG(x) (0x0 + (x) * 8)
590#define MPI_CSBASE_BASE_SHIFT 13
591#define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT)
592#define MPI_CSBASE_SIZE_SHIFT 0
593#define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT)
594
595#define MPI_CSBASE_SIZE_8K 0
596#define MPI_CSBASE_SIZE_16K 1
597#define MPI_CSBASE_SIZE_32K 2
598#define MPI_CSBASE_SIZE_64K 3
599#define MPI_CSBASE_SIZE_128K 4
600#define MPI_CSBASE_SIZE_256K 5
601#define MPI_CSBASE_SIZE_512K 6
602#define MPI_CSBASE_SIZE_1M 7
603#define MPI_CSBASE_SIZE_2M 8
604#define MPI_CSBASE_SIZE_4M 9
605#define MPI_CSBASE_SIZE_8M 10
606#define MPI_CSBASE_SIZE_16M 11
607#define MPI_CSBASE_SIZE_32M 12
608#define MPI_CSBASE_SIZE_64M 13
609#define MPI_CSBASE_SIZE_128M 14
610#define MPI_CSBASE_SIZE_256M 15
611
612/* Chip select control register */
613#define MPI_CSCTL_REG(x) (0x4 + (x) * 8)
614#define MPI_CSCTL_ENABLE_MASK (1 << 0)
615#define MPI_CSCTL_WAIT_SHIFT 1
616#define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT)
617#define MPI_CSCTL_DATA16_MASK (1 << 4)
618#define MPI_CSCTL_SYNCMODE_MASK (1 << 7)
619#define MPI_CSCTL_TSIZE_MASK (1 << 8)
620#define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10)
621#define MPI_CSCTL_SETUP_SHIFT 16
622#define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT)
623#define MPI_CSCTL_HOLD_SHIFT 20
624#define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT)
625
626/* PCI registers */
627#define MPI_SP0_RANGE_REG 0x100
628#define MPI_SP0_REMAP_REG 0x104
629#define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
630#define MPI_SP1_RANGE_REG 0x10C
631#define MPI_SP1_REMAP_REG 0x110
632#define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
633
634#define MPI_L2PCFG_REG 0x11C
635#define MPI_L2PCFG_CFG_TYPE_SHIFT 0
636#define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
637#define MPI_L2PCFG_REG_SHIFT 2
638#define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
639#define MPI_L2PCFG_FUNC_SHIFT 8
640#define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
641#define MPI_L2PCFG_DEVNUM_SHIFT 11
642#define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
643#define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
644#define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
645
646#define MPI_L2PMEMRANGE1_REG 0x120
647#define MPI_L2PMEMBASE1_REG 0x124
648#define MPI_L2PMEMREMAP1_REG 0x128
649#define MPI_L2PMEMRANGE2_REG 0x12C
650#define MPI_L2PMEMBASE2_REG 0x130
651#define MPI_L2PMEMREMAP2_REG 0x134
652#define MPI_L2PIORANGE_REG 0x138
653#define MPI_L2PIOBASE_REG 0x13C
654#define MPI_L2PIOREMAP_REG 0x140
655#define MPI_L2P_BASE_MASK (0xffff8000)
656#define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
657#define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
658
659#define MPI_PCIMODESEL_REG 0x144
660#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
661#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
662#define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
663#define MPI_PCIMODESEL_PREFETCH_SHIFT 4
664#define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
665
666#define MPI_LOCBUSCTL_REG 0x14C
667#define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
668#define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
669
670#define MPI_LOCINT_REG 0x150
671#define MPI_LOCINT_MASK(x) (1 << (x + 16))
672#define MPI_LOCINT_STAT(x) (1 << (x))
673#define MPI_LOCINT_DIR_FAILED 6
674#define MPI_LOCINT_EXT_PCI_INT 7
675#define MPI_LOCINT_SERR 8
676#define MPI_LOCINT_CSERR 9
677
678#define MPI_PCICFGCTL_REG 0x178
679#define MPI_PCICFGCTL_CFGADDR_SHIFT 2
680#define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
681#define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
682
683#define MPI_PCICFGDATA_REG 0x17C
684
685/* PCI host bridge custom register */
686#define BCMPCI_REG_TIMERS 0x40
687#define REG_TIMER_TRDY_SHIFT 0
688#define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
689#define REG_TIMER_RETRY_SHIFT 8
690#define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
691
692
693/*************************************************************************
694 * _REG relative to RSET_PCMCIA
695 *************************************************************************/
696
697#define PCMCIA_C1_REG 0x0
698#define PCMCIA_C1_CD1_MASK (1 << 0)
699#define PCMCIA_C1_CD2_MASK (1 << 1)
700#define PCMCIA_C1_VS1_MASK (1 << 2)
701#define PCMCIA_C1_VS2_MASK (1 << 3)
702#define PCMCIA_C1_VS1OE_MASK (1 << 6)
703#define PCMCIA_C1_VS2OE_MASK (1 << 7)
704#define PCMCIA_C1_CBIDSEL_SHIFT (8)
705#define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
706#define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
707#define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
708#define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
709#define PCMCIA_C1_RESET_MASK (1 << 18)
710
711#define PCMCIA_C2_REG 0x8
712#define PCMCIA_C2_DATA16_MASK (1 << 0)
713#define PCMCIA_C2_BYTESWAP_MASK (1 << 1)
714#define PCMCIA_C2_RWCOUNT_SHIFT 2
715#define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
716#define PCMCIA_C2_INACTIVE_SHIFT 8
717#define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
718#define PCMCIA_C2_SETUP_SHIFT 16
719#define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT)
720#define PCMCIA_C2_HOLD_SHIFT 24
721#define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT)
722
723
724/*************************************************************************
725 * _REG relative to RSET_SDRAM
726 *************************************************************************/
727
728#define SDRAM_CFG_REG 0x0
729#define SDRAM_CFG_ROW_SHIFT 4
730#define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
731#define SDRAM_CFG_COL_SHIFT 6
732#define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
733#define SDRAM_CFG_32B_SHIFT 10
734#define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
735#define SDRAM_CFG_BANK_SHIFT 13
736#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
737
738#define SDRAM_PRIO_REG 0x2C
739#define SDRAM_PRIO_MIPS_SHIFT 29
740#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
741#define SDRAM_PRIO_ADSL_SHIFT 30
742#define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT)
743#define SDRAM_PRIO_EN_SHIFT 31
744#define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT)
745
746
747/*************************************************************************
748 * _REG relative to RSET_MEMC
749 *************************************************************************/
750
751#define MEMC_CFG_REG 0x4
752#define MEMC_CFG_32B_SHIFT 1
753#define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
754#define MEMC_CFG_COL_SHIFT 3
755#define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
756#define MEMC_CFG_ROW_SHIFT 6
757#define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
758
759
760/*************************************************************************
761 * _REG relative to RSET_DDR
762 *************************************************************************/
763
764#define DDR_DMIPSPLLCFG_REG 0x18
765#define DMIPSPLLCFG_M1_SHIFT 0
766#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
767#define DMIPSPLLCFG_N1_SHIFT 23
768#define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT)
769#define DMIPSPLLCFG_N2_SHIFT 29
770#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
771
772#endif /* BCM63XX_REGS_H_ */
773
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h
new file mode 100644
index 000000000000..c0fce833c9ed
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h
@@ -0,0 +1,11 @@
1#ifndef BCM63XX_TIMER_H_
2#define BCM63XX_TIMER_H_
3
4int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data);
5void bcm63xx_timer_unregister(int id);
6int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us);
7int bcm63xx_timer_enable(int id);
8int bcm63xx_timer_disable(int id);
9unsigned int bcm63xx_timer_countdown(unsigned int countdown_us);
10
11#endif /* !BCM63XX_TIMER_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
new file mode 100644
index 000000000000..6479090a4106
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -0,0 +1,60 @@
1#ifndef BOARD_BCM963XX_H_
2#define BOARD_BCM963XX_H_
3
4#include <linux/types.h>
5#include <linux/gpio.h>
6#include <linux/leds.h>
7#include <bcm63xx_dev_enet.h>
8#include <bcm63xx_dev_dsp.h>
9
10/*
11 * flash mapping
12 */
13#define BCM963XX_CFE_VERSION_OFFSET 0x570
14#define BCM963XX_NVRAM_OFFSET 0x580
15
16/*
17 * nvram structure
18 */
19struct bcm963xx_nvram {
20 u32 version;
21 u8 reserved1[256];
22 u8 name[16];
23 u32 main_tp_number;
24 u32 psi_size;
25 u32 mac_addr_count;
26 u8 mac_addr_base[6];
27 u8 reserved2[2];
28 u32 checksum_old;
29 u8 reserved3[720];
30 u32 checksum_high;
31};
32
33/*
34 * board definition
35 */
36struct board_info {
37 u8 name[16];
38 unsigned int expected_cpu_id;
39
40 /* enabled feature/device */
41 unsigned int has_enet0:1;
42 unsigned int has_enet1:1;
43 unsigned int has_pci:1;
44 unsigned int has_pccard:1;
45 unsigned int has_ohci0:1;
46 unsigned int has_ehci0:1;
47 unsigned int has_dsp:1;
48
49 /* ethernet config */
50 struct bcm63xx_enet_platform_data enet0;
51 struct bcm63xx_enet_platform_data enet1;
52
53 /* DSP config */
54 struct bcm63xx_dsp_platform_data dsp;
55
56 /* GPIO LEDs */
57 struct gpio_led leds[5];
58};
59
60#endif /* ! BOARD_BCM963XX_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
new file mode 100644
index 000000000000..71742bac940d
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
@@ -0,0 +1,51 @@
1#ifndef __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
2#define __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
3
4#include <bcm63xx_cpu.h>
5
6#define cpu_has_tlb 1
7#define cpu_has_4kex 1
8#define cpu_has_4k_cache 1
9#define cpu_has_fpu 0
10#define cpu_has_32fpr 0
11#define cpu_has_counter 1
12#define cpu_has_watch 0
13#define cpu_has_divec 1
14#define cpu_has_vce 0
15#define cpu_has_cache_cdex_p 0
16#define cpu_has_cache_cdex_s 0
17#define cpu_has_prefetch 1
18#define cpu_has_mcheck 1
19#define cpu_has_ejtag 1
20#define cpu_has_llsc 1
21#define cpu_has_mips16 0
22#define cpu_has_mdmx 0
23#define cpu_has_mips3d 0
24#define cpu_has_smartmips 0
25#define cpu_has_vtag_icache 0
26
27#if !defined(BCMCPU_RUNTIME_DETECT) && (defined(CONFIG_BCMCPU_IS_6348) || defined(CONFIG_CPU_IS_6338) || defined(CONFIG_CPU_IS_BCM6345))
28#define cpu_has_dc_aliases 0
29#endif
30
31#define cpu_has_ic_fills_f_dc 0
32#define cpu_has_pindexed_dcache 0
33
34#define cpu_has_mips32r1 1
35#define cpu_has_mips32r2 0
36#define cpu_has_mips64r1 0
37#define cpu_has_mips64r2 0
38
39#define cpu_has_dsp 0
40#define cpu_has_mipsmt 0
41#define cpu_has_userlocal 0
42
43#define cpu_has_nofpuex 0
44#define cpu_has_64bits 0
45#define cpu_has_64bit_zero_reg 0
46
47#define cpu_dcache_line_size() 16
48#define cpu_icache_line_size() 16
49#define cpu_scache_line_size() 0
50
51#endif /* __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/gpio.h b/arch/mips/include/asm/mach-bcm63xx/gpio.h
new file mode 100644
index 000000000000..7cda8c0a3979
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/gpio.h
@@ -0,0 +1,15 @@
1#ifndef __ASM_MIPS_MACH_BCM63XX_GPIO_H
2#define __ASM_MIPS_MACH_BCM63XX_GPIO_H
3
4#include <bcm63xx_gpio.h>
5
6#define gpio_to_irq(gpio) NULL
7
8#define gpio_get_value __gpio_get_value
9#define gpio_set_value __gpio_set_value
10
11#define gpio_cansleep __gpio_cansleep
12
13#include <asm-generic/gpio.h>
14
15#endif /* __ASM_MIPS_MACH_BCM63XX_GPIO_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/war.h b/arch/mips/include/asm/mach-bcm63xx/war.h
new file mode 100644
index 000000000000..8e3f3fdf3209
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_BCM63XX_WAR_H
9#define __ASM_MIPS_MACH_BCM63XX_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_BCM63XX_WAR_H */
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 0d4d5ea6fac3..91bfe73a7f60 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -16,6 +16,8 @@ obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
16obj-$(CONFIG_NEC_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o 16obj-$(CONFIG_NEC_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
17obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o 17obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
18obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o 18obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
19obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
20 ops-bcm63xx.o
19 21
20# 22#
21# These are still pretty much in the old state, watch, go blind. 23# These are still pretty much in the old state, watch, go blind.
diff --git a/arch/mips/pci/fixup-bcm63xx.c b/arch/mips/pci/fixup-bcm63xx.c
new file mode 100644
index 000000000000..340863009da9
--- /dev/null
+++ b/arch/mips/pci/fixup-bcm63xx.c
@@ -0,0 +1,21 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <bcm63xx_cpu.h>
12
13int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
14{
15 return bcm63xx_get_irq_number(IRQ_PCI);
16}
17
18int pcibios_plat_dev_init(struct pci_dev *dev)
19{
20 return 0;
21}
diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c
new file mode 100644
index 000000000000..822ae179bc56
--- /dev/null
+++ b/arch/mips/pci/ops-bcm63xx.c
@@ -0,0 +1,467 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/io.h>
15
16#include "pci-bcm63xx.h"
17
18/*
19 * swizzle 32bits data to return only the needed part
20 */
21static int postprocess_read(u32 data, int where, unsigned int size)
22{
23 u32 ret;
24
25 ret = 0;
26 switch (size) {
27 case 1:
28 ret = (data >> ((where & 3) << 3)) & 0xff;
29 break;
30 case 2:
31 ret = (data >> ((where & 3) << 3)) & 0xffff;
32 break;
33 case 4:
34 ret = data;
35 break;
36 }
37 return ret;
38}
39
40static int preprocess_write(u32 orig_data, u32 val, int where,
41 unsigned int size)
42{
43 u32 ret;
44
45 ret = 0;
46 switch (size) {
47 case 1:
48 ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
49 (val << ((where & 3) << 3));
50 break;
51 case 2:
52 ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
53 (val << ((where & 3) << 3));
54 break;
55 case 4:
56 ret = val;
57 break;
58 }
59 return ret;
60}
61
62/*
63 * setup hardware for a configuration cycle with given parameters
64 */
65static int bcm63xx_setup_cfg_access(int type, unsigned int busn,
66 unsigned int devfn, int where)
67{
68 unsigned int slot, func, reg;
69 u32 val;
70
71 slot = PCI_SLOT(devfn);
72 func = PCI_FUNC(devfn);
73 reg = where >> 2;
74
75 /* sanity check */
76 if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
77 return 1;
78
79 if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
80 return 1;
81
82 if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
83 return 1;
84
85 /* ok, setup config access */
86 val = (reg << MPI_L2PCFG_REG_SHIFT);
87 val |= (func << MPI_L2PCFG_FUNC_SHIFT);
88 val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
89 val |= MPI_L2PCFG_CFG_USEREG_MASK;
90 val |= MPI_L2PCFG_CFG_SEL_MASK;
91 /* type 0 cycle for local bus, type 1 cycle for anything else */
92 if (type != 0) {
93 /* FIXME: how to specify bus ??? */
94 val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
95 }
96 bcm_mpi_writel(val, MPI_L2PCFG_REG);
97
98 return 0;
99}
100
101static int bcm63xx_do_cfg_read(int type, unsigned int busn,
102 unsigned int devfn, int where, int size,
103 u32 *val)
104{
105 u32 data;
106
107 /* two phase cycle, first we write address, then read data at
108 * another location, caller already has a spinlock so no need
109 * to add one here */
110 if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
111 return PCIBIOS_DEVICE_NOT_FOUND;
112 iob();
113 data = le32_to_cpu(__raw_readl(pci_iospace_start));
114 /* restore IO space normal behaviour */
115 bcm_mpi_writel(0, MPI_L2PCFG_REG);
116
117 *val = postprocess_read(data, where, size);
118
119 return PCIBIOS_SUCCESSFUL;
120}
121
122static int bcm63xx_do_cfg_write(int type, unsigned int busn,
123 unsigned int devfn, int where, int size,
124 u32 val)
125{
126 u32 data;
127
128 /* two phase cycle, first we write address, then write data to
129 * another location, caller already has a spinlock so no need
130 * to add one here */
131 if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
132 return PCIBIOS_DEVICE_NOT_FOUND;
133 iob();
134
135 data = le32_to_cpu(__raw_readl(pci_iospace_start));
136 data = preprocess_write(data, val, where, size);
137
138 __raw_writel(cpu_to_le32(data), pci_iospace_start);
139 wmb();
140 /* no way to know the access is done, we have to wait */
141 udelay(500);
142 /* restore IO space normal behaviour */
143 bcm_mpi_writel(0, MPI_L2PCFG_REG);
144
145 return PCIBIOS_SUCCESSFUL;
146}
147
148static int bcm63xx_pci_read(struct pci_bus *bus, unsigned int devfn,
149 int where, int size, u32 *val)
150{
151 int type;
152
153 type = bus->parent ? 1 : 0;
154
155 if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
156 return PCIBIOS_DEVICE_NOT_FOUND;
157
158 return bcm63xx_do_cfg_read(type, bus->number, devfn,
159 where, size, val);
160}
161
162static int bcm63xx_pci_write(struct pci_bus *bus, unsigned int devfn,
163 int where, int size, u32 val)
164{
165 int type;
166
167 type = bus->parent ? 1 : 0;
168
169 if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
170 return PCIBIOS_DEVICE_NOT_FOUND;
171
172 return bcm63xx_do_cfg_write(type, bus->number, devfn,
173 where, size, val);
174}
175
176struct pci_ops bcm63xx_pci_ops = {
177 .read = bcm63xx_pci_read,
178 .write = bcm63xx_pci_write
179};
180
181#ifdef CONFIG_CARDBUS
182/*
183 * emulate configuration read access on a cardbus bridge
184 */
185#define FAKE_CB_BRIDGE_SLOT 0x1e
186
187static int fake_cb_bridge_bus_number = -1;
188
189static struct {
190 u16 pci_command;
191 u8 cb_latency;
192 u8 subordinate_busn;
193 u8 cardbus_busn;
194 u8 pci_busn;
195 int bus_assigned;
196 u16 bridge_control;
197
198 u32 mem_base0;
199 u32 mem_limit0;
200 u32 mem_base1;
201 u32 mem_limit1;
202
203 u32 io_base0;
204 u32 io_limit0;
205 u32 io_base1;
206 u32 io_limit1;
207} fake_cb_bridge_regs;
208
209static int fake_cb_bridge_read(int where, int size, u32 *val)
210{
211 unsigned int reg;
212 u32 data;
213
214 data = 0;
215 reg = where >> 2;
216 switch (reg) {
217 case (PCI_VENDOR_ID >> 2):
218 case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2):
219 /* create dummy vendor/device id from our cpu id */
220 data = (bcm63xx_get_cpu_id() << 16) | PCI_VENDOR_ID_BROADCOM;
221 break;
222
223 case (PCI_COMMAND >> 2):
224 data = (PCI_STATUS_DEVSEL_SLOW << 16);
225 data |= fake_cb_bridge_regs.pci_command;
226 break;
227
228 case (PCI_CLASS_REVISION >> 2):
229 data = (PCI_CLASS_BRIDGE_CARDBUS << 16);
230 break;
231
232 case (PCI_CACHE_LINE_SIZE >> 2):
233 data = (PCI_HEADER_TYPE_CARDBUS << 16);
234 break;
235
236 case (PCI_INTERRUPT_LINE >> 2):
237 /* bridge control */
238 data = (fake_cb_bridge_regs.bridge_control << 16);
239 /* pin:intA line:0xff */
240 data |= (0x1 << 8) | 0xff;
241 break;
242
243 case (PCI_CB_PRIMARY_BUS >> 2):
244 data = (fake_cb_bridge_regs.cb_latency << 24);
245 data |= (fake_cb_bridge_regs.subordinate_busn << 16);
246 data |= (fake_cb_bridge_regs.cardbus_busn << 8);
247 data |= fake_cb_bridge_regs.pci_busn;
248 break;
249
250 case (PCI_CB_MEMORY_BASE_0 >> 2):
251 data = fake_cb_bridge_regs.mem_base0;
252 break;
253
254 case (PCI_CB_MEMORY_LIMIT_0 >> 2):
255 data = fake_cb_bridge_regs.mem_limit0;
256 break;
257
258 case (PCI_CB_MEMORY_BASE_1 >> 2):
259 data = fake_cb_bridge_regs.mem_base1;
260 break;
261
262 case (PCI_CB_MEMORY_LIMIT_1 >> 2):
263 data = fake_cb_bridge_regs.mem_limit1;
264 break;
265
266 case (PCI_CB_IO_BASE_0 >> 2):
267 /* | 1 for 32bits io support */
268 data = fake_cb_bridge_regs.io_base0 | 0x1;
269 break;
270
271 case (PCI_CB_IO_LIMIT_0 >> 2):
272 data = fake_cb_bridge_regs.io_limit0;
273 break;
274
275 case (PCI_CB_IO_BASE_1 >> 2):
276 /* | 1 for 32bits io support */
277 data = fake_cb_bridge_regs.io_base1 | 0x1;
278 break;
279
280 case (PCI_CB_IO_LIMIT_1 >> 2):
281 data = fake_cb_bridge_regs.io_limit1;
282 break;
283 }
284
285 *val = postprocess_read(data, where, size);
286 return PCIBIOS_SUCCESSFUL;
287}
288
289/*
290 * emulate configuration write access on a cardbus bridge
291 */
292static int fake_cb_bridge_write(int where, int size, u32 val)
293{
294 unsigned int reg;
295 u32 data, tmp;
296 int ret;
297
298 ret = fake_cb_bridge_read((where & ~0x3), 4, &data);
299 if (ret != PCIBIOS_SUCCESSFUL)
300 return ret;
301
302 data = preprocess_write(data, val, where, size);
303
304 reg = where >> 2;
305 switch (reg) {
306 case (PCI_COMMAND >> 2):
307 fake_cb_bridge_regs.pci_command = (data & 0xffff);
308 break;
309
310 case (PCI_CB_PRIMARY_BUS >> 2):
311 fake_cb_bridge_regs.cb_latency = (data >> 24) & 0xff;
312 fake_cb_bridge_regs.subordinate_busn = (data >> 16) & 0xff;
313 fake_cb_bridge_regs.cardbus_busn = (data >> 8) & 0xff;
314 fake_cb_bridge_regs.pci_busn = data & 0xff;
315 if (fake_cb_bridge_regs.cardbus_busn)
316 fake_cb_bridge_regs.bus_assigned = 1;
317 break;
318
319 case (PCI_INTERRUPT_LINE >> 2):
320 tmp = (data >> 16) & 0xffff;
321 /* disable memory prefetch support */
322 tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
323 tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
324 fake_cb_bridge_regs.bridge_control = tmp;
325 break;
326
327 case (PCI_CB_MEMORY_BASE_0 >> 2):
328 fake_cb_bridge_regs.mem_base0 = data;
329 break;
330
331 case (PCI_CB_MEMORY_LIMIT_0 >> 2):
332 fake_cb_bridge_regs.mem_limit0 = data;
333 break;
334
335 case (PCI_CB_MEMORY_BASE_1 >> 2):
336 fake_cb_bridge_regs.mem_base1 = data;
337 break;
338
339 case (PCI_CB_MEMORY_LIMIT_1 >> 2):
340 fake_cb_bridge_regs.mem_limit1 = data;
341 break;
342
343 case (PCI_CB_IO_BASE_0 >> 2):
344 fake_cb_bridge_regs.io_base0 = data;
345 break;
346
347 case (PCI_CB_IO_LIMIT_0 >> 2):
348 fake_cb_bridge_regs.io_limit0 = data;
349 break;
350
351 case (PCI_CB_IO_BASE_1 >> 2):
352 fake_cb_bridge_regs.io_base1 = data;
353 break;
354
355 case (PCI_CB_IO_LIMIT_1 >> 2):
356 fake_cb_bridge_regs.io_limit1 = data;
357 break;
358 }
359
360 return PCIBIOS_SUCCESSFUL;
361}
362
363static int bcm63xx_cb_read(struct pci_bus *bus, unsigned int devfn,
364 int where, int size, u32 *val)
365{
366 /* snoop access to slot 0x1e on root bus, we fake a cardbus
367 * bridge at this location */
368 if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
369 fake_cb_bridge_bus_number = bus->number;
370 return fake_cb_bridge_read(where, size, val);
371 }
372
373 /* a configuration cycle for the device behind the cardbus
374 * bridge is actually done as a type 0 cycle on the primary
375 * bus. This means that only one device can be on the cardbus
376 * bus */
377 if (fake_cb_bridge_regs.bus_assigned &&
378 bus->number == fake_cb_bridge_regs.cardbus_busn &&
379 PCI_SLOT(devfn) == 0)
380 return bcm63xx_do_cfg_read(0, 0,
381 PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
382 where, size, val);
383
384 return PCIBIOS_DEVICE_NOT_FOUND;
385}
386
387static int bcm63xx_cb_write(struct pci_bus *bus, unsigned int devfn,
388 int where, int size, u32 val)
389{
390 if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
391 fake_cb_bridge_bus_number = bus->number;
392 return fake_cb_bridge_write(where, size, val);
393 }
394
395 if (fake_cb_bridge_regs.bus_assigned &&
396 bus->number == fake_cb_bridge_regs.cardbus_busn &&
397 PCI_SLOT(devfn) == 0)
398 return bcm63xx_do_cfg_write(0, 0,
399 PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
400 where, size, val);
401
402 return PCIBIOS_DEVICE_NOT_FOUND;
403}
404
405struct pci_ops bcm63xx_cb_ops = {
406 .read = bcm63xx_cb_read,
407 .write = bcm63xx_cb_write,
408};
409
410/*
411 * only one IO window, so it cannot be shared by PCI and cardbus, use
412 * fixup to choose and detect unhandled configuration
413 */
414static void bcm63xx_fixup(struct pci_dev *dev)
415{
416 static int io_window = -1;
417 int i, found, new_io_window;
418 u32 val;
419
420 /* look for any io resource */
421 found = 0;
422 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
423 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
424 found = 1;
425 break;
426 }
427 }
428
429 if (!found)
430 return;
431
432 /* skip our fake bus with only cardbus bridge on it */
433 if (dev->bus->number == fake_cb_bridge_bus_number)
434 return;
435
436 /* find on which bus the device is */
437 if (fake_cb_bridge_regs.bus_assigned &&
438 dev->bus->number == fake_cb_bridge_regs.cardbus_busn &&
439 PCI_SLOT(dev->devfn) == 0)
440 new_io_window = 1;
441 else
442 new_io_window = 0;
443
444 if (new_io_window == io_window)
445 return;
446
447 if (io_window != -1) {
448 printk(KERN_ERR "bcm63xx: both PCI and cardbus devices "
449 "need IO, which hardware cannot do\n");
450 return;
451 }
452
453 printk(KERN_INFO "bcm63xx: PCI IO window assigned to %s\n",
454 (new_io_window == 0) ? "PCI" : "cardbus");
455
456 val = bcm_mpi_readl(MPI_L2PIOREMAP_REG);
457 if (io_window)
458 val |= MPI_L2PREMAP_IS_CARDBUS_MASK;
459 else
460 val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK;
461 bcm_mpi_writel(val, MPI_L2PIOREMAP_REG);
462
463 io_window = new_io_window;
464}
465
466DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
467#endif
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
new file mode 100644
index 000000000000..82e0fde1dba0
--- /dev/null
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -0,0 +1,224 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <asm/bootinfo.h>
14
15#include "pci-bcm63xx.h"
16
17/*
18 * Allow PCI to be disabled at runtime depending on board nvram
19 * configuration
20 */
21int bcm63xx_pci_enabled;
22
23static struct resource bcm_pci_mem_resource = {
24 .name = "bcm63xx PCI memory space",
25 .start = BCM_PCI_MEM_BASE_PA,
26 .end = BCM_PCI_MEM_END_PA,
27 .flags = IORESOURCE_MEM
28};
29
30static struct resource bcm_pci_io_resource = {
31 .name = "bcm63xx PCI IO space",
32 .start = BCM_PCI_IO_BASE_PA,
33#ifdef CONFIG_CARDBUS
34 .end = BCM_PCI_IO_HALF_PA,
35#else
36 .end = BCM_PCI_IO_END_PA,
37#endif
38 .flags = IORESOURCE_IO
39};
40
41struct pci_controller bcm63xx_controller = {
42 .pci_ops = &bcm63xx_pci_ops,
43 .io_resource = &bcm_pci_io_resource,
44 .mem_resource = &bcm_pci_mem_resource,
45};
46
47/*
48 * We handle cardbus via a fake Cardbus bridge, memory and io spaces
49 * have to be clearly separated from PCI one since we have different
50 * memory decoder.
51 */
52#ifdef CONFIG_CARDBUS
53static struct resource bcm_cb_mem_resource = {
54 .name = "bcm63xx Cardbus memory space",
55 .start = BCM_CB_MEM_BASE_PA,
56 .end = BCM_CB_MEM_END_PA,
57 .flags = IORESOURCE_MEM
58};
59
60static struct resource bcm_cb_io_resource = {
61 .name = "bcm63xx Cardbus IO space",
62 .start = BCM_PCI_IO_HALF_PA + 1,
63 .end = BCM_PCI_IO_END_PA,
64 .flags = IORESOURCE_IO
65};
66
67struct pci_controller bcm63xx_cb_controller = {
68 .pci_ops = &bcm63xx_cb_ops,
69 .io_resource = &bcm_cb_io_resource,
70 .mem_resource = &bcm_cb_mem_resource,
71};
72#endif
73
74static u32 bcm63xx_int_cfg_readl(u32 reg)
75{
76 u32 tmp;
77
78 tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
79 tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
80 bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
81 iob();
82 return bcm_mpi_readl(MPI_PCICFGDATA_REG);
83}
84
85static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
86{
87 u32 tmp;
88
89 tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
90 tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
91 bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
92 bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
93}
94
95void __iomem *pci_iospace_start;
96
97static int __init bcm63xx_pci_init(void)
98{
99 unsigned int mem_size;
100 u32 val;
101
102 if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358())
103 return -ENODEV;
104
105 if (!bcm63xx_pci_enabled)
106 return -ENODEV;
107
108 /*
109 * configuration access are done through IO space, remap 4
110 * first bytes to access it from CPU.
111 *
112 * this means that no io access from CPU should happen while
113 * we do a configuration cycle, but there's no way we can add
114 * a spinlock for each io access, so this is currently kind of
115 * broken on SMP.
116 */
117 pci_iospace_start = ioremap_nocache(BCM_PCI_IO_BASE_PA, 4);
118 if (!pci_iospace_start)
119 return -ENOMEM;
120
121 /* setup local bus to PCI access (PCI memory) */
122 val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK;
123 bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG);
124 bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG);
125 bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG);
126
127 /* set Cardbus IDSEL (type 0 cfg access on primary bus for
128 * this IDSEL will be done on Cardbus instead) */
129 val = bcm_pcmcia_readl(PCMCIA_C1_REG);
130 val &= ~PCMCIA_C1_CBIDSEL_MASK;
131 val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
132 bcm_pcmcia_writel(val, PCMCIA_C1_REG);
133
134#ifdef CONFIG_CARDBUS
135 /* setup local bus to PCI access (Cardbus memory) */
136 val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK;
137 bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG);
138 bcm_mpi_writel(~(BCM_CB_MEM_SIZE - 1), MPI_L2PMEMRANGE2_REG);
139 val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
140 bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG);
141#else
142 /* disable second access windows */
143 bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
144#endif
145
146 /* setup local bus to PCI access (IO memory), we have only 1
147 * IO window for both PCI and cardbus, but it cannot handle
148 * both at the same time, assume standard PCI for now, if
149 * cardbus card has IO zone, PCI fixup will change window to
150 * cardbus */
151 val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
152 bcm_mpi_writel(val, MPI_L2PIOBASE_REG);
153 bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG);
154 bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG);
155
156 /* enable PCI related GPIO pins */
157 bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG);
158
159 /* setup PCI to local bus access, used by PCI device to target
160 * local RAM while bus mastering */
161 bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
162 if (BCMCPU_IS_6358())
163 val = MPI_SP0_REMAP_ENABLE_MASK;
164 else
165 val = 0;
166 bcm_mpi_writel(val, MPI_SP0_REMAP_REG);
167
168 bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4);
169 bcm_mpi_writel(0, MPI_SP1_REMAP_REG);
170
171 mem_size = bcm63xx_get_memory_size();
172
173 /* 6348 before rev b0 exposes only 16 MB of RAM memory through
174 * PCI, throw a warning if we have more memory */
175 if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) {
176 if (mem_size > (16 * 1024 * 1024))
177 printk(KERN_WARNING "bcm63xx: this CPU "
178 "revision cannot handle more than 16MB "
179 "of RAM for PCI bus mastering\n");
180 } else {
181 /* setup sp0 range to local RAM size */
182 bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG);
183 bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
184 }
185
186 /* change host bridge retry counter to infinite number of
187 * retry, needed for some broadcom wifi cards with Silicon
188 * Backplane bus where access to srom seems very slow */
189 val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);
190 val &= ~REG_TIMER_RETRY_MASK;
191 bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS);
192
193 /* enable memory decoder and bus mastering */
194 val = bcm63xx_int_cfg_readl(PCI_COMMAND);
195 val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
196 bcm63xx_int_cfg_writel(val, PCI_COMMAND);
197
198 /* enable read prefetching & disable byte swapping for bus
199 * mastering transfers */
200 val = bcm_mpi_readl(MPI_PCIMODESEL_REG);
201 val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
202 val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
203 val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
204 val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
205 bcm_mpi_writel(val, MPI_PCIMODESEL_REG);
206
207 /* enable pci interrupt */
208 val = bcm_mpi_readl(MPI_LOCINT_REG);
209 val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
210 bcm_mpi_writel(val, MPI_LOCINT_REG);
211
212 register_pci_controller(&bcm63xx_controller);
213
214#ifdef CONFIG_CARDBUS
215 register_pci_controller(&bcm63xx_cb_controller);
216#endif
217
218 /* mark memory space used for IO mapping as reserved */
219 request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
220 "bcm63xx PCI IO space");
221 return 0;
222}
223
224arch_initcall(bcm63xx_pci_init);
diff --git a/arch/mips/pci/pci-bcm63xx.h b/arch/mips/pci/pci-bcm63xx.h
new file mode 100644
index 000000000000..a6e594ef3d6a
--- /dev/null
+++ b/arch/mips/pci/pci-bcm63xx.h
@@ -0,0 +1,27 @@
1#ifndef PCI_BCM63XX_H_
2#define PCI_BCM63XX_H_
3
4#include <bcm63xx_cpu.h>
5#include <bcm63xx_io.h>
6#include <bcm63xx_regs.h>
7#include <bcm63xx_dev_pci.h>
8
9/*
10 * Cardbus shares the PCI bus, but has no IDSEL, so a special id is
11 * reserved for it. If you have a standard PCI device at this id, you
12 * need to change the following definition.
13 */
14#define CARDBUS_PCI_IDSEL 0x8
15
16/*
17 * defined in ops-bcm63xx.c
18 */
19extern struct pci_ops bcm63xx_pci_ops;
20extern struct pci_ops bcm63xx_cb_ops;
21
22/*
23 * defined in pci-bcm63xx.c
24 */
25extern void __iomem *pci_iospace_start;
26
27#endif /* ! PCI_BCM63XX_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 22:00:15 -0500