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-rw-r--r--arch/mips/sibyte/bcm1480/irq.c75
-rw-r--r--arch/mips/sibyte/bcm1480/smp.c4
-rw-r--r--arch/mips/sibyte/bcm1480/time.c117
-rw-r--r--arch/mips/sibyte/sb1250/irq.c35
-rw-r--r--arch/mips/sibyte/sb1250/smp.c4
-rw-r--r--arch/mips/sibyte/sb1250/time.c88
-rw-r--r--include/asm-mips/sibyte/sb1250.h2
7 files changed, 158 insertions, 167 deletions
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 7aa79bf63c4a..10299bafeab7 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -452,6 +452,43 @@ static void bcm1480_kgdb_interrupt(void)
452 452
453extern void bcm1480_mailbox_interrupt(void); 453extern void bcm1480_mailbox_interrupt(void);
454 454
455static inline void dispatch_ip4(void)
456{
457 int cpu = smp_processor_id();
458 int irq = K_BCM1480_INT_TIMER_0 + cpu;
459
460 /* Reset the timer */
461 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
462 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
463
464 do_IRQ(irq);
465}
466
467static inline void dispatch_ip2(void)
468{
469 unsigned long long mask_h, mask_l;
470 unsigned int cpu = smp_processor_id();
471 unsigned long base;
472
473 /*
474 * Default...we've hit an IP[2] interrupt, which means we've got to
475 * check the 1480 interrupt registers to figure out what to do. Need
476 * to detect which CPU we're on, now that smp_affinity is supported.
477 */
478 base = A_BCM1480_IMR_MAPPER(cpu);
479 mask_h = __raw_readq(
480 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H));
481 mask_l = __raw_readq(
482 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L));
483
484 if (mask_h) {
485 if (mask_h ^ 1)
486 do_IRQ(fls64(mask_h) - 1);
487 else if (mask_l)
488 do_IRQ(63 + fls64(mask_l));
489 }
490}
491
455asmlinkage void plat_irq_dispatch(void) 492asmlinkage void plat_irq_dispatch(void)
456{ 493{
457 unsigned int pending; 494 unsigned int pending;
@@ -469,17 +506,8 @@ asmlinkage void plat_irq_dispatch(void)
469 else 506 else
470#endif 507#endif
471 508
472 if (pending & CAUSEF_IP4) { 509 if (pending & CAUSEF_IP4)
473 int cpu = smp_processor_id(); 510 dispatch_ip4();
474 int irq = K_BCM1480_INT_TIMER_0 + cpu;
475
476 /* Reset the timer */
477 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
478 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
479
480 do_IRQ(irq);
481 }
482
483#ifdef CONFIG_SMP 511#ifdef CONFIG_SMP
484 else if (pending & CAUSEF_IP3) 512 else if (pending & CAUSEF_IP3)
485 bcm1480_mailbox_interrupt(); 513 bcm1480_mailbox_interrupt();
@@ -490,27 +518,6 @@ asmlinkage void plat_irq_dispatch(void)
490 bcm1480_kgdb_interrupt(); /* KGDB (uart 1) */ 518 bcm1480_kgdb_interrupt(); /* KGDB (uart 1) */
491#endif 519#endif
492 520
493 else if (pending & CAUSEF_IP2) { 521 else if (pending & CAUSEF_IP2)
494 unsigned long long mask_h, mask_l; 522 dispatch_ip2();
495 unsigned long base;
496
497 /*
498 * Default...we've hit an IP[2] interrupt, which means we've
499 * got to check the 1480 interrupt registers to figure out what
500 * to do. Need to detect which CPU we're on, now that
501 * smp_affinity is supported.
502 */
503 base = A_BCM1480_IMR_MAPPER(smp_processor_id());
504 mask_h = __raw_readq(
505 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H));
506 mask_l = __raw_readq(
507 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L));
508
509 if (mask_h) {
510 if (mask_h ^ 1)
511 do_IRQ(fls64(mask_h) - 1);
512 else
513 do_IRQ(63 + fls64(mask_l));
514 }
515 }
516} 523}
diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c
index 02b266a31c46..436ba78359ab 100644
--- a/arch/mips/sibyte/bcm1480/smp.c
+++ b/arch/mips/sibyte/bcm1480/smp.c
@@ -58,7 +58,7 @@ static void *mailbox_0_regs[] = {
58/* 58/*
59 * SMP init and finish on secondary CPUs 59 * SMP init and finish on secondary CPUs
60 */ 60 */
61void bcm1480_smp_init(void) 61void __cpuinit bcm1480_smp_init(void)
62{ 62{
63 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | 63 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
64 STATUSF_IP1 | STATUSF_IP0; 64 STATUSF_IP1 | STATUSF_IP0;
@@ -67,7 +67,7 @@ void bcm1480_smp_init(void)
67 change_c0_status(ST0_IM, imask); 67 change_c0_status(ST0_IM, imask);
68} 68}
69 69
70void bcm1480_smp_finish(void) 70void __cpuinit bcm1480_smp_finish(void)
71{ 71{
72 extern void sb1480_clockevent_init(void); 72 extern void sb1480_clockevent_init(void);
73 73
diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c
index c730744aa474..610f0253954d 100644
--- a/arch/mips/sibyte/bcm1480/time.c
+++ b/arch/mips/sibyte/bcm1480/time.c
@@ -15,22 +15,12 @@
15 * along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */ 17 */
18
19/*
20 * These are routines to set up and handle interrupts from the
21 * bcm1480 general purpose timer 0. We're using the timer as a
22 * system clock, so we set it up to run at 100 Hz. On every
23 * interrupt, we update our idea of what the time of day is,
24 * then call do_timer() in the architecture-independent kernel
25 * code to do general bookkeeping (e.g. update jiffies, run
26 * bottom halves, etc.)
27 */
28#include <linux/clockchips.h> 18#include <linux/clockchips.h>
29#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/irq.h>
30#include <linux/percpu.h> 21#include <linux/percpu.h>
31#include <linux/spinlock.h> 22#include <linux/spinlock.h>
32 23
33#include <asm/irq.h>
34#include <asm/addrspace.h> 24#include <asm/addrspace.h>
35#include <asm/time.h> 25#include <asm/time.h>
36#include <asm/io.h> 26#include <asm/io.h>
@@ -47,33 +37,10 @@
47#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 37#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
48#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 38#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
49 39
50#ifdef CONFIG_SIMULATION
51#define BCM1480_HPT_VALUE 50000
52#else
53#define BCM1480_HPT_VALUE 1000000
54#endif
55
56extern int bcm1480_steal_irq(int irq); 40extern int bcm1480_steal_irq(int irq);
57 41
58void __init plat_time_init(void)
59{
60 unsigned int cpu = smp_processor_id();
61 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
62
63 BUG_ON(cpu > 3); /* Only have 4 general purpose timers */
64
65 bcm1480_mask_irq(cpu, irq);
66
67 /* Map the timer interrupt to ip[4] of this cpu */
68 __raw_writeq(IMR_IP4_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H)
69 + (irq<<3)));
70
71 bcm1480_unmask_irq(cpu, irq);
72 bcm1480_steal_irq(irq);
73}
74
75/* 42/*
76 * The general purpose timer ticks at 1 Mhz independent if 43 * The general purpose timer ticks at 1MHz independent if
77 * the rest of the system 44 * the rest of the system
78 */ 45 */
79static void sibyte_set_mode(enum clock_event_mode mode, 46static void sibyte_set_mode(enum clock_event_mode mode,
@@ -88,7 +55,7 @@ static void sibyte_set_mode(enum clock_event_mode mode,
88 switch (mode) { 55 switch (mode) {
89 case CLOCK_EVT_MODE_PERIODIC: 56 case CLOCK_EVT_MODE_PERIODIC:
90 __raw_writeq(0, timer_cfg); 57 __raw_writeq(0, timer_cfg);
91 __raw_writeq(BCM1480_HPT_VALUE / HZ - 1, timer_init); 58 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
92 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 59 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
93 timer_cfg); 60 timer_cfg);
94 break; 61 break;
@@ -121,80 +88,96 @@ static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
121 return res; 88 return res;
122} 89}
123 90
124static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
125
126static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) 91static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
127{ 92{
128 unsigned int cpu = smp_processor_id(); 93 unsigned int cpu = smp_processor_id();
129 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu); 94 struct clock_event_device *cd = dev_id;
95 void __iomem *timer_cfg;
96
97 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
130 98
131 /* Reset the timer */ 99 /* Reset the timer */
132 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 100 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
133 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 101 timer_cfg);
134 cd->event_handler(cd); 102 cd->event_handler(cd);
135 103
136 return IRQ_HANDLED; 104 return IRQ_HANDLED;
137} 105}
138 106
139static struct irqaction sibyte_counter_irqaction = { 107static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
140 .handler = sibyte_counter_handler, 108static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
141 .flags = IRQF_DISABLED | IRQF_PERCPU, 109static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
142 .name = "timer",
143};
144 110
145/*
146 * This interrupt is "special" in that it doesn't use the request_irq
147 * way to hook the irq line. The timer interrupt is initialized early
148 * enough to make this a major pain, and it's also firing enough to
149 * warrant a bit of special case code. bcm1480_timer_interrupt is
150 * called directly from irq_handler.S when IP[4] is set during an
151 * interrupt
152 */
153void __cpuinit sb1480_clockevent_init(void) 111void __cpuinit sb1480_clockevent_init(void)
154{ 112{
155 unsigned int cpu = smp_processor_id(); 113 unsigned int cpu = smp_processor_id();
156 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu; 114 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
115 struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
157 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu); 116 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
117 unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
118
119 BUG_ON(cpu > 3); /* Only have 4 general purpose timers */
158 120
159 cd->name = "bcm1480-counter"; 121 sprintf(name, "bcm1480-counter %d", cpu);
122 cd->name = name;
160 cd->features = CLOCK_EVT_FEAT_PERIODIC | 123 cd->features = CLOCK_EVT_FEAT_PERIODIC |
161 CLOCK_EVT_MODE_ONESHOT; 124 CLOCK_EVT_MODE_ONESHOT;
125 clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
126 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
127 cd->min_delta_ns = clockevent_delta2ns(1, cd);
128 cd->rating = 200;
129 cd->irq = irq;
130 cd->cpumask = cpumask_of_cpu(cpu);
162 cd->set_next_event = sibyte_next_event; 131 cd->set_next_event = sibyte_next_event;
163 cd->set_mode = sibyte_set_mode; 132 cd->set_mode = sibyte_set_mode;
164 cd->irq = irq; 133 clockevents_register_device(cd);
165 clockevent_set_clock(cd, BCM1480_HPT_VALUE); 134
135 bcm1480_mask_irq(cpu, irq);
136
137 /*
138 * Map timer interrupt to IP[4] of this cpu
139 */
140 __raw_writeq(IMR_IP4_VAL,
141 IOADDR(A_BCM1480_IMR_REGISTER(cpu,
142 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3)));
166 143
167 setup_irq(irq, &sibyte_counter_irqaction); 144 bcm1480_unmask_irq(cpu, irq);
145 bcm1480_steal_irq(irq);
146
147 action->handler = sibyte_counter_handler;
148 action->flags = IRQF_DISABLED | IRQF_PERCPU;
149 action->name = name;
150 action->dev_id = cd;
151 setup_irq(irq, action);
168} 152}
169 153
170static cycle_t bcm1480_hpt_read(void) 154static cycle_t bcm1480_hpt_read(void)
171{ 155{
172 /* We assume this function is called xtime_lock held. */ 156 return (cycle_t) __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT));
173 unsigned long count =
174 __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
175 return (jiffies + 1) * (BCM1480_HPT_VALUE / HZ) - count;
176} 157}
177 158
178struct clocksource bcm1480_clocksource = { 159struct clocksource bcm1480_clocksource = {
179 .name = "MIPS", 160 .name = "zbbus-cycles",
180 .rating = 200, 161 .rating = 200,
181 .read = bcm1480_hpt_read, 162 .read = bcm1480_hpt_read,
182 .mask = CLOCKSOURCE_MASK(32), 163 .mask = CLOCKSOURCE_MASK(64),
183 .shift = 32,
184 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 164 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
185}; 165};
186 166
187void __init sb1480_clocksource_init(void) 167void __init sb1480_clocksource_init(void)
188{ 168{
189 struct clocksource *cs = &bcm1480_clocksource; 169 struct clocksource *cs = &bcm1480_clocksource;
170 unsigned int plldiv;
171 unsigned long zbbus;
190 172
191 clocksource_set_clock(cs, BCM1480_HPT_VALUE); 173 plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
174 zbbus = ((plldiv >> 1) * 50000000) + ((plldiv & 1) * 25000000);
175 clocksource_set_clock(cs, zbbus);
192 clocksource_register(cs); 176 clocksource_register(cs);
193} 177}
194 178
195void __init bcm1480_hpt_setup(void) 179void __init plat_time_init(void)
196{ 180{
197 mips_hpt_frequency = BCM1480_HPT_VALUE;
198 sb1480_clocksource_init(); 181 sb1480_clocksource_init();
199 sb1480_clockevent_init(); 182 sb1480_clockevent_init();
200} 183}
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 500d17e84c09..53780a179d1d 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -402,6 +402,22 @@ static void sb1250_kgdb_interrupt(void)
402 402
403extern void sb1250_mailbox_interrupt(void); 403extern void sb1250_mailbox_interrupt(void);
404 404
405static inline void dispatch_ip2(void)
406{
407 unsigned int cpu = smp_processor_id();
408 unsigned long long mask;
409
410 /*
411 * Default...we've hit an IP[2] interrupt, which means we've got to
412 * check the 1250 interrupt registers to figure out what to do. Need
413 * to detect which CPU we're on, now that smp_affinity is supported.
414 */
415 mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
416 R_IMR_INTERRUPT_STATUS_BASE)));
417 if (mask)
418 do_IRQ(fls64(mask) - 1);
419}
420
405asmlinkage void plat_irq_dispatch(void) 421asmlinkage void plat_irq_dispatch(void)
406{ 422{
407 unsigned int cpu = smp_processor_id(); 423 unsigned int cpu = smp_processor_id();
@@ -434,21 +450,8 @@ asmlinkage void plat_irq_dispatch(void)
434 sb1250_kgdb_interrupt(); 450 sb1250_kgdb_interrupt();
435#endif 451#endif
436 452
437 else if (pending & CAUSEF_IP2) { 453 else if (pending & CAUSEF_IP2)
438 unsigned long long mask; 454 dispatch_ip2();
439 455 else
440 /*
441 * Default...we've hit an IP[2] interrupt, which means we've
442 * got to check the 1250 interrupt registers to figure out what
443 * to do. Need to detect which CPU we're on, now that
444 * smp_affinity is supported.
445 */
446 mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
447 R_IMR_INTERRUPT_STATUS_BASE)));
448 if (mask)
449 do_IRQ(fls64(mask) - 1);
450 else
451 spurious_interrupt();
452 } else
453 spurious_interrupt(); 456 spurious_interrupt();
454} 457}
diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c
index aaa4f30dda79..3f52c95a4eb8 100644
--- a/arch/mips/sibyte/sb1250/smp.c
+++ b/arch/mips/sibyte/sb1250/smp.c
@@ -46,7 +46,7 @@ static void *mailbox_regs[] = {
46/* 46/*
47 * SMP init and finish on secondary CPUs 47 * SMP init and finish on secondary CPUs
48 */ 48 */
49void sb1250_smp_init(void) 49void __cpuinit sb1250_smp_init(void)
50{ 50{
51 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | 51 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
52 STATUSF_IP1 | STATUSF_IP0; 52 STATUSF_IP1 | STATUSF_IP0;
@@ -55,7 +55,7 @@ void sb1250_smp_init(void)
55 change_c0_status(ST0_IM, imask); 55 change_c0_status(ST0_IM, imask);
56} 56}
57 57
58void sb1250_smp_finish(void) 58void __cpuinit sb1250_smp_finish(void)
59{ 59{
60 extern void sb1250_clockevent_init(void); 60 extern void sb1250_clockevent_init(void);
61 61
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index 9ef54628bc9c..a41e908bc218 100644
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -52,26 +52,6 @@
52 52
53extern int sb1250_steal_irq(int irq); 53extern int sb1250_steal_irq(int irq);
54 54
55static cycle_t sb1250_hpt_read(void);
56
57void __init sb1250_hpt_setup(void)
58{
59 int cpu = smp_processor_id();
60
61 if (!cpu) {
62 /* Setup hpt using timer #3 but do not enable irq for it */
63 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
64 __raw_writeq(SB1250_HPT_VALUE,
65 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT)));
66 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
67 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
68
69 mips_hpt_frequency = V_SCD_TIMER_FREQ;
70 clocksource_mips.read = sb1250_hpt_read;
71 clocksource_mips.mask = M_SCD_TIMER_INIT;
72 }
73}
74
75/* 55/*
76 * The general purpose timer ticks at 1 Mhz independent if 56 * The general purpose timer ticks at 1 Mhz independent if
77 * the rest of the system 57 * the rest of the system
@@ -121,18 +101,14 @@ sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
121 return 0; 101 return 0;
122} 102}
123 103
124struct clock_event_device sibyte_hpt_clockevent = {
125 .name = "sb1250-counter",
126 .features = CLOCK_EVT_FEAT_PERIODIC,
127 .set_mode = sibyte_set_mode,
128 .set_next_event = sibyte_next_event,
129 .shift = 32,
130 .irq = 0,
131};
132
133static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) 104static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
134{ 105{
135 struct clock_event_device *cd = &sibyte_hpt_clockevent; 106 unsigned int cpu = smp_processor_id();
107 struct clock_event_device *cd = dev_id;
108
109 /* ACK interrupt */
110 ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
111 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
136 112
137 cd->event_handler(cd); 113 cd->event_handler(cd);
138 114
@@ -145,15 +121,35 @@ static struct irqaction sibyte_irqaction = {
145 .name = "timer", 121 .name = "timer",
146}; 122};
147 123
124static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
125static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
126static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
127
148void __cpuinit sb1250_clockevent_init(void) 128void __cpuinit sb1250_clockevent_init(void)
149{ 129{
150 struct clock_event_device *cd = &sibyte_hpt_clockevent;
151 unsigned int cpu = smp_processor_id(); 130 unsigned int cpu = smp_processor_id();
152 int irq = K_INT_TIMER_0 + cpu; 131 unsigned int irq = K_INT_TIMER_0 + cpu;
132 struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
133 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
134 unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
153 135
154 /* Only have 4 general purpose timers, and we use last one as hpt */ 136 /* Only have 4 general purpose timers, and we use last one as hpt */
155 BUG_ON(cpu > 2); 137 BUG_ON(cpu > 2);
156 138
139 sprintf(name, "bcm1480-counter %d", cpu);
140 cd->name = name;
141 cd->features = CLOCK_EVT_FEAT_PERIODIC |
142 CLOCK_EVT_MODE_ONESHOT;
143 clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
144 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
145 cd->min_delta_ns = clockevent_delta2ns(1, cd);
146 cd->rating = 200;
147 cd->irq = irq;
148 cd->cpumask = cpumask_of_cpu(cpu);
149 cd->set_next_event = sibyte_next_event;
150 cd->set_mode = sibyte_set_mode;
151 clockevents_register_device(cd);
152
157 sb1250_mask_irq(cpu, irq); 153 sb1250_mask_irq(cpu, irq);
158 154
159 /* Map the timer interrupt to ip[4] of this cpu */ 155 /* Map the timer interrupt to ip[4] of this cpu */
@@ -165,17 +161,11 @@ void __cpuinit sb1250_clockevent_init(void)
165 sb1250_unmask_irq(cpu, irq); 161 sb1250_unmask_irq(cpu, irq);
166 sb1250_steal_irq(irq); 162 sb1250_steal_irq(irq);
167 163
168 /* 164 action->handler = sibyte_counter_handler;
169 * This interrupt is "special" in that it doesn't use the request_irq 165 action->flags = IRQF_DISABLED | IRQF_PERCPU;
170 * way to hook the irq line. The timer interrupt is initialized early 166 action->name = name;
171 * enough to make this a major pain, and it's also firing enough to 167 action->dev_id = cd;
172 * warrant a bit of special case code. sb1250_timer_interrupt is
173 * called directly from irq_handler.S when IP[4] is set during an
174 * interrupt
175 */
176 setup_irq(irq, &sibyte_irqaction); 168 setup_irq(irq, &sibyte_irqaction);
177
178 clockevents_register_device(cd);
179} 169}
180 170
181/* 171/*
@@ -195,8 +185,7 @@ struct clocksource bcm1250_clocksource = {
195 .name = "MIPS", 185 .name = "MIPS",
196 .rating = 200, 186 .rating = 200,
197 .read = sb1250_hpt_read, 187 .read = sb1250_hpt_read,
198 .mask = CLOCKSOURCE_MASK(32), 188 .mask = CLOCKSOURCE_MASK(23),
199 .shift = 32,
200 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 189 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
201}; 190};
202 191
@@ -204,6 +193,17 @@ void __init sb1250_clocksource_init(void)
204{ 193{
205 struct clocksource *cs = &bcm1250_clocksource; 194 struct clocksource *cs = &bcm1250_clocksource;
206 195
196 /* Setup hpt using timer #3 but do not enable irq for it */
197 __raw_writeq(0,
198 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
199 R_SCD_TIMER_CFG)));
200 __raw_writeq(SB1250_HPT_VALUE,
201 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
202 R_SCD_TIMER_INIT)));
203 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
204 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
205 R_SCD_TIMER_CFG)));
206
207 clocksource_set_clock(cs, V_SCD_TIMER_FREQ); 207 clocksource_set_clock(cs, V_SCD_TIMER_FREQ);
208 clocksource_register(cs); 208 clocksource_register(cs);
209} 209}
diff --git a/include/asm-mips/sibyte/sb1250.h b/include/asm-mips/sibyte/sb1250.h
index 494aa65dcfbd..0dad844a3b5b 100644
--- a/include/asm-mips/sibyte/sb1250.h
+++ b/include/asm-mips/sibyte/sb1250.h
@@ -45,13 +45,11 @@ extern unsigned int soc_type;
45extern unsigned int periph_rev; 45extern unsigned int periph_rev;
46extern unsigned int zbbus_mhz; 46extern unsigned int zbbus_mhz;
47 47
48extern void sb1250_hpt_setup(void);
49extern void sb1250_time_init(void); 48extern void sb1250_time_init(void);
50extern void sb1250_mask_irq(int cpu, int irq); 49extern void sb1250_mask_irq(int cpu, int irq);
51extern void sb1250_unmask_irq(int cpu, int irq); 50extern void sb1250_unmask_irq(int cpu, int irq);
52extern void sb1250_smp_finish(void); 51extern void sb1250_smp_finish(void);
53 52
54extern void bcm1480_hpt_setup(void);
55extern void bcm1480_time_init(void); 53extern void bcm1480_time_init(void);
56extern void bcm1480_mask_irq(int cpu, int irq); 54extern void bcm1480_mask_irq(int cpu, int irq);
57extern void bcm1480_unmask_irq(int cpu, int irq); 55extern void bcm1480_unmask_irq(int cpu, int irq);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 07:51:18 -0500