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-rw-r--r--Documentation/powerpc/booting-without-of.txt1168
-rw-r--r--Documentation/powerpc/dts-bindings/4xx/emac.txt148
-rw-r--r--Documentation/powerpc/dts-bindings/gpio/gpio.txt50
-rw-r--r--Documentation/powerpc/dts-bindings/gpio/mdio.txt19
-rw-r--r--Documentation/powerpc/dts-bindings/marvell.txt521
-rw-r--r--Documentation/powerpc/dts-bindings/phy.txt25
-rw-r--r--Documentation/powerpc/dts-bindings/spi-bus.txt57
-rw-r--r--Documentation/powerpc/dts-bindings/usb-ehci.txt25
-rw-r--r--Documentation/powerpc/dts-bindings/xilinx.txt295
-rw-r--r--arch/powerpc/Kconfig1
-rw-r--r--arch/powerpc/boot/.gitignore10
-rw-r--r--arch/powerpc/boot/dts/amigaone.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8569mds.dts1
-rw-r--r--arch/powerpc/include/asm/cpm1.h2
-rw-r--r--arch/powerpc/include/asm/dma-mapping.h24
-rw-r--r--arch/powerpc/include/asm/highmem.h57
-rw-r--r--arch/powerpc/include/asm/hw_irq.h20
-rw-r--r--arch/powerpc/include/asm/pte-hash64-64k.h3
-rw-r--r--arch/powerpc/include/asm/rtas.h5
-rw-r--r--arch/powerpc/kernel/entry_32.S127
-rw-r--r--arch/powerpc/kernel/head_32.S17
-rw-r--r--arch/powerpc/kernel/of_device.c2
-rw-r--r--arch/powerpc/kernel/process.c2
-rw-r--r--arch/powerpc/kernel/rtas.c69
-rw-r--r--arch/powerpc/kernel/setup_32.c2
-rw-r--r--arch/powerpc/kernel/smp.c3
-rw-r--r--arch/powerpc/kernel/udbg_16550.c2
-rw-r--r--arch/powerpc/mm/Makefile1
-rw-r--r--arch/powerpc/mm/highmem.c77
-rw-r--r--arch/powerpc/platforms/44x/warp.c44
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c1
-rw-r--r--arch/powerpc/platforms/85xx/smp.c9
-rw-r--r--arch/powerpc/platforms/85xx/socrates.c6
-rw-r--r--arch/powerpc/platforms/85xx/xes_mpc85xx.c1
-rw-r--r--arch/powerpc/platforms/cell/smp.c30
-rw-r--r--arch/powerpc/platforms/chrp/smp.c33
-rw-r--r--arch/powerpc/platforms/pasemi/setup.c15
-rw-r--r--arch/powerpc/platforms/powermac/setup.c41
-rw-r--r--arch/powerpc/platforms/powermac/smp.c166
-rw-r--r--arch/powerpc/platforms/pseries/smp.c30
-rw-r--r--arch/powerpc/sysdev/mpic.c34
-rw-r--r--arch/powerpc/sysdev/qe_lib/qe.c9
-rw-r--r--drivers/char/bsr.c42
-rw-r--r--drivers/macintosh/macio_asic.c11
-rw-r--r--drivers/watchdog/wdrtas.c8
-rw-r--r--scripts/dtc/.gitignore5
46 files changed, 1691 insertions, 1531 deletions
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index 8d999d862d0e..79f533f38c61 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -1238,1122 +1238,7 @@ descriptions for the SOC devices for which new nodes have been
1238defined; this list will expand as more and more SOC-containing 1238defined; this list will expand as more and more SOC-containing
1239platforms are moved over to use the flattened-device-tree model. 1239platforms are moved over to use the flattened-device-tree model.
1240 1240
1241 a) PHY nodes 1241VII - Specifying interrupt information for devices
1242
1243 Required properties:
1244
1245 - device_type : Should be "ethernet-phy"
1246 - interrupts : <a b> where a is the interrupt number and b is a
1247 field that represents an encoding of the sense and level
1248 information for the interrupt. This should be encoded based on
1249 the information in section 2) depending on the type of interrupt
1250 controller you have.
1251 - interrupt-parent : the phandle for the interrupt controller that
1252 services interrupts for this device.
1253 - reg : The ID number for the phy, usually a small integer
1254 - linux,phandle : phandle for this node; likely referenced by an
1255 ethernet controller node.
1256
1257
1258 Example:
1259
1260 ethernet-phy@0 {
1261 linux,phandle = <2452000>
1262 interrupt-parent = <40000>;
1263 interrupts = <35 1>;
1264 reg = <0>;
1265 device_type = "ethernet-phy";
1266 };
1267
1268
1269 b) Interrupt controllers
1270
1271 Some SOC devices contain interrupt controllers that are different
1272 from the standard Open PIC specification. The SOC device nodes for
1273 these types of controllers should be specified just like a standard
1274 OpenPIC controller. Sense and level information should be encoded
1275 as specified in section 2) of this chapter for each device that
1276 specifies an interrupt.
1277
1278 Example :
1279
1280 pic@40000 {
1281 linux,phandle = <40000>;
1282 interrupt-controller;
1283 #address-cells = <0>;
1284 reg = <40000 40000>;
1285 compatible = "chrp,open-pic";
1286 device_type = "open-pic";
1287 };
1288
1289 c) 4xx/Axon EMAC ethernet nodes
1290
1291 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
1292 the Axon bridge. To operate this needs to interact with a ths
1293 special McMAL DMA controller, and sometimes an RGMII or ZMII
1294 interface. In addition to the nodes and properties described
1295 below, the node for the OPB bus on which the EMAC sits must have a
1296 correct clock-frequency property.
1297
1298 i) The EMAC node itself
1299
1300 Required properties:
1301 - device_type : "network"
1302
1303 - compatible : compatible list, contains 2 entries, first is
1304 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
1305 405gp, Axon) and second is either "ibm,emac" or
1306 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
1307 "ibm,emac4"
1308 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
1309 - interrupt-parent : optional, if needed for interrupt mapping
1310 - reg : <registers mapping>
1311 - local-mac-address : 6 bytes, MAC address
1312 - mal-device : phandle of the associated McMAL node
1313 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
1314 with this EMAC
1315 - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
1316 with this EMAC
1317 - cell-index : 1 cell, hardware index of the EMAC cell on a given
1318 ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
1319 each Axon chip)
1320 - max-frame-size : 1 cell, maximum frame size supported in bytes
1321 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
1322 operations.
1323 For Axon, 2048
1324 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
1325 operations.
1326 For Axon, 2048.
1327 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
1328 thresholds).
1329 For Axon, 0x00000010
1330 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
1331 in bytes.
1332 For Axon, 0x00000100 (I think ...)
1333 - phy-mode : string, mode of operations of the PHY interface.
1334 Supported values are: "mii", "rmii", "smii", "rgmii",
1335 "tbi", "gmii", rtbi", "sgmii".
1336 For Axon on CAB, it is "rgmii"
1337 - mdio-device : 1 cell, required iff using shared MDIO registers
1338 (440EP). phandle of the EMAC to use to drive the
1339 MDIO lines for the PHY used by this EMAC.
1340 - zmii-device : 1 cell, required iff connected to a ZMII. phandle of
1341 the ZMII device node
1342 - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII
1343 channel or 0xffffffff if ZMII is only used for MDIO.
1344 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
1345 of the RGMII device node.
1346 For Axon: phandle of plb5/plb4/opb/rgmii
1347 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
1348 RGMII channel is used by this EMAC.
1349 Fox Axon: present, whatever value is appropriate for each
1350 EMAC, that is the content of the current (bogus) "phy-port"
1351 property.
1352
1353 Optional properties:
1354 - phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
1355 a search is performed.
1356 - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY
1357 for, used if phy-address is absent. bit 0x00000001 is
1358 MDIO address 0.
1359 For Axon it can be absent, though my current driver
1360 doesn't handle phy-address yet so for now, keep
1361 0x00ffffff in it.
1362 - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
1363 operations (if absent the value is the same as
1364 rx-fifo-size). For Axon, either absent or 2048.
1365 - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
1366 operations (if absent the value is the same as
1367 tx-fifo-size). For Axon, either absent or 2048.
1368 - tah-device : 1 cell, optional. If connected to a TAH engine for
1369 offload, phandle of the TAH device node.
1370 - tah-channel : 1 cell, optional. If appropriate, channel used on the
1371 TAH engine.
1372
1373 Example:
1374
1375 EMAC0: ethernet@40000800 {
1376 device_type = "network";
1377 compatible = "ibm,emac-440gp", "ibm,emac";
1378 interrupt-parent = <&UIC1>;
1379 interrupts = <1c 4 1d 4>;
1380 reg = <40000800 70>;
1381 local-mac-address = [00 04 AC E3 1B 1E];
1382 mal-device = <&MAL0>;
1383 mal-tx-channel = <0 1>;
1384 mal-rx-channel = <0>;
1385 cell-index = <0>;
1386 max-frame-size = <5dc>;
1387 rx-fifo-size = <1000>;
1388 tx-fifo-size = <800>;
1389 phy-mode = "rmii";
1390 phy-map = <00000001>;
1391 zmii-device = <&ZMII0>;
1392 zmii-channel = <0>;
1393 };
1394
1395 ii) McMAL node
1396
1397 Required properties:
1398 - device_type : "dma-controller"
1399 - compatible : compatible list, containing 2 entries, first is
1400 "ibm,mcmal-CHIP" where CHIP is the host ASIC (like
1401 emac) and the second is either "ibm,mcmal" or
1402 "ibm,mcmal2".
1403 For Axon, "ibm,mcmal-axon","ibm,mcmal2"
1404 - interrupts : <interrupt mapping for the MAL interrupts sources:
1405 5 sources: tx_eob, rx_eob, serr, txde, rxde>.
1406 For Axon: This is _different_ from the current
1407 firmware. We use the "delayed" interrupts for txeob
1408 and rxeob. Thus we end up with mapping those 5 MPIC
1409 interrupts, all level positive sensitive: 10, 11, 32,
1410 33, 34 (in decimal)
1411 - dcr-reg : < DCR registers range >
1412 - dcr-parent : if needed for dcr-reg
1413 - num-tx-chans : 1 cell, number of Tx channels
1414 - num-rx-chans : 1 cell, number of Rx channels
1415
1416 iii) ZMII node
1417
1418 Required properties:
1419 - compatible : compatible list, containing 2 entries, first is
1420 "ibm,zmii-CHIP" where CHIP is the host ASIC (like
1421 EMAC) and the second is "ibm,zmii".
1422 For Axon, there is no ZMII node.
1423 - reg : <registers mapping>
1424
1425 iv) RGMII node
1426
1427 Required properties:
1428 - compatible : compatible list, containing 2 entries, first is
1429 "ibm,rgmii-CHIP" where CHIP is the host ASIC (like
1430 EMAC) and the second is "ibm,rgmii".
1431 For Axon, "ibm,rgmii-axon","ibm,rgmii"
1432 - reg : <registers mapping>
1433 - revision : as provided by the RGMII new version register if
1434 available.
1435 For Axon: 0x0000012a
1436
1437 d) Xilinx IP cores
1438
1439 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
1440 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
1441 of standard device types (network, serial, etc.) and miscellaneous
1442 devices (gpio, LCD, spi, etc). Also, since these devices are
1443 implemented within the fpga fabric every instance of the device can be
1444 synthesised with different options that change the behaviour.
1445
1446 Each IP-core has a set of parameters which the FPGA designer can use to
1447 control how the core is synthesized. Historically, the EDK tool would
1448 extract the device parameters relevant to device drivers and copy them
1449 into an 'xparameters.h' in the form of #define symbols. This tells the
1450 device drivers how the IP cores are configured, but it requres the kernel
1451 to be recompiled every time the FPGA bitstream is resynthesized.
1452
1453 The new approach is to export the parameters into the device tree and
1454 generate a new device tree each time the FPGA bitstream changes. The
1455 parameters which used to be exported as #defines will now become
1456 properties of the device node. In general, device nodes for IP-cores
1457 will take the following form:
1458
1459 (name): (generic-name)@(base-address) {
1460 compatible = "xlnx,(ip-core-name)-(HW_VER)"
1461 [, (list of compatible devices), ...];
1462 reg = <(baseaddr) (size)>;
1463 interrupt-parent = <&interrupt-controller-phandle>;
1464 interrupts = < ... >;
1465 xlnx,(parameter1) = "(string-value)";
1466 xlnx,(parameter2) = <(int-value)>;
1467 };
1468
1469 (generic-name): an open firmware-style name that describes the
1470 generic class of device. Preferably, this is one word, such
1471 as 'serial' or 'ethernet'.
1472 (ip-core-name): the name of the ip block (given after the BEGIN
1473 directive in system.mhs). Should be in lowercase
1474 and all underscores '_' converted to dashes '-'.
1475 (name): is derived from the "PARAMETER INSTANCE" value.
1476 (parameter#): C_* parameters from system.mhs. The C_ prefix is
1477 dropped from the parameter name, the name is converted
1478 to lowercase and all underscore '_' characters are
1479 converted to dashes '-'.
1480 (baseaddr): the baseaddr parameter value (often named C_BASEADDR).
1481 (HW_VER): from the HW_VER parameter.
1482 (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
1483
1484 Typically, the compatible list will include the exact IP core version
1485 followed by an older IP core version which implements the same
1486 interface or any other device with the same interface.
1487
1488 'reg', 'interrupt-parent' and 'interrupts' are all optional properties.
1489
1490 For example, the following block from system.mhs:
1491
1492 BEGIN opb_uartlite
1493 PARAMETER INSTANCE = opb_uartlite_0
1494 PARAMETER HW_VER = 1.00.b
1495 PARAMETER C_BAUDRATE = 115200
1496 PARAMETER C_DATA_BITS = 8
1497 PARAMETER C_ODD_PARITY = 0
1498 PARAMETER C_USE_PARITY = 0
1499 PARAMETER C_CLK_FREQ = 50000000
1500 PARAMETER C_BASEADDR = 0xEC100000
1501 PARAMETER C_HIGHADDR = 0xEC10FFFF
1502 BUS_INTERFACE SOPB = opb_7
1503 PORT OPB_Clk = CLK_50MHz
1504 PORT Interrupt = opb_uartlite_0_Interrupt
1505 PORT RX = opb_uartlite_0_RX
1506 PORT TX = opb_uartlite_0_TX
1507 PORT OPB_Rst = sys_bus_reset_0
1508 END
1509
1510 becomes the following device tree node:
1511
1512 opb_uartlite_0: serial@ec100000 {
1513 device_type = "serial";
1514 compatible = "xlnx,opb-uartlite-1.00.b";
1515 reg = <ec100000 10000>;
1516 interrupt-parent = <&opb_intc_0>;
1517 interrupts = <1 0>; // got this from the opb_intc parameters
1518 current-speed = <d#115200>; // standard serial device prop
1519 clock-frequency = <d#50000000>; // standard serial device prop
1520 xlnx,data-bits = <8>;
1521 xlnx,odd-parity = <0>;
1522 xlnx,use-parity = <0>;
1523 };
1524
1525 Some IP cores actually implement 2 or more logical devices. In
1526 this case, the device should still describe the whole IP core with
1527 a single node and add a child node for each logical device. The
1528 ranges property can be used to translate from parent IP-core to the
1529 registers of each device. In addition, the parent node should be
1530 compatible with the bus type 'xlnx,compound', and should contain
1531 #address-cells and #size-cells, as with any other bus. (Note: this
1532 makes the assumption that both logical devices have the same bus
1533 binding. If this is not true, then separate nodes should be used
1534 for each logical device). The 'cell-index' property can be used to
1535 enumerate logical devices within an IP core. For example, the
1536 following is the system.mhs entry for the dual ps2 controller found
1537 on the ml403 reference design.
1538
1539 BEGIN opb_ps2_dual_ref
1540 PARAMETER INSTANCE = opb_ps2_dual_ref_0
1541 PARAMETER HW_VER = 1.00.a
1542 PARAMETER C_BASEADDR = 0xA9000000
1543 PARAMETER C_HIGHADDR = 0xA9001FFF
1544 BUS_INTERFACE SOPB = opb_v20_0
1545 PORT Sys_Intr1 = ps2_1_intr
1546 PORT Sys_Intr2 = ps2_2_intr
1547 PORT Clkin1 = ps2_clk_rx_1
1548 PORT Clkin2 = ps2_clk_rx_2
1549 PORT Clkpd1 = ps2_clk_tx_1
1550 PORT Clkpd2 = ps2_clk_tx_2
1551 PORT Rx1 = ps2_d_rx_1
1552 PORT Rx2 = ps2_d_rx_2
1553 PORT Txpd1 = ps2_d_tx_1
1554 PORT Txpd2 = ps2_d_tx_2
1555 END
1556
1557 It would result in the following device tree nodes:
1558
1559 opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
1560 #address-cells = <1>;
1561 #size-cells = <1>;
1562 compatible = "xlnx,compound";
1563 ranges = <0 a9000000 2000>;
1564 // If this device had extra parameters, then they would
1565 // go here.
1566 ps2@0 {
1567 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
1568 reg = <0 40>;
1569 interrupt-parent = <&opb_intc_0>;
1570 interrupts = <3 0>;
1571 cell-index = <0>;
1572 };
1573 ps2@1000 {
1574 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
1575 reg = <1000 40>;
1576 interrupt-parent = <&opb_intc_0>;
1577 interrupts = <3 0>;
1578 cell-index = <0>;
1579 };
1580 };
1581
1582 Also, the system.mhs file defines bus attachments from the processor
1583 to the devices. The device tree structure should reflect the bus
1584 attachments. Again an example; this system.mhs fragment:
1585
1586 BEGIN ppc405_virtex4
1587 PARAMETER INSTANCE = ppc405_0
1588 PARAMETER HW_VER = 1.01.a
1589 BUS_INTERFACE DPLB = plb_v34_0
1590 BUS_INTERFACE IPLB = plb_v34_0
1591 END
1592
1593 BEGIN opb_intc
1594 PARAMETER INSTANCE = opb_intc_0
1595 PARAMETER HW_VER = 1.00.c
1596 PARAMETER C_BASEADDR = 0xD1000FC0
1597 PARAMETER C_HIGHADDR = 0xD1000FDF
1598 BUS_INTERFACE SOPB = opb_v20_0
1599 END
1600
1601 BEGIN opb_uart16550
1602 PARAMETER INSTANCE = opb_uart16550_0
1603 PARAMETER HW_VER = 1.00.d
1604 PARAMETER C_BASEADDR = 0xa0000000
1605 PARAMETER C_HIGHADDR = 0xa0001FFF
1606 BUS_INTERFACE SOPB = opb_v20_0
1607 END
1608
1609 BEGIN plb_v34
1610 PARAMETER INSTANCE = plb_v34_0
1611 PARAMETER HW_VER = 1.02.a
1612 END
1613
1614 BEGIN plb_bram_if_cntlr
1615 PARAMETER INSTANCE = plb_bram_if_cntlr_0
1616 PARAMETER HW_VER = 1.00.b
1617 PARAMETER C_BASEADDR = 0xFFFF0000
1618 PARAMETER C_HIGHADDR = 0xFFFFFFFF
1619 BUS_INTERFACE SPLB = plb_v34_0
1620 END
1621
1622 BEGIN plb2opb_bridge
1623 PARAMETER INSTANCE = plb2opb_bridge_0
1624 PARAMETER HW_VER = 1.01.a
1625 PARAMETER C_RNG0_BASEADDR = 0x20000000
1626 PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
1627 PARAMETER C_RNG1_BASEADDR = 0x60000000
1628 PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
1629 PARAMETER C_RNG2_BASEADDR = 0x80000000
1630 PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
1631 PARAMETER C_RNG3_BASEADDR = 0xC0000000
1632 PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
1633 BUS_INTERFACE SPLB = plb_v34_0
1634 BUS_INTERFACE MOPB = opb_v20_0
1635 END
1636
1637 Gives this device tree (some properties removed for clarity):
1638
1639 plb@0 {
1640 #address-cells = <1>;
1641 #size-cells = <1>;
1642 compatible = "xlnx,plb-v34-1.02.a";
1643 device_type = "ibm,plb";
1644 ranges; // 1:1 translation
1645
1646 plb_bram_if_cntrl_0: bram@ffff0000 {
1647 reg = <ffff0000 10000>;
1648 }
1649
1650 opb@20000000 {
1651 #address-cells = <1>;
1652 #size-cells = <1>;
1653 ranges = <20000000 20000000 20000000
1654 60000000 60000000 20000000
1655 80000000 80000000 40000000
1656 c0000000 c0000000 20000000>;
1657
1658 opb_uart16550_0: serial@a0000000 {
1659 reg = <a00000000 2000>;
1660 };
1661
1662 opb_intc_0: interrupt-controller@d1000fc0 {
1663 reg = <d1000fc0 20>;
1664 };
1665 };
1666 };
1667
1668 That covers the general approach to binding xilinx IP cores into the
1669 device tree. The following are bindings for specific devices:
1670
1671 i) Xilinx ML300 Framebuffer
1672
1673 Simple framebuffer device from the ML300 reference design (also on the
1674 ML403 reference design as well as others).
1675
1676 Optional properties:
1677 - resolution = <xres yres> : pixel resolution of framebuffer. Some
1678 implementations use a different resolution.
1679 Default is <d#640 d#480>
1680 - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
1681 Default is <d#1024 d#480>.
1682 - rotate-display (empty) : rotate display 180 degrees.
1683
1684 ii) Xilinx SystemACE
1685
1686 The Xilinx SystemACE device is used to program FPGAs from an FPGA
1687 bitstream stored on a CF card. It can also be used as a generic CF
1688 interface device.
1689
1690 Optional properties:
1691 - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
1692
1693 iii) Xilinx EMAC and Xilinx TEMAC
1694
1695 Xilinx Ethernet devices. In addition to general xilinx properties
1696 listed above, nodes for these devices should include a phy-handle
1697 property, and may include other common network device properties
1698 like local-mac-address.
1699
1700 iv) Xilinx Uartlite
1701
1702 Xilinx uartlite devices are simple fixed speed serial ports.
1703
1704 Required properties:
1705 - current-speed : Baud rate of uartlite
1706
1707 v) Xilinx hwicap
1708
1709 Xilinx hwicap devices provide access to the configuration logic
1710 of the FPGA through the Internal Configuration Access Port
1711 (ICAP). The ICAP enables partial reconfiguration of the FPGA,
1712 readback of the configuration information, and some control over
1713 'warm boots' of the FPGA fabric.
1714
1715 Required properties:
1716 - xlnx,family : The family of the FPGA, necessary since the
1717 capabilities of the underlying ICAP hardware
1718 differ between different families. May be
1719 'virtex2p', 'virtex4', or 'virtex5'.
1720
1721 vi) Xilinx Uart 16550
1722
1723 Xilinx UART 16550 devices are very similar to the NS16550 but with
1724 different register spacing and an offset from the base address.
1725
1726 Required properties:
1727 - clock-frequency : Frequency of the clock input
1728 - reg-offset : A value of 3 is required
1729 - reg-shift : A value of 2 is required
1730
1731 e) USB EHCI controllers
1732
1733 Required properties:
1734 - compatible : should be "usb-ehci".
1735 - reg : should contain at least address and length of the standard EHCI
1736 register set for the device. Optional platform-dependent registers
1737 (debug-port or other) can be also specified here, but only after
1738 definition of standard EHCI registers.
1739 - interrupts : one EHCI interrupt should be described here.
1740 If device registers are implemented in big endian mode, the device
1741 node should have "big-endian-regs" property.
1742 If controller implementation operates with big endian descriptors,
1743 "big-endian-desc" property should be specified.
1744 If both big endian registers and descriptors are used by the controller
1745 implementation, "big-endian" property can be specified instead of having
1746 both "big-endian-regs" and "big-endian-desc".
1747
1748 Example (Sequoia 440EPx):
1749 ehci@e0000300 {
1750 compatible = "ibm,usb-ehci-440epx", "usb-ehci";
1751 interrupt-parent = <&UIC0>;
1752 interrupts = <1a 4>;
1753 reg = <0 e0000300 90 0 e0000390 70>;
1754 big-endian;
1755 };
1756
1757 f) MDIO on GPIOs
1758
1759 Currently defined compatibles:
1760 - virtual,gpio-mdio
1761
1762 MDC and MDIO lines connected to GPIO controllers are listed in the
1763 gpios property as described in section VIII.1 in the following order:
1764
1765 MDC, MDIO.
1766
1767 Example:
1768
1769 mdio {
1770 compatible = "virtual,mdio-gpio";
1771 #address-cells = <1>;
1772 #size-cells = <0>;
1773 gpios = <&qe_pio_a 11
1774 &qe_pio_c 6>;
1775 };
1776
1777 g) SPI (Serial Peripheral Interface) busses
1778
1779 SPI busses can be described with a node for the SPI master device
1780 and a set of child nodes for each SPI slave on the bus. For this
1781 discussion, it is assumed that the system's SPI controller is in
1782 SPI master mode. This binding does not describe SPI controllers
1783 in slave mode.
1784
1785 The SPI master node requires the following properties:
1786 - #address-cells - number of cells required to define a chip select
1787 address on the SPI bus.
1788 - #size-cells - should be zero.
1789 - compatible - name of SPI bus controller following generic names
1790 recommended practice.
1791 No other properties are required in the SPI bus node. It is assumed
1792 that a driver for an SPI bus device will understand that it is an SPI bus.
1793 However, the binding does not attempt to define the specific method for
1794 assigning chip select numbers. Since SPI chip select configuration is
1795 flexible and non-standardized, it is left out of this binding with the
1796 assumption that board specific platform code will be used to manage
1797 chip selects. Individual drivers can define additional properties to
1798 support describing the chip select layout.
1799
1800 SPI slave nodes must be children of the SPI master node and can
1801 contain the following properties.
1802 - reg - (required) chip select address of device.
1803 - compatible - (required) name of SPI device following generic names
1804 recommended practice
1805 - spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz
1806 - spi-cpol - (optional) Empty property indicating device requires
1807 inverse clock polarity (CPOL) mode
1808 - spi-cpha - (optional) Empty property indicating device requires
1809 shifted clock phase (CPHA) mode
1810 - spi-cs-high - (optional) Empty property indicating device requires
1811 chip select active high
1812
1813 SPI example for an MPC5200 SPI bus:
1814 spi@f00 {
1815 #address-cells = <1>;
1816 #size-cells = <0>;
1817 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
1818 reg = <0xf00 0x20>;
1819 interrupts = <2 13 0 2 14 0>;
1820 interrupt-parent = <&mpc5200_pic>;
1821
1822 ethernet-switch@0 {
1823 compatible = "micrel,ks8995m";
1824 spi-max-frequency = <1000000>;
1825 reg = <0>;
1826 };
1827
1828 codec@1 {
1829 compatible = "ti,tlv320aic26";
1830 spi-max-frequency = <100000>;
1831 reg = <1>;
1832 };
1833 };
1834
1835VII - Marvell Discovery mv64[345]6x System Controller chips
1836===========================================================
1837
1838The Marvell mv64[345]60 series of system controller chips contain
1839many of the peripherals needed to implement a complete computer
1840system. In this section, we define device tree nodes to describe
1841the system controller chip itself and each of the peripherals
1842which it contains. Compatible string values for each node are
1843prefixed with the string "marvell,", for Marvell Technology Group Ltd.
1844
18451) The /system-controller node
1846
1847 This node is used to represent the system-controller and must be
1848 present when the system uses a system controller chip. The top-level
1849 system-controller node contains information that is global to all
1850 devices within the system controller chip. The node name begins
1851 with "system-controller" followed by the unit address, which is
1852 the base address of the memory-mapped register set for the system
1853 controller chip.
1854
1855 Required properties:
1856
1857 - ranges : Describes the translation of system controller addresses
1858 for memory mapped registers.
1859 - clock-frequency: Contains the main clock frequency for the system
1860 controller chip.
1861 - reg : This property defines the address and size of the
1862 memory-mapped registers contained within the system controller
1863 chip. The address specified in the "reg" property should match
1864 the unit address of the system-controller node.
1865 - #address-cells : Address representation for system controller
1866 devices. This field represents the number of cells needed to
1867 represent the address of the memory-mapped registers of devices
1868 within the system controller chip.
1869 - #size-cells : Size representation for for the memory-mapped
1870 registers within the system controller chip.
1871 - #interrupt-cells : Defines the width of cells used to represent
1872 interrupts.
1873
1874 Optional properties:
1875
1876 - model : The specific model of the system controller chip. Such
1877 as, "mv64360", "mv64460", or "mv64560".
1878 - compatible : A string identifying the compatibility identifiers
1879 of the system controller chip.
1880
1881 The system-controller node contains child nodes for each system
1882 controller device that the platform uses. Nodes should not be created
1883 for devices which exist on the system controller chip but are not used
1884
1885 Example Marvell Discovery mv64360 system-controller node:
1886
1887 system-controller@f1000000 { /* Marvell Discovery mv64360 */
1888 #address-cells = <1>;
1889 #size-cells = <1>;
1890 model = "mv64360"; /* Default */
1891 compatible = "marvell,mv64360";
1892 clock-frequency = <133333333>;
1893 reg = <0xf1000000 0x10000>;
1894 virtual-reg = <0xf1000000>;
1895 ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
1896 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
1897 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
1898 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
1899 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
1900
1901 [ child node definitions... ]
1902 }
1903
19042) Child nodes of /system-controller
1905
1906 a) Marvell Discovery MDIO bus
1907
1908 The MDIO is a bus to which the PHY devices are connected. For each
1909 device that exists on this bus, a child node should be created. See
1910 the definition of the PHY node below for an example of how to define
1911 a PHY.
1912
1913 Required properties:
1914 - #address-cells : Should be <1>
1915 - #size-cells : Should be <0>
1916 - device_type : Should be "mdio"
1917 - compatible : Should be "marvell,mv64360-mdio"
1918
1919 Example:
1920
1921 mdio {
1922 #address-cells = <1>;
1923 #size-cells = <0>;
1924 device_type = "mdio";
1925 compatible = "marvell,mv64360-mdio";
1926
1927 ethernet-phy@0 {
1928 ......
1929 };
1930 };
1931
1932
1933 b) Marvell Discovery ethernet controller
1934
1935 The Discover ethernet controller is described with two levels
1936 of nodes. The first level describes an ethernet silicon block
1937 and the second level describes up to 3 ethernet nodes within
1938 that block. The reason for the multiple levels is that the
1939 registers for the node are interleaved within a single set
1940 of registers. The "ethernet-block" level describes the
1941 shared register set, and the "ethernet" nodes describe ethernet
1942 port-specific properties.
1943
1944 Ethernet block node
1945
1946 Required properties:
1947 - #address-cells : <1>
1948 - #size-cells : <0>
1949 - compatible : "marvell,mv64360-eth-block"
1950 - reg : Offset and length of the register set for this block
1951
1952 Example Discovery Ethernet block node:
1953 ethernet-block@2000 {
1954 #address-cells = <1>;
1955 #size-cells = <0>;
1956 compatible = "marvell,mv64360-eth-block";
1957 reg = <0x2000 0x2000>;
1958 ethernet@0 {
1959 .......
1960 };
1961 };
1962
1963 Ethernet port node
1964
1965 Required properties:
1966 - device_type : Should be "network".
1967 - compatible : Should be "marvell,mv64360-eth".
1968 - reg : Should be <0>, <1>, or <2>, according to which registers
1969 within the silicon block the device uses.
1970 - interrupts : <a> where a is the interrupt number for the port.
1971 - interrupt-parent : the phandle for the interrupt controller
1972 that services interrupts for this device.
1973 - phy : the phandle for the PHY connected to this ethernet
1974 controller.
1975 - local-mac-address : 6 bytes, MAC address
1976
1977 Example Discovery Ethernet port node:
1978 ethernet@0 {
1979 device_type = "network";
1980 compatible = "marvell,mv64360-eth";
1981 reg = <0>;
1982 interrupts = <32>;
1983 interrupt-parent = <&PIC>;
1984 phy = <&PHY0>;
1985 local-mac-address = [ 00 00 00 00 00 00 ];
1986 };
1987
1988
1989
1990 c) Marvell Discovery PHY nodes
1991
1992 Required properties:
1993 - device_type : Should be "ethernet-phy"
1994 - interrupts : <a> where a is the interrupt number for this phy.
1995 - interrupt-parent : the phandle for the interrupt controller that
1996 services interrupts for this device.
1997 - reg : The ID number for the phy, usually a small integer
1998
1999 Example Discovery PHY node:
2000 ethernet-phy@1 {
2001 device_type = "ethernet-phy";
2002 compatible = "broadcom,bcm5421";
2003 interrupts = <76>; /* GPP 12 */
2004 interrupt-parent = <&PIC>;
2005 reg = <1>;
2006 };
2007
2008
2009 d) Marvell Discovery SDMA nodes
2010
2011 Represent DMA hardware associated with the MPSC (multiprotocol
2012 serial controllers).
2013
2014 Required properties:
2015 - compatible : "marvell,mv64360-sdma"
2016 - reg : Offset and length of the register set for this device
2017 - interrupts : <a> where a is the interrupt number for the DMA
2018 device.
2019 - interrupt-parent : the phandle for the interrupt controller
2020 that services interrupts for this device.
2021
2022 Example Discovery SDMA node:
2023 sdma@4000 {
2024 compatible = "marvell,mv64360-sdma";
2025 reg = <0x4000 0xc18>;
2026 virtual-reg = <0xf1004000>;
2027 interrupts = <36>;
2028 interrupt-parent = <&PIC>;
2029 };
2030
2031
2032 e) Marvell Discovery BRG nodes
2033
2034 Represent baud rate generator hardware associated with the MPSC
2035 (multiprotocol serial controllers).
2036
2037 Required properties:
2038 - compatible : "marvell,mv64360-brg"
2039 - reg : Offset and length of the register set for this device
2040 - clock-src : A value from 0 to 15 which selects the clock
2041 source for the baud rate generator. This value corresponds
2042 to the CLKS value in the BRGx configuration register. See
2043 the mv64x60 User's Manual.
2044 - clock-frequence : The frequency (in Hz) of the baud rate
2045 generator's input clock.
2046 - current-speed : The current speed setting (presumably by
2047 firmware) of the baud rate generator.
2048
2049 Example Discovery BRG node:
2050 brg@b200 {
2051 compatible = "marvell,mv64360-brg";
2052 reg = <0xb200 0x8>;
2053 clock-src = <8>;
2054 clock-frequency = <133333333>;
2055 current-speed = <9600>;
2056 };
2057
2058
2059 f) Marvell Discovery CUNIT nodes
2060
2061 Represent the Serial Communications Unit device hardware.
2062
2063 Required properties:
2064 - reg : Offset and length of the register set for this device
2065
2066 Example Discovery CUNIT node:
2067 cunit@f200 {
2068 reg = <0xf200 0x200>;
2069 };
2070
2071
2072 g) Marvell Discovery MPSCROUTING nodes
2073
2074 Represent the Discovery's MPSC routing hardware
2075
2076 Required properties:
2077 - reg : Offset and length of the register set for this device
2078
2079 Example Discovery CUNIT node:
2080 mpscrouting@b500 {
2081 reg = <0xb400 0xc>;
2082 };
2083
2084
2085 h) Marvell Discovery MPSCINTR nodes
2086
2087 Represent the Discovery's MPSC DMA interrupt hardware registers
2088 (SDMA cause and mask registers).
2089
2090 Required properties:
2091 - reg : Offset and length of the register set for this device
2092
2093 Example Discovery MPSCINTR node:
2094 mpsintr@b800 {
2095 reg = <0xb800 0x100>;
2096 };
2097
2098
2099 i) Marvell Discovery MPSC nodes
2100
2101 Represent the Discovery's MPSC (Multiprotocol Serial Controller)
2102 serial port.
2103
2104 Required properties:
2105 - device_type : "serial"
2106 - compatible : "marvell,mv64360-mpsc"
2107 - reg : Offset and length of the register set for this device
2108 - sdma : the phandle for the SDMA node used by this port
2109 - brg : the phandle for the BRG node used by this port
2110 - cunit : the phandle for the CUNIT node used by this port
2111 - mpscrouting : the phandle for the MPSCROUTING node used by this port
2112 - mpscintr : the phandle for the MPSCINTR node used by this port
2113 - cell-index : the hardware index of this cell in the MPSC core
2114 - max_idle : value needed for MPSC CHR3 (Maximum Frame Length)
2115 register
2116 - interrupts : <a> where a is the interrupt number for the MPSC.
2117 - interrupt-parent : the phandle for the interrupt controller
2118 that services interrupts for this device.
2119
2120 Example Discovery MPSCINTR node:
2121 mpsc@8000 {
2122 device_type = "serial";
2123 compatible = "marvell,mv64360-mpsc";
2124 reg = <0x8000 0x38>;
2125 virtual-reg = <0xf1008000>;
2126 sdma = <&SDMA0>;
2127 brg = <&BRG0>;
2128 cunit = <&CUNIT>;
2129 mpscrouting = <&MPSCROUTING>;
2130 mpscintr = <&MPSCINTR>;
2131 cell-index = <0>;
2132 max_idle = <40>;
2133 interrupts = <40>;
2134 interrupt-parent = <&PIC>;
2135 };
2136
2137
2138 j) Marvell Discovery Watch Dog Timer nodes
2139
2140 Represent the Discovery's watchdog timer hardware
2141
2142 Required properties:
2143 - compatible : "marvell,mv64360-wdt"
2144 - reg : Offset and length of the register set for this device
2145
2146 Example Discovery Watch Dog Timer node:
2147 wdt@b410 {
2148 compatible = "marvell,mv64360-wdt";
2149 reg = <0xb410 0x8>;
2150 };
2151
2152
2153 k) Marvell Discovery I2C nodes
2154
2155 Represent the Discovery's I2C hardware
2156
2157 Required properties:
2158 - device_type : "i2c"
2159 - compatible : "marvell,mv64360-i2c"
2160 - reg : Offset and length of the register set for this device
2161 - interrupts : <a> where a is the interrupt number for the I2C.
2162 - interrupt-parent : the phandle for the interrupt controller
2163 that services interrupts for this device.
2164
2165 Example Discovery I2C node:
2166 compatible = "marvell,mv64360-i2c";
2167 reg = <0xc000 0x20>;
2168 virtual-reg = <0xf100c000>;
2169 interrupts = <37>;
2170 interrupt-parent = <&PIC>;
2171 };
2172
2173
2174 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
2175
2176 Represent the Discovery's PIC hardware
2177
2178 Required properties:
2179 - #interrupt-cells : <1>
2180 - #address-cells : <0>
2181 - compatible : "marvell,mv64360-pic"
2182 - reg : Offset and length of the register set for this device
2183 - interrupt-controller
2184
2185 Example Discovery PIC node:
2186 pic {
2187 #interrupt-cells = <1>;
2188 #address-cells = <0>;
2189 compatible = "marvell,mv64360-pic";
2190 reg = <0x0 0x88>;
2191 interrupt-controller;
2192 };
2193
2194
2195 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
2196
2197 Represent the Discovery's MPP hardware
2198
2199 Required properties:
2200 - compatible : "marvell,mv64360-mpp"
2201 - reg : Offset and length of the register set for this device
2202
2203 Example Discovery MPP node:
2204 mpp@f000 {
2205 compatible = "marvell,mv64360-mpp";
2206 reg = <0xf000 0x10>;
2207 };
2208
2209
2210 n) Marvell Discovery GPP (General Purpose Pins) nodes
2211
2212 Represent the Discovery's GPP hardware
2213
2214 Required properties:
2215 - compatible : "marvell,mv64360-gpp"
2216 - reg : Offset and length of the register set for this device
2217
2218 Example Discovery GPP node:
2219 gpp@f000 {
2220 compatible = "marvell,mv64360-gpp";
2221 reg = <0xf100 0x20>;
2222 };
2223
2224
2225 o) Marvell Discovery PCI host bridge node
2226
2227 Represents the Discovery's PCI host bridge device. The properties
2228 for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE
2229 1275-1994. A typical value for the compatible property is
2230 "marvell,mv64360-pci".
2231
2232 Example Discovery PCI host bridge node
2233 pci@80000000 {
2234 #address-cells = <3>;
2235 #size-cells = <2>;
2236 #interrupt-cells = <1>;
2237 device_type = "pci";
2238 compatible = "marvell,mv64360-pci";
2239 reg = <0xcf8 0x8>;
2240 ranges = <0x01000000 0x0 0x0
2241 0x88000000 0x0 0x01000000
2242 0x02000000 0x0 0x80000000
2243 0x80000000 0x0 0x08000000>;
2244 bus-range = <0 255>;
2245 clock-frequency = <66000000>;
2246 interrupt-parent = <&PIC>;
2247 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
2248 interrupt-map = <
2249 /* IDSEL 0x0a */
2250 0x5000 0 0 1 &PIC 80
2251 0x5000 0 0 2 &PIC 81
2252 0x5000 0 0 3 &PIC 91
2253 0x5000 0 0 4 &PIC 93
2254
2255 /* IDSEL 0x0b */
2256 0x5800 0 0 1 &PIC 91
2257 0x5800 0 0 2 &PIC 93
2258 0x5800 0 0 3 &PIC 80
2259 0x5800 0 0 4 &PIC 81
2260
2261 /* IDSEL 0x0c */
2262 0x6000 0 0 1 &PIC 91
2263 0x6000 0 0 2 &PIC 93
2264 0x6000 0 0 3 &PIC 80
2265 0x6000 0 0 4 &PIC 81
2266
2267 /* IDSEL 0x0d */
2268 0x6800 0 0 1 &PIC 93
2269 0x6800 0 0 2 &PIC 80
2270 0x6800 0 0 3 &PIC 81
2271 0x6800 0 0 4 &PIC 91
2272 >;
2273 };
2274
2275
2276 p) Marvell Discovery CPU Error nodes
2277
2278 Represent the Discovery's CPU error handler device.
2279
2280 Required properties:
2281 - compatible : "marvell,mv64360-cpu-error"
2282 - reg : Offset and length of the register set for this device
2283 - interrupts : the interrupt number for this device
2284 - interrupt-parent : the phandle for the interrupt controller
2285 that services interrupts for this device.
2286
2287 Example Discovery CPU Error node:
2288 cpu-error@0070 {
2289 compatible = "marvell,mv64360-cpu-error";
2290 reg = <0x70 0x10 0x128 0x28>;
2291 interrupts = <3>;
2292 interrupt-parent = <&PIC>;
2293 };
2294
2295
2296 q) Marvell Discovery SRAM Controller nodes
2297
2298 Represent the Discovery's SRAM controller device.
2299
2300 Required properties:
2301 - compatible : "marvell,mv64360-sram-ctrl"
2302 - reg : Offset and length of the register set for this device
2303 - interrupts : the interrupt number for this device
2304 - interrupt-parent : the phandle for the interrupt controller
2305 that services interrupts for this device.
2306
2307 Example Discovery SRAM Controller node:
2308 sram-ctrl@0380 {
2309 compatible = "marvell,mv64360-sram-ctrl";
2310 reg = <0x380 0x80>;
2311 interrupts = <13>;
2312 interrupt-parent = <&PIC>;
2313 };
2314
2315
2316 r) Marvell Discovery PCI Error Handler nodes
2317
2318 Represent the Discovery's PCI error handler device.
2319
2320 Required properties:
2321 - compatible : "marvell,mv64360-pci-error"
2322 - reg : Offset and length of the register set for this device
2323 - interrupts : the interrupt number for this device
2324 - interrupt-parent : the phandle for the interrupt controller
2325 that services interrupts for this device.
2326
2327 Example Discovery PCI Error Handler node:
2328 pci-error@1d40 {
2329 compatible = "marvell,mv64360-pci-error";
2330 reg = <0x1d40 0x40 0xc28 0x4>;
2331 interrupts = <12>;
2332 interrupt-parent = <&PIC>;
2333 };
2334
2335
2336 s) Marvell Discovery Memory Controller nodes
2337
2338 Represent the Discovery's memory controller device.
2339
2340 Required properties:
2341 - compatible : "marvell,mv64360-mem-ctrl"
2342 - reg : Offset and length of the register set for this device
2343 - interrupts : the interrupt number for this device
2344 - interrupt-parent : the phandle for the interrupt controller
2345 that services interrupts for this device.
2346
2347 Example Discovery Memory Controller node:
2348 mem-ctrl@1400 {
2349 compatible = "marvell,mv64360-mem-ctrl";
2350 reg = <0x1400 0x60>;
2351 interrupts = <17>;
2352 interrupt-parent = <&PIC>;
2353 };
2354
2355
2356VIII - Specifying interrupt information for devices
2357=================================================== 1242===================================================
2358 1243
2359The device tree represents the busses and devices of a hardware 1244The device tree represents the busses and devices of a hardware
@@ -2439,56 +1324,7 @@ encodings listed below:
2439 2 = high to low edge sensitive type enabled 1324 2 = high to low edge sensitive type enabled
2440 3 = low to high edge sensitive type enabled 1325 3 = low to high edge sensitive type enabled
2441 1326
2442IX - Specifying GPIO information for devices 1327VIII - Specifying Device Power Management Information (sleep property)
2443============================================
2444
24451) gpios property
2446-----------------
2447
2448Nodes that makes use of GPIOs should define them using `gpios' property,
2449format of which is: <&gpio-controller1-phandle gpio1-specifier
2450 &gpio-controller2-phandle gpio2-specifier
2451 0 /* holes are permitted, means no GPIO 3 */
2452 &gpio-controller4-phandle gpio4-specifier
2453 ...>;
2454
2455Note that gpio-specifier length is controller dependent.
2456
2457gpio-specifier may encode: bank, pin position inside the bank,
2458whether pin is open-drain and whether pin is logically inverted.
2459
2460Example of the node using GPIOs:
2461
2462 node {
2463 gpios = <&qe_pio_e 18 0>;
2464 };
2465
2466In this example gpio-specifier is "18 0" and encodes GPIO pin number,
2467and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
2468
24692) gpio-controller nodes
2470------------------------
2471
2472Every GPIO controller node must have #gpio-cells property defined,
2473this information will be used to translate gpio-specifiers.
2474
2475Example of two SOC GPIO banks defined as gpio-controller nodes:
2476
2477 qe_pio_a: gpio-controller@1400 {
2478 #gpio-cells = <2>;
2479 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
2480 reg = <0x1400 0x18>;
2481 gpio-controller;
2482 };
2483
2484 qe_pio_e: gpio-controller@1460 {
2485 #gpio-cells = <2>;
2486 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
2487 reg = <0x1460 0x18>;
2488 gpio-controller;
2489 };
2490
2491X - Specifying Device Power Management Information (sleep property)
2492=================================================================== 1328===================================================================
2493 1329
2494Devices on SOCs often have mechanisms for placing devices into low-power 1330Devices on SOCs often have mechanisms for placing devices into low-power
diff --git a/Documentation/powerpc/dts-bindings/4xx/emac.txt b/Documentation/powerpc/dts-bindings/4xx/emac.txt
new file mode 100644
index 000000000000..2161334a7ca5
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/4xx/emac.txt
@@ -0,0 +1,148 @@
1 4xx/Axon EMAC ethernet nodes
2
3 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
4 the Axon bridge. To operate this needs to interact with a ths
5 special McMAL DMA controller, and sometimes an RGMII or ZMII
6 interface. In addition to the nodes and properties described
7 below, the node for the OPB bus on which the EMAC sits must have a
8 correct clock-frequency property.
9
10 i) The EMAC node itself
11
12 Required properties:
13 - device_type : "network"
14
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
17 405gp, Axon) and second is either "ibm,emac" or
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
19 "ibm,emac4"
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - interrupt-parent : optional, if needed for interrupt mapping
22 - reg : <registers mapping>
23 - local-mac-address : 6 bytes, MAC address
24 - mal-device : phandle of the associated McMAL node
25 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
26 with this EMAC
27 - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
28 with this EMAC
29 - cell-index : 1 cell, hardware index of the EMAC cell on a given
30 ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
31 each Axon chip)
32 - max-frame-size : 1 cell, maximum frame size supported in bytes
33 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
34 operations.
35 For Axon, 2048
36 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
37 operations.
38 For Axon, 2048.
39 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
40 thresholds).
41 For Axon, 0x00000010
42 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
43 in bytes.
44 For Axon, 0x00000100 (I think ...)
45 - phy-mode : string, mode of operations of the PHY interface.
46 Supported values are: "mii", "rmii", "smii", "rgmii",
47 "tbi", "gmii", rtbi", "sgmii".
48 For Axon on CAB, it is "rgmii"
49 - mdio-device : 1 cell, required iff using shared MDIO registers
50 (440EP). phandle of the EMAC to use to drive the
51 MDIO lines for the PHY used by this EMAC.
52 - zmii-device : 1 cell, required iff connected to a ZMII. phandle of
53 the ZMII device node
54 - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII
55 channel or 0xffffffff if ZMII is only used for MDIO.
56 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
57 of the RGMII device node.
58 For Axon: phandle of plb5/plb4/opb/rgmii
59 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
60 RGMII channel is used by this EMAC.
61 Fox Axon: present, whatever value is appropriate for each
62 EMAC, that is the content of the current (bogus) "phy-port"
63 property.
64
65 Optional properties:
66 - phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
67 a search is performed.
68 - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY
69 for, used if phy-address is absent. bit 0x00000001 is
70 MDIO address 0.
71 For Axon it can be absent, though my current driver
72 doesn't handle phy-address yet so for now, keep
73 0x00ffffff in it.
74 - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
75 operations (if absent the value is the same as
76 rx-fifo-size). For Axon, either absent or 2048.
77 - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
78 operations (if absent the value is the same as
79 tx-fifo-size). For Axon, either absent or 2048.
80 - tah-device : 1 cell, optional. If connected to a TAH engine for
81 offload, phandle of the TAH device node.
82 - tah-channel : 1 cell, optional. If appropriate, channel used on the
83 TAH engine.
84
85 Example:
86
87 EMAC0: ethernet@40000800 {
88 device_type = "network";
89 compatible = "ibm,emac-440gp", "ibm,emac";
90 interrupt-parent = <&UIC1>;
91 interrupts = <1c 4 1d 4>;
92 reg = <40000800 70>;
93 local-mac-address = [00 04 AC E3 1B 1E];
94 mal-device = <&MAL0>;
95 mal-tx-channel = <0 1>;
96 mal-rx-channel = <0>;
97 cell-index = <0>;
98 max-frame-size = <5dc>;
99 rx-fifo-size = <1000>;
100 tx-fifo-size = <800>;
101 phy-mode = "rmii";
102 phy-map = <00000001>;
103 zmii-device = <&ZMII0>;
104 zmii-channel = <0>;
105 };
106
107 ii) McMAL node
108
109 Required properties:
110 - device_type : "dma-controller"
111 - compatible : compatible list, containing 2 entries, first is
112 "ibm,mcmal-CHIP" where CHIP is the host ASIC (like
113 emac) and the second is either "ibm,mcmal" or
114 "ibm,mcmal2".
115 For Axon, "ibm,mcmal-axon","ibm,mcmal2"
116 - interrupts : <interrupt mapping for the MAL interrupts sources:
117 5 sources: tx_eob, rx_eob, serr, txde, rxde>.
118 For Axon: This is _different_ from the current
119 firmware. We use the "delayed" interrupts for txeob
120 and rxeob. Thus we end up with mapping those 5 MPIC
121 interrupts, all level positive sensitive: 10, 11, 32,
122 33, 34 (in decimal)
123 - dcr-reg : < DCR registers range >
124 - dcr-parent : if needed for dcr-reg
125 - num-tx-chans : 1 cell, number of Tx channels
126 - num-rx-chans : 1 cell, number of Rx channels
127
128 iii) ZMII node
129
130 Required properties:
131 - compatible : compatible list, containing 2 entries, first is
132 "ibm,zmii-CHIP" where CHIP is the host ASIC (like
133 EMAC) and the second is "ibm,zmii".
134 For Axon, there is no ZMII node.
135 - reg : <registers mapping>
136
137 iv) RGMII node
138
139 Required properties:
140 - compatible : compatible list, containing 2 entries, first is
141 "ibm,rgmii-CHIP" where CHIP is the host ASIC (like
142 EMAC) and the second is "ibm,rgmii".
143 For Axon, "ibm,rgmii-axon","ibm,rgmii"
144 - reg : <registers mapping>
145 - revision : as provided by the RGMII new version register if
146 available.
147 For Axon: 0x0000012a
148
diff --git a/Documentation/powerpc/dts-bindings/gpio/gpio.txt b/Documentation/powerpc/dts-bindings/gpio/gpio.txt
new file mode 100644
index 000000000000..edaa84d288a1
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/gpio/gpio.txt
@@ -0,0 +1,50 @@
1Specifying GPIO information for devices
2============================================
3
41) gpios property
5-----------------
6
7Nodes that makes use of GPIOs should define them using `gpios' property,
8format of which is: <&gpio-controller1-phandle gpio1-specifier
9 &gpio-controller2-phandle gpio2-specifier
10 0 /* holes are permitted, means no GPIO 3 */
11 &gpio-controller4-phandle gpio4-specifier
12 ...>;
13
14Note that gpio-specifier length is controller dependent.
15
16gpio-specifier may encode: bank, pin position inside the bank,
17whether pin is open-drain and whether pin is logically inverted.
18
19Example of the node using GPIOs:
20
21 node {
22 gpios = <&qe_pio_e 18 0>;
23 };
24
25In this example gpio-specifier is "18 0" and encodes GPIO pin number,
26and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
27
282) gpio-controller nodes
29------------------------
30
31Every GPIO controller node must have #gpio-cells property defined,
32this information will be used to translate gpio-specifiers.
33
34Example of two SOC GPIO banks defined as gpio-controller nodes:
35
36 qe_pio_a: gpio-controller@1400 {
37 #gpio-cells = <2>;
38 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
39 reg = <0x1400 0x18>;
40 gpio-controller;
41 };
42
43 qe_pio_e: gpio-controller@1460 {
44 #gpio-cells = <2>;
45 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
46 reg = <0x1460 0x18>;
47 gpio-controller;
48 };
49
50
diff --git a/Documentation/powerpc/dts-bindings/gpio/mdio.txt b/Documentation/powerpc/dts-bindings/gpio/mdio.txt
new file mode 100644
index 000000000000..bc9549529014
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/gpio/mdio.txt
@@ -0,0 +1,19 @@
1MDIO on GPIOs
2
3Currently defined compatibles:
4- virtual,gpio-mdio
5
6MDC and MDIO lines connected to GPIO controllers are listed in the
7gpios property as described in section VIII.1 in the following order:
8
9MDC, MDIO.
10
11Example:
12
13mdio {
14 compatible = "virtual,mdio-gpio";
15 #address-cells = <1>;
16 #size-cells = <0>;
17 gpios = <&qe_pio_a 11
18 &qe_pio_c 6>;
19};
diff --git a/Documentation/powerpc/dts-bindings/marvell.txt b/Documentation/powerpc/dts-bindings/marvell.txt
new file mode 100644
index 000000000000..3708a2fd4747
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/marvell.txt
@@ -0,0 +1,521 @@
1Marvell Discovery mv64[345]6x System Controller chips
2===========================================================
3
4The Marvell mv64[345]60 series of system controller chips contain
5many of the peripherals needed to implement a complete computer
6system. In this section, we define device tree nodes to describe
7the system controller chip itself and each of the peripherals
8which it contains. Compatible string values for each node are
9prefixed with the string "marvell,", for Marvell Technology Group Ltd.
10
111) The /system-controller node
12
13 This node is used to represent the system-controller and must be
14 present when the system uses a system controller chip. The top-level
15 system-controller node contains information that is global to all
16 devices within the system controller chip. The node name begins
17 with "system-controller" followed by the unit address, which is
18 the base address of the memory-mapped register set for the system
19 controller chip.
20
21 Required properties:
22
23 - ranges : Describes the translation of system controller addresses
24 for memory mapped registers.
25 - clock-frequency: Contains the main clock frequency for the system
26 controller chip.
27 - reg : This property defines the address and size of the
28 memory-mapped registers contained within the system controller
29 chip. The address specified in the "reg" property should match
30 the unit address of the system-controller node.
31 - #address-cells : Address representation for system controller
32 devices. This field represents the number of cells needed to
33 represent the address of the memory-mapped registers of devices
34 within the system controller chip.
35 - #size-cells : Size representation for for the memory-mapped
36 registers within the system controller chip.
37 - #interrupt-cells : Defines the width of cells used to represent
38 interrupts.
39
40 Optional properties:
41
42 - model : The specific model of the system controller chip. Such
43 as, "mv64360", "mv64460", or "mv64560".
44 - compatible : A string identifying the compatibility identifiers
45 of the system controller chip.
46
47 The system-controller node contains child nodes for each system
48 controller device that the platform uses. Nodes should not be created
49 for devices which exist on the system controller chip but are not used
50
51 Example Marvell Discovery mv64360 system-controller node:
52
53 system-controller@f1000000 { /* Marvell Discovery mv64360 */
54 #address-cells = <1>;
55 #size-cells = <1>;
56 model = "mv64360"; /* Default */
57 compatible = "marvell,mv64360";
58 clock-frequency = <133333333>;
59 reg = <0xf1000000 0x10000>;
60 virtual-reg = <0xf1000000>;
61 ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
62 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
63 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
64 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
65 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
66
67 [ child node definitions... ]
68 }
69
702) Child nodes of /system-controller
71
72 a) Marvell Discovery MDIO bus
73
74 The MDIO is a bus to which the PHY devices are connected. For each
75 device that exists on this bus, a child node should be created. See
76 the definition of the PHY node below for an example of how to define
77 a PHY.
78
79 Required properties:
80 - #address-cells : Should be <1>
81 - #size-cells : Should be <0>
82 - device_type : Should be "mdio"
83 - compatible : Should be "marvell,mv64360-mdio"
84
85 Example:
86
87 mdio {
88 #address-cells = <1>;
89 #size-cells = <0>;
90 device_type = "mdio";
91 compatible = "marvell,mv64360-mdio";
92
93 ethernet-phy@0 {
94 ......
95 };
96 };
97
98
99 b) Marvell Discovery ethernet controller
100
101 The Discover ethernet controller is described with two levels
102 of nodes. The first level describes an ethernet silicon block
103 and the second level describes up to 3 ethernet nodes within
104 that block. The reason for the multiple levels is that the
105 registers for the node are interleaved within a single set
106 of registers. The "ethernet-block" level describes the
107 shared register set, and the "ethernet" nodes describe ethernet
108 port-specific properties.
109
110 Ethernet block node
111
112 Required properties:
113 - #address-cells : <1>
114 - #size-cells : <0>
115 - compatible : "marvell,mv64360-eth-block"
116 - reg : Offset and length of the register set for this block
117
118 Example Discovery Ethernet block node:
119 ethernet-block@2000 {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 compatible = "marvell,mv64360-eth-block";
123 reg = <0x2000 0x2000>;
124 ethernet@0 {
125 .......
126 };
127 };
128
129 Ethernet port node
130
131 Required properties:
132 - device_type : Should be "network".
133 - compatible : Should be "marvell,mv64360-eth".
134 - reg : Should be <0>, <1>, or <2>, according to which registers
135 within the silicon block the device uses.
136 - interrupts : <a> where a is the interrupt number for the port.
137 - interrupt-parent : the phandle for the interrupt controller
138 that services interrupts for this device.
139 - phy : the phandle for the PHY connected to this ethernet
140 controller.
141 - local-mac-address : 6 bytes, MAC address
142
143 Example Discovery Ethernet port node:
144 ethernet@0 {
145 device_type = "network";
146 compatible = "marvell,mv64360-eth";
147 reg = <0>;
148 interrupts = <32>;
149 interrupt-parent = <&PIC>;
150 phy = <&PHY0>;
151 local-mac-address = [ 00 00 00 00 00 00 ];
152 };
153
154
155
156 c) Marvell Discovery PHY nodes
157
158 Required properties:
159 - device_type : Should be "ethernet-phy"
160 - interrupts : <a> where a is the interrupt number for this phy.
161 - interrupt-parent : the phandle for the interrupt controller that
162 services interrupts for this device.
163 - reg : The ID number for the phy, usually a small integer
164
165 Example Discovery PHY node:
166 ethernet-phy@1 {
167 device_type = "ethernet-phy";
168 compatible = "broadcom,bcm5421";
169 interrupts = <76>; /* GPP 12 */
170 interrupt-parent = <&PIC>;
171 reg = <1>;
172 };
173
174
175 d) Marvell Discovery SDMA nodes
176
177 Represent DMA hardware associated with the MPSC (multiprotocol
178 serial controllers).
179
180 Required properties:
181 - compatible : "marvell,mv64360-sdma"
182 - reg : Offset and length of the register set for this device
183 - interrupts : <a> where a is the interrupt number for the DMA
184 device.
185 - interrupt-parent : the phandle for the interrupt controller
186 that services interrupts for this device.
187
188 Example Discovery SDMA node:
189 sdma@4000 {
190 compatible = "marvell,mv64360-sdma";
191 reg = <0x4000 0xc18>;
192 virtual-reg = <0xf1004000>;
193 interrupts = <36>;
194 interrupt-parent = <&PIC>;
195 };
196
197
198 e) Marvell Discovery BRG nodes
199
200 Represent baud rate generator hardware associated with the MPSC
201 (multiprotocol serial controllers).
202
203 Required properties:
204 - compatible : "marvell,mv64360-brg"
205 - reg : Offset and length of the register set for this device
206 - clock-src : A value from 0 to 15 which selects the clock
207 source for the baud rate generator. This value corresponds
208 to the CLKS value in the BRGx configuration register. See
209 the mv64x60 User's Manual.
210 - clock-frequence : The frequency (in Hz) of the baud rate
211 generator's input clock.
212 - current-speed : The current speed setting (presumably by
213 firmware) of the baud rate generator.
214
215 Example Discovery BRG node:
216 brg@b200 {
217 compatible = "marvell,mv64360-brg";
218 reg = <0xb200 0x8>;
219 clock-src = <8>;
220 clock-frequency = <133333333>;
221 current-speed = <9600>;
222 };
223
224
225 f) Marvell Discovery CUNIT nodes
226
227 Represent the Serial Communications Unit device hardware.
228
229 Required properties:
230 - reg : Offset and length of the register set for this device
231
232 Example Discovery CUNIT node:
233 cunit@f200 {
234 reg = <0xf200 0x200>;
235 };
236
237
238 g) Marvell Discovery MPSCROUTING nodes
239
240 Represent the Discovery's MPSC routing hardware
241
242 Required properties:
243 - reg : Offset and length of the register set for this device
244
245 Example Discovery CUNIT node:
246 mpscrouting@b500 {
247 reg = <0xb400 0xc>;
248 };
249
250
251 h) Marvell Discovery MPSCINTR nodes
252
253 Represent the Discovery's MPSC DMA interrupt hardware registers
254 (SDMA cause and mask registers).
255
256 Required properties:
257 - reg : Offset and length of the register set for this device
258
259 Example Discovery MPSCINTR node:
260 mpsintr@b800 {
261 reg = <0xb800 0x100>;
262 };
263
264
265 i) Marvell Discovery MPSC nodes
266
267 Represent the Discovery's MPSC (Multiprotocol Serial Controller)
268 serial port.
269
270 Required properties:
271 - device_type : "serial"
272 - compatible : "marvell,mv64360-mpsc"
273 - reg : Offset and length of the register set for this device
274 - sdma : the phandle for the SDMA node used by this port
275 - brg : the phandle for the BRG node used by this port
276 - cunit : the phandle for the CUNIT node used by this port
277 - mpscrouting : the phandle for the MPSCROUTING node used by this port
278 - mpscintr : the phandle for the MPSCINTR node used by this port
279 - cell-index : the hardware index of this cell in the MPSC core
280 - max_idle : value needed for MPSC CHR3 (Maximum Frame Length)
281 register
282 - interrupts : <a> where a is the interrupt number for the MPSC.
283 - interrupt-parent : the phandle for the interrupt controller
284 that services interrupts for this device.
285
286 Example Discovery MPSCINTR node:
287 mpsc@8000 {
288 device_type = "serial";
289 compatible = "marvell,mv64360-mpsc";
290 reg = <0x8000 0x38>;
291 virtual-reg = <0xf1008000>;
292 sdma = <&SDMA0>;
293 brg = <&BRG0>;
294 cunit = <&CUNIT>;
295 mpscrouting = <&MPSCROUTING>;
296 mpscintr = <&MPSCINTR>;
297 cell-index = <0>;
298 max_idle = <40>;
299 interrupts = <40>;
300 interrupt-parent = <&PIC>;
301 };
302
303
304 j) Marvell Discovery Watch Dog Timer nodes
305
306 Represent the Discovery's watchdog timer hardware
307
308 Required properties:
309 - compatible : "marvell,mv64360-wdt"
310 - reg : Offset and length of the register set for this device
311
312 Example Discovery Watch Dog Timer node:
313 wdt@b410 {
314 compatible = "marvell,mv64360-wdt";
315 reg = <0xb410 0x8>;
316 };
317
318
319 k) Marvell Discovery I2C nodes
320
321 Represent the Discovery's I2C hardware
322
323 Required properties:
324 - device_type : "i2c"
325 - compatible : "marvell,mv64360-i2c"
326 - reg : Offset and length of the register set for this device
327 - interrupts : <a> where a is the interrupt number for the I2C.
328 - interrupt-parent : the phandle for the interrupt controller
329 that services interrupts for this device.
330
331 Example Discovery I2C node:
332 compatible = "marvell,mv64360-i2c";
333 reg = <0xc000 0x20>;
334 virtual-reg = <0xf100c000>;
335 interrupts = <37>;
336 interrupt-parent = <&PIC>;
337 };
338
339
340 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
341
342 Represent the Discovery's PIC hardware
343
344 Required properties:
345 - #interrupt-cells : <1>
346 - #address-cells : <0>
347 - compatible : "marvell,mv64360-pic"
348 - reg : Offset and length of the register set for this device
349 - interrupt-controller
350
351 Example Discovery PIC node:
352 pic {
353 #interrupt-cells = <1>;
354 #address-cells = <0>;
355 compatible = "marvell,mv64360-pic";
356 reg = <0x0 0x88>;
357 interrupt-controller;
358 };
359
360
361 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
362
363 Represent the Discovery's MPP hardware
364
365 Required properties:
366 - compatible : "marvell,mv64360-mpp"
367 - reg : Offset and length of the register set for this device
368
369 Example Discovery MPP node:
370 mpp@f000 {
371 compatible = "marvell,mv64360-mpp";
372 reg = <0xf000 0x10>;
373 };
374
375
376 n) Marvell Discovery GPP (General Purpose Pins) nodes
377
378 Represent the Discovery's GPP hardware
379
380 Required properties:
381 - compatible : "marvell,mv64360-gpp"
382 - reg : Offset and length of the register set for this device
383
384 Example Discovery GPP node:
385 gpp@f000 {
386 compatible = "marvell,mv64360-gpp";
387 reg = <0xf100 0x20>;
388 };
389
390
391 o) Marvell Discovery PCI host bridge node
392
393 Represents the Discovery's PCI host bridge device. The properties
394 for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE
395 1275-1994. A typical value for the compatible property is
396 "marvell,mv64360-pci".
397
398 Example Discovery PCI host bridge node
399 pci@80000000 {
400 #address-cells = <3>;
401 #size-cells = <2>;
402 #interrupt-cells = <1>;
403 device_type = "pci";
404 compatible = "marvell,mv64360-pci";
405 reg = <0xcf8 0x8>;
406 ranges = <0x01000000 0x0 0x0
407 0x88000000 0x0 0x01000000
408 0x02000000 0x0 0x80000000
409 0x80000000 0x0 0x08000000>;
410 bus-range = <0 255>;
411 clock-frequency = <66000000>;
412 interrupt-parent = <&PIC>;
413 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
414 interrupt-map = <
415 /* IDSEL 0x0a */
416 0x5000 0 0 1 &PIC 80
417 0x5000 0 0 2 &PIC 81
418 0x5000 0 0 3 &PIC 91
419 0x5000 0 0 4 &PIC 93
420
421 /* IDSEL 0x0b */
422 0x5800 0 0 1 &PIC 91
423 0x5800 0 0 2 &PIC 93
424 0x5800 0 0 3 &PIC 80
425 0x5800 0 0 4 &PIC 81
426
427 /* IDSEL 0x0c */
428 0x6000 0 0 1 &PIC 91
429 0x6000 0 0 2 &PIC 93
430 0x6000 0 0 3 &PIC 80
431 0x6000 0 0 4 &PIC 81
432
433 /* IDSEL 0x0d */
434 0x6800 0 0 1 &PIC 93
435 0x6800 0 0 2 &PIC 80
436 0x6800 0 0 3 &PIC 81
437 0x6800 0 0 4 &PIC 91
438 >;
439 };
440
441
442 p) Marvell Discovery CPU Error nodes
443
444 Represent the Discovery's CPU error handler device.
445
446 Required properties:
447 - compatible : "marvell,mv64360-cpu-error"
448 - reg : Offset and length of the register set for this device
449 - interrupts : the interrupt number for this device
450 - interrupt-parent : the phandle for the interrupt controller
451 that services interrupts for this device.
452
453 Example Discovery CPU Error node:
454 cpu-error@0070 {
455 compatible = "marvell,mv64360-cpu-error";
456 reg = <0x70 0x10 0x128 0x28>;
457 interrupts = <3>;
458 interrupt-parent = <&PIC>;
459 };
460
461
462 q) Marvell Discovery SRAM Controller nodes
463
464 Represent the Discovery's SRAM controller device.
465
466 Required properties:
467 - compatible : "marvell,mv64360-sram-ctrl"
468 - reg : Offset and length of the register set for this device
469 - interrupts : the interrupt number for this device
470 - interrupt-parent : the phandle for the interrupt controller
471 that services interrupts for this device.
472
473 Example Discovery SRAM Controller node:
474 sram-ctrl@0380 {
475 compatible = "marvell,mv64360-sram-ctrl";
476 reg = <0x380 0x80>;
477 interrupts = <13>;
478 interrupt-parent = <&PIC>;
479 };
480
481
482 r) Marvell Discovery PCI Error Handler nodes
483
484 Represent the Discovery's PCI error handler device.
485
486 Required properties:
487 - compatible : "marvell,mv64360-pci-error"
488 - reg : Offset and length of the register set for this device
489 - interrupts : the interrupt number for this device
490 - interrupt-parent : the phandle for the interrupt controller
491 that services interrupts for this device.
492
493 Example Discovery PCI Error Handler node:
494 pci-error@1d40 {
495 compatible = "marvell,mv64360-pci-error";
496 reg = <0x1d40 0x40 0xc28 0x4>;
497 interrupts = <12>;
498 interrupt-parent = <&PIC>;
499 };
500
501
502 s) Marvell Discovery Memory Controller nodes
503
504 Represent the Discovery's memory controller device.
505
506 Required properties:
507 - compatible : "marvell,mv64360-mem-ctrl"
508 - reg : Offset and length of the register set for this device
509 - interrupts : the interrupt number for this device
510 - interrupt-parent : the phandle for the interrupt controller
511 that services interrupts for this device.
512
513 Example Discovery Memory Controller node:
514 mem-ctrl@1400 {
515 compatible = "marvell,mv64360-mem-ctrl";
516 reg = <0x1400 0x60>;
517 interrupts = <17>;
518 interrupt-parent = <&PIC>;
519 };
520
521
diff --git a/Documentation/powerpc/dts-bindings/phy.txt b/Documentation/powerpc/dts-bindings/phy.txt
new file mode 100644
index 000000000000..bb8c742eb8c5
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/phy.txt
@@ -0,0 +1,25 @@
1PHY nodes
2
3Required properties:
4
5 - device_type : Should be "ethernet-phy"
6 - interrupts : <a b> where a is the interrupt number and b is a
7 field that represents an encoding of the sense and level
8 information for the interrupt. This should be encoded based on
9 the information in section 2) depending on the type of interrupt
10 controller you have.
11 - interrupt-parent : the phandle for the interrupt controller that
12 services interrupts for this device.
13 - reg : The ID number for the phy, usually a small integer
14 - linux,phandle : phandle for this node; likely referenced by an
15 ethernet controller node.
16
17Example:
18
19ethernet-phy@0 {
20 linux,phandle = <2452000>
21 interrupt-parent = <40000>;
22 interrupts = <35 1>;
23 reg = <0>;
24 device_type = "ethernet-phy";
25};
diff --git a/Documentation/powerpc/dts-bindings/spi-bus.txt b/Documentation/powerpc/dts-bindings/spi-bus.txt
new file mode 100644
index 000000000000..e782add2e457
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/spi-bus.txt
@@ -0,0 +1,57 @@
1SPI (Serial Peripheral Interface) busses
2
3SPI busses can be described with a node for the SPI master device
4and a set of child nodes for each SPI slave on the bus. For this
5discussion, it is assumed that the system's SPI controller is in
6SPI master mode. This binding does not describe SPI controllers
7in slave mode.
8
9The SPI master node requires the following properties:
10- #address-cells - number of cells required to define a chip select
11 address on the SPI bus.
12- #size-cells - should be zero.
13- compatible - name of SPI bus controller following generic names
14 recommended practice.
15No other properties are required in the SPI bus node. It is assumed
16that a driver for an SPI bus device will understand that it is an SPI bus.
17However, the binding does not attempt to define the specific method for
18assigning chip select numbers. Since SPI chip select configuration is
19flexible and non-standardized, it is left out of this binding with the
20assumption that board specific platform code will be used to manage
21chip selects. Individual drivers can define additional properties to
22support describing the chip select layout.
23
24SPI slave nodes must be children of the SPI master node and can
25contain the following properties.
26- reg - (required) chip select address of device.
27- compatible - (required) name of SPI device following generic names
28 recommended practice
29- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz
30- spi-cpol - (optional) Empty property indicating device requires
31 inverse clock polarity (CPOL) mode
32- spi-cpha - (optional) Empty property indicating device requires
33 shifted clock phase (CPHA) mode
34- spi-cs-high - (optional) Empty property indicating device requires
35 chip select active high
36
37SPI example for an MPC5200 SPI bus:
38 spi@f00 {
39 #address-cells = <1>;
40 #size-cells = <0>;
41 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
42 reg = <0xf00 0x20>;
43 interrupts = <2 13 0 2 14 0>;
44 interrupt-parent = <&mpc5200_pic>;
45
46 ethernet-switch@0 {
47 compatible = "micrel,ks8995m";
48 spi-max-frequency = <1000000>;
49 reg = <0>;
50 };
51
52 codec@1 {
53 compatible = "ti,tlv320aic26";
54 spi-max-frequency = <100000>;
55 reg = <1>;
56 };
57 };
diff --git a/Documentation/powerpc/dts-bindings/usb-ehci.txt b/Documentation/powerpc/dts-bindings/usb-ehci.txt
new file mode 100644
index 000000000000..fa18612f757b
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/usb-ehci.txt
@@ -0,0 +1,25 @@
1USB EHCI controllers
2
3Required properties:
4 - compatible : should be "usb-ehci".
5 - reg : should contain at least address and length of the standard EHCI
6 register set for the device. Optional platform-dependent registers
7 (debug-port or other) can be also specified here, but only after
8 definition of standard EHCI registers.
9 - interrupts : one EHCI interrupt should be described here.
10If device registers are implemented in big endian mode, the device
11node should have "big-endian-regs" property.
12If controller implementation operates with big endian descriptors,
13"big-endian-desc" property should be specified.
14If both big endian registers and descriptors are used by the controller
15implementation, "big-endian" property can be specified instead of having
16both "big-endian-regs" and "big-endian-desc".
17
18Example (Sequoia 440EPx):
19 ehci@e0000300 {
20 compatible = "ibm,usb-ehci-440epx", "usb-ehci";
21 interrupt-parent = <&UIC0>;
22 interrupts = <1a 4>;
23 reg = <0 e0000300 90 0 e0000390 70>;
24 big-endian;
25 };
diff --git a/Documentation/powerpc/dts-bindings/xilinx.txt b/Documentation/powerpc/dts-bindings/xilinx.txt
new file mode 100644
index 000000000000..80339fe4300b
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/xilinx.txt
@@ -0,0 +1,295 @@
1 d) Xilinx IP cores
2
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
4 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
5 of standard device types (network, serial, etc.) and miscellaneous
6 devices (gpio, LCD, spi, etc). Also, since these devices are
7 implemented within the fpga fabric every instance of the device can be
8 synthesised with different options that change the behaviour.
9
10 Each IP-core has a set of parameters which the FPGA designer can use to
11 control how the core is synthesized. Historically, the EDK tool would
12 extract the device parameters relevant to device drivers and copy them
13 into an 'xparameters.h' in the form of #define symbols. This tells the
14 device drivers how the IP cores are configured, but it requres the kernel
15 to be recompiled every time the FPGA bitstream is resynthesized.
16
17 The new approach is to export the parameters into the device tree and
18 generate a new device tree each time the FPGA bitstream changes. The
19 parameters which used to be exported as #defines will now become
20 properties of the device node. In general, device nodes for IP-cores
21 will take the following form:
22
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
25 [, (list of compatible devices), ...];
26 reg = <(baseaddr) (size)>;
27 interrupt-parent = <&interrupt-controller-phandle>;
28 interrupts = < ... >;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
31 };
32
33 (generic-name): an open firmware-style name that describes the
34 generic class of device. Preferably, this is one word, such
35 as 'serial' or 'ethernet'.
36 (ip-core-name): the name of the ip block (given after the BEGIN
37 directive in system.mhs). Should be in lowercase
38 and all underscores '_' converted to dashes '-'.
39 (name): is derived from the "PARAMETER INSTANCE" value.
40 (parameter#): C_* parameters from system.mhs. The C_ prefix is
41 dropped from the parameter name, the name is converted
42 to lowercase and all underscore '_' characters are
43 converted to dashes '-'.
44 (baseaddr): the baseaddr parameter value (often named C_BASEADDR).
45 (HW_VER): from the HW_VER parameter.
46 (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
47
48 Typically, the compatible list will include the exact IP core version
49 followed by an older IP core version which implements the same
50 interface or any other device with the same interface.
51
52 'reg', 'interrupt-parent' and 'interrupts' are all optional properties.
53
54 For example, the following block from system.mhs:
55
56 BEGIN opb_uartlite
57 PARAMETER INSTANCE = opb_uartlite_0
58 PARAMETER HW_VER = 1.00.b
59 PARAMETER C_BAUDRATE = 115200
60 PARAMETER C_DATA_BITS = 8
61 PARAMETER C_ODD_PARITY = 0
62 PARAMETER C_USE_PARITY = 0
63 PARAMETER C_CLK_FREQ = 50000000
64 PARAMETER C_BASEADDR = 0xEC100000
65 PARAMETER C_HIGHADDR = 0xEC10FFFF
66 BUS_INTERFACE SOPB = opb_7
67 PORT OPB_Clk = CLK_50MHz
68 PORT Interrupt = opb_uartlite_0_Interrupt
69 PORT RX = opb_uartlite_0_RX
70 PORT TX = opb_uartlite_0_TX
71 PORT OPB_Rst = sys_bus_reset_0
72 END
73
74 becomes the following device tree node:
75
76 opb_uartlite_0: serial@ec100000 {
77 device_type = "serial";
78 compatible = "xlnx,opb-uartlite-1.00.b";
79 reg = <ec100000 10000>;
80 interrupt-parent = <&opb_intc_0>;
81 interrupts = <1 0>; // got this from the opb_intc parameters
82 current-speed = <d#115200>; // standard serial device prop
83 clock-frequency = <d#50000000>; // standard serial device prop
84 xlnx,data-bits = <8>;
85 xlnx,odd-parity = <0>;
86 xlnx,use-parity = <0>;
87 };
88
89 Some IP cores actually implement 2 or more logical devices. In
90 this case, the device should still describe the whole IP core with
91 a single node and add a child node for each logical device. The
92 ranges property can be used to translate from parent IP-core to the
93 registers of each device. In addition, the parent node should be
94 compatible with the bus type 'xlnx,compound', and should contain
95 #address-cells and #size-cells, as with any other bus. (Note: this
96 makes the assumption that both logical devices have the same bus
97 binding. If this is not true, then separate nodes should be used
98 for each logical device). The 'cell-index' property can be used to
99 enumerate logical devices within an IP core. For example, the
100 following is the system.mhs entry for the dual ps2 controller found
101 on the ml403 reference design.
102
103 BEGIN opb_ps2_dual_ref
104 PARAMETER INSTANCE = opb_ps2_dual_ref_0
105 PARAMETER HW_VER = 1.00.a
106 PARAMETER C_BASEADDR = 0xA9000000
107 PARAMETER C_HIGHADDR = 0xA9001FFF
108 BUS_INTERFACE SOPB = opb_v20_0
109 PORT Sys_Intr1 = ps2_1_intr
110 PORT Sys_Intr2 = ps2_2_intr
111 PORT Clkin1 = ps2_clk_rx_1
112 PORT Clkin2 = ps2_clk_rx_2
113 PORT Clkpd1 = ps2_clk_tx_1
114 PORT Clkpd2 = ps2_clk_tx_2
115 PORT Rx1 = ps2_d_rx_1
116 PORT Rx2 = ps2_d_rx_2
117 PORT Txpd1 = ps2_d_tx_1
118 PORT Txpd2 = ps2_d_tx_2
119 END
120
121 It would result in the following device tree nodes:
122
123 opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 compatible = "xlnx,compound";
127 ranges = <0 a9000000 2000>;
128 // If this device had extra parameters, then they would
129 // go here.
130 ps2@0 {
131 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
132 reg = <0 40>;
133 interrupt-parent = <&opb_intc_0>;
134 interrupts = <3 0>;
135 cell-index = <0>;
136 };
137 ps2@1000 {
138 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
139 reg = <1000 40>;
140 interrupt-parent = <&opb_intc_0>;
141 interrupts = <3 0>;
142 cell-index = <0>;
143 };
144 };
145
146 Also, the system.mhs file defines bus attachments from the processor
147 to the devices. The device tree structure should reflect the bus
148 attachments. Again an example; this system.mhs fragment:
149
150 BEGIN ppc405_virtex4
151 PARAMETER INSTANCE = ppc405_0
152 PARAMETER HW_VER = 1.01.a
153 BUS_INTERFACE DPLB = plb_v34_0
154 BUS_INTERFACE IPLB = plb_v34_0
155 END
156
157 BEGIN opb_intc
158 PARAMETER INSTANCE = opb_intc_0
159 PARAMETER HW_VER = 1.00.c
160 PARAMETER C_BASEADDR = 0xD1000FC0
161 PARAMETER C_HIGHADDR = 0xD1000FDF
162 BUS_INTERFACE SOPB = opb_v20_0
163 END
164
165 BEGIN opb_uart16550
166 PARAMETER INSTANCE = opb_uart16550_0
167 PARAMETER HW_VER = 1.00.d
168 PARAMETER C_BASEADDR = 0xa0000000
169 PARAMETER C_HIGHADDR = 0xa0001FFF
170 BUS_INTERFACE SOPB = opb_v20_0
171 END
172
173 BEGIN plb_v34
174 PARAMETER INSTANCE = plb_v34_0
175 PARAMETER HW_VER = 1.02.a
176 END
177
178 BEGIN plb_bram_if_cntlr
179 PARAMETER INSTANCE = plb_bram_if_cntlr_0
180 PARAMETER HW_VER = 1.00.b
181 PARAMETER C_BASEADDR = 0xFFFF0000
182 PARAMETER C_HIGHADDR = 0xFFFFFFFF
183 BUS_INTERFACE SPLB = plb_v34_0
184 END
185
186 BEGIN plb2opb_bridge
187 PARAMETER INSTANCE = plb2opb_bridge_0
188 PARAMETER HW_VER = 1.01.a
189 PARAMETER C_RNG0_BASEADDR = 0x20000000
190 PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
191 PARAMETER C_RNG1_BASEADDR = 0x60000000
192 PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
193 PARAMETER C_RNG2_BASEADDR = 0x80000000
194 PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
195 PARAMETER C_RNG3_BASEADDR = 0xC0000000
196 PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
197 BUS_INTERFACE SPLB = plb_v34_0
198 BUS_INTERFACE MOPB = opb_v20_0
199 END
200
201 Gives this device tree (some properties removed for clarity):
202
203 plb@0 {
204 #address-cells = <1>;
205 #size-cells = <1>;
206 compatible = "xlnx,plb-v34-1.02.a";
207 device_type = "ibm,plb";
208 ranges; // 1:1 translation
209
210 plb_bram_if_cntrl_0: bram@ffff0000 {
211 reg = <ffff0000 10000>;
212 }
213
214 opb@20000000 {
215 #address-cells = <1>;
216 #size-cells = <1>;
217 ranges = <20000000 20000000 20000000
218 60000000 60000000 20000000
219 80000000 80000000 40000000
220 c0000000 c0000000 20000000>;
221
222 opb_uart16550_0: serial@a0000000 {
223 reg = <a00000000 2000>;
224 };
225
226 opb_intc_0: interrupt-controller@d1000fc0 {
227 reg = <d1000fc0 20>;
228 };
229 };
230 };
231
232 That covers the general approach to binding xilinx IP cores into the
233 device tree. The following are bindings for specific devices:
234
235 i) Xilinx ML300 Framebuffer
236
237 Simple framebuffer device from the ML300 reference design (also on the
238 ML403 reference design as well as others).
239
240 Optional properties:
241 - resolution = <xres yres> : pixel resolution of framebuffer. Some
242 implementations use a different resolution.
243 Default is <d#640 d#480>
244 - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
245 Default is <d#1024 d#480>.
246 - rotate-display (empty) : rotate display 180 degrees.
247
248 ii) Xilinx SystemACE
249
250 The Xilinx SystemACE device is used to program FPGAs from an FPGA
251 bitstream stored on a CF card. It can also be used as a generic CF
252 interface device.
253
254 Optional properties:
255 - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
256
257 iii) Xilinx EMAC and Xilinx TEMAC
258
259 Xilinx Ethernet devices. In addition to general xilinx properties
260 listed above, nodes for these devices should include a phy-handle
261 property, and may include other common network device properties
262 like local-mac-address.
263
264 iv) Xilinx Uartlite
265
266 Xilinx uartlite devices are simple fixed speed serial ports.
267
268 Required properties:
269 - current-speed : Baud rate of uartlite
270
271 v) Xilinx hwicap
272
273 Xilinx hwicap devices provide access to the configuration logic
274 of the FPGA through the Internal Configuration Access Port
275 (ICAP). The ICAP enables partial reconfiguration of the FPGA,
276 readback of the configuration information, and some control over
277 'warm boots' of the FPGA fabric.
278
279 Required properties:
280 - xlnx,family : The family of the FPGA, necessary since the
281 capabilities of the underlying ICAP hardware
282 differ between different families. May be
283 'virtex2p', 'virtex4', or 'virtex5'.
284
285 vi) Xilinx Uart 16550
286
287 Xilinx UART 16550 devices are very similar to the NS16550 but with
288 different register spacing and an offset from the base address.
289
290 Required properties:
291 - clock-frequency : Frequency of the clock input
292 - reg-offset : A value of 3 is required
293 - reg-shift : A value of 2 is required
294
295
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index bf6cedfa05db..d00131ca0835 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -62,7 +62,6 @@ config HAVE_LATENCYTOP_SUPPORT
62 62
63config TRACE_IRQFLAGS_SUPPORT 63config TRACE_IRQFLAGS_SUPPORT
64 bool 64 bool
65 depends on PPC64
66 default y 65 default y
67 66
68config LOCKDEP_SUPPORT 67config LOCKDEP_SUPPORT
diff --git a/arch/powerpc/boot/.gitignore b/arch/powerpc/boot/.gitignore
index 2f50acd11a60..3d80c3e9cf60 100644
--- a/arch/powerpc/boot/.gitignore
+++ b/arch/powerpc/boot/.gitignore
@@ -36,3 +36,13 @@ zImage.pseries
36zconf.h 36zconf.h
37zlib.h 37zlib.h
38zutil.h 38zutil.h
39fdt.c
40fdt.h
41fdt_ro.c
42fdt_rw.c
43fdt_strerror.c
44fdt_sw.c
45fdt_wip.c
46libfdt.h
47libfdt_internal.h
48
diff --git a/arch/powerpc/boot/dts/amigaone.dts b/arch/powerpc/boot/dts/amigaone.dts
index 26549fca2ed4..49ac36b16dd7 100644
--- a/arch/powerpc/boot/dts/amigaone.dts
+++ b/arch/powerpc/boot/dts/amigaone.dts
@@ -70,8 +70,8 @@
70 devsel-speed = <0x00000001>; 70 devsel-speed = <0x00000001>;
71 min-grant = <0>; 71 min-grant = <0>;
72 max-latency = <0>; 72 max-latency = <0>;
73 /* First 64k for I/O at 0x0 on PCI mapped to 0x0 on ISA. */ 73 /* First 4k for I/O at 0x0 on PCI mapped to 0x0 on ISA. */
74 ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00010000>; 74 ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00001000>;
75 interrupt-parent = <&i8259>; 75 interrupt-parent = <&i8259>;
76 #interrupt-cells = <2>; 76 #interrupt-cells = <2>;
77 #address-cells = <2>; 77 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
index a8dcb018c4a5..a680165292f2 100644
--- a/arch/powerpc/boot/dts/mpc8569mds.dts
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -253,6 +253,7 @@
253 /* Filled in by U-Boot */ 253 /* Filled in by U-Boot */
254 clock-frequency = <0>; 254 clock-frequency = <0>;
255 status = "disabled"; 255 status = "disabled";
256 sdhci,1-bit-only;
256 }; 257 };
257 258
258 crypto@30000 { 259 crypto@30000 {
diff --git a/arch/powerpc/include/asm/cpm1.h b/arch/powerpc/include/asm/cpm1.h
index 2ff798744c1d..7685ffde8821 100644
--- a/arch/powerpc/include/asm/cpm1.h
+++ b/arch/powerpc/include/asm/cpm1.h
@@ -598,8 +598,6 @@ typedef struct risc_timer_pram {
598#define CICR_IEN ((uint)0x00000080) /* Int. enable */ 598#define CICR_IEN ((uint)0x00000080) /* Int. enable */
599#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ 599#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
600 600
601#define IMAP_ADDR (get_immrbase())
602
603#define CPM_PIN_INPUT 0 601#define CPM_PIN_INPUT 0
604#define CPM_PIN_OUTPUT 1 602#define CPM_PIN_OUTPUT 1
605#define CPM_PIN_PRIMARY 0 603#define CPM_PIN_PRIMARY 0
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h
index 3d9e887c3c0c..b44aaabdd1a6 100644
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -309,7 +309,9 @@ static inline void dma_sync_single_for_cpu(struct device *dev,
309 struct dma_mapping_ops *dma_ops = get_dma_ops(dev); 309 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
310 310
311 BUG_ON(!dma_ops); 311 BUG_ON(!dma_ops);
312 dma_ops->sync_single_range_for_cpu(dev, dma_handle, 0, 312
313 if (dma_ops->sync_single_range_for_cpu)
314 dma_ops->sync_single_range_for_cpu(dev, dma_handle, 0,
313 size, direction); 315 size, direction);
314} 316}
315 317
@@ -320,7 +322,9 @@ static inline void dma_sync_single_for_device(struct device *dev,
320 struct dma_mapping_ops *dma_ops = get_dma_ops(dev); 322 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
321 323
322 BUG_ON(!dma_ops); 324 BUG_ON(!dma_ops);
323 dma_ops->sync_single_range_for_device(dev, dma_handle, 325
326 if (dma_ops->sync_single_range_for_device)
327 dma_ops->sync_single_range_for_device(dev, dma_handle,
324 0, size, direction); 328 0, size, direction);
325} 329}
326 330
@@ -331,7 +335,9 @@ static inline void dma_sync_sg_for_cpu(struct device *dev,
331 struct dma_mapping_ops *dma_ops = get_dma_ops(dev); 335 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
332 336
333 BUG_ON(!dma_ops); 337 BUG_ON(!dma_ops);
334 dma_ops->sync_sg_for_cpu(dev, sgl, nents, direction); 338
339 if (dma_ops->sync_sg_for_cpu)
340 dma_ops->sync_sg_for_cpu(dev, sgl, nents, direction);
335} 341}
336 342
337static inline void dma_sync_sg_for_device(struct device *dev, 343static inline void dma_sync_sg_for_device(struct device *dev,
@@ -341,7 +347,9 @@ static inline void dma_sync_sg_for_device(struct device *dev,
341 struct dma_mapping_ops *dma_ops = get_dma_ops(dev); 347 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
342 348
343 BUG_ON(!dma_ops); 349 BUG_ON(!dma_ops);
344 dma_ops->sync_sg_for_device(dev, sgl, nents, direction); 350
351 if (dma_ops->sync_sg_for_device)
352 dma_ops->sync_sg_for_device(dev, sgl, nents, direction);
345} 353}
346 354
347static inline void dma_sync_single_range_for_cpu(struct device *dev, 355static inline void dma_sync_single_range_for_cpu(struct device *dev,
@@ -351,7 +359,9 @@ static inline void dma_sync_single_range_for_cpu(struct device *dev,
351 struct dma_mapping_ops *dma_ops = get_dma_ops(dev); 359 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
352 360
353 BUG_ON(!dma_ops); 361 BUG_ON(!dma_ops);
354 dma_ops->sync_single_range_for_cpu(dev, dma_handle, 362
363 if (dma_ops->sync_single_range_for_cpu)
364 dma_ops->sync_single_range_for_cpu(dev, dma_handle,
355 offset, size, direction); 365 offset, size, direction);
356} 366}
357 367
@@ -362,7 +372,9 @@ static inline void dma_sync_single_range_for_device(struct device *dev,
362 struct dma_mapping_ops *dma_ops = get_dma_ops(dev); 372 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
363 373
364 BUG_ON(!dma_ops); 374 BUG_ON(!dma_ops);
365 dma_ops->sync_single_range_for_device(dev, dma_handle, offset, 375
376 if (dma_ops->sync_single_range_for_device)
377 dma_ops->sync_single_range_for_device(dev, dma_handle, offset,
366 size, direction); 378 size, direction);
367} 379}
368#else /* CONFIG_PPC_NEED_DMA_SYNC_OPS */ 380#else /* CONFIG_PPC_NEED_DMA_SYNC_OPS */
diff --git a/arch/powerpc/include/asm/highmem.h b/arch/powerpc/include/asm/highmem.h
index 684a73f4324f..a74c4ee6c020 100644
--- a/arch/powerpc/include/asm/highmem.h
+++ b/arch/powerpc/include/asm/highmem.h
@@ -22,9 +22,7 @@
22 22
23#ifdef __KERNEL__ 23#ifdef __KERNEL__
24 24
25#include <linux/init.h>
26#include <linux/interrupt.h> 25#include <linux/interrupt.h>
27#include <linux/highmem.h>
28#include <asm/kmap_types.h> 26#include <asm/kmap_types.h>
29#include <asm/tlbflush.h> 27#include <asm/tlbflush.h>
30#include <asm/page.h> 28#include <asm/page.h>
@@ -62,6 +60,9 @@ extern pte_t *pkmap_page_table;
62 60
63extern void *kmap_high(struct page *page); 61extern void *kmap_high(struct page *page);
64extern void kunmap_high(struct page *page); 62extern void kunmap_high(struct page *page);
63extern void *kmap_atomic_prot(struct page *page, enum km_type type,
64 pgprot_t prot);
65extern void kunmap_atomic(void *kvaddr, enum km_type type);
65 66
66static inline void *kmap(struct page *page) 67static inline void *kmap(struct page *page)
67{ 68{
@@ -79,62 +80,11 @@ static inline void kunmap(struct page *page)
79 kunmap_high(page); 80 kunmap_high(page);
80} 81}
81 82
82/*
83 * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
84 * gives a more generic (and caching) interface. But kmap_atomic can
85 * be used in IRQ contexts, so in some (very limited) cases we need
86 * it.
87 */
88static inline void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot)
89{
90 unsigned int idx;
91 unsigned long vaddr;
92
93 /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
94 pagefault_disable();
95 if (!PageHighMem(page))
96 return page_address(page);
97
98 debug_kmap_atomic(type);
99 idx = type + KM_TYPE_NR*smp_processor_id();
100 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
101#ifdef CONFIG_DEBUG_HIGHMEM
102 BUG_ON(!pte_none(*(kmap_pte-idx)));
103#endif
104 __set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot), 1);
105 local_flush_tlb_page(NULL, vaddr);
106
107 return (void*) vaddr;
108}
109
110static inline void *kmap_atomic(struct page *page, enum km_type type) 83static inline void *kmap_atomic(struct page *page, enum km_type type)
111{ 84{
112 return kmap_atomic_prot(page, type, kmap_prot); 85 return kmap_atomic_prot(page, type, kmap_prot);
113} 86}
114 87
115static inline void kunmap_atomic(void *kvaddr, enum km_type type)
116{
117#ifdef CONFIG_DEBUG_HIGHMEM
118 unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
119 enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id();
120
121 if (vaddr < __fix_to_virt(FIX_KMAP_END)) {
122 pagefault_enable();
123 return;
124 }
125
126 BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx));
127
128 /*
129 * force other mappings to Oops if they'll try to access
130 * this pte without first remap it
131 */
132 pte_clear(&init_mm, vaddr, kmap_pte-idx);
133 local_flush_tlb_page(NULL, vaddr);
134#endif
135 pagefault_enable();
136}
137
138static inline struct page *kmap_atomic_to_page(void *ptr) 88static inline struct page *kmap_atomic_to_page(void *ptr)
139{ 89{
140 unsigned long idx, vaddr = (unsigned long) ptr; 90 unsigned long idx, vaddr = (unsigned long) ptr;
@@ -148,6 +98,7 @@ static inline struct page *kmap_atomic_to_page(void *ptr)
148 return pte_page(*pte); 98 return pte_page(*pte);
149} 99}
150 100
101
151#define flush_cache_kmaps() flush_cache_all() 102#define flush_cache_kmaps() flush_cache_all()
152 103
153#endif /* __KERNEL__ */ 104#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index 867ab8ed69b3..8b505eaaa38a 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -68,13 +68,13 @@ static inline int irqs_disabled_flags(unsigned long flags)
68 68
69#if defined(CONFIG_BOOKE) 69#if defined(CONFIG_BOOKE)
70#define SET_MSR_EE(x) mtmsr(x) 70#define SET_MSR_EE(x) mtmsr(x)
71#define local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory") 71#define raw_local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory")
72#else 72#else
73#define SET_MSR_EE(x) mtmsr(x) 73#define SET_MSR_EE(x) mtmsr(x)
74#define local_irq_restore(flags) mtmsr(flags) 74#define raw_local_irq_restore(flags) mtmsr(flags)
75#endif 75#endif
76 76
77static inline void local_irq_disable(void) 77static inline void raw_local_irq_disable(void)
78{ 78{
79#ifdef CONFIG_BOOKE 79#ifdef CONFIG_BOOKE
80 __asm__ __volatile__("wrteei 0": : :"memory"); 80 __asm__ __volatile__("wrteei 0": : :"memory");
@@ -86,7 +86,7 @@ static inline void local_irq_disable(void)
86#endif 86#endif
87} 87}
88 88
89static inline void local_irq_enable(void) 89static inline void raw_local_irq_enable(void)
90{ 90{
91#ifdef CONFIG_BOOKE 91#ifdef CONFIG_BOOKE
92 __asm__ __volatile__("wrteei 1": : :"memory"); 92 __asm__ __volatile__("wrteei 1": : :"memory");
@@ -98,7 +98,7 @@ static inline void local_irq_enable(void)
98#endif 98#endif
99} 99}
100 100
101static inline void local_irq_save_ptr(unsigned long *flags) 101static inline void raw_local_irq_save_ptr(unsigned long *flags)
102{ 102{
103 unsigned long msr; 103 unsigned long msr;
104 msr = mfmsr(); 104 msr = mfmsr();
@@ -110,12 +110,12 @@ static inline void local_irq_save_ptr(unsigned long *flags)
110#endif 110#endif
111} 111}
112 112
113#define local_save_flags(flags) ((flags) = mfmsr()) 113#define raw_local_save_flags(flags) ((flags) = mfmsr())
114#define local_irq_save(flags) local_irq_save_ptr(&flags) 114#define raw_local_irq_save(flags) raw_local_irq_save_ptr(&flags)
115#define irqs_disabled() ((mfmsr() & MSR_EE) == 0) 115#define raw_irqs_disabled() ((mfmsr() & MSR_EE) == 0)
116#define raw_irqs_disabled_flags(flags) (((flags) & MSR_EE) == 0)
116 117
117#define hard_irq_enable() local_irq_enable() 118#define hard_irq_disable() raw_local_irq_disable()
118#define hard_irq_disable() local_irq_disable()
119 119
120static inline int irqs_disabled_flags(unsigned long flags) 120static inline int irqs_disabled_flags(unsigned long flags)
121{ 121{
diff --git a/arch/powerpc/include/asm/pte-hash64-64k.h b/arch/powerpc/include/asm/pte-hash64-64k.h
index e05d26fa372f..82b72207c51c 100644
--- a/arch/powerpc/include/asm/pte-hash64-64k.h
+++ b/arch/powerpc/include/asm/pte-hash64-64k.h
@@ -47,7 +47,8 @@
47 * generic accessors and iterators here 47 * generic accessors and iterators here
48 */ 48 */
49#define __real_pte(e,p) ((real_pte_t) { \ 49#define __real_pte(e,p) ((real_pte_t) { \
50 (e), pte_val(*((p) + PTRS_PER_PTE)) }) 50 (e), ((e) & _PAGE_COMBO) ? \
51 (pte_val(*((p) + PTRS_PER_PTE))) : 0 })
51#define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \ 52#define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \
52 (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf)) 53 (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
53#define __rpte_to_pte(r) ((r).pte) 54#define __rpte_to_pte(r) ((r).pte)
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 01c12339b304..168fce726201 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -58,7 +58,7 @@ struct rtas_t {
58 unsigned long entry; /* physical address pointer */ 58 unsigned long entry; /* physical address pointer */
59 unsigned long base; /* physical address pointer */ 59 unsigned long base; /* physical address pointer */
60 unsigned long size; 60 unsigned long size;
61 spinlock_t lock; 61 raw_spinlock_t lock;
62 struct rtas_args args; 62 struct rtas_args args;
63 struct device_node *dev; /* virtual address pointer */ 63 struct device_node *dev; /* virtual address pointer */
64}; 64};
@@ -245,5 +245,8 @@ static inline u32 rtas_config_addr(int busno, int devfn, int reg)
245 (devfn << 8) | (reg & 0xff); 245 (devfn << 8) | (reg & 0xff);
246} 246}
247 247
248extern void __cpuinit rtas_give_timebase(void);
249extern void __cpuinit rtas_take_timebase(void);
250
248#endif /* __KERNEL__ */ 251#endif /* __KERNEL__ */
249#endif /* _POWERPC_RTAS_H */ 252#endif /* _POWERPC_RTAS_H */
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 4dd38f129153..3cadba60a4b6 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -191,11 +191,49 @@ transfer_to_handler_cont:
191 mflr r9 191 mflr r9
192 lwz r11,0(r9) /* virtual address of handler */ 192 lwz r11,0(r9) /* virtual address of handler */
193 lwz r9,4(r9) /* where to go when done */ 193 lwz r9,4(r9) /* where to go when done */
194#ifdef CONFIG_TRACE_IRQFLAGS
195 lis r12,reenable_mmu@h
196 ori r12,r12,reenable_mmu@l
197 mtspr SPRN_SRR0,r12
198 mtspr SPRN_SRR1,r10
199 SYNC
200 RFI
201reenable_mmu: /* re-enable mmu so we can */
202 mfmsr r10
203 lwz r12,_MSR(r1)
204 xor r10,r10,r12
205 andi. r10,r10,MSR_EE /* Did EE change? */
206 beq 1f
207
208 /* Save handler and return address into the 2 unused words
209 * of the STACK_FRAME_OVERHEAD (sneak sneak sneak). Everything
210 * else can be recovered from the pt_regs except r3 which for
211 * normal interrupts has been set to pt_regs and for syscalls
212 * is an argument, so we temporarily use ORIG_GPR3 to save it
213 */
214 stw r9,8(r1)
215 stw r11,12(r1)
216 stw r3,ORIG_GPR3(r1)
217 bl trace_hardirqs_off
218 lwz r0,GPR0(r1)
219 lwz r3,ORIG_GPR3(r1)
220 lwz r4,GPR4(r1)
221 lwz r5,GPR5(r1)
222 lwz r6,GPR6(r1)
223 lwz r7,GPR7(r1)
224 lwz r8,GPR8(r1)
225 lwz r9,8(r1)
226 lwz r11,12(r1)
2271: mtctr r11
228 mtlr r9
229 bctr /* jump to handler */
230#else /* CONFIG_TRACE_IRQFLAGS */
194 mtspr SPRN_SRR0,r11 231 mtspr SPRN_SRR0,r11
195 mtspr SPRN_SRR1,r10 232 mtspr SPRN_SRR1,r10
196 mtlr r9 233 mtlr r9
197 SYNC 234 SYNC
198 RFI /* jump to handler, enable MMU */ 235 RFI /* jump to handler, enable MMU */
236#endif /* CONFIG_TRACE_IRQFLAGS */
199 237
200#if defined (CONFIG_6xx) || defined(CONFIG_E500) 238#if defined (CONFIG_6xx) || defined(CONFIG_E500)
2014: rlwinm r12,r12,0,~_TLF_NAPPING 2394: rlwinm r12,r12,0,~_TLF_NAPPING
@@ -251,6 +289,31 @@ _GLOBAL(DoSyscall)
251#ifdef SHOW_SYSCALLS 289#ifdef SHOW_SYSCALLS
252 bl do_show_syscall 290 bl do_show_syscall
253#endif /* SHOW_SYSCALLS */ 291#endif /* SHOW_SYSCALLS */
292#ifdef CONFIG_TRACE_IRQFLAGS
293 /* Return from syscalls can (and generally will) hard enable
294 * interrupts. You aren't supposed to call a syscall with
295 * interrupts disabled in the first place. However, to ensure
296 * that we get it right vs. lockdep if it happens, we force
297 * that hard enable here with appropriate tracing if we see
298 * that we have been called with interrupts off
299 */
300 mfmsr r11
301 andi. r12,r11,MSR_EE
302 bne+ 1f
303 /* We came in with interrupts disabled, we enable them now */
304 bl trace_hardirqs_on
305 mfmsr r11
306 lwz r0,GPR0(r1)
307 lwz r3,GPR3(r1)
308 lwz r4,GPR4(r1)
309 ori r11,r11,MSR_EE
310 lwz r5,GPR5(r1)
311 lwz r6,GPR6(r1)
312 lwz r7,GPR7(r1)
313 lwz r8,GPR8(r1)
314 mtmsr r11
3151:
316#endif /* CONFIG_TRACE_IRQFLAGS */
254 rlwinm r10,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */ 317 rlwinm r10,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
255 lwz r11,TI_FLAGS(r10) 318 lwz r11,TI_FLAGS(r10)
256 andi. r11,r11,_TIF_SYSCALL_T_OR_A 319 andi. r11,r11,_TIF_SYSCALL_T_OR_A
@@ -275,6 +338,7 @@ ret_from_syscall:
275 rlwinm r12,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */ 338 rlwinm r12,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
276 /* disable interrupts so current_thread_info()->flags can't change */ 339 /* disable interrupts so current_thread_info()->flags can't change */
277 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */ 340 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
341 /* Note: We don't bother telling lockdep about it */
278 SYNC 342 SYNC
279 MTMSRD(r10) 343 MTMSRD(r10)
280 lwz r9,TI_FLAGS(r12) 344 lwz r9,TI_FLAGS(r12)
@@ -288,6 +352,19 @@ ret_from_syscall:
288 oris r11,r11,0x1000 /* Set SO bit in CR */ 352 oris r11,r11,0x1000 /* Set SO bit in CR */
289 stw r11,_CCR(r1) 353 stw r11,_CCR(r1)
290syscall_exit_cont: 354syscall_exit_cont:
355 lwz r8,_MSR(r1)
356#ifdef CONFIG_TRACE_IRQFLAGS
357 /* If we are going to return from the syscall with interrupts
358 * off, we trace that here. It shouldn't happen though but we
359 * want to catch the bugger if it does right ?
360 */
361 andi. r10,r8,MSR_EE
362 bne+ 1f
363 stw r3,GPR3(r1)
364 bl trace_hardirqs_off
365 lwz r3,GPR3(r1)
3661:
367#endif /* CONFIG_TRACE_IRQFLAGS */
291#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 368#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
292 /* If the process has its own DBCR0 value, load it up. The internal 369 /* If the process has its own DBCR0 value, load it up. The internal
293 debug mode bit tells us that dbcr0 should be loaded. */ 370 debug mode bit tells us that dbcr0 should be loaded. */
@@ -311,7 +388,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
311 mtlr r4 388 mtlr r4
312 mtcr r5 389 mtcr r5
313 lwz r7,_NIP(r1) 390 lwz r7,_NIP(r1)
314 lwz r8,_MSR(r1)
315 FIX_SRR1(r8, r0) 391 FIX_SRR1(r8, r0)
316 lwz r2,GPR2(r1) 392 lwz r2,GPR2(r1)
317 lwz r1,GPR1(r1) 393 lwz r1,GPR1(r1)
@@ -394,7 +470,9 @@ syscall_exit_work:
394 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP) 470 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
395 beq ret_from_except 471 beq ret_from_except
396 472
397 /* Re-enable interrupts */ 473 /* Re-enable interrupts. There is no need to trace that with
474 * lockdep as we are supposed to have IRQs on at this point
475 */
398 ori r10,r10,MSR_EE 476 ori r10,r10,MSR_EE
399 SYNC 477 SYNC
400 MTMSRD(r10) 478 MTMSRD(r10)
@@ -705,6 +783,7 @@ ret_from_except:
705 /* Hard-disable interrupts so that current_thread_info()->flags 783 /* Hard-disable interrupts so that current_thread_info()->flags
706 * can't change between when we test it and when we return 784 * can't change between when we test it and when we return
707 * from the interrupt. */ 785 * from the interrupt. */
786 /* Note: We don't bother telling lockdep about it */
708 LOAD_MSR_KERNEL(r10,MSR_KERNEL) 787 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
709 SYNC /* Some chip revs have problems here... */ 788 SYNC /* Some chip revs have problems here... */
710 MTMSRD(r10) /* disable interrupts */ 789 MTMSRD(r10) /* disable interrupts */
@@ -744,11 +823,24 @@ resume_kernel:
744 beq+ restore 823 beq+ restore
745 andi. r0,r3,MSR_EE /* interrupts off? */ 824 andi. r0,r3,MSR_EE /* interrupts off? */
746 beq restore /* don't schedule if so */ 825 beq restore /* don't schedule if so */
826#ifdef CONFIG_TRACE_IRQFLAGS
827 /* Lockdep thinks irqs are enabled, we need to call
828 * preempt_schedule_irq with IRQs off, so we inform lockdep
829 * now that we -did- turn them off already
830 */
831 bl trace_hardirqs_off
832#endif
7471: bl preempt_schedule_irq 8331: bl preempt_schedule_irq
748 rlwinm r9,r1,0,0,(31-THREAD_SHIFT) 834 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
749 lwz r3,TI_FLAGS(r9) 835 lwz r3,TI_FLAGS(r9)
750 andi. r0,r3,_TIF_NEED_RESCHED 836 andi. r0,r3,_TIF_NEED_RESCHED
751 bne- 1b 837 bne- 1b
838#ifdef CONFIG_TRACE_IRQFLAGS
839 /* And now, to properly rebalance the above, we tell lockdep they
840 * are being turned back on, which will happen when we return
841 */
842 bl trace_hardirqs_on
843#endif
752#else 844#else
753resume_kernel: 845resume_kernel:
754#endif /* CONFIG_PREEMPT */ 846#endif /* CONFIG_PREEMPT */
@@ -765,6 +857,28 @@ restore:
765 stw r6,icache_44x_need_flush@l(r4) 857 stw r6,icache_44x_need_flush@l(r4)
7661: 8581:
767#endif /* CONFIG_44x */ 859#endif /* CONFIG_44x */
860
861 lwz r9,_MSR(r1)
862#ifdef CONFIG_TRACE_IRQFLAGS
863 /* Lockdep doesn't know about the fact that IRQs are temporarily turned
864 * off in this assembly code while peeking at TI_FLAGS() and such. However
865 * we need to inform it if the exception turned interrupts off, and we
866 * are about to trun them back on.
867 *
868 * The problem here sadly is that we don't know whether the exceptions was
869 * one that turned interrupts off or not. So we always tell lockdep about
870 * turning them on here when we go back to wherever we came from with EE
871 * on, even if that may meen some redudant calls being tracked. Maybe later
872 * we could encode what the exception did somewhere or test the exception
873 * type in the pt_regs but that sounds overkill
874 */
875 andi. r10,r9,MSR_EE
876 beq 1f
877 bl trace_hardirqs_on
878 lwz r9,_MSR(r1)
8791:
880#endif /* CONFIG_TRACE_IRQFLAGS */
881
768 lwz r0,GPR0(r1) 882 lwz r0,GPR0(r1)
769 lwz r2,GPR2(r1) 883 lwz r2,GPR2(r1)
770 REST_4GPRS(3, r1) 884 REST_4GPRS(3, r1)
@@ -782,7 +896,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
782 stwcx. r0,0,r1 /* to clear the reservation */ 896 stwcx. r0,0,r1 /* to clear the reservation */
783 897
784#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) 898#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
785 lwz r9,_MSR(r1)
786 andi. r10,r9,MSR_RI /* check if this exception occurred */ 899 andi. r10,r9,MSR_RI /* check if this exception occurred */
787 beql nonrecoverable /* at a bad place (MSR:RI = 0) */ 900 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
788 901
@@ -805,7 +918,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
805 MTMSRD(r10) /* clear the RI bit */ 918 MTMSRD(r10) /* clear the RI bit */
806 .globl exc_exit_restart 919 .globl exc_exit_restart
807exc_exit_restart: 920exc_exit_restart:
808 lwz r9,_MSR(r1)
809 lwz r12,_NIP(r1) 921 lwz r12,_NIP(r1)
810 FIX_SRR1(r9,r10) 922 FIX_SRR1(r9,r10)
811 mtspr SPRN_SRR0,r12 923 mtspr SPRN_SRR0,r12
@@ -1035,11 +1147,18 @@ do_work: /* r10 contains MSR_KERNEL here */
1035 beq do_user_signal 1147 beq do_user_signal
1036 1148
1037do_resched: /* r10 contains MSR_KERNEL here */ 1149do_resched: /* r10 contains MSR_KERNEL here */
1150 /* Note: We don't need to inform lockdep that we are enabling
1151 * interrupts here. As far as it knows, they are already enabled
1152 */
1038 ori r10,r10,MSR_EE 1153 ori r10,r10,MSR_EE
1039 SYNC 1154 SYNC
1040 MTMSRD(r10) /* hard-enable interrupts */ 1155 MTMSRD(r10) /* hard-enable interrupts */
1041 bl schedule 1156 bl schedule
1042recheck: 1157recheck:
1158 /* Note: And we don't tell it we are disabling them again
1159 * neither. Those disable/enable cycles used to peek at
1160 * TI_FLAGS aren't advertised.
1161 */
1043 LOAD_MSR_KERNEL(r10,MSR_KERNEL) 1162 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
1044 SYNC 1163 SYNC
1045 MTMSRD(r10) /* disable interrupts */ 1164 MTMSRD(r10) /* disable interrupts */
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 48469463f89e..fc2132942754 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -1124,9 +1124,8 @@ mmu_off:
1124 RFI 1124 RFI
1125 1125
1126/* 1126/*
1127 * Use the first pair of BAT registers to map the 1st 16MB 1127 * On 601, we use 3 BATs to map up to 24M of RAM at _PAGE_OFFSET
1128 * of RAM to PAGE_OFFSET. From this point on we can't safely 1128 * (we keep one for debugging) and on others, we use one 256M BAT.
1129 * call OF any more.
1130 */ 1129 */
1131initial_bats: 1130initial_bats:
1132 lis r11,PAGE_OFFSET@h 1131 lis r11,PAGE_OFFSET@h
@@ -1136,12 +1135,16 @@ initial_bats:
1136 bne 4f 1135 bne 4f
1137 ori r11,r11,4 /* set up BAT registers for 601 */ 1136 ori r11,r11,4 /* set up BAT registers for 601 */
1138 li r8,0x7f /* valid, block length = 8MB */ 1137 li r8,0x7f /* valid, block length = 8MB */
1139 oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */
1140 oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */
1141 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */ 1138 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1142 mtspr SPRN_IBAT0L,r8 /* lower BAT register */ 1139 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1143 mtspr SPRN_IBAT1U,r9 1140 addis r11,r11,0x800000@h
1144 mtspr SPRN_IBAT1L,r10 1141 addis r8,r8,0x800000@h
1142 mtspr SPRN_IBAT1U,r11
1143 mtspr SPRN_IBAT1L,r8
1144 addis r11,r11,0x800000@h
1145 addis r8,r8,0x800000@h
1146 mtspr SPRN_IBAT2U,r11
1147 mtspr SPRN_IBAT2L,r8
1145 isync 1148 isync
1146 blr 1149 blr
1147 1150
diff --git a/arch/powerpc/kernel/of_device.c b/arch/powerpc/kernel/of_device.c
index fa983a59c4ce..a359cb08e900 100644
--- a/arch/powerpc/kernel/of_device.c
+++ b/arch/powerpc/kernel/of_device.c
@@ -76,7 +76,7 @@ struct of_device *of_device_alloc(struct device_node *np,
76 dev->dev.archdata.of_node = np; 76 dev->dev.archdata.of_node = np;
77 77
78 if (bus_id) 78 if (bus_id)
79 dev_set_name(&dev->dev, bus_id); 79 dev_set_name(&dev->dev, "%s", bus_id);
80 else 80 else
81 of_device_make_bus_id(dev); 81 of_device_make_bus_id(dev);
82 82
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 3e7135bbe40f..892a9f2e6d76 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -528,7 +528,7 @@ void show_regs(struct pt_regs * regs)
528 528
529 for (i = 0; i < 32; i++) { 529 for (i = 0; i < 32; i++) {
530 if ((i % REGS_PER_LINE) == 0) 530 if ((i % REGS_PER_LINE) == 0)
531 printk("\n" KERN_INFO "GPR%02d: ", i); 531 printk("\nGPR%02d: ", i);
532 printk(REG " ", regs->gpr[i]); 532 printk(REG " ", regs->gpr[i]);
533 if (i == LAST_VOLATILE && !FULL_REGS(regs)) 533 if (i == LAST_VOLATILE && !FULL_REGS(regs))
534 break; 534 break;
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index ee4c7609b649..c434823b8c83 100644
--- a/arch/powerpc/kernel/rtas.c
+++ b/arch/powerpc/kernel/rtas.c
@@ -38,9 +38,10 @@
38#include <asm/syscalls.h> 38#include <asm/syscalls.h>
39#include <asm/smp.h> 39#include <asm/smp.h>
40#include <asm/atomic.h> 40#include <asm/atomic.h>
41#include <asm/time.h>
41 42
42struct rtas_t rtas = { 43struct rtas_t rtas = {
43 .lock = SPIN_LOCK_UNLOCKED 44 .lock = __RAW_SPIN_LOCK_UNLOCKED
44}; 45};
45EXPORT_SYMBOL(rtas); 46EXPORT_SYMBOL(rtas);
46 47
@@ -67,6 +68,28 @@ unsigned long rtas_rmo_buf;
67void (*rtas_flash_term_hook)(int); 68void (*rtas_flash_term_hook)(int);
68EXPORT_SYMBOL(rtas_flash_term_hook); 69EXPORT_SYMBOL(rtas_flash_term_hook);
69 70
71/* RTAS use home made raw locking instead of spin_lock_irqsave
72 * because those can be called from within really nasty contexts
73 * such as having the timebase stopped which would lockup with
74 * normal locks and spinlock debugging enabled
75 */
76static unsigned long lock_rtas(void)
77{
78 unsigned long flags;
79
80 local_irq_save(flags);
81 preempt_disable();
82 __raw_spin_lock_flags(&rtas.lock, flags);
83 return flags;
84}
85
86static void unlock_rtas(unsigned long flags)
87{
88 __raw_spin_unlock(&rtas.lock);
89 local_irq_restore(flags);
90 preempt_enable();
91}
92
70/* 93/*
71 * call_rtas_display_status and call_rtas_display_status_delay 94 * call_rtas_display_status and call_rtas_display_status_delay
72 * are designed only for very early low-level debugging, which 95 * are designed only for very early low-level debugging, which
@@ -79,7 +102,7 @@ static void call_rtas_display_status(char c)
79 102
80 if (!rtas.base) 103 if (!rtas.base)
81 return; 104 return;
82 spin_lock_irqsave(&rtas.lock, s); 105 s = lock_rtas();
83 106
84 args->token = 10; 107 args->token = 10;
85 args->nargs = 1; 108 args->nargs = 1;
@@ -89,7 +112,7 @@ static void call_rtas_display_status(char c)
89 112
90 enter_rtas(__pa(args)); 113 enter_rtas(__pa(args));
91 114
92 spin_unlock_irqrestore(&rtas.lock, s); 115 unlock_rtas(s);
93} 116}
94 117
95static void call_rtas_display_status_delay(char c) 118static void call_rtas_display_status_delay(char c)
@@ -411,8 +434,7 @@ int rtas_call(int token, int nargs, int nret, int *outputs, ...)
411 if (!rtas.entry || token == RTAS_UNKNOWN_SERVICE) 434 if (!rtas.entry || token == RTAS_UNKNOWN_SERVICE)
412 return -1; 435 return -1;
413 436
414 /* Gotta do something different here, use global lock for now... */ 437 s = lock_rtas();
415 spin_lock_irqsave(&rtas.lock, s);
416 rtas_args = &rtas.args; 438 rtas_args = &rtas.args;
417 439
418 rtas_args->token = token; 440 rtas_args->token = token;
@@ -439,8 +461,7 @@ int rtas_call(int token, int nargs, int nret, int *outputs, ...)
439 outputs[i] = rtas_args->rets[i+1]; 461 outputs[i] = rtas_args->rets[i+1];
440 ret = (nret > 0)? rtas_args->rets[0]: 0; 462 ret = (nret > 0)? rtas_args->rets[0]: 0;
441 463
442 /* Gotta do something different here, use global lock for now... */ 464 unlock_rtas(s);
443 spin_unlock_irqrestore(&rtas.lock, s);
444 465
445 if (buff_copy) { 466 if (buff_copy) {
446 log_error(buff_copy, ERR_TYPE_RTAS_LOG, 0); 467 log_error(buff_copy, ERR_TYPE_RTAS_LOG, 0);
@@ -837,7 +858,7 @@ asmlinkage int ppc_rtas(struct rtas_args __user *uargs)
837 858
838 buff_copy = get_errorlog_buffer(); 859 buff_copy = get_errorlog_buffer();
839 860
840 spin_lock_irqsave(&rtas.lock, flags); 861 flags = lock_rtas();
841 862
842 rtas.args = args; 863 rtas.args = args;
843 enter_rtas(__pa(&rtas.args)); 864 enter_rtas(__pa(&rtas.args));
@@ -848,7 +869,7 @@ asmlinkage int ppc_rtas(struct rtas_args __user *uargs)
848 if (args.rets[0] == -1) 869 if (args.rets[0] == -1)
849 errbuf = __fetch_rtas_last_error(buff_copy); 870 errbuf = __fetch_rtas_last_error(buff_copy);
850 871
851 spin_unlock_irqrestore(&rtas.lock, flags); 872 unlock_rtas(flags);
852 873
853 if (buff_copy) { 874 if (buff_copy) {
854 if (errbuf) 875 if (errbuf)
@@ -951,3 +972,33 @@ int __init early_init_dt_scan_rtas(unsigned long node,
951 /* break now */ 972 /* break now */
952 return 1; 973 return 1;
953} 974}
975
976static raw_spinlock_t timebase_lock;
977static u64 timebase = 0;
978
979void __cpuinit rtas_give_timebase(void)
980{
981 unsigned long flags;
982
983 local_irq_save(flags);
984 hard_irq_disable();
985 __raw_spin_lock(&timebase_lock);
986 rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL);
987 timebase = get_tb();
988 __raw_spin_unlock(&timebase_lock);
989
990 while (timebase)
991 barrier();
992 rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL);
993 local_irq_restore(flags);
994}
995
996void __cpuinit rtas_take_timebase(void)
997{
998 while (!timebase)
999 barrier();
1000 __raw_spin_lock(&timebase_lock);
1001 set_tb(timebase >> 32, timebase & 0xffffffff);
1002 timebase = 0;
1003 __raw_spin_unlock(&timebase_lock);
1004}
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 1d154248cf40..e1e3059cf34b 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -119,6 +119,8 @@ notrace unsigned long __init early_init(unsigned long dt_ptr)
119 */ 119 */
120notrace void __init machine_init(unsigned long dt_ptr) 120notrace void __init machine_init(unsigned long dt_ptr)
121{ 121{
122 lockdep_init();
123
122 /* Enable early debugging if any specified (see udbg.h) */ 124 /* Enable early debugging if any specified (see udbg.h) */
123 udbg_early_init(); 125 udbg_early_init();
124 126
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 65484b2200b3..0b47de07302d 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -68,7 +68,8 @@ EXPORT_PER_CPU_SYMBOL(cpu_core_map);
68/* SMP operations for this machine */ 68/* SMP operations for this machine */
69struct smp_ops_t *smp_ops; 69struct smp_ops_t *smp_ops;
70 70
71static volatile unsigned int cpu_callin_map[NR_CPUS]; 71/* Can't be static due to PowerMac hackery */
72volatile unsigned int cpu_callin_map[NR_CPUS];
72 73
73int smt_enabled_at_boot = 1; 74int smt_enabled_at_boot = 1;
74 75
diff --git a/arch/powerpc/kernel/udbg_16550.c b/arch/powerpc/kernel/udbg_16550.c
index 0362a891e54e..acb74a17bbbf 100644
--- a/arch/powerpc/kernel/udbg_16550.c
+++ b/arch/powerpc/kernel/udbg_16550.c
@@ -219,7 +219,7 @@ void udbg_init_pas_realmode(void)
219#ifdef CONFIG_PPC_EARLY_DEBUG_44x 219#ifdef CONFIG_PPC_EARLY_DEBUG_44x
220#include <platforms/44x/44x.h> 220#include <platforms/44x/44x.h>
221 221
222static int udbg_44x_as1_flush(void) 222static void udbg_44x_as1_flush(void)
223{ 223{
224 if (udbg_comport) { 224 if (udbg_comport) {
225 while ((as1_readb(&udbg_comport->lsr) & LSR_THRE) == 0) 225 while ((as1_readb(&udbg_comport->lsr) & LSR_THRE) == 0)
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index 2d2192e48de7..3e68363405b7 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -30,3 +30,4 @@ obj-$(CONFIG_PPC_MM_SLICES) += slice.o
30obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o 30obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
31obj-$(CONFIG_PPC_SUBPAGE_PROT) += subpage-prot.o 31obj-$(CONFIG_PPC_SUBPAGE_PROT) += subpage-prot.o
32obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o 32obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o
33obj-$(CONFIG_HIGHMEM) += highmem.o
diff --git a/arch/powerpc/mm/highmem.c b/arch/powerpc/mm/highmem.c
new file mode 100644
index 000000000000..c2186c74c85a
--- /dev/null
+++ b/arch/powerpc/mm/highmem.c
@@ -0,0 +1,77 @@
1/*
2 * highmem.c: virtual kernel memory mappings for high memory
3 *
4 * PowerPC version, stolen from the i386 version.
5 *
6 * Used in CONFIG_HIGHMEM systems for memory pages which
7 * are not addressable by direct kernel virtual addresses.
8 *
9 * Copyright (C) 1999 Gerhard Wichert, Siemens AG
10 * Gerhard.Wichert@pdb.siemens.de
11 *
12 *
13 * Redesigned the x86 32-bit VM architecture to deal with
14 * up to 16 Terrabyte physical memory. With current x86 CPUs
15 * we now support up to 64 Gigabytes physical RAM.
16 *
17 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
18 *
19 * Reworked for PowerPC by various contributors. Moved from
20 * highmem.h by Benjamin Herrenschmidt (c) 2009 IBM Corp.
21 */
22
23#include <linux/highmem.h>
24#include <linux/module.h>
25
26/*
27 * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
28 * gives a more generic (and caching) interface. But kmap_atomic can
29 * be used in IRQ contexts, so in some (very limited) cases we need
30 * it.
31 */
32void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot)
33{
34 unsigned int idx;
35 unsigned long vaddr;
36
37 /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
38 pagefault_disable();
39 if (!PageHighMem(page))
40 return page_address(page);
41
42 debug_kmap_atomic(type);
43 idx = type + KM_TYPE_NR*smp_processor_id();
44 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
45#ifdef CONFIG_DEBUG_HIGHMEM
46 BUG_ON(!pte_none(*(kmap_pte-idx)));
47#endif
48 __set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot), 1);
49 local_flush_tlb_page(NULL, vaddr);
50
51 return (void*) vaddr;
52}
53EXPORT_SYMBOL(kmap_atomic_prot);
54
55void kunmap_atomic(void *kvaddr, enum km_type type)
56{
57#ifdef CONFIG_DEBUG_HIGHMEM
58 unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
59 enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id();
60
61 if (vaddr < __fix_to_virt(FIX_KMAP_END)) {
62 pagefault_enable();
63 return;
64 }
65
66 BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx));
67
68 /*
69 * force other mappings to Oops if they'll try to access
70 * this pte without first remap it
71 */
72 pte_clear(&init_mm, vaddr, kmap_pte-idx);
73 local_flush_tlb_page(NULL, vaddr);
74#endif
75 pagefault_enable();
76}
77EXPORT_SYMBOL(kunmap_atomic);
diff --git a/arch/powerpc/platforms/44x/warp.c b/arch/powerpc/platforms/44x/warp.c
index 42e09a9f77e2..0362c88f47d7 100644
--- a/arch/powerpc/platforms/44x/warp.c
+++ b/arch/powerpc/platforms/44x/warp.c
@@ -16,6 +16,7 @@
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/delay.h> 17#include <linux/delay.h>
18#include <linux/of_gpio.h> 18#include <linux/of_gpio.h>
19#include <linux/of_i2c.h>
19 20
20#include <asm/machdep.h> 21#include <asm/machdep.h>
21#include <asm/prom.h> 22#include <asm/prom.h>
@@ -65,7 +66,6 @@ define_machine(warp) {
65 66
66static u32 post_info; 67static u32 post_info;
67 68
68/* I am not sure this is the best place for this... */
69static int __init warp_post_info(void) 69static int __init warp_post_info(void)
70{ 70{
71 struct device_node *np; 71 struct device_node *np;
@@ -194,9 +194,9 @@ static int pika_setup_leds(void)
194 return 0; 194 return 0;
195} 195}
196 196
197static void pika_setup_critical_temp(struct i2c_client *client) 197static void pika_setup_critical_temp(struct device_node *np,
198 struct i2c_client *client)
198{ 199{
199 struct device_node *np;
200 int irq, rc; 200 int irq, rc;
201 201
202 /* Do this before enabling critical temp interrupt since we 202 /* Do this before enabling critical temp interrupt since we
@@ -208,14 +208,7 @@ static void pika_setup_critical_temp(struct i2c_client *client)
208 i2c_smbus_write_byte_data(client, 2, 65); /* Thigh */ 208 i2c_smbus_write_byte_data(client, 2, 65); /* Thigh */
209 i2c_smbus_write_byte_data(client, 3, 0); /* Tlow */ 209 i2c_smbus_write_byte_data(client, 3, 0); /* Tlow */
210 210
211 np = of_find_compatible_node(NULL, NULL, "adi,ad7414");
212 if (np == NULL) {
213 printk(KERN_ERR __FILE__ ": Unable to find ad7414\n");
214 return;
215 }
216
217 irq = irq_of_parse_and_map(np, 0); 211 irq = irq_of_parse_and_map(np, 0);
218 of_node_put(np);
219 if (irq == NO_IRQ) { 212 if (irq == NO_IRQ) {
220 printk(KERN_ERR __FILE__ ": Unable to get ad7414 irq\n"); 213 printk(KERN_ERR __FILE__ ": Unable to get ad7414 irq\n");
221 return; 214 return;
@@ -244,32 +237,24 @@ static inline void pika_dtm_check_fan(void __iomem *fpga)
244 237
245static int pika_dtm_thread(void __iomem *fpga) 238static int pika_dtm_thread(void __iomem *fpga)
246{ 239{
247 struct i2c_adapter *adap; 240 struct device_node *np;
248 struct i2c_client *client; 241 struct i2c_client *client;
249 242
250 /* We loop in case either driver was compiled as a module and 243 np = of_find_compatible_node(NULL, NULL, "adi,ad7414");
251 * has not been insmoded yet. 244 if (np == NULL)
252 */ 245 return -ENOENT;
253 while (!(adap = i2c_get_adapter(0))) {
254 set_current_state(TASK_INTERRUPTIBLE);
255 schedule_timeout(HZ);
256 }
257
258 while (1) {
259 list_for_each_entry(client, &adap->clients, list)
260 if (client->addr == 0x4a)
261 goto found_it;
262 246
263 set_current_state(TASK_INTERRUPTIBLE); 247 client = of_find_i2c_device_by_node(np);
264 schedule_timeout(HZ); 248 if (client == NULL) {
249 of_node_put(np);
250 return -ENOENT;
265 } 251 }
266 252
267found_it: 253 pika_setup_critical_temp(np, client);
268 pika_setup_critical_temp(client);
269 254
270 i2c_put_adapter(adap); 255 of_node_put(np);
271 256
272 printk(KERN_INFO "PIKA DTM thread running.\n"); 257 printk(KERN_INFO "Warp DTM thread running.\n");
273 258
274 while (!kthread_should_stop()) { 259 while (!kthread_should_stop()) {
275 int val; 260 int val;
@@ -291,7 +276,6 @@ found_it:
291 return 0; 276 return 0;
292} 277}
293 278
294
295static int __init pika_dtm_start(void) 279static int __init pika_dtm_start(void)
296{ 280{
297 struct task_struct *dtm_thread; 281 struct task_struct *dtm_thread;
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 77f90b356356..60ed9c067b1d 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -285,6 +285,7 @@ static struct of_device_id mpc85xx_ids[] = {
285 { .type = "qe", }, 285 { .type = "qe", },
286 { .compatible = "fsl,qe", }, 286 { .compatible = "fsl,qe", },
287 { .compatible = "gianfar", }, 287 { .compatible = "gianfar", },
288 { .compatible = "fsl,rapidio-delta", },
288 {}, 289 {},
289}; 290};
290 291
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index cc0b0db8a6f3..62c592ede641 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -52,20 +52,19 @@ smp_85xx_kick_cpu(int nr)
52 52
53 pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr); 53 pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr);
54 54
55 local_irq_save(flags);
56
57 np = of_get_cpu_node(nr, NULL); 55 np = of_get_cpu_node(nr, NULL);
58 cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL); 56 cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL);
59 57
60 if (cpu_rel_addr == NULL) { 58 if (cpu_rel_addr == NULL) {
61 printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr); 59 printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr);
62 local_irq_restore(flags);
63 return; 60 return;
64 } 61 }
65 62
66 /* Map the spin table */ 63 /* Map the spin table */
67 bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY); 64 bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY);
68 65
66 local_irq_save(flags);
67
69 out_be32(bptr_vaddr + BOOT_ENTRY_PIR, nr); 68 out_be32(bptr_vaddr + BOOT_ENTRY_PIR, nr);
70 out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start)); 69 out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start));
71 70
@@ -73,10 +72,10 @@ smp_85xx_kick_cpu(int nr)
73 while ((__secondary_hold_acknowledge != nr) && (++n < 1000)) 72 while ((__secondary_hold_acknowledge != nr) && (++n < 1000))
74 mdelay(1); 73 mdelay(1);
75 74
76 iounmap(bptr_vaddr);
77
78 local_irq_restore(flags); 75 local_irq_restore(flags);
79 76
77 iounmap(bptr_vaddr);
78
80 pr_debug("waited %d msecs for CPU #%d.\n", n, nr); 79 pr_debug("waited %d msecs for CPU #%d.\n", n, nr);
81} 80}
82 81
diff --git a/arch/powerpc/platforms/85xx/socrates.c b/arch/powerpc/platforms/85xx/socrates.c
index d0e8443b12c6..747d8fb3ab82 100644
--- a/arch/powerpc/platforms/85xx/socrates.c
+++ b/arch/powerpc/platforms/85xx/socrates.c
@@ -102,10 +102,11 @@ static struct of_device_id __initdata socrates_of_bus_ids[] = {
102 {}, 102 {},
103}; 103};
104 104
105static void __init socrates_init(void) 105static int __init socrates_publish_devices(void)
106{ 106{
107 of_platform_bus_probe(NULL, socrates_of_bus_ids, NULL); 107 return of_platform_bus_probe(NULL, socrates_of_bus_ids, NULL);
108} 108}
109machine_device_initcall(socrates, socrates_publish_devices);
109 110
110/* 111/*
111 * Called very early, device-tree isn't unflattened 112 * Called very early, device-tree isn't unflattened
@@ -124,7 +125,6 @@ define_machine(socrates) {
124 .name = "Socrates", 125 .name = "Socrates",
125 .probe = socrates_probe, 126 .probe = socrates_probe,
126 .setup_arch = socrates_setup_arch, 127 .setup_arch = socrates_setup_arch,
127 .init = socrates_init,
128 .init_IRQ = socrates_pic_init, 128 .init_IRQ = socrates_pic_init,
129 .get_irq = mpic_get_irq, 129 .get_irq = mpic_get_irq,
130 .restart = fsl_rstcr_restart, 130 .restart = fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
index ee01532786e4..1b426050a2f9 100644
--- a/arch/powerpc/platforms/85xx/xes_mpc85xx.c
+++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
@@ -32,7 +32,6 @@
32 32
33#include <sysdev/fsl_soc.h> 33#include <sysdev/fsl_soc.h>
34#include <sysdev/fsl_pci.h> 34#include <sysdev/fsl_pci.h>
35#include <linux/of_platform.h>
36 35
37/* A few bit definitions needed for fixups on some boards */ 36/* A few bit definitions needed for fixups on some boards */
38#define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */ 37#define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */
diff --git a/arch/powerpc/platforms/cell/smp.c b/arch/powerpc/platforms/cell/smp.c
index 9046803c8276..bc97fada48c6 100644
--- a/arch/powerpc/platforms/cell/smp.c
+++ b/arch/powerpc/platforms/cell/smp.c
@@ -36,7 +36,6 @@
36#include <asm/prom.h> 36#include <asm/prom.h>
37#include <asm/smp.h> 37#include <asm/smp.h>
38#include <asm/paca.h> 38#include <asm/paca.h>
39#include <asm/time.h>
40#include <asm/machdep.h> 39#include <asm/machdep.h>
41#include <asm/cputable.h> 40#include <asm/cputable.h>
42#include <asm/firmware.h> 41#include <asm/firmware.h>
@@ -140,31 +139,6 @@ static void __devinit smp_cell_setup_cpu(int cpu)
140 mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER); 139 mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER);
141} 140}
142 141
143static DEFINE_SPINLOCK(timebase_lock);
144static unsigned long timebase = 0;
145
146static void __devinit cell_give_timebase(void)
147{
148 spin_lock(&timebase_lock);
149 rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL);
150 timebase = get_tb();
151 spin_unlock(&timebase_lock);
152
153 while (timebase)
154 barrier();
155 rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL);
156}
157
158static void __devinit cell_take_timebase(void)
159{
160 while (!timebase)
161 barrier();
162 spin_lock(&timebase_lock);
163 set_tb(timebase >> 32, timebase & 0xffffffff);
164 timebase = 0;
165 spin_unlock(&timebase_lock);
166}
167
168static void __devinit smp_cell_kick_cpu(int nr) 142static void __devinit smp_cell_kick_cpu(int nr)
169{ 143{
170 BUG_ON(nr < 0 || nr >= NR_CPUS); 144 BUG_ON(nr < 0 || nr >= NR_CPUS);
@@ -224,8 +198,8 @@ void __init smp_init_cell(void)
224 198
225 /* Non-lpar has additional take/give timebase */ 199 /* Non-lpar has additional take/give timebase */
226 if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) { 200 if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) {
227 smp_ops->give_timebase = cell_give_timebase; 201 smp_ops->give_timebase = rtas_give_timebase;
228 smp_ops->take_timebase = cell_take_timebase; 202 smp_ops->take_timebase = rtas_take_timebase;
229 } 203 }
230 204
231 DBG(" <- smp_init_cell()\n"); 205 DBG(" <- smp_init_cell()\n");
diff --git a/arch/powerpc/platforms/chrp/smp.c b/arch/powerpc/platforms/chrp/smp.c
index 10a4a4d063b6..02cafecc90e3 100644
--- a/arch/powerpc/platforms/chrp/smp.c
+++ b/arch/powerpc/platforms/chrp/smp.c
@@ -26,7 +26,6 @@
26#include <asm/io.h> 26#include <asm/io.h>
27#include <asm/prom.h> 27#include <asm/prom.h>
28#include <asm/smp.h> 28#include <asm/smp.h>
29#include <asm/time.h>
30#include <asm/machdep.h> 29#include <asm/machdep.h>
31#include <asm/mpic.h> 30#include <asm/mpic.h>
32#include <asm/rtas.h> 31#include <asm/rtas.h>
@@ -42,40 +41,12 @@ static void __devinit smp_chrp_setup_cpu(int cpu_nr)
42 mpic_setup_this_cpu(); 41 mpic_setup_this_cpu();
43} 42}
44 43
45static DEFINE_SPINLOCK(timebase_lock);
46static unsigned int timebase_upper = 0, timebase_lower = 0;
47
48void __devinit smp_chrp_give_timebase(void)
49{
50 spin_lock(&timebase_lock);
51 rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL);
52 timebase_upper = get_tbu();
53 timebase_lower = get_tbl();
54 spin_unlock(&timebase_lock);
55
56 while (timebase_upper || timebase_lower)
57 barrier();
58 rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL);
59}
60
61void __devinit smp_chrp_take_timebase(void)
62{
63 while (!(timebase_upper || timebase_lower))
64 barrier();
65 spin_lock(&timebase_lock);
66 set_tb(timebase_upper, timebase_lower);
67 timebase_upper = 0;
68 timebase_lower = 0;
69 spin_unlock(&timebase_lock);
70 printk("CPU %i taken timebase\n", smp_processor_id());
71}
72
73/* CHRP with openpic */ 44/* CHRP with openpic */
74struct smp_ops_t chrp_smp_ops = { 45struct smp_ops_t chrp_smp_ops = {
75 .message_pass = smp_mpic_message_pass, 46 .message_pass = smp_mpic_message_pass,
76 .probe = smp_mpic_probe, 47 .probe = smp_mpic_probe,
77 .kick_cpu = smp_chrp_kick_cpu, 48 .kick_cpu = smp_chrp_kick_cpu,
78 .setup_cpu = smp_chrp_setup_cpu, 49 .setup_cpu = smp_chrp_setup_cpu,
79 .give_timebase = smp_chrp_give_timebase, 50 .give_timebase = rtas_give_timebase,
80 .take_timebase = smp_chrp_take_timebase, 51 .take_timebase = rtas_take_timebase,
81}; 52};
diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c
index 153051eb6d93..a4619347aa7e 100644
--- a/arch/powerpc/platforms/pasemi/setup.c
+++ b/arch/powerpc/platforms/pasemi/setup.c
@@ -71,20 +71,25 @@ static void pas_restart(char *cmd)
71} 71}
72 72
73#ifdef CONFIG_SMP 73#ifdef CONFIG_SMP
74static DEFINE_SPINLOCK(timebase_lock); 74static raw_spinlock_t timebase_lock;
75static unsigned long timebase; 75static unsigned long timebase;
76 76
77static void __devinit pas_give_timebase(void) 77static void __devinit pas_give_timebase(void)
78{ 78{
79 spin_lock(&timebase_lock); 79 unsigned long flags;
80
81 local_irq_save(flags);
82 hard_irq_disable();
83 __raw_spin_lock(&timebase_lock);
80 mtspr(SPRN_TBCTL, TBCTL_FREEZE); 84 mtspr(SPRN_TBCTL, TBCTL_FREEZE);
81 isync(); 85 isync();
82 timebase = get_tb(); 86 timebase = get_tb();
83 spin_unlock(&timebase_lock); 87 __raw_spin_unlock(&timebase_lock);
84 88
85 while (timebase) 89 while (timebase)
86 barrier(); 90 barrier();
87 mtspr(SPRN_TBCTL, TBCTL_RESTART); 91 mtspr(SPRN_TBCTL, TBCTL_RESTART);
92 local_irq_restore(flags);
88} 93}
89 94
90static void __devinit pas_take_timebase(void) 95static void __devinit pas_take_timebase(void)
@@ -92,10 +97,10 @@ static void __devinit pas_take_timebase(void)
92 while (!timebase) 97 while (!timebase)
93 smp_rmb(); 98 smp_rmb();
94 99
95 spin_lock(&timebase_lock); 100 __raw_spin_lock(&timebase_lock);
96 set_tb(timebase >> 32, timebase & 0xffffffff); 101 set_tb(timebase >> 32, timebase & 0xffffffff);
97 timebase = 0; 102 timebase = 0;
98 spin_unlock(&timebase_lock); 103 __raw_spin_unlock(&timebase_lock);
99} 104}
100 105
101struct smp_ops_t pas_smp_ops = { 106struct smp_ops_t pas_smp_ops = {
diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c
index 86f69a4eb49b..c20522656367 100644
--- a/arch/powerpc/platforms/powermac/setup.c
+++ b/arch/powerpc/platforms/powermac/setup.c
@@ -103,11 +103,6 @@ unsigned long smu_cmdbuf_abs;
103EXPORT_SYMBOL(smu_cmdbuf_abs); 103EXPORT_SYMBOL(smu_cmdbuf_abs);
104#endif 104#endif
105 105
106#ifdef CONFIG_SMP
107extern struct smp_ops_t psurge_smp_ops;
108extern struct smp_ops_t core99_smp_ops;
109#endif /* CONFIG_SMP */
110
111static void pmac_show_cpuinfo(struct seq_file *m) 106static void pmac_show_cpuinfo(struct seq_file *m)
112{ 107{
113 struct device_node *np; 108 struct device_node *np;
@@ -341,34 +336,6 @@ static void __init pmac_setup_arch(void)
341 ROOT_DEV = DEFAULT_ROOT_DEVICE; 336 ROOT_DEV = DEFAULT_ROOT_DEVICE;
342#endif 337#endif
343 338
344#ifdef CONFIG_SMP
345 /* Check for Core99 */
346 ic = of_find_node_by_name(NULL, "uni-n");
347 if (!ic)
348 ic = of_find_node_by_name(NULL, "u3");
349 if (!ic)
350 ic = of_find_node_by_name(NULL, "u4");
351 if (ic) {
352 of_node_put(ic);
353 smp_ops = &core99_smp_ops;
354 }
355#ifdef CONFIG_PPC32
356 else {
357 /*
358 * We have to set bits in cpu_possible_map here since the
359 * secondary CPU(s) aren't in the device tree, and
360 * setup_per_cpu_areas only allocates per-cpu data for
361 * CPUs in the cpu_possible_map.
362 */
363 int cpu;
364
365 for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu)
366 cpu_set(cpu, cpu_possible_map);
367 smp_ops = &psurge_smp_ops;
368 }
369#endif
370#endif /* CONFIG_SMP */
371
372#ifdef CONFIG_ADB 339#ifdef CONFIG_ADB
373 if (strstr(cmd_line, "adb_sync")) { 340 if (strstr(cmd_line, "adb_sync")) {
374 extern int __adb_probe_sync; 341 extern int __adb_probe_sync;
@@ -512,6 +479,14 @@ static void __init pmac_init_early(void)
512#ifdef CONFIG_PPC64 479#ifdef CONFIG_PPC64
513 iommu_init_early_dart(); 480 iommu_init_early_dart();
514#endif 481#endif
482
483 /* SMP Init has to be done early as we need to patch up
484 * cpu_possible_map before interrupt stacks are allocated
485 * or kaboom...
486 */
487#ifdef CONFIG_SMP
488 pmac_setup_smp();
489#endif
515} 490}
516 491
517static int __init pmac_declare_of_platform_devices(void) 492static int __init pmac_declare_of_platform_devices(void)
diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c
index cf1dbe758890..6d4da7b46b41 100644
--- a/arch/powerpc/platforms/powermac/smp.c
+++ b/arch/powerpc/platforms/powermac/smp.c
@@ -64,10 +64,11 @@
64extern void __secondary_start_pmac_0(void); 64extern void __secondary_start_pmac_0(void);
65extern int pmac_pfunc_base_install(void); 65extern int pmac_pfunc_base_install(void);
66 66
67#ifdef CONFIG_PPC32 67static void (*pmac_tb_freeze)(int freeze);
68static u64 timebase;
69static int tb_req;
68 70
69/* Sync flag for HW tb sync */ 71#ifdef CONFIG_PPC32
70static volatile int sec_tb_reset = 0;
71 72
72/* 73/*
73 * Powersurge (old powermac SMP) support. 74 * Powersurge (old powermac SMP) support.
@@ -294,6 +295,9 @@ static int __init smp_psurge_probe(void)
294 psurge_quad_init(); 295 psurge_quad_init();
295 /* All released cards using this HW design have 4 CPUs */ 296 /* All released cards using this HW design have 4 CPUs */
296 ncpus = 4; 297 ncpus = 4;
298 /* No sure how timebase sync works on those, let's use SW */
299 smp_ops->give_timebase = smp_generic_give_timebase;
300 smp_ops->take_timebase = smp_generic_take_timebase;
297 } else { 301 } else {
298 iounmap(quad_base); 302 iounmap(quad_base);
299 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { 303 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
@@ -308,18 +312,15 @@ static int __init smp_psurge_probe(void)
308 psurge_start = ioremap(PSURGE_START, 4); 312 psurge_start = ioremap(PSURGE_START, 4);
309 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); 313 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
310 314
311 /* 315 /* This is necessary because OF doesn't know about the
312 * This is necessary because OF doesn't know about the
313 * secondary cpu(s), and thus there aren't nodes in the 316 * secondary cpu(s), and thus there aren't nodes in the
314 * device tree for them, and smp_setup_cpu_maps hasn't 317 * device tree for them, and smp_setup_cpu_maps hasn't
315 * set their bits in cpu_possible_map and cpu_present_map. 318 * set their bits in cpu_present_map.
316 */ 319 */
317 if (ncpus > NR_CPUS) 320 if (ncpus > NR_CPUS)
318 ncpus = NR_CPUS; 321 ncpus = NR_CPUS;
319 for (i = 1; i < ncpus ; ++i) { 322 for (i = 1; i < ncpus ; ++i)
320 cpu_set(i, cpu_present_map); 323 cpu_set(i, cpu_present_map);
321 set_hard_smp_processor_id(i, i);
322 }
323 324
324 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); 325 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
325 326
@@ -329,8 +330,14 @@ static int __init smp_psurge_probe(void)
329static void __init smp_psurge_kick_cpu(int nr) 330static void __init smp_psurge_kick_cpu(int nr)
330{ 331{
331 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8; 332 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
332 unsigned long a; 333 unsigned long a, flags;
333 int i; 334 int i, j;
335
336 /* Defining this here is evil ... but I prefer hiding that
337 * crap to avoid giving people ideas that they can do the
338 * same.
339 */
340 extern volatile unsigned int cpu_callin_map[NR_CPUS];
334 341
335 /* may need to flush here if secondary bats aren't setup */ 342 /* may need to flush here if secondary bats aren't setup */
336 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) 343 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
@@ -339,47 +346,52 @@ static void __init smp_psurge_kick_cpu(int nr)
339 346
340 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); 347 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
341 348
349 /* This is going to freeze the timeebase, we disable interrupts */
350 local_irq_save(flags);
351
342 out_be32(psurge_start, start); 352 out_be32(psurge_start, start);
343 mb(); 353 mb();
344 354
345 psurge_set_ipi(nr); 355 psurge_set_ipi(nr);
356
346 /* 357 /*
347 * We can't use udelay here because the timebase is now frozen. 358 * We can't use udelay here because the timebase is now frozen.
348 */ 359 */
349 for (i = 0; i < 2000; ++i) 360 for (i = 0; i < 2000; ++i)
350 barrier(); 361 asm volatile("nop" : : : "memory");
351 psurge_clr_ipi(nr); 362 psurge_clr_ipi(nr);
352 363
353 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); 364 /*
354} 365 * Also, because the timebase is frozen, we must not return to the
355 366 * caller which will try to do udelay's etc... Instead, we wait -here-
356/* 367 * for the CPU to callin.
357 * With the dual-cpu powersurge board, the decrementers and timebases 368 */
358 * of both cpus are frozen after the secondary cpu is started up, 369 for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) {
359 * until we give the secondary cpu another interrupt. This routine 370 for (j = 1; j < 10000; j++)
360 * uses this to get the timebases synchronized. 371 asm volatile("nop" : : : "memory");
361 * -- paulus. 372 asm volatile("sync" : : : "memory");
362 */ 373 }
363static void __init psurge_dual_sync_tb(int cpu_nr) 374 if (!cpu_callin_map[nr])
364{ 375 goto stuck;
365 int t; 376
366 377 /* And we do the TB sync here too for standard dual CPU cards */
367 set_dec(tb_ticks_per_jiffy); 378 if (psurge_type == PSURGE_DUAL) {
368 /* XXX fixme */ 379 while(!tb_req)
369 set_tb(0, 0); 380 barrier();
370 381 tb_req = 0;
371 if (cpu_nr > 0) { 382 mb();
383 timebase = get_tb();
384 mb();
385 while (timebase)
386 barrier();
372 mb(); 387 mb();
373 sec_tb_reset = 1;
374 return;
375 } 388 }
389 stuck:
390 /* now interrupt the secondary, restarting both TBs */
391 if (psurge_type == PSURGE_DUAL)
392 psurge_set_ipi(1);
376 393
377 /* wait for the secondary to have reset its TB before proceeding */ 394 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
378 for (t = 10000000; t > 0 && !sec_tb_reset; --t)
379 ;
380
381 /* now interrupt the secondary, starting both TBs */
382 psurge_set_ipi(1);
383} 395}
384 396
385static struct irqaction psurge_irqaction = { 397static struct irqaction psurge_irqaction = {
@@ -390,36 +402,35 @@ static struct irqaction psurge_irqaction = {
390 402
391static void __init smp_psurge_setup_cpu(int cpu_nr) 403static void __init smp_psurge_setup_cpu(int cpu_nr)
392{ 404{
405 if (cpu_nr != 0)
406 return;
393 407
394 if (cpu_nr == 0) { 408 /* reset the entry point so if we get another intr we won't
395 /* If we failed to start the second CPU, we should still 409 * try to startup again */
396 * send it an IPI to start the timebase & DEC or we might 410 out_be32(psurge_start, 0x100);
397 * have them stuck. 411 if (setup_irq(30, &psurge_irqaction))
398 */ 412 printk(KERN_ERR "Couldn't get primary IPI interrupt");
399 if (num_online_cpus() < 2) {
400 if (psurge_type == PSURGE_DUAL)
401 psurge_set_ipi(1);
402 return;
403 }
404 /* reset the entry point so if we get another intr we won't
405 * try to startup again */
406 out_be32(psurge_start, 0x100);
407 if (setup_irq(30, &psurge_irqaction))
408 printk(KERN_ERR "Couldn't get primary IPI interrupt");
409 }
410
411 if (psurge_type == PSURGE_DUAL)
412 psurge_dual_sync_tb(cpu_nr);
413} 413}
414 414
415void __init smp_psurge_take_timebase(void) 415void __init smp_psurge_take_timebase(void)
416{ 416{
417 /* Dummy implementation */ 417 if (psurge_type != PSURGE_DUAL)
418 return;
419
420 tb_req = 1;
421 mb();
422 while (!timebase)
423 barrier();
424 mb();
425 set_tb(timebase >> 32, timebase & 0xffffffff);
426 timebase = 0;
427 mb();
428 set_dec(tb_ticks_per_jiffy/2);
418} 429}
419 430
420void __init smp_psurge_give_timebase(void) 431void __init smp_psurge_give_timebase(void)
421{ 432{
422 /* Dummy implementation */ 433 /* Nothing to do here */
423} 434}
424 435
425/* PowerSurge-style Macs */ 436/* PowerSurge-style Macs */
@@ -437,9 +448,6 @@ struct smp_ops_t psurge_smp_ops = {
437 * Core 99 and later support 448 * Core 99 and later support
438 */ 449 */
439 450
440static void (*pmac_tb_freeze)(int freeze);
441static u64 timebase;
442static int tb_req;
443 451
444static void smp_core99_give_timebase(void) 452static void smp_core99_give_timebase(void)
445{ 453{
@@ -478,7 +486,6 @@ static void __devinit smp_core99_take_timebase(void)
478 set_tb(timebase >> 32, timebase & 0xffffffff); 486 set_tb(timebase >> 32, timebase & 0xffffffff);
479 timebase = 0; 487 timebase = 0;
480 mb(); 488 mb();
481 set_dec(tb_ticks_per_jiffy/2);
482 489
483 local_irq_restore(flags); 490 local_irq_restore(flags);
484} 491}
@@ -920,3 +927,34 @@ struct smp_ops_t core99_smp_ops = {
920# endif 927# endif
921#endif 928#endif
922}; 929};
930
931void __init pmac_setup_smp(void)
932{
933 struct device_node *np;
934
935 /* Check for Core99 */
936 np = of_find_node_by_name(NULL, "uni-n");
937 if (!np)
938 np = of_find_node_by_name(NULL, "u3");
939 if (!np)
940 np = of_find_node_by_name(NULL, "u4");
941 if (np) {
942 of_node_put(np);
943 smp_ops = &core99_smp_ops;
944 }
945#ifdef CONFIG_PPC32
946 else {
947 /* We have to set bits in cpu_possible_map here since the
948 * secondary CPU(s) aren't in the device tree. Various
949 * things won't be initialized for CPUs not in the possible
950 * map, so we really need to fix it up here.
951 */
952 int cpu;
953
954 for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu)
955 cpu_set(cpu, cpu_possible_map);
956 smp_ops = &psurge_smp_ops;
957 }
958#endif /* CONFIG_PPC32 */
959}
960
diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c
index 1a231c389ba0..1f8f6cfb94f7 100644
--- a/arch/powerpc/platforms/pseries/smp.c
+++ b/arch/powerpc/platforms/pseries/smp.c
@@ -35,7 +35,6 @@
35#include <asm/prom.h> 35#include <asm/prom.h>
36#include <asm/smp.h> 36#include <asm/smp.h>
37#include <asm/paca.h> 37#include <asm/paca.h>
38#include <asm/time.h>
39#include <asm/machdep.h> 38#include <asm/machdep.h>
40#include <asm/cputable.h> 39#include <asm/cputable.h>
41#include <asm/firmware.h> 40#include <asm/firmware.h>
@@ -118,31 +117,6 @@ static void __devinit smp_xics_setup_cpu(int cpu)
118} 117}
119#endif /* CONFIG_XICS */ 118#endif /* CONFIG_XICS */
120 119
121static DEFINE_SPINLOCK(timebase_lock);
122static unsigned long timebase = 0;
123
124static void __devinit pSeries_give_timebase(void)
125{
126 spin_lock(&timebase_lock);
127 rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL);
128 timebase = get_tb();
129 spin_unlock(&timebase_lock);
130
131 while (timebase)
132 barrier();
133 rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL);
134}
135
136static void __devinit pSeries_take_timebase(void)
137{
138 while (!timebase)
139 barrier();
140 spin_lock(&timebase_lock);
141 set_tb(timebase >> 32, timebase & 0xffffffff);
142 timebase = 0;
143 spin_unlock(&timebase_lock);
144}
145
146static void __devinit smp_pSeries_kick_cpu(int nr) 120static void __devinit smp_pSeries_kick_cpu(int nr)
147{ 121{
148 BUG_ON(nr < 0 || nr >= NR_CPUS); 122 BUG_ON(nr < 0 || nr >= NR_CPUS);
@@ -209,8 +183,8 @@ static void __init smp_init_pseries(void)
209 183
210 /* Non-lpar has additional take/give timebase */ 184 /* Non-lpar has additional take/give timebase */
211 if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) { 185 if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) {
212 smp_ops->give_timebase = pSeries_give_timebase; 186 smp_ops->give_timebase = rtas_give_timebase;
213 smp_ops->take_timebase = pSeries_take_timebase; 187 smp_ops->take_timebase = rtas_take_timebase;
214 } 188 }
215 189
216 pr_debug(" <- smp_init_pSeries()\n"); 190 pr_debug(" <- smp_init_pSeries()\n");
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 9c3af5045495..d46de1f0f3ee 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -279,28 +279,29 @@ static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
279} 279}
280 280
281#ifdef CONFIG_PPC_DCR 281#ifdef CONFIG_PPC_DCR
282static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, 282static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
283 struct mpic_reg_bank *rb,
283 unsigned int offset, unsigned int size) 284 unsigned int offset, unsigned int size)
284{ 285{
285 const u32 *dbasep; 286 const u32 *dbasep;
286 287
287 dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL); 288 dbasep = of_get_property(node, "dcr-reg", NULL);
288 289
289 rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size); 290 rb->dhost = dcr_map(node, *dbasep + offset, size);
290 BUG_ON(!DCR_MAP_OK(rb->dhost)); 291 BUG_ON(!DCR_MAP_OK(rb->dhost));
291} 292}
292 293
293static inline void mpic_map(struct mpic *mpic, phys_addr_t phys_addr, 294static inline void mpic_map(struct mpic *mpic, struct device_node *node,
294 struct mpic_reg_bank *rb, unsigned int offset, 295 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
295 unsigned int size) 296 unsigned int offset, unsigned int size)
296{ 297{
297 if (mpic->flags & MPIC_USES_DCR) 298 if (mpic->flags & MPIC_USES_DCR)
298 _mpic_map_dcr(mpic, rb, offset, size); 299 _mpic_map_dcr(mpic, node, rb, offset, size);
299 else 300 else
300 _mpic_map_mmio(mpic, phys_addr, rb, offset, size); 301 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
301} 302}
302#else /* CONFIG_PPC_DCR */ 303#else /* CONFIG_PPC_DCR */
303#define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) 304#define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
304#endif /* !CONFIG_PPC_DCR */ 305#endif /* !CONFIG_PPC_DCR */
305 306
306 307
@@ -1052,11 +1053,10 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1052 int intvec_top; 1053 int intvec_top;
1053 u64 paddr = phys_addr; 1054 u64 paddr = phys_addr;
1054 1055
1055 mpic = alloc_bootmem(sizeof(struct mpic)); 1056 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1056 if (mpic == NULL) 1057 if (mpic == NULL)
1057 return NULL; 1058 return NULL;
1058 1059
1059 memset(mpic, 0, sizeof(struct mpic));
1060 mpic->name = name; 1060 mpic->name = name;
1061 1061
1062 mpic->hc_irq = mpic_irq_chip; 1062 mpic->hc_irq = mpic_irq_chip;
@@ -1152,8 +1152,8 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1152 } 1152 }
1153 1153
1154 /* Map the global registers */ 1154 /* Map the global registers */
1155 mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); 1155 mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1156 mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); 1156 mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1157 1157
1158 /* Reset */ 1158 /* Reset */
1159 if (flags & MPIC_WANTS_RESET) { 1159 if (flags & MPIC_WANTS_RESET) {
@@ -1194,7 +1194,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1194 1194
1195 /* Map the per-CPU registers */ 1195 /* Map the per-CPU registers */
1196 for (i = 0; i < mpic->num_cpus; i++) { 1196 for (i = 0; i < mpic->num_cpus; i++) {
1197 mpic_map(mpic, paddr, &mpic->cpuregs[i], 1197 mpic_map(mpic, node, paddr, &mpic->cpuregs[i],
1198 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), 1198 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1199 0x1000); 1199 0x1000);
1200 } 1200 }
@@ -1202,7 +1202,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1202 /* Initialize main ISU if none provided */ 1202 /* Initialize main ISU if none provided */
1203 if (mpic->isu_size == 0) { 1203 if (mpic->isu_size == 0) {
1204 mpic->isu_size = mpic->num_sources; 1204 mpic->isu_size = mpic->num_sources;
1205 mpic_map(mpic, paddr, &mpic->isus[0], 1205 mpic_map(mpic, node, paddr, &mpic->isus[0],
1206 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1206 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1207 } 1207 }
1208 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 1208 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
@@ -1256,8 +1256,10 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1256 1256
1257 BUG_ON(isu_num >= MPIC_MAX_ISU); 1257 BUG_ON(isu_num >= MPIC_MAX_ISU);
1258 1258
1259 mpic_map(mpic, paddr, &mpic->isus[isu_num], 0, 1259 mpic_map(mpic, mpic->irqhost->of_node,
1260 paddr, &mpic->isus[isu_num], 0,
1260 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); 1261 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1262
1261 if ((isu_first + mpic->isu_size) > mpic->num_sources) 1263 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1262 mpic->num_sources = isu_first + mpic->isu_size; 1264 mpic->num_sources = isu_first + mpic->isu_size;
1263} 1265}
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index b28b0e512d67..237e3654f48c 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -112,6 +112,7 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
112{ 112{
113 unsigned long flags; 113 unsigned long flags;
114 u8 mcn_shift = 0, dev_shift = 0; 114 u8 mcn_shift = 0, dev_shift = 0;
115 u32 ret;
115 116
116 spin_lock_irqsave(&qe_lock, flags); 117 spin_lock_irqsave(&qe_lock, flags);
117 if (cmd == QE_RESET) { 118 if (cmd == QE_RESET) {
@@ -139,11 +140,13 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
139 } 140 }
140 141
141 /* wait for the QE_CR_FLG to clear */ 142 /* wait for the QE_CR_FLG to clear */
142 while(in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) 143 ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
143 cpu_relax(); 144 100, 0);
145 /* On timeout (e.g. failure), the expression will be false (ret == 0),
146 otherwise it will be true (ret == 1). */
144 spin_unlock_irqrestore(&qe_lock, flags); 147 spin_unlock_irqrestore(&qe_lock, flags);
145 148
146 return 0; 149 return ret == 1;
147} 150}
148EXPORT_SYMBOL(qe_issue_cmd); 151EXPORT_SYMBOL(qe_issue_cmd);
149 152
diff --git a/drivers/char/bsr.c b/drivers/char/bsr.c
index 140ea10ecb88..c02db01f736e 100644
--- a/drivers/char/bsr.c
+++ b/drivers/char/bsr.c
@@ -27,6 +27,7 @@
27#include <linux/cdev.h> 27#include <linux/cdev.h>
28#include <linux/list.h> 28#include <linux/list.h>
29#include <linux/mm.h> 29#include <linux/mm.h>
30#include <asm/pgtable.h>
30#include <asm/io.h> 31#include <asm/io.h>
31 32
32/* 33/*
@@ -75,12 +76,13 @@ static struct class *bsr_class;
75static int bsr_major; 76static int bsr_major;
76 77
77enum { 78enum {
78 BSR_8 = 0, 79 BSR_8 = 0,
79 BSR_16 = 1, 80 BSR_16 = 1,
80 BSR_64 = 2, 81 BSR_64 = 2,
81 BSR_128 = 3, 82 BSR_128 = 3,
82 BSR_UNKNOWN = 4, 83 BSR_4096 = 4,
83 BSR_MAX = 5, 84 BSR_UNKNOWN = 5,
85 BSR_MAX = 6,
84}; 86};
85 87
86static unsigned bsr_types[BSR_MAX]; 88static unsigned bsr_types[BSR_MAX];
@@ -117,15 +119,22 @@ static int bsr_mmap(struct file *filp, struct vm_area_struct *vma)
117{ 119{
118 unsigned long size = vma->vm_end - vma->vm_start; 120 unsigned long size = vma->vm_end - vma->vm_start;
119 struct bsr_dev *dev = filp->private_data; 121 struct bsr_dev *dev = filp->private_data;
122 int ret;
120 123
121 if (size > dev->bsr_len || (size & (PAGE_SIZE-1)))
122 return -EINVAL;
123
124 vma->vm_flags |= (VM_IO | VM_DONTEXPAND);
125 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 124 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
126 125
127 if (io_remap_pfn_range(vma, vma->vm_start, dev->bsr_addr >> PAGE_SHIFT, 126 /* check for the case of a small BSR device and map one 4k page for it*/
128 size, vma->vm_page_prot)) 127 if (dev->bsr_len < PAGE_SIZE && size == PAGE_SIZE)
128 ret = remap_4k_pfn(vma, vma->vm_start, dev->bsr_addr >> 12,
129 vma->vm_page_prot);
130 else if (size <= dev->bsr_len)
131 ret = io_remap_pfn_range(vma, vma->vm_start,
132 dev->bsr_addr >> PAGE_SHIFT,
133 size, vma->vm_page_prot);
134 else
135 return -EINVAL;
136
137 if (ret)
129 return -EAGAIN; 138 return -EAGAIN;
130 139
131 return 0; 140 return 0;
@@ -205,6 +214,11 @@ static int bsr_add_node(struct device_node *bn)
205 cur->bsr_stride = bsr_stride[i]; 214 cur->bsr_stride = bsr_stride[i];
206 cur->bsr_dev = MKDEV(bsr_major, i + total_bsr_devs); 215 cur->bsr_dev = MKDEV(bsr_major, i + total_bsr_devs);
207 216
217 /* if we have a bsr_len of > 4k and less then PAGE_SIZE (64k pages) */
218 /* we can only map 4k of it, so only advertise the 4k in sysfs */
219 if (cur->bsr_len > 4096 && cur->bsr_len < PAGE_SIZE)
220 cur->bsr_len = 4096;
221
208 switch(cur->bsr_bytes) { 222 switch(cur->bsr_bytes) {
209 case 8: 223 case 8:
210 cur->bsr_type = BSR_8; 224 cur->bsr_type = BSR_8;
@@ -218,9 +232,11 @@ static int bsr_add_node(struct device_node *bn)
218 case 128: 232 case 128:
219 cur->bsr_type = BSR_128; 233 cur->bsr_type = BSR_128;
220 break; 234 break;
235 case 4096:
236 cur->bsr_type = BSR_4096;
237 break;
221 default: 238 default:
222 cur->bsr_type = BSR_UNKNOWN; 239 cur->bsr_type = BSR_UNKNOWN;
223 printk(KERN_INFO "unknown BSR size %d\n",cur->bsr_bytes);
224 } 240 }
225 241
226 cur->bsr_num = bsr_types[cur->bsr_type]; 242 cur->bsr_num = bsr_types[cur->bsr_type];
diff --git a/drivers/macintosh/macio_asic.c b/drivers/macintosh/macio_asic.c
index 6e149f4a1fff..a0f68386c12f 100644
--- a/drivers/macintosh/macio_asic.c
+++ b/drivers/macintosh/macio_asic.c
@@ -378,6 +378,17 @@ static struct macio_dev * macio_add_one_device(struct macio_chip *chip,
378 dev->ofdev.dev.bus = &macio_bus_type; 378 dev->ofdev.dev.bus = &macio_bus_type;
379 dev->ofdev.dev.release = macio_release_dev; 379 dev->ofdev.dev.release = macio_release_dev;
380 380
381#ifdef CONFIG_PCI
382 /* Set the DMA ops to the ones from the PCI device, this could be
383 * fishy if we didn't know that on PowerMac it's always direct ops
384 * or iommu ops that will work fine
385 */
386 dev->ofdev.dev.archdata.dma_ops =
387 chip->lbus.pdev->dev.archdata.dma_ops;
388 dev->ofdev.dev.archdata.dma_data =
389 chip->lbus.pdev->dev.archdata.dma_data;
390#endif /* CONFIG_PCI */
391
381#ifdef DEBUG 392#ifdef DEBUG
382 printk("preparing mdev @%p, ofdev @%p, dev @%p, kobj @%p\n", 393 printk("preparing mdev @%p, ofdev @%p, dev @%p, kobj @%p\n",
383 dev, &dev->ofdev, &dev->ofdev.dev, &dev->ofdev.dev.kobj); 394 dev, &dev->ofdev, &dev->ofdev.dev, &dev->ofdev.dev.kobj);
diff --git a/drivers/watchdog/wdrtas.c b/drivers/watchdog/wdrtas.c
index a4fe7a38d9b0..3bde56bce63a 100644
--- a/drivers/watchdog/wdrtas.c
+++ b/drivers/watchdog/wdrtas.c
@@ -218,16 +218,14 @@ static void wdrtas_timer_keepalive(void)
218 */ 218 */
219static int wdrtas_get_temperature(void) 219static int wdrtas_get_temperature(void)
220{ 220{
221 long result; 221 int result;
222 int temperature = 0; 222 int temperature = 0;
223 223
224 result = rtas_call(wdrtas_token_get_sensor_state, 2, 2, 224 result = rtas_get_sensor(WDRTAS_THERMAL_SENSOR, 0, &temperature);
225 (void *)__pa(&temperature),
226 WDRTAS_THERMAL_SENSOR, 0);
227 225
228 if (result < 0) 226 if (result < 0)
229 printk(KERN_WARNING "wdrtas: reading the thermal sensor " 227 printk(KERN_WARNING "wdrtas: reading the thermal sensor "
230 "faild: %li\n", result); 228 "failed: %i\n", result);
231 else 229 else
232 temperature = ((temperature * 9) / 5) + 32; /* fahrenheit */ 230 temperature = ((temperature * 9) / 5) + 32; /* fahrenheit */
233 231
diff --git a/scripts/dtc/.gitignore b/scripts/dtc/.gitignore
new file mode 100644
index 000000000000..095acb49a374
--- /dev/null
+++ b/scripts/dtc/.gitignore
@@ -0,0 +1,5 @@
1dtc
2dtc-lexer.lex.c
3dtc-parser.tab.c
4dtc-parser.tab.h
5