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-rw-r--r--arch/arm/mach-pxa/dma.c2
-rw-r--r--arch/arm/mach-pxa/include/mach/dma.h56
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa-regs.h59
-rw-r--r--drivers/media/video/pxa_camera.c1
-rw-r--r--drivers/mmc/host/pxamci.c3
-rw-r--r--drivers/mtd/nand/pxa3xx_nand.c1
-rw-r--r--drivers/spi/pxa2xx_spi.c2
-rw-r--r--sound/soc/pxa/pxa-ssp.c2
-rw-r--r--sound/soc/pxa/pxa2xx-ac97.c2
-rw-r--r--sound/soc/pxa/pxa2xx-i2s.c2
10 files changed, 60 insertions, 70 deletions
diff --git a/arch/arm/mach-pxa/dma.c b/arch/arm/mach-pxa/dma.c
index 4613bf1fe43c..01217e01f7d2 100644
--- a/arch/arm/mach-pxa/dma.c
+++ b/arch/arm/mach-pxa/dma.c
@@ -23,8 +23,6 @@
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24#include <mach/dma.h> 24#include <mach/dma.h>
25 25
26#include <mach/pxa-regs.h>
27
28struct dma_channel { 26struct dma_channel {
29 char *name; 27 char *name;
30 pxa_dma_prio prio; 28 pxa_dma_prio prio;
diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h
index 77607fe4bd65..b0812f59d3f8 100644
--- a/arch/arm/mach-pxa/include/mach/dma.h
+++ b/arch/arm/mach-pxa/include/mach/dma.h
@@ -12,6 +12,62 @@
12#ifndef __ASM_ARCH_DMA_H 12#ifndef __ASM_ARCH_DMA_H
13#define __ASM_ARCH_DMA_H 13#define __ASM_ARCH_DMA_H
14 14
15#include <mach/hardware.h>
16
17/* DMA Controller Registers Definitions */
18#define DMAC_REGS_VIRT io_p2v(0x40000000)
19#define DMAC_REG(x) (*((volatile u32 *)(DMAC_REGS_VIRT + (x))))
20
21#define DCSR(n) DMAC_REG((n) << 2)
22#define DALGN DMAC_REG(0x00a0) /* DMA Alignment Register */
23#define DINT DMAC_REG(0x00f0) /* DMA Interrupt Register */
24#define DDADR(n) DMAC_REG(0x0200 + ((n) << 4))
25#define DSADR(n) DMAC_REG(0x0204 + ((n) << 4))
26#define DTADR(n) DMAC_REG(0x0208 + ((n) << 4))
27#define DCMD(n) DMAC_REG(0x020c + ((n) << 4))
28#define DRCMR(n) DMAC_REG((((n) < 64) ? 0x0100 : 0x1100) + \
29 (((n) & 0x3f) << 2))
30
31#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
32#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
33#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
34#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
35#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
36#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
37#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
38#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
39
40#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
41#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
42#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
43#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
44#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
45#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
46#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
47#define DCSR_EORINTR (1 << 9) /* The end of Receive */
48#endif
49
50#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
51#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
52
53#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
54#define DDADR_STOP (1 << 0) /* Stop (read / write) */
55
56#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
57#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
58#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
59#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
60#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
61#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
62#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
63#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
64#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
65#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
66#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
67#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
68#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
69#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
70
15/* 71/*
16 * Descriptor structure for PXA's DMA engine 72 * Descriptor structure for PXA's DMA engine
17 * Note: this structure must always be aligned to a 16-byte boundary. 73 * Note: this structure must always be aligned to a 16-byte boundary.
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
index 31d615aa7723..7d8db197615c 100644
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h
@@ -65,65 +65,6 @@
65#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ 65#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
66#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ 66#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
67 67
68
69
70/*
71 * DMA Controller
72 */
73#define DCSR(x) __REG2(0x40000000, (x) << 2)
74
75#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
76#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
77#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
78#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
79#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
80#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
81#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
82#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
83
84#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
85#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
86#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
87#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
88#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
89#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
90#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
91#define DCSR_EORINTR (1 << 9) /* The end of Receive */
92#endif
93
94#define DALGN __REG(0x400000a0) /* DMA Alignment Register */
95#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
96
97#define DRCMR(n) (*(((n) < 64) ? \
98 &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
99 &__REG2(0x40001100, ((n) & 0x3f) << 2)))
100
101#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
102#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
103
104#define DDADR(x) __REG2(0x40000200, (x) << 4)
105#define DSADR(x) __REG2(0x40000204, (x) << 4)
106#define DTADR(x) __REG2(0x40000208, (x) << 4)
107#define DCMD(x) __REG2(0x4000020c, (x) << 4)
108
109#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
110#define DDADR_STOP (1 << 0) /* Stop (read / write) */
111
112#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
113#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
114#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
115#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
116#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
117#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
118#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
119#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
120#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
121#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
122#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
123#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
124#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
125#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
126
127/* 68/*
128 * Real Time Clock 69 * Real Time Clock
129 */ 70 */
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c
index a1d6008efcbb..e3e6b29ea6d2 100644
--- a/drivers/media/video/pxa_camera.c
+++ b/drivers/media/video/pxa_camera.c
@@ -35,7 +35,6 @@
35#include <linux/videodev2.h> 35#include <linux/videodev2.h>
36 36
37#include <mach/dma.h> 37#include <mach/dma.h>
38#include <mach/pxa-regs.h>
39#include <mach/camera.h> 38#include <mach/camera.h>
40 39
41#define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) 40#define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index 9702ad3774cf..430095725f9f 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -30,9 +30,8 @@
30 30
31#include <asm/sizes.h> 31#include <asm/sizes.h>
32 32
33#include <mach/dma.h>
34#include <mach/hardware.h> 33#include <mach/hardware.h>
35#include <mach/pxa-regs.h> 34#include <mach/dma.h>
36#include <mach/mmc.h> 35#include <mach/mmc.h>
37 36
38#include "pxamci.h" 37#include "pxamci.h"
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index cc55cbc2b308..61b69cc40009 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -22,7 +22,6 @@
22#include <linux/irq.h> 22#include <linux/irq.h>
23 23
24#include <mach/dma.h> 24#include <mach/dma.h>
25#include <mach/pxa-regs.h>
26#include <mach/pxa3xx_nand.h> 25#include <mach/pxa3xx_nand.h>
27 26
28#define CHIP_DELAY_TIMEOUT (2 * HZ/10) 27#define CHIP_DELAY_TIMEOUT (2 * HZ/10)
diff --git a/drivers/spi/pxa2xx_spi.c b/drivers/spi/pxa2xx_spi.c
index d0fc4ca2f656..d22fac27219a 100644
--- a/drivers/spi/pxa2xx_spi.c
+++ b/drivers/spi/pxa2xx_spi.c
@@ -34,8 +34,6 @@
34#include <asm/delay.h> 34#include <asm/delay.h>
35 35
36#include <mach/dma.h> 36#include <mach/dma.h>
37#include <mach/hardware.h>
38#include <mach/pxa-regs.h>
39#include <mach/regs-ssp.h> 37#include <mach/regs-ssp.h>
40#include <mach/ssp.h> 38#include <mach/ssp.h>
41#include <mach/pxa2xx_spi.h> 39#include <mach/pxa2xx_spi.h>
diff --git a/sound/soc/pxa/pxa-ssp.c b/sound/soc/pxa/pxa-ssp.c
index 73cb6b4c2f2d..1dfdf66fb1f3 100644
--- a/sound/soc/pxa/pxa-ssp.c
+++ b/sound/soc/pxa/pxa-ssp.c
@@ -29,7 +29,7 @@
29#include <sound/pxa2xx-lib.h> 29#include <sound/pxa2xx-lib.h>
30 30
31#include <mach/hardware.h> 31#include <mach/hardware.h>
32#include <mach/pxa-regs.h> 32#include <mach/dma.h>
33#include <mach/regs-ssp.h> 33#include <mach/regs-ssp.h>
34#include <mach/audio.h> 34#include <mach/audio.h>
35#include <mach/ssp.h> 35#include <mach/ssp.h>
diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c
index 812c2b4d3e07..a4a655f7e304 100644
--- a/sound/soc/pxa/pxa2xx-ac97.c
+++ b/sound/soc/pxa/pxa2xx-ac97.c
@@ -20,8 +20,8 @@
20#include <sound/pxa2xx-lib.h> 20#include <sound/pxa2xx-lib.h>
21 21
22#include <mach/hardware.h> 22#include <mach/hardware.h>
23#include <mach/pxa-regs.h>
24#include <mach/regs-ac97.h> 23#include <mach/regs-ac97.h>
24#include <mach/dma.h>
25 25
26#include "pxa2xx-pcm.h" 26#include "pxa2xx-pcm.h"
27#include "pxa2xx-ac97.h" 27#include "pxa2xx-ac97.h"
diff --git a/sound/soc/pxa/pxa2xx-i2s.c b/sound/soc/pxa/pxa2xx-i2s.c
index 517991fb1099..223de890259e 100644
--- a/sound/soc/pxa/pxa2xx-i2s.c
+++ b/sound/soc/pxa/pxa2xx-i2s.c
@@ -24,7 +24,7 @@
24#include <sound/pxa2xx-lib.h> 24#include <sound/pxa2xx-lib.h>
25 25
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/pxa-regs.h> 27#include <mach/dma.h>
28#include <mach/pxa2xx-gpio.h> 28#include <mach/pxa2xx-gpio.h>
29#include <mach/audio.h> 29#include <mach/audio.h>
30 30
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 08:44:05 -0500