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-rw-r--r--include/asm-ia64/uv/uv_hub.h309
-rw-r--r--include/asm-ia64/uv/uv_mmrs.h266
2 files changed, 575 insertions, 0 deletions
diff --git a/include/asm-ia64/uv/uv_hub.h b/include/asm-ia64/uv/uv_hub.h
new file mode 100644
index 000000000000..f607018af4a1
--- /dev/null
+++ b/include/asm-ia64/uv/uv_hub.h
@@ -0,0 +1,309 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV architectural definitions
7 *
8 * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef __ASM_IA64_UV_HUB_H__
12#define __ASM_IA64_UV_HUB_H__
13
14#include <linux/numa.h>
15#include <linux/percpu.h>
16#include <asm/types.h>
17#include <asm/percpu.h>
18
19
20/*
21 * Addressing Terminology
22 *
23 * M - The low M bits of a physical address represent the offset
24 * into the blade local memory. RAM memory on a blade is physically
25 * contiguous (although various IO spaces may punch holes in
26 * it)..
27 *
28 * N - Number of bits in the node portion of a socket physical
29 * address.
30 *
31 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
32 * routers always have low bit of 1, C/MBricks have low bit
33 * equal to 0. Most addressing macros that target UV hub chips
34 * right shift the NASID by 1 to exclude the always-zero bit.
35 * NASIDs contain up to 15 bits.
36 *
37 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
38 * of nasids.
39 *
40 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
41 * of the nasid for socket usage.
42 *
43 *
44 * NumaLink Global Physical Address Format:
45 * +--------------------------------+---------------------+
46 * |00..000| GNODE | NodeOffset |
47 * +--------------------------------+---------------------+
48 * |<-------53 - M bits --->|<--------M bits ----->
49 *
50 * M - number of node offset bits (35 .. 40)
51 *
52 *
53 * Memory/UV-HUB Processor Socket Address Format:
54 * +----------------+---------------+---------------------+
55 * |00..000000000000| PNODE | NodeOffset |
56 * +----------------+---------------+---------------------+
57 * <--- N bits --->|<--------M bits ----->
58 *
59 * M - number of node offset bits (35 .. 40)
60 * N - number of PNODE bits (0 .. 10)
61 *
62 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
63 * The actual values are configuration dependent and are set at
64 * boot time. M & N values are set by the hardware/BIOS at boot.
65 */
66
67
68/*
69 * Maximum number of bricks in all partitions and in all coherency domains.
70 * This is the total number of bricks accessible in the numalink fabric. It
71 * includes all C & M bricks. Routers are NOT included.
72 *
73 * This value is also the value of the maximum number of non-router NASIDs
74 * in the numalink fabric.
75 *
76 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
77 */
78#define UV_MAX_NUMALINK_BLADES 16384
79
80/*
81 * Maximum number of C/Mbricks within a software SSI (hardware may support
82 * more).
83 */
84#define UV_MAX_SSI_BLADES 1
85
86/*
87 * The largest possible NASID of a C or M brick (+ 2)
88 */
89#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2)
90
91/*
92 * The following defines attributes of the HUB chip. These attributes are
93 * frequently referenced and are kept in the per-cpu data areas of each cpu.
94 * They are kept together in a struct to minimize cache misses.
95 */
96struct uv_hub_info_s {
97 unsigned long global_mmr_base;
98 unsigned long gpa_mask;
99 unsigned long gnode_upper;
100 unsigned long lowmem_remap_top;
101 unsigned long lowmem_remap_base;
102 unsigned short pnode;
103 unsigned short pnode_mask;
104 unsigned short coherency_domain_number;
105 unsigned short numa_blade_id;
106 unsigned char blade_processor_id;
107 unsigned char m_val;
108 unsigned char n_val;
109};
110DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
111#define uv_hub_info (&__get_cpu_var(__uv_hub_info))
112#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
113
114/*
115 * Local & Global MMR space macros.
116 * Note: macros are intended to be used ONLY by inline functions
117 * in this file - not by other kernel code.
118 * n - NASID (full 15-bit global nasid)
119 * g - GNODE (full 15-bit global nasid, right shifted 1)
120 * p - PNODE (local part of nsids, right shifted 1)
121 */
122#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
123#define UV_PNODE_TO_NASID(p) (((p) << 1) | uv_hub_info->gnode_upper)
124
125#define UV_LOCAL_MMR_BASE 0xf4000000UL
126#define UV_GLOBAL_MMR32_BASE 0xf8000000UL
127#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
128
129#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
130#define UV_GLOBAL_MMR64_PNODE_SHIFT 26
131
132#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
133
134#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
135 ((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)
136
137/*
138 * Macros for converting between kernel virtual addresses, socket local physical
139 * addresses, and UV global physical addresses.
140 * Note: use the standard __pa() & __va() macros for converting
141 * between socket virtual and socket physical addresses.
142 */
143
144/* socket phys RAM --> UV global physical address */
145static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
146{
147 if (paddr < uv_hub_info->lowmem_remap_top)
148 paddr += uv_hub_info->lowmem_remap_base;
149 return paddr | uv_hub_info->gnode_upper;
150}
151
152
153/* socket virtual --> UV global physical address */
154static inline unsigned long uv_gpa(void *v)
155{
156 return __pa(v) | uv_hub_info->gnode_upper;
157}
158
159/* socket virtual --> UV global physical address */
160static inline void *uv_vgpa(void *v)
161{
162 return (void *)uv_gpa(v);
163}
164
165/* UV global physical address --> socket virtual */
166static inline void *uv_va(unsigned long gpa)
167{
168 return __va(gpa & uv_hub_info->gpa_mask);
169}
170
171/* pnode, offset --> socket virtual */
172static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
173{
174 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
175}
176
177
178/*
179 * Access global MMRs using the low memory MMR32 space. This region supports
180 * faster MMR access but not all MMRs are accessible in this space.
181 */
182static inline unsigned long *uv_global_mmr32_address(int pnode,
183 unsigned long offset)
184{
185 return __va(UV_GLOBAL_MMR32_BASE |
186 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
187}
188
189static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
190 unsigned long val)
191{
192 *uv_global_mmr32_address(pnode, offset) = val;
193}
194
195static inline unsigned long uv_read_global_mmr32(int pnode,
196 unsigned long offset)
197{
198 return *uv_global_mmr32_address(pnode, offset);
199}
200
201/*
202 * Access Global MMR space using the MMR space located at the top of physical
203 * memory.
204 */
205static inline unsigned long *uv_global_mmr64_address(int pnode,
206 unsigned long offset)
207{
208 return __va(UV_GLOBAL_MMR64_BASE |
209 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
210}
211
212static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
213 unsigned long val)
214{
215 *uv_global_mmr64_address(pnode, offset) = val;
216}
217
218static inline unsigned long uv_read_global_mmr64(int pnode,
219 unsigned long offset)
220{
221 return *uv_global_mmr64_address(pnode, offset);
222}
223
224/*
225 * Access hub local MMRs. Faster than using global space but only local MMRs
226 * are accessible.
227 */
228static inline unsigned long *uv_local_mmr_address(unsigned long offset)
229{
230 return __va(UV_LOCAL_MMR_BASE | offset);
231}
232
233static inline unsigned long uv_read_local_mmr(unsigned long offset)
234{
235 return *uv_local_mmr_address(offset);
236}
237
238static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
239{
240 *uv_local_mmr_address(offset) = val;
241}
242
243/*
244 * Structures and definitions for converting between cpu, node, pnode, and blade
245 * numbers.
246 */
247
248/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
249static inline int uv_blade_processor_id(void)
250{
251 return smp_processor_id();
252}
253
254/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
255static inline int uv_numa_blade_id(void)
256{
257 return 0;
258}
259
260/* Convert a cpu number to the the UV blade number */
261static inline int uv_cpu_to_blade_id(int cpu)
262{
263 return 0;
264}
265
266/* Convert linux node number to the UV blade number */
267static inline int uv_node_to_blade_id(int nid)
268{
269 return 0;
270}
271
272/* Convert a blade id to the PNODE of the blade */
273static inline int uv_blade_to_pnode(int bid)
274{
275 return 0;
276}
277
278/* Determine the number of possible cpus on a blade */
279static inline int uv_blade_nr_possible_cpus(int bid)
280{
281 return num_possible_cpus();
282}
283
284/* Determine the number of online cpus on a blade */
285static inline int uv_blade_nr_online_cpus(int bid)
286{
287 return num_online_cpus();
288}
289
290/* Convert a cpu id to the PNODE of the blade containing the cpu */
291static inline int uv_cpu_to_pnode(int cpu)
292{
293 return 0;
294}
295
296/* Convert a linux node number to the PNODE of the blade */
297static inline int uv_node_to_pnode(int nid)
298{
299 return 0;
300}
301
302/* Maximum possible number of blades */
303static inline int uv_num_possible_blades(void)
304{
305 return 1;
306}
307
308#endif /* __ASM_IA64_UV_HUB__ */
309
diff --git a/include/asm-ia64/uv/uv_mmrs.h b/include/asm-ia64/uv/uv_mmrs.h
new file mode 100644
index 000000000000..1cc1dbb0182f
--- /dev/null
+++ b/include/asm-ia64/uv/uv_mmrs.h
@@ -0,0 +1,266 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV MMR definitions
7 *
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef __ASM_IA64_UV_MMRS__
12#define __ASM_IA64_UV_MMRS__
13
14/*
15 * AUTO GENERATED - Do not edit
16 */
17
18 #define UV_MMR_ENABLE (1UL << 63)
19
20/* ========================================================================= */
21/* UVH_NODE_ID */
22/* ========================================================================= */
23#define UVH_NODE_ID 0x0UL
24
25#define UVH_NODE_ID_FORCE1_SHFT 0
26#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
27#define UVH_NODE_ID_MANUFACTURER_SHFT 1
28#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
29#define UVH_NODE_ID_PART_NUMBER_SHFT 12
30#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
31#define UVH_NODE_ID_REVISION_SHFT 28
32#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
33#define UVH_NODE_ID_NODE_ID_SHFT 32
34#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
35#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
36#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
37#define UVH_NODE_ID_NI_PORT_SHFT 56
38#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
39
40union uvh_node_id_u {
41 unsigned long v;
42 struct uvh_node_id_s {
43 unsigned long force1 : 1; /* RO */
44 unsigned long manufacturer : 11; /* RO */
45 unsigned long part_number : 16; /* RO */
46 unsigned long revision : 4; /* RO */
47 unsigned long node_id : 15; /* RW */
48 unsigned long rsvd_47 : 1; /* */
49 unsigned long nodes_per_bit : 7; /* RW */
50 unsigned long rsvd_55 : 1; /* */
51 unsigned long ni_port : 4; /* RO */
52 unsigned long rsvd_60_63 : 4; /* */
53 } s;
54};
55
56/* ========================================================================= */
57/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
58/* ========================================================================= */
59#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
60
61#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
62#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
63
64union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
65 unsigned long v;
66 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
67 unsigned long rsvd_0_23 : 24; /* */
68 unsigned long dest_base : 22; /* RW */
69 unsigned long rsvd_46_63: 18; /* */
70 } s;
71};
72
73/* ========================================================================= */
74/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
75/* ========================================================================= */
76#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
77
78#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
79#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
80
81union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
82 unsigned long v;
83 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
84 unsigned long rsvd_0_23 : 24; /* */
85 unsigned long dest_base : 22; /* RW */
86 unsigned long rsvd_46_63: 18; /* */
87 } s;
88};
89
90/* ========================================================================= */
91/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
92/* ========================================================================= */
93#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
94
95#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
96#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
97
98union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
99 unsigned long v;
100 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
101 unsigned long rsvd_0_23 : 24; /* */
102 unsigned long dest_base : 22; /* RW */
103 unsigned long rsvd_46_63: 18; /* */
104 } s;
105};
106
107/* ========================================================================= */
108/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
109/* ========================================================================= */
110#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
111
112#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
113#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
114#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 46
115#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0000400000000000UL
116#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
117#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
118#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
119#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
120
121union uvh_rh_gam_gru_overlay_config_mmr_u {
122 unsigned long v;
123 struct uvh_rh_gam_gru_overlay_config_mmr_s {
124 unsigned long rsvd_0_27: 28; /* */
125 unsigned long base : 18; /* RW */
126 unsigned long gr4 : 1; /* RW */
127 unsigned long rsvd_47_51: 5; /* */
128 unsigned long n_gru : 4; /* RW */
129 unsigned long rsvd_56_62: 7; /* */
130 unsigned long enable : 1; /* RW */
131 } s;
132};
133
134/* ========================================================================= */
135/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
136/* ========================================================================= */
137#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
138
139#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
140#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
141#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
142#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
143#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
144#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
145
146union uvh_rh_gam_mmr_overlay_config_mmr_u {
147 unsigned long v;
148 struct uvh_rh_gam_mmr_overlay_config_mmr_s {
149 unsigned long rsvd_0_25: 26; /* */
150 unsigned long base : 20; /* RW */
151 unsigned long dual_hub : 1; /* RW */
152 unsigned long rsvd_47_62: 16; /* */
153 unsigned long enable : 1; /* RW */
154 } s;
155};
156
157/* ========================================================================= */
158/* UVH_RTC */
159/* ========================================================================= */
160#define UVH_RTC 0x28000UL
161
162#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
163#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
164
165union uvh_rtc_u {
166 unsigned long v;
167 struct uvh_rtc_s {
168 unsigned long real_time_clock : 56; /* RW */
169 unsigned long rsvd_56_63 : 8; /* */
170 } s;
171};
172
173/* ========================================================================= */
174/* UVH_SI_ADDR_MAP_CONFIG */
175/* ========================================================================= */
176#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
177
178#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
179#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
180#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
181#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
182
183union uvh_si_addr_map_config_u {
184 unsigned long v;
185 struct uvh_si_addr_map_config_s {
186 unsigned long m_skt : 6; /* RW */
187 unsigned long rsvd_6_7: 2; /* */
188 unsigned long n_skt : 4; /* RW */
189 unsigned long rsvd_12_63: 52; /* */
190 } s;
191};
192
193/* ========================================================================= */
194/* UVH_SI_ALIAS0_OVERLAY_CONFIG */
195/* ========================================================================= */
196#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
197
198#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
199#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
200#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
201#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
202#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
203#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
204
205union uvh_si_alias0_overlay_config_u {
206 unsigned long v;
207 struct uvh_si_alias0_overlay_config_s {
208 unsigned long rsvd_0_23: 24; /* */
209 unsigned long base : 8; /* RW */
210 unsigned long rsvd_32_47: 16; /* */
211 unsigned long m_alias : 5; /* RW */
212 unsigned long rsvd_53_62: 10; /* */
213 unsigned long enable : 1; /* RW */
214 } s;
215};
216
217/* ========================================================================= */
218/* UVH_SI_ALIAS1_OVERLAY_CONFIG */
219/* ========================================================================= */
220#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
221
222#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
223#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
224#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
225#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
226#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
227#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
228
229union uvh_si_alias1_overlay_config_u {
230 unsigned long v;
231 struct uvh_si_alias1_overlay_config_s {
232 unsigned long rsvd_0_23: 24; /* */
233 unsigned long base : 8; /* RW */
234 unsigned long rsvd_32_47: 16; /* */
235 unsigned long m_alias : 5; /* RW */
236 unsigned long rsvd_53_62: 10; /* */
237 unsigned long enable : 1; /* RW */
238 } s;
239};
240
241/* ========================================================================= */
242/* UVH_SI_ALIAS2_OVERLAY_CONFIG */
243/* ========================================================================= */
244#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
245
246#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
247#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
248#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
249#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
250#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
251#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
252
253union uvh_si_alias2_overlay_config_u {
254 unsigned long v;
255 struct uvh_si_alias2_overlay_config_s {
256 unsigned long rsvd_0_23: 24; /* */
257 unsigned long base : 8; /* RW */
258 unsigned long rsvd_32_47: 16; /* */
259 unsigned long m_alias : 5; /* RW */
260 unsigned long rsvd_53_62: 10; /* */
261 unsigned long enable : 1; /* RW */
262 } s;
263};
264
265
266#endif /* __ASM_IA64_UV_MMRS__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 04:31:40 -0500