diff options
-rw-r--r-- | arch/sparc/kernel/smp.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/sparc/kernel/smp.c b/arch/sparc/kernel/smp.c index a93f5da6855d..40b42c88e6a7 100644 --- a/arch/sparc/kernel/smp.c +++ b/arch/sparc/kernel/smp.c | |||
@@ -69,6 +69,17 @@ void __init smp_store_cpu_info(int id) | |||
69 | "clock-frequency", 0); | 69 | "clock-frequency", 0); |
70 | cpu_data(id).prom_node = cpu_node; | 70 | cpu_data(id).prom_node = cpu_node; |
71 | cpu_data(id).mid = cpu_get_hwmid(cpu_node); | 71 | cpu_data(id).mid = cpu_get_hwmid(cpu_node); |
72 | |||
73 | /* this is required to tune the scheduler correctly */ | ||
74 | /* is it possible to have CPUs with different cache sizes? */ | ||
75 | if (id == boot_cpu_id) { | ||
76 | int cache_line,cache_nlines; | ||
77 | cache_line = 0x20; | ||
78 | cache_line = prom_getintdefault(cpu_node, "ecache-line-size", cache_line); | ||
79 | cache_nlines = 0x8000; | ||
80 | cache_nlines = prom_getintdefault(cpu_node, "ecache-nlines", cache_nlines); | ||
81 | max_cache_size = cache_line * cache_nlines; | ||
82 | } | ||
72 | if (cpu_data(id).mid < 0) | 83 | if (cpu_data(id).mid < 0) |
73 | panic("No MID found for CPU%d at node 0x%08d", id, cpu_node); | 84 | panic("No MID found for CPU%d at node 0x%08d", id, cpu_node); |
74 | } | 85 | } |