427 files changed, 20368 insertions, 5778 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index ab61fb44b4a3..391d57eec003 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5676,7 +5676,8 @@ F:	arch/arm/mach-s3c2410/bast-ide.c
 F:      arch/arm/mach-s3c2410/bast-irq.c
 
 TI DAVINCI MACHINE SUPPORT
-M:      Kevin Hilman <khilman@deeprootsystems.com>
+M:      Sekhar Nori <nsekhar@ti.com>
+M:      Kevin Hilman <khilman@ti.com>
 L:      davinci-linux-open-source@linux.davincidsp.com (subscribers-only)
 Q:      http://patchwork.kernel.org/project/linux-davinci/list/
 S:      Supported
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e34bf0272da4..b70fe202c00b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -722,7 +722,8 @@ config ARCH_S5P64X0
         select GENERIC_GPIO
         select HAVE_CLK
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
-        select ARCH_USES_GETTIMEOFFSET
+        select GENERIC_CLOCKEVENTS
+        select HAVE_SCHED_CLOCK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C_RTC if RTC_CLASS
         help
@@ -760,15 +761,16 @@ config ARCH_S5PV210
         select HAVE_CLK
         select ARM_L1_CACHE_SHIFT_6
         select ARCH_HAS_CPUFREQ
-        select ARCH_USES_GETTIMEOFFSET
+        select GENERIC_CLOCKEVENTS
+        select HAVE_SCHED_CLOCK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C_RTC if RTC_CLASS
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         help
           Samsung S5PV210/S5PC110 series based systems
 
-config ARCH_S5PV310
-        bool "Samsung S5PV310/S5PC210"
+config ARCH_EXYNOS4
+        bool "Samsung EXYNOS4"
         select CPU_V7
         select ARCH_SPARSEMEM_ENABLE
         select GENERIC_GPIO
@@ -779,7 +781,7 @@ config ARCH_S5PV310
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         help
-          Samsung S5PV310 series based systems
+          Samsung EXYNOS4 series based systems
 
 config ARCH_SHARK
         bool "Shark"
@@ -993,7 +995,7 @@ source "arch/arm/mach-s5pc100/Kconfig"
 
 source "arch/arm/mach-s5pv210/Kconfig"
 
-source "arch/arm/mach-s5pv310/Kconfig"
+source "arch/arm/mach-exynos4/Kconfig"
 
 source "arch/arm/mach-shmobile/Kconfig"
 
@@ -1315,7 +1317,7 @@ config SMP
         depends on GENERIC_CLOCKEVENTS
         depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
                  MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
-                 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
+                 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
                  ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
         select USE_GENERIC_SMP_HELPERS
         select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
@@ -1403,7 +1405,7 @@ config LOCAL_TIMERS
         bool "Use local timer interrupts"
         depends on SMP
         default y
-        select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP
+        select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
         help
           Enable support for local timers on SMP platforms, rather then the
           legacy IPI broadcast method.  Local timers allows the system
@@ -1415,7 +1417,7 @@ source kernel/Kconfig.preempt
 config HZ
         int
         default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
-                ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
+                ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
         default AT91_TIMER_HZ if ARCH_AT91
         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5c7114bb8a25..c7d321a3d95d 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -181,7 +181,7 @@ machine-$(CONFIG_ARCH_S5P64X0)		:= s5p64x0
 machine-$(CONFIG_ARCH_S5P6442)          := s5p6442
 machine-$(CONFIG_ARCH_S5PC100)          := s5pc100
 machine-$(CONFIG_ARCH_S5PV210)          := s5pv210
-machine-$(CONFIG_ARCH_S5PV310)          := s5pv310
+machine-$(CONFIG_ARCH_EXYNOS4)          := exynos4
 machine-$(CONFIG_ARCH_SA1100)           := sa1100
 machine-$(CONFIG_ARCH_SHARK)            := shark
 machine-$(CONFIG_ARCH_SHMOBILE)         := shmobile
diff --git a/arch/arm/configs/exynos4_defconfig b/arch/arm/configs/exynos4_defconfig
new file mode 100644
index 000000000000..2ffba24d2e2a
--- /dev/null
+++ b/arch/arm/configs/exynos4_defconfig
@@ -0,0 +1,70 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_EXYNOS4=y
+CONFIG_S3C_LOWLEVEL_UART_PORT=1
+CONFIG_MACH_SMDKC210=y
+CONFIG_MACH_SMDKV310=y
+CONFIG_MACH_UNIVERSAL_C210=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_HOTPLUG_CPU=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+# CONFIG_HWMON is not set
+# CONFIG_MFD_SUPPORT is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CRAMFS=y
+CONFIG_ROMFS_FS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_DEBUG_S3C_UART=1
+CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 2f7042813765..aeb3af541fed 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -24,6 +24,7 @@ CONFIG_MACH_OPENRD_ULTIMATE=y
 CONFIG_MACH_NETSPACE_V2=y
 CONFIG_MACH_INETSPACE_V2=y
 CONFIG_MACH_NETSPACE_MAX_V2=y
+CONFIG_MACH_D2NET_V2=y
 CONFIG_MACH_NET2BIG_V2=y
 CONFIG_MACH_NET5BIG_V2=y
 CONFIG_MACH_T5325=y
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig
index 9cba68cfa51a..e3c903281f70 100644
--- a/arch/arm/configs/mx51_defconfig
+++ b/arch/arm/configs/mx51_defconfig
@@ -110,7 +110,7 @@ CONFIG_MMC=y
 CONFIG_MMC_BLOCK=m
 CONFIG_MMC_SDHCI=m
 CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=m
+CONFIG_LEDS_CLASS=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_INTF_DEV_UIE_EMUL=y
 CONFIG_EXT2_FS=y
diff --git a/arch/arm/configs/s5p64x0_defconfig b/arch/arm/configs/s5p64x0_defconfig
index 2993ecd35145..ad6b61b0bd11 100644
--- a/arch/arm/configs/s5p64x0_defconfig
+++ b/arch/arm/configs/s5p64x0_defconfig
@@ -10,6 +10,8 @@ CONFIG_S3C_BOOT_ERROR_RESET=y
 CONFIG_S3C_LOWLEVEL_UART_PORT=1
 CONFIG_MACH_SMDK6440=y
 CONFIG_MACH_SMDK6450=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_CPU_32v6K=y
 CONFIG_AEABI=y
 CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig
index 0488a1eb4d7d..fa989902236d 100644
--- a/arch/arm/configs/s5pv210_defconfig
+++ b/arch/arm/configs/s5pv210_defconfig
@@ -13,6 +13,8 @@ CONFIG_MACH_AQUILA=y
 CONFIG_MACH_GONI=y
 CONFIG_MACH_SMDKC110=y
 CONFIG_MACH_SMDKV210=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_VMSPLIT_2G=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h
index c0094d8edae4..c2b9b4bdec00 100644
--- a/arch/arm/include/asm/kexec.h
+++ b/arch/arm/include/asm/kexec.h
@@ -50,6 +50,9 @@ static inline void crash_setup_regs(struct pt_regs *newregs,
         }
 }
 
+/* Function pointer to optional machine-specific reinitialization */
+extern void (*kexec_reinit)(void);
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* CONFIG_KEXEC */
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 8ccea012722c..7544ce6b481a 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -12,11 +12,25 @@
 #ifndef __ARM_PMU_H__
 #define __ARM_PMU_H__
 
+#include <linux/interrupt.h>
+
 enum arm_pmu_type {
         ARM_PMU_DEVICE_CPU      = 0,
         ARM_NUM_PMU_DEVICES,
 };
 
+/*
+ * struct arm_pmu_platdata - ARM PMU platform data
+ *
+ * @handle_irq: an optional handler which will be called from the interrupt and
+ * passed the address of the low level handler, and can be used to implement
+ * any platform specific handling before or after calling it.
+ */
+struct arm_pmu_platdata {
+        irqreturn_t (*handle_irq)(int irq, void *dev,
+                                  irq_handler_t pmu_handler);
+};
+
 #ifdef CONFIG_CPU_HAS_PMU
 
 /**
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 30ead135ff5f..e59bbd496c39 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -75,6 +75,11 @@ void machine_crash_shutdown(struct pt_regs *regs)
         printk(KERN_INFO "Loading crashdump kernel...\n");
 }
 
+/*
+ * Function pointer to optional machine-specific reinitialization
+ */
+void (*kexec_reinit)(void);
+
 void machine_kexec(struct kimage *image)
 {
         unsigned long page_list;
@@ -104,6 +109,8 @@ void machine_kexec(struct kimage *image)
                            (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
         printk(KERN_INFO "Bye!\n");
 
+        if (kexec_reinit)
+                kexec_reinit();
         local_irq_disable();
         local_fiq_disable();
         setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index d150ad1ccb5d..22e194eb8536 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -377,9 +377,18 @@ validate_group(struct perf_event *event)
         return 0;
 }
 
+static irqreturn_t armpmu_platform_irq(int irq, void *dev)
+{
+        struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev);
+
+        return plat->handle_irq(irq, dev, armpmu->handle_irq);
+}
+
 static int
 armpmu_reserve_hardware(void)
 {
+        struct arm_pmu_platdata *plat;
+        irq_handler_t handle_irq;
         int i, err = -ENODEV, irq;
 
         pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU);
@@ -390,6 +399,12 @@ armpmu_reserve_hardware(void)
 
         init_pmu(ARM_PMU_DEVICE_CPU);
 
+        plat = dev_get_platdata(&pmu_device->dev);
+        if (plat && plat->handle_irq)
+                handle_irq = armpmu_platform_irq;
+        else
+                handle_irq = armpmu->handle_irq;
+
         if (pmu_device->num_resources < 1) {
                 pr_err("no irqs for PMUs defined\n");
                 return -ENODEV;
@@ -400,7 +415,7 @@ armpmu_reserve_hardware(void)
                 if (irq < 0)
                         continue;
 
-                err = request_irq(irq, armpmu->handle_irq,
+                err = request_irq(irq, handle_irq,
                                   IRQF_DISABLED | IRQF_NOBALANCING,
                                   "armpmu", NULL);
                 if (err) {
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index b52a3a1abd94..8bc3701aa05c 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -20,6 +20,8 @@
 #include <linux/i2c/at24.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -30,6 +32,7 @@
 #include <mach/da8xx.h>
 #include <mach/usb.h>
 #include <mach/aemif.h>
+#include <mach/spi.h>
 
 #define DA830_EVM_PHY_ID                ""
 /*
@@ -534,6 +537,64 @@ static struct edma_rsv_info da830_edma_rsv[] = {
         },
 };
 
+static struct mtd_partition da830evm_spiflash_part[] = {
+        [0] = {
+                .name = "DSP-UBL",
+                .offset = 0,
+                .size = SZ_8K,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        [1] = {
+                .name = "ARM-UBL",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_16K + SZ_8K,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        [2] = {
+                .name = "U-Boot",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_256K - SZ_32K,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        [3] = {
+                .name = "U-Boot-Environment",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_16K,
+                .mask_flags = 0,
+        },
+        [4] = {
+                .name = "Kernel",
+                .offset = MTDPART_OFS_APPEND,
+                .size = MTDPART_SIZ_FULL,
+                .mask_flags = 0,
+        },
+};
+
+static struct flash_platform_data da830evm_spiflash_data = {
+        .name           = "m25p80",
+        .parts          = da830evm_spiflash_part,
+        .nr_parts       = ARRAY_SIZE(da830evm_spiflash_part),
+        .type           = "w25x32",
+};
+
+static struct davinci_spi_config da830evm_spiflash_cfg = {
+        .io_type        = SPI_IO_TYPE_DMA,
+        .c2tdelay       = 8,
+        .t2cdelay       = 8,
+};
+
+static struct spi_board_info da830evm_spi_info[] = {
+        {
+                .modalias               = "m25p80",
+                .platform_data          = &da830evm_spiflash_data,
+                .controller_data        = &da830evm_spiflash_cfg,
+                .mode                   = SPI_MODE_0,
+                .max_speed_hz           = 30000000,
+                .bus_num                = 0,
+                .chip_select            = 0,
+        },
+};
+
 static __init void da830_evm_init(void)
 {
         struct davinci_soc_info *soc_info = &davinci_soc_info;
@@ -590,6 +651,12 @@ static __init void da830_evm_init(void)
         ret = da8xx_register_rtc();
         if (ret)
                 pr_warning("da830_evm_init: rtc setup failed: %d\n", ret);
+
+        ret = da8xx_register_spi(0, da830evm_spi_info,
+                                 ARRAY_SIZE(da830evm_spi_info));
+        if (ret)
+                pr_warning("da830_evm_init: spi 0 registration failed: %d\n",
+                           ret);
 }
 
 #ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index b01fb2ab944a..a7b41bf505f1 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -29,6 +29,8 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/tps6507x.h>
 #include <linux/input/tps6507x-ts.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -38,6 +40,7 @@
 #include <mach/nand.h>
 #include <mach/mux.h>
 #include <mach/aemif.h>
+#include <mach/spi.h>
 
 #define DA850_EVM_PHY_ID                "0:00"
 #define DA850_LCD_PWR_PIN               GPIO_TO_PIN(2, 8)
@@ -48,6 +51,70 @@
 
 #define DA850_MII_MDIO_CLKEN_PIN        GPIO_TO_PIN(2, 6)
 
+static struct mtd_partition da850evm_spiflash_part[] = {
+        [0] = {
+                .name = "UBL",
+                .offset = 0,
+                .size = SZ_64K,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        [1] = {
+                .name = "U-Boot",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_512K,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        [2] = {
+                .name = "U-Boot-Env",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_64K,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        [3] = {
+                .name = "Kernel",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_2M + SZ_512K,
+                .mask_flags = 0,
+        },
+        [4] = {
+                .name = "Filesystem",
+                .offset = MTDPART_OFS_APPEND,
+                .size = SZ_4M,
+                .mask_flags = 0,
+        },
+        [5] = {
+                .name = "MAC-Address",
+                .offset = SZ_8M - SZ_64K,
+                .size = SZ_64K,
+                .mask_flags = MTD_WRITEABLE,
+        },
+};
+
+static struct flash_platform_data da850evm_spiflash_data = {
+        .name           = "m25p80",
+        .parts          = da850evm_spiflash_part,
+        .nr_parts       = ARRAY_SIZE(da850evm_spiflash_part),
+        .type           = "m25p64",
+};
+
+static struct davinci_spi_config da850evm_spiflash_cfg = {
+        .io_type        = SPI_IO_TYPE_DMA,
+        .c2tdelay       = 8,
+        .t2cdelay       = 8,
+};
+
+static struct spi_board_info da850evm_spi_info[] = {
+        {
+                .modalias               = "m25p80",
+                .platform_data          = &da850evm_spiflash_data,
+                .controller_data        = &da850evm_spiflash_cfg,
+                .mode                   = SPI_MODE_0,
+                .max_speed_hz           = 30000000,
+                .bus_num                = 1,
+                .chip_select            = 0,
+        },
+};
+
 static struct mtd_partition da850_evm_norflash_partition[] = {
         {
                 .name           = "bootloaders + env",
@@ -231,8 +298,6 @@ static const short da850_evm_nor_pins[] = {
         -1
 };
 
-static u32 ui_card_detected;
-
 #if defined(CONFIG_MMC_DAVINCI) || \
     defined(CONFIG_MMC_DAVINCI_MODULE)
 #define HAS_MMC 1
@@ -244,7 +309,7 @@ static inline void da850_evm_setup_nor_nand(void)
 {
         int ret = 0;
 
-        if (ui_card_detected & !HAS_MMC) {
+        if (!HAS_MMC) {
                 ret = davinci_cfg_reg_list(da850_evm_nand_pins);
                 if (ret)
                         pr_warning("da850_evm_init: nand mux setup failed: "
@@ -394,7 +459,6 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
                 goto exp_setup_keys_fail;
         }
 
-        ui_card_detected = 1;
         pr_info("DA850/OMAP-L138 EVM UI card detected\n");
 
         da850_evm_setup_nor_nand();
@@ -664,6 +728,13 @@ static struct snd_platform_data da850_evm_snd_data = {
         .rxnumevt       = 1,
 };
 
+static const short da850_evm_mcasp_pins[] __initconst = {
+        DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
+        DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
+        DA850_AXR_11, DA850_AXR_12,
+        -1
+};
+
 static int da850_evm_mmc_get_ro(int index)
 {
         return gpio_get_value(DA850_MMCSD_WP_PIN);
@@ -683,6 +754,13 @@ static struct davinci_mmc_config da850_mmc_config = {
         .version        = MMC_CTLR_VERSION_2,
 };
 
+static const short da850_evm_mmcsd0_pins[] __initconst = {
+        DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
+        DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
+        DA850_GPIO4_0, DA850_GPIO4_1,
+        -1
+};
+
 static void da850_panel_power_ctrl(int val)
 {
         /* lcd backlight */
@@ -1070,7 +1148,7 @@ static __init void da850_evm_init(void)
                                 ret);
 
         if (HAS_MMC) {
-                ret = davinci_cfg_reg_list(da850_mmcsd0_pins);
+                ret = davinci_cfg_reg_list(da850_evm_mmcsd0_pins);
                 if (ret)
                         pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
                                         " %d\n", ret);
@@ -1106,7 +1184,7 @@ static __init void da850_evm_init(void)
         __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
         __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
 
-        ret = davinci_cfg_reg_list(da850_mcasp_pins);
+        ret = davinci_cfg_reg_list(da850_evm_mcasp_pins);
         if (ret)
                 pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
                                 ret);
@@ -1153,6 +1231,12 @@ static __init void da850_evm_init(void)
         if (ret)
                 pr_warning("da850_evm_init: suspend registration failed: %d\n",
                                 ret);
+
+        ret = da8xx_register_spi(1, da850evm_spi_info,
+                                 ARRAY_SIZE(da850evm_spi_info));
+        if (ret)
+                pr_warning("da850_evm_init: spi 1 registration failed: %d\n",
+                                ret);
 }
 
 #ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 0ca90b834586..556bbd468db3 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -440,11 +440,6 @@ evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
         gpio_request(gpio + 7, "nCF_SEL");
         gpio_direction_output(gpio + 7, 1);
 
-        /* irlml6401 switches over 1A, in under 8 msec;
-         * now it can be managed by nDRV_VBUS ...
-         */
-        davinci_setup_usb(1000, 8);
-
         return 0;
 }
 
@@ -705,6 +700,9 @@ static __init void davinci_evm_init(void)
         davinci_serial_init(&uart_config);
         dm644x_init_asp(&dm644x_evm_snd_data);
 
+        /* irlml6401 switches over 1A, in under 8 msec */
+        davinci_setup_usb(1000, 8);
+
         soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
         /* Register the fixup for PHY on DaVinci */
         phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 0bb5f0ce4fdc..2aa79c54f98e 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -17,6 +17,8 @@
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
 #include <linux/etherdevice.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -25,6 +27,7 @@
 #include <mach/da8xx.h>
 #include <mach/nand.h>
 #include <mach/mux.h>
+#include <mach/spi.h>
 
 #define MITYOMAPL138_PHY_ID             "0:03"
 
@@ -44,38 +47,109 @@ struct factory_config {
 
 static struct factory_config factory_config;
 
+struct part_no_info {
+        const char      *part_no;       /* part number string of interest */
+        int             max_freq;       /* khz */
+};
+
+static struct part_no_info mityomapl138_pn_info[] = {
+        {
+                .part_no        = "L138-C",
+                .max_freq       = 300000,
+        },
+        {
+                .part_no        = "L138-D",
+                .max_freq       = 375000,
+        },
+        {
+                .part_no        = "L138-F",
+                .max_freq       = 456000,
+        },
+        {
+                .part_no        = "1808-C",
+                .max_freq       = 300000,
+        },
+        {
+                .part_no        = "1808-D",
+                .max_freq       = 375000,
+        },
+        {
+                .part_no        = "1808-F",
+                .max_freq       = 456000,
+        },
+        {
+                .part_no        = "1810-D",
+                .max_freq       = 375000,
+        },
+};
+
+#ifdef CONFIG_CPU_FREQ
+static void mityomapl138_cpufreq_init(const char *partnum)
+{
+        int i, ret;
+
+        for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
+                /*
+                 * the part number has additional characters beyond what is
+                 * stored in the table.  This information is not needed for
+                 * determining the speed grade, and would require several
+                 * more table entries.  Only check the first N characters
+                 * for a match.
+                 */
+                if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
+                             strlen(mityomapl138_pn_info[i].part_no))) {
+                        da850_max_speed = mityomapl138_pn_info[i].max_freq;
+                        break;
+                }
+        }
+
+        ret = da850_register_cpufreq("pll0_sysclk3");
+        if (ret)
+                pr_warning("cpufreq registration failed: %d\n", ret);
+}
+#else
+static void mityomapl138_cpufreq_init(const char *partnum) { }
+#endif
+
 static void read_factory_config(struct memory_accessor *a, void *context)
 {
         int ret;
+        const char *partnum = NULL;
         struct davinci_soc_info *soc_info = &davinci_soc_info;
 
         ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
         if (ret != sizeof(struct factory_config)) {
                 pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
                                 ret);
-                return;
+                goto bad_config;
         }
 
         if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
                 pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
                                 factory_config.magic);
-                return;
+                goto bad_config;
         }
 
         if (factory_config.version != FACTORY_CONFIG_VERSION) {
                 pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
                                 factory_config.version);
-                return;
+                goto bad_config;
         }
 
         pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
-        pr_info("MityOMAPL138: Part Number = %s\n", factory_config.partnum);
         if (is_valid_ether_addr(factory_config.mac))
                 memcpy(soc_info->emac_pdata->mac_addr,
                         factory_config.mac, ETH_ALEN);
         else
                 pr_warning("MityOMAPL138: Invalid MAC found "
                                 "in factory config block\n");
+
+        partnum = factory_config.partnum;
+        pr_info("MityOMAPL138: Part Number = %s\n", partnum);
+
+bad_config:
+        /* default maximum speed is valid for all platforms */
+        mityomapl138_cpufreq_init(partnum);
 }
 
 static struct at24_platform_data mityomapl138_fd_chip = {
@@ -223,6 +297,82 @@ static int __init pmic_tps65023_init(void)
 }
 
 /*
+ * SPI Devices:
+ *      SPI1_CS0: 8M Flash ST-M25P64-VME6G
+ */
+static struct mtd_partition spi_flash_partitions[] = {
+        [0] = {
+                .name           = "ubl",
+                .offset         = 0,
+                .size           = SZ_64K,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        [1] = {
+                .name           = "u-boot",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_512K,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        [2] = {
+                .name           = "u-boot-env",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_64K,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        [3] = {
+                .name           = "periph-config",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_64K,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        [4] = {
+                .name           = "reserved",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_256K + SZ_64K,
+        },
+        [5] = {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_2M + SZ_1M,
+        },
+        [6] = {
+                .name           = "fpga",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_2M,
+        },
+        [7] = {
+                .name           = "spare",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct flash_platform_data mityomapl138_spi_flash_data = {
+        .name           = "m25p80",
+        .parts          = spi_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(spi_flash_partitions),
+        .type           = "m24p64",
+};
+
+static struct davinci_spi_config spi_eprom_config = {
+        .io_type        = SPI_IO_TYPE_DMA,
+        .c2tdelay       = 8,
+        .t2cdelay       = 8,
+};
+
+static struct spi_board_info mityomapl138_spi_flash_info[] = {
+        {
+                .modalias               = "m25p80",
+                .platform_data          = &mityomapl138_spi_flash_data,
+                .controller_data        = &spi_eprom_config,
+                .mode                   = SPI_MODE_0,
+                .max_speed_hz           = 30000000,
+                .bus_num                = 1,
+                .chip_select            = 0,
+        },
+};
+
+/*
  * MityDSP-L138 includes a 256 MByte large-page NAND flash
  * (128K blocks).
  */
@@ -377,16 +527,17 @@ static void __init mityomapl138_init(void)
 
         mityomapl138_setup_nand();
 
+        ret = da8xx_register_spi(1, mityomapl138_spi_flash_info,
+                               ARRAY_SIZE(mityomapl138_spi_flash_info));
+        if (ret)
+                pr_warning("spi 1 registration failed: %d\n", ret);
+
         mityomapl138_config_emac();
 
         ret = da8xx_register_rtc();
         if (ret)
                 pr_warning("rtc setup failed: %d\n", ret);
 
-        ret = da850_register_cpufreq("pll0_sysclk3");
-        if (ret)
-                pr_warning("cpufreq registration failed: %d\n", ret);
-
         ret = da8xx_register_cpuidle();
         if (ret)
                 pr_warning("cpuidle registration failed: %d\n", ret);
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 0b8dbdb79fe0..67c38d0ecd10 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -19,6 +19,279 @@
 
 #include <mach/cp_intc.h>
 #include <mach/da8xx.h>
+#include <mach/mux.h>
+
+#define HAWKBOARD_PHY_ID                "0:07"
+#define DA850_HAWK_MMCSD_CD_PIN         GPIO_TO_PIN(3, 12)
+#define DA850_HAWK_MMCSD_WP_PIN         GPIO_TO_PIN(3, 13)
+
+#define DA850_USB1_VBUS_PIN             GPIO_TO_PIN(2, 4)
+#define DA850_USB1_OC_PIN               GPIO_TO_PIN(6, 13)
+
+static short omapl138_hawk_mii_pins[] __initdata = {
+        DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
+        DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
+        DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
+        DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
+        DA850_MDIO_D,
+        -1
+};
+
+static __init void omapl138_hawk_config_emac(void)
+{
+        void __iomem *cfgchip3 = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
+        int ret;
+        u32 val;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+
+        val = __raw_readl(cfgchip3);
+        val &= ~BIT(8);
+        ret = davinci_cfg_reg_list(omapl138_hawk_mii_pins);
+        if (ret) {
+                pr_warning("%s: cpgmac/mii mux setup failed: %d\n",
+                        __func__, ret);
+                return;
+        }
+
+        /* configure the CFGCHIP3 register for MII */
+        __raw_writel(val, cfgchip3);
+        pr_info("EMAC: MII PHY configured\n");
+
+        soc_info->emac_pdata->phy_id = HAWKBOARD_PHY_ID;
+
+        ret = da8xx_register_emac();
+        if (ret)
+                pr_warning("%s: emac registration failed: %d\n",
+                        __func__, ret);
+}
+
+/*
+ * The following EDMA channels/slots are not being used by drivers (for
+ * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM/Hawkboard,
+ * hence they are being reserved for codecs on the DSP side.
+ */
+static const s16 da850_dma0_rsv_chans[][2] = {
+        /* (offset, number) */
+        { 8,  6},
+        {24,  4},
+        {30,  2},
+        {-1, -1}
+};
+
+static const s16 da850_dma0_rsv_slots[][2] = {
+        /* (offset, number) */
+        { 8,  6},
+        {24,  4},
+        {30, 50},
+        {-1, -1}
+};
+
+static const s16 da850_dma1_rsv_chans[][2] = {
+        /* (offset, number) */
+        { 0, 28},
+        {30,  2},
+        {-1, -1}
+};
+
+static const s16 da850_dma1_rsv_slots[][2] = {
+        /* (offset, number) */
+        { 0, 28},
+        {30, 90},
+        {-1, -1}
+};
+
+static struct edma_rsv_info da850_edma_cc0_rsv = {
+        .rsv_chans      = da850_dma0_rsv_chans,
+        .rsv_slots      = da850_dma0_rsv_slots,
+};
+
+static struct edma_rsv_info da850_edma_cc1_rsv = {
+        .rsv_chans      = da850_dma1_rsv_chans,
+        .rsv_slots      = da850_dma1_rsv_slots,
+};
+
+static struct edma_rsv_info *da850_edma_rsv[2] = {
+        &da850_edma_cc0_rsv,
+        &da850_edma_cc1_rsv,
+};
+
+static const short hawk_mmcsd0_pins[] = {
+        DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
+        DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
+        DA850_GPIO3_12, DA850_GPIO3_13,
+        -1
+};
+
+static int da850_hawk_mmc_get_ro(int index)
+{
+        return gpio_get_value(DA850_HAWK_MMCSD_WP_PIN);
+}
+
+static int da850_hawk_mmc_get_cd(int index)
+{
+        return !gpio_get_value(DA850_HAWK_MMCSD_CD_PIN);
+}
+
+static struct davinci_mmc_config da850_mmc_config = {
+        .get_ro         = da850_hawk_mmc_get_ro,
+        .get_cd         = da850_hawk_mmc_get_cd,
+        .wires          = 4,
+        .max_freq       = 50000000,
+        .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
+        .version        = MMC_CTLR_VERSION_2,
+};
+
+static __init void omapl138_hawk_mmc_init(void)
+{
+        int ret;
+
+        ret = davinci_cfg_reg_list(hawk_mmcsd0_pins);
+        if (ret) {
+                pr_warning("%s: MMC/SD0 mux setup failed: %d\n",
+                        __func__, ret);
+                return;
+        }
+
+        ret = gpio_request_one(DA850_HAWK_MMCSD_CD_PIN,
+                        GPIOF_DIR_IN, "MMC CD");
+        if (ret < 0) {
+                pr_warning("%s: can not open GPIO %d\n",
+                        __func__, DA850_HAWK_MMCSD_CD_PIN);
+                return;
+        }
+
+        ret = gpio_request_one(DA850_HAWK_MMCSD_WP_PIN,
+                        GPIOF_DIR_IN, "MMC WP");
+        if (ret < 0) {
+                pr_warning("%s: can not open GPIO %d\n",
+                        __func__, DA850_HAWK_MMCSD_WP_PIN);
+                goto mmc_setup_wp_fail;
+        }
+
+        ret = da8xx_register_mmcsd0(&da850_mmc_config);
+        if (ret) {
+                pr_warning("%s: MMC/SD0 registration failed: %d\n",
+                        __func__, ret);
+                goto mmc_setup_mmcsd_fail;
+        }
+
+        return;
+
+mmc_setup_mmcsd_fail:
+        gpio_free(DA850_HAWK_MMCSD_WP_PIN);
+mmc_setup_wp_fail:
+        gpio_free(DA850_HAWK_MMCSD_CD_PIN);
+}
+
+static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id);
+static da8xx_ocic_handler_t hawk_usb_ocic_handler;
+
+static const short da850_hawk_usb11_pins[] = {
+        DA850_GPIO2_4, DA850_GPIO6_13,
+        -1
+};
+
+static int hawk_usb_set_power(unsigned port, int on)
+{
+        gpio_set_value(DA850_USB1_VBUS_PIN, on);
+        return 0;
+}
+
+static int hawk_usb_get_power(unsigned port)
+{
+        return gpio_get_value(DA850_USB1_VBUS_PIN);
+}
+
+static int hawk_usb_get_oci(unsigned port)
+{
+        return !gpio_get_value(DA850_USB1_OC_PIN);
+}
+
+static int hawk_usb_ocic_notify(da8xx_ocic_handler_t handler)
+{
+        int irq         = gpio_to_irq(DA850_USB1_OC_PIN);
+        int error       = 0;
+
+        if (handler != NULL) {
+                hawk_usb_ocic_handler = handler;
+
+                error = request_irq(irq, omapl138_hawk_usb_ocic_irq,
+                                        IRQF_DISABLED | IRQF_TRIGGER_RISING |
+                                        IRQF_TRIGGER_FALLING,
+                                        "OHCI over-current indicator", NULL);
+                if (error)
+                        pr_err("%s: could not request IRQ to watch "
+                                "over-current indicator changes\n", __func__);
+        } else {
+                free_irq(irq, NULL);
+        }
+        return error;
+}
+
+static struct da8xx_ohci_root_hub omapl138_hawk_usb11_pdata = {
+        .set_power      = hawk_usb_set_power,
+        .get_power      = hawk_usb_get_power,
+        .get_oci        = hawk_usb_get_oci,
+        .ocic_notify    = hawk_usb_ocic_notify,
+        /* TPS2087 switch @ 5V */
+        .potpgt         = (3 + 1) / 2,  /* 3 ms max */
+};
+
+static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id)
+{
+        hawk_usb_ocic_handler(&omapl138_hawk_usb11_pdata, 1);
+        return IRQ_HANDLED;
+}
+
+static __init void omapl138_hawk_usb_init(void)
+{
+        int ret;
+        u32 cfgchip2;
+
+        ret = davinci_cfg_reg_list(da850_hawk_usb11_pins);
+        if (ret) {
+                pr_warning("%s: USB 1.1 PinMux setup failed: %d\n",
+                        __func__, ret);
+                return;
+        }
+
+        /* Setup the Ref. clock frequency for the HAWK at 24 MHz. */
+
+        cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
+        cfgchip2 &= ~CFGCHIP2_REFFREQ;
+        cfgchip2 |=  CFGCHIP2_REFFREQ_24MHZ;
+        __raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
+
+        ret = gpio_request_one(DA850_USB1_VBUS_PIN,
+                        GPIOF_DIR_OUT, "USB1 VBUS");
+        if (ret < 0) {
+                pr_err("%s: failed to request GPIO for USB 1.1 port "
+                        "power control: %d\n", __func__, ret);
+                return;
+        }
+
+        ret = gpio_request_one(DA850_USB1_OC_PIN,
+                        GPIOF_DIR_IN, "USB1 OC");
+        if (ret < 0) {
+                pr_err("%s: failed to request GPIO for USB 1.1 port "
+                        "over-current indicator: %d\n", __func__, ret);
+                goto usb11_setup_oc_fail;
+        }
+
+        ret = da8xx_register_usb11(&omapl138_hawk_usb11_pdata);
+        if (ret) {
+                pr_warning("%s: USB 1.1 registration failed: %d\n",
+                        __func__, ret);
+                goto usb11_setup_fail;
+        }
+
+        return;
+
+usb11_setup_fail:
+        gpio_free(DA850_USB1_OC_PIN);
+usb11_setup_oc_fail:
+        gpio_free(DA850_USB1_VBUS_PIN);
+}
 
 static struct davinci_uart_config omapl138_hawk_uart_config __initdata = {
         .enabled_uarts = 0x7,
@@ -30,6 +303,17 @@ static __init void omapl138_hawk_init(void)
 
         davinci_serial_init(&omapl138_hawk_uart_config);
 
+        omapl138_hawk_config_emac();
+
+        ret = da850_register_edma(da850_edma_rsv);
+        if (ret)
+                pr_warning("%s: EDMA registration failed: %d\n",
+                        __func__, ret);
+
+        omapl138_hawk_mmc_init();
+
+        omapl138_hawk_usb_init();
+
         ret = da8xx_register_watchdog();
         if (ret)
                 pr_warning("omapl138_hawk_init: "
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index a6db85460227..1a656e882262 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -25,6 +25,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/input.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/spi/spi.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -37,6 +38,7 @@
 
 #define EVM_MMC_WP_GPIO         21
 #define EVM_MMC_CD_GPIO         24
+#define EVM_SPI_CS_GPIO         54
 
 static int initialize_gpio(int gpio, char *desc)
 {
@@ -99,6 +101,12 @@ static const short uart1_pins[] __initdata = {
         -1
 };
 
+static const short ssp_pins[] __initdata = {
+        TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2,
+        TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2,
+        TNETV107X_SSP1_3, -1
+};
+
 static struct mtd_partition nand_partitions[] = {
         /* bootloader (U-Boot, etc) in first 12 sectors */
         {
@@ -196,19 +204,68 @@ static struct matrix_keypad_platform_data keypad_config = {
         .no_autorepeat  = 0,
 };
 
+static void spi_select_device(int cs)
+{
+        static int gpio;
+
+        if (!gpio) {
+                int ret;
+                ret = gpio_request(EVM_SPI_CS_GPIO, "spi chipsel");
+                if (ret < 0) {
+                        pr_err("cannot open spi chipsel gpio\n");
+                        gpio = -ENOSYS;
+                        return;
+                } else {
+                        gpio = EVM_SPI_CS_GPIO;
+                        gpio_direction_output(gpio, 0);
+                }
+        }
+
+        if (gpio < 0)
+                return;
+
+        return gpio_set_value(gpio, cs ? 1 : 0);
+}
+
+static struct ti_ssp_spi_data spi_master_data = {
+        .num_cs = 2,
+        .select = spi_select_device,
+        .iosel  = SSP_PIN_SEL(0, SSP_CLOCK)     | SSP_PIN_SEL(1, SSP_DATA) |
+                  SSP_PIN_SEL(2, SSP_CHIPSEL)   | SSP_PIN_SEL(3, SSP_IN)   |
+                  SSP_INPUT_SEL(3),
+};
+
+static struct ti_ssp_data ssp_config = {
+        .out_clock      = 250 * 1000,
+        .dev_data       = {
+                [1] = {
+                        .dev_name = "ti-ssp-spi",
+                        .pdata = &spi_master_data,
+                        .pdata_size = sizeof(spi_master_data),
+                },
+        },
+};
+
 static struct tnetv107x_device_info evm_device_info __initconst = {
         .serial_config          = &serial_config,
         .mmc_config[1]          = &mmc_config,  /* controller 1 */
         .nand_config[0]         = &nand_config, /* chip select 0 */
         .keypad_config          = &keypad_config,
+        .ssp_config             = &ssp_config,
+};
+
+static struct spi_board_info spi_info[] __initconst = {
 };
 
 static __init void tnetv107x_evm_board_init(void)
 {
         davinci_cfg_reg_list(sdio1_pins);
         davinci_cfg_reg_list(uart1_pins);
+        davinci_cfg_reg_list(ssp_pins);
 
         tnetv107x_devices_init(&evm_device_info);
+
+        spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
 }
 
 #ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index ec23ab473620..2ed2f822fc40 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -148,7 +148,7 @@ static struct clk scr2_ss_clk = {
 static struct clk dmax_clk = {
         .name           = "dmax",
         .parent         = &pll0_sysclk2,
-        .lpsc           = DA8XX_LPSC0_DMAX,
+        .lpsc           = DA8XX_LPSC0_PRUSS,
         .flags          = ALWAYS_ENABLED,
 };
 
@@ -397,8 +397,8 @@ static struct clk_lookup da830_clks[] = {
         CLK(NULL,               "uart0",        &uart0_clk),
         CLK(NULL,               "uart1",        &uart1_clk),
         CLK(NULL,               "uart2",        &uart2_clk),
-        CLK("dm_spi.0",         NULL,           &spi0_clk),
-        CLK("dm_spi.1",         NULL,           &spi1_clk),
+        CLK("spi_davinci.0",    NULL,           &spi0_clk),
+        CLK("spi_davinci.1",    NULL,           &spi1_clk),
         CLK(NULL,               "ecap0",        &ecap0_clk),
         CLK(NULL,               "ecap1",        &ecap1_clk),
         CLK(NULL,               "ecap2",        &ecap2_clk),
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 78b5ae29ae40..68fe4c289d77 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -345,6 +345,34 @@ static struct clk aemif_clk = {
         .flags          = ALWAYS_ENABLED,
 };
 
+static struct clk usb11_clk = {
+        .name           = "usb11",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC1_USB11,
+        .gpsc           = 1,
+};
+
+static struct clk usb20_clk = {
+        .name           = "usb20",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_USB20,
+        .gpsc           = 1,
+};
+
+static struct clk spi0_clk = {
+        .name           = "spi0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_SPI0,
+};
+
+static struct clk spi1_clk = {
+        .name           = "spi1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_SPI1,
+        .gpsc           = 1,
+        .flags          = DA850_CLK_ASYNC3,
+};
+
 static struct clk_lookup da850_clks[] = {
         CLK(NULL,               "ref",          &ref_clk),
         CLK(NULL,               "pll0",         &pll0_clk),
@@ -387,6 +415,10 @@ static struct clk_lookup da850_clks[] = {
         CLK("davinci_mmc.0",    NULL,           &mmcsd0_clk),
         CLK("davinci_mmc.1",    NULL,           &mmcsd1_clk),
         CLK(NULL,               "aemif",        &aemif_clk),
+        CLK(NULL,               "usb11",        &usb11_clk),
+        CLK(NULL,               "usb20",        &usb20_clk),
+        CLK("spi_davinci.0",    NULL,           &spi0_clk),
+        CLK("spi_davinci.1",    NULL,           &spi1_clk),
         CLK(NULL,               NULL,           NULL),
 };
 
@@ -543,30 +575,19 @@ static const struct mux_config da850_pins[] = {
         MUX_CFG(DA850, EMA_WAIT_1,      6,      24,     15,     1,      false)
         MUX_CFG(DA850, NEMA_CS_2,       7,      0,      15,     1,      false)
         /* GPIO function */
+        MUX_CFG(DA850, GPIO2_4,         6,      12,     15,     8,      false)
         MUX_CFG(DA850, GPIO2_6,         6,      4,      15,     8,      false)
         MUX_CFG(DA850, GPIO2_8,         5,      28,     15,     8,      false)
         MUX_CFG(DA850, GPIO2_15,        5,      0,      15,     8,      false)
+        MUX_CFG(DA850, GPIO3_12,        7,      12,     15,     8,      false)
+        MUX_CFG(DA850, GPIO3_13,        7,      8,      15,     8,      false)
         MUX_CFG(DA850, GPIO4_0,         10,     28,     15,     8,      false)
         MUX_CFG(DA850, GPIO4_1,         10,     24,     15,     8,      false)
+        MUX_CFG(DA850, GPIO6_13,        13,     8,      15,     8,      false)
         MUX_CFG(DA850, RTC_ALARM,       0,      28,     15,     2,      false)
 #endif
 };
 
-const short da850_uart0_pins[] __initdata = {
-        DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
-        -1
-};
-
-const short da850_uart1_pins[] __initdata = {
-        DA850_UART1_RXD, DA850_UART1_TXD,
-        -1
-};
-
-const short da850_uart2_pins[] __initdata = {
-        DA850_UART2_RXD, DA850_UART2_TXD,
-        -1
-};
-
 const short da850_i2c0_pins[] __initdata = {
         DA850_I2C0_SDA, DA850_I2C0_SCL,
         -1
@@ -577,24 +598,6 @@ const short da850_i2c1_pins[] __initdata = {
         -1
 };
 
-const short da850_cpgmac_pins[] __initdata = {
-        DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
-        DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
-        DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
-        DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
-        DA850_MDIO_D, DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
-        DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, DA850_RMII_RXER,
-        DA850_RMII_MHZ_50_CLK,
-        -1
-};
-
-const short da850_mcasp_pins[] __initdata = {
-        DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
-        DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
-        DA850_AXR_11, DA850_AXR_12,
-        -1
-};
-
 const short da850_lcdcntl_pins[] __initdata = {
         DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
         DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
@@ -604,29 +607,6 @@ const short da850_lcdcntl_pins[] __initdata = {
         -1
 };
 
-const short da850_mmcsd0_pins[] __initdata = {
-        DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
-        DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
-        DA850_GPIO4_0, DA850_GPIO4_1,
-        -1
-};
-
-const short da850_emif25_pins[] __initdata = {
-        DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
-        DA850_NEMA_CS_3, DA850_NEMA_CS_4, DA850_NEMA_WE, DA850_NEMA_OE,
-        DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
-        DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
-        DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11,
-        DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15,
-        DA850_EMA_A_0, DA850_EMA_A_1, DA850_EMA_A_2, DA850_EMA_A_3,
-        DA850_EMA_A_4, DA850_EMA_A_5, DA850_EMA_A_6, DA850_EMA_A_7,
-        DA850_EMA_A_8, DA850_EMA_A_9, DA850_EMA_A_10, DA850_EMA_A_11,
-        DA850_EMA_A_12, DA850_EMA_A_13, DA850_EMA_A_14, DA850_EMA_A_15,
-        DA850_EMA_A_16, DA850_EMA_A_17, DA850_EMA_A_18, DA850_EMA_A_19,
-        DA850_EMA_A_20, DA850_EMA_A_21, DA850_EMA_A_22, DA850_EMA_A_23,
-        -1
-};
-
 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
         [IRQ_DA8XX_COMMTX]              = 7,
@@ -764,6 +744,13 @@ static struct davinci_id da850_ids[] = {
                 .cpu_id         = DAVINCI_CPU_ID_DA850,
                 .name           = "da850/omap-l138",
         },
+        {
+                .variant        = 0x1,
+                .part_no        = 0xb7d1,
+                .manufacturer   = 0x017,        /* 0x02f >> 1 */
+                .cpu_id         = DAVINCI_CPU_ID_DA850,
+                .name           = "da850/omap-l138/am18x",
+        },
 };
 
 static struct davinci_timer_instance da850_timer_instance[4] = {
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index beda8a4133a0..625d4b66718b 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -38,12 +38,23 @@
 #define DA8XX_EMAC_MDIO_BASE            0x01e24000
 #define DA8XX_GPIO_BASE                 0x01e26000
 #define DA8XX_I2C1_BASE                 0x01e28000
+#define DA8XX_SPI0_BASE                 0x01c41000
+#define DA8XX_SPI1_BASE                 0x01f0e000
 
 #define DA8XX_EMAC_CTRL_REG_OFFSET      0x3000
 #define DA8XX_EMAC_MOD_REG_OFFSET       0x2000
 #define DA8XX_EMAC_RAM_OFFSET           0x0000
 #define DA8XX_EMAC_CTRL_RAM_SIZE        SZ_8K
 
+#define DA8XX_DMA_SPI0_RX       EDMA_CTLR_CHAN(0, 14)
+#define DA8XX_DMA_SPI0_TX       EDMA_CTLR_CHAN(0, 15)
+#define DA8XX_DMA_MMCSD0_RX     EDMA_CTLR_CHAN(0, 16)
+#define DA8XX_DMA_MMCSD0_TX     EDMA_CTLR_CHAN(0, 17)
+#define DA8XX_DMA_SPI1_RX       EDMA_CTLR_CHAN(0, 18)
+#define DA8XX_DMA_SPI1_TX       EDMA_CTLR_CHAN(0, 19)
+#define DA850_DMA_MMCSD1_RX     EDMA_CTLR_CHAN(1, 28)
+#define DA850_DMA_MMCSD1_TX     EDMA_CTLR_CHAN(1, 29)
+
 void __iomem *da8xx_syscfg0_base;
 void __iomem *da8xx_syscfg1_base;
 
@@ -573,13 +584,13 @@ static struct resource da8xx_mmcsd0_resources[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         {               /* DMA RX */
-                .start  = EDMA_CTLR_CHAN(0, 16),
-                .end    = EDMA_CTLR_CHAN(0, 16),
+                .start  = DA8XX_DMA_MMCSD0_RX,
+                .end    = DA8XX_DMA_MMCSD0_RX,
                 .flags  = IORESOURCE_DMA,
         },
         {               /* DMA TX */
-                .start  = EDMA_CTLR_CHAN(0, 17),
-                .end    = EDMA_CTLR_CHAN(0, 17),
+                .start  = DA8XX_DMA_MMCSD0_TX,
+                .end    = DA8XX_DMA_MMCSD0_TX,
                 .flags  = IORESOURCE_DMA,
         },
 };
@@ -610,13 +621,13 @@ static struct resource da850_mmcsd1_resources[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         {               /* DMA RX */
-                .start  = EDMA_CTLR_CHAN(1, 28),
-                .end    = EDMA_CTLR_CHAN(1, 28),
+                .start  = DA850_DMA_MMCSD1_RX,
+                .end    = DA850_DMA_MMCSD1_RX,
                 .flags  = IORESOURCE_DMA,
         },
         {               /* DMA TX */
-                .start  = EDMA_CTLR_CHAN(1, 29),
-                .end    = EDMA_CTLR_CHAN(1, 29),
+                .start  = DA850_DMA_MMCSD1_TX,
+                .end    = DA850_DMA_MMCSD1_TX,
                 .flags  = IORESOURCE_DMA,
         },
 };
@@ -725,3 +736,101 @@ int __init da8xx_register_cpuidle(void)
 
         return platform_device_register(&da8xx_cpuidle_device);
 }
+
+static struct resource da8xx_spi0_resources[] = {
+        [0] = {
+                .start  = DA8XX_SPI0_BASE,
+                .end    = DA8XX_SPI0_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_DA8XX_SPINT0,
+                .end    = IRQ_DA8XX_SPINT0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = DA8XX_DMA_SPI0_RX,
+                .end    = DA8XX_DMA_SPI0_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = DA8XX_DMA_SPI0_TX,
+                .end    = DA8XX_DMA_SPI0_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct resource da8xx_spi1_resources[] = {
+        [0] = {
+                .start  = DA8XX_SPI1_BASE,
+                .end    = DA8XX_SPI1_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_DA8XX_SPINT1,
+                .end    = IRQ_DA8XX_SPINT1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = DA8XX_DMA_SPI1_RX,
+                .end    = DA8XX_DMA_SPI1_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = DA8XX_DMA_SPI1_TX,
+                .end    = DA8XX_DMA_SPI1_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+struct davinci_spi_platform_data da8xx_spi_pdata[] = {
+        [0] = {
+                .version        = SPI_VERSION_2,
+                .intr_line      = 1,
+                .dma_event_q    = EVENTQ_0,
+        },
+        [1] = {
+                .version        = SPI_VERSION_2,
+                .intr_line      = 1,
+                .dma_event_q    = EVENTQ_0,
+        },
+};
+
+static struct platform_device da8xx_spi_device[] = {
+        [0] = {
+                .name           = "spi_davinci",
+                .id             = 0,
+                .num_resources  = ARRAY_SIZE(da8xx_spi0_resources),
+                .resource       = da8xx_spi0_resources,
+                .dev            = {
+                        .platform_data = &da8xx_spi_pdata[0],
+                },
+        },
+        [1] = {
+                .name           = "spi_davinci",
+                .id             = 1,
+                .num_resources  = ARRAY_SIZE(da8xx_spi1_resources),
+                .resource       = da8xx_spi1_resources,
+                .dev            = {
+                        .platform_data = &da8xx_spi_pdata[1],
+                },
+        },
+};
+
+int __init da8xx_register_spi(int instance, struct spi_board_info *info,
+                              unsigned len)
+{
+        int ret;
+
+        if (instance < 0 || instance > 1)
+                return -EINVAL;
+
+        ret = spi_register_board_info(info, len);
+        if (ret)
+                pr_warning("%s: failed to register board info for spi %d :"
+                           " %d\n", __func__, instance, ret);
+
+        da8xx_spi_pdata[instance].num_chipselect = len;
+
+        return platform_device_register(&da8xx_spi_device[instance]);
+}
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 85503debda51..6162cae7f868 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -35,6 +35,7 @@
 #define TNETV107X_SDIO0_BASE                    0x08088700
 #define TNETV107X_SDIO1_BASE                    0x08088800
 #define TNETV107X_KEYPAD_BASE                   0x08088a00
+#define TNETV107X_SSP_BASE                      0x08088c00
 #define TNETV107X_ASYNC_EMIF_CNTRL_BASE         0x08200000
 #define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE      0x30000000
 #define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE      0x40000000
@@ -342,6 +343,25 @@ static struct platform_device tsc_device = {
         .resource       = tsc_resources,
 };
 
+static struct resource ssp_resources[] = {
+        {
+                .start  = TNETV107X_SSP_BASE,
+                .end    = TNETV107X_SSP_BASE + 0x1ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_TNETV107X_SSP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device ssp_device = {
+        .name           = "ti-ssp",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(ssp_resources),
+        .resource       = ssp_resources,
+};
+
 void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
 {
         int i, error;
@@ -380,4 +400,9 @@ void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
                 keypad_device.dev.platform_data = info->keypad_config;
                 platform_device_register(&keypad_device);
         }
+
+        if (info->ssp_config) {
+                ssp_device.dev.platform_data = info->ssp_config;
+                platform_device_register(&ssp_device);
+        }
 }
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index a5f8a80c1f28..76364d1345df 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -403,16 +403,13 @@ static struct resource dm355_spi0_resources[] = {
                 .start = 16,
                 .flags = IORESOURCE_DMA,
         },
-        {
-                .start = EVENTQ_1,
-                .flags = IORESOURCE_DMA,
-        },
 };
 
 static struct davinci_spi_platform_data dm355_spi0_pdata = {
         .version        = SPI_VERSION_1,
         .num_chipselect = 2,
         .cshold_bug     = true,
+        .dma_event_q    = EVENTQ_1,
 };
 static struct platform_device dm355_spi0_device = {
         .name = "spi_davinci",
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 02d2cc380df7..4604e72d7d99 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -625,6 +625,7 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
 static struct davinci_spi_platform_data dm365_spi0_pdata = {
         .version        = SPI_VERSION_1,
         .num_chipselect = 2,
+        .dma_event_q    = EVENTQ_3,
 };
 
 static struct resource dm365_spi0_resources[] = {
@@ -645,10 +646,6 @@ static struct resource dm365_spi0_resources[] = {
                 .start = 16,
                 .flags = IORESOURCE_DMA,
         },
-        {
-                .start = EVENTQ_3,
-                .flags = IORESOURCE_DMA,
-        },
 };
 
 static struct platform_device dm365_spi0_device = {
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index e7f952066527..e4fc1af8500e 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -15,6 +15,7 @@
 
 #include <linux/platform_device.h>
 #include <linux/davinci_emac.h>
+#include <linux/spi/spi.h>
 
 #include <mach/serial.h>
 #include <mach/edma.h>
@@ -23,6 +24,7 @@
 #include <mach/mmc.h>
 #include <mach/usb.h>
 #include <mach/pm.h>
+#include <mach/spi.h>
 
 extern void __iomem *da8xx_syscfg0_base;
 extern void __iomem *da8xx_syscfg1_base;
@@ -77,6 +79,7 @@ void __init da850_init(void);
 int da830_register_edma(struct edma_rsv_info *rsv);
 int da850_register_edma(struct edma_rsv_info *rsv[2]);
 int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
+int da8xx_register_spi(int instance, struct spi_board_info *info, unsigned len);
 int da8xx_register_watchdog(void);
 int da8xx_register_usb20(unsigned mA, unsigned potpgt);
 int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
@@ -95,6 +98,7 @@ extern struct platform_device da8xx_serial_device;
 extern struct emac_platform_data da8xx_emac_pdata;
 extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
 extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
+extern struct davinci_spi_platform_data da8xx_spi_pdata[];
 
 extern struct platform_device da8xx_wdt_device;
 
@@ -123,15 +127,8 @@ extern const short da830_ecap2_pins[];
 extern const short da830_eqep0_pins[];
 extern const short da830_eqep1_pins[];
 
-extern const short da850_uart0_pins[];
-extern const short da850_uart1_pins[];
-extern const short da850_uart2_pins[];
 extern const short da850_i2c0_pins[];
 extern const short da850_i2c1_pins[];
-extern const short da850_cpgmac_pins[];
-extern const short da850_mcasp_pins[];
 extern const short da850_lcdcntl_pins[];
-extern const short da850_mmcsd0_pins[];
-extern const short da850_emif25_pins[];
 
 #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index dc10ef6cf572..20c77f29bf0f 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -151,42 +151,6 @@ struct edmacc_param {
 #define DA830_DMACH2EVENT_MAP1          0x00000000u
 #define DA830_EDMA_ARM_OWN              0x30FFCCFFu
 
-/* DA830 specific EDMA3 Events Information */
-enum DA830_edma_ch {
-        DA830_DMACH_MCASP0_RX,
-        DA830_DMACH_MCASP0_TX,
-        DA830_DMACH_MCASP1_RX,
-        DA830_DMACH_MCASP1_TX,
-        DA830_DMACH_MCASP2_RX,
-        DA830_DMACH_MCASP2_TX,
-        DA830_DMACH_GPIO_BNK0INT,
-        DA830_DMACH_GPIO_BNK1INT,
-        DA830_DMACH_UART0_RX,
-        DA830_DMACH_UART0_TX,
-        DA830_DMACH_TMR64P0_EVTOUT12,
-        DA830_DMACH_TMR64P0_EVTOUT34,
-        DA830_DMACH_UART1_RX,
-        DA830_DMACH_UART1_TX,
-        DA830_DMACH_SPI0_RX,
-        DA830_DMACH_SPI0_TX,
-        DA830_DMACH_MMCSD_RX,
-        DA830_DMACH_MMCSD_TX,
-        DA830_DMACH_SPI1_RX,
-        DA830_DMACH_SPI1_TX,
-        DA830_DMACH_DMAX_EVTOUT6,
-        DA830_DMACH_DMAX_EVTOUT7,
-        DA830_DMACH_GPIO_BNK2INT,
-        DA830_DMACH_GPIO_BNK3INT,
-        DA830_DMACH_I2C0_RX,
-        DA830_DMACH_I2C0_TX,
-        DA830_DMACH_I2C1_RX,
-        DA830_DMACH_I2C1_TX,
-        DA830_DMACH_GPIO_BNK4INT,
-        DA830_DMACH_GPIO_BNK5INT,
-        DA830_DMACH_UART2_RX,
-        DA830_DMACH_UART2_TX
-};
-
 /*ch_status paramater of callback function possible values*/
 #define DMA_COMPLETE 1
 #define DMA_CC_ERROR 2
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index de11aac76a80..5d4e0fed828a 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -908,11 +908,15 @@ enum davinci_da850_index {
         DA850_NEMA_CS_2,
 
         /* GPIO function */
+        DA850_GPIO2_4,
         DA850_GPIO2_6,
         DA850_GPIO2_8,
         DA850_GPIO2_15,
+        DA850_GPIO3_12,
+        DA850_GPIO3_13,
         DA850_GPIO4_0,
         DA850_GPIO4_1,
+        DA850_GPIO6_13,
         DA850_RTC_ALARM,
 };
 
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 62b0858f68ca..a47e6f29206e 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -150,7 +150,7 @@
 #define DA8XX_LPSC0_SCR0_SS             10
 #define DA8XX_LPSC0_SCR1_SS             11
 #define DA8XX_LPSC0_SCR2_SS             12
-#define DA8XX_LPSC0_DMAX                13
+#define DA8XX_LPSC0_PRUSS               13
 #define DA8XX_LPSC0_ARM                 14
 #define DA8XX_LPSC0_GEM                 15
 
diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h
index 38f4da5ca135..7af305b37868 100644
--- a/arch/arm/mach-davinci/include/mach/spi.h
+++ b/arch/arm/mach-davinci/include/mach/spi.h
@@ -19,6 +19,8 @@
 #ifndef __ARCH_ARM_DAVINCI_SPI_H
 #define __ARCH_ARM_DAVINCI_SPI_H
 
+#include <mach/edma.h>
+
 #define SPI_INTERN_CS   0xFF
 
 enum {
@@ -39,13 +41,16 @@ enum {
  *              to populate if all chip-selects are internal.
  * @cshold_bug: set this to true if the SPI controller on your chip requires
  *              a write to CSHOLD bit in between transfers (like in DM355).
+ * @dma_event_q: DMA event queue to use if SPI_IO_TYPE_DMA is used for any
+ *              device on the bus.
  */
 struct davinci_spi_platform_data {
-        u8      version;
-        u8      num_chipselect;
-        u8      intr_line;
-        u8      *chip_sel;
-        bool    cshold_bug;
+        u8                      version;
+        u8                      num_chipselect;
+        u8                      intr_line;
+        u8                      *chip_sel;
+        bool                    cshold_bug;
+        enum dma_event_q        dma_event_q;
 };
 
 /**
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 5a681d880dcb..89c1fdc63c0b 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -34,6 +34,7 @@
 
 #include <linux/serial_8250.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/mfd/ti_ssp.h>
 
 #include <mach/mmc.h>
 #include <mach/nand.h>
@@ -44,6 +45,7 @@ struct tnetv107x_device_info {
         struct davinci_mmc_config       *mmc_config[2];  /* 2 controllers */
         struct davinci_nand_pdata       *nand_config[4]; /* 4 chipsels */
         struct matrix_keypad_platform_data *keypad_config;
+        struct ti_ssp_data              *ssp_config;
 };
 
 extern struct platform_device tnetv107x_wdt_device;
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index 6fcdecec8d8c..1b28fdd892a6 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -278,7 +278,7 @@ static struct clk_lookup clks[] = {
         CLK(NULL,               "timer1",               &clk_timer1),
         CLK("tnetv107x_wdt.0",  NULL,                   &clk_wdt_arm),
         CLK(NULL,               "clk_wdt_dsp",          &clk_wdt_dsp),
-        CLK("ti-ssp.0",         NULL,                   &clk_ssp),
+        CLK("ti-ssp",           NULL,                   &clk_ssp),
         CLK(NULL,               "clk_tdm0",             &clk_tdm0),
         CLK(NULL,               "clk_vlynq",            &clk_vlynq),
         CLK(NULL,               "clk_mcdma",            &clk_mcdma),
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
index 96e0e94e5fa9..03e11f9dca97 100644
--- a/arch/arm/mach-dove/cm-a510.c
+++ b/arch/arm/mach-dove/cm-a510.c
@@ -90,6 +90,7 @@ MACHINE_START(CM_A510, "Compulab CM-A510 Board")
         .boot_params    = 0x00000100,
         .init_machine   = cm_a510_init,
         .map_io         = dove_map_io,
+        .init_early     = dove_init_early,
         .init_irq       = dove_init_irq,
         .timer          = &dove_timer,
 MACHINE_END
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index fe627aba6da7..e06a88f1f81d 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -532,6 +532,11 @@ void __init dove_i2c_init(void)
 /*****************************************************************************
  * Time handling
  ****************************************************************************/
+void __init dove_init_early(void)
+{
+        orion_time_set_base(TIMER_VIRT_BASE);
+}
+
 static int get_tclk(void)
 {
         /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
@@ -540,7 +545,8 @@ static int get_tclk(void)
 
 static void dove_timer_init(void)
 {
-        orion_time_init(IRQ_DOVE_BRIDGE, get_tclk());
+        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+                        IRQ_DOVE_BRIDGE, get_tclk());
 }
 
 struct sys_timer dove_timer = {
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index a51517c3fe76..6a2046e44706 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -22,6 +22,7 @@ extern struct mbus_dram_target_info dove_mbus_dram_info;
  */
 void dove_map_io(void);
 void dove_init(void);
+void dove_init_early(void);
 void dove_init_irq(void);
 void dove_setup_cpu_mbus(void);
 void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index 95925aa76dd9..2ac34ecfa745 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -97,6 +97,7 @@ MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
         .boot_params    = 0x00000100,
         .init_machine   = dove_db_init,
         .map_io         = dove_map_io,
+        .init_early     = dove_init_early,
         .init_irq       = dove_init_irq,
         .timer          = &dove_timer,
 MACHINE_END
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
index 214a4c31f069..226949dc4ac0 100644
--- a/arch/arm/mach-dove/include/mach/bridge-regs.h
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -26,10 +26,6 @@
 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
 #define  SOFT_RESET             0x00000001
 
-#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
-#define BRIDGE_MASK             (BRIDGE_VIRT_BASE | 0x0114)
-#define  BRIDGE_INT_TIMER0      0x0002
-#define  BRIDGE_INT_TIMER1      0x0004
 #define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
 
 #define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index 27b414578f2e..e5fcdd3f5bf5 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -130,7 +130,8 @@
 #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
 #define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE | 0x014)
 #define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE | 0x018)
-#define DOVE_GPIO_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_GPIO_LO_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_GPIO_HI_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE | 0xd0420)
 #define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
 #define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
 #define  DOVE_AU1_SPDIFO_GPIO_EN        (1 << 1)
diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h
index 340bb7af529d..e7e5101e35a5 100644
--- a/arch/arm/mach-dove/include/mach/gpio.h
+++ b/arch/arm/mach-dove/include/mach/gpio.h
@@ -6,46 +6,4 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#include <asm/errno.h>
-#include <mach/irqs.h>
 #include <plat/gpio.h>
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-
-#define GPIO_MAX        72
-
-#define GPIO_BASE_LO            (DOVE_GPIO_VIRT_BASE + 0x00)
-#define GPIO_BASE_HI            (DOVE_GPIO_VIRT_BASE + 0x20)
-
-#define GPIO_BASE(pin)          ((pin < 32) ? GPIO_BASE_LO :            \
-                                 ((pin < 64) ? GPIO_BASE_HI :           \
-                                  DOVE_GPIO2_VIRT_BASE))
-
-#define GPIO_OUT(pin)           (GPIO_BASE(pin) + 0x00)
-#define GPIO_IO_CONF(pin)       (GPIO_BASE(pin) + 0x04)
-#define GPIO_BLINK_EN(pin)      (GPIO_BASE(pin) + 0x08)
-#define GPIO_IN_POL(pin)        (GPIO_BASE(pin) + 0x0c)
-#define GPIO_DATA_IN(pin)       (GPIO_BASE(pin) + 0x10)
-#define GPIO_EDGE_CAUSE(pin)    (GPIO_BASE(pin) + 0x14)
-#define GPIO_EDGE_MASK(pin)     (GPIO_BASE(pin) + 0x18)
-#define GPIO_LEVEL_MASK(pin)    (GPIO_BASE(pin) + 0x1c)
-
-static inline int gpio_to_irq(int pin)
-{
-        if (pin < NR_GPIO_IRQS)
-                return pin + IRQ_DOVE_GPIO_START;
-
-        return -EINVAL;
-}
-
-static inline int irq_to_gpio(int irq)
-{
-        if (IRQ_DOVE_GPIO_START < irq && irq < NR_IRQS)
-                return irq - IRQ_DOVE_GPIO_START;
-
-        return -EINVAL;
-}
-
-#endif
diff --git a/arch/arm/mach-dove/include/mach/irqs.h b/arch/arm/mach-dove/include/mach/irqs.h
index 46681466f92b..03d401d20453 100644
--- a/arch/arm/mach-dove/include/mach/irqs.h
+++ b/arch/arm/mach-dove/include/mach/irqs.h
@@ -92,10 +92,5 @@
 
 #define NR_IRQS                 (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
 
-/* Required for compatability with PXA AC97 driver.     */
-#define IRQ_AC97                IRQ_DOVE_AC97
-/* Required for compatability with PXA DMA driver.      */
-#define IRQ_DMA                 IRQ_DOVE_PDMA
-/* Required for compatability with PXA NAND driver      */
-#define IRQ_NAND                IRQ_DOVE_NAND
+
 #endif
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 9317f0558b57..101707fa2e2c 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -99,11 +99,21 @@ void __init dove_init_irq(void)
         orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
 
         /*
-         * Mask and clear GPIO IRQ interrupts.
+         * Initialize gpiolib for GPIOs 0-71.
          */
-        writel(0, GPIO_LEVEL_MASK(0));
-        writel(0, GPIO_EDGE_MASK(0));
-        writel(0, GPIO_EDGE_CAUSE(0));
+        orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
+                        IRQ_DOVE_GPIO_START);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
+
+        orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
+                        IRQ_DOVE_GPIO_START + 32);
+        set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
+
+        orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
+                        IRQ_DOVE_GPIO_START + 64);
 
         /*
          * Mask and clear PMU interrupts
@@ -111,18 +121,6 @@ void __init dove_init_irq(void)
         writel(0, PMU_INTERRUPT_MASK);
         writel(0, PMU_INTERRUPT_CAUSE);
 
-        for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) {
-                set_irq_chip(i, &orion_gpio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                irq_desc[i].status |= IRQ_LEVEL;
-                set_irq_flags(i, IRQF_VALID);
-        }
-        set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
-
         for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
                 set_irq_chip(i, &pmu_irq_chip);
                 set_irq_handler(i, handle_level_irq);
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
new file mode 100644
index 000000000000..a021b5240bba
--- /dev/null
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -0,0 +1,195 @@
+# arch/arm/mach-exynos4/Kconfig
+#
+# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+#               http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+# Configuration options for the EXYNOS4
+
+if ARCH_EXYNOS4
+
+config CPU_EXYNOS4210
+        bool
+        select S3C_PL330_DMA
+        help
+          Enable EXYNOS4210 CPU support
+
+config EXYNOS4_MCT
+        bool "Kernel timer support by MCT"
+        help
+          Use MCT (Multi Core Timer) as kernel timers
+
+config EXYNOS4_DEV_PD
+        bool
+        help
+          Compile in platform device definitions for Power Domain
+
+config EXYNOS4_DEV_SYSMMU
+        bool
+        help
+          Common setup code for SYSTEM MMU in EXYNOS4
+
+config EXYNOS4_SETUP_I2C1
+        bool
+        help
+          Common setup code for i2c bus 1.
+
+config EXYNOS4_SETUP_I2C2
+        bool
+        help
+          Common setup code for i2c bus 2.
+
+config EXYNOS4_SETUP_I2C3
+        bool
+        help
+          Common setup code for i2c bus 3.
+
+config EXYNOS4_SETUP_I2C4
+        bool
+        help
+          Common setup code for i2c bus 4.
+
+config EXYNOS4_SETUP_I2C5
+        bool
+        help
+          Common setup code for i2c bus 5.
+
+config EXYNOS4_SETUP_I2C6
+        bool
+        help
+          Common setup code for i2c bus 6.
+
+config EXYNOS4_SETUP_I2C7
+        bool
+        help
+          Common setup code for i2c bus 7.
+
+config EXYNOS4_SETUP_KEYPAD
+        bool
+        help
+          Common setup code for keypad.
+
+config EXYNOS4_SETUP_SDHCI
+        bool
+        select EXYNOS4_SETUP_SDHCI_GPIO
+        help
+          Internal helper functions for EXYNOS4 based SDHCI systems.
+
+config EXYNOS4_SETUP_SDHCI_GPIO
+        bool
+        help
+          Common setup code for SDHCI gpio.
+
+config EXYNOS4_SETUP_FIMC
+        bool
+        help
+          Common setup code for the camera interfaces.
+
+# machine support
+
+menu "EXYNOS4 Machines"
+
+config MACH_SMDKC210
+        bool "SMDKC210"
+        select CPU_EXYNOS4210
+        select S3C_DEV_RTC
+        select S3C_DEV_WDT
+        select S3C_DEV_I2C1
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C_DEV_HSMMC2
+        select S3C_DEV_HSMMC3
+        select EXYNOS4_DEV_PD
+        select EXYNOS4_DEV_SYSMMU
+        select EXYNOS4_SETUP_I2C1
+        select EXYNOS4_SETUP_SDHCI
+        help
+          Machine support for Samsung SMDKC210
+
+config MACH_SMDKV310
+        bool "SMDKV310"
+        select CPU_EXYNOS4210
+        select S3C_DEV_RTC
+        select S3C_DEV_WDT
+        select S3C_DEV_I2C1
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C_DEV_HSMMC2
+        select S3C_DEV_HSMMC3
+        select SAMSUNG_DEV_KEYPAD
+        select EXYNOS4_DEV_PD
+        select EXYNOS4_DEV_SYSMMU
+        select EXYNOS4_SETUP_I2C1
+        select EXYNOS4_SETUP_KEYPAD
+        select EXYNOS4_SETUP_SDHCI
+        help
+          Machine support for Samsung SMDKV310
+
+config MACH_ARMLEX4210
+        bool "ARMLEX4210"
+        select CPU_EXYNOS4210
+        select S3C_DEV_RTC
+        select S3C_DEV_WDT
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC2
+        select S3C_DEV_HSMMC3
+        select EXYNOS4_DEV_SYSMMU
+        select EXYNOS4_SETUP_SDHCI
+        select SATA_AHCI_PLATFORM
+        help
+          Machine support for Samsung ARMLEX4210 based on EXYNOS4210
+
+config MACH_UNIVERSAL_C210
+        bool "Mobile UNIVERSAL_C210 Board"
+        select CPU_EXYNOS4210
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC2
+        select S3C_DEV_HSMMC3
+        select S3C_DEV_I2C1
+        select S3C_DEV_I2C5
+        select S5P_DEV_ONENAND
+        select EXYNOS4_SETUP_I2C1
+        select EXYNOS4_SETUP_I2C5
+        select EXYNOS4_SETUP_SDHCI
+        help
+          Machine support for Samsung Mobile Universal S5PC210 Reference
+          Board.
+
+config MACH_NURI
+        bool "Mobile NURI Board"
+        select CPU_EXYNOS4210
+        select S3C_DEV_WDT
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC2
+        select S3C_DEV_HSMMC3
+        select S3C_DEV_I2C1
+        select S3C_DEV_I2C5
+        select EXYNOS4_SETUP_I2C1
+        select EXYNOS4_SETUP_I2C5
+        select EXYNOS4_SETUP_SDHCI
+        select SAMSUNG_DEV_PWM
+        help
+          Machine support for Samsung Mobile NURI Board.
+
+endmenu
+
+comment "Configuration for HSMMC bus width"
+
+menu "Use 8-bit bus width"
+
+config EXYNOS4_SDHCI_CH0_8BIT
+        bool "Channel 0 with 8-bit bus"
+        help
+          Support HSMMC Channel 0 8-bit bus.
+          If selected, Channel 1 is disabled.
+
+config EXYNOS4_SDHCI_CH2_8BIT
+        bool "Channel 2 with 8-bit bus"
+        help
+          Support HSMMC Channel 2 8-bit bus.
+          If selected, Channel 3 is disabled.
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
new file mode 100644
index 000000000000..b8f0e7d82d7e
--- /dev/null
+++ b/arch/arm/mach-exynos4/Makefile
@@ -0,0 +1,56 @@
+# arch/arm/mach-exynos4/Makefile
+#
+# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+#               http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+obj-y                           :=
+obj-m                           :=
+obj-n                           :=
+obj-                            :=
+
+# Core support for EXYNOS4 system
+
+obj-$(CONFIG_CPU_EXYNOS4210)    += cpu.o init.o clock.o irq-combiner.o
+obj-$(CONFIG_CPU_EXYNOS4210)    += setup-i2c0.o gpiolib.o irq-eint.o dma.o
+obj-$(CONFIG_PM)                += pm.o sleep.o
+obj-$(CONFIG_CPU_FREQ)          += cpufreq.o
+
+obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
+
+ifeq ($(CONFIG_EXYNOS4_MCT),y)
+obj-y                           += mct.o
+else
+obj-y                           += time.o
+obj-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
+endif
+
+obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
+
+# machine support
+
+obj-$(CONFIG_MACH_SMDKC210)             += mach-smdkc210.o
+obj-$(CONFIG_MACH_SMDKV310)             += mach-smdkv310.o
+obj-$(CONFIG_MACH_ARMLEX4210)           += mach-armlex4210.o
+obj-$(CONFIG_MACH_UNIVERSAL_C210)       += mach-universal_c210.o
+obj-$(CONFIG_MACH_NURI)                 += mach-nuri.o
+
+# device support
+
+obj-y                                   += dev-audio.o
+obj-$(CONFIG_EXYNOS4_DEV_PD)            += dev-pd.o
+obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)        += dev-sysmmu.o
+
+obj-$(CONFIG_EXYNOS4_SETUP_FIMC)        += setup-fimc.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C1)        += setup-i2c1.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C2)        += setup-i2c2.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C3)        += setup-i2c3.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C4)        += setup-i2c4.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C5)        += setup-i2c5.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C6)        += setup-i2c6.o
+obj-$(CONFIG_EXYNOS4_SETUP_I2C7)        += setup-i2c7.o
+obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)      += setup-keypad.o
+obj-$(CONFIG_EXYNOS4_SETUP_SDHCI)       += setup-sdhci.o
+obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
+obj-$(CONFIG_SATA_AHCI_PLATFORM)        += dev-ahci.o
diff --git a/arch/arm/mach-s5pv310/Makefile.boot b/arch/arm/mach-exynos4/Makefile.boot
index d65956ffb43d..d65956ffb43d 100644
--- a/arch/arm/mach-s5pv310/Makefile.boot
+++ b/arch/arm/mach-exynos4/Makefile.boot
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-exynos4/clock.c
index fc7c2f8d165e..871f9d508fde 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5pv310/clock.c
+/* linux/arch/arm/mach-exynos4/clock.c
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5PV310 - Clock support
+ * EXYNOS4 - Clock support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -23,6 +23,7 @@
 
 #include <mach/map.h>
 #include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
 
 static struct clk clk_sclk_hdmi27m = {
         .name           = "sclk_hdmi27m",
@@ -46,72 +47,82 @@ static struct clk clk_sclk_usbphy1 = {
         .id             = -1,
 };
 
-static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
 }
 
-static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
+static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
 }
 
-static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
+static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
 }
 
-static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
+static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
 }
 
-static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
 }
 
-static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
+static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
 }
 
-static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
+static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
 }
 
-static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
+static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
+}
+
+static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
 }
 
-static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable)
+static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
+}
+
+static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
 }
 
-static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
+static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
 }
 
-static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
 }
 
-static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
 }
 
-static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
+static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
 }
 
-static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable)
+static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
 }
@@ -358,7 +369,7 @@ static struct clksrc_clk clk_vpllsrc = {
         .clk    = {
                 .name           = "vpll_src",
                 .id             = -1,
-                .enable         = s5pv310_clksrc_mask_top_ctrl,
+                .enable         = exynos4_clksrc_mask_top_ctrl,
                 .ctrlbit        = (1 << 0),
         },
         .sources        = &clkset_vpllsrc,
@@ -389,239 +400,322 @@ static struct clk init_clocks_off[] = {
                 .name           = "timers",
                 .id             = -1,
                 .parent         = &clk_aclk_100.clk,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1<<24),
         }, {
                 .name           = "csis",
                 .id             = 0,
-                .enable         = s5pv310_clk_ip_cam_ctrl,
+                .enable         = exynos4_clk_ip_cam_ctrl,
                 .ctrlbit        = (1 << 4),
         }, {
                 .name           = "csis",
                 .id             = 1,
-                .enable         = s5pv310_clk_ip_cam_ctrl,
+                .enable         = exynos4_clk_ip_cam_ctrl,
                 .ctrlbit        = (1 << 5),
         }, {
                 .name           = "fimc",
                 .id             = 0,
-                .enable         = s5pv310_clk_ip_cam_ctrl,
+                .enable         = exynos4_clk_ip_cam_ctrl,
                 .ctrlbit        = (1 << 0),
         }, {
                 .name           = "fimc",
                 .id             = 1,
-                .enable         = s5pv310_clk_ip_cam_ctrl,
+                .enable         = exynos4_clk_ip_cam_ctrl,
                 .ctrlbit        = (1 << 1),
         }, {
                 .name           = "fimc",
                 .id             = 2,
-                .enable         = s5pv310_clk_ip_cam_ctrl,
+                .enable         = exynos4_clk_ip_cam_ctrl,
                 .ctrlbit        = (1 << 2),
         }, {
                 .name           = "fimc",
                 .id             = 3,
-                .enable         = s5pv310_clk_ip_cam_ctrl,
+                .enable         = exynos4_clk_ip_cam_ctrl,
                 .ctrlbit        = (1 << 3),
         }, {
                 .name           = "fimd",
                 .id             = 0,
-                .enable         = s5pv310_clk_ip_lcd0_ctrl,
+                .enable         = exynos4_clk_ip_lcd0_ctrl,
                 .ctrlbit        = (1 << 0),
         }, {
                 .name           = "fimd",
                 .id             = 1,
-                .enable         = s5pv310_clk_ip_lcd1_ctrl,
+                .enable         = exynos4_clk_ip_lcd1_ctrl,
                 .ctrlbit        = (1 << 0),
         }, {
+                .name           = "sataphy",
+                .id             = -1,
+                .parent         = &clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
                 .name           = "hsmmc",
                 .id             = 0,
                 .parent         = &clk_aclk_133.clk,
-                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 5),
         }, {
                 .name           = "hsmmc",
                 .id             = 1,
                 .parent         = &clk_aclk_133.clk,
-                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 6),
         }, {
                 .name           = "hsmmc",
                 .id             = 2,
                 .parent         = &clk_aclk_133.clk,
-                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 7),
         }, {
                 .name           = "hsmmc",
                 .id             = 3,
                 .parent         = &clk_aclk_133.clk,
-                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 8),
         }, {
                 .name           = "hsmmc",
                 .id             = 4,
                 .parent         = &clk_aclk_133.clk,
-                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 9),
         }, {
                 .name           = "sata",
                 .id             = -1,
-                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .parent         = &clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 10),
         }, {
                 .name           = "pdma",
                 .id             = 0,
-                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 0),
         }, {
                 .name           = "pdma",
                 .id             = 1,
-                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 1),
         }, {
                 .name           = "adc",
                 .id             = -1,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 15),
         }, {
+                .name           = "keypad",
+                .id             = -1,
+                .enable         = exynos4_clk_ip_perir_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
                 .name           = "rtc",
                 .id             = -1,
-                .enable         = s5pv310_clk_ip_perir_ctrl,
+                .enable         = exynos4_clk_ip_perir_ctrl,
                 .ctrlbit        = (1 << 15),
         }, {
                 .name           = "watchdog",
                 .id             = -1,
-                .enable         = s5pv310_clk_ip_perir_ctrl,
+                .parent         = &clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_perir_ctrl,
                 .ctrlbit        = (1 << 14),
         }, {
                 .name           = "usbhost",
                 .id             = -1,
-                .enable         = s5pv310_clk_ip_fsys_ctrl ,
+                .enable         = exynos4_clk_ip_fsys_ctrl ,
                 .ctrlbit        = (1 << 12),
         }, {
                 .name           = "otg",
                 .id             = -1,
-                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 13),
         }, {
                 .name           = "spi",
                 .id             = 0,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 16),
         }, {
                 .name           = "spi",
                 .id             = 1,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 17),
         }, {
                 .name           = "spi",
                 .id             = 2,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 18),
         }, {
                 .name           = "iis",
                 .id             = 0,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 19),
         }, {
                 .name           = "iis",
                 .id             = 1,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 20),
         }, {
                 .name           = "iis",
                 .id             = 2,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 21),
         }, {
                 .name           = "ac97",
                 .id             = -1,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 27),
         }, {
                 .name           = "fimg2d",
                 .id             = -1,
-                .enable         = s5pv310_clk_ip_image_ctrl,
+                .enable         = exynos4_clk_ip_image_ctrl,
                 .ctrlbit        = (1 << 0),
         }, {
                 .name           = "i2c",
                 .id             = 0,
                 .parent         = &clk_aclk_100.clk,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 6),
         }, {
                 .name           = "i2c",
                 .id             = 1,
                 .parent         = &clk_aclk_100.clk,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 7),
         }, {
                 .name           = "i2c",
                 .id             = 2,
                 .parent         = &clk_aclk_100.clk,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 8),
         }, {
                 .name           = "i2c",
                 .id             = 3,
                 .parent         = &clk_aclk_100.clk,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 9),
         }, {
                 .name           = "i2c",
                 .id             = 4,
                 .parent         = &clk_aclk_100.clk,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 10),
         }, {
                 .name           = "i2c",
                 .id             = 5,
                 .parent         = &clk_aclk_100.clk,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 11),
         }, {
                 .name           = "i2c",
                 .id             = 6,
                 .parent         = &clk_aclk_100.clk,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 12),
         }, {
                 .name           = "i2c",
                 .id             = 7,
                 .parent         = &clk_aclk_100.clk,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 13),
-        },
+        }, {
+                .name           = "SYSMMU_MDMA",
+                .id             = -1,
+                .enable         = exynos4_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "SYSMMU_FIMC0",
+                .id             = -1,
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "SYSMMU_FIMC1",
+                .id             = -1,
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "SYSMMU_FIMC2",
+                .id             = -1,
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "SYSMMU_FIMC3",
+                .id             = -1,
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 10),
+        }, {
+                .name           = "SYSMMU_JPEG",
+                .id             = -1,
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 11),
+        }, {
+                .name           = "SYSMMU_FIMD0",
+                .id             = -1,
+                .enable         = exynos4_clk_ip_lcd0_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "SYSMMU_FIMD1",
+                .id             = -1,
+                .enable         = exynos4_clk_ip_lcd1_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "SYSMMU_PCIe",
+                .id             = -1,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 18),
+        }, {
+                .name           = "SYSMMU_G2D",
+                .id             = -1,
+                .enable         = exynos4_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "SYSMMU_ROTATOR",
+                .id             = -1,
+                .enable         = exynos4_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "SYSMMU_TV",
+                .id             = -1,
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "SYSMMU_MFC_L",
+                .id             = -1,
+                .enable         = exynos4_clk_ip_mfc_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "SYSMMU_MFC_R",
+                .id             = -1,
+                .enable         = exynos4_clk_ip_mfc_ctrl,
+                .ctrlbit        = (1 << 2),
+        }
 };
 
 static struct clk init_clocks[] = {
         {
                 .name           = "uart",
                 .id             = 0,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 0),
         }, {
                 .name           = "uart",
                 .id             = 1,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 1),
         }, {
                 .name           = "uart",
                 .id             = 2,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 2),
         }, {
                 .name           = "uart",
                 .id             = 3,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 3),
         }, {
                 .name           = "uart",
                 .id             = 4,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 4),
         }, {
                 .name           = "uart",
                 .id             = 5,
-                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 5),
         }
 };
@@ -746,7 +840,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk    = {
                         .name           = "uclk1",
                         .id             = 0,
-                        .enable         = s5pv310_clksrc_mask_peril0_ctrl,
+                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
                         .ctrlbit        = (1 << 0),
                 },
                 .sources = &clkset_group,
@@ -756,7 +850,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "uclk1",
                         .id             = 1,
-                        .enable         = s5pv310_clksrc_mask_peril0_ctrl,
+                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
                         .ctrlbit        = (1 << 4),
                 },
                 .sources = &clkset_group,
@@ -766,7 +860,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "uclk1",
                         .id             = 2,
-                        .enable         = s5pv310_clksrc_mask_peril0_ctrl,
+                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
                         .ctrlbit        = (1 << 8),
                 },
                 .sources = &clkset_group,
@@ -776,7 +870,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "uclk1",
                         .id             = 3,
-                        .enable         = s5pv310_clksrc_mask_peril0_ctrl,
+                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
                         .ctrlbit        = (1 << 12),
                 },
                 .sources = &clkset_group,
@@ -786,7 +880,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "sclk_pwm",
                         .id             = -1,
-                        .enable         = s5pv310_clksrc_mask_peril0_ctrl,
+                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
                         .ctrlbit        = (1 << 24),
                 },
                 .sources = &clkset_group,
@@ -796,7 +890,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "sclk_csis",
                         .id             = 0,
-                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
                         .ctrlbit        = (1 << 24),
                 },
                 .sources = &clkset_group,
@@ -806,7 +900,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "sclk_csis",
                         .id             = 1,
-                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
                         .ctrlbit        = (1 << 28),
                 },
                 .sources = &clkset_group,
@@ -816,7 +910,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "sclk_cam",
                         .id             = 0,
-                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
                         .ctrlbit        = (1 << 16),
                 },
                 .sources = &clkset_group,
@@ -826,7 +920,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "sclk_cam",
                         .id             = 1,
-                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
                         .ctrlbit        = (1 << 20),
                 },
                 .sources = &clkset_group,
@@ -836,7 +930,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "sclk_fimc",
                         .id             = 0,
-                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
                         .ctrlbit        = (1 << 0),
                 },
                 .sources = &clkset_group,
@@ -846,7 +940,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "sclk_fimc",
                         .id             = 1,
-                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
                         .ctrlbit        = (1 << 4),
                 },
                 .sources = &clkset_group,
@@ -856,7 +950,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "sclk_fimc",
                         .id             = 2,
-                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
                         .ctrlbit        = (1 << 8),
                 },
                 .sources = &clkset_group,
@@ -866,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "sclk_fimc",
                         .id             = 3,
-                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
                         .ctrlbit        = (1 << 12),
                 },
                 .sources = &clkset_group,
@@ -876,7 +970,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "sclk_fimd",
                         .id             = 0,
-                        .enable         = s5pv310_clksrc_mask_lcd0_ctrl,
+                        .enable         = exynos4_clksrc_mask_lcd0_ctrl,
                         .ctrlbit        = (1 << 0),
                 },
                 .sources = &clkset_group,
@@ -886,7 +980,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "sclk_fimd",
                         .id             = 1,
-                        .enable         = s5pv310_clksrc_mask_lcd1_ctrl,
+                        .enable         = exynos4_clksrc_mask_lcd1_ctrl,
                         .ctrlbit        = (1 << 0),
                 },
                 .sources = &clkset_group,
@@ -896,7 +990,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "sclk_sata",
                         .id             = -1,
-                        .enable         = s5pv310_clksrc_mask_fsys_ctrl,
+                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
                         .ctrlbit        = (1 << 24),
                 },
                 .sources = &clkset_mout_corebus,
@@ -906,7 +1000,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "sclk_spi",
                         .id             = 0,
-                        .enable         = s5pv310_clksrc_mask_peril1_ctrl,
+                        .enable         = exynos4_clksrc_mask_peril1_ctrl,
                         .ctrlbit        = (1 << 16),
                 },
                 .sources = &clkset_group,
@@ -916,7 +1010,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "sclk_spi",
                         .id             = 1,
-                        .enable         = s5pv310_clksrc_mask_peril1_ctrl,
+                        .enable         = exynos4_clksrc_mask_peril1_ctrl,
                         .ctrlbit        = (1 << 20),
                 },
                 .sources = &clkset_group,
@@ -926,7 +1020,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "sclk_spi",
                         .id             = 2,
-                        .enable         = s5pv310_clksrc_mask_peril1_ctrl,
+                        .enable         = exynos4_clksrc_mask_peril1_ctrl,
                         .ctrlbit        = (1 << 24),
                 },
                 .sources = &clkset_group,
@@ -945,7 +1039,7 @@ static struct clksrc_clk clksrcs[] = {
                         .name           = "sclk_mmc",
                         .id             = 0,
                         .parent         = &clk_dout_mmc0.clk,
-                        .enable         = s5pv310_clksrc_mask_fsys_ctrl,
+                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
                         .ctrlbit        = (1 << 0),
                 },
                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
@@ -954,7 +1048,7 @@ static struct clksrc_clk clksrcs[] = {
                         .name           = "sclk_mmc",
                         .id             = 1,
                         .parent         = &clk_dout_mmc1.clk,
-                        .enable         = s5pv310_clksrc_mask_fsys_ctrl,
+                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
                         .ctrlbit        = (1 << 4),
                 },
                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
@@ -963,7 +1057,7 @@ static struct clksrc_clk clksrcs[] = {
                         .name           = "sclk_mmc",
                         .id             = 2,
                         .parent         = &clk_dout_mmc2.clk,
-                        .enable         = s5pv310_clksrc_mask_fsys_ctrl,
+                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
                         .ctrlbit        = (1 << 8),
                 },
                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
@@ -972,7 +1066,7 @@ static struct clksrc_clk clksrcs[] = {
                         .name           = "sclk_mmc",
                         .id             = 3,
                         .parent         = &clk_dout_mmc3.clk,
-                        .enable         = s5pv310_clksrc_mask_fsys_ctrl,
+                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
                         .ctrlbit        = (1 << 12),
                 },
                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
@@ -981,7 +1075,7 @@ static struct clksrc_clk clksrcs[] = {
                         .name           = "sclk_mmc",
                         .id             = 4,
                         .parent         = &clk_dout_mmc4.clk,
-                        .enable         = s5pv310_clksrc_mask_fsys_ctrl,
+                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
                         .ctrlbit        = (1 << 16),
                 },
                 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
@@ -1022,16 +1116,16 @@ static struct clksrc_clk *sysclks[] = {
 
 static int xtal_rate;
 
-static unsigned long s5pv310_fout_apll_get_rate(struct clk *clk)
+static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
 {
         return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
 }
 
-static struct clk_ops s5pv310_fout_apll_ops = {
-        .get_rate = s5pv310_fout_apll_get_rate,
+static struct clk_ops exynos4_fout_apll_ops = {
+        .get_rate = exynos4_fout_apll_get_rate,
 };
 
-void __init_or_cpufreq s5pv310_setup_clocks(void)
+void __init_or_cpufreq exynos4_setup_clocks(void)
 {
         struct clk *xtal_clk;
         unsigned long apll;
@@ -1070,12 +1164,12 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
         vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
                                 __raw_readl(S5P_VPLL_CON1), pll_4650);
 
-        clk_fout_apll.ops = &s5pv310_fout_apll_ops;
+        clk_fout_apll.ops = &exynos4_fout_apll_ops;
         clk_fout_mpll.rate = mpll;
         clk_fout_epll.rate = epll;
         clk_fout_vpll.rate = vpll;
 
-        printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
+        printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
                         apll, mpll, epll, vpll);
 
         armclk = clk_get_rate(&clk_armclk.clk);
@@ -1086,7 +1180,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
         aclk_160 = clk_get_rate(&clk_aclk_160.clk);
         aclk_133 = clk_get_rate(&clk_aclk_133.clk);
 
-        printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
+        printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
                         armclk, sclk_dmc, aclk_200,
                         aclk_100, aclk_160, aclk_133);
@@ -1103,7 +1197,7 @@ static struct clk *clks[] __initdata = {
         /* Nothing here yet */
 };
 
-void __init s5pv310_register_clocks(void)
+void __init exynos4_register_clocks(void)
 {
         int ptr;
 
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 0db0fb65bd70..793011391943 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -1,7 +1,7 @@
-/* linux/arch/arm/mach-s5pv310/cpu.c
+/* linux/arch/arm/mach-exynos4/cpu.c
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -19,8 +19,10 @@
 
 #include <plat/cpu.h>
 #include <plat/clock.h>
-#include <plat/s5pv310.h>
+#include <plat/exynos4.h>
 #include <plat/sdhci.h>
+#include <plat/devs.h>
+#include <plat/fimc-core.h>
 
 #include <mach/regs-irq.h>
 
@@ -29,55 +31,60 @@ extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
 
 /* Initial IO mappings */
-static struct map_desc s5pv310_iodesc[] __initdata = {
+static struct map_desc exynos4_iodesc[] __initdata = {
         {
+                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
-                .pfn            = __phys_to_pfn(S5PV310_PA_SYSRAM),
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S5P_VA_CMU,
-                .pfn            = __phys_to_pfn(S5PV310_PA_CMU),
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
                 .length         = SZ_128K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S5P_VA_PMU,
-                .pfn            = __phys_to_pfn(S5PV310_PA_PMU),
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
                 .length         = SZ_64K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
-                .pfn            = __phys_to_pfn(S5PV310_PA_COMBINER),
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
-                .pfn            = __phys_to_pfn(S5PV310_PA_COREPERI),
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
                 .length         = SZ_8K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S5P_VA_L2CC,
-                .pfn            = __phys_to_pfn(S5PV310_PA_L2CC),
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S5P_VA_GPIO1,
-                .pfn            = __phys_to_pfn(S5PV310_PA_GPIO1),
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S5P_VA_GPIO2,
-                .pfn            = __phys_to_pfn(S5PV310_PA_GPIO2),
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S5P_VA_GPIO3,
-                .pfn            = __phys_to_pfn(S5PV310_PA_GPIO3),
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
                 .length         = SZ_256,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S5P_VA_DMC0,
-                .pfn            = __phys_to_pfn(S5PV310_PA_DMC0),
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
@@ -87,13 +94,13 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S5P_VA_SROMC,
-                .pfn            = __phys_to_pfn(S5PV310_PA_SROMC),
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         },
 };
 
-static void s5pv310_idle(void)
+static void exynos4_idle(void)
 {
         if (!need_resched())
                 cpu_do_idle();
@@ -101,32 +108,38 @@ static void s5pv310_idle(void)
         local_irq_enable();
 }
 
-/* s5pv310_map_io
+/*
+ * exynos4_map_io
  *
  * register the standard cpu IO areas
-*/
-void __init s5pv310_map_io(void)
+ */
+void __init exynos4_map_io(void)
 {
-        iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc));
+        iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 
         /* initialize device information early */
-        s5pv310_default_sdhci0();
-        s5pv310_default_sdhci1();
-        s5pv310_default_sdhci2();
-        s5pv310_default_sdhci3();
+        exynos4_default_sdhci0();
+        exynos4_default_sdhci1();
+        exynos4_default_sdhci2();
+        exynos4_default_sdhci3();
+
+        s3c_fimc_setname(0, "exynos4-fimc");
+        s3c_fimc_setname(1, "exynos4-fimc");
+        s3c_fimc_setname(2, "exynos4-fimc");
+        s3c_fimc_setname(3, "exynos4-fimc");
 }
 
-void __init s5pv310_init_clocks(int xtal)
+void __init exynos4_init_clocks(int xtal)
 {
         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 
         s3c24xx_register_baseclocks(xtal);
         s5p_register_clocks(xtal);
-        s5pv310_register_clocks();
-        s5pv310_setup_clocks();
+        exynos4_register_clocks();
+        exynos4_setup_clocks();
 }
 
-void __init s5pv310_init_irq(void)
+void __init exynos4_init_irq(void)
 {
         int irq;
 
@@ -148,29 +161,29 @@ void __init s5pv310_init_irq(void)
         }
 
         /* The parameters of s5p_init_irq() are for VIC init.
-         * Theses parameters should be NULL and 0 because S5PV310
+         * Theses parameters should be NULL and 0 because EXYNOS4
          * uses GIC instead of VIC.
          */
         s5p_init_irq(NULL, 0);
 }
 
-struct sysdev_class s5pv310_sysclass = {
-        .name   = "s5pv310-core",
+struct sysdev_class exynos4_sysclass = {
+        .name   = "exynos4-core",
 };
 
-static struct sys_device s5pv310_sysdev = {
-        .cls    = &s5pv310_sysclass,
+static struct sys_device exynos4_sysdev = {
+        .cls    = &exynos4_sysclass,
 };
 
-static int __init s5pv310_core_init(void)
+static int __init exynos4_core_init(void)
 {
-        return sysdev_class_register(&s5pv310_sysclass);
+        return sysdev_class_register(&exynos4_sysclass);
 }
 
-core_initcall(s5pv310_core_init);
+core_initcall(exynos4_core_init);
 
 #ifdef CONFIG_CACHE_L2X0
-static int __init s5pv310_l2x0_cache_init(void)
+static int __init exynos4_l2x0_cache_init(void)
 {
         /* TAG, Data Latency Control: 2cycle */
         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
@@ -188,15 +201,15 @@ static int __init s5pv310_l2x0_cache_init(void)
         return 0;
 }
 
-early_initcall(s5pv310_l2x0_cache_init);
+early_initcall(exynos4_l2x0_cache_init);
 #endif
 
-int __init s5pv310_init(void)
+int __init exynos4_init(void)
 {
-        printk(KERN_INFO "S5PV310: Initializing architecture\n");
+        printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
 
         /* set idle function */
-        pm_idle = s5pv310_idle;
+        pm_idle = exynos4_idle;
 
-        return sysdev_register(&s5pv310_sysdev);
+        return sysdev_register(&exynos4_sysdev);
 }
diff --git a/arch/arm/mach-s5pv310/cpufreq.c b/arch/arm/mach-exynos4/cpufreq.c
index 7c08ad7d8887..a1bd258f0c4d 100644
--- a/arch/arm/mach-s5pv310/cpufreq.c
+++ b/arch/arm/mach-exynos4/cpufreq.c
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5pv310/cpufreq.c
+/* linux/arch/arm/mach-exynos4/cpufreq.c
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * S5PV310 - CPU frequency scaling support
+ * EXYNOS4 - CPU frequency scaling support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -31,15 +31,13 @@ static struct clk *moutcore;
 static struct clk *mout_mpll;
 static struct clk *mout_apll;
 
-#ifdef CONFIG_REGULATOR
 static struct regulator *arm_regulator;
 static struct regulator *int_regulator;
-#endif
 
 static struct cpufreq_freqs freqs;
 static unsigned int memtype;
 
-enum s5pv310_memory_type {
+enum exynos4_memory_type {
         DDR2 = 4,
         LPDDR2,
         DDR3,
@@ -49,7 +47,7 @@ enum cpufreq_level_index {
         L0, L1, L2, L3, CPUFREQ_LEVEL_END,
 };
 
-static struct cpufreq_frequency_table s5pv310_freq_table[] = {
+static struct cpufreq_frequency_table exynos4_freq_table[] = {
         {L0, 1000*1000},
         {L1, 800*1000},
         {L2, 400*1000},
@@ -160,7 +158,7 @@ struct cpufreq_voltage_table {
         unsigned int    int_volt;
 };
 
-static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
+static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
         {
                 .index          = L0,
                 .arm_volt       = 1200000,
@@ -180,7 +178,7 @@ static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
         },
 };
 
-static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
+static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
         /* APLL FOUT L0: 1000MHz */
         ((250 << 16) | (6 << 8) | 1),
 
@@ -194,17 +192,17 @@ static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
         ((200 << 16) | (6 << 8) | 4),
 };
 
-int s5pv310_verify_speed(struct cpufreq_policy *policy)
+int exynos4_verify_speed(struct cpufreq_policy *policy)
 {
-        return cpufreq_frequency_table_verify(policy, s5pv310_freq_table);
+        return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
 }
 
-unsigned int s5pv310_getspeed(unsigned int cpu)
+unsigned int exynos4_getspeed(unsigned int cpu)
 {
         return clk_get_rate(cpu_clk) / 1000;
 }
 
-void s5pv310_set_clkdiv(unsigned int div_index)
+void exynos4_set_clkdiv(unsigned int div_index)
 {
         unsigned int tmp;
 
@@ -321,7 +319,7 @@ void s5pv310_set_clkdiv(unsigned int div_index)
         } while (tmp & 0x11);
 }
 
-static void s5pv310_set_apll(unsigned int index)
+static void exynos4_set_apll(unsigned int index)
 {
         unsigned int tmp;
 
@@ -340,7 +338,7 @@ static void s5pv310_set_apll(unsigned int index)
         /* 3. Change PLL PMS values */
         tmp = __raw_readl(S5P_APLL_CON0);
         tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
-        tmp |= s5pv310_apll_pms_table[index];
+        tmp |= exynos4_apll_pms_table[index];
         __raw_writel(tmp, S5P_APLL_CON0);
 
         /* 4. wait_lock_time */
@@ -357,99 +355,95 @@ static void s5pv310_set_apll(unsigned int index)
         } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
 }
 
-static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index)
+static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
 {
         unsigned int tmp;
 
         if (old_index > new_index) {
                 /* The frequency changing to L0 needs to change apll */
-                if (freqs.new == s5pv310_freq_table[L0].frequency) {
+                if (freqs.new == exynos4_freq_table[L0].frequency) {
                         /* 1. Change the system clock divider values */
-                        s5pv310_set_clkdiv(new_index);
+                        exynos4_set_clkdiv(new_index);
 
                         /* 2. Change the apll m,p,s value */
-                        s5pv310_set_apll(new_index);
+                        exynos4_set_apll(new_index);
                 } else {
                         /* 1. Change the system clock divider values */
-                        s5pv310_set_clkdiv(new_index);
+                        exynos4_set_clkdiv(new_index);
 
                         /* 2. Change just s value in apll m,p,s value */
                         tmp = __raw_readl(S5P_APLL_CON0);
                         tmp &= ~(0x7 << 0);
-                        tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
+                        tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
                         __raw_writel(tmp, S5P_APLL_CON0);
                 }
         }
 
         else if (old_index < new_index) {
                 /* The frequency changing from L0 needs to change apll */
-                if (freqs.old == s5pv310_freq_table[L0].frequency) {
+                if (freqs.old == exynos4_freq_table[L0].frequency) {
                         /* 1. Change the apll m,p,s value */
-                        s5pv310_set_apll(new_index);
+                        exynos4_set_apll(new_index);
 
                         /* 2. Change the system clock divider values */
-                        s5pv310_set_clkdiv(new_index);
+                        exynos4_set_clkdiv(new_index);
                 } else {
                         /* 1. Change just s value in apll m,p,s value */
                         tmp = __raw_readl(S5P_APLL_CON0);
                         tmp &= ~(0x7 << 0);
-                        tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
+                        tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
                         __raw_writel(tmp, S5P_APLL_CON0);
 
                         /* 2. Change the system clock divider values */
-                        s5pv310_set_clkdiv(new_index);
+                        exynos4_set_clkdiv(new_index);
                 }
         }
 }
 
-static int s5pv310_target(struct cpufreq_policy *policy,
+static int exynos4_target(struct cpufreq_policy *policy,
                           unsigned int target_freq,
                           unsigned int relation)
 {
         unsigned int index, old_index;
         unsigned int arm_volt, int_volt;
 
-        freqs.old = s5pv310_getspeed(policy->cpu);
+        freqs.old = exynos4_getspeed(policy->cpu);
 
-        if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
+        if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
                                            freqs.old, relation, &old_index))
                 return -EINVAL;
 
-        if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
+        if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
                                            target_freq, relation, &index))
                 return -EINVAL;
 
-        freqs.new = s5pv310_freq_table[index].frequency;
+        freqs.new = exynos4_freq_table[index].frequency;
         freqs.cpu = policy->cpu;
 
         if (freqs.new == freqs.old)
                 return 0;
 
         /* get the voltage value */
-        arm_volt = s5pv310_volt_table[index].arm_volt;
-        int_volt = s5pv310_volt_table[index].int_volt;
+        arm_volt = exynos4_volt_table[index].arm_volt;
+        int_volt = exynos4_volt_table[index].int_volt;
 
         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 
         /* control regulator */
         if (freqs.new > freqs.old) {
                 /* Voltage up */
-#ifdef CONFIG_REGULATOR
                 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
                 regulator_set_voltage(int_regulator, int_volt, int_volt);
-#endif
         }
 
         /* Clock Configuration Procedure */
-        s5pv310_set_frequency(old_index, index);
+        exynos4_set_frequency(old_index, index);
 
         /* control regulator */
         if (freqs.new < freqs.old) {
                 /* Voltage down */
-#ifdef CONFIG_REGULATOR
                 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
                 regulator_set_voltage(int_regulator, int_volt, int_volt);
-#endif
         }
 
         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
@@ -458,51 +452,51 @@ static int s5pv310_target(struct cpufreq_policy *policy,
 }
 
 #ifdef CONFIG_PM
-static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy)
+static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy)
 {
         return 0;
 }
 
-static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy)
+static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
 {
         return 0;
 }
 #endif
 
-static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy)
+static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
 {
-        policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu);
+        policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
 
-        cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu);
+        cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
 
         /* set the transition latency value */
         policy->cpuinfo.transition_latency = 100000;
 
         /*
-         * S5PV310 multi-core processors has 2 cores
+         * EXYNOS4 multi-core processors has 2 cores
          * that the frequency cannot be set independently.
          * Each cpu is bound to the same speed.
          * So the affected cpu is all of the cpus.
          */
         cpumask_setall(policy->cpus);
 
-        return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table);
+        return cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
 }
 
-static struct cpufreq_driver s5pv310_driver = {
+static struct cpufreq_driver exynos4_driver = {
         .flags          = CPUFREQ_STICKY,
-        .verify         = s5pv310_verify_speed,
-        .target         = s5pv310_target,
-        .get            = s5pv310_getspeed,
-        .init           = s5pv310_cpufreq_cpu_init,
-        .name           = "s5pv310_cpufreq",
+        .verify         = exynos4_verify_speed,
+        .target         = exynos4_target,
+        .get            = exynos4_getspeed,
+        .init           = exynos4_cpufreq_cpu_init,
+        .name           = "exynos4_cpufreq",
 #ifdef CONFIG_PM
-        .suspend        = s5pv310_cpufreq_suspend,
-        .resume         = s5pv310_cpufreq_resume,
+        .suspend        = exynos4_cpufreq_suspend,
+        .resume         = exynos4_cpufreq_resume,
 #endif
 };
 
-static int __init s5pv310_cpufreq_init(void)
+static int __init exynos4_cpufreq_init(void)
 {
         cpu_clk = clk_get(NULL, "armclk");
         if (IS_ERR(cpu_clk))
@@ -520,7 +514,6 @@ static int __init s5pv310_cpufreq_init(void)
         if (IS_ERR(mout_apll))
                 goto out;
 
-#ifdef CONFIG_REGULATOR
         arm_regulator = regulator_get(NULL, "vdd_arm");
         if (IS_ERR(arm_regulator)) {
                 printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
@@ -532,7 +525,6 @@ static int __init s5pv310_cpufreq_init(void)
                 printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
                 goto out;
         }
-#endif
 
         /*
          * Check DRAM type.
@@ -549,7 +541,7 @@ static int __init s5pv310_cpufreq_init(void)
                 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
         }
 
-        return cpufreq_register_driver(&s5pv310_driver);
+        return cpufreq_register_driver(&exynos4_driver);
 
 out:
         if (!IS_ERR(cpu_clk))
@@ -564,16 +556,14 @@ out:
         if (!IS_ERR(mout_apll))
                 clk_put(mout_apll);
 
-#ifdef CONFIG_REGULATOR
         if (!IS_ERR(arm_regulator))
                 regulator_put(arm_regulator);
 
         if (!IS_ERR(int_regulator))
                 regulator_put(int_regulator);
-#endif
 
         printk(KERN_ERR "%s: failed initialization\n", __func__);
 
         return -EINVAL;
 }
-late_initcall(s5pv310_cpufreq_init);
+late_initcall(exynos4_cpufreq_init);
diff --git a/arch/arm/mach-exynos4/dev-ahci.c b/arch/arm/mach-exynos4/dev-ahci.c
new file mode 100644
index 000000000000..f57a3de8e1d2
--- /dev/null
+++ b/arch/arm/mach-exynos4/dev-ahci.c
@@ -0,0 +1,263 @@
+/* linux/arch/arm/mach-exynos4/dev-ahci.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4 - AHCI support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/ahci_platform.h>
+
+#include <plat/cpu.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <mach/regs-pmu.h>
+
+/* PHY Control Register */
+#define SATA_CTRL0              0x0
+/* PHY Link Control Register */
+#define SATA_CTRL1              0x4
+/* PHY Status Register */
+#define SATA_PHY_STATUS         0x8
+
+#define SATA_CTRL0_RX_DATA_VALID(x)     (x << 27)
+#define SATA_CTRL0_SPEED_MODE           (1 << 26)
+#define SATA_CTRL0_M_PHY_CAL            (1 << 19)
+#define SATA_CTRL0_PHY_CMU_RST_N        (1 << 10)
+#define SATA_CTRL0_M_PHY_LN_RST_N       (1 << 9)
+#define SATA_CTRL0_PHY_POR_N            (1 << 8)
+
+#define SATA_CTRL1_RST_PMALIVE_N        (1 << 8)
+#define SATA_CTRL1_RST_RXOOB_N          (1 << 7)
+#define SATA_CTRL1_RST_RX_N             (1 << 6)
+#define SATA_CTRL1_RST_TX_N             (1 << 5)
+
+#define SATA_PHY_STATUS_CMU_OK          (1 << 18)
+#define SATA_PHY_STATUS_LANE_OK         (1 << 16)
+
+#define LANE0           0x200
+#define COM_LANE        0xA00
+
+#define HOST_PORTS_IMPL 0xC
+#define SCLK_SATA_FREQ  (67 * MHZ)
+
+static void __iomem *phy_base, *phy_ctrl;
+
+struct phy_reg {
+        u8      reg;
+        u8      val;
+};
+
+/* SATA PHY setup */
+static const struct phy_reg exynos4_sataphy_cmu[] = {
+        { 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 },
+        { 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 },
+        { 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 },
+        { 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 },
+        { 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 },
+        { 0x6b, 0xc8 }, { 0x6c, 0x06 },
+};
+
+static const struct phy_reg exynos4_sataphy_lane[] = {
+        { 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 },
+        { 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 },
+        { 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e },
+        { 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 },
+        { 0x51, 0x0f },
+};
+
+static const struct phy_reg exynos4_sataphy_comlane[] = {
+        { 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d },
+        { 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 },
+        { 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 },
+        { 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 },
+        { 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 },
+        { 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 },
+        { 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 },
+        { 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d },
+        { 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 },
+        { 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 },
+        { 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 },
+        { 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff },
+        { 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 },
+        { 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 },
+};
+
+static int wait_for_phy_ready(void __iomem *reg, unsigned long bit)
+{
+        unsigned long timeout;
+
+        /* wait for maximum of 3 sec */
+        timeout = jiffies + msecs_to_jiffies(3000);
+        while (!(__raw_readl(reg) & bit)) {
+                if (time_after(jiffies, timeout))
+                        return -1;
+                cpu_relax();
+        }
+        return 0;
+}
+
+static int ahci_phy_init(void __iomem *mmio)
+{
+        int i, ctrl0;
+
+        for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)
+                __raw_writeb(exynos4_sataphy_cmu[i].val,
+                phy_base + (exynos4_sataphy_cmu[i].reg * 4));
+
+        for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)
+                __raw_writeb(exynos4_sataphy_lane[i].val,
+                phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);
+
+        for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)
+                __raw_writeb(exynos4_sataphy_comlane[i].val,
+                phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);
+
+        __raw_writeb(0x07, phy_base);
+
+        ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
+        ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;
+        __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
+
+        if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
+                                SATA_PHY_STATUS_CMU_OK) < 0) {
+                printk(KERN_ERR "PHY CMU not ready\n");
+                return -EBUSY;
+        }
+
+        __raw_writeb(0x03, phy_base + (COM_LANE * 4));
+
+        ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
+        ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;
+        __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
+
+        if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
+                                SATA_PHY_STATUS_LANE_OK) < 0) {
+                printk(KERN_ERR "PHY LANE not ready\n");
+                return -EBUSY;
+        }
+
+        ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
+        ctrl0 |= SATA_CTRL0_M_PHY_CAL;
+        __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
+
+        return 0;
+}
+
+static int exynos4_ahci_init(struct device *dev, void __iomem *mmio)
+{
+        struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata;
+        int val, ret;
+
+        phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K);
+        if (!phy_base) {
+                dev_err(dev, "failed to allocate memory for SATA PHY\n");
+                return -ENOMEM;
+        }
+
+        phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16);
+        if (!phy_ctrl) {
+                dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        clk_sata = clk_get(dev, "sata");
+        if (IS_ERR(clk_sata)) {
+                dev_err(dev, "failed to get sata clock\n");
+                ret = PTR_ERR(clk_sata);
+                clk_sata = NULL;
+                goto err2;
+
+        }
+        clk_enable(clk_sata);
+
+        clk_sataphy = clk_get(dev, "sataphy");
+        if (IS_ERR(clk_sataphy)) {
+                dev_err(dev, "failed to get sataphy clock\n");
+                ret = PTR_ERR(clk_sataphy);
+                clk_sataphy = NULL;
+                goto err3;
+        }
+        clk_enable(clk_sataphy);
+
+        clk_sclk_sata = clk_get(dev, "sclk_sata");
+        if (IS_ERR(clk_sclk_sata)) {
+                dev_err(dev, "failed to get sclk_sata\n");
+                ret = PTR_ERR(clk_sclk_sata);
+                clk_sclk_sata = NULL;
+                goto err4;
+        }
+        clk_enable(clk_sclk_sata);
+        clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);
+
+        __raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL);
+
+        /* Enable PHY link control */
+        val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N |
+                        SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N;
+        __raw_writel(val, phy_ctrl + SATA_CTRL1);
+
+        /* Set communication speed as 3Gbps and enable PHY power */
+        val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE |
+                        SATA_CTRL0_PHY_POR_N;
+        __raw_writel(val, phy_ctrl + SATA_CTRL0);
+
+        /* Port0 is available */
+        __raw_writel(0x1, mmio + HOST_PORTS_IMPL);
+
+        return ahci_phy_init(mmio);
+
+err4:
+        clk_disable(clk_sataphy);
+        clk_put(clk_sataphy);
+err3:
+        clk_disable(clk_sata);
+        clk_put(clk_sata);
+err2:
+        iounmap(phy_ctrl);
+err1:
+        iounmap(phy_base);
+
+        return ret;
+}
+
+static struct ahci_platform_data exynos4_ahci_pdata = {
+        .init = exynos4_ahci_init,
+};
+
+static struct resource exynos4_ahci_resource[] = {
+        [0] = {
+                .start  = EXYNOS4_PA_SATA,
+                .end    = EXYNOS4_PA_SATA + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_SATA,
+                .end    = IRQ_SATA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device exynos4_device_ahci = {
+        .name           = "ahci",
+        .id             = -1,
+        .resource       = exynos4_ahci_resource,
+        .num_resources  = ARRAY_SIZE(exynos4_ahci_resource),
+        .dev            = {
+                .platform_data          = &exynos4_ahci_pdata,
+                .dma_mask               = &exynos4_ahci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
diff --git a/arch/arm/mach-s5pv310/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c
index a1964242f0fa..1eed5f9f7bd3 100644
--- a/arch/arm/mach-s5pv310/dev-audio.c
+++ b/arch/arm/mach-exynos4/dev-audio.c
@@ -1,4 +1,7 @@
-/* linux/arch/arm/mach-s5pv310/dev-audio.c
+/* linux/arch/arm/mach-exynos4/dev-audio.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * Copyright (c) 2010 Samsung Electronics Co. Ltd
  *      Jaswinder Singh <jassi.brar@samsung.com>
@@ -24,18 +27,18 @@ static const char *rclksrc[] = {
         [1] = "i2sclk",
 };
 
-static int s5pv310_cfg_i2s(struct platform_device *pdev)
+static int exynos4_cfg_i2s(struct platform_device *pdev)
 {
         /* configure GPIO for i2s port */
         switch (pdev->id) {
         case 0:
-                s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 7, S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
                 break;
         case 1:
-                s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
                 break;
         case 2:
-                s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(4));
+                s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
                 break;
         default:
                 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
@@ -46,7 +49,7 @@ static int s5pv310_cfg_i2s(struct platform_device *pdev)
 }
 
 static struct s3c_audio_pdata i2sv5_pdata = {
-        .cfg_gpio = s5pv310_cfg_i2s,
+        .cfg_gpio = exynos4_cfg_i2s,
         .type = {
                 .i2s = {
                         .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
@@ -56,10 +59,10 @@ static struct s3c_audio_pdata i2sv5_pdata = {
         },
 };
 
-static struct resource s5pv310_i2s0_resource[] = {
+static struct resource exynos4_i2s0_resource[] = {
         [0] = {
-                .start  = S5PV310_PA_I2S0,
-                .end    = S5PV310_PA_I2S0 + 0x100 - 1,
+                .start  = EXYNOS4_PA_I2S0,
+                .end    = EXYNOS4_PA_I2S0 + 0x100 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -79,11 +82,11 @@ static struct resource s5pv310_i2s0_resource[] = {
         },
 };
 
-struct platform_device s5pv310_device_i2s0 = {
+struct platform_device exynos4_device_i2s0 = {
         .name = "samsung-i2s",
         .id = 0,
-        .num_resources = ARRAY_SIZE(s5pv310_i2s0_resource),
-        .resource = s5pv310_i2s0_resource,
+        .num_resources = ARRAY_SIZE(exynos4_i2s0_resource),
+        .resource = exynos4_i2s0_resource,
         .dev = {
                 .platform_data = &i2sv5_pdata,
         },
@@ -95,7 +98,7 @@ static const char *rclksrc_v3[] = {
 };
 
 static struct s3c_audio_pdata i2sv3_pdata = {
-        .cfg_gpio = s5pv310_cfg_i2s,
+        .cfg_gpio = exynos4_cfg_i2s,
         .type = {
                 .i2s = {
                         .quirks = QUIRK_NO_MUXPSR,
@@ -104,10 +107,10 @@ static struct s3c_audio_pdata i2sv3_pdata = {
         },
 };
 
-static struct resource s5pv310_i2s1_resource[] = {
+static struct resource exynos4_i2s1_resource[] = {
         [0] = {
-                .start  = S5PV310_PA_I2S1,
-                .end    = S5PV310_PA_I2S1 + 0x100 - 1,
+                .start  = EXYNOS4_PA_I2S1,
+                .end    = EXYNOS4_PA_I2S1 + 0x100 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -122,20 +125,20 @@ static struct resource s5pv310_i2s1_resource[] = {
         },
 };
 
-struct platform_device s5pv310_device_i2s1 = {
+struct platform_device exynos4_device_i2s1 = {
         .name = "samsung-i2s",
         .id = 1,
-        .num_resources = ARRAY_SIZE(s5pv310_i2s1_resource),
-        .resource = s5pv310_i2s1_resource,
+        .num_resources = ARRAY_SIZE(exynos4_i2s1_resource),
+        .resource = exynos4_i2s1_resource,
         .dev = {
                 .platform_data = &i2sv3_pdata,
         },
 };
 
-static struct resource s5pv310_i2s2_resource[] = {
+static struct resource exynos4_i2s2_resource[] = {
         [0] = {
-                .start  = S5PV310_PA_I2S2,
-                .end    = S5PV310_PA_I2S2 + 0x100 - 1,
+                .start  = EXYNOS4_PA_I2S2,
+                .end    = EXYNOS4_PA_I2S2 + 0x100 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -150,11 +153,11 @@ static struct resource s5pv310_i2s2_resource[] = {
         },
 };
 
-struct platform_device s5pv310_device_i2s2 = {
+struct platform_device exynos4_device_i2s2 = {
         .name = "samsung-i2s",
         .id = 2,
-        .num_resources = ARRAY_SIZE(s5pv310_i2s2_resource),
-        .resource = s5pv310_i2s2_resource,
+        .num_resources = ARRAY_SIZE(exynos4_i2s2_resource),
+        .resource = exynos4_i2s2_resource,
         .dev = {
                 .platform_data = &i2sv3_pdata,
         },
@@ -162,17 +165,17 @@ struct platform_device s5pv310_device_i2s2 = {
 
 /* PCM Controller platform_devices */
 
-static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev)
+static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
 {
         switch (pdev->id) {
         case 0:
-                s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 5, S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
                 break;
         case 1:
-                s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
                 break;
         case 2:
-                s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
                 break;
         default:
                 printk(KERN_DEBUG "Invalid PCM Controller number!");
@@ -183,13 +186,13 @@ static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev)
 }
 
 static struct s3c_audio_pdata s3c_pcm_pdata = {
-        .cfg_gpio = s5pv310_pcm_cfg_gpio,
+        .cfg_gpio = exynos4_pcm_cfg_gpio,
 };
 
-static struct resource s5pv310_pcm0_resource[] = {
+static struct resource exynos4_pcm0_resource[] = {
         [0] = {
-                .start  = S5PV310_PA_PCM0,
-                .end    = S5PV310_PA_PCM0 + 0x100 - 1,
+                .start  = EXYNOS4_PA_PCM0,
+                .end    = EXYNOS4_PA_PCM0 + 0x100 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -204,20 +207,20 @@ static struct resource s5pv310_pcm0_resource[] = {
         },
 };
 
-struct platform_device s5pv310_device_pcm0 = {
+struct platform_device exynos4_device_pcm0 = {
         .name = "samsung-pcm",
         .id = 0,
-        .num_resources = ARRAY_SIZE(s5pv310_pcm0_resource),
-        .resource = s5pv310_pcm0_resource,
+        .num_resources = ARRAY_SIZE(exynos4_pcm0_resource),
+        .resource = exynos4_pcm0_resource,
         .dev = {
                 .platform_data = &s3c_pcm_pdata,
         },
 };
 
-static struct resource s5pv310_pcm1_resource[] = {
+static struct resource exynos4_pcm1_resource[] = {
         [0] = {
-                .start  = S5PV310_PA_PCM1,
-                .end    = S5PV310_PA_PCM1 + 0x100 - 1,
+                .start  = EXYNOS4_PA_PCM1,
+                .end    = EXYNOS4_PA_PCM1 + 0x100 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -232,20 +235,20 @@ static struct resource s5pv310_pcm1_resource[] = {
         },
 };
 
-struct platform_device s5pv310_device_pcm1 = {
+struct platform_device exynos4_device_pcm1 = {
         .name = "samsung-pcm",
         .id = 1,
-        .num_resources = ARRAY_SIZE(s5pv310_pcm1_resource),
-        .resource = s5pv310_pcm1_resource,
+        .num_resources = ARRAY_SIZE(exynos4_pcm1_resource),
+        .resource = exynos4_pcm1_resource,
         .dev = {
                 .platform_data = &s3c_pcm_pdata,
         },
 };
 
-static struct resource s5pv310_pcm2_resource[] = {
+static struct resource exynos4_pcm2_resource[] = {
         [0] = {
-                .start  = S5PV310_PA_PCM2,
-                .end    = S5PV310_PA_PCM2 + 0x100 - 1,
+                .start  = EXYNOS4_PA_PCM2,
+                .end    = EXYNOS4_PA_PCM2 + 0x100 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -260,11 +263,11 @@ static struct resource s5pv310_pcm2_resource[] = {
         },
 };
 
-struct platform_device s5pv310_device_pcm2 = {
+struct platform_device exynos4_device_pcm2 = {
         .name = "samsung-pcm",
         .id = 2,
-        .num_resources = ARRAY_SIZE(s5pv310_pcm2_resource),
-        .resource = s5pv310_pcm2_resource,
+        .num_resources = ARRAY_SIZE(exynos4_pcm2_resource),
+        .resource = exynos4_pcm2_resource,
         .dev = {
                 .platform_data = &s3c_pcm_pdata,
         },
@@ -272,15 +275,15 @@ struct platform_device s5pv310_device_pcm2 = {
 
 /* AC97 Controller platform devices */
 
-static int s5pv310_ac97_cfg_gpio(struct platform_device *pdev)
+static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
 {
-        return s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(4));
+        return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
 }
 
-static struct resource s5pv310_ac97_resource[] = {
+static struct resource exynos4_ac97_resource[] = {
         [0] = {
-                .start  = S5PV310_PA_AC97,
-                .end    = S5PV310_PA_AC97 + 0x100 - 1,
+                .start  = EXYNOS4_PA_AC97,
+                .end    = EXYNOS4_PA_AC97 + 0x100 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -306,36 +309,36 @@ static struct resource s5pv310_ac97_resource[] = {
 };
 
 static struct s3c_audio_pdata s3c_ac97_pdata = {
-        .cfg_gpio = s5pv310_ac97_cfg_gpio,
+        .cfg_gpio = exynos4_ac97_cfg_gpio,
 };
 
-static u64 s5pv310_ac97_dmamask = DMA_BIT_MASK(32);
+static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32);
 
-struct platform_device s5pv310_device_ac97 = {
+struct platform_device exynos4_device_ac97 = {
         .name = "samsung-ac97",
         .id = -1,
-        .num_resources = ARRAY_SIZE(s5pv310_ac97_resource),
-        .resource = s5pv310_ac97_resource,
+        .num_resources = ARRAY_SIZE(exynos4_ac97_resource),
+        .resource = exynos4_ac97_resource,
         .dev = {
                 .platform_data = &s3c_ac97_pdata,
-                .dma_mask = &s5pv310_ac97_dmamask,
+                .dma_mask = &exynos4_ac97_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
         },
 };
 
 /* S/PDIF Controller platform_device */
 
-static int s5pv310_spdif_cfg_gpio(struct platform_device *pdev)
+static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
 {
-        s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 2, S3C_GPIO_SFN(3));
+        s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));
 
         return 0;
 }
 
-static struct resource s5pv310_spdif_resource[] = {
+static struct resource exynos4_spdif_resource[] = {
         [0] = {
-                .start  = S5PV310_PA_SPDIF,
-                .end    = S5PV310_PA_SPDIF + 0x100 - 1,
+                .start  = EXYNOS4_PA_SPDIF,
+                .end    = EXYNOS4_PA_SPDIF + 0x100 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -346,19 +349,19 @@ static struct resource s5pv310_spdif_resource[] = {
 };
 
 static struct s3c_audio_pdata samsung_spdif_pdata = {
-        .cfg_gpio = s5pv310_spdif_cfg_gpio,
+        .cfg_gpio = exynos4_spdif_cfg_gpio,
 };
 
-static u64 s5pv310_spdif_dmamask = DMA_BIT_MASK(32);
+static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32);
 
-struct platform_device s5pv310_device_spdif = {
+struct platform_device exynos4_device_spdif = {
         .name = "samsung-spdif",
         .id = -1,
-        .num_resources = ARRAY_SIZE(s5pv310_spdif_resource),
-        .resource = s5pv310_spdif_resource,
+        .num_resources = ARRAY_SIZE(exynos4_spdif_resource),
+        .resource = exynos4_spdif_resource,
         .dev = {
                 .platform_data = &samsung_spdif_pdata,
-                .dma_mask = &s5pv310_spdif_dmamask,
+                .dma_mask = &exynos4_spdif_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
         },
 };
diff --git a/arch/arm/mach-s5pv310/dev-pd.c b/arch/arm/mach-exynos4/dev-pd.c
index 58a50c2d0b67..3273f25d6a75 100644
--- a/arch/arm/mach-s5pv310/dev-pd.c
+++ b/arch/arm/mach-exynos4/dev-pd.c
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5pv310/dev-pd.c
+/* linux/arch/arm/mach-exynos4/dev-pd.c
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * S5PV310 - Power Domain support
+ * EXYNOS4 - Power Domain support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -19,7 +19,7 @@
 
 #include <plat/pd.h>
 
-static int s5pv310_pd_enable(struct device *dev)
+static int exynos4_pd_enable(struct device *dev)
 {
         struct samsung_pd_info *pdata =  dev->platform_data;
         u32 timeout;
@@ -42,7 +42,7 @@ static int s5pv310_pd_enable(struct device *dev)
         return 0;
 }
 
-static int s5pv310_pd_disable(struct device *dev)
+static int exynos4_pd_disable(struct device *dev)
 {
         struct samsung_pd_info *pdata =  dev->platform_data;
         u32 timeout;
@@ -64,14 +64,14 @@ static int s5pv310_pd_disable(struct device *dev)
         return 0;
 }
 
-struct platform_device s5pv310_device_pd[] = {
+struct platform_device exynos4_device_pd[] = {
         {
                 .name           = "samsung-pd",
                 .id             = 0,
                 .dev = {
                         .platform_data = &(struct samsung_pd_info) {
-                                .enable         = s5pv310_pd_enable,
-                                .disable        = s5pv310_pd_disable,
+                                .enable         = exynos4_pd_enable,
+                                .disable        = exynos4_pd_disable,
                                 .base           = S5P_PMU_MFC_CONF,
                         },
                 },
@@ -80,8 +80,8 @@ struct platform_device s5pv310_device_pd[] = {
                 .id             = 1,
                 .dev = {
                         .platform_data = &(struct samsung_pd_info) {
-                                .enable         = s5pv310_pd_enable,
-                                .disable        = s5pv310_pd_disable,
+                                .enable         = exynos4_pd_enable,
+                                .disable        = exynos4_pd_disable,
                                 .base           = S5P_PMU_G3D_CONF,
                         },
                 },
@@ -90,8 +90,8 @@ struct platform_device s5pv310_device_pd[] = {
                 .id             = 2,
                 .dev = {
                         .platform_data = &(struct samsung_pd_info) {
-                                .enable         = s5pv310_pd_enable,
-                                .disable        = s5pv310_pd_disable,
+                                .enable         = exynos4_pd_enable,
+                                .disable        = exynos4_pd_disable,
                                 .base           = S5P_PMU_LCD0_CONF,
                         },
                 },
@@ -100,8 +100,8 @@ struct platform_device s5pv310_device_pd[] = {
                 .id             = 3,
                 .dev = {
                         .platform_data = &(struct samsung_pd_info) {
-                                .enable         = s5pv310_pd_enable,
-                                .disable        = s5pv310_pd_disable,
+                                .enable         = exynos4_pd_enable,
+                                .disable        = exynos4_pd_disable,
                                 .base           = S5P_PMU_LCD1_CONF,
                         },
                 },
@@ -110,8 +110,8 @@ struct platform_device s5pv310_device_pd[] = {
                 .id             = 4,
                 .dev = {
                         .platform_data = &(struct samsung_pd_info) {
-                                .enable         = s5pv310_pd_enable,
-                                .disable        = s5pv310_pd_disable,
+                                .enable         = exynos4_pd_enable,
+                                .disable        = exynos4_pd_disable,
                                 .base           = S5P_PMU_TV_CONF,
                         },
                 },
@@ -120,8 +120,8 @@ struct platform_device s5pv310_device_pd[] = {
                 .id             = 5,
                 .dev = {
                         .platform_data = &(struct samsung_pd_info) {
-                                .enable         = s5pv310_pd_enable,
-                                .disable        = s5pv310_pd_disable,
+                                .enable         = exynos4_pd_enable,
+                                .disable        = exynos4_pd_disable,
                                 .base           = S5P_PMU_CAM_CONF,
                         },
                 },
@@ -130,8 +130,8 @@ struct platform_device s5pv310_device_pd[] = {
                 .id             = 6,
                 .dev = {
                         .platform_data = &(struct samsung_pd_info) {
-                                .enable         = s5pv310_pd_enable,
-                                .disable        = s5pv310_pd_disable,
+                                .enable         = exynos4_pd_enable,
+                                .disable        = exynos4_pd_disable,
                                 .base           = S5P_PMU_GPS_CONF,
                         },
                 },
diff --git a/arch/arm/mach-s5pv310/dev-sysmmu.c b/arch/arm/mach-exynos4/dev-sysmmu.c
index e1bb200ac0f0..3b7cae0fe23e 100644
--- a/arch/arm/mach-s5pv310/dev-sysmmu.c
+++ b/arch/arm/mach-exynos4/dev-sysmmu.c
@@ -1,8 +1,10 @@
-/* linux/arch/arm/mach-s5pv310/dev-sysmmu.c
+/* linux/arch/arm/mach-exynos4/dev-sysmmu.c
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
+ * EXYNOS4 - System MMU support
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
@@ -13,11 +15,33 @@
 
 #include <mach/map.h>
 #include <mach/irqs.h>
+#include <mach/sysmmu.h>
+#include <plat/s5p-clock.h>
+
+/* These names must be equal to the clock names in mach-exynos4/clock.c */
+const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
+        "SYSMMU_MDMA"   ,
+        "SYSMMU_SSS"    ,
+        "SYSMMU_FIMC0"  ,
+        "SYSMMU_FIMC1"  ,
+        "SYSMMU_FIMC2"  ,
+        "SYSMMU_FIMC3"  ,
+        "SYSMMU_JPEG"   ,
+        "SYSMMU_FIMD0"  ,
+        "SYSMMU_FIMD1"  ,
+        "SYSMMU_PCIe"   ,
+        "SYSMMU_G2D"    ,
+        "SYSMMU_ROTATOR",
+        "SYSMMU_MDMA2"  ,
+        "SYSMMU_TV"     ,
+        "SYSMMU_MFC_L"  ,
+        "SYSMMU_MFC_R"  ,
+};
 
-static struct resource s5pv310_sysmmu_resource[] = {
+static struct resource exynos4_sysmmu_resource[] = {
         [0] = {
-                .start  = S5PV310_PA_SYSMMU_MDMA,
-                .end    = S5PV310_PA_SYSMMU_MDMA + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SYSMMU_MDMA,
+                .end    = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -26,8 +50,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         [2] = {
-                .start  = S5PV310_PA_SYSMMU_SSS,
-                .end    = S5PV310_PA_SYSMMU_SSS + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SYSMMU_SSS,
+                .end    = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [3] = {
@@ -36,8 +60,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         [4] = {
-                .start  = S5PV310_PA_SYSMMU_FIMC0,
-                .end    = S5PV310_PA_SYSMMU_FIMC0 + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SYSMMU_FIMC0,
+                .end    = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [5] = {
@@ -46,8 +70,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         [6] = {
-                .start  = S5PV310_PA_SYSMMU_FIMC1,
-                .end    = S5PV310_PA_SYSMMU_FIMC1 + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SYSMMU_FIMC1,
+                .end    = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [7] = {
@@ -56,8 +80,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         [8] = {
-                .start  = S5PV310_PA_SYSMMU_FIMC2,
-                .end    = S5PV310_PA_SYSMMU_FIMC2 + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SYSMMU_FIMC2,
+                .end    = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [9] = {
@@ -66,8 +90,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         [10] = {
-                .start  = S5PV310_PA_SYSMMU_FIMC3,
-                .end    = S5PV310_PA_SYSMMU_FIMC3 + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SYSMMU_FIMC3,
+                .end    = EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [11] = {
@@ -76,8 +100,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         [12] = {
-                .start  = S5PV310_PA_SYSMMU_JPEG,
-                .end    = S5PV310_PA_SYSMMU_JPEG + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SYSMMU_JPEG,
+                .end    = EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [13] = {
@@ -86,8 +110,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         [14] = {
-                .start  = S5PV310_PA_SYSMMU_FIMD0,
-                .end    = S5PV310_PA_SYSMMU_FIMD0 + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SYSMMU_FIMD0,
+                .end    = EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [15] = {
@@ -96,8 +120,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         [16] = {
-                .start  = S5PV310_PA_SYSMMU_FIMD1,
-                .end    = S5PV310_PA_SYSMMU_FIMD1 + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SYSMMU_FIMD1,
+                .end    = EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [17] = {
@@ -106,8 +130,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         [18] = {
-                .start  = S5PV310_PA_SYSMMU_PCIe,
-                .end    = S5PV310_PA_SYSMMU_PCIe + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SYSMMU_PCIe,
+                .end    = EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [19] = {
@@ -116,8 +140,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         [20] = {
-                .start  = S5PV310_PA_SYSMMU_G2D,
-                .end    = S5PV310_PA_SYSMMU_G2D + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SYSMMU_G2D,
+                .end    = EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [21] = {
@@ -126,8 +150,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         [22] = {
-                .start  = S5PV310_PA_SYSMMU_ROTATOR,
-                .end    = S5PV310_PA_SYSMMU_ROTATOR + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SYSMMU_ROTATOR,
+                .end    = EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [23] = {
@@ -136,8 +160,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         [24] = {
-                .start  = S5PV310_PA_SYSMMU_MDMA2,
-                .end    = S5PV310_PA_SYSMMU_MDMA2 + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SYSMMU_MDMA2,
+                .end    = EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [25] = {
@@ -146,8 +170,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         [26] = {
-                .start  = S5PV310_PA_SYSMMU_TV,
-                .end    = S5PV310_PA_SYSMMU_TV + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SYSMMU_TV,
+                .end    = EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [27] = {
@@ -156,8 +180,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         [28] = {
-                .start  = S5PV310_PA_SYSMMU_MFC_L,
-                .end    = S5PV310_PA_SYSMMU_MFC_L + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SYSMMU_MFC_L,
+                .end    = EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [29] = {
@@ -166,8 +190,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
                 .flags  = IORESOURCE_IRQ,
         },
         [30] = {
-                .start  = S5PV310_PA_SYSMMU_MFC_R,
-                .end    = S5PV310_PA_SYSMMU_MFC_R + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SYSMMU_MFC_R,
+                .end    = EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [31] = {
@@ -177,11 +201,32 @@ static struct resource s5pv310_sysmmu_resource[] = {
         },
 };
 
-struct platform_device s5pv310_device_sysmmu = {
+struct platform_device exynos4_device_sysmmu = {
         .name           = "s5p-sysmmu",
         .id             = 32,
-        .num_resources  = ARRAY_SIZE(s5pv310_sysmmu_resource),
-        .resource       = s5pv310_sysmmu_resource,
+        .num_resources  = ARRAY_SIZE(exynos4_sysmmu_resource),
+        .resource       = exynos4_sysmmu_resource,
 };
+EXPORT_SYMBOL(exynos4_device_sysmmu);
+
+static struct clk *sysmmu_clk[S5P_SYSMMU_TOTAL_IPNUM];
+void sysmmu_clk_init(struct device *dev, sysmmu_ips ips)
+{
+        sysmmu_clk[ips] = clk_get(dev, sysmmu_ips_name[ips]);
+        if (IS_ERR(sysmmu_clk[ips]))
+                sysmmu_clk[ips] = NULL;
+        else
+                clk_put(sysmmu_clk[ips]);
+}
+
+void sysmmu_clk_enable(sysmmu_ips ips)
+{
+        if (sysmmu_clk[ips])
+                clk_enable(sysmmu_clk[ips]);
+}
 
-EXPORT_SYMBOL(s5pv310_device_sysmmu);
+void sysmmu_clk_disable(sysmmu_ips ips)
+{
+        if (sysmmu_clk[ips])
+                clk_disable(sysmmu_clk[ips]);
+}
diff --git a/arch/arm/mach-s5pv310/dma.c b/arch/arm/mach-exynos4/dma.c
index 20066c7c9e56..564bb530f332 100644
--- a/arch/arm/mach-s5pv310/dma.c
+++ b/arch/arm/mach-exynos4/dma.c
@@ -1,4 +1,8 @@
-/*
+/* linux/arch/arm/mach-exynos4/dma.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
  *      Jaswinder Singh <jassi.brar@samsung.com>
  *
@@ -30,10 +34,10 @@
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-static struct resource s5pv310_pdma0_resource[] = {
+static struct resource exynos4_pdma0_resource[] = {
         [0] = {
-                .start  = S5PV310_PA_PDMA0,
-                .end    = S5PV310_PA_PDMA0 + SZ_4K,
+                .start  = EXYNOS4_PA_PDMA0,
+                .end    = EXYNOS4_PA_PDMA0 + SZ_4K,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -43,7 +47,7 @@ static struct resource s5pv310_pdma0_resource[] = {
         },
 };
 
-static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
+static struct s3c_pl330_platdata exynos4_pdma0_pdata = {
         .peri = {
                 [0] = DMACH_PCM0_RX,
                 [1] = DMACH_PCM0_TX,
@@ -80,22 +84,22 @@ static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
         },
 };
 
-static struct platform_device s5pv310_device_pdma0 = {
+static struct platform_device exynos4_device_pdma0 = {
         .name           = "s3c-pl330",
         .id             = 0,
-        .num_resources  = ARRAY_SIZE(s5pv310_pdma0_resource),
-        .resource       = s5pv310_pdma0_resource,
+        .num_resources  = ARRAY_SIZE(exynos4_pdma0_resource),
+        .resource       = exynos4_pdma0_resource,
         .dev            = {
                 .dma_mask = &dma_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &s5pv310_pdma0_pdata,
+                .platform_data = &exynos4_pdma0_pdata,
         },
 };
 
-static struct resource s5pv310_pdma1_resource[] = {
+static struct resource exynos4_pdma1_resource[] = {
         [0] = {
-                .start  = S5PV310_PA_PDMA1,
-                .end    = S5PV310_PA_PDMA1 + SZ_4K,
+                .start  = EXYNOS4_PA_PDMA1,
+                .end    = EXYNOS4_PA_PDMA1 + SZ_4K,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -105,7 +109,7 @@ static struct resource s5pv310_pdma1_resource[] = {
         },
 };
 
-static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
+static struct s3c_pl330_platdata exynos4_pdma1_pdata = {
         .peri = {
                 [0] = DMACH_PCM0_RX,
                 [1] = DMACH_PCM0_TX,
@@ -142,27 +146,27 @@ static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
         },
 };
 
-static struct platform_device s5pv310_device_pdma1 = {
+static struct platform_device exynos4_device_pdma1 = {
         .name           = "s3c-pl330",
         .id             = 1,
-        .num_resources  = ARRAY_SIZE(s5pv310_pdma1_resource),
-        .resource       = s5pv310_pdma1_resource,
+        .num_resources  = ARRAY_SIZE(exynos4_pdma1_resource),
+        .resource       = exynos4_pdma1_resource,
         .dev            = {
                 .dma_mask = &dma_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &s5pv310_pdma1_pdata,
+                .platform_data = &exynos4_pdma1_pdata,
         },
 };
 
-static struct platform_device *s5pv310_dmacs[] __initdata = {
-        &s5pv310_device_pdma0,
-        &s5pv310_device_pdma1,
+static struct platform_device *exynos4_dmacs[] __initdata = {
+        &exynos4_device_pdma0,
+        &exynos4_device_pdma1,
 };
 
-static int __init s5pv310_dma_init(void)
+static int __init exynos4_dma_init(void)
 {
-        platform_add_devices(s5pv310_dmacs, ARRAY_SIZE(s5pv310_dmacs));
+        platform_add_devices(exynos4_dmacs, ARRAY_SIZE(exynos4_dmacs));
 
         return 0;
 }
-arch_initcall(s5pv310_dma_init);
+arch_initcall(exynos4_dma_init);
diff --git a/arch/arm/mach-exynos4/gpiolib.c b/arch/arm/mach-exynos4/gpiolib.c
new file mode 100644
index 000000000000..d54ca6adb660
--- /dev/null
+++ b/arch/arm/mach-exynos4/gpiolib.c
@@ -0,0 +1,365 @@
+/* linux/arch/arm/mach-exynos4/gpiolib.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4 - GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/map.h>
+
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+
+static struct s3c_gpio_cfg gpio_cfg = {
+        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .set_pull       = s3c_gpio_setpull_updown,
+        .get_pull       = s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_cfg gpio_cfg_noint = {
+        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .set_pull       = s3c_gpio_setpull_updown,
+        .get_pull       = s3c_gpio_getpull_updown,
+};
+
+/*
+ * Following are the gpio banks in v310.
+ *
+ * The 'config' member when left to NULL, is initialized to the default
+ * structure gpio_cfg in the init function below.
+ *
+ * The 'base' member is also initialized in the init function below.
+ * Note: The initialization of 'base' member of s3c_gpio_chip structure
+ * uses the above macro and depends on the banks being listed in order here.
+ */
+static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {
+        {
+                .chip   = {
+                        .base   = EXYNOS4_GPA0(0),
+                        .ngpio  = EXYNOS4_GPIO_A0_NR,
+                        .label  = "GPA0",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPA1(0),
+                        .ngpio  = EXYNOS4_GPIO_A1_NR,
+                        .label  = "GPA1",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPB(0),
+                        .ngpio  = EXYNOS4_GPIO_B_NR,
+                        .label  = "GPB",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPC0(0),
+                        .ngpio  = EXYNOS4_GPIO_C0_NR,
+                        .label  = "GPC0",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPC1(0),
+                        .ngpio  = EXYNOS4_GPIO_C1_NR,
+                        .label  = "GPC1",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPD0(0),
+                        .ngpio  = EXYNOS4_GPIO_D0_NR,
+                        .label  = "GPD0",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPD1(0),
+                        .ngpio  = EXYNOS4_GPIO_D1_NR,
+                        .label  = "GPD1",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPE0(0),
+                        .ngpio  = EXYNOS4_GPIO_E0_NR,
+                        .label  = "GPE0",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPE1(0),
+                        .ngpio  = EXYNOS4_GPIO_E1_NR,
+                        .label  = "GPE1",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPE2(0),
+                        .ngpio  = EXYNOS4_GPIO_E2_NR,
+                        .label  = "GPE2",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPE3(0),
+                        .ngpio  = EXYNOS4_GPIO_E3_NR,
+                        .label  = "GPE3",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPE4(0),
+                        .ngpio  = EXYNOS4_GPIO_E4_NR,
+                        .label  = "GPE4",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPF0(0),
+                        .ngpio  = EXYNOS4_GPIO_F0_NR,
+                        .label  = "GPF0",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPF1(0),
+                        .ngpio  = EXYNOS4_GPIO_F1_NR,
+                        .label  = "GPF1",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPF2(0),
+                        .ngpio  = EXYNOS4_GPIO_F2_NR,
+                        .label  = "GPF2",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPF3(0),
+                        .ngpio  = EXYNOS4_GPIO_F3_NR,
+                        .label  = "GPF3",
+                },
+        },
+};
+
+static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
+        {
+                .chip   = {
+                        .base   = EXYNOS4_GPJ0(0),
+                        .ngpio  = EXYNOS4_GPIO_J0_NR,
+                        .label  = "GPJ0",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPJ1(0),
+                        .ngpio  = EXYNOS4_GPIO_J1_NR,
+                        .label  = "GPJ1",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPK0(0),
+                        .ngpio  = EXYNOS4_GPIO_K0_NR,
+                        .label  = "GPK0",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPK1(0),
+                        .ngpio  = EXYNOS4_GPIO_K1_NR,
+                        .label  = "GPK1",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPK2(0),
+                        .ngpio  = EXYNOS4_GPIO_K2_NR,
+                        .label  = "GPK2",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPK3(0),
+                        .ngpio  = EXYNOS4_GPIO_K3_NR,
+                        .label  = "GPK3",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPL0(0),
+                        .ngpio  = EXYNOS4_GPIO_L0_NR,
+                        .label  = "GPL0",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPL1(0),
+                        .ngpio  = EXYNOS4_GPIO_L1_NR,
+                        .label  = "GPL1",
+                },
+        }, {
+                .chip   = {
+                        .base   = EXYNOS4_GPL2(0),
+                        .ngpio  = EXYNOS4_GPIO_L2_NR,
+                        .label  = "GPL2",
+                },
+        }, {
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = EXYNOS4_GPY0(0),
+                        .ngpio  = EXYNOS4_GPIO_Y0_NR,
+                        .label  = "GPY0",
+                },
+        }, {
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = EXYNOS4_GPY1(0),
+                        .ngpio  = EXYNOS4_GPIO_Y1_NR,
+                        .label  = "GPY1",
+                },
+        }, {
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = EXYNOS4_GPY2(0),
+                        .ngpio  = EXYNOS4_GPIO_Y2_NR,
+                        .label  = "GPY2",
+                },
+        }, {
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = EXYNOS4_GPY3(0),
+                        .ngpio  = EXYNOS4_GPIO_Y3_NR,
+                        .label  = "GPY3",
+                },
+        }, {
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = EXYNOS4_GPY4(0),
+                        .ngpio  = EXYNOS4_GPIO_Y4_NR,
+                        .label  = "GPY4",
+                },
+        }, {
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = EXYNOS4_GPY5(0),
+                        .ngpio  = EXYNOS4_GPIO_Y5_NR,
+                        .label  = "GPY5",
+                },
+        }, {
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = EXYNOS4_GPY6(0),
+                        .ngpio  = EXYNOS4_GPIO_Y6_NR,
+                        .label  = "GPY6",
+                },
+        }, {
+                .base   = (S5P_VA_GPIO2 + 0xC00),
+                .config = &gpio_cfg_noint,
+                .irq_base = IRQ_EINT(0),
+                .chip   = {
+                        .base   = EXYNOS4_GPX0(0),
+                        .ngpio  = EXYNOS4_GPIO_X0_NR,
+                        .label  = "GPX0",
+                        .to_irq = samsung_gpiolib_to_irq,
+                },
+        }, {
+                .base   = (S5P_VA_GPIO2 + 0xC20),
+                .config = &gpio_cfg_noint,
+                .irq_base = IRQ_EINT(8),
+                .chip   = {
+                        .base   = EXYNOS4_GPX1(0),
+                        .ngpio  = EXYNOS4_GPIO_X1_NR,
+                        .label  = "GPX1",
+                        .to_irq = samsung_gpiolib_to_irq,
+                },
+        }, {
+                .base   = (S5P_VA_GPIO2 + 0xC40),
+                .config = &gpio_cfg_noint,
+                .irq_base = IRQ_EINT(16),
+                .chip   = {
+                        .base   = EXYNOS4_GPX2(0),
+                        .ngpio  = EXYNOS4_GPIO_X2_NR,
+                        .label  = "GPX2",
+                        .to_irq = samsung_gpiolib_to_irq,
+                },
+        }, {
+                .base   = (S5P_VA_GPIO2 + 0xC60),
+                .config = &gpio_cfg_noint,
+                .irq_base = IRQ_EINT(24),
+                .chip   = {
+                        .base   = EXYNOS4_GPX3(0),
+                        .ngpio  = EXYNOS4_GPIO_X3_NR,
+                        .label  = "GPX3",
+                        .to_irq = samsung_gpiolib_to_irq,
+                },
+        },
+};
+
+static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {
+        {
+                .chip   = {
+                        .base   = EXYNOS4_GPZ(0),
+                        .ngpio  = EXYNOS4_GPIO_Z_NR,
+                        .label  = "GPZ",
+                },
+        },
+};
+
+static __init int exynos4_gpiolib_init(void)
+{
+        struct s3c_gpio_chip *chip;
+        int i;
+        int group = 0;
+        int nr_chips;
+
+        /* GPIO part 1 */
+
+        chip = exynos4_gpio_part1_4bit;
+        nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
+
+        for (i = 0; i < nr_chips; i++, chip++) {
+                if (chip->config == NULL) {
+                        chip->config = &gpio_cfg;
+                        /* Assign the GPIO interrupt group */
+                        chip->group = group++;
+                }
+                if (chip->base == NULL)
+                        chip->base = S5P_VA_GPIO1 + (i) * 0x20;
+        }
+
+        samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);
+
+        /* GPIO part 2 */
+
+        chip = exynos4_gpio_part2_4bit;
+        nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
+
+        for (i = 0; i < nr_chips; i++, chip++) {
+                if (chip->config == NULL) {
+                        chip->config = &gpio_cfg;
+                        /* Assign the GPIO interrupt group */
+                        chip->group = group++;
+                }
+                if (chip->base == NULL)
+                        chip->base = S5P_VA_GPIO2 + (i) * 0x20;
+        }
+
+        samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);
+
+        /* GPIO part 3 */
+
+        chip = exynos4_gpio_part3_4bit;
+        nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
+
+        for (i = 0; i < nr_chips; i++, chip++) {
+                if (chip->config == NULL) {
+                        chip->config = &gpio_cfg;
+                        /* Assign the GPIO interrupt group */
+                        chip->group = group++;
+                }
+                if (chip->base == NULL)
+                        chip->base = S5P_VA_GPIO3 + (i) * 0x20;
+        }
+
+        samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
+        s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
+        s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
+
+        return 0;
+}
+core_initcall(exynos4_gpiolib_init);
diff --git a/arch/arm/mach-s5pv310/headsmp.S b/arch/arm/mach-exynos4/headsmp.S
index 164b7b045713..6c6cfc50c46b 100644
--- a/arch/arm/mach-s5pv310/headsmp.S
+++ b/arch/arm/mach-exynos4/headsmp.S
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/mach-s5pv310/headsmp.S
+ *  linux/arch/arm/mach-exynos4/headsmp.S
  *
  *  Cloned from linux/arch/arm/mach-realview/headsmp.S
  *
@@ -16,11 +16,11 @@
         __INIT
 
 /*
- * s5pv310 specific entry point for secondary CPUs.  This provides
+ * exynos4 specific entry point for secondary CPUs.  This provides
  * a "holding pen" into which all secondary cores are held until we're
  * ready for them to initialise.
  */
-ENTRY(s5pv310_secondary_startup)
+ENTRY(exynos4_secondary_startup)
         mrc     p15, 0, r0, c0, c0, 5
         and     r0, r0, #15
         adr     r4, 1f
diff --git a/arch/arm/mach-s5pv310/hotplug.c b/arch/arm/mach-exynos4/hotplug.c
index c24235c89eed..2b5909e2ccd3 100644
--- a/arch/arm/mach-s5pv310/hotplug.c
+++ b/arch/arm/mach-exynos4/hotplug.c
@@ -1,4 +1,4 @@
-/* linux arch/arm/mach-s5pv310/hotplug.c
+/* linux arch/arm/mach-exynos4/hotplug.c
  *
  *  Cloned from linux/arch/arm/mach-realview/hotplug.c
  *
@@ -30,13 +30,13 @@ static inline void cpu_enter_lowpower(void)
          * Turn off coherency
          */
         "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       bic     %0, %0, #0x20\n"
+        "       bic     %0, %0, %3\n"
         "       mcr     p15, 0, %0, c1, c0, 1\n"
         "       mrc     p15, 0, %0, c1, c0, 0\n"
         "       bic     %0, %0, %2\n"
         "       mcr     p15, 0, %0, c1, c0, 0\n"
           : "=&r" (v)
-          : "r" (0), "Ir" (CR_C)
+          : "r" (0), "Ir" (CR_C), "Ir" (0x40)
           : "cc");
 }
 
@@ -49,10 +49,10 @@ static inline void cpu_leave_lowpower(void)
         "       orr     %0, %0, %1\n"
         "       mcr     p15, 0, %0, c1, c0, 0\n"
         "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       orr     %0, %0, #0x20\n"
+        "       orr     %0, %0, %2\n"
         "       mcr     p15, 0, %0, c1, c0, 1\n"
           : "=&r" (v)
-          : "Ir" (CR_C)
+          : "Ir" (CR_C), "Ir" (0x40)
           : "cc");
 }
 
diff --git a/arch/arm/mach-s5pv310/include/mach/debug-macro.S b/arch/arm/mach-exynos4/include/mach/debug-macro.S
index b0d920c474d3..58bbd049a6c4 100644
--- a/arch/arm/mach-s5pv310/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/debug-macro.S
@@ -1,7 +1,7 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/debug-macro.S
+/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
  *
diff --git a/arch/arm/mach-s5pv310/include/mach/dma.h b/arch/arm/mach-exynos4/include/mach/dma.h
index 81209eb1409b..81209eb1409b 100644
--- a/arch/arm/mach-s5pv310/include/mach/dma.h
+++ b/arch/arm/mach-exynos4/include/mach/dma.h
diff --git a/arch/arm/mach-s5pv310/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index e600e1d522df..d8f38c2e5654 100644
--- a/arch/arm/mach-s5pv310/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -1,8 +1,8 @@
-/* arch/arm/mach-s5pv310/include/mach/entry-macro.S
+/* arch/arm/mach-exynos4/include/mach/entry-macro.S
  *
  * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
  *
- * Low-level IRQ helper macros for S5PV310 platforms
+ * Low-level IRQ helper macros for EXYNOS4 platforms
  *
  * This file is licensed under  the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
diff --git a/arch/arm/mach-exynos4/include/mach/gpio.h b/arch/arm/mach-exynos4/include/mach/gpio.h
new file mode 100644
index 000000000000..939728b38d48
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/gpio.h
@@ -0,0 +1,156 @@
+/* linux/arch/arm/mach-exynos4/include/mach/gpio.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4 - GPIO lib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H __FILE__
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+
+/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
+
+/* GPIO bank sizes */
+#define EXYNOS4_GPIO_A0_NR      (8)
+#define EXYNOS4_GPIO_A1_NR      (6)
+#define EXYNOS4_GPIO_B_NR       (8)
+#define EXYNOS4_GPIO_C0_NR      (5)
+#define EXYNOS4_GPIO_C1_NR      (5)
+#define EXYNOS4_GPIO_D0_NR      (4)
+#define EXYNOS4_GPIO_D1_NR      (4)
+#define EXYNOS4_GPIO_E0_NR      (5)
+#define EXYNOS4_GPIO_E1_NR      (8)
+#define EXYNOS4_GPIO_E2_NR      (6)
+#define EXYNOS4_GPIO_E3_NR      (8)
+#define EXYNOS4_GPIO_E4_NR      (8)
+#define EXYNOS4_GPIO_F0_NR      (8)
+#define EXYNOS4_GPIO_F1_NR      (8)
+#define EXYNOS4_GPIO_F2_NR      (8)
+#define EXYNOS4_GPIO_F3_NR      (6)
+#define EXYNOS4_GPIO_J0_NR      (8)
+#define EXYNOS4_GPIO_J1_NR      (5)
+#define EXYNOS4_GPIO_K0_NR      (7)
+#define EXYNOS4_GPIO_K1_NR      (7)
+#define EXYNOS4_GPIO_K2_NR      (7)
+#define EXYNOS4_GPIO_K3_NR      (7)
+#define EXYNOS4_GPIO_L0_NR      (8)
+#define EXYNOS4_GPIO_L1_NR      (3)
+#define EXYNOS4_GPIO_L2_NR      (8)
+#define EXYNOS4_GPIO_X0_NR      (8)
+#define EXYNOS4_GPIO_X1_NR      (8)
+#define EXYNOS4_GPIO_X2_NR      (8)
+#define EXYNOS4_GPIO_X3_NR      (8)
+#define EXYNOS4_GPIO_Y0_NR      (6)
+#define EXYNOS4_GPIO_Y1_NR      (4)
+#define EXYNOS4_GPIO_Y2_NR      (6)
+#define EXYNOS4_GPIO_Y3_NR      (8)
+#define EXYNOS4_GPIO_Y4_NR      (8)
+#define EXYNOS4_GPIO_Y5_NR      (8)
+#define EXYNOS4_GPIO_Y6_NR      (8)
+#define EXYNOS4_GPIO_Z_NR       (7)
+
+/* GPIO bank numbers */
+
+#define EXYNOS4_GPIO_NEXT(__gpio) \
+        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+
+enum s5p_gpio_number {
+        EXYNOS4_GPIO_A0_START   = 0,
+        EXYNOS4_GPIO_A1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0),
+        EXYNOS4_GPIO_B_START    = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1),
+        EXYNOS4_GPIO_C0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B),
+        EXYNOS4_GPIO_C1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0),
+        EXYNOS4_GPIO_D0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1),
+        EXYNOS4_GPIO_D1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0),
+        EXYNOS4_GPIO_E0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1),
+        EXYNOS4_GPIO_E1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E0),
+        EXYNOS4_GPIO_E2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E1),
+        EXYNOS4_GPIO_E3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E2),
+        EXYNOS4_GPIO_E4_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E3),
+        EXYNOS4_GPIO_F0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E4),
+        EXYNOS4_GPIO_F1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0),
+        EXYNOS4_GPIO_F2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1),
+        EXYNOS4_GPIO_F3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2),
+        EXYNOS4_GPIO_J0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3),
+        EXYNOS4_GPIO_J1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J0),
+        EXYNOS4_GPIO_K0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J1),
+        EXYNOS4_GPIO_K1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0),
+        EXYNOS4_GPIO_K2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1),
+        EXYNOS4_GPIO_K3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2),
+        EXYNOS4_GPIO_L0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3),
+        EXYNOS4_GPIO_L1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0),
+        EXYNOS4_GPIO_L2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1),
+        EXYNOS4_GPIO_X0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2),
+        EXYNOS4_GPIO_X1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0),
+        EXYNOS4_GPIO_X2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1),
+        EXYNOS4_GPIO_X3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2),
+        EXYNOS4_GPIO_Y0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3),
+        EXYNOS4_GPIO_Y1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y0),
+        EXYNOS4_GPIO_Y2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y1),
+        EXYNOS4_GPIO_Y3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y2),
+        EXYNOS4_GPIO_Y4_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y3),
+        EXYNOS4_GPIO_Y5_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y4),
+        EXYNOS4_GPIO_Y6_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y5),
+        EXYNOS4_GPIO_Z_START    = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y6),
+};
+
+/* EXYNOS4 GPIO number definitions */
+#define EXYNOS4_GPA0(_nr)       (EXYNOS4_GPIO_A0_START + (_nr))
+#define EXYNOS4_GPA1(_nr)       (EXYNOS4_GPIO_A1_START + (_nr))
+#define EXYNOS4_GPB(_nr)        (EXYNOS4_GPIO_B_START + (_nr))
+#define EXYNOS4_GPC0(_nr)       (EXYNOS4_GPIO_C0_START + (_nr))
+#define EXYNOS4_GPC1(_nr)       (EXYNOS4_GPIO_C1_START + (_nr))
+#define EXYNOS4_GPD0(_nr)       (EXYNOS4_GPIO_D0_START + (_nr))
+#define EXYNOS4_GPD1(_nr)       (EXYNOS4_GPIO_D1_START + (_nr))
+#define EXYNOS4_GPE0(_nr)       (EXYNOS4_GPIO_E0_START + (_nr))
+#define EXYNOS4_GPE1(_nr)       (EXYNOS4_GPIO_E1_START + (_nr))
+#define EXYNOS4_GPE2(_nr)       (EXYNOS4_GPIO_E2_START + (_nr))
+#define EXYNOS4_GPE3(_nr)       (EXYNOS4_GPIO_E3_START + (_nr))
+#define EXYNOS4_GPE4(_nr)       (EXYNOS4_GPIO_E4_START + (_nr))
+#define EXYNOS4_GPF0(_nr)       (EXYNOS4_GPIO_F0_START + (_nr))
+#define EXYNOS4_GPF1(_nr)       (EXYNOS4_GPIO_F1_START + (_nr))
+#define EXYNOS4_GPF2(_nr)       (EXYNOS4_GPIO_F2_START + (_nr))
+#define EXYNOS4_GPF3(_nr)       (EXYNOS4_GPIO_F3_START + (_nr))
+#define EXYNOS4_GPJ0(_nr)       (EXYNOS4_GPIO_J0_START + (_nr))
+#define EXYNOS4_GPJ1(_nr)       (EXYNOS4_GPIO_J1_START + (_nr))
+#define EXYNOS4_GPK0(_nr)       (EXYNOS4_GPIO_K0_START + (_nr))
+#define EXYNOS4_GPK1(_nr)       (EXYNOS4_GPIO_K1_START + (_nr))
+#define EXYNOS4_GPK2(_nr)       (EXYNOS4_GPIO_K2_START + (_nr))
+#define EXYNOS4_GPK3(_nr)       (EXYNOS4_GPIO_K3_START + (_nr))
+#define EXYNOS4_GPL0(_nr)       (EXYNOS4_GPIO_L0_START + (_nr))
+#define EXYNOS4_GPL1(_nr)       (EXYNOS4_GPIO_L1_START + (_nr))
+#define EXYNOS4_GPL2(_nr)       (EXYNOS4_GPIO_L2_START + (_nr))
+#define EXYNOS4_GPX0(_nr)       (EXYNOS4_GPIO_X0_START + (_nr))
+#define EXYNOS4_GPX1(_nr)       (EXYNOS4_GPIO_X1_START + (_nr))
+#define EXYNOS4_GPX2(_nr)       (EXYNOS4_GPIO_X2_START + (_nr))
+#define EXYNOS4_GPX3(_nr)       (EXYNOS4_GPIO_X3_START + (_nr))
+#define EXYNOS4_GPY0(_nr)       (EXYNOS4_GPIO_Y0_START + (_nr))
+#define EXYNOS4_GPY1(_nr)       (EXYNOS4_GPIO_Y1_START + (_nr))
+#define EXYNOS4_GPY2(_nr)       (EXYNOS4_GPIO_Y2_START + (_nr))
+#define EXYNOS4_GPY3(_nr)       (EXYNOS4_GPIO_Y3_START + (_nr))
+#define EXYNOS4_GPY4(_nr)       (EXYNOS4_GPIO_Y4_START + (_nr))
+#define EXYNOS4_GPY5(_nr)       (EXYNOS4_GPIO_Y5_START + (_nr))
+#define EXYNOS4_GPY6(_nr)       (EXYNOS4_GPIO_Y6_START + (_nr))
+#define EXYNOS4_GPZ(_nr)        (EXYNOS4_GPIO_Z_START + (_nr))
+
+/* the end of the EXYNOS4 specific gpios */
+#define EXYNOS4_GPIO_END        (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
+#define S3C_GPIO_END            EXYNOS4_GPIO_END
+
+/* define the number of gpios we need to the one after the GPZ() range */
+#define ARCH_NR_GPIOS           (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) +       \
+                                 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
+
+#include <asm-generic/gpio.h>
+
+#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/hardware.h b/arch/arm/mach-exynos4/include/mach/hardware.h
index 28ff9881f1a6..5109eb232f23 100644
--- a/arch/arm/mach-s5pv310/include/mach/hardware.h
+++ b/arch/arm/mach-exynos4/include/mach/hardware.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/hardware.h
+/* linux/arch/arm/mach-exynos4/include/mach/hardware.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5PV310 - Hardware support
+ * EXYNOS4 - Hardware support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/io.h b/arch/arm/mach-exynos4/include/mach/io.h
index 8a7f9128391f..d5478d247535 100644
--- a/arch/arm/mach-s5pv310/include/mach/io.h
+++ b/arch/arm/mach-exynos4/include/mach/io.h
@@ -1,13 +1,13 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/io.h
+/* linux/arch/arm/mach-exynos4/include/mach/io.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
  *
  * Based on arch/arm/mach-s5p6442/include/mach/io.h
  *
- * Default IO routines for S5PV310
+ * Default IO routines for EXYNOS4
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index 536b0b59fc83..5d037301d21a 100644
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/irqs.h
+/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5PV310 - IRQ definitions
+ * EXYNOS4 - IRQ definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -85,6 +85,9 @@
 #define IRQ_RTC_ALARM           COMBINER_IRQ(23, 0)
 #define IRQ_RTC_TIC             COMBINER_IRQ(23, 1)
 
+#define IRQ_GPIO_XB             COMBINER_IRQ(24, 0)
+#define IRQ_GPIO_XA             COMBINER_IRQ(24, 1)
+
 #define IRQ_UART0               COMBINER_IRQ(26, 0)
 #define IRQ_UART1               COMBINER_IRQ(26, 1)
 #define IRQ_UART2               COMBINER_IRQ(26, 2)
@@ -108,6 +111,11 @@
 #define IRQ_MIPI_CSIS0          COMBINER_IRQ(30, 0)
 #define IRQ_MIPI_CSIS1          COMBINER_IRQ(30, 1)
 
+#define IRQ_FIMC0               COMBINER_IRQ(32, 0)
+#define IRQ_FIMC1               COMBINER_IRQ(32, 1)
+#define IRQ_FIMC2               COMBINER_IRQ(33, 0)
+#define IRQ_FIMC3               COMBINER_IRQ(33, 1)
+
 #define IRQ_ONENAND_AUDI        COMBINER_IRQ(34, 0)
 
 #define IRQ_MCT_L1              COMBINER_IRQ(35, 3)
@@ -131,6 +139,7 @@
 #define IRQ_MCT_L0              COMBINER_IRQ(51, 0)
 
 #define IRQ_WDT                 COMBINER_IRQ(53, 0)
+#define IRQ_MCT_G0              COMBINER_IRQ(53, 4)
 
 #define MAX_COMBINER_NR         54
 
@@ -139,8 +148,13 @@
 #define S5P_EINT_BASE1          (S5P_IRQ_EINT_BASE + 0)
 #define S5P_EINT_BASE2          (S5P_IRQ_EINT_BASE + 16)
 
-/* Set the default NR_IRQS */
+/* optional GPIO interrupts */
+#define S5P_GPIOINT_BASE        (S5P_IRQ_EINT_BASE + 32)
+#define IRQ_GPIO1_NR_GROUPS     16
+#define IRQ_GPIO2_NR_GROUPS     9
+#define IRQ_GPIO_END            (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
 
-#define NR_IRQS                 (S5P_IRQ_EINT_BASE + 32)
+/* Set the default NR_IRQS */
+#define NR_IRQS                 (IRQ_GPIO_END)
 
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
new file mode 100644
index 000000000000..6330b73b9ea7
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -0,0 +1,162 @@
+/* linux/arch/arm/mach-exynos4/include/mach/map.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * EXYNOS4 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H __FILE__
+
+#include <plat/map-base.h>
+
+/*
+ * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
+ * So need to define it, and here is to avoid redefinition warning.
+ */
+#define S3C_UART_OFFSET                 (0x10000)
+
+#include <plat/map-s5p.h>
+
+#define EXYNOS4_PA_SYSRAM               0x02020000
+
+#define EXYNOS4_PA_FIMC0                0x11800000
+#define EXYNOS4_PA_FIMC1                0x11810000
+#define EXYNOS4_PA_FIMC2                0x11820000
+#define EXYNOS4_PA_FIMC3                0x11830000
+
+#define EXYNOS4_PA_I2S0                 0x03830000
+#define EXYNOS4_PA_I2S1                 0xE3100000
+#define EXYNOS4_PA_I2S2                 0xE2A00000
+
+#define EXYNOS4_PA_PCM0                 0x03840000
+#define EXYNOS4_PA_PCM1                 0x13980000
+#define EXYNOS4_PA_PCM2                 0x13990000
+
+#define EXYNOS4_PA_SROM_BANK(x)         (0x04000000 + ((x) * 0x01000000))
+
+#define EXYNOS4_PA_ONENAND              0x0C000000
+#define EXYNOS4_PA_ONENAND_DMA          0x0C600000
+
+#define EXYNOS4_PA_CHIPID               0x10000000
+
+#define EXYNOS4_PA_SYSCON               0x10010000
+#define EXYNOS4_PA_PMU                  0x10020000
+#define EXYNOS4_PA_CMU                  0x10030000
+
+#define EXYNOS4_PA_SYSTIMER             0x10050000
+#define EXYNOS4_PA_WATCHDOG             0x10060000
+#define EXYNOS4_PA_RTC                  0x10070000
+
+#define EXYNOS4_PA_KEYPAD               0x100A0000
+
+#define EXYNOS4_PA_DMC0                 0x10400000
+
+#define EXYNOS4_PA_COMBINER             0x10448000
+
+#define EXYNOS4_PA_COREPERI             0x10500000
+#define EXYNOS4_PA_GIC_CPU              0x10500100
+#define EXYNOS4_PA_TWD                  0x10500600
+#define EXYNOS4_PA_GIC_DIST             0x10501000
+#define EXYNOS4_PA_L2CC                 0x10502000
+
+#define EXYNOS4_PA_MDMA                 0x10810000
+#define EXYNOS4_PA_PDMA0                0x12680000
+#define EXYNOS4_PA_PDMA1                0x12690000
+
+#define EXYNOS4_PA_SYSMMU_MDMA          0x10A40000
+#define EXYNOS4_PA_SYSMMU_SSS           0x10A50000
+#define EXYNOS4_PA_SYSMMU_FIMC0         0x11A20000
+#define EXYNOS4_PA_SYSMMU_FIMC1         0x11A30000
+#define EXYNOS4_PA_SYSMMU_FIMC2         0x11A40000
+#define EXYNOS4_PA_SYSMMU_FIMC3         0x11A50000
+#define EXYNOS4_PA_SYSMMU_JPEG          0x11A60000
+#define EXYNOS4_PA_SYSMMU_FIMD0         0x11E20000
+#define EXYNOS4_PA_SYSMMU_FIMD1         0x12220000
+#define EXYNOS4_PA_SYSMMU_PCIe          0x12620000
+#define EXYNOS4_PA_SYSMMU_G2D           0x12A20000
+#define EXYNOS4_PA_SYSMMU_ROTATOR       0x12A30000
+#define EXYNOS4_PA_SYSMMU_MDMA2         0x12A40000
+#define EXYNOS4_PA_SYSMMU_TV            0x12E20000
+#define EXYNOS4_PA_SYSMMU_MFC_L         0x13620000
+#define EXYNOS4_PA_SYSMMU_MFC_R         0x13630000
+
+#define EXYNOS4_PA_GPIO1                0x11400000
+#define EXYNOS4_PA_GPIO2                0x11000000
+#define EXYNOS4_PA_GPIO3                0x03860000
+
+#define EXYNOS4_PA_MIPI_CSIS0           0x11880000
+#define EXYNOS4_PA_MIPI_CSIS1           0x11890000
+
+#define EXYNOS4_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
+
+#define EXYNOS4_PA_SATA                 0x12560000
+#define EXYNOS4_PA_SATAPHY              0x125D0000
+#define EXYNOS4_PA_SATAPHY_CTRL         0x126B0000
+
+#define EXYNOS4_PA_SROMC                0x12570000
+
+#define EXYNOS4_PA_UART                 0x13800000
+
+#define EXYNOS4_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
+
+#define EXYNOS4_PA_AC97                 0x139A0000
+
+#define EXYNOS4_PA_SPDIF                0x139B0000
+
+#define EXYNOS4_PA_TIMER                0x139D0000
+
+#define EXYNOS4_PA_SDRAM                0x40000000
+
+/* Compatibiltiy Defines */
+
+#define S3C_PA_HSMMC0                   EXYNOS4_PA_HSMMC(0)
+#define S3C_PA_HSMMC1                   EXYNOS4_PA_HSMMC(1)
+#define S3C_PA_HSMMC2                   EXYNOS4_PA_HSMMC(2)
+#define S3C_PA_HSMMC3                   EXYNOS4_PA_HSMMC(3)
+#define S3C_PA_IIC                      EXYNOS4_PA_IIC(0)
+#define S3C_PA_IIC1                     EXYNOS4_PA_IIC(1)
+#define S3C_PA_IIC2                     EXYNOS4_PA_IIC(2)
+#define S3C_PA_IIC3                     EXYNOS4_PA_IIC(3)
+#define S3C_PA_IIC4                     EXYNOS4_PA_IIC(4)
+#define S3C_PA_IIC5                     EXYNOS4_PA_IIC(5)
+#define S3C_PA_IIC6                     EXYNOS4_PA_IIC(6)
+#define S3C_PA_IIC7                     EXYNOS4_PA_IIC(7)
+#define S3C_PA_RTC                      EXYNOS4_PA_RTC
+#define S3C_PA_WDT                      EXYNOS4_PA_WATCHDOG
+
+#define S5P_PA_CHIPID                   EXYNOS4_PA_CHIPID
+#define S5P_PA_FIMC0                    EXYNOS4_PA_FIMC0
+#define S5P_PA_FIMC1                    EXYNOS4_PA_FIMC1
+#define S5P_PA_FIMC2                    EXYNOS4_PA_FIMC2
+#define S5P_PA_FIMC3                    EXYNOS4_PA_FIMC3
+#define S5P_PA_MIPI_CSIS0               EXYNOS4_PA_MIPI_CSIS0
+#define S5P_PA_MIPI_CSIS1               EXYNOS4_PA_MIPI_CSIS1
+#define S5P_PA_ONENAND                  EXYNOS4_PA_ONENAND
+#define S5P_PA_ONENAND_DMA              EXYNOS4_PA_ONENAND_DMA
+#define S5P_PA_SDRAM                    EXYNOS4_PA_SDRAM
+#define S5P_PA_SROMC                    EXYNOS4_PA_SROMC
+#define S5P_PA_SYSCON                   EXYNOS4_PA_SYSCON
+#define S5P_PA_TIMER                    EXYNOS4_PA_TIMER
+
+#define SAMSUNG_PA_KEYPAD               EXYNOS4_PA_KEYPAD
+
+/* UART */
+
+#define S3C_PA_UART                     EXYNOS4_PA_UART
+
+#define S5P_PA_UART(x)                  (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0                    S5P_PA_UART(0)
+#define S5P_PA_UART1                    S5P_PA_UART(1)
+#define S5P_PA_UART2                    S5P_PA_UART(2)
+#define S5P_PA_UART3                    S5P_PA_UART(3)
+#define S5P_PA_UART4                    S5P_PA_UART(4)
+
+#define S5P_SZ_UART                     SZ_256
+
+#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/memory.h b/arch/arm/mach-exynos4/include/mach/memory.h
index 470b01bf8614..374ef2cf7152 100644
--- a/arch/arm/mach-s5pv310/include/mach/memory.h
+++ b/arch/arm/mach-exynos4/include/mach/memory.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/memory.h
+/* linux/arch/arm/mach-exynos4/include/mach/memory.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5PV310 - Memory definitions
+ * EXYNOS4 - Memory definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h
new file mode 100644
index 000000000000..f26e46bc06ca
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/pm-core.h
@@ -0,0 +1,49 @@
+/* linux/arch/arm/mach-exynos4/include/mach/pm-core.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * EXYNOS4210 - PM core support for arch/arm/plat-s5p/pm.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <mach/regs-pmu.h>
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+        /* nothing here yet */
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+        unsigned int tmp;
+        tmp = __raw_readl(S5P_WAKEUP_MASK);
+        tmp &= ~(1 << 31);
+        __raw_writel(tmp, S5P_WAKEUP_MASK);
+
+        __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
+        __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
+}
+
+static inline void s3c_pm_arch_stop_clocks(void)
+{
+        /* nothing here yet */
+}
+
+static inline void s3c_pm_arch_show_resume_irqs(void)
+{
+        /* nothing here yet */
+}
+
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+                                           struct pm_uart_save *save)
+{
+        /* nothing here yet */
+}
diff --git a/arch/arm/mach-s5pv310/include/mach/pwm-clock.h b/arch/arm/mach-exynos4/include/mach/pwm-clock.h
index 7e6da2701088..8e12090287bb 100644
--- a/arch/arm/mach-s5pv310/include/mach/pwm-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/pwm-clock.h
@@ -1,7 +1,7 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/pwm-clock.h
+/* linux/arch/arm/mach-exynos4/include/mach/pwm-clock.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * Copyright 2008 Openmoko, Inc.
  * Copyright 2008 Simtec Electronics
@@ -10,7 +10,7 @@
  *
  * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
  *
- * S5PV310 - pwm clock and timer support
+ * EXYNOS4 - pwm clock and timer support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index b5c4ada1cff5..6e311c1157f5 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5PV310 - Clock register definitions
+ * EXYNOS4 - Clock register definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -17,13 +17,13 @@
 
 #define S5P_CLKREG(x)                   (S5P_VA_CMU + (x))
 
-#define S5P_INFORM0                     S5P_CLKREG(0x800)
-
 #define S5P_CLKDIV_LEFTBUS              S5P_CLKREG(0x04500)
 #define S5P_CLKDIV_STAT_LEFTBUS         S5P_CLKREG(0x04600)
+#define S5P_CLKGATE_IP_LEFTBUS          S5P_CLKREG(0x04800)
 
 #define S5P_CLKDIV_RIGHTBUS             S5P_CLKREG(0x08500)
 #define S5P_CLKDIV_STAT_RIGHTBUS        S5P_CLKREG(0x08600)
+#define S5P_CLKGATE_IP_RIGHTBUS         S5P_CLKREG(0x08800)
 
 #define S5P_EPLL_CON0                   S5P_CLKREG(0x0C110)
 #define S5P_EPLL_CON1                   S5P_CLKREG(0x0C114)
@@ -33,18 +33,24 @@
 #define S5P_CLKSRC_TOP0                 S5P_CLKREG(0x0C210)
 #define S5P_CLKSRC_TOP1                 S5P_CLKREG(0x0C214)
 #define S5P_CLKSRC_CAM                  S5P_CLKREG(0x0C220)
+#define S5P_CLKSRC_MFC                  S5P_CLKREG(0x0C228)
 #define S5P_CLKSRC_IMAGE                S5P_CLKREG(0x0C230)
 #define S5P_CLKSRC_LCD0                 S5P_CLKREG(0x0C234)
 #define S5P_CLKSRC_LCD1                 S5P_CLKREG(0x0C238)
+#define S5P_CLKSRC_MAUDIO               S5P_CLKREG(0x0C23C)
 #define S5P_CLKSRC_FSYS                 S5P_CLKREG(0x0C240)
 #define S5P_CLKSRC_PERIL0               S5P_CLKREG(0x0C250)
 #define S5P_CLKSRC_PERIL1               S5P_CLKREG(0x0C254)
 
 #define S5P_CLKDIV_TOP                  S5P_CLKREG(0x0C510)
 #define S5P_CLKDIV_CAM                  S5P_CLKREG(0x0C520)
+#define S5P_CLKDIV_TV                   S5P_CLKREG(0x0C524)
+#define S5P_CLKDIV_MFC                  S5P_CLKREG(0x0C528)
+#define S5P_CLKDIV_G3D                  S5P_CLKREG(0x0C52C)
 #define S5P_CLKDIV_IMAGE                S5P_CLKREG(0x0C530)
 #define S5P_CLKDIV_LCD0                 S5P_CLKREG(0x0C534)
 #define S5P_CLKDIV_LCD1                 S5P_CLKREG(0x0C538)
+#define S5P_CLKDIV_MAUDIO               S5P_CLKREG(0x0C53C)
 #define S5P_CLKDIV_FSYS0                S5P_CLKREG(0x0C540)
 #define S5P_CLKDIV_FSYS1                S5P_CLKREG(0x0C544)
 #define S5P_CLKDIV_FSYS2                S5P_CLKREG(0x0C548)
@@ -58,25 +64,36 @@
 
 #define S5P_CLKSRC_MASK_TOP             S5P_CLKREG(0x0C310)
 #define S5P_CLKSRC_MASK_CAM             S5P_CLKREG(0x0C320)
+#define S5P_CLKSRC_MASK_TV              S5P_CLKREG(0x0C324)
 #define S5P_CLKSRC_MASK_LCD0            S5P_CLKREG(0x0C334)
 #define S5P_CLKSRC_MASK_LCD1            S5P_CLKREG(0x0C338)
+#define S5P_CLKSRC_MASK_MAUDIO          S5P_CLKREG(0x0C33C)
 #define S5P_CLKSRC_MASK_FSYS            S5P_CLKREG(0x0C340)
 #define S5P_CLKSRC_MASK_PERIL0          S5P_CLKREG(0x0C350)
 #define S5P_CLKSRC_MASK_PERIL1          S5P_CLKREG(0x0C354)
 
 #define S5P_CLKDIV_STAT_TOP             S5P_CLKREG(0x0C610)
 
+#define S5P_CLKGATE_SCLKCAM             S5P_CLKREG(0x0C820)
 #define S5P_CLKGATE_IP_CAM              S5P_CLKREG(0x0C920)
+#define S5P_CLKGATE_IP_TV               S5P_CLKREG(0x0C924)
+#define S5P_CLKGATE_IP_MFC              S5P_CLKREG(0x0C928)
+#define S5P_CLKGATE_IP_G3D              S5P_CLKREG(0x0C92C)
 #define S5P_CLKGATE_IP_IMAGE            S5P_CLKREG(0x0C930)
 #define S5P_CLKGATE_IP_LCD0             S5P_CLKREG(0x0C934)
 #define S5P_CLKGATE_IP_LCD1             S5P_CLKREG(0x0C938)
 #define S5P_CLKGATE_IP_FSYS             S5P_CLKREG(0x0C940)
+#define S5P_CLKGATE_IP_GPS              S5P_CLKREG(0x0C94C)
 #define S5P_CLKGATE_IP_PERIL            S5P_CLKREG(0x0C950)
 #define S5P_CLKGATE_IP_PERIR            S5P_CLKREG(0x0C960)
+#define S5P_CLKGATE_BLOCK               S5P_CLKREG(0x0C970)
 
+#define S5P_CLKSRC_MASK_DMC             S5P_CLKREG(0x10300)
 #define S5P_CLKSRC_DMC                  S5P_CLKREG(0x10200)
 #define S5P_CLKDIV_DMC0                 S5P_CLKREG(0x10500)
+#define S5P_CLKDIV_DMC1                 S5P_CLKREG(0x10504)
 #define S5P_CLKDIV_STAT_DMC0            S5P_CLKREG(0x10600)
+#define S5P_CLKGATE_IP_DMC              S5P_CLKREG(0x10900)
 
 #define S5P_APLL_LOCK                   S5P_CLKREG(0x14000)
 #define S5P_MPLL_LOCK                   S5P_CLKREG(0x14004)
@@ -94,21 +111,18 @@
 #define S5P_CLKDIV_STATCPU1             S5P_CLKREG(0x14604)
 
 #define S5P_CLKGATE_SCLKCPU             S5P_CLKREG(0x14800)
+#define S5P_CLKGATE_IP_CPU              S5P_CLKREG(0x14900)
 
-/* APLL_LOCK */
 #define S5P_APLL_LOCKTIME               (0x1C20)        /* 300us */
 
-/* APLL_CON0 */
 #define S5P_APLLCON0_ENABLE_SHIFT       (31)
 #define S5P_APLLCON0_LOCKED_SHIFT       (29)
 #define S5P_APLL_VAL_1000               ((250 << 16) | (6 << 8) | 1)
 #define S5P_APLL_VAL_800                ((200 << 16) | (6 << 8) | 1)
 
-/* CLK_SRC_CPU */
 #define S5P_CLKSRC_CPU_MUXCORE_SHIFT    (16)
 #define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
 
-/* CLKDIV_CPU0 */
 #define S5P_CLKDIV_CPU0_CORE_SHIFT      (0)
 #define S5P_CLKDIV_CPU0_CORE_MASK       (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
 #define S5P_CLKDIV_CPU0_COREM0_SHIFT    (4)
@@ -124,7 +138,6 @@
 #define S5P_CLKDIV_CPU0_APLL_SHIFT      (24)
 #define S5P_CLKDIV_CPU0_APLL_MASK       (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
 
-/* CLKDIV_DMC0 */
 #define S5P_CLKDIV_DMC0_ACP_SHIFT       (0)
 #define S5P_CLKDIV_DMC0_ACP_MASK        (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
 #define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT   (4)
@@ -142,7 +155,6 @@
 #define S5P_CLKDIV_DMC0_CORETI_SHIFT    (28)
 #define S5P_CLKDIV_DMC0_CORETI_MASK     (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
 
-/* CLKDIV_TOP */
 #define S5P_CLKDIV_TOP_ACLK200_SHIFT    (0)
 #define S5P_CLKDIV_TOP_ACLK200_MASK     (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
 #define S5P_CLKDIV_TOP_ACLK100_SHIFT    (4)
@@ -154,13 +166,14 @@
 #define S5P_CLKDIV_TOP_ONENAND_SHIFT    (16)
 #define S5P_CLKDIV_TOP_ONENAND_MASK     (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
 
-/* CLKDIV_LEFTBUS / CLKDIV_RIGHTBUS*/
 #define S5P_CLKDIV_BUS_GDLR_SHIFT       (0)
 #define S5P_CLKDIV_BUS_GDLR_MASK        (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
 #define S5P_CLKDIV_BUS_GPLR_SHIFT       (4)
 #define S5P_CLKDIV_BUS_GPLR_MASK        (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
 
-/* Compatibility defines */
+/* Compatibility defines and inclusion */
+
+#include <mach/regs-pmu.h>
 
 #define S5P_EPLL_CON                    S5P_EPLL_CON0
 
diff --git a/arch/arm/mach-exynos4/include/mach/regs-gpio.h b/arch/arm/mach-exynos4/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..1401b21663a5
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/regs-gpio.h
@@ -0,0 +1,42 @@
+/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4 - GPIO (including EINT) register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_GPIO_H
+#define __ASM_ARCH_REGS_GPIO_H __FILE__
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+#define EXYNOS4_EINT40CON               (S5P_VA_GPIO2 + 0xE00)
+#define S5P_EINT_CON(x)                 (EXYNOS4_EINT40CON + ((x) * 0x4))
+
+#define EXYNOS4_EINT40FLTCON0           (S5P_VA_GPIO2 + 0xE80)
+#define S5P_EINT_FLTCON(x)              (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
+
+#define EXYNOS4_EINT40MASK              (S5P_VA_GPIO2 + 0xF00)
+#define S5P_EINT_MASK(x)                (EXYNOS4_EINT40MASK + ((x) * 0x4))
+
+#define EXYNOS4_EINT40PEND              (S5P_VA_GPIO2 + 0xF40)
+#define S5P_EINT_PEND(x)                (EXYNOS4_EINT40PEND + ((x) * 0x4))
+
+#define EINT_REG_NR(x)                  (EINT_OFFSET(x) >> 3)
+
+#define eint_irq_to_bit(irq)            (1 << (EINT_OFFSET(irq) & 0x7))
+
+#define EINT_MODE                       S3C_GPIO_SFN(0xf)
+
+#define EINT_GPIO_0(x)                  EXYNOS4_GPX0(x)
+#define EINT_GPIO_1(x)                  EXYNOS4_GPX1(x)
+#define EINT_GPIO_2(x)                  EXYNOS4_GPX2(x)
+#define EINT_GPIO_3(x)                  EXYNOS4_GPX3(x)
+
+#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-irq.h b/arch/arm/mach-exynos4/include/mach/regs-irq.h
index c6e09c7f9161..9c7b4bfd546f 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-irq.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-irq.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/regs-irq.h
+/* linux/arch/arm/mach-exynos4/include/mach/regs-irq.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5PV310 - IRQ register definitions
+ * EXYNOS4 - IRQ register definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-exynos4/include/mach/regs-mct.h b/arch/arm/mach-exynos4/include/mach/regs-mct.h
new file mode 100644
index 000000000000..ca9c8434b023
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/regs-mct.h
@@ -0,0 +1,52 @@
+/* arch/arm/mach-exynos4/include/mach/regs-mct.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4 MCT configutation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_MCT_H
+#define __ASM_ARCH_REGS_MCT_H __FILE__
+
+#include <mach/map.h>
+
+#define EXYNOS4_MCTREG(x)               (S5P_VA_SYSTIMER + (x))
+
+#define EXYNOS4_MCT_G_CNT_L             EXYNOS4_MCTREG(0x100)
+#define EXYNOS4_MCT_G_CNT_U             EXYNOS4_MCTREG(0x104)
+#define EXYNOS4_MCT_G_CNT_WSTAT         EXYNOS4_MCTREG(0x110)
+
+#define EXYNOS4_MCT_G_COMP0_L           EXYNOS4_MCTREG(0x200)
+#define EXYNOS4_MCT_G_COMP0_U           EXYNOS4_MCTREG(0x204)
+#define EXYNOS4_MCT_G_COMP0_ADD_INCR    EXYNOS4_MCTREG(0x208)
+
+#define EXYNOS4_MCT_G_TCON              EXYNOS4_MCTREG(0x240)
+
+#define EXYNOS4_MCT_G_INT_CSTAT         EXYNOS4_MCTREG(0x244)
+#define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
+#define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
+
+#define EXYNOS4_MCT_L0_BASE             EXYNOS4_MCTREG(0x300)
+#define EXYNOS4_MCT_L1_BASE             EXYNOS4_MCTREG(0x400)
+
+#define MCT_L_TCNTB_OFFSET              (0x00)
+#define MCT_L_ICNTB_OFFSET              (0x08)
+#define MCT_L_TCON_OFFSET               (0x20)
+#define MCT_L_INT_CSTAT_OFFSET          (0x30)
+#define MCT_L_INT_ENB_OFFSET            (0x34)
+#define MCT_L_WSTAT_OFFSET              (0x40)
+
+#define MCT_G_TCON_START                (1 << 8)
+#define MCT_G_TCON_COMP0_AUTO_INC       (1 << 1)
+#define MCT_G_TCON_COMP0_ENABLE         (1 << 0)
+
+#define MCT_L_TCON_INTERVAL_MODE        (1 << 2)
+#define MCT_L_TCON_INT_START            (1 << 1)
+#define MCT_L_TCON_TIMER_START          (1 << 0)
+
+#endif /* __ASM_ARCH_REGS_MCT_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-mem.h b/arch/arm/mach-exynos4/include/mach/regs-mem.h
index 834227140eaa..0368b5a27252 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-mem.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-mem.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/regs-mem.h
+/* linux/arch/arm/mach-exynos4/include/mach/regs-mem.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * S5PV310 - SROMC and DMC register definitions
+ * EXYNOS4 - SROMC and DMC register definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
new file mode 100644
index 000000000000..62b0014d05e0
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -0,0 +1,162 @@
+/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4 - Power management unit definition
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_PMU_H
+#define __ASM_ARCH_REGS_PMU_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_PMUREG(x)                           (S5P_VA_PMU + (x))
+
+#define S5P_CENTRAL_SEQ_CONFIGURATION           S5P_PMUREG(0x0200)
+
+#define S5P_CENTRAL_LOWPWR_CFG                  (1 << 16)
+
+#define S5P_CENTRAL_SEQ_OPTION                  S5P_PMUREG(0x0208)
+
+#define S5P_USE_STANDBY_WFI0                    (1 << 16)
+#define S5P_USE_STANDBY_WFI1                    (1 << 17)
+#define S5P_USE_STANDBY_WFE0                    (1 << 24)
+#define S5P_USE_STANDBY_WFE1                    (1 << 25)
+#define S5P_USE_MASK                            ((0x3 << 16) | (0x3 << 24))
+
+#define S5P_WAKEUP_STAT                         S5P_PMUREG(0x0600)
+#define S5P_EINT_WAKEUP_MASK                    S5P_PMUREG(0x0604)
+#define S5P_WAKEUP_MASK                         S5P_PMUREG(0x0608)
+
+#define S5P_MIPI_DPHY_CONTROL(n)                S5P_PMUREG(0x0710 + (n) * 4)
+#define S5P_MIPI_DPHY_ENABLE                    (1 << 0)
+#define S5P_MIPI_DPHY_SRESETN                   (1 << 1)
+#define S5P_MIPI_DPHY_MRESETN                   (1 << 2)
+
+#define S5P_PMU_SATA_PHY_CONTROL                S5P_PMUREG(0x0720)
+#define S5P_INFORM0                             S5P_PMUREG(0x0800)
+#define S5P_INFORM1                             S5P_PMUREG(0x0804)
+#define S5P_INFORM2                             S5P_PMUREG(0x0808)
+#define S5P_INFORM3                             S5P_PMUREG(0x080C)
+#define S5P_INFORM4                             S5P_PMUREG(0x0810)
+#define S5P_INFORM5                             S5P_PMUREG(0x0814)
+#define S5P_INFORM6                             S5P_PMUREG(0x0818)
+#define S5P_INFORM7                             S5P_PMUREG(0x081C)
+
+#define S5P_ARM_CORE0_LOWPWR                    S5P_PMUREG(0x1000)
+#define S5P_DIS_IRQ_CORE0                       S5P_PMUREG(0x1004)
+#define S5P_DIS_IRQ_CENTRAL0                    S5P_PMUREG(0x1008)
+#define S5P_ARM_CORE1_LOWPWR                    S5P_PMUREG(0x1010)
+#define S5P_DIS_IRQ_CORE1                       S5P_PMUREG(0x1014)
+#define S5P_DIS_IRQ_CENTRAL1                    S5P_PMUREG(0x1018)
+#define S5P_ARM_COMMON_LOWPWR                   S5P_PMUREG(0x1080)
+#define S5P_L2_0_LOWPWR                         S5P_PMUREG(0x10C0)
+#define S5P_L2_1_LOWPWR                         S5P_PMUREG(0x10C4)
+#define S5P_CMU_ACLKSTOP_LOWPWR                 S5P_PMUREG(0x1100)
+#define S5P_CMU_SCLKSTOP_LOWPWR                 S5P_PMUREG(0x1104)
+#define S5P_CMU_RESET_LOWPWR                    S5P_PMUREG(0x110C)
+#define S5P_APLL_SYSCLK_LOWPWR                  S5P_PMUREG(0x1120)
+#define S5P_MPLL_SYSCLK_LOWPWR                  S5P_PMUREG(0x1124)
+#define S5P_VPLL_SYSCLK_LOWPWR                  S5P_PMUREG(0x1128)
+#define S5P_EPLL_SYSCLK_LOWPWR                  S5P_PMUREG(0x112C)
+#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR        S5P_PMUREG(0x1138)
+#define S5P_CMU_RESET_GPSALIVE_LOWPWR           S5P_PMUREG(0x113C)
+#define S5P_CMU_CLKSTOP_CAM_LOWPWR              S5P_PMUREG(0x1140)
+#define S5P_CMU_CLKSTOP_TV_LOWPWR               S5P_PMUREG(0x1144)
+#define S5P_CMU_CLKSTOP_MFC_LOWPWR              S5P_PMUREG(0x1148)
+#define S5P_CMU_CLKSTOP_G3D_LOWPWR              S5P_PMUREG(0x114C)
+#define S5P_CMU_CLKSTOP_LCD0_LOWPWR             S5P_PMUREG(0x1150)
+#define S5P_CMU_CLKSTOP_LCD1_LOWPWR             S5P_PMUREG(0x1154)
+#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR           S5P_PMUREG(0x1158)
+#define S5P_CMU_CLKSTOP_GPS_LOWPWR              S5P_PMUREG(0x115C)
+#define S5P_CMU_RESET_CAM_LOWPWR                S5P_PMUREG(0x1160)
+#define S5P_CMU_RESET_TV_LOWPWR                 S5P_PMUREG(0x1164)
+#define S5P_CMU_RESET_MFC_LOWPWR                S5P_PMUREG(0x1168)
+#define S5P_CMU_RESET_G3D_LOWPWR                S5P_PMUREG(0x116C)
+#define S5P_CMU_RESET_LCD0_LOWPWR               S5P_PMUREG(0x1170)
+#define S5P_CMU_RESET_LCD1_LOWPWR               S5P_PMUREG(0x1174)
+#define S5P_CMU_RESET_MAUDIO_LOWPWR             S5P_PMUREG(0x1178)
+#define S5P_CMU_RESET_GPS_LOWPWR                S5P_PMUREG(0x117C)
+#define S5P_TOP_BUS_LOWPWR                      S5P_PMUREG(0x1180)
+#define S5P_TOP_RETENTION_LOWPWR                S5P_PMUREG(0x1184)
+#define S5P_TOP_PWR_LOWPWR                      S5P_PMUREG(0x1188)
+#define S5P_LOGIC_RESET_LOWPWR                  S5P_PMUREG(0x11A0)
+#define S5P_ONENAND_MEM_LOWPWR                  S5P_PMUREG(0x11C0)
+#define S5P_MODIMIF_MEM_LOWPWR                  S5P_PMUREG(0x11C4)
+#define S5P_G2D_ACP_MEM_LOWPWR                  S5P_PMUREG(0x11C8)
+#define S5P_USBOTG_MEM_LOWPWR                   S5P_PMUREG(0x11CC)
+#define S5P_HSMMC_MEM_LOWPWR                    S5P_PMUREG(0x11D0)
+#define S5P_CSSYS_MEM_LOWPWR                    S5P_PMUREG(0x11D4)
+#define S5P_SECSS_MEM_LOWPWR                    S5P_PMUREG(0x11D8)
+#define S5P_PCIE_MEM_LOWPWR                     S5P_PMUREG(0x11E0)
+#define S5P_SATA_MEM_LOWPWR                     S5P_PMUREG(0x11E4)
+#define S5P_PAD_RETENTION_DRAM_LOWPWR           S5P_PMUREG(0x1200)
+#define S5P_PAD_RETENTION_MAUDIO_LOWPWR         S5P_PMUREG(0x1204)
+#define S5P_PAD_RETENTION_GPIO_LOWPWR           S5P_PMUREG(0x1220)
+#define S5P_PAD_RETENTION_UART_LOWPWR           S5P_PMUREG(0x1224)
+#define S5P_PAD_RETENTION_MMCA_LOWPWR           S5P_PMUREG(0x1228)
+#define S5P_PAD_RETENTION_MMCB_LOWPWR           S5P_PMUREG(0x122C)
+#define S5P_PAD_RETENTION_EBIA_LOWPWR           S5P_PMUREG(0x1230)
+#define S5P_PAD_RETENTION_EBIB_LOWPWR           S5P_PMUREG(0x1234)
+#define S5P_PAD_RETENTION_ISOLATION_LOWPWR      S5P_PMUREG(0x1240)
+#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR        S5P_PMUREG(0x1260)
+#define S5P_XUSBXTI_LOWPWR                      S5P_PMUREG(0x1280)
+#define S5P_XXTI_LOWPWR                         S5P_PMUREG(0x1284)
+#define S5P_EXT_REGULATOR_LOWPWR                S5P_PMUREG(0x12C0)
+#define S5P_GPIO_MODE_LOWPWR                    S5P_PMUREG(0x1300)
+#define S5P_GPIO_MODE_MAUDIO_LOWPWR             S5P_PMUREG(0x1340)
+#define S5P_CAM_LOWPWR                          S5P_PMUREG(0x1380)
+#define S5P_TV_LOWPWR                           S5P_PMUREG(0x1384)
+#define S5P_MFC_LOWPWR                          S5P_PMUREG(0x1388)
+#define S5P_G3D_LOWPWR                          S5P_PMUREG(0x138C)
+#define S5P_LCD0_LOWPWR                         S5P_PMUREG(0x1390)
+#define S5P_LCD1_LOWPWR                         S5P_PMUREG(0x1394)
+#define S5P_MAUDIO_LOWPWR                       S5P_PMUREG(0x1398)
+#define S5P_GPS_LOWPWR                          S5P_PMUREG(0x139C)
+#define S5P_GPS_ALIVE_LOWPWR                    S5P_PMUREG(0x13A0)
+
+#define S5P_ARM_CORE0_CONFIGURATION             S5P_PMUREG(0x2000)
+#define S5P_ARM_CORE0_OPTION                    S5P_PMUREG(0x2008)
+#define S5P_ARM_CORE1_CONFIGURATION             S5P_PMUREG(0x2080)
+#define S5P_ARM_CORE1_STATUS                    S5P_PMUREG(0x2084)
+#define S5P_ARM_CORE1_OPTION                    S5P_PMUREG(0x2088)
+
+#define S5P_ARM_COMMON_OPTION                   S5P_PMUREG(0x2408)
+#define S5P_TOP_PWR_OPTION                      S5P_PMUREG(0x2C48)
+#define S5P_CAM_OPTION                          S5P_PMUREG(0x3C08)
+#define S5P_TV_OPTION                           S5P_PMUREG(0x3C28)
+#define S5P_MFC_OPTION                          S5P_PMUREG(0x3C48)
+#define S5P_G3D_OPTION                          S5P_PMUREG(0x3C68)
+#define S5P_LCD0_OPTION                         S5P_PMUREG(0x3C88)
+#define S5P_LCD1_OPTION                         S5P_PMUREG(0x3CA8)
+#define S5P_MAUDIO_OPTION                       S5P_PMUREG(0x3CC8)
+#define S5P_GPS_OPTION                          S5P_PMUREG(0x3CE8)
+#define S5P_GPS_ALIVE_OPTION                    S5P_PMUREG(0x3D08)
+
+#define S5P_PAD_RET_MAUDIO_OPTION               S5P_PMUREG(0x3028)
+#define S5P_PAD_RET_GPIO_OPTION                 S5P_PMUREG(0x3108)
+#define S5P_PAD_RET_UART_OPTION                 S5P_PMUREG(0x3128)
+#define S5P_PAD_RET_MMCA_OPTION                 S5P_PMUREG(0x3148)
+#define S5P_PAD_RET_MMCB_OPTION                 S5P_PMUREG(0x3168)
+#define S5P_PAD_RET_EBIA_OPTION                 S5P_PMUREG(0x3188)
+#define S5P_PAD_RET_EBIB_OPTION                 S5P_PMUREG(0x31A8)
+
+#define S5P_PMU_CAM_CONF                        S5P_PMUREG(0x3C00)
+#define S5P_PMU_TV_CONF                         S5P_PMUREG(0x3C20)
+#define S5P_PMU_MFC_CONF                        S5P_PMUREG(0x3C40)
+#define S5P_PMU_G3D_CONF                        S5P_PMUREG(0x3C60)
+#define S5P_PMU_LCD0_CONF                       S5P_PMUREG(0x3C80)
+#define S5P_PMU_LCD1_CONF                       S5P_PMUREG(0x3CA0)
+#define S5P_PMU_GPS_CONF                        S5P_PMUREG(0x3CE0)
+
+#define S5P_PMU_SATA_PHY_CONTROL_EN             0x1
+#define S5P_INT_LOCAL_PWR_EN                    0x7
+
+#define S5P_CHECK_SLEEP                         0x00000BAD
+
+#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h b/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
index 0b28e81a16f7..68ff6ad08a2b 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
+/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * S5PV310 - System MMU register
+ * EXYNOS4 - System MMU register
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -19,6 +19,10 @@
 #define S5P_MMU_FLUSH                   0x00C
 #define S5P_PT_BASE_ADDR                0x014
 #define S5P_INT_STATUS                  0x018
+#define S5P_INT_CLEAR                   0x01C
 #define S5P_PAGE_FAULT_ADDR             0x024
+#define S5P_AW_FAULT_ADDR               0x028
+#define S5P_AR_FAULT_ADDR               0x02C
+#define S5P_DEFAULT_SLAVE_ADDR          0x030
 
 #endif /* __ASM_ARCH_REGS_SYSMMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-exynos4/include/mach/smp.h
index 393ccbd52c4a..a463dcebcfd3 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-exynos4/include/mach/smp.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/smp.h
+/* linux/arch/arm/mach-exynos4/include/mach/smp.h
  *
  * Cloned from arch/arm/mach-realview/include/mach/smp.h
 */
diff --git a/arch/arm/mach-exynos4/include/mach/sysmmu.h b/arch/arm/mach-exynos4/include/mach/sysmmu.h
new file mode 100644
index 000000000000..6a5fbb534e82
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/sysmmu.h
@@ -0,0 +1,46 @@
+/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung sysmmu driver for EXYNOS4
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARM_ARCH_SYSMMU_H
+#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
+
+enum exynos4_sysmmu_ips {
+        SYSMMU_MDMA,
+        SYSMMU_SSS,
+        SYSMMU_FIMC0,
+        SYSMMU_FIMC1,
+        SYSMMU_FIMC2,
+        SYSMMU_FIMC3,
+        SYSMMU_JPEG,
+        SYSMMU_FIMD0,
+        SYSMMU_FIMD1,
+        SYSMMU_PCIe,
+        SYSMMU_G2D,
+        SYSMMU_ROTATOR,
+        SYSMMU_MDMA2,
+        SYSMMU_TV,
+        SYSMMU_MFC_L,
+        SYSMMU_MFC_R,
+        EXYNOS4_SYSMMU_TOTAL_IPNUM,
+};
+
+#define S5P_SYSMMU_TOTAL_IPNUM          EXYNOS4_SYSMMU_TOTAL_IPNUM
+
+extern const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM];
+
+typedef enum exynos4_sysmmu_ips sysmmu_ips;
+
+void sysmmu_clk_init(struct device *dev, sysmmu_ips ips);
+void sysmmu_clk_enable(sysmmu_ips ips);
+void sysmmu_clk_disable(sysmmu_ips ips);
+
+#endif /* __ASM_ARM_ARCH_SYSMMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/system.h b/arch/arm/mach-exynos4/include/mach/system.h
index d10c009cf0f1..5e3220c18fc7 100644
--- a/arch/arm/mach-s5pv310/include/mach/system.h
+++ b/arch/arm/mach-exynos4/include/mach/system.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/system.h
+/* linux/arch/arm/mach-exynos4/include/mach/system.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5PV310 - system support header
+ * EXYNOS4 - system support header
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/timex.h b/arch/arm/mach-exynos4/include/mach/timex.h
index bd2359b952b4..6d138750a708 100644
--- a/arch/arm/mach-s5pv310/include/mach/timex.h
+++ b/arch/arm/mach-exynos4/include/mach/timex.h
@@ -1,14 +1,14 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/timex.h
+/* linux/arch/arm/mach-exynos4/include/mach/timex.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * Copyright (c) 2003-2010 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *
  * Based on arch/arm/mach-s5p6442/include/mach/timex.h
  *
- * S5PV310 - time parameters
+ * EXYNOS4 - time parameters
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/uncompress.h b/arch/arm/mach-exynos4/include/mach/uncompress.h
index 59593c1e2416..21d97bcd9acb 100644
--- a/arch/arm/mach-s5pv310/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos4/include/mach/uncompress.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/uncompress.h
+/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5PV310 - uncompress code
+ * EXYNOS4 - uncompress code
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/vmalloc.h b/arch/arm/mach-exynos4/include/mach/vmalloc.h
index 65759fb97581..284330e571d2 100644
--- a/arch/arm/mach-s5pv310/include/mach/vmalloc.h
+++ b/arch/arm/mach-exynos4/include/mach/vmalloc.h
@@ -1,7 +1,7 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/vmalloc.h
+/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
  *
@@ -11,7 +11,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
- * S5PV310 vmalloc definition
+ * EXYNOS4 vmalloc definition
 */
 
 #ifndef __ASM_ARCH_VMALLOC_H
diff --git a/arch/arm/mach-s5pv310/init.c b/arch/arm/mach-exynos4/init.c
index 182dcf42cfb4..cf91f50e43ab 100644
--- a/arch/arm/mach-s5pv310/init.c
+++ b/arch/arm/mach-exynos4/init.c
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s5pv310/init.c
+/* linux/arch/arm/mach-exynos4/init.c
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
@@ -14,7 +14,7 @@
 #include <plat/devs.h>
 #include <plat/regs-serial.h>
 
-static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = {
+static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
         [0] = {
                 .name           = "uclk1",
                 .divisor        = 1,
@@ -24,7 +24,7 @@ static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = {
 };
 
 /* uart registration process */
-void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
         struct s3c2410_uartcfg *tcfg = cfg;
         u32 ucnt;
@@ -32,8 +32,8 @@ void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
         for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
                 if (!tcfg->clocks) {
                         tcfg->has_fracval = 1;
-                        tcfg->clocks = s5pv310_serial_clocks;
-                        tcfg->clocks_size = ARRAY_SIZE(s5pv310_serial_clocks);
+                        tcfg->clocks = exynos4_serial_clocks;
+                        tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
                 }
         }
 
diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c
index 1ea4a9e83bbe..31618d91ce15 100644
--- a/arch/arm/mach-s5pv310/irq-combiner.c
+++ b/arch/arm/mach-exynos4/irq-combiner.c
@@ -1,6 +1,6 @@
-/* linux/arch/arm/mach-s5pv310/irq-combiner.c
+/* linux/arch/arm/mach-exynos4/irq-combiner.c
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
  * Based on arch/arm/common/gic.c
diff --git a/arch/arm/mach-s5pv310/irq-eint.c b/arch/arm/mach-exynos4/irq-eint.c
index 477bd9e97f0f..4f7ad4a796e4 100644
--- a/arch/arm/mach-s5pv310/irq-eint.c
+++ b/arch/arm/mach-exynos4/irq-eint.c
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5pv310/irq-eint.c
+/* linux/arch/arm/mach-exynos4/irq-eint.c
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * S5PV310 - IRQ EINT support
+ * EXYNOS4 - IRQ EINT support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -27,7 +27,7 @@ static DEFINE_SPINLOCK(eint_lock);
 
 static unsigned int eint0_15_data[16];
 
-static unsigned int s5pv310_get_irq_nr(unsigned int number)
+static unsigned int exynos4_get_irq_nr(unsigned int number)
 {
         u32 ret = 0;
 
@@ -48,7 +48,7 @@ static unsigned int s5pv310_get_irq_nr(unsigned int number)
         return ret;
 }
 
-static inline void s5pv310_irq_eint_mask(struct irq_data *data)
+static inline void exynos4_irq_eint_mask(struct irq_data *data)
 {
         u32 mask;
 
@@ -59,7 +59,7 @@ static inline void s5pv310_irq_eint_mask(struct irq_data *data)
         spin_unlock(&eint_lock);
 }
 
-static void s5pv310_irq_eint_unmask(struct irq_data *data)
+static void exynos4_irq_eint_unmask(struct irq_data *data)
 {
         u32 mask;
 
@@ -70,19 +70,19 @@ static void s5pv310_irq_eint_unmask(struct irq_data *data)
         spin_unlock(&eint_lock);
 }
 
-static inline void s5pv310_irq_eint_ack(struct irq_data *data)
+static inline void exynos4_irq_eint_ack(struct irq_data *data)
 {
         __raw_writel(eint_irq_to_bit(data->irq),
                      S5P_EINT_PEND(EINT_REG_NR(data->irq)));
 }
 
-static void s5pv310_irq_eint_maskack(struct irq_data *data)
+static void exynos4_irq_eint_maskack(struct irq_data *data)
 {
-        s5pv310_irq_eint_mask(data);
-        s5pv310_irq_eint_ack(data);
+        exynos4_irq_eint_mask(data);
+        exynos4_irq_eint_ack(data);
 }
 
-static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type)
+static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
 {
         int offs = EINT_OFFSET(data->irq);
         int shift;
@@ -145,19 +145,19 @@ static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type)
         return 0;
 }
 
-static struct irq_chip s5pv310_irq_eint = {
-        .name           = "s5pv310-eint",
-        .irq_mask       = s5pv310_irq_eint_mask,
-        .irq_unmask     = s5pv310_irq_eint_unmask,
-        .irq_mask_ack   = s5pv310_irq_eint_maskack,
-        .irq_ack        = s5pv310_irq_eint_ack,
-        .irq_set_type   = s5pv310_irq_eint_set_type,
+static struct irq_chip exynos4_irq_eint = {
+        .name           = "exynos4-eint",
+        .irq_mask       = exynos4_irq_eint_mask,
+        .irq_unmask     = exynos4_irq_eint_unmask,
+        .irq_mask_ack   = exynos4_irq_eint_maskack,
+        .irq_ack        = exynos4_irq_eint_ack,
+        .irq_set_type   = exynos4_irq_eint_set_type,
 #ifdef CONFIG_PM
         .irq_set_wake   = s3c_irqext_wake,
 #endif
 };
 
-/* s5pv310_irq_demux_eint
+/* exynos4_irq_demux_eint
  *
  * This function demuxes the IRQ from from EINTs 16 to 31.
  * It is designed to be inlined into the specific handler
@@ -165,7 +165,7 @@ static struct irq_chip s5pv310_irq_eint = {
  *
  * Each EINT pend/mask registers handle eight of them.
  */
-static inline void s5pv310_irq_demux_eint(unsigned int start)
+static inline void exynos4_irq_demux_eint(unsigned int start)
 {
         unsigned int irq;
 
@@ -182,13 +182,13 @@ static inline void s5pv310_irq_demux_eint(unsigned int start)
         }
 }
 
-static void s5pv310_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 {
-        s5pv310_irq_demux_eint(IRQ_EINT(16));
-        s5pv310_irq_demux_eint(IRQ_EINT(24));
+        exynos4_irq_demux_eint(IRQ_EINT(16));
+        exynos4_irq_demux_eint(IRQ_EINT(24));
 }
 
-static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
+static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 {
         u32 *irq_data = get_irq_data(irq);
         struct irq_chip *chip = get_irq_chip(irq);
@@ -203,27 +203,27 @@ static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
         chip->irq_unmask(&desc->irq_data);
 }
 
-int __init s5pv310_init_irq_eint(void)
+int __init exynos4_init_irq_eint(void)
 {
         int irq;
 
         for (irq = 0 ; irq <= 31 ; irq++) {
-                set_irq_chip(IRQ_EINT(irq), &s5pv310_irq_eint);
+                set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint);
                 set_irq_handler(IRQ_EINT(irq), handle_level_irq);
                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
         }
 
-        set_irq_chained_handler(IRQ_EINT16_31, s5pv310_irq_demux_eint16_31);
+        set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
 
         for (irq = 0 ; irq <= 15 ; irq++) {
                 eint0_15_data[irq] = IRQ_EINT(irq);
 
-                set_irq_data(s5pv310_get_irq_nr(irq), &eint0_15_data[irq]);
-                set_irq_chained_handler(s5pv310_get_irq_nr(irq),
-                                        s5pv310_irq_eint0_15);
+                set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]);
+                set_irq_chained_handler(exynos4_get_irq_nr(irq),
+                                        exynos4_irq_eint0_15);
         }
 
         return 0;
 }
 
-arch_initcall(s5pv310_init_irq_eint);
+arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/mach-s5pv310/localtimer.c b/arch/arm/mach-exynos4/localtimer.c
index 2784036cd8b1..2a2993ae8d86 100644
--- a/arch/arm/mach-s5pv310/localtimer.c
+++ b/arch/arm/mach-exynos4/localtimer.c
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s5pv310/localtimer.c
+/* linux/arch/arm/mach-exynos4/localtimer.c
  *
  * Cloned from linux/arch/arm/mach-realview/localtimer.c
  *
diff --git a/arch/arm/mach-exynos4/mach-armlex4210.c b/arch/arm/mach-exynos4/mach-armlex4210.c
new file mode 100644
index 000000000000..b482c6285fc4
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-armlex4210.c
@@ -0,0 +1,215 @@
+/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/smsc911x.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-serial.h>
+#include <plat/regs-srom.h>
+#include <plat/sdhci.h>
+
+#include <mach/map.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL |        \
+                                 S3C2410_UCON_RXILEVEL |        \
+                                 S3C2410_UCON_TXIRQMODE |       \
+                                 S3C2410_UCON_RXIRQMODE |       \
+                                 S3C2410_UCON_RXFIFO_TOI |      \
+                                 S3C2443_UCON_RXERR_IRQEN)
+
+#define ARMLEX4210_ULCON_DEFAULT        S3C2410_LCON_CS8
+
+#define ARMLEX4210_UFCON_DEFAULT        (S3C2410_UFCON_FIFOMODE |       \
+                                 S5PV210_UFCON_TXTRIG4 |        \
+                                 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = ARMLEX4210_UCON_DEFAULT,
+                .ulcon          = ARMLEX4210_ULCON_DEFAULT,
+                .ufcon          = ARMLEX4210_UFCON_DEFAULT,
+        },
+        [1] = {
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = ARMLEX4210_UCON_DEFAULT,
+                .ulcon          = ARMLEX4210_ULCON_DEFAULT,
+                .ufcon          = ARMLEX4210_UFCON_DEFAULT,
+        },
+        [2] = {
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = ARMLEX4210_UCON_DEFAULT,
+                .ulcon          = ARMLEX4210_ULCON_DEFAULT,
+                .ufcon          = ARMLEX4210_UFCON_DEFAULT,
+        },
+        [3] = {
+                .hwport         = 3,
+                .flags          = 0,
+                .ucon           = ARMLEX4210_UCON_DEFAULT,
+                .ulcon          = ARMLEX4210_ULCON_DEFAULT,
+                .ufcon          = ARMLEX4210_UFCON_DEFAULT,
+        },
+};
+
+static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_PERMANENT,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
+        .max_width              = 8,
+        .host_caps              = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_GPIO,
+        .ext_cd_gpio            = EXYNOS4_GPX2(5),
+        .ext_cd_gpio_invert     = 1,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+        .max_width              = 4,
+};
+
+static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_PERMANENT,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+        .max_width              = 4,
+};
+
+static void __init armlex4210_sdhci_init(void)
+{
+        s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
+        s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
+        s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
+}
+
+static void __init armlex4210_wlan_init(void)
+{
+        /* enable */
+        s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
+        s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
+
+        /* reset */
+        s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
+        s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
+
+        /* wakeup */
+        s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
+        s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
+}
+
+static struct resource armlex4210_smsc911x_resources[] = {
+        [0] = {
+                .start  = EXYNOS4_PA_SROM_BANK(3),
+                .end    = EXYNOS4_PA_SROM_BANK(3) + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_EINT(27),
+                .end    = IRQ_EINT(27),
+                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
+        },
+};
+
+static struct smsc911x_platform_config smsc9215_config = {
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+        .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+        .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
+};
+
+static struct platform_device armlex4210_smsc911x = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(armlex4210_smsc911x_resources),
+        .resource       = armlex4210_smsc911x_resources,
+        .dev            = {
+                .platform_data  = &smsc9215_config,
+        },
+};
+
+static struct platform_device *armlex4210_devices[] __initdata = {
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc2,
+        &s3c_device_hsmmc3,
+        &s3c_device_rtc,
+        &s3c_device_wdt,
+        &exynos4_device_sysmmu,
+        &samsung_asoc_dma,
+        &armlex4210_smsc911x,
+        &exynos4_device_ahci,
+};
+
+static void __init armlex4210_smsc911x_init(void)
+{
+        u32 cs1;
+
+        /* configure nCS1 width to 16 bits */
+        cs1 = __raw_readl(S5P_SROM_BW) &
+                ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
+        cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
+                (0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
+                (1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
+                (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
+                S5P_SROM_BW__NCS1__SHIFT;
+        __raw_writel(cs1, S5P_SROM_BW);
+
+        /* set timing for nCS1 suitable for ethernet chip */
+        __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
+                     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
+                     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
+                     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
+                     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
+                     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
+                     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
+}
+
+static void __init armlex4210_map_io(void)
+{
+        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s3c24xx_init_clocks(24000000);
+        s3c24xx_init_uarts(armlex4210_uartcfgs,
+                           ARRAY_SIZE(armlex4210_uartcfgs));
+}
+
+static void __init armlex4210_machine_init(void)
+{
+        armlex4210_smsc911x_init();
+
+        armlex4210_sdhci_init();
+
+        armlex4210_wlan_init();
+
+        platform_add_devices(armlex4210_devices,
+                             ARRAY_SIZE(armlex4210_devices));
+}
+
+MACHINE_START(ARMLEX4210, "ARMLEX4210")
+        /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
+        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .init_irq       = exynos4_init_irq,
+        .map_io         = armlex4210_map_io,
+        .init_machine   = armlex4210_machine_init,
+        .timer          = &exynos4_timer,
+MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
new file mode 100644
index 000000000000..b79ad010d194
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -0,0 +1,305 @@
+/*
+ * linux/arch/arm/mach-exynos4/mach-nuri.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mmc/host.h>
+#include <linux/fb.h>
+#include <linux/pwm_backlight.h>
+
+#include <video/platform_lcd.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <plat/exynos4.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/sdhci.h>
+
+#include <mach/map.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define NURI_UCON_DEFAULT       (S3C2410_UCON_TXILEVEL |        \
+                                 S3C2410_UCON_RXILEVEL |        \
+                                 S3C2410_UCON_TXIRQMODE |       \
+                                 S3C2410_UCON_RXIRQMODE |       \
+                                 S3C2410_UCON_RXFIFO_TOI |      \
+                                 S3C2443_UCON_RXERR_IRQEN)
+
+#define NURI_ULCON_DEFAULT      S3C2410_LCON_CS8
+
+#define NURI_UFCON_DEFAULT      (S3C2410_UFCON_FIFOMODE |       \
+                                 S5PV210_UFCON_TXTRIG256 |      \
+                                 S5PV210_UFCON_RXTRIG256)
+
+enum fixed_regulator_id {
+        FIXED_REG_ID_MMC = 0,
+};
+
+static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
+        {
+                .hwport         = 0,
+                .ucon           = NURI_UCON_DEFAULT,
+                .ulcon          = NURI_ULCON_DEFAULT,
+                .ufcon          = NURI_UFCON_DEFAULT,
+        },
+        {
+                .hwport         = 1,
+                .ucon           = NURI_UCON_DEFAULT,
+                .ulcon          = NURI_ULCON_DEFAULT,
+                .ufcon          = NURI_UFCON_DEFAULT,
+        },
+        {
+                .hwport         = 2,
+                .ucon           = NURI_UCON_DEFAULT,
+                .ulcon          = NURI_ULCON_DEFAULT,
+                .ufcon          = NURI_UFCON_DEFAULT,
+        },
+        {
+                .hwport         = 3,
+                .ucon           = NURI_UCON_DEFAULT,
+                .ulcon          = NURI_ULCON_DEFAULT,
+                .ufcon          = NURI_UFCON_DEFAULT,
+        },
+};
+
+/* eMMC */
+static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
+        .max_width              = 8,
+        .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+                                MMC_CAP_DISABLE | MMC_CAP_ERASE),
+        .cd_type                = S3C_SDHCI_CD_PERMANENT,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct regulator_consumer_supply emmc_supplies[] = {
+        REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
+        REGULATOR_SUPPLY("vmmc", "dw_mmc"),
+};
+
+static struct regulator_init_data emmc_fixed_voltage_init_data = {
+        .constraints            = {
+                .name           = "VMEM_VDD_2.8V",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(emmc_supplies),
+        .consumer_supplies      = emmc_supplies,
+};
+
+static struct fixed_voltage_config emmc_fixed_voltage_config = {
+        .supply_name            = "MASSMEMORY_EN (inverted)",
+        .microvolts             = 2800000,
+        .gpio                   = EXYNOS4_GPL1(1),
+        .enable_high            = false,
+        .init_data              = &emmc_fixed_voltage_init_data,
+};
+
+static struct platform_device emmc_fixed_voltage = {
+        .name                   = "reg-fixed-voltage",
+        .id                     = FIXED_REG_ID_MMC,
+        .dev                    = {
+                .platform_data  = &emmc_fixed_voltage_config,
+        },
+};
+
+/* SD */
+static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
+        .max_width              = 4,
+        .host_caps              = MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+                                MMC_CAP_DISABLE,
+        .ext_cd_gpio            = EXYNOS4_GPX3(3),      /* XEINT_27 */
+        .ext_cd_gpio_invert     = 1,
+        .cd_type                = S3C_SDHCI_CD_GPIO,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+/* WLAN */
+static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = {
+        .max_width              = 4,
+        .host_caps              = MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
+        .cd_type                = S3C_SDHCI_CD_EXTERNAL,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static void __init nuri_sdhci_init(void)
+{
+        s3c_sdhci0_set_platdata(&nuri_hsmmc0_data);
+        s3c_sdhci2_set_platdata(&nuri_hsmmc2_data);
+        s3c_sdhci3_set_platdata(&nuri_hsmmc3_data);
+}
+
+/* GPIO KEYS */
+static struct gpio_keys_button nuri_gpio_keys_tables[] = {
+        {
+                .code                   = KEY_VOLUMEUP,
+                .gpio                   = EXYNOS4_GPX2(0),      /* XEINT16 */
+                .desc                   = "gpio-keys: KEY_VOLUMEUP",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .debounce_interval      = 1,
+        }, {
+                .code                   = KEY_VOLUMEDOWN,
+                .gpio                   = EXYNOS4_GPX2(1),      /* XEINT17 */
+                .desc                   = "gpio-keys: KEY_VOLUMEDOWN",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .debounce_interval      = 1,
+        }, {
+                .code                   = KEY_POWER,
+                .gpio                   = EXYNOS4_GPX2(7),      /* XEINT23 */
+                .desc                   = "gpio-keys: KEY_POWER",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .wakeup                 = 1,
+                .debounce_interval      = 1,
+        },
+};
+
+static struct gpio_keys_platform_data nuri_gpio_keys_data = {
+        .buttons                = nuri_gpio_keys_tables,
+        .nbuttons               = ARRAY_SIZE(nuri_gpio_keys_tables),
+};
+
+static struct platform_device nuri_gpio_keys = {
+        .name                   = "gpio-keys",
+        .dev                    = {
+                .platform_data  = &nuri_gpio_keys_data,
+        },
+};
+
+static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
+{
+        int gpio = EXYNOS4_GPE1(5);
+
+        gpio_request(gpio, "LVDS_nSHDN");
+        gpio_direction_output(gpio, power);
+        gpio_free(gpio);
+}
+
+static int nuri_bl_init(struct device *dev)
+{
+        int ret, gpio = EXYNOS4_GPE2(3);
+
+        ret = gpio_request(gpio, "LCD_LDO_EN");
+        if (!ret)
+                gpio_direction_output(gpio, 0);
+
+        return ret;
+}
+
+static int nuri_bl_notify(struct device *dev, int brightness)
+{
+        if (brightness < 1)
+                brightness = 0;
+
+        gpio_set_value(EXYNOS4_GPE2(3), 1);
+
+        return brightness;
+}
+
+static void nuri_bl_exit(struct device *dev)
+{
+        gpio_free(EXYNOS4_GPE2(3));
+}
+
+/* nuri pwm backlight */
+static struct platform_pwm_backlight_data nuri_backlight_data = {
+        .pwm_id                 = 0,
+        .pwm_period_ns          = 30000,
+        .max_brightness         = 100,
+        .dft_brightness         = 50,
+        .init                   = nuri_bl_init,
+        .notify                 = nuri_bl_notify,
+        .exit                   = nuri_bl_exit,
+};
+
+static struct platform_device nuri_backlight_device = {
+        .name                   = "pwm-backlight",
+        .id                     = -1,
+        .dev                    = {
+                .parent         = &s3c_device_timer[0].dev,
+                .platform_data  = &nuri_backlight_data,
+        },
+};
+
+static struct plat_lcd_data nuri_lcd_platform_data = {
+        .set_power              = nuri_lcd_power_on,
+};
+
+static struct platform_device nuri_lcd_device = {
+        .name                   = "platform-lcd",
+        .id                     = -1,
+        .dev                    = {
+                .platform_data  = &nuri_lcd_platform_data,
+        },
+};
+
+/* I2C1 */
+static struct i2c_board_info i2c1_devs[] __initdata = {
+        /* Gyro, To be updated */
+};
+
+/* GPIO I2C 5 (PMIC) */
+static struct i2c_board_info i2c5_devs[] __initdata = {
+        /* max8997, To be updated */
+};
+
+static struct platform_device *nuri_devices[] __initdata = {
+        /* Samsung Platform Devices */
+        &emmc_fixed_voltage,
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc2,
+        &s3c_device_hsmmc3,
+        &s3c_device_wdt,
+        &s3c_device_timer[0],
+
+        /* NURI Devices */
+        &nuri_gpio_keys,
+        &nuri_lcd_device,
+        &nuri_backlight_device,
+};
+
+static void __init nuri_map_io(void)
+{
+        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s3c24xx_init_clocks(24000000);
+        s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
+}
+
+static void __init nuri_machine_init(void)
+{
+        nuri_sdhci_init();
+
+        i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
+        i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
+
+        /* Last */
+        platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
+}
+
+MACHINE_START(NURI, "NURI")
+        /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
+        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .init_irq       = exynos4_init_irq,
+        .map_io         = nuri_map_io,
+        .init_machine   = nuri_machine_init,
+        .timer          = &exynos4_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c
index d9cab02e23ca..25a256818122 100644
--- a/arch/arm/mach-s5pv310/mach-smdkc210.c
+++ b/arch/arm/mach-exynos4/mach-smdkc210.c
@@ -1,7 +1,7 @@
-/* linux/arch/arm/mach-s5pv310/mach-smdkc210.c
+/* linux/arch/arm/mach-exynos4/mach-smdkc210.c
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -21,7 +21,7 @@
 
 #include <plat/regs-serial.h>
 #include <plat/regs-srom.h>
-#include <plat/s5pv310.h>
+#include <plat/exynos4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/sdhci.h>
@@ -77,10 +77,10 @@ static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
 
 static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
         .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = S5PV310_GPK0(2),
+        .ext_cd_gpio            = EXYNOS4_GPK0(2),
         .ext_cd_gpio_invert     = 1,
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
         .max_width              = 8,
         .host_caps              = MMC_CAP_8_BIT_DATA,
 #endif
@@ -88,17 +88,17 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
 
 static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
         .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = S5PV310_GPK0(2),
+        .ext_cd_gpio            = EXYNOS4_GPK0(2),
         .ext_cd_gpio_invert     = 1,
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 
 static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
         .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = S5PV310_GPK2(2),
+        .ext_cd_gpio            = EXYNOS4_GPK2(2),
         .ext_cd_gpio_invert     = 1,
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
         .max_width              = 8,
         .host_caps              = MMC_CAP_8_BIT_DATA,
 #endif
@@ -106,15 +106,15 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
 
 static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
         .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = S5PV310_GPK2(2),
+        .ext_cd_gpio            = EXYNOS4_GPK2(2),
         .ext_cd_gpio_invert     = 1,
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 
 static struct resource smdkc210_smsc911x_resources[] = {
         [0] = {
-                .start  = S5PV310_PA_SROM_BANK(1),
-                .end    = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SROM_BANK(1),
+                .end    = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -154,16 +154,16 @@ static struct platform_device *smdkc210_devices[] __initdata = {
         &s3c_device_i2c1,
         &s3c_device_rtc,
         &s3c_device_wdt,
-        &s5pv310_device_ac97,
-        &s5pv310_device_i2s0,
-        &s5pv310_device_pd[PD_MFC],
-        &s5pv310_device_pd[PD_G3D],
-        &s5pv310_device_pd[PD_LCD0],
-        &s5pv310_device_pd[PD_LCD1],
-        &s5pv310_device_pd[PD_CAM],
-        &s5pv310_device_pd[PD_TV],
-        &s5pv310_device_pd[PD_GPS],
-        &s5pv310_device_sysmmu,
+        &exynos4_device_ac97,
+        &exynos4_device_i2s0,
+        &exynos4_device_pd[PD_MFC],
+        &exynos4_device_pd[PD_G3D],
+        &exynos4_device_pd[PD_LCD0],
+        &exynos4_device_pd[PD_LCD1],
+        &exynos4_device_pd[PD_CAM],
+        &exynos4_device_pd[PD_TV],
+        &exynos4_device_pd[PD_GPS],
+        &exynos4_device_sysmmu,
         &samsung_asoc_dma,
         &smdkc210_smsc911x,
 };
@@ -216,8 +216,8 @@ static void __init smdkc210_machine_init(void)
 MACHINE_START(SMDKC210, "SMDKC210")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
         .boot_params    = S5P_PA_SDRAM + 0x100,
-        .init_irq       = s5pv310_init_irq,
+        .init_irq       = exynos4_init_irq,
         .map_io         = smdkc210_map_io,
         .init_machine   = smdkc210_machine_init,
-        .timer          = &s5pv310_timer,
+        .timer          = &exynos4_timer,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index b1cddbf3c616..88e0275143be 100644
--- a/arch/arm/mach-s5pv310/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -1,7 +1,7 @@
-/* linux/arch/arm/mach-s5pv310/mach-smdkv310.c
+/* linux/arch/arm/mach-exynos4/mach-smdkv310.c
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -15,15 +15,17 @@
 #include <linux/smsc911x.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
+#include <linux/input.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
 #include <plat/regs-serial.h>
 #include <plat/regs-srom.h>
-#include <plat/s5pv310.h>
+#include <plat/exynos4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
+#include <plat/keypad.h>
 #include <plat/sdhci.h>
 #include <plat/iic.h>
 #include <plat/pd.h>
@@ -77,10 +79,10 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
 
 static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
         .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = S5PV310_GPK0(2),
+        .ext_cd_gpio            = EXYNOS4_GPK0(2),
         .ext_cd_gpio_invert     = 1,
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
+#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
         .max_width              = 8,
         .host_caps              = MMC_CAP_8_BIT_DATA,
 #endif
@@ -88,17 +90,17 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
 
 static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
         .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = S5PV310_GPK0(2),
+        .ext_cd_gpio            = EXYNOS4_GPK0(2),
         .ext_cd_gpio_invert     = 1,
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 
 static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
         .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = S5PV310_GPK2(2),
+        .ext_cd_gpio            = EXYNOS4_GPK2(2),
         .ext_cd_gpio_invert     = 1,
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
         .max_width              = 8,
         .host_caps              = MMC_CAP_8_BIT_DATA,
 #endif
@@ -106,15 +108,15 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
 
 static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
         .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = S5PV310_GPK2(2),
+        .ext_cd_gpio            = EXYNOS4_GPK2(2),
         .ext_cd_gpio_invert     = 1,
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 
 static struct resource smdkv310_smsc911x_resources[] = {
         [0] = {
-                .start  = S5PV310_PA_SROM_BANK(1),
-                .end    = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1,
+                .start  = EXYNOS4_PA_SROM_BANK(1),
+                .end    = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -142,6 +144,25 @@ static struct platform_device smdkv310_smsc911x = {
         },
 };
 
+static uint32_t smdkv310_keymap[] __initdata = {
+        /* KEY(row, col, keycode) */
+        KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
+        KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
+        KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
+        KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
+};
+
+static struct matrix_keymap_data smdkv310_keymap_data __initdata = {
+        .keymap         = smdkv310_keymap,
+        .keymap_size    = ARRAY_SIZE(smdkv310_keymap),
+};
+
+static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = {
+        .keymap_data    = &smdkv310_keymap_data,
+        .rows           = 2,
+        .cols           = 8,
+};
+
 static struct i2c_board_info i2c_devs1[] __initdata = {
         {I2C_BOARD_INFO("wm8994", 0x1a),},
 };
@@ -154,16 +175,17 @@ static struct platform_device *smdkv310_devices[] __initdata = {
         &s3c_device_i2c1,
         &s3c_device_rtc,
         &s3c_device_wdt,
-        &s5pv310_device_ac97,
-        &s5pv310_device_i2s0,
-        &s5pv310_device_pd[PD_MFC],
-        &s5pv310_device_pd[PD_G3D],
-        &s5pv310_device_pd[PD_LCD0],
-        &s5pv310_device_pd[PD_LCD1],
-        &s5pv310_device_pd[PD_CAM],
-        &s5pv310_device_pd[PD_TV],
-        &s5pv310_device_pd[PD_GPS],
-        &s5pv310_device_sysmmu,
+        &exynos4_device_ac97,
+        &exynos4_device_i2s0,
+        &samsung_device_keypad,
+        &exynos4_device_pd[PD_MFC],
+        &exynos4_device_pd[PD_G3D],
+        &exynos4_device_pd[PD_LCD0],
+        &exynos4_device_pd[PD_LCD1],
+        &exynos4_device_pd[PD_CAM],
+        &exynos4_device_pd[PD_TV],
+        &exynos4_device_pd[PD_GPS],
+        &exynos4_device_sysmmu,
         &samsung_asoc_dma,
         &smdkv310_smsc911x,
 };
@@ -210,6 +232,8 @@ static void __init smdkv310_machine_init(void)
         s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
         s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
 
+        samsung_keypad_set_platdata(&smdkv310_keypad_data);
+
         platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
 }
 
@@ -217,8 +241,8 @@ MACHINE_START(SMDKV310, "SMDKV310")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
         /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
         .boot_params    = S5P_PA_SDRAM + 0x100,
-        .init_irq       = s5pv310_init_irq,
+        .init_irq       = exynos4_init_irq,
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
-        .timer          = &s5pv310_timer,
+        .timer          = &exynos4_timer,
 MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
new file mode 100644
index 000000000000..97d329fff2cf
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -0,0 +1,650 @@
+/* linux/arch/arm/mach-exynos4/mach-universal_c210.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio.h>
+#include <linux/mfd/max8998.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/max8952.h>
+#include <linux/mmc/host.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <plat/exynos4.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/iic.h>
+#include <plat/sdhci.h>
+
+#include <mach/map.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define UNIVERSAL_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |        \
+                                 S3C2410_UCON_RXILEVEL |        \
+                                 S3C2410_UCON_TXIRQMODE |       \
+                                 S3C2410_UCON_RXIRQMODE |       \
+                                 S3C2410_UCON_RXFIFO_TOI |      \
+                                 S3C2443_UCON_RXERR_IRQEN)
+
+#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
+
+#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE |       \
+                                 S5PV210_UFCON_TXTRIG256 |      \
+                                 S5PV210_UFCON_RXTRIG256)
+
+static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport         = 0,
+                .ucon           = UNIVERSAL_UCON_DEFAULT,
+                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
+                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
+        },
+        [1] = {
+                .hwport         = 1,
+                .ucon           = UNIVERSAL_UCON_DEFAULT,
+                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
+                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
+        },
+        [2] = {
+                .hwport         = 2,
+                .ucon           = UNIVERSAL_UCON_DEFAULT,
+                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
+                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
+        },
+        [3] = {
+                .hwport         = 3,
+                .ucon           = UNIVERSAL_UCON_DEFAULT,
+                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
+                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
+        },
+};
+
+static struct regulator_consumer_supply max8952_consumer =
+        REGULATOR_SUPPLY("vddarm", NULL);
+
+static struct max8952_platform_data universal_max8952_pdata __initdata = {
+        .gpio_vid0      = EXYNOS4_GPX0(3),
+        .gpio_vid1      = EXYNOS4_GPX0(4),
+        .gpio_en        = -1, /* Not controllable, set "Always High" */
+        .default_mode   = 0, /* vid0 = 0, vid1 = 0 */
+        .dvs_mode       = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
+        .sync_freq      = 0, /* default: fastest */
+        .ramp_speed     = 0, /* default: fastest */
+
+        .reg_data       = {
+                .constraints    = {
+                        .name           = "VARM_1.2V",
+                        .min_uV         = 770000,
+                        .max_uV         = 1400000,
+                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                        .always_on      = 1,
+                        .boot_on        = 1,
+                },
+                .num_consumer_supplies  = 1,
+                .consumer_supplies      = &max8952_consumer,
+        },
+};
+
+static struct regulator_consumer_supply lp3974_buck1_consumer =
+        REGULATOR_SUPPLY("vddint", NULL);
+
+static struct regulator_consumer_supply lp3974_buck2_consumer =
+        REGULATOR_SUPPLY("vddg3d", NULL);
+
+static struct regulator_init_data lp3974_buck1_data = {
+        .constraints    = {
+                .name           = "VINT_1.1V",
+                .min_uV         = 750000,
+                .max_uV         = 1500000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                        REGULATOR_CHANGE_STATUS,
+                .boot_on        = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies = 1,
+        .consumer_supplies = &lp3974_buck1_consumer,
+};
+
+static struct regulator_init_data lp3974_buck2_data = {
+        .constraints    = {
+                .name           = "VG3D_1.1V",
+                .min_uV         = 750000,
+                .max_uV         = 1500000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                        REGULATOR_CHANGE_STATUS,
+                .boot_on        = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies = 1,
+        .consumer_supplies = &lp3974_buck2_consumer,
+};
+
+static struct regulator_init_data lp3974_buck3_data = {
+        .constraints    = {
+                .name           = "VCC_1.8V",
+                .min_uV         = 1800000,
+                .max_uV         = 1800000,
+                .apply_uV       = 1,
+                .always_on      = 1,
+                .state_mem      = {
+                        .enabled        = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_buck4_data = {
+        .constraints    = {
+                .name           = "VMEM_1.2V",
+                .min_uV         = 1200000,
+                .max_uV         = 1200000,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .apply_uV       = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_ldo2_data = {
+        .constraints    = {
+                .name           = "VALIVE_1.2V",
+                .min_uV         = 1200000,
+                .max_uV         = 1200000,
+                .apply_uV       = 1,
+                .always_on      = 1,
+                .state_mem      = {
+                        .enabled        = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_ldo3_data = {
+        .constraints    = {
+                .name           = "VUSB+MIPI_1.1V",
+                .min_uV         = 1100000,
+                .max_uV         = 1100000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_ldo4_data = {
+        .constraints    = {
+                .name           = "VADC_3.3V",
+                .min_uV         = 3300000,
+                .max_uV         = 3300000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_ldo5_data = {
+        .constraints    = {
+                .name           = "VTF_2.8V",
+                .min_uV         = 2800000,
+                .max_uV         = 2800000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_ldo6_data = {
+        .constraints    = {
+                .name           = "LDO6",
+                .min_uV         = 2000000,
+                .max_uV         = 2000000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_ldo7_data = {
+        .constraints    = {
+                .name           = "VLCD+VMIPI_1.8V",
+                .min_uV         = 1800000,
+                .max_uV         = 1800000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_ldo8_data = {
+        .constraints    = {
+                .name           = "VUSB+VDAC_3.3V",
+                .min_uV         = 3300000,
+                .max_uV         = 3300000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_ldo9_data = {
+        .constraints    = {
+                .name           = "VCC_2.8V",
+                .min_uV         = 2800000,
+                .max_uV         = 2800000,
+                .apply_uV       = 1,
+                .always_on      = 1,
+                .state_mem      = {
+                        .enabled        = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_ldo10_data = {
+        .constraints    = {
+                .name           = "VPLL_1.1V",
+                .min_uV         = 1100000,
+                .max_uV         = 1100000,
+                .boot_on        = 1,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_ldo11_data = {
+        .constraints    = {
+                .name           = "CAM_AF_3.3V",
+                .min_uV         = 3300000,
+                .max_uV         = 3300000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_ldo12_data = {
+        .constraints    = {
+                .name           = "PS_2.8V",
+                .min_uV         = 2800000,
+                .max_uV         = 2800000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_ldo13_data = {
+        .constraints    = {
+                .name           = "VHIC_1.2V",
+                .min_uV         = 1200000,
+                .max_uV         = 1200000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_ldo14_data = {
+        .constraints    = {
+                .name           = "CAM_I_HOST_1.8V",
+                .min_uV         = 1800000,
+                .max_uV         = 1800000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_ldo15_data = {
+        .constraints    = {
+                .name           = "CAM_S_DIG+FM33_CORE_1.2V",
+                .min_uV         = 1200000,
+                .max_uV         = 1200000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_ldo16_data = {
+        .constraints    = {
+                .name           = "CAM_S_ANA_2.8V",
+                .min_uV         = 2800000,
+                .max_uV         = 2800000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_ldo17_data = {
+        .constraints    = {
+                .name           = "VCC_3.0V_LCD",
+                .min_uV         = 3000000,
+                .max_uV         = 3000000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .boot_on        = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_32khz_ap_data = {
+        .constraints    = {
+                .name           = "32KHz AP",
+                .always_on      = 1,
+                .state_mem      = {
+                        .enabled        = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_32khz_cp_data = {
+        .constraints    = {
+                .name           = "32KHz CP",
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_vichg_data = {
+        .constraints    = {
+                .name           = "VICHG",
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_esafeout1_data = {
+        .constraints    = {
+                .name           = "SAFEOUT1",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .enabled        = 1,
+                },
+        },
+};
+
+static struct regulator_init_data lp3974_esafeout2_data = {
+        .constraints    = {
+                .name           = "SAFEOUT2",
+                .boot_on        = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .enabled        = 1,
+                },
+        },
+};
+
+static struct max8998_regulator_data lp3974_regulators[] = {
+        { MAX8998_LDO2,  &lp3974_ldo2_data },
+        { MAX8998_LDO3,  &lp3974_ldo3_data },
+        { MAX8998_LDO4,  &lp3974_ldo4_data },
+        { MAX8998_LDO5,  &lp3974_ldo5_data },
+        { MAX8998_LDO6,  &lp3974_ldo6_data },
+        { MAX8998_LDO7,  &lp3974_ldo7_data },
+        { MAX8998_LDO8,  &lp3974_ldo8_data },
+        { MAX8998_LDO9,  &lp3974_ldo9_data },
+        { MAX8998_LDO10, &lp3974_ldo10_data },
+        { MAX8998_LDO11, &lp3974_ldo11_data },
+        { MAX8998_LDO12, &lp3974_ldo12_data },
+        { MAX8998_LDO13, &lp3974_ldo13_data },
+        { MAX8998_LDO14, &lp3974_ldo14_data },
+        { MAX8998_LDO15, &lp3974_ldo15_data },
+        { MAX8998_LDO16, &lp3974_ldo16_data },
+        { MAX8998_LDO17, &lp3974_ldo17_data },
+        { MAX8998_BUCK1, &lp3974_buck1_data },
+        { MAX8998_BUCK2, &lp3974_buck2_data },
+        { MAX8998_BUCK3, &lp3974_buck3_data },
+        { MAX8998_BUCK4, &lp3974_buck4_data },
+        { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },
+        { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },
+        { MAX8998_ENVICHG, &lp3974_vichg_data },
+        { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },
+        { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },
+};
+
+static struct max8998_platform_data universal_lp3974_pdata = {
+        .num_regulators         = ARRAY_SIZE(lp3974_regulators),
+        .regulators             = lp3974_regulators,
+        .buck1_voltage1         = 1100000,      /* INT */
+        .buck1_voltage2         = 1000000,
+        .buck1_voltage3         = 1100000,
+        .buck1_voltage4         = 1000000,
+        .buck1_set1             = EXYNOS4_GPX0(5),
+        .buck1_set2             = EXYNOS4_GPX0(6),
+        .buck2_voltage1         = 1200000,      /* G3D */
+        .buck2_voltage2         = 1100000,
+        .buck1_default_idx      = 0,
+        .buck2_set3             = EXYNOS4_GPE2(0),
+        .buck2_default_idx      = 0,
+        .wakeup                 = true,
+};
+
+/* GPIO I2C 5 (PMIC) */
+static struct i2c_board_info i2c5_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("max8952", 0xC0 >> 1),
+                .platform_data  = &universal_max8952_pdata,
+        }, {
+                I2C_BOARD_INFO("lp3974", 0xCC >> 1),
+                .platform_data  = &universal_lp3974_pdata,
+        },
+};
+
+/* GPIO KEYS */
+static struct gpio_keys_button universal_gpio_keys_tables[] = {
+        {
+                .code                   = KEY_VOLUMEUP,
+                .gpio                   = EXYNOS4_GPX2(0),      /* XEINT16 */
+                .desc                   = "gpio-keys: KEY_VOLUMEUP",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .debounce_interval      = 1,
+        }, {
+                .code                   = KEY_VOLUMEDOWN,
+                .gpio                   = EXYNOS4_GPX2(1),      /* XEINT17 */
+                .desc                   = "gpio-keys: KEY_VOLUMEDOWN",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .debounce_interval      = 1,
+        }, {
+                .code                   = KEY_CONFIG,
+                .gpio                   = EXYNOS4_GPX2(2),      /* XEINT18 */
+                .desc                   = "gpio-keys: KEY_CONFIG",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .debounce_interval      = 1,
+        }, {
+                .code                   = KEY_CAMERA,
+                .gpio                   = EXYNOS4_GPX2(3),      /* XEINT19 */
+                .desc                   = "gpio-keys: KEY_CAMERA",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .debounce_interval      = 1,
+        }, {
+                .code                   = KEY_OK,
+                .gpio                   = EXYNOS4_GPX3(5),      /* XEINT29 */
+                .desc                   = "gpio-keys: KEY_OK",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .debounce_interval      = 1,
+        },
+};
+
+static struct gpio_keys_platform_data universal_gpio_keys_data = {
+        .buttons        = universal_gpio_keys_tables,
+        .nbuttons       = ARRAY_SIZE(universal_gpio_keys_tables),
+};
+
+static struct platform_device universal_gpio_keys = {
+        .name                   = "gpio-keys",
+        .dev                    = {
+                .platform_data  = &universal_gpio_keys_data,
+        },
+};
+
+/* eMMC */
+static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
+        .max_width              = 8,
+        .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+                                MMC_CAP_DISABLE),
+        .cd_type                = S3C_SDHCI_CD_PERMANENT,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct regulator_consumer_supply mmc0_supplies[] = {
+        REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
+};
+
+static struct regulator_init_data mmc0_fixed_voltage_init_data = {
+        .constraints            = {
+                .name           = "VMEM_VDD_2.8V",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(mmc0_supplies),
+        .consumer_supplies      = mmc0_supplies,
+};
+
+static struct fixed_voltage_config mmc0_fixed_voltage_config = {
+        .supply_name            = "MASSMEMORY_EN",
+        .microvolts             = 2800000,
+        .gpio                   = EXYNOS4_GPE1(3),
+        .enable_high            = true,
+        .init_data              = &mmc0_fixed_voltage_init_data,
+};
+
+static struct platform_device mmc0_fixed_voltage = {
+        .name                   = "reg-fixed-voltage",
+        .id                     = 0,
+        .dev                    = {
+                .platform_data  = &mmc0_fixed_voltage_config,
+        },
+};
+
+/* SD */
+static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
+        .max_width              = 4,
+        .host_caps              = MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+                                MMC_CAP_DISABLE,
+        .ext_cd_gpio            = EXYNOS4_GPX3(4),      /* XEINT_28 */
+        .ext_cd_gpio_invert     = 1,
+        .cd_type                = S3C_SDHCI_CD_GPIO,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+/* WiFi */
+static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
+        .max_width              = 4,
+        .host_caps              = MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+                                MMC_CAP_DISABLE,
+        .cd_type                = S3C_SDHCI_CD_EXTERNAL,
+};
+
+static void __init universal_sdhci_init(void)
+{
+        s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
+        s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
+        s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
+}
+
+/* I2C0 */
+static struct i2c_board_info i2c0_devs[] __initdata = {
+        /* Camera, To be updated */
+};
+
+/* I2C1 */
+static struct i2c_board_info i2c1_devs[] __initdata = {
+        /* Gyro, To be updated */
+};
+
+static struct platform_device *universal_devices[] __initdata = {
+        /* Samsung Platform Devices */
+        &mmc0_fixed_voltage,
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc2,
+        &s3c_device_hsmmc3,
+        &s3c_device_i2c5,
+
+        /* Universal Devices */
+        &universal_gpio_keys,
+        &s5p_device_onenand,
+};
+
+static void __init universal_map_io(void)
+{
+        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s3c24xx_init_clocks(24000000);
+        s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
+}
+
+static void __init universal_machine_init(void)
+{
+        universal_sdhci_init();
+
+        i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
+        i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
+
+        s3c_i2c5_set_platdata(NULL);
+        i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
+
+        /* Last */
+        platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
+}
+
+MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
+        /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
+        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .init_irq       = exynos4_init_irq,
+        .map_io         = universal_map_io,
+        .init_machine   = universal_machine_init,
+        .timer          = &exynos4_timer,
+MACHINE_END
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
new file mode 100644
index 000000000000..af82a8fbb68b
--- /dev/null
+++ b/arch/arm/mach-exynos4/mct.c
@@ -0,0 +1,421 @@
+/* linux/arch/arm/mach-exynos4/mct.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4 MCT(Multi-Core Timer) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/percpu.h>
+
+#include <mach/map.h>
+#include <mach/regs-mct.h>
+#include <asm/mach/time.h>
+
+static unsigned long clk_cnt_per_tick;
+static unsigned long clk_rate;
+
+struct mct_clock_event_device {
+        struct clock_event_device *evt;
+        void __iomem *base;
+};
+
+struct mct_clock_event_device mct_tick[2];
+
+static void exynos4_mct_write(unsigned int value, void *addr)
+{
+        void __iomem *stat_addr;
+        u32 mask;
+        u32 i;
+
+        __raw_writel(value, addr);
+
+        switch ((u32) addr) {
+        case (u32) EXYNOS4_MCT_G_TCON:
+                stat_addr = EXYNOS4_MCT_G_WSTAT;
+                mask = 1 << 16;         /* G_TCON write status */
+                break;
+        case (u32) EXYNOS4_MCT_G_COMP0_L:
+                stat_addr = EXYNOS4_MCT_G_WSTAT;
+                mask = 1 << 0;          /* G_COMP0_L write status */
+                break;
+        case (u32) EXYNOS4_MCT_G_COMP0_U:
+                stat_addr = EXYNOS4_MCT_G_WSTAT;
+                mask = 1 << 1;          /* G_COMP0_U write status */
+                break;
+        case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
+                stat_addr = EXYNOS4_MCT_G_WSTAT;
+                mask = 1 << 2;          /* G_COMP0_ADD_INCR write status */
+                break;
+        case (u32) EXYNOS4_MCT_G_CNT_L:
+                stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+                mask = 1 << 0;          /* G_CNT_L write status */
+                break;
+        case (u32) EXYNOS4_MCT_G_CNT_U:
+                stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+                mask = 1 << 1;          /* G_CNT_U write status */
+                break;
+        case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET):
+                stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
+                mask = 1 << 3;          /* L0_TCON write status */
+                break;
+        case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET):
+                stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
+                mask = 1 << 3;          /* L1_TCON write status */
+                break;
+        case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET):
+                stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
+                mask = 1 << 0;          /* L0_TCNTB write status */
+                break;
+        case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET):
+                stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
+                mask = 1 << 0;          /* L1_TCNTB write status */
+                break;
+        case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET):
+                stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
+                mask = 1 << 1;          /* L0_ICNTB write status */
+                break;
+        case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET):
+                stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
+                mask = 1 << 1;          /* L1_ICNTB write status */
+                break;
+        default:
+                return;
+        }
+
+        /* Wait maximum 1 ms until written values are applied */
+        for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
+                if (__raw_readl(stat_addr) & mask) {
+                        __raw_writel(mask, stat_addr);
+                        return;
+                }
+
+        panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
+}
+
+/* Clocksource handling */
+static void exynos4_mct_frc_start(u32 hi, u32 lo)
+{
+        u32 reg;
+
+        exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
+        exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
+
+        reg = __raw_readl(EXYNOS4_MCT_G_TCON);
+        reg |= MCT_G_TCON_START;
+        exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
+}
+
+static cycle_t exynos4_frc_read(struct clocksource *cs)
+{
+        unsigned int lo, hi;
+        u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+
+        do {
+                hi = hi2;
+                lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
+                hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+        } while (hi != hi2);
+
+        return ((cycle_t)hi << 32) | lo;
+}
+
+struct clocksource mct_frc = {
+        .name           = "mct-frc",
+        .rating         = 400,
+        .read           = exynos4_frc_read,
+        .mask           = CLOCKSOURCE_MASK(64),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __init exynos4_clocksource_init(void)
+{
+        exynos4_mct_frc_start(0, 0);
+
+        if (clocksource_register_hz(&mct_frc, clk_rate))
+                panic("%s: can't register clocksource\n", mct_frc.name);
+}
+
+static void exynos4_mct_comp0_stop(void)
+{
+        unsigned int tcon;
+
+        tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
+        tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
+
+        exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
+        exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
+}
+
+static void exynos4_mct_comp0_start(enum clock_event_mode mode,
+                                    unsigned long cycles)
+{
+        unsigned int tcon;
+        cycle_t comp_cycle;
+
+        tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
+
+        if (mode == CLOCK_EVT_MODE_PERIODIC) {
+                tcon |= MCT_G_TCON_COMP0_AUTO_INC;
+                exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
+        }
+
+        comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
+        exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
+        exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
+
+        exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
+
+        tcon |= MCT_G_TCON_COMP0_ENABLE;
+        exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
+}
+
+static int exynos4_comp_set_next_event(unsigned long cycles,
+                                       struct clock_event_device *evt)
+{
+        exynos4_mct_comp0_start(evt->mode, cycles);
+
+        return 0;
+}
+
+static void exynos4_comp_set_mode(enum clock_event_mode mode,
+                                  struct clock_event_device *evt)
+{
+        exynos4_mct_comp0_stop();
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
+                break;
+
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+
+static struct clock_event_device mct_comp_device = {
+        .name           = "mct-comp",
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .rating         = 250,
+        .set_next_event = exynos4_comp_set_next_event,
+        .set_mode       = exynos4_comp_set_mode,
+};
+
+static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = dev_id;
+
+        exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction mct_comp_event_irq = {
+        .name           = "mct_comp_irq",
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = exynos4_mct_comp_isr,
+        .dev_id         = &mct_comp_device,
+};
+
+static void exynos4_clockevent_init(void)
+{
+        clk_cnt_per_tick = clk_rate / 2 / HZ;
+
+        clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
+        mct_comp_device.max_delta_ns =
+                clockevent_delta2ns(0xffffffff, &mct_comp_device);
+        mct_comp_device.min_delta_ns =
+                clockevent_delta2ns(0xf, &mct_comp_device);
+        mct_comp_device.cpumask = cpumask_of(0);
+        clockevents_register_device(&mct_comp_device);
+
+        setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
+}
+
+#ifdef CONFIG_LOCAL_TIMERS
+/* Clock event handling */
+static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
+{
+        unsigned long tmp;
+        unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
+        void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
+
+        tmp = __raw_readl(addr);
+        if (tmp & mask) {
+                tmp &= ~mask;
+                exynos4_mct_write(tmp, addr);
+        }
+}
+
+static void exynos4_mct_tick_start(unsigned long cycles,
+                                   struct mct_clock_event_device *mevt)
+{
+        unsigned long tmp;
+
+        exynos4_mct_tick_stop(mevt);
+
+        tmp = (1 << 31) | cycles;       /* MCT_L_UPDATE_ICNTB */
+
+        /* update interrupt count buffer */
+        exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
+
+        /* enable MCT tick interupt */
+        exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
+
+        tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
+        tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
+               MCT_L_TCON_INTERVAL_MODE;
+        exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
+}
+
+static int exynos4_tick_set_next_event(unsigned long cycles,
+                                       struct clock_event_device *evt)
+{
+        struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
+
+        exynos4_mct_tick_start(cycles, mevt);
+
+        return 0;
+}
+
+static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
+                                         struct clock_event_device *evt)
+{
+        struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
+
+        exynos4_mct_tick_stop(mevt);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                exynos4_mct_tick_start(clk_cnt_per_tick, mevt);
+                break;
+
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+
+static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
+{
+        struct mct_clock_event_device *mevt = dev_id;
+        struct clock_event_device *evt = mevt->evt;
+
+        /*
+         * This is for supporting oneshot mode.
+         * Mct would generate interrupt periodically
+         * without explicit stopping.
+         */
+        if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
+                exynos4_mct_tick_stop(mevt);
+
+        /* Clear the MCT tick interrupt */
+        exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction mct_tick0_event_irq = {
+        .name           = "mct_tick0_irq",
+        .flags          = IRQF_TIMER | IRQF_NOBALANCING,
+        .handler        = exynos4_mct_tick_isr,
+};
+
+static struct irqaction mct_tick1_event_irq = {
+        .name           = "mct_tick1_irq",
+        .flags          = IRQF_TIMER | IRQF_NOBALANCING,
+        .handler        = exynos4_mct_tick_isr,
+};
+
+static void exynos4_mct_tick_init(struct clock_event_device *evt)
+{
+        unsigned int cpu = smp_processor_id();
+
+        mct_tick[cpu].evt = evt;
+
+        if (cpu == 0) {
+                mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE;
+                evt->name = "mct_tick0";
+        } else {
+                mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE;
+                evt->name = "mct_tick1";
+        }
+
+        evt->cpumask = cpumask_of(cpu);
+        evt->set_next_event = exynos4_tick_set_next_event;
+        evt->set_mode = exynos4_tick_set_mode;
+        evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+        evt->rating = 450;
+
+        clockevents_calc_mult_shift(evt, clk_rate / 2, 5);
+        evt->max_delta_ns =
+                clockevent_delta2ns(0x7fffffff, evt);
+        evt->min_delta_ns =
+                clockevent_delta2ns(0xf, evt);
+
+        clockevents_register_device(evt);
+
+        exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
+
+        if (cpu == 0) {
+                mct_tick0_event_irq.dev_id = &mct_tick[cpu];
+                setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
+        } else {
+                mct_tick1_event_irq.dev_id = &mct_tick[cpu];
+                irq_set_affinity(IRQ_MCT1, cpumask_of(1));
+                setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
+        }
+}
+
+/* Setup the local clock events for a CPU */
+void __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+        exynos4_mct_tick_init(evt);
+}
+
+int local_timer_ack(void)
+{
+        return 0;
+}
+
+#endif /* CONFIG_LOCAL_TIMERS */
+
+static void __init exynos4_timer_resources(void)
+{
+        struct clk *mct_clk;
+        mct_clk = clk_get(NULL, "xtal");
+
+        clk_rate = clk_get_rate(mct_clk);
+}
+
+static void __init exynos4_timer_init(void)
+{
+        exynos4_timer_resources();
+        exynos4_clocksource_init();
+        exynos4_clockevent_init();
+}
+
+struct sys_timer exynos4_timer = {
+        .init           = exynos4_timer_init,
+};
diff --git a/arch/arm/mach-s5pv310/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index 34093b069f67..6d35878ec1aa 100644
--- a/arch/arm/mach-s5pv310/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -1,7 +1,7 @@
-/* linux/arch/arm/mach-s5pv310/platsmp.c
+/* linux/arch/arm/mach-exynos4/platsmp.c
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
  *
@@ -28,7 +28,7 @@
 #include <mach/hardware.h>
 #include <mach/regs-clock.h>
 
-extern void s5pv310_secondary_startup(void);
+extern void exynos4_secondary_startup(void);
 
 /*
  * control for which core is the next to come out of the secondary
@@ -139,7 +139,7 @@ void __init smp_init_cpus(void)
         /* sanity check */
         if (ncores > NR_CPUS) {
                 printk(KERN_WARNING
-                       "S5PV310: no. of cores (%d) greater than configured "
+                       "EXYNOS4: no. of cores (%d) greater than configured "
                        "maximum of %d - clipping\n",
                        ncores, NR_CPUS);
                 ncores = NR_CPUS;
@@ -168,5 +168,5 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
          * until it receives a soft interrupt, and then the
          * secondary CPU branches to this address.
          */
-        __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM);
+        __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
 }
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
new file mode 100644
index 000000000000..10d917d9e3ad
--- /dev/null
+++ b/arch/arm/mach-exynos4/pm.c
@@ -0,0 +1,420 @@
+/* linux/arch/arm/mach-exynos4/pm.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4210 - Power Management support
+ *
+ * Based on arch/arm/mach-s3c2410/pm.c
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-pmu.h>
+#include <mach/pm-core.h>
+
+static struct sleep_save exynos4_sleep[] = {
+        { .reg = S5P_ARM_CORE0_LOWPWR                   , .val = 0x2, },
+        { .reg = S5P_DIS_IRQ_CORE0                      , .val = 0x0, },
+        { .reg = S5P_DIS_IRQ_CENTRAL0                   , .val = 0x0, },
+        { .reg = S5P_ARM_CORE1_LOWPWR                   , .val = 0x2, },
+        { .reg = S5P_DIS_IRQ_CORE1                      , .val = 0x0, },
+        { .reg = S5P_DIS_IRQ_CENTRAL1                   , .val = 0x0, },
+        { .reg = S5P_ARM_COMMON_LOWPWR                  , .val = 0x2, },
+        { .reg = S5P_L2_0_LOWPWR                        , .val = 0x3, },
+        { .reg = S5P_L2_1_LOWPWR                        , .val = 0x3, },
+        { .reg = S5P_CMU_ACLKSTOP_LOWPWR                , .val = 0x0, },
+        { .reg = S5P_CMU_SCLKSTOP_LOWPWR                , .val = 0x0, },
+        { .reg = S5P_CMU_RESET_LOWPWR                   , .val = 0x0, },
+        { .reg = S5P_APLL_SYSCLK_LOWPWR                 , .val = 0x0, },
+        { .reg = S5P_MPLL_SYSCLK_LOWPWR                 , .val = 0x0, },
+        { .reg = S5P_VPLL_SYSCLK_LOWPWR                 , .val = 0x0, },
+        { .reg = S5P_EPLL_SYSCLK_LOWPWR                 , .val = 0x0, },
+        { .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR       , .val = 0x0, },
+        { .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR          , .val = 0x0, },
+        { .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR             , .val = 0x0, },
+        { .reg = S5P_CMU_CLKSTOP_TV_LOWPWR              , .val = 0x0, },
+        { .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR             , .val = 0x0, },
+        { .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR             , .val = 0x0, },
+        { .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR            , .val = 0x0, },
+        { .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR            , .val = 0x0, },
+        { .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR          , .val = 0x0, },
+        { .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR             , .val = 0x0, },
+        { .reg = S5P_CMU_RESET_CAM_LOWPWR               , .val = 0x0, },
+        { .reg = S5P_CMU_RESET_TV_LOWPWR                , .val = 0x0, },
+        { .reg = S5P_CMU_RESET_MFC_LOWPWR               , .val = 0x0, },
+        { .reg = S5P_CMU_RESET_G3D_LOWPWR               , .val = 0x0, },
+        { .reg = S5P_CMU_RESET_LCD0_LOWPWR              , .val = 0x0, },
+        { .reg = S5P_CMU_RESET_LCD1_LOWPWR              , .val = 0x0, },
+        { .reg = S5P_CMU_RESET_MAUDIO_LOWPWR            , .val = 0x0, },
+        { .reg = S5P_CMU_RESET_GPS_LOWPWR               , .val = 0x0, },
+        { .reg = S5P_TOP_BUS_LOWPWR                     , .val = 0x0, },
+        { .reg = S5P_TOP_RETENTION_LOWPWR               , .val = 0x1, },
+        { .reg = S5P_TOP_PWR_LOWPWR                     , .val = 0x3, },
+        { .reg = S5P_LOGIC_RESET_LOWPWR                 , .val = 0x0, },
+        { .reg = S5P_ONENAND_MEM_LOWPWR                 , .val = 0x0, },
+        { .reg = S5P_MODIMIF_MEM_LOWPWR                 , .val = 0x0, },
+        { .reg = S5P_G2D_ACP_MEM_LOWPWR                 , .val = 0x0, },
+        { .reg = S5P_USBOTG_MEM_LOWPWR                  , .val = 0x0, },
+        { .reg = S5P_HSMMC_MEM_LOWPWR                   , .val = 0x0, },
+        { .reg = S5P_CSSYS_MEM_LOWPWR                   , .val = 0x0, },
+        { .reg = S5P_SECSS_MEM_LOWPWR                   , .val = 0x0, },
+        { .reg = S5P_PCIE_MEM_LOWPWR                    , .val = 0x0, },
+        { .reg = S5P_SATA_MEM_LOWPWR                    , .val = 0x0, },
+        { .reg = S5P_PAD_RETENTION_DRAM_LOWPWR          , .val = 0x0, },
+        { .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR        , .val = 0x0, },
+        { .reg = S5P_PAD_RETENTION_GPIO_LOWPWR          , .val = 0x0, },
+        { .reg = S5P_PAD_RETENTION_UART_LOWPWR          , .val = 0x0, },
+        { .reg = S5P_PAD_RETENTION_MMCA_LOWPWR          , .val = 0x0, },
+        { .reg = S5P_PAD_RETENTION_MMCB_LOWPWR          , .val = 0x0, },
+        { .reg = S5P_PAD_RETENTION_EBIA_LOWPWR          , .val = 0x0, },
+        { .reg = S5P_PAD_RETENTION_EBIB_LOWPWR          , .val = 0x0, },
+        { .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR     , .val = 0x0, },
+        { .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR       , .val = 0x0, },
+        { .reg = S5P_XUSBXTI_LOWPWR                     , .val = 0x0, },
+        { .reg = S5P_XXTI_LOWPWR                        , .val = 0x0, },
+        { .reg = S5P_EXT_REGULATOR_LOWPWR               , .val = 0x0, },
+        { .reg = S5P_GPIO_MODE_LOWPWR                   , .val = 0x0, },
+        { .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR            , .val = 0x0, },
+        { .reg = S5P_CAM_LOWPWR                         , .val = 0x0, },
+        { .reg = S5P_TV_LOWPWR                          , .val = 0x0, },
+        { .reg = S5P_MFC_LOWPWR                         , .val = 0x0, },
+        { .reg = S5P_G3D_LOWPWR                         , .val = 0x0, },
+        { .reg = S5P_LCD0_LOWPWR                        , .val = 0x0, },
+        { .reg = S5P_LCD1_LOWPWR                        , .val = 0x0, },
+        { .reg = S5P_MAUDIO_LOWPWR                      , .val = 0x0, },
+        { .reg = S5P_GPS_LOWPWR                         , .val = 0x0, },
+        { .reg = S5P_GPS_ALIVE_LOWPWR                   , .val = 0x0, },
+};
+
+static struct sleep_save exynos4_set_clksrc[] = {
+        { .reg = S5P_CLKSRC_MASK_TOP                    , .val = 0x00000001, },
+        { .reg = S5P_CLKSRC_MASK_CAM                    , .val = 0x11111111, },
+        { .reg = S5P_CLKSRC_MASK_TV                     , .val = 0x00000111, },
+        { .reg = S5P_CLKSRC_MASK_LCD0                   , .val = 0x00001111, },
+        { .reg = S5P_CLKSRC_MASK_LCD1                   , .val = 0x00001111, },
+        { .reg = S5P_CLKSRC_MASK_MAUDIO                 , .val = 0x00000001, },
+        { .reg = S5P_CLKSRC_MASK_FSYS                   , .val = 0x01011111, },
+        { .reg = S5P_CLKSRC_MASK_PERIL0                 , .val = 0x01111111, },
+        { .reg = S5P_CLKSRC_MASK_PERIL1                 , .val = 0x01110111, },
+        { .reg = S5P_CLKSRC_MASK_DMC                    , .val = 0x00010000, },
+};
+
+static struct sleep_save exynos4_core_save[] = {
+        /* CMU side */
+        SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
+        SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
+        SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
+        SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
+        SAVE_ITEM(S5P_EPLL_CON0),
+        SAVE_ITEM(S5P_EPLL_CON1),
+        SAVE_ITEM(S5P_VPLL_CON0),
+        SAVE_ITEM(S5P_VPLL_CON1),
+        SAVE_ITEM(S5P_CLKSRC_TOP0),
+        SAVE_ITEM(S5P_CLKSRC_TOP1),
+        SAVE_ITEM(S5P_CLKSRC_CAM),
+        SAVE_ITEM(S5P_CLKSRC_MFC),
+        SAVE_ITEM(S5P_CLKSRC_IMAGE),
+        SAVE_ITEM(S5P_CLKSRC_LCD0),
+        SAVE_ITEM(S5P_CLKSRC_LCD1),
+        SAVE_ITEM(S5P_CLKSRC_MAUDIO),
+        SAVE_ITEM(S5P_CLKSRC_FSYS),
+        SAVE_ITEM(S5P_CLKSRC_PERIL0),
+        SAVE_ITEM(S5P_CLKSRC_PERIL1),
+        SAVE_ITEM(S5P_CLKDIV_CAM),
+        SAVE_ITEM(S5P_CLKDIV_TV),
+        SAVE_ITEM(S5P_CLKDIV_MFC),
+        SAVE_ITEM(S5P_CLKDIV_G3D),
+        SAVE_ITEM(S5P_CLKDIV_IMAGE),
+        SAVE_ITEM(S5P_CLKDIV_LCD0),
+        SAVE_ITEM(S5P_CLKDIV_LCD1),
+        SAVE_ITEM(S5P_CLKDIV_MAUDIO),
+        SAVE_ITEM(S5P_CLKDIV_FSYS0),
+        SAVE_ITEM(S5P_CLKDIV_FSYS1),
+        SAVE_ITEM(S5P_CLKDIV_FSYS2),
+        SAVE_ITEM(S5P_CLKDIV_FSYS3),
+        SAVE_ITEM(S5P_CLKDIV_PERIL0),
+        SAVE_ITEM(S5P_CLKDIV_PERIL1),
+        SAVE_ITEM(S5P_CLKDIV_PERIL2),
+        SAVE_ITEM(S5P_CLKDIV_PERIL3),
+        SAVE_ITEM(S5P_CLKDIV_PERIL4),
+        SAVE_ITEM(S5P_CLKDIV_PERIL5),
+        SAVE_ITEM(S5P_CLKDIV_TOP),
+        SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
+        SAVE_ITEM(S5P_CLKSRC_MASK_TV),
+        SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
+        SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
+        SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
+        SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
+        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
+        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
+        SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
+        SAVE_ITEM(S5P_CLKGATE_IP_CAM),
+        SAVE_ITEM(S5P_CLKGATE_IP_TV),
+        SAVE_ITEM(S5P_CLKGATE_IP_MFC),
+        SAVE_ITEM(S5P_CLKGATE_IP_G3D),
+        SAVE_ITEM(S5P_CLKGATE_IP_IMAGE),
+        SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
+        SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
+        SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
+        SAVE_ITEM(S5P_CLKGATE_IP_GPS),
+        SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
+        SAVE_ITEM(S5P_CLKGATE_IP_PERIR),
+        SAVE_ITEM(S5P_CLKGATE_BLOCK),
+        SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
+        SAVE_ITEM(S5P_CLKSRC_DMC),
+        SAVE_ITEM(S5P_CLKDIV_DMC0),
+        SAVE_ITEM(S5P_CLKDIV_DMC1),
+        SAVE_ITEM(S5P_CLKGATE_IP_DMC),
+        SAVE_ITEM(S5P_CLKSRC_CPU),
+        SAVE_ITEM(S5P_CLKDIV_CPU),
+        SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
+        SAVE_ITEM(S5P_CLKGATE_IP_CPU),
+        /* GIC side */
+        SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
+        SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
+        SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
+        SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
+        SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
+        SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
+
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
+
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
+        SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
+
+        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
+        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
+        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
+        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
+        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
+        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
+        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
+        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
+        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
+        SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
+};
+
+static struct sleep_save exynos4_l2cc_save[] = {
+        SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL),
+        SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL),
+        SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL),
+        SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL),
+        SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
+};
+
+void exynos4_cpu_suspend(void)
+{
+        unsigned long tmp;
+        unsigned long mask = 0xFFFFFFFF;
+
+        /* Setting Central Sequence Register for power down mode */
+
+        tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+        tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
+        __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+        /* Setting Central Sequence option Register */
+
+        tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
+        tmp &= ~(S5P_USE_MASK);
+        tmp |= S5P_USE_STANDBY_WFI0;
+        __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+
+        /* Clear all interrupt pending to avoid early wakeup */
+
+        __raw_writel(mask, (S5P_VA_GIC_DIST + 0x280));
+        __raw_writel(mask, (S5P_VA_GIC_DIST + 0x284));
+        __raw_writel(mask, (S5P_VA_GIC_DIST + 0x288));
+
+        /* Disable all interrupt */
+
+        __raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000));
+        __raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000));
+        __raw_writel(mask, (S5P_VA_GIC_DIST + 0x184));
+        __raw_writel(mask, (S5P_VA_GIC_DIST + 0x188));
+
+        outer_flush_all();
+
+        /* issue the standby signal into the pm unit. */
+        cpu_do_idle();
+
+        /* we should never get past here */
+        panic("sleep resumed to originator?");
+}
+
+static void exynos4_pm_prepare(void)
+{
+        u32 tmp;
+
+        s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
+        s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
+
+        tmp = __raw_readl(S5P_INFORM1);
+
+        /* Set value of power down register for sleep mode */
+
+        s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep));
+        __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
+
+        /* ensure at least INFORM0 has the resume address */
+
+        __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
+
+        /* Before enter central sequence mode, clock src register have to set */
+
+        s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
+
+}
+
+static int exynos4_pm_add(struct sys_device *sysdev)
+{
+        pm_cpu_prep = exynos4_pm_prepare;
+        pm_cpu_sleep = exynos4_cpu_suspend;
+
+        return 0;
+}
+
+/* This function copy from linux/arch/arm/kernel/smp_scu.c */
+
+void exynos4_scu_enable(void __iomem *scu_base)
+{
+        u32 scu_ctrl;
+
+        scu_ctrl = __raw_readl(scu_base);
+        /* already enabled? */
+        if (scu_ctrl & 1)
+                return;
+
+        scu_ctrl |= 1;
+        __raw_writel(scu_ctrl, scu_base);
+
+        /*
+         * Ensure that the data accessed by CPU0 before the SCU was
+         * initialised is visible to the other CPUs.
+         */
+        flush_cache_all();
+}
+
+static int exynos4_pm_resume(struct sys_device *dev)
+{
+        /* For release retention */
+
+        __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
+        __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
+        __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
+        __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
+        __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
+        __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
+        __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
+
+        s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
+
+        exynos4_scu_enable(S5P_VA_SCU);
+
+#ifdef CONFIG_CACHE_L2X0
+        s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
+        outer_inv_all();
+        /* enable L2X0*/
+        writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
+#endif
+
+        return 0;
+}
+
+static struct sysdev_driver exynos4_pm_driver = {
+        .add            = exynos4_pm_add,
+        .resume         = exynos4_pm_resume,
+};
+
+static __init int exynos4_pm_drvinit(void)
+{
+        unsigned int tmp;
+
+        s3c_pm_init();
+
+        /* All wakeup disable */
+
+        tmp = __raw_readl(S5P_WAKEUP_MASK);
+        tmp |= ((0xFF << 8) | (0x1F << 1));
+        __raw_writel(tmp, S5P_WAKEUP_MASK);
+
+        return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
+}
+arch_initcall(exynos4_pm_drvinit);
diff --git a/arch/arm/mach-exynos4/setup-fimc.c b/arch/arm/mach-exynos4/setup-fimc.c
new file mode 100644
index 000000000000..6a45078d9d12
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-fimc.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *
+ * Exynos4 camera interface GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+#include <plat/camport.h>
+
+int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
+{
+        u32 gpio8, gpio5;
+        u32 sfn;
+        int ret;
+
+        switch (id) {
+        case S5P_CAMPORT_A:
+                gpio8 = EXYNOS4_GPJ0(0); /* PCLK, VSYNC, HREF, DATA[0:4] */
+                gpio5 = EXYNOS4_GPJ1(0); /* DATA[5:7], CLKOUT, FIELD */
+                sfn = S3C_GPIO_SFN(2);
+                break;
+
+        case S5P_CAMPORT_B:
+                gpio8 = EXYNOS4_GPE0(0); /* DATA[0:7] */
+                gpio5 = EXYNOS4_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
+                sfn = S3C_GPIO_SFN(3);
+                break;
+
+        default:
+                WARN(1, "Wrong camport id: %d\n", id);
+                return -EINVAL;
+        }
+
+        ret = s3c_gpio_cfgall_range(gpio8, 8, sfn, S3C_GPIO_PULL_UP);
+        if (ret)
+                return ret;
+
+        return s3c_gpio_cfgall_range(gpio5, 5, sfn, S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-s5pv310/setup-i2c0.c b/arch/arm/mach-exynos4/setup-i2c0.c
index f47f8f3152ec..d395bd17c38b 100644
--- a/arch/arm/mach-s5pv310/setup-i2c0.c
+++ b/arch/arm/mach-exynos4/setup-i2c0.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-s5pv310/setup-i2c0.c
+ * linux/arch/arm/mach-exynos4/setup-i2c0.c
  *
  * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
@@ -21,6 +21,6 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgall_range(S5PV310_GPD1(0), 2,
+        s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
                               S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5pv310/setup-i2c1.c b/arch/arm/mach-exynos4/setup-i2c1.c
index 9d07e4e2f14c..fd7235a43f6e 100644
--- a/arch/arm/mach-s5pv310/setup-i2c1.c
+++ b/arch/arm/mach-exynos4/setup-i2c1.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-s5pv310/setup-i2c1.c
+ * linux/arch/arm/mach-exynos4/setup-i2c1.c
  *
  * Copyright (C) 2010 Samsung Electronics Co., Ltd.
  *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgall_range(S5PV310_GPD1(2), 2,
+        s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2,
                               S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5pv310/setup-i2c2.c b/arch/arm/mach-exynos4/setup-i2c2.c
index 4163b1233daf..2694b19e8b37 100644
--- a/arch/arm/mach-s5pv310/setup-i2c2.c
+++ b/arch/arm/mach-exynos4/setup-i2c2.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-s5pv310/setup-i2c2.c
+ * linux/arch/arm/mach-exynos4/setup-i2c2.c
  *
  * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
  *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c2_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgall_range(S5PV310_GPA0(6), 2,
+        s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2,
                               S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5pv310/setup-i2c3.c b/arch/arm/mach-exynos4/setup-i2c3.c
index 180f153d2a20..379bd306993f 100644
--- a/arch/arm/mach-s5pv310/setup-i2c3.c
+++ b/arch/arm/mach-exynos4/setup-i2c3.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-s5pv310/setup-i2c3.c
+ * linux/arch/arm/mach-exynos4/setup-i2c3.c
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c3_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgall_range(S5PV310_GPA1(2), 2,
+        s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2,
                               S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5pv310/setup-i2c4.c b/arch/arm/mach-exynos4/setup-i2c4.c
index 909e8dfc5316..9f3c04855b76 100644
--- a/arch/arm/mach-s5pv310/setup-i2c4.c
+++ b/arch/arm/mach-exynos4/setup-i2c4.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-s5pv310/setup-i2c4.c
+ * linux/arch/arm/mach-exynos4/setup-i2c4.c
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c4_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgall_range(S5PV310_GPB(2), 2,
+        s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
                               S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5pv310/setup-i2c5.c b/arch/arm/mach-exynos4/setup-i2c5.c
index 5d0fa4ac0283..77e1a1e57c76 100644
--- a/arch/arm/mach-s5pv310/setup-i2c5.c
+++ b/arch/arm/mach-exynos4/setup-i2c5.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-s5pv310/setup-i2c5.c
+ * linux/arch/arm/mach-exynos4/setup-i2c5.c
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c5_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgall_range(S5PV310_GPB(6), 2,
+        s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
                               S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5pv310/setup-i2c6.c b/arch/arm/mach-exynos4/setup-i2c6.c
index 34aafab92ac4..284d12b7af0e 100644
--- a/arch/arm/mach-s5pv310/setup-i2c6.c
+++ b/arch/arm/mach-exynos4/setup-i2c6.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-s5pv310/setup-i2c6.c
+ * linux/arch/arm/mach-exynos4/setup-i2c6.c
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c6_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgall_range(S5PV310_GPC1(3), 2,
+        s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
                               S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5pv310/setup-i2c7.c b/arch/arm/mach-exynos4/setup-i2c7.c
index 9b25b8d18920..b7611ee359a2 100644
--- a/arch/arm/mach-s5pv310/setup-i2c7.c
+++ b/arch/arm/mach-exynos4/setup-i2c7.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-s5pv310/setup-i2c7.c
+ * linux/arch/arm/mach-exynos4/setup-i2c7.c
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c7_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgall_range(S5PV310_GPD0(2), 2,
+        s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2,
                               S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-exynos4/setup-keypad.c b/arch/arm/mach-exynos4/setup-keypad.c
new file mode 100644
index 000000000000..1ee0ebff111f
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-keypad.c
@@ -0,0 +1,35 @@
+/* linux/arch/arm/mach-exynos4/setup-keypad.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * GPIO configuration for Exynos4 KeyPad device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+
+void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
+{
+        /* Keypads can be of various combinations, Just making sure */
+
+        if (rows > 8) {
+                /* Set all the necessary GPX2 pins: KP_ROW[0~7] */
+                s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3));
+
+                /* Set all the necessary GPX3 pins: KP_ROW[8~] */
+                s3c_gpio_cfgrange_nopull(EXYNOS4_GPX3(0), (rows - 8),
+                                         S3C_GPIO_SFN(3));
+        } else {
+                /* Set all the necessary GPX2 pins: KP_ROW[x] */
+                s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), rows,
+                                         S3C_GPIO_SFN(3));
+        }
+
+        /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
+        s3c_gpio_cfgrange_nopull(EXYNOS4_GPX1(0), cols, S3C_GPIO_SFN(3));
+}
diff --git a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c b/arch/arm/mach-exynos4/setup-sdhci-gpio.c
index 86d38cc49135..1b3d3a2de95c 100644
--- a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
+++ b/arch/arm/mach-exynos4/setup-sdhci-gpio.c
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
+/* linux/arch/arm/mach-exynos4/setup-sdhci-gpio.c
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5PV310 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ * EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -23,13 +23,13 @@
 #include <plat/regs-sdhci.h>
 #include <plat/sdhci.h>
 
-void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 {
         struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
         unsigned int gpio;
 
         /* Set all the necessary GPK0[0:1] pins to special-function 2 */
-        for (gpio = S5PV310_GPK0(0); gpio < S5PV310_GPK0(2); gpio++) {
+        for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) {
                 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
                 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
                 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
@@ -37,14 +37,14 @@ void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 
         switch (width) {
         case 8:
-                for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
+                for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
                         /* Data pin GPK1[3:6] to special-funtion 3 */
                         s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
                         s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
                         s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
                 }
         case 4:
-                for (gpio = S5PV310_GPK0(3); gpio <= S5PV310_GPK0(6); gpio++) {
+                for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
                         /* Data pin GPK0[3:6] to special-funtion 2 */
                         s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
                         s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
@@ -55,25 +55,25 @@ void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
         }
 
         if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_cfgpin(S5PV310_GPK0(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5PV310_GPK0(2), S3C_GPIO_PULL_UP);
+                s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP);
                 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
         }
 }
 
-void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 {
         struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
         unsigned int gpio;
 
         /* Set all the necessary GPK1[0:1] pins to special-function 2 */
-        for (gpio = S5PV310_GPK1(0); gpio < S5PV310_GPK1(2); gpio++) {
+        for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) {
                 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
                 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
                 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
         }
 
-        for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
+        for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
                 /* Data pin GPK1[3:6] to special-function 2 */
                 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
                 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
@@ -81,19 +81,19 @@ void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
         }
 
         if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_cfgpin(S5PV310_GPK1(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5PV310_GPK1(2), S3C_GPIO_PULL_UP);
+                s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP);
                 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
         }
 }
 
-void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
 {
         struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
         unsigned int gpio;
 
         /* Set all the necessary GPK2[0:1] pins to special-function 2 */
-        for (gpio = S5PV310_GPK2(0); gpio < S5PV310_GPK2(2); gpio++) {
+        for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) {
                 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
                 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
                 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
@@ -101,14 +101,14 @@ void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
 
         switch (width) {
         case 8:
-                for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
+                for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
                         /* Data pin GPK3[3:6] to special-function 3 */
                         s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
                         s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
                         s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
                 }
         case 4:
-                for (gpio = S5PV310_GPK2(3); gpio <= S5PV310_GPK2(6); gpio++) {
+                for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) {
                         /* Data pin GPK2[3:6] to special-function 2 */
                         s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
                         s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
@@ -119,25 +119,25 @@ void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
         }
 
         if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_cfgpin(S5PV310_GPK2(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5PV310_GPK2(2), S3C_GPIO_PULL_UP);
+                s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_UP);
                 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
         }
 }
 
-void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
+void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
 {
         struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
         unsigned int gpio;
 
         /* Set all the necessary GPK3[0:1] pins to special-function 2 */
-        for (gpio = S5PV310_GPK3(0); gpio < S5PV310_GPK3(2); gpio++) {
+        for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) {
                 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
                 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
                 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
         }
 
-        for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
+        for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
                 /* Data pin GPK3[3:6] to special-function 2 */
                 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
                 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
@@ -145,8 +145,8 @@ void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
         }
 
         if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_cfgpin(S5PV310_GPK3(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5PV310_GPK3(2), S3C_GPIO_PULL_UP);
+                s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_UP);
                 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
         }
 }
diff --git a/arch/arm/mach-s5pv310/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c
index db8358fc4662..85f9433d4836 100644
--- a/arch/arm/mach-s5pv310/setup-sdhci.c
+++ b/arch/arm/mach-exynos4/setup-sdhci.c
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5pv310/setup-sdhci.c
+/* linux/arch/arm/mach-exynos4/setup-sdhci.c
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5PV310 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -23,14 +23,14 @@
 
 /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
 
-char *s5pv310_hsmmc_clksrcs[4] = {
+char *exynos4_hsmmc_clksrcs[4] = {
         [0] = NULL,
         [1] = NULL,
         [2] = "sclk_mmc",       /* mmc_bus */
         [3] = NULL,
 };
 
-void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
+void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
                                   struct mmc_ios *ios, struct mmc_card *card)
 {
         u32 ctrl2, ctrl3;
diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S
new file mode 100644
index 000000000000..6b62425417a6
--- /dev/null
+++ b/arch/arm/mach-exynos4/sleep.S
@@ -0,0 +1,76 @@
+/* linux/arch/arm/mach-exynos4/sleep.S
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4210 power Manager (Suspend-To-RAM) support
+ * Based on S3C2410 sleep code by:
+ *      Ben Dooks, (c) 2004 Simtec Electronics
+ *
+ * Based on PXA/SA1100 sleep code by:
+ *      Nicolas Pitre, (c) 2002 Monta Vista Software Inc
+ *      Cliff Brake, (c) 2001
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/memory.h>
+
+        .text
+
+        /*
+         * s3c_cpu_save
+         *
+         * entry:
+         *      r1 = v:p offset
+         */
+
+ENTRY(s3c_cpu_save)
+
+        stmfd   sp!, { r3 - r12, lr }
+        ldr     r3, =resume_with_mmu
+        bl      cpu_suspend
+
+        ldr     r0, =pm_cpu_sleep
+        ldr     r0, [ r0 ]
+        mov     pc, r0
+
+resume_with_mmu:
+        ldmfd   sp!, { r3 - r12, pc }
+
+        .ltorg
+
+        /*
+         * sleep magic, to allow the bootloader to check for an valid
+         * image to resume to. Must be the first word before the
+         * s3c_cpu_resume entry.
+         */
+
+        .word   0x2bedf00d
+
+        /*
+         * s3c_cpu_resume
+         *
+         * resume code entry for bootloader to call
+         *
+         * we must put this code here in the data segment as we have no
+         * other way of restoring the stack pointer after sleep, and we
+         * must not write to the code segment (code is read-only)
+         */
+
+ENTRY(s3c_cpu_resume)
+        b       cpu_resume
diff --git a/arch/arm/mach-s5pv310/time.c b/arch/arm/mach-exynos4/time.c
index b262d4615331..86b9fa0d3639 100644
--- a/arch/arm/mach-s5pv310/time.c
+++ b/arch/arm/mach-exynos4/time.c
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5pv310/time.c
+/* linux/arch/arm/mach-exynos4/time.c
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * S5PV310 (and compatible) HRT support
+ * EXYNOS4 (and compatible) HRT support
  * PWM 2/4 is used for this feature
  *
  * This program is free software; you can redistribute it and/or modify
@@ -33,7 +33,7 @@ static struct clk *tdiv2;
 static struct clk *tdiv4;
 static struct clk *timerclk;
 
-static void s5pv310_pwm_stop(unsigned int pwm_id)
+static void exynos4_pwm_stop(unsigned int pwm_id)
 {
         unsigned long tcon;
 
@@ -52,7 +52,7 @@ static void s5pv310_pwm_stop(unsigned int pwm_id)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt)
+static void exynos4_pwm_init(unsigned int pwm_id, unsigned long tcnt)
 {
         unsigned long tcon;
 
@@ -86,7 +86,7 @@ static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt)
         }
 }
 
-static inline void s5pv310_pwm_start(unsigned int pwm_id, bool periodic)
+static inline void exynos4_pwm_start(unsigned int pwm_id, bool periodic)
 {
         unsigned long tcon;
 
@@ -117,23 +117,23 @@ static inline void s5pv310_pwm_start(unsigned int pwm_id, bool periodic)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static int s5pv310_pwm_set_next_event(unsigned long cycles,
+static int exynos4_pwm_set_next_event(unsigned long cycles,
                                         struct clock_event_device *evt)
 {
-        s5pv310_pwm_init(2, cycles);
-        s5pv310_pwm_start(2, 0);
+        exynos4_pwm_init(2, cycles);
+        exynos4_pwm_start(2, 0);
         return 0;
 }
 
-static void s5pv310_pwm_set_mode(enum clock_event_mode mode,
+static void exynos4_pwm_set_mode(enum clock_event_mode mode,
                                 struct clock_event_device *evt)
 {
-        s5pv310_pwm_stop(2);
+        exynos4_pwm_stop(2);
 
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
-                s5pv310_pwm_init(2, clock_count_per_tick);
-                s5pv310_pwm_start(2, 1);
+                exynos4_pwm_init(2, clock_count_per_tick);
+                exynos4_pwm_start(2, 1);
                 break;
         case CLOCK_EVT_MODE_ONESHOT:
                 break;
@@ -149,11 +149,11 @@ static struct clock_event_device pwm_event_device = {
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
         .rating         = 200,
         .shift          = 32,
-        .set_next_event = s5pv310_pwm_set_next_event,
-        .set_mode       = s5pv310_pwm_set_mode,
+        .set_next_event = exynos4_pwm_set_next_event,
+        .set_mode       = exynos4_pwm_set_mode,
 };
 
-irqreturn_t s5pv310_clock_event_isr(int irq, void *dev_id)
+irqreturn_t exynos4_clock_event_isr(int irq, void *dev_id)
 {
         struct clock_event_device *evt = &pwm_event_device;
 
@@ -162,13 +162,13 @@ irqreturn_t s5pv310_clock_event_isr(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-static struct irqaction s5pv310_clock_event_irq = {
+static struct irqaction exynos4_clock_event_irq = {
         .name           = "pwm_timer2_irq",
         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = s5pv310_clock_event_isr,
+        .handler        = exynos4_clock_event_isr,
 };
 
-static void __init s5pv310_clockevent_init(void)
+static void __init exynos4_clockevent_init(void)
 {
         unsigned long pclk;
         unsigned long clock_rate;
@@ -198,23 +198,39 @@ static void __init s5pv310_clockevent_init(void)
         pwm_event_device.cpumask = cpumask_of(0);
         clockevents_register_device(&pwm_event_device);
 
-        setup_irq(IRQ_TIMER2, &s5pv310_clock_event_irq);
+        setup_irq(IRQ_TIMER2, &exynos4_clock_event_irq);
 }
 
-static cycle_t s5pv310_pwm4_read(struct clocksource *cs)
+static cycle_t exynos4_pwm4_read(struct clocksource *cs)
 {
         return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
 }
 
+static void exynos4_pwm4_resume(struct clocksource *cs)
+{
+        unsigned long pclk;
+
+        pclk = clk_get_rate(timerclk);
+
+        clk_set_rate(tdiv4, pclk / 2);
+        clk_set_parent(tin4, tdiv4);
+
+        exynos4_pwm_init(4, ~0);
+        exynos4_pwm_start(4, 1);
+}
+
 struct clocksource pwm_clocksource = {
         .name           = "pwm_timer4",
         .rating         = 250,
-        .read           = s5pv310_pwm4_read,
+        .read           = exynos4_pwm4_read,
         .mask           = CLOCKSOURCE_MASK(32),
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS ,
+#ifdef CONFIG_PM
+        .resume         = exynos4_pwm4_resume,
+#endif
 };
 
-static void __init s5pv310_clocksource_init(void)
+static void __init exynos4_clocksource_init(void)
 {
         unsigned long pclk;
         unsigned long clock_rate;
@@ -226,14 +242,14 @@ static void __init s5pv310_clocksource_init(void)
 
         clock_rate = clk_get_rate(tin4);
 
-        s5pv310_pwm_init(4, ~0);
-        s5pv310_pwm_start(4, 1);
+        exynos4_pwm_init(4, ~0);
+        exynos4_pwm_start(4, 1);
 
         if (clocksource_register_hz(&pwm_clocksource, clock_rate))
                 panic("%s: can't register clocksource\n", pwm_clocksource.name);
 }
 
-static void __init s5pv310_timer_resources(void)
+static void __init exynos4_timer_resources(void)
 {
         struct platform_device tmpdev;
 
@@ -267,17 +283,17 @@ static void __init s5pv310_timer_resources(void)
         clk_enable(tin4);
 }
 
-static void __init s5pv310_timer_init(void)
+static void __init exynos4_timer_init(void)
 {
 #ifdef CONFIG_LOCAL_TIMERS
         twd_base = S5P_VA_TWD;
 #endif
 
-        s5pv310_timer_resources();
-        s5pv310_clockevent_init();
-        s5pv310_clocksource_init();
+        exynos4_timer_resources();
+        exynos4_clockevent_init();
+        exynos4_clocksource_init();
 }
 
-struct sys_timer s5pv310_timer = {
-        .init           = s5pv310_timer_init,
+struct sys_timer exynos4_timer = {
+        .init           = exynos4_timer_init,
 };
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 56684b517070..5eec099e0c72 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -100,6 +100,7 @@ config MACH_MX25_3DS
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMXDI_RTC
+        select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_KEYPAD
         select IMX_HAVE_PLATFORM_IMX_UART
@@ -238,6 +239,7 @@ config MACH_MX27_3DS
         select SOC_IMX27
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_KEYPAD
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_EHCI
@@ -265,6 +267,7 @@ config MACH_IMX27LITE
         bool "LogicPD MX27 LITEKIT platform"
         select SOC_IMX27
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IMX_SSI
         help
           Include support for MX27 LITEKIT platform. This includes specific
           configurations for the board and its peripherals.
@@ -300,4 +303,13 @@ config MACH_MXT_TD60
           Include support for i-MXT (aka td60) platform. This
           includes specific configurations for the module and its peripherals.
 
+config MACH_IMX27IPCAM
+        bool "IMX27 IPCAM platform"
+        select SOC_IMX27
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Include support for IMX27 IPCAM platform. This includes specific
+          configurations for the board and its peripherals.
+
 endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 77100bf26153..b85794d27991 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -9,10 +9,10 @@ obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
 obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
 obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
 
-obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o
+obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o
 
 obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
-obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
+obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
 
 # Support for CMOS sensor interface
 obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
@@ -36,3 +36,4 @@ obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
 obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
 obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
+obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c
index 3938a563b280..dcc41728fe72 100644
--- a/arch/arm/mach-imx/clock-imx1.c
+++ b/arch/arm/mach-imx/clock-imx1.c
@@ -592,6 +592,7 @@ static struct clk_lookup lookups[] __initdata = {
         _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
         _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk)
+        _REGISTER_CLOCK("imx1-cspi.1", NULL, spi_clk)
         _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
         _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
diff --git a/arch/arm/mach-imx/clock-imx25.c b/arch/arm/mach-imx/clock-imx25.c
index daa0165b6772..a65838fc061c 100644
--- a/arch/arm/mach-imx/clock-imx25.c
+++ b/arch/arm/mach-imx/clock-imx25.c
@@ -228,6 +228,7 @@ DEFINE_CLOCK(esdhc1_per_clk, 0, CCM_CGCR0,  3, get_rate_esdhc1,	 NULL,
 DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2,  NULL, NULL);
 DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0,  4, get_rate_esdhc2,  NULL,
                 &esdhc2_ahb_clk);
+DEFINE_CLOCK(sdma_ahb_clk, 0, CCM_CGCR0, 26, NULL,       NULL, NULL);
 DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL,        NULL, NULL);
 DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL,       NULL, NULL);
 DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0,  7, NULL,       NULL, &lcdc_ahb_clk);
@@ -253,6 +254,7 @@ DEFINE_CLOCK(lcdc_clk,	 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
 DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR2, 19, get_rate_ipg, NULL,  NULL);
 DEFINE_CLOCK(ssi1_clk,  0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
 DEFINE_CLOCK(ssi2_clk,  1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
+DEFINE_CLOCK(sdma_clk, 0, CCM_CGCR2,  6, get_rate_ipg, NULL, &sdma_ahb_clk);
 DEFINE_CLOCK(esdhc1_clk,  0, CCM_CGCR1, 13, get_rate_esdhc1, NULL,
                 &esdhc1_per_clk);
 DEFINE_CLOCK(esdhc2_clk,  1, CCM_CGCR1, 14, get_rate_esdhc2, NULL,
@@ -304,6 +306,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
         _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
         _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
+        _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
 };
 
 int __init mx25_clocks_init(void)
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
index 81979486218e..da593657ff3f 100644
--- a/arch/arm/mach-imx/devices-imx1.h
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -9,6 +9,10 @@
 #include <mach/mx1.h>
 #include <mach/devices-common.h>
 
+extern const struct imx_imx_fb_data imx1_imx_fb_data __initconst;
+#define imx1_add_imx_fb(pdata) \
+    imx_add_imx_fb(&imx1_imx_fb_data, pdata)
+
 extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst;
 #define imx1_add_imx_i2c(pdata)         \
         imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
@@ -18,3 +22,10 @@ extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst;
         imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
 #define imx1_add_imx_uart0(pdata)       imx1_add_imx_uart(0, pdata)
 #define imx1_add_imx_uart1(pdata)       imx1_add_imx_uart(1, pdata)
+
+extern const struct imx_spi_imx_data imx1_cspi_data[] __initconst;
+#define imx1_add_cspi(id, pdata)   \
+        imx_add_spi_imx(&imx1_cspi_data[id], pdata)
+
+#define imx1_add_spi_imx0(pdata) imx1_add_cspi(0, pdata)
+#define imx1_add_spi_imx1(pdata) imx1_add_cspi(1, pdata)
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index bde33caf1b90..b591d72f6037 100644
--- a/arch/arm/mach-imx/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -81,7 +81,11 @@ imx25_sdhci_esdhc_imx_data[] __initconst;
 
 extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst;
 #define imx25_add_spi_imx(id, pdata)    \
-        imx_add_spi_imx(&imx25_spi_imx_data[id], pdata)
+        imx_add_spi_imx(&imx25_cspi_data[id], pdata)
 #define imx25_add_spi_imx0(pdata)       imx25_add_spi_imx(0, pdata)
 #define imx25_add_spi_imx1(pdata)       imx25_add_spi_imx(1, pdata)
 #define imx25_add_spi_imx2(pdata)       imx25_add_spi_imx(2, pdata)
+
+extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst;
+#define imx25_add_mxc_pwm(id)   \
+        imx_add_mxc_pwm(&imx25_mxc_pwm_data[id])
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
index e9f1769b49f5..236f1495efad 100644
--- a/arch/arm/mach-imx/dma-v1.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -699,7 +699,7 @@ int imx_dma_request(int channel, const char *name)
                 local_irq_restore(flags);
                 return -EBUSY;
         }
-        memset(imxdma, 0, sizeof(imxdma));
+        memset(imxdma, 0, sizeof(*imxdma));
         imxdma->name = name;
         local_irq_restore(flags); /* request_irq() can block */
 
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
new file mode 100644
index 000000000000..865daf0b09e9
--- /dev/null
+++ b/arch/arm/mach-imx/ehci-imx25.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
+
+#define USBCTRL_OTGBASE_OFFSET  0x600
+
+#define MX25_OTG_SIC_SHIFT      29
+#define MX25_OTG_SIC_MASK       (0x3 << MX25_OTG_SIC_SHIFT)
+#define MX25_OTG_PM_BIT         (1 << 24)
+
+#define MX25_H1_SIC_SHIFT       21
+#define MX25_H1_SIC_MASK        (0x3 << MX25_H1_SIC_SHIFT)
+#define MX25_H1_PM_BIT          (1 << 8)
+#define MX25_H1_IPPUE_UP_BIT    (1 << 7)
+#define MX25_H1_IPPUE_DOWN_BIT  (1 << 6)
+#define MX25_H1_TLL_BIT         (1 << 5)
+#define MX25_H1_USBTE_BIT       (1 << 4)
+
+int mx25_initialize_usb_hw(int port, unsigned int flags)
+{
+        unsigned int v;
+
+        v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+
+        switch (port) {
+        case 0: /* OTG port */
+                v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
+
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX25_OTG_PM_BIT;
+
+                break;
+        case 1: /* H1 port */
+                v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_TLL_BIT |
+                        MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
+
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX25_H1_PM_BIT;
+
+                if (!(flags & MXC_EHCI_TTL_ENABLED))
+                        v |= MX25_H1_TLL_BIT;
+
+                if (flags & MXC_EHCI_INTERNAL_PHY)
+                        v |= MX25_H1_USBTE_BIT;
+
+                if (flags & MXC_EHCI_IPPUE_DOWN)
+                        v |= MX25_H1_IPPUE_DOWN_BIT;
+
+                if (flags & MXC_EHCI_IPPUE_UP)
+                        v |= MX25_H1_IPPUE_UP_BIT;
+
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+
+        return 0;
+}
+
diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c
new file mode 100644
index 000000000000..fa69419eabdd
--- /dev/null
+++ b/arch/arm/mach-imx/ehci-imx27.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
+
+#define USBCTRL_OTGBASE_OFFSET  0x600
+
+#define MX27_OTG_SIC_SHIFT      29
+#define MX27_OTG_SIC_MASK       (0x3 << MX27_OTG_SIC_SHIFT)
+#define MX27_OTG_PM_BIT         (1 << 24)
+
+#define MX27_H2_SIC_SHIFT       21
+#define MX27_H2_SIC_MASK        (0x3 << MX27_H2_SIC_SHIFT)
+#define MX27_H2_PM_BIT          (1 << 16)
+#define MX27_H2_DT_BIT          (1 << 5)
+
+#define MX27_H1_SIC_SHIFT       13
+#define MX27_H1_SIC_MASK        (0x3 << MX27_H1_SIC_SHIFT)
+#define MX27_H1_PM_BIT          (1 << 8)
+#define MX27_H1_DT_BIT          (1 << 4)
+
+int mx27_initialize_usb_hw(int port, unsigned int flags)
+{
+        unsigned int v;
+
+        v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+
+        switch (port) {
+        case 0: /* OTG port */
+                v &= ~(MX27_OTG_SIC_MASK | MX27_OTG_PM_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_OTG_SIC_SHIFT;
+
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX27_OTG_PM_BIT;
+                break;
+        case 1: /* H1 port */
+                v &= ~(MX27_H1_SIC_MASK | MX27_H1_PM_BIT | MX27_H1_DT_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H1_SIC_SHIFT;
+
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX27_H1_PM_BIT;
+
+                if (!(flags & MXC_EHCI_TTL_ENABLED))
+                        v |= MX27_H1_DT_BIT;
+
+                break;
+        case 2: /* H2 port */
+                v &= ~(MX27_H2_SIC_MASK | MX27_H2_PM_BIT | MX27_H2_DT_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H2_SIC_SHIFT;
+
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX27_H2_PM_BIT;
+
+                if (!(flags & MXC_EHCI_TTL_ENABLED))
+                        v |= MX27_H2_DT_BIT;
+
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+
+        return 0;
+}
+
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 275c8589d797..fa5288018ba7 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -249,7 +249,7 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
 
 #define ADS7846_PENDOWN (GPIO_PORTD | 25)
 
-static void ads7846_dev_init(void)
+static void __maybe_unused ads7846_dev_init(void)
 {
         if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
                 printk(KERN_ERR "can't get ads746 pen down GPIO\n");
@@ -268,7 +268,8 @@ static struct ads7846_platform_data ads7846_config __initdata = {
         .keep_vref_on           = 1,
 };
 
-static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
+static struct spi_board_info __maybe_unused
+                eukrea_mbimx27_spi_board_info[] __initdata = {
         [0] = {
                 .modalias       = "ads7846",
                 .bus_num        = 0,
@@ -357,13 +358,11 @@ void __init eukrea_mbimx27_baseboard_init(void)
         ads7846_dev_init();
 #endif
 
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
         /* SPI_CS0 init */
         mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
         imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
         spi_register_board_info(eukrea_mbimx27_spi_board_info,
                         ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
-#endif
 
         /* Leds configuration */
         mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 6cf04da2456a..759299bb035b 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -209,17 +209,25 @@ static struct platform_device serial_device = {
 };
 #endif
 
-#if defined(CONFIG_USB_ULPI)
+static int eukrea_cpuimx27_otg_init(struct platform_device *pdev)
+{
+        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
+
 static struct mxc_usbh_platform_data otg_pdata __initdata = {
+        .init   = eukrea_cpuimx27_otg_init,
         .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 
+static int eukrea_cpuimx27_usbh2_init(struct platform_device *pdev)
+{
+        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
+
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
+        .init   = eukrea_cpuimx27_usbh2_init,
         .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
-#endif
 
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
@@ -273,21 +281,19 @@ static void __init eukrea_cpuimx27_init(void)
         platform_device_register(&serial_device);
 #endif
 
-#if defined(CONFIG_USB_ULPI)
         if (otg_mode_host) {
-                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
-                imx27_add_mxc_ehci_otg(&otg_pdata);
+                otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                                ULPI_OTG_DRVVBUS_EXT);
+                if (otg_pdata.otg)
+                        imx27_add_mxc_ehci_otg(&otg_pdata);
+        } else {
+                imx27_add_fsl_usb2_udc(&otg_device_pdata);
         }
 
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
-        imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
-#endif
-        if (!otg_mode_host)
-                imx27_add_fsl_usb2_udc(&otg_device_pdata);
+        usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                        ULPI_OTG_DRVVBUS_EXT);
+        if (usbh2_pdata.otg)
+                imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
 
 #ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
         eukrea_mbimx27_baseboard_init();
@@ -304,9 +310,10 @@ static struct sys_timer eukrea_cpuimx27_timer = {
 };
 
 MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
-        .boot_params    = MX27_PHYS_OFFSET + 0x100,
-        .map_io         = mx27_map_io,
-        .init_irq       = mx27_init_irq,
-        .init_machine   = eukrea_cpuimx27_init,
-        .timer          = &eukrea_cpuimx27_timer,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .map_io = mx27_map_io,
+        .init_early = imx27_init_early,
+        .init_irq = mx27_init_irq,
+        .timer = &eukrea_cpuimx27_timer,
+        .init_machine = eukrea_cpuimx27_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index eb395aba9237..9da8d18eeb00 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -84,15 +84,25 @@ static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
         },
 };
 
+static int eukrea_cpuimx25_otg_init(struct platform_device *pdev)
+{
+        return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
+
 static const struct mxc_usbh_platform_data otg_pdata __initconst = {
+        .init   = eukrea_cpuimx25_otg_init,
         .portsc = MXC_EHCI_MODE_UTMI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 
+static int eukrea_cpuimx25_usbh2_init(struct platform_device *pdev)
+{
+        return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
+                        MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
+}
+
 static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
+        .init   = eukrea_cpuimx25_usbh2_init,
         .portsc = MXC_EHCI_MODE_SERIAL,
-        .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
-                  MXC_EHCI_IPPUE_DOWN,
 };
 
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
@@ -153,9 +163,10 @@ static struct sys_timer eukrea_cpuimx25_timer = {
 
 MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
         /* Maintainer: Eukrea Electromatique */
-        .boot_params    = MX25_PHYS_OFFSET + 0x100,
-        .map_io         = mx25_map_io,
-        .init_irq       = mx25_init_irq,
-        .init_machine   = eukrea_cpuimx25_init,
-        .timer          = &eukrea_cpuimx25_timer,
+        .boot_params = MX25_PHYS_OFFSET + 0x100,
+        .map_io = mx25_map_io,
+        .init_early = imx25_init_early,
+        .init_irq = mx25_init_irq,
+        .timer = &eukrea_cpuimx25_timer,
+        .init_machine = eukrea_cpuimx25_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 40a3666ea632..d7e0d219726a 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -30,6 +30,7 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
+#include <linux/delay.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -66,6 +67,11 @@ static const int visstrim_m10_pins[] __initconst = {
         PD15_AOUT_FEC_COL,
         PD16_AIN_FEC_TX_ER,
         PF23_AIN_FEC_TX_EN,
+        /* SSI1 */
+        PC20_PF_SSI1_FS,
+        PC21_PF_SSI1_RXD,
+        PC22_PF_SSI1_TXD,
+        PC23_PF_SSI1_CLK,
         /* SDHC1 */
         PE18_PF_SD1_D0,
         PE19_PF_SD1_D1,
@@ -204,20 +210,30 @@ static struct i2c_board_info visstrim_m10_i2c_devices[] = {
                 I2C_BOARD_INFO("pca9555", 0x20),
                 .platform_data = &visstrim_m10_pca9555_pdata,
         },
+        {
+                I2C_BOARD_INFO("tlv320aic32x4", 0x18),
+        }
 };
 
 /* USB OTG */
 static int otg_phy_init(struct platform_device *pdev)
 {
         gpio_set_value(OTG_PHY_CS_GPIO, 0);
-        return 0;
+
+        mdelay(10);
+
+        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
 }
 
 static const struct mxc_usbh_platform_data
 visstrim_m10_usbotg_pdata __initconst = {
         .init = otg_phy_init,
         .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
+};
+
+/* SSI */
+static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = {
+        .flags                  = IMX_SSI_DMA | IMX_SSI_SYN,
 };
 
 static void __init visstrim_m10_board_init(void)
@@ -229,6 +245,7 @@ static void __init visstrim_m10_board_init(void)
         if (ret)
                 pr_err("Failed to setup pins (%d)\n", ret);
 
+        imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata);
         imx27_add_imx_uart0(&uart_pdata);
 
         i2c_register_board_info(0, visstrim_m10_i2c_devices,
@@ -251,9 +268,10 @@ static struct sys_timer visstrim_m10_timer = {
 };
 
 MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
-        .boot_params    = MX27_PHYS_OFFSET + 0x100,
-        .map_io         = mx27_map_io,
-        .init_irq       = mx27_init_irq,
-        .init_machine   = visstrim_m10_board_init,
-        .timer          = &visstrim_m10_timer,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .map_io = mx27_map_io,
+        .init_early = imx27_init_early,
+        .init_irq = mx27_init_irq,
+        .timer = &visstrim_m10_timer,
+        .init_machine = visstrim_m10_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
new file mode 100644
index 000000000000..9be6cd6fbf8c
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx27.h>
+
+#include "devices-imx27.h"
+
+static const int mx27ipcam_pins[] __initconst = {
+        /* UART1 */
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        /* FEC */
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_RX_CLK,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN,
+};
+
+static void __init mx27ipcam_init(void)
+{
+        mxc_gpio_setup_multiple_pins(mx27ipcam_pins, ARRAY_SIZE(mx27ipcam_pins),
+                "mx27ipcam");
+
+        imx27_add_imx_uart0(NULL);
+        imx27_add_fec(NULL);
+        imx27_add_imx2_wdt(NULL);
+}
+
+static void __init mx27ipcam_timer_init(void)
+{
+        mx27_clocks_init(25000000);
+}
+
+static struct sys_timer mx27ipcam_timer = {
+        .init   = mx27ipcam_timer_init,
+};
+
+MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
+        /* maintainer: Freescale Semiconductor, Inc. */
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .map_io = mx27_map_io,
+        .init_early = imx27_init_early,
+        .init_irq = mx27_init_irq,
+        .timer = &mx27ipcam_timer,
+        .init_machine = mx27ipcam_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index 3a1202e47212..841140516ede 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -75,9 +75,10 @@ static struct sys_timer mx27lite_timer = {
 };
 
 MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
-        .boot_params    = MX27_PHYS_OFFSET + 0x100,
-        .map_io         = mx27_map_io,
-        .init_irq       = mx27_init_irq,
-        .init_machine   = mx27lite_init,
-        .timer          = &mx27lite_timer,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .map_io = mx27_map_io,
+        .init_early = imx27_init_early,
+        .init_irq = mx27_init_irq,
+        .timer = &mx27lite_timer,
+        .init_machine = mx27lite_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 1f446e5eb636..47cf56ac6d5b 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -144,17 +144,19 @@ struct sys_timer mx1ads_timer = {
 
 MACHINE_START(MX1ADS, "Freescale MX1ADS")
         /* Maintainer: Sascha Hauer, Pengutronix */
-        .boot_params    = MX1_PHYS_OFFSET + 0x100,
-        .map_io         = mx1_map_io,
-        .init_irq       = mx1_init_irq,
-        .timer          = &mx1ads_timer,
-        .init_machine   = mx1ads_init,
+        .boot_params = MX1_PHYS_OFFSET + 0x100,
+        .map_io = mx1_map_io,
+        .init_early = imx1_init_early,
+        .init_irq = mx1_init_irq,
+        .timer = &mx1ads_timer,
+        .init_machine = mx1ads_init,
 MACHINE_END
 
 MACHINE_START(MXLADS, "Freescale MXLADS")
-        .boot_params    = MX1_PHYS_OFFSET + 0x100,
-        .map_io         = mx1_map_io,
-        .init_irq       = mx1_init_irq,
-        .timer          = &mx1ads_timer,
-        .init_machine   = mx1ads_init,
+        .boot_params = MX1_PHYS_OFFSET + 0x100,
+        .map_io = mx1_map_io,
+        .init_early = imx1_init_early,
+        .init_irq = mx1_init_irq,
+        .timer = &mx1ads_timer,
+        .init_machine = mx1ads_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 0a372577c2ac..fa52a1086eae 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -304,9 +304,10 @@ static struct sys_timer mx21ads_timer = {
 
 MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
         /* maintainer: Freescale Semiconductor, Inc. */
-        .boot_params    = MX21_PHYS_OFFSET + 0x100,
-        .map_io         = mx21ads_map_io,
-        .init_irq       = mx21_init_irq,
-        .init_machine   = mx21ads_board_init,
-        .timer          = &mx21ads_timer,
+        .boot_params = MX21_PHYS_OFFSET + 0x100,
+        .map_io = mx21ads_map_io,
+        .init_early = imx21_init_early,
+        .init_irq = mx21_init_irq,
+        .timer = &mx21ads_timer,
+        .init_machine = mx21ads_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 8382e7902078..06da438282aa 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -103,14 +103,18 @@ static iomux_v3_cfg_t mx25pdk_pads[] = {
         MX25_PAD_SD1_DATA1__SD1_DATA1,
         MX25_PAD_SD1_DATA2__SD1_DATA2,
         MX25_PAD_SD1_DATA3__SD1_DATA3,
+
+        /* I2C1 */
+        MX25_PAD_I2C1_CLK__I2C1_CLK,
+        MX25_PAD_I2C1_DAT__I2C1_DAT,
 };
 
 static const struct fec_platform_data mx25_fec_pdata __initconst = {
         .phy    = PHY_INTERFACE_MODE_RMII,
 };
 
-#define FEC_ENABLE_GPIO         35
-#define FEC_RESET_B_GPIO        104
+#define FEC_ENABLE_GPIO         IMX_GPIO_NR(2, 3)
+#define FEC_RESET_B_GPIO        IMX_GPIO_NR(4, 8)
 
 static void __init mx25pdk_fec_reset(void)
 {
@@ -185,9 +189,14 @@ static const struct matrix_keymap_data mx25pdk_keymap_data __initconst = {
         .keymap_size    = ARRAY_SIZE(mx25pdk_keymap),
 };
 
+static int mx25pdk_usbh2_init(struct platform_device *pdev)
+{
+        return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
+}
+
 static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
+        .init   = mx25pdk_usbh2_init,
         .portsc = MXC_EHCI_MODE_SERIAL,
-        .flags  = MXC_EHCI_INTERNAL_PHY,
 };
 
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
@@ -195,6 +204,10 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_UTMI,
 };
 
+static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = {
+        .bitrate = 100000,
+};
+
 static void __init mx25pdk_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
@@ -213,6 +226,7 @@ static void __init mx25pdk_init(void)
         imx25_add_imx_keypad(&mx25pdk_keymap_data);
 
         imx25_add_sdhci_esdhc_imx(0, NULL);
+        imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
 }
 
 static void __init mx25pdk_timer_init(void)
@@ -226,10 +240,10 @@ static struct sys_timer mx25pdk_timer = {
 
 MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .boot_params    = MX25_PHYS_OFFSET + 0x100,
-        .map_io         = mx25_map_io,
-        .init_irq       = mx25_init_irq,
-        .init_machine   = mx25pdk_init,
-        .timer          = &mx25pdk_timer,
+        .boot_params = MX25_PHYS_OFFSET + 0x100,
+        .map_io = mx25_map_io,
+        .init_early = imx25_init_early,
+        .init_irq = mx25_init_irq,
+        .timer = &mx25pdk_timer,
+        .init_machine = mx25pdk_init,
 MACHINE_END
-
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 164331518bdd..614b3c00c4a0 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -98,6 +98,9 @@ static const int mx27pdk_pins[] __initconst = {
         PD22_PF_CSPI2_SCLK,
         PD23_PF_CSPI2_MISO,
         PD24_PF_CSPI2_MOSI,
+        /* I2C1 */
+        PD17_PF_I2C_DATA,
+        PD18_PF_I2C_CLK,
 };
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -159,13 +162,15 @@ static int otg_phy_init(void)
         return 0;
 }
 
-#if defined(CONFIG_USB_ULPI)
+static int mx27_3ds_otg_init(struct platform_device *pdev)
+{
+        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
 
 static struct mxc_usbh_platform_data otg_pdata __initdata = {
+        .init   = mx27_3ds_otg_init,
         .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
-#endif
 
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
@@ -216,7 +221,7 @@ static struct regulator_init_data vgen_init = {
         .consumer_supplies = vgen_consumers,
 };
 
-static struct mc13783_regulator_init_data mx27_3ds_regulators[] = {
+static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
         {
                 .id = MC13783_REG_VMMC1,
                 .init_data = &vmmc1_init,
@@ -227,10 +232,10 @@ static struct mc13783_regulator_init_data mx27_3ds_regulators[] = {
 };
 
 /* MC13783 */
-static struct mc13783_platform_data mc13783_pdata __initdata = {
+static struct mc13xxx_platform_data mc13783_pdata __initdata = {
         .regulators = mx27_3ds_regulators,
         .num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
-        .flags  = MC13783_USE_REGULATOR,
+        .flags  = MC13XXX_USE_REGULATOR,
 };
 
 /* SPI */
@@ -253,6 +258,9 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
         },
 };
 
+static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = {
+        .bitrate = 100000,
+};
 
 static void __init mx27pdk_init(void)
 {
@@ -265,14 +273,15 @@ static void __init mx27pdk_init(void)
         imx27_add_mxc_mmc(0, &sdhc1_pdata);
         imx27_add_imx2_wdt(NULL);
         otg_phy_init();
-#if defined(CONFIG_USB_ULPI)
+
         if (otg_mode_host) {
-                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                                ULPI_OTG_DRVVBUS_EXT);
 
-                imx27_add_mxc_ehci_otg(&otg_pdata);
+                if (otg_pdata.otg)
+                        imx27_add_mxc_ehci_otg(&otg_pdata);
         }
-#endif
+
         if (!otg_mode_host)
                 imx27_add_fsl_usb2_udc(&otg_device_pdata);
 
@@ -282,6 +291,7 @@ static void __init mx27pdk_init(void)
 
         if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
                 pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
+        imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
 }
 
 static void __init mx27pdk_timer_init(void)
@@ -295,9 +305,10 @@ static struct sys_timer mx27pdk_timer = {
 
 MACHINE_START(MX27_3DS, "Freescale MX27PDK")
         /* maintainer: Freescale Semiconductor, Inc. */
-        .boot_params    = MX27_PHYS_OFFSET + 0x100,
-        .map_io         = mx27_map_io,
-        .init_irq       = mx27_init_irq,
-        .init_machine   = mx27pdk_init,
-        .timer          = &mx27pdk_timer,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .map_io = mx27_map_io,
+        .init_early = imx27_init_early,
+        .init_irq = mx27_init_irq,
+        .timer = &mx27pdk_timer,
+        .init_machine = mx27pdk_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index b832f960fec4..367d1e4384c7 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -344,9 +344,10 @@ static void __init mx27ads_map_io(void)
 
 MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
         /* maintainer: Freescale Semiconductor, Inc. */
-        .boot_params    = MX27_PHYS_OFFSET + 0x100,
-        .map_io         = mx27ads_map_io,
-        .init_irq       = mx27_init_irq,
-        .init_machine   = mx27ads_board_init,
-        .timer          = &mx27ads_timer,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .map_io = mx27ads_map_io,
+        .init_early = imx27_init_early,
+        .init_irq = mx27_init_irq,
+        .timer = &mx27ads_timer,
+        .init_machine = mx27ads_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 4ce71b0401db..69787c30c320 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -266,10 +266,10 @@ static struct sys_timer mxt_td60_timer = {
 
 MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
         /* maintainer: Maxtrack Industrial */
-        .boot_params    = MX27_PHYS_OFFSET + 0x100,
-        .map_io         = mx27_map_io,
-        .init_irq       = mx27_init_irq,
-        .init_machine   = mxt_td60_board_init,
-        .timer          = &mxt_td60_timer,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .map_io = mx27_map_io,
+        .init_early = imx27_init_early,
+        .init_irq = mx27_init_irq,
+        .timer = &mxt_td60_timer,
+        .init_machine = mxt_td60_board_init,
 MACHINE_END
-
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index cccc0a0a9c72..63e182556778 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -187,7 +187,6 @@ static struct i2c_board_info pca100_i2c_devices[] = {
         }
 };
 
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
 static struct spi_eeprom at25320 = {
         .name           = "at25320an",
         .byte_len       = 4096,
@@ -211,7 +210,6 @@ static const struct spi_imx_master pca100_spi0_data __initconst = {
         .chipselect     = pca100_spi_cs,
         .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
 };
-#endif
 
 static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
 {
@@ -269,31 +267,33 @@ static const struct imxmmc_platform_data sdhc_pdata __initconst = {
         .exit = pca100_sdhc2_exit,
 };
 
-#if defined(CONFIG_USB_ULPI)
 static int otg_phy_init(struct platform_device *pdev)
 {
         gpio_set_value(OTG_PHY_CS_GPIO, 0);
-        return 0;
+
+        mdelay(10);
+
+        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
 }
 
 static struct mxc_usbh_platform_data otg_pdata __initdata = {
         .init   = otg_phy_init,
         .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 
 static int usbh2_phy_init(struct platform_device *pdev)
 {
         gpio_set_value(USBH2_PHY_CS_GPIO, 0);
-        return 0;
+
+        mdelay(10);
+
+        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
 }
 
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
         .init   = usbh2_phy_init,
         .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
-#endif
 
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
@@ -389,36 +389,33 @@ static void __init pca100_init(void)
 
         imx27_add_imx_i2c(1, &pca100_i2c1_data);
 
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
         mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
         mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
         spi_register_board_info(pca100_spi_board_info,
                                 ARRAY_SIZE(pca100_spi_board_info));
         imx27_add_spi_imx0(&pca100_spi0_data);
-#endif
 
         gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
         gpio_direction_output(OTG_PHY_CS_GPIO, 1);
         gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
         gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
 
-#if defined(CONFIG_USB_ULPI)
         if (otg_mode_host) {
-                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+                otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                                ULPI_OTG_DRVVBUS_EXT);
 
-                imx27_add_mxc_ehci_otg(&otg_pdata);
+                if (otg_pdata.otg)
+                        imx27_add_mxc_ehci_otg(&otg_pdata);
+        } else {
+                gpio_set_value(OTG_PHY_CS_GPIO, 0);
+                imx27_add_fsl_usb2_udc(&otg_device_pdata);
         }
 
         usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
                                 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
-        imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
-#endif
-        if (!otg_mode_host) {
-                gpio_set_value(OTG_PHY_CS_GPIO, 0);
-                imx27_add_fsl_usb2_udc(&otg_device_pdata);
-        }
+        if (usbh2_pdata.otg)
+                imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
 
         imx27_add_imx_fb(&pca100_fb_data);
 
@@ -437,10 +434,10 @@ static struct sys_timer pca100_timer = {
 };
 
 MACHINE_START(PCA100, "phyCARD-i.MX27")
-        .boot_params    = MX27_PHYS_OFFSET + 0x100,
-        .map_io         = mx27_map_io,
-        .init_irq       = mx27_init_irq,
-        .init_machine   = pca100_init,
-        .timer          = &pca100_timer,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .map_io = mx27_map_io,
+        .init_early = imx27_init_early,
+        .init_irq = mx27_init_irq,
+        .init_machine = pca100_init,
+        .timer = &pca100_timer,
 MACHINE_END
-
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 505614803bc6..38c77084b615 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -252,7 +252,7 @@ static struct regulator_init_data cam_data = {
         .consumer_supplies = cam_consumers,
 };
 
-static struct mc13783_regulator_init_data pcm038_regulators[] = {
+static struct mc13xxx_regulator_init_data pcm038_regulators[] = {
         {
                 .id = MC13783_REG_VCAM,
                 .init_data = &cam_data,
@@ -262,11 +262,11 @@ static struct mc13783_regulator_init_data pcm038_regulators[] = {
         },
 };
 
-static struct mc13783_platform_data pcm038_pmic = {
+static struct mc13xxx_platform_data pcm038_pmic = {
         .regulators = pcm038_regulators,
         .num_regulators = ARRAY_SIZE(pcm038_regulators),
-        .flags = MC13783_USE_ADC | MC13783_USE_REGULATOR |
-                 MC13783_USE_TOUCHSCREEN,
+        .flags = MC13XXX_USE_ADC | MC13XXX_USE_REGULATOR |
+                 MC13XXX_USE_TOUCHSCREEN,
 };
 
 static struct spi_board_info pcm038_spi_board_info[] __initdata = {
@@ -281,9 +281,15 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = {
         }
 };
 
+static int pcm038_usbh2_init(struct platform_device *pdev)
+{
+        return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_INTERFACE_DIFF_UNI);
+}
+
 static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
+        .init   = pcm038_usbh2_init,
         .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 
 static void __init pcm038_init(void)
@@ -340,9 +346,10 @@ static struct sys_timer pcm038_timer = {
 };
 
 MACHINE_START(PCM038, "phyCORE-i.MX27")
-        .boot_params    = MX27_PHYS_OFFSET + 0x100,
-        .map_io         = mx27_map_io,
-        .init_irq       = mx27_init_irq,
-        .init_machine   = pcm038_init,
-        .timer          = &pcm038_timer,
+        .boot_params = MX27_PHYS_OFFSET + 0x100,
+        .map_io = mx27_map_io,
+        .init_early = imx27_init_early,
+        .init_irq = mx27_init_irq,
+        .timer = &pcm038_timer,
+        .init_machine = pcm038_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index eae878f306c6..dcaee043628e 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -145,10 +145,11 @@ static struct sys_timer scb9328_timer = {
 };
 
 MACHINE_START(SCB9328, "Synertronixx scb9328")
-    /* Sascha Hauer */
-        .boot_params    = 0x08000100,
-        .map_io         = mx1_map_io,
-        .init_irq       = mx1_init_irq,
-        .timer          = &scb9328_timer,
-        .init_machine   = scb9328_init,
+        /* Sascha Hauer */
+        .boot_params = 0x08000100,
+        .map_io = mx1_map_io,
+        .init_early = imx1_init_early,
+        .init_irq = mx1_init_irq,
+        .timer = &scb9328_timer,
+        .init_machine = scb9328_init,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 729ae0915af8..2e482ba5a0e7 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -23,6 +23,9 @@
 
 #include <mach/common.h>
 #include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+#include <mach/iomux-v1.h>
 
 static struct map_desc imx_io_desc[] __initdata = {
         imx_map_entry(MX1, IO, MT_DEVICE),
@@ -30,16 +33,26 @@ static struct map_desc imx_io_desc[] __initdata = {
 
 void __init mx1_map_io(void)
 {
+        iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
+}
+
+void __init imx1_init_early(void)
+{
         mxc_set_cpu_type(MXC_CPU_MX1);
         mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
-
-        iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
+        imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
+                        MX1_NUM_GPIO_PORT);
 }
 
-int imx1_register_gpios(void);
+static struct mxc_gpio_port imx1_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
+};
 
 void __init mx1_init_irq(void)
 {
         mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
-        imx1_register_gpios();
+        mxc_gpio_init(imx1_gpio_ports,  ARRAY_SIZE(imx1_gpio_ports));
 }
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index e728af81d1b1..7a0c500ac2c8 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -24,6 +24,9 @@
 #include <mach/common.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+#include <mach/iomux-v1.h>
 
 /* MX21 memory map definition */
 static struct map_desc imx21_io_desc[] __initdata = {
@@ -56,16 +59,28 @@ static struct map_desc imx21_io_desc[] __initdata = {
  */
 void __init mx21_map_io(void)
 {
+        iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
+}
+
+void __init imx21_init_early(void)
+{
         mxc_set_cpu_type(MXC_CPU_MX21);
         mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
-
-        iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
+        imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR),
+                        MX21_NUM_GPIO_PORT);
 }
 
-int imx21_register_gpios(void);
+static struct mxc_gpio_port imx21_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
+        DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
+        DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
+        DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
+        DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
+        DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
+};
 
 void __init mx21_init_irq(void)
 {
         mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
-        imx21_register_gpios();
+        mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
 }
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 2edec6ce8fe7..02f7b5c7fa8e 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -27,6 +27,8 @@
 #include <mach/hardware.h>
 #include <mach/mx25.h>
 #include <mach/iomux-v3.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
 
 /*
  * This table defines static virtual address mappings for I/O regions.
@@ -45,18 +47,26 @@ static struct map_desc mx25_io_desc[] __initdata = {
  */
 void __init mx25_map_io(void)
 {
+        iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
+}
+
+void __init imx25_init_early(void)
+{
         mxc_set_cpu_type(MXC_CPU_MX25);
         mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
-
-        iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
 }
 
-int imx25_register_gpios(void);
+static struct mxc_gpio_port imx25_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
+};
 
 void __init mx25_init_irq(void)
 {
         mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
-        imx25_register_gpios();
+        mxc_gpio_init(imx25_gpio_ports, ARRAY_SIZE(imx25_gpio_ports));
 }
 
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 374e48b7a412..a6761a39f08c 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -24,6 +24,9 @@
 #include <mach/common.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+#include <mach/iomux-v1.h>
 
 /* MX27 memory map definition */
 static struct map_desc imx27_io_desc[] __initdata = {
@@ -56,16 +59,28 @@ static struct map_desc imx27_io_desc[] __initdata = {
  */
 void __init mx27_map_io(void)
 {
+        iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
+}
+
+void __init imx27_init_early(void)
+{
         mxc_set_cpu_type(MXC_CPU_MX27);
         mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
-
-        iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
+        imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR),
+                        MX27_NUM_GPIO_PORT);
 }
 
-int imx27_register_gpios(void);
+static struct mxc_gpio_port imx27_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
+        DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
+        DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
+        DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
+        DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
+        DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
+};
 
 void __init mx27_init_irq(void)
 {
         mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
-        imx27_register_gpios();
+        mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
 }
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 3688123b5ad8..20e71df3e3bb 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -21,6 +21,7 @@
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
+#include <asm/kexec.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <mach/kirkwood.h>
@@ -846,9 +847,14 @@ static void __init kirkwood_wdt_init(void)
 /*****************************************************************************
  * Time handling
  ****************************************************************************/
+void __init kirkwood_init_early(void)
+{
+        orion_time_set_base(TIMER_VIRT_BASE);
+}
+
 int kirkwood_tclk;
 
-int __init kirkwood_find_tclk(void)
+static int __init kirkwood_find_tclk(void)
 {
         u32 dev, rev;
 
@@ -864,7 +870,9 @@ int __init kirkwood_find_tclk(void)
 static void __init kirkwood_timer_init(void)
 {
         kirkwood_tclk = kirkwood_find_tclk();
-        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
+
+        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+                        IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
 }
 
 struct sys_timer kirkwood_timer = {
@@ -1003,6 +1011,10 @@ void __init kirkwood_init(void)
         kirkwood_xor0_init();
         kirkwood_xor1_init();
         kirkwood_crypto_init();
+
+#ifdef CONFIG_KEXEC 
+        kexec_reinit = kirkwood_enable_pcie;
+#endif
 }
 
 static int __init kirkwood_clock_gate(void)
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 95bb0a73adfb..b9b0f0968a36 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -27,11 +27,13 @@ struct kirkwood_asoc_platform_data;
  */
 void kirkwood_map_io(void);
 void kirkwood_init(void);
+void kirkwood_init_early(void);
 void kirkwood_init_irq(void);
 
 extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
 void kirkwood_setup_cpu_mbus(void);
 
+void kirkwood_enable_pcie(void);
 void kirkwood_pcie_id(u32 *dev, u32 *rev);
 
 void kirkwood_ehci_init(void);
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
index a31c9499ab36..043cfd5e140b 100644
--- a/arch/arm/mach-kirkwood/d2net_v2-setup.c
+++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c
@@ -224,6 +224,7 @@ MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
         .boot_params    = 0x00000100,
         .init_machine   = d2net_v2_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 9ea71182d31a..bff04e04d679 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -100,6 +100,7 @@ MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
         .boot_params    = 0x00000100,
         .init_machine   = db88f6281_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
index 433ea368c060..f14dfb8508c5 100644
--- a/arch/arm/mach-kirkwood/dockstar-setup.c
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -105,6 +105,7 @@ MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar")
         .boot_params    = 0x00000100,
         .init_machine   = dockstar_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index 8f47dc0a2fef..41d1b40696a3 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -124,6 +124,7 @@ MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board")
         .boot_params    = 0x00000100,
         .init_machine   = guruplug_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index aff0e1327e38..957bd7997d7e 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -29,9 +29,6 @@
 #define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
 #define WDT_INT_REQ             0x0008
 
-#define BRIDGE_MASK             (BRIDGE_VIRT_BASE | 0x0114)
-#define BRIDGE_INT_TIMER0       0x0002
-#define BRIDGE_INT_TIMER1       0x0004
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 
 #define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
diff --git a/arch/arm/mach-kirkwood/include/mach/gpio.h b/arch/arm/mach-kirkwood/include/mach/gpio.h
index 81b335eb62ec..84f340b546c0 100644
--- a/arch/arm/mach-kirkwood/include/mach/gpio.h
+++ b/arch/arm/mach-kirkwood/include/mach/gpio.h
@@ -6,33 +6,4 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#include <mach/irqs.h>
 #include <plat/gpio.h>
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-
-#define GPIO_MAX                50
-#define GPIO_OFF(pin)           (((pin) >> 5) ? 0x0140 : 0x0100)
-#define GPIO_OUT(pin)           (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x00)
-#define GPIO_IO_CONF(pin)       (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x04)
-#define GPIO_BLINK_EN(pin)      (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x08)
-#define GPIO_IN_POL(pin)        (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x0c)
-#define GPIO_DATA_IN(pin)       (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x10)
-#define GPIO_EDGE_CAUSE(pin)    (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x14)
-#define GPIO_EDGE_MASK(pin)     (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x18)
-#define GPIO_LEVEL_MASK(pin)    (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x1c)
-
-static inline int gpio_to_irq(int pin)
-{
-        return pin + IRQ_KIRKWOOD_GPIO_START;
-}
-
-static inline int irq_to_gpio(int irq)
-{
-        return irq - IRQ_KIRKWOOD_GPIO_START;
-}
-
-
-#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 6e924b398919..010bdeb4ac5f 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -69,6 +69,8 @@
 #define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
 #define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE | 0x0030)
 #define  DEVICE_ID              (DEV_BUS_VIRT_BASE | 0x0034)
+#define  GPIO_LOW_VIRT_BASE     (DEV_BUS_VIRT_BASE | 0x0100)
+#define  GPIO_HIGH_VIRT_BASE    (DEV_BUS_VIRT_BASE | 0x0140)
 #define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0300)
 #define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0600)
 #define  I2C_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x1000)
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index 28020abf49e1..cbdb5863d13b 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -27,31 +27,21 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
 void __init kirkwood_init_irq(void)
 {
-        int i;
-
         orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
         orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
 
         /*
-         * Mask and clear GPIO IRQ interrupts.
+         * Initialize gpiolib for GPIOs 0-49.
          */
-        writel(0, GPIO_LEVEL_MASK(0));
-        writel(0, GPIO_EDGE_MASK(0));
-        writel(0, GPIO_EDGE_CAUSE(0));
-        writel(0, GPIO_LEVEL_MASK(32));
-        writel(0, GPIO_EDGE_MASK(32));
-        writel(0, GPIO_EDGE_CAUSE(32));
-
-        for (i = IRQ_KIRKWOOD_GPIO_START; i < NR_IRQS; i++) {
-                set_irq_chip(i, &orion_gpio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                irq_desc[i].status |= IRQ_LEVEL;
-                set_irq_flags(i, IRQF_VALID);
-        }
+        orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0,
+                        IRQ_KIRKWOOD_GPIO_START);
         set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
         set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
         set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
         set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
+
+        orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0,
+                        IRQ_KIRKWOOD_GPIO_START + 32);
         set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
         set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
         set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler);
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 27901f702feb..7ce201848067 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -49,9 +49,6 @@ void __init kirkwood_mpp_conf(unsigned int *mpp_list)
         if (!variant_mask)
                 return;
 
-        /* Initialize gpiolib. */
-        orion_gpio_init();
-
         printk(KERN_DEBUG "initial MPP regs:");
         for (i = 0; i < MPP_NR_REGS; i++) {
                 mpp_ctrl[i] = readl(MPP_CTRL(i));
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 1e5266f57e2a..00cca22eca6f 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -166,6 +166,7 @@ MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board")
         .boot_params    = 0x00000100,
         .init_machine   = mv88f6281gtw_ge_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 65ee21fd2f3b..7cdab5776452 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -261,6 +261,7 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
         .boot_params    = 0x00000100,
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
@@ -271,6 +272,7 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
         .boot_params    = 0x00000100,
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
@@ -281,6 +283,7 @@ MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
         .boot_params    = 0x00000100,
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 93afd3c8bfd8..6be627deb0fc 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -402,6 +402,7 @@ MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
         .boot_params    = 0x00000100,
         .init_machine   = netxbig_v2_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
@@ -412,6 +413,7 @@ MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
         .boot_params    = 0x00000100,
         .init_machine   = netxbig_v2_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index cfcca4174e25..f69beeff4450 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -217,6 +217,7 @@ MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board")
         .boot_params    = 0x00000100,
         .init_machine   = openrd_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
@@ -228,6 +229,7 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
         .boot_params    = 0x00000100,
         .init_machine   = openrd_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
@@ -239,6 +241,7 @@ MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
         .boot_params    = 0x00000100,
         .init_machine   = openrd_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 513ad3102d7c..ca294ff6d5be 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -18,8 +18,16 @@
 #include <mach/bridge-regs.h>
 #include "common.h"
 
+void kirkwood_enable_pcie(void)
+{
+        u32 curr = readl(CLOCK_GATING_CTRL);
+        if (!(curr & CGC_PEX0))
+                writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
+}
+
 void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
 {
+        kirkwood_enable_pcie();
         *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
         *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 0049614cd324..75c6601b8d87 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -82,6 +82,7 @@ MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
         .boot_params    = 0x00000100,
         .init_machine   = rd88f6192_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 0998a08cf42d..0f75494d5902 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -118,6 +118,7 @@ MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
         .boot_params    = 0x00000100,
         .init_machine   = rd88f6281_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index d2eec35dfe0f..0a95063f6d32 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -134,6 +134,7 @@ MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")
         .boot_params    = 0x00000100,
         .init_machine   = sheevaplug_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
@@ -144,6 +145,7 @@ MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board")
         .boot_params    = 0x00000100,
         .init_machine   = sheevaplug_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
index ce50e61aac9f..e6b9b1b22a35 100644
--- a/arch/arm/mach-kirkwood/t5325-setup.c
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -23,6 +23,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <sound/alc5623.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
@@ -134,6 +135,7 @@ static unsigned int hp_t5325_mpp_config[] __initdata = {
         MPP33_GE1_TXCTL,
         MPP39_AU_I2SBCLK,
         MPP40_AU_I2SDO,
+        MPP43_AU_I2SDI,
         MPP41_AU_I2SLRCLK,
         MPP42_AU_I2SMCLK,
         MPP45_GPIO,             /* Power button */
@@ -141,6 +143,18 @@ static unsigned int hp_t5325_mpp_config[] __initdata = {
         0
 };
 
+static struct alc5623_platform_data alc5621_data = {
+        .add_ctrl = 0x3700,
+        .jack_det_ctrl = 0x4810,
+};
+
+static struct i2c_board_info i2c_board_info[] __initdata = {
+        {
+                I2C_BOARD_INFO("alc5621", 0x1a),
+                .platform_data = &alc5621_data,
+        },
+};
+
 #define HP_T5325_GPIO_POWER_OFF         48
 
 static void hp_t5325_power_off(void)
@@ -166,6 +180,9 @@ static void __init hp_t5325_init(void)
         kirkwood_ehci_init();
         platform_device_register(&hp_t5325_button_device);
 
+        i2c_register_board_info(0, i2c_board_info, ARRAY_SIZE(i2c_board_info));
+        kirkwood_audio_init();
+
         if (gpio_request(HP_T5325_GPIO_POWER_OFF, "power-off") == 0 &&
             gpio_direction_output(HP_T5325_GPIO_POWER_OFF, 0) == 0)
                 pm_power_off = hp_t5325_power_off;
@@ -187,6 +204,7 @@ MACHINE_START(T5325, "HP t5325 Thin Client")
         .boot_params    = 0x00000100,
         .init_machine   = hp_t5325_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index dc999c4c5806..68f32f2bf552 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -135,6 +135,7 @@ MACHINE_START(TS219, "QNAP TS-119/TS-219")
         .boot_params    = 0x00000100,
         .init_machine   = qnap_ts219_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 9a44029915e2..d5d009970705 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -154,6 +154,8 @@ static void __init qnap_ts41x_init(void)
 static int __init ts41x_pci_init(void)
 {
         if (machine_is_ts41x()) {
+                u32 dev, rev;
+
                 /*
                  * Without this explicit reset, the PCIe SATA controller
                  * (Marvell 88sx7042/sata_mv) is known to stop working
@@ -161,7 +163,11 @@ static int __init ts41x_pci_init(void)
                  */
                 orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
 
-                kirkwood_pcie_init(KW_PCIE0);
+                kirkwood_pcie_id(&dev, &rev);
+                if (dev == MV88F6282_DEV_ID)
+                        kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
+                else
+                        kirkwood_pcie_init(KW_PCIE0);
         }
 
    return 0;
@@ -173,6 +179,7 @@ MACHINE_START(TS41X, "QNAP TS-41x")
         .boot_params    = 0x00000100,
         .init_machine   = qnap_ts41x_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c
index 818f19d7ab1f..e41e909cf8f4 100644
--- a/arch/arm/mach-loki/common.c
+++ b/arch/arm/mach-loki/common.c
@@ -18,6 +18,7 @@
 #include <asm/timex.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <mach/bridge-regs.h>
 #include <mach/loki.h>
 #include <plat/orion_nand.h>
 #include <plat/time.h>
@@ -290,9 +291,15 @@ void __init loki_uart1_init(void)
 /*****************************************************************************
  * Time handling
  ****************************************************************************/
+void __init loki_init_early(void)
+{
+        orion_time_set_base(TIMER_VIRT_BASE);
+}
+
 static void loki_timer_init(void)
 {
-        orion_time_init(IRQ_LOKI_BRIDGE, LOKI_TCLK);
+        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+                        IRQ_LOKI_BRIDGE, LOKI_TCLK);
 }
 
 struct sys_timer loki_timer = {
diff --git a/arch/arm/mach-loki/common.h b/arch/arm/mach-loki/common.h
index 26054fd0f05e..a315dcf8887c 100644
--- a/arch/arm/mach-loki/common.h
+++ b/arch/arm/mach-loki/common.h
@@ -18,6 +18,7 @@ struct mv643xx_eth_platform_data;
  */
 void loki_map_io(void);
 void loki_init(void);
+void loki_init_early(void);
 void loki_init_irq(void);
 
 extern struct mbus_dram_target_info loki_mbus_dram_info;
diff --git a/arch/arm/mach-loki/include/mach/bridge-regs.h b/arch/arm/mach-loki/include/mach/bridge-regs.h
index a3fabf70044f..fd87732097cd 100644
--- a/arch/arm/mach-loki/include/mach/bridge-regs.h
+++ b/arch/arm/mach-loki/include/mach/bridge-regs.h
@@ -17,11 +17,6 @@
 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
 #define SOFT_RESET              0x00000001
 
-#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
-
-#define BRIDGE_MASK             (BRIDGE_VIRT_BASE | 0x0114)
-#define BRIDGE_INT_TIMER0       0x0002
-#define BRIDGE_INT_TIMER1       0x0004
 #define BRIDGE_INT_TIMER1_CLR   0x0004
 
 #define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
diff --git a/arch/arm/mach-loki/lb88rc8480-setup.c b/arch/arm/mach-loki/lb88rc8480-setup.c
index a1e75e7fc500..35eae4e6abb2 100644
--- a/arch/arm/mach-loki/lb88rc8480-setup.c
+++ b/arch/arm/mach-loki/lb88rc8480-setup.c
@@ -93,6 +93,7 @@ MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board")
         .boot_params    = 0x00000100,
         .init_machine   = lb88rc8480_init,
         .map_io         = loki_map_io,
+        .init_early     = loki_init_early,
         .init_irq       = loki_init_irq,
         .timer          = &loki_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
index 29e390e89ff4..20f3f125ed2b 100644
--- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
+++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
@@ -148,6 +148,7 @@ MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL")
         .boot_params    = 0x00000100,
         .init_machine   = wxl_init,
         .map_io         = mv78xx0_map_io,
+        .init_early     = mv78xx0_init_early,
         .init_irq       = mv78xx0_init_irq,
         .timer          = &mv78xx0_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 08465eb6a2c2..44fb4e55be0d 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -818,9 +818,15 @@ void __init mv78xx0_uart3_init(void)
 /*****************************************************************************
  * Time handling
  ****************************************************************************/
+void __init mv78xx0_init_early(void)
+{
+        orion_time_set_base(TIMER_VIRT_BASE);
+}
+
 static void mv78xx0_timer_init(void)
 {
-        orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk());
+        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+                        IRQ_MV78XX0_TIMER_1, get_tclk());
 }
 
 struct sys_timer mv78xx0_timer = {
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index befc22475469..632e63d65e7a 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -20,6 +20,7 @@ struct mv_sata_platform_data;
 int mv78xx0_core_index(void);
 void mv78xx0_map_io(void);
 void mv78xx0_init(void);
+void mv78xx0_init_early(void);
 void mv78xx0_init_irq(void);
 
 extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
index 207c95e403b9..df5aebe5b0fa 100644
--- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -96,6 +96,7 @@ MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
         .boot_params    = 0x00000100,
         .init_machine   = db78x00_init,
         .map_io         = mv78xx0_map_io,
+        .init_early     = mv78xx0_init_early,
         .init_irq       = mv78xx0_init_irq,
         .timer          = &mv78xx0_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
index 2d14c4fe294d..c64dbb96dbad 100644
--- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
@@ -20,10 +20,6 @@
 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
 #define SOFT_RESET              0x00000001
 
-#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
-#define BRIDGE_MASK             (BRIDGE_VIRT_BASE | 0x0114)
-#define BRIDGE_INT_TIMER0       0x0002
-#define BRIDGE_INT_TIMER1       0x0004
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 
 #define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
diff --git a/arch/arm/mach-mv78xx0/include/mach/gpio.h b/arch/arm/mach-mv78xx0/include/mach/gpio.h
index d9d1535ea100..77e1b843e768 100644
--- a/arch/arm/mach-mv78xx0/include/mach/gpio.h
+++ b/arch/arm/mach-mv78xx0/include/mach/gpio.h
@@ -6,35 +6,4 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#include <mach/irqs.h>
 #include <plat/gpio.h>
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-
-extern int mv78xx0_core_index(void);
-
-#define GPIO_MAX                32
-#define GPIO_OUT(pin)           (DEV_BUS_VIRT_BASE + 0x0100)
-#define GPIO_IO_CONF(pin)       (DEV_BUS_VIRT_BASE + 0x0104)
-#define GPIO_BLINK_EN(pin)      (DEV_BUS_VIRT_BASE + 0x0108)
-#define GPIO_IN_POL(pin)        (DEV_BUS_VIRT_BASE + 0x010c)
-#define GPIO_DATA_IN(pin)       (DEV_BUS_VIRT_BASE + 0x0110)
-#define GPIO_EDGE_CAUSE(pin)    (DEV_BUS_VIRT_BASE + 0x0114)
-#define GPIO_MASK_OFF           (mv78xx0_core_index() ? 0x18 : 0)
-#define GPIO_EDGE_MASK(pin)     (DEV_BUS_VIRT_BASE + 0x0118 + GPIO_MASK_OFF)
-#define GPIO_LEVEL_MASK(pin)    (DEV_BUS_VIRT_BASE + 0x011c + GPIO_MASK_OFF)
-
-static inline int gpio_to_irq(int pin)
-{
-        return pin + IRQ_MV78XX0_GPIO_START;
-}
-
-static inline int irq_to_gpio(int irq)
-{
-        return irq - IRQ_MV78XX0_GPIO_START;
-}
-
-
-#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index 3eff39921d4d..3674497162e3 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -71,6 +71,7 @@
 #define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x10000)
 #define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE | 0x0030)
 #define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE | 0x0034)
+#define  GPIO_VIRT_BASE         (DEV_BUS_VIRT_BASE | 0x0100)
 #define  I2C_0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1000)
 #define  I2C_1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1100)
 #define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index 22b4ff893b3c..08da497c39c2 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -26,28 +26,18 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
 void __init mv78xx0_init_irq(void)
 {
-        int i;
-
-        /* Initialize gpiolib. */
-        orion_gpio_init();
-
         orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
         orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
         orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
 
         /*
-         * Mask and clear GPIO IRQ interrupts.
+         * Initialize gpiolib for GPIOs 0-31.  (The GPIO interrupt mask
+         * registers for core #1 are at an offset of 0x18 from those of
+         * core #0.)
          */
-        writel(0, GPIO_LEVEL_MASK(0));
-        writel(0, GPIO_EDGE_MASK(0));
-        writel(0, GPIO_EDGE_CAUSE(0));
-
-        for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) {
-                set_irq_chip(i, &orion_gpio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                irq_desc[i].status |= IRQ_LEVEL;
-                set_irq_flags(i, IRQF_VALID);
-        }
+        orion_gpio_init(0, 32, GPIO_VIRT_BASE,
+                        mv78xx0_core_index() ? 0x18 : 0,
+                        IRQ_MV78XX0_GPIO_START);
         set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
         set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
         set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index 84db2dfc475c..65b72c454cb0 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -44,9 +44,6 @@ void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
         if (!variant_mask)
                 return;
 
-        /* Initialize gpiolib. */
-        orion_gpio_init();
-
         printk(KERN_DEBUG "initial MPP regs:");
         for (i = 0; i < MPP_NR_REGS; i++) {
                 mpp_ctrl[i] = readl(MPP_CTRL(i));
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
index 3511ad4d973b..d927f14c6810 100644
--- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
+++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
@@ -81,6 +81,7 @@ MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board")
         .boot_params    = 0x00000100,
         .init_machine   = rd78x00_masa_init,
         .map_io         = mv78xx0_map_io,
+        .init_early     = mv78xx0_init_early,
         .init_irq       = mv78xx0_init_irq,
         .timer          = &mv78xx0_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 0717f887cba0..340809a7d233 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -94,6 +94,7 @@ config MACH_MX31_3DS
         select MXC_DEBUG_BOARD
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_KEYPAD
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_EHCI
@@ -183,6 +184,7 @@ config MACH_MX35_3DS
         select MXC_DEBUG_BOARD
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
@@ -199,6 +201,15 @@ config MACH_KZM_ARM11_01
           Include support for KZM-ARM11-01. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_BUG
+        bool "Support Buglabs BUGBase platform"
+        select SOC_IMX31
+        select IMX_HAVE_PLATFORM_IMX_UART
+        default y
+        help
+          Include support for BUGBase 1.3 platform. This includes specific
+          configurations for the board and its peripherals.
+
 config MACH_EUKREA_CPUIMX35
         bool "Support Eukrea CPUIMX35 Platform"
         select SOC_IMX35
@@ -229,4 +240,18 @@ config MACH_EUKREA_MBIMXSD35_BASEBOARD
 
 endchoice
 
+config MACH_VPR200
+        bool "Support VPR200 platform"
+        select SOC_IMX35
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+        help
+          Include support for VPR200 platform. This includes specific
+          configurations for the board and its peripherals.
+
 endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 8db13294ad27..a54faf2cf5fa 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -5,8 +5,8 @@
 # Object file lists.
 
 obj-y                           := mm.o devices.o cpu.o
-obj-$(CONFIG_SOC_IMX31)         += clock-imx31.o iomux-imx31.o
-obj-$(CONFIG_SOC_IMX35)         += clock-imx35.o
+obj-$(CONFIG_SOC_IMX31)         += clock-imx31.o iomux-imx31.o ehci-imx31.o
+obj-$(CONFIG_SOC_IMX35)         += clock-imx35.o ehci-imx35.o
 obj-$(CONFIG_MACH_MX31ADS)      += mach-mx31ads.o
 obj-$(CONFIG_MACH_MX31LILLY)    += mach-mx31lilly.o mx31lilly-db.o
 obj-$(CONFIG_MACH_MX31LITE)     += mach-mx31lite.o mx31lite-db.o
@@ -20,5 +20,7 @@ obj-$(CONFIG_MACH_PCM043)	+= mach-pcm043.o
 obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
 obj-$(CONFIG_MACH_MX35_3DS)     += mach-mx35_3ds.o
 obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
+obj-$(CONFIG_MACH_BUG)          += mach-bug.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX35)      += mach-cpuimx35.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD)   += eukrea_mbimxsd-baseboard.o
+obj-$(CONFIG_MACH_VPR200)       += mach-vpr200.o
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
index 677b18aa7ae6..d545d86cc202 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -35,7 +35,7 @@ extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
 #define imx35_add_imx_i2c2(pdata)       imx35_add_imx_i2c(2, pdata)
 
 extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst;
-#define imx31_add_imx_keypad(pdata)     \
+#define imx35_add_imx_keypad(pdata)     \
         imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
 
 extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
diff --git a/arch/arm/mach-mx3/ehci-imx31.c b/arch/arm/mach-mx3/ehci-imx31.c
new file mode 100644
index 000000000000..314a983ac614
--- /dev/null
+++ b/arch/arm/mach-mx3/ehci-imx31.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
+
+#define USBCTRL_OTGBASE_OFFSET  0x600
+
+#define MX31_OTG_SIC_SHIFT      29
+#define MX31_OTG_SIC_MASK       (0x3 << MX31_OTG_SIC_SHIFT)
+#define MX31_OTG_PM_BIT         (1 << 24)
+
+#define MX31_H2_SIC_SHIFT       21
+#define MX31_H2_SIC_MASK        (0x3 << MX31_H2_SIC_SHIFT)
+#define MX31_H2_PM_BIT          (1 << 16)
+#define MX31_H2_DT_BIT          (1 << 5)
+
+#define MX31_H1_SIC_SHIFT       13
+#define MX31_H1_SIC_MASK        (0x3 << MX31_H1_SIC_SHIFT)
+#define MX31_H1_PM_BIT          (1 << 8)
+#define MX31_H1_DT_BIT          (1 << 4)
+
+int mx31_initialize_usb_hw(int port, unsigned int flags)
+{
+        unsigned int v;
+
+        v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+
+        switch (port) {
+        case 0: /* OTG port */
+                v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
+
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX31_OTG_PM_BIT;
+
+                break;
+        case 1: /* H1 port */
+                v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
+
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX31_H1_PM_BIT;
+
+                if (!(flags & MXC_EHCI_TTL_ENABLED))
+                        v |= MX31_H1_DT_BIT;
+
+                break;
+        case 2: /* H2 port */
+                v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
+
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX31_H2_PM_BIT;
+
+                if (!(flags & MXC_EHCI_TTL_ENABLED))
+                        v |= MX31_H2_DT_BIT;
+
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+
+        return 0;
+}
+
diff --git a/arch/arm/mach-mx3/ehci-imx35.c b/arch/arm/mach-mx3/ehci-imx35.c
new file mode 100644
index 000000000000..33983a478c6b
--- /dev/null
+++ b/arch/arm/mach-mx3/ehci-imx35.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
+
+#define USBCTRL_OTGBASE_OFFSET  0x600
+
+#define MX35_OTG_SIC_SHIFT      29
+#define MX35_OTG_SIC_MASK       (0x3 << MX35_OTG_SIC_SHIFT)
+#define MX35_OTG_PM_BIT         (1 << 24)
+
+#define MX35_H1_SIC_SHIFT       21
+#define MX35_H1_SIC_MASK        (0x3 << MX35_H1_SIC_SHIFT)
+#define MX35_H1_PM_BIT          (1 << 8)
+#define MX35_H1_IPPUE_UP_BIT    (1 << 7)
+#define MX35_H1_IPPUE_DOWN_BIT  (1 << 6)
+#define MX35_H1_TLL_BIT         (1 << 5)
+#define MX35_H1_USBTE_BIT       (1 << 4)
+
+int mx35_initialize_usb_hw(int port, unsigned int flags)
+{
+        unsigned int v;
+
+        v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+
+        switch (port) {
+        case 0: /* OTG port */
+                v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
+
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX35_OTG_PM_BIT;
+
+                break;
+        case 1: /* H1 port */
+                v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+                        MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+                v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
+
+                if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                        v |= MX35_H1_PM_BIT;
+
+                if (!(flags & MXC_EHCI_TTL_ENABLED))
+                        v |= MX35_H1_TLL_BIT;
+
+                if (flags & MXC_EHCI_INTERNAL_PHY)
+                        v |= MX35_H1_USBTE_BIT;
+
+                if (flags & MXC_EHCI_IPPUE_DOWN)
+                        v |= MX35_H1_IPPUE_DOWN_BIT;
+
+                if (flags & MXC_EHCI_IPPUE_UP)
+                        v |= MX35_H1_IPPUE_UP_BIT;
+
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+
+        return 0;
+}
+
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
index 14a5ffc939ad..80761474c0f8 100644
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -165,8 +165,8 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
         MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
 };
 
-#define GPIO_LED1       (2 * 32 + 29)
-#define GPIO_SWITCH1    (2 * 32 + 25)
+#define GPIO_LED1       IMX_GPIO_NR(3, 29)
+#define GPIO_SWITCH1    IMX_GPIO_NR(3, 25)
 #define GPIO_LCDPWR     (4)
 
 static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
diff --git a/arch/arm/mach-mx3/iomux-imx31.c b/arch/arm/mach-mx3/iomux-imx31.c
index a1d7fa5123dc..cf8f8099ebd7 100644
--- a/arch/arm/mach-mx3/iomux-imx31.c
+++ b/arch/arm/mach-mx3/iomux-imx31.c
@@ -97,7 +97,7 @@ EXPORT_SYMBOL(mxc_iomux_set_pad);
  *      - reserves the pin so that it is not claimed by another driver
  *      - setups the iomux according to the configuration
  */
-int mxc_iomux_alloc_pin(const unsigned int pin, const char *label)
+int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
 {
         unsigned pad = pin & IOMUX_PADNUM_MASK;
 
@@ -118,10 +118,10 @@ int mxc_iomux_alloc_pin(const unsigned int pin, const char *label)
 }
 EXPORT_SYMBOL(mxc_iomux_alloc_pin);
 
-int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
                 const char *label)
 {
-        unsigned int *p = pin_list;
+        const unsigned int *p = pin_list;
         int i;
         int ret = -EINVAL;
 
@@ -139,7 +139,7 @@ setup_error:
 }
 EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
 
-void mxc_iomux_release_pin(const unsigned int pin)
+void mxc_iomux_release_pin(unsigned int pin)
 {
         unsigned pad = pin & IOMUX_PADNUM_MASK;
 
@@ -148,9 +148,9 @@ void mxc_iomux_release_pin(const unsigned int pin)
 }
 EXPORT_SYMBOL(mxc_iomux_release_pin);
 
-void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
+void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
 {
-        unsigned int *p = pin_list;
+        const unsigned int *p = pin_list;
         int i;
 
         for (i = 0; i < count; i++) {
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 28b6f414b5d5..226829bf7c25 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -133,7 +133,6 @@ static int armadillo5x0_pins[] = {
 };
 
 /* USB */
-#if defined(CONFIG_USB_ULPI)
 
 #define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4)
 #define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6)
@@ -176,8 +175,10 @@ static int usbotg_init(struct platform_device *pdev)
         gpio_set_value(OTG_RESET, 0/*LOW*/);
         mdelay(5);
         gpio_set_value(OTG_RESET, 1/*HIGH*/);
+        mdelay(10);
 
-        return 0;
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_INTERFACE_DIFF_UNI);
 
 otg_free_reset:
         gpio_free(OTG_RESET);
@@ -233,8 +234,10 @@ static int usbh2_init(struct platform_device *pdev)
         gpio_set_value(USBH2_RESET, 0/*LOW*/);
         mdelay(5);
         gpio_set_value(USBH2_RESET, 1/*HIGH*/);
+        mdelay(10);
 
-        return 0;
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_INTERFACE_DIFF_UNI);
 
 h2_free_reset:
         gpio_free(USBH2_RESET);
@@ -246,15 +249,12 @@ h2_free_cs:
 static struct mxc_usbh_platform_data usbotg_pdata __initdata = {
         .init   = usbotg_init,
         .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
         .init   = usbh2_init,
         .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
 };
-#endif /* CONFIG_USB_ULPI */
 
 /* RTC over I2C*/
 #define ARMADILLO5X0_RTC_GPIO   IOMUX_TO_GPIO(MX31_PIN_SRXD4)
@@ -547,15 +547,15 @@ static void __init armadillo5x0_init(void)
         i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
 
         /* USB */
-#if defined(CONFIG_USB_ULPI)
-        usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                        ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                        ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
-        imx31_add_mxc_ehci_otg(&usbotg_pdata);
-        imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-#endif
+
+        usbotg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                        ULPI_OTG_DRVVBUS_EXT);
+        if (usbotg_pdata.otg)
+                imx31_add_mxc_ehci_otg(&usbotg_pdata);
+        usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                        ULPI_OTG_DRVVBUS_EXT);
+        if (usbh2_pdata.otg)
+                imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
 }
 
 static void __init armadillo5x0_timer_init(void)
@@ -569,9 +569,10 @@ static struct sys_timer armadillo5x0_timer = {
 
 MACHINE_START(ARMADILLO5X0, "Armadillo-500")
         /* Maintainer: Alberto Panizzo  */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31_map_io,
-        .init_irq       = mx31_init_irq,
-        .timer          = &armadillo5x0_timer,
-        .init_machine   = armadillo5x0_init,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .map_io = mx31_map_io,
+        .init_early = imx31_init_early,
+        .init_irq = mx31_init_irq,
+        .timer = &armadillo5x0_timer,
+        .init_machine = armadillo5x0_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-bug.c b/arch/arm/mach-mx3/mach-bug.c
new file mode 100644
index 000000000000..d137d7078ee9
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-bug.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <mach/iomux-mx3.h>
+#include <mach/imx-uart.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+
+#include <asm/mach/time.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include "devices-imx31.h"
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static const unsigned int bug_pins[] __initconst = {
+        MX31_PIN_PC_RST__CTS5,
+        MX31_PIN_PC_VS2__RTS5,
+        MX31_PIN_PC_BVD2__TXD5,
+        MX31_PIN_PC_BVD1__RXD5,
+};
+
+static void __init bug_board_init(void)
+{
+        mxc_iomux_setup_multiple_pins(bug_pins,
+                                      ARRAY_SIZE(bug_pins), "uart-4");
+        imx31_add_imx_uart4(&uart_pdata);
+}
+
+static void __init bug_timer_init(void)
+{
+        mx31_clocks_init(26000000);
+}
+
+static struct sys_timer bug_timer = {
+        .init = bug_timer_init,
+};
+
+MACHINE_START(BUG, "BugLabs BUGBase")
+        .map_io = mx31_map_io,
+        .init_early = imx31_init_early,
+        .init_irq = mx31_init_irq,
+        .timer = &bug_timer,
+        .init_machine = bug_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
index 26ae90f02582..ec63d998f647 100644
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -60,7 +60,7 @@ static struct tsc2007_platform_data tsc2007_info = {
         .x_plate_ohms           = 180,
 };
 
-#define TSC2007_IRQGPIO         (2 * 32 + 2)
+#define TSC2007_IRQGPIO         IMX_GPIO_NR(3, 2)
 static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("pcf8563", 0x51),
@@ -111,15 +111,25 @@ static const struct mxc_nand_platform_data
         .flash_bbt      = 1,
 };
 
+static int eukrea_cpuimx35_otg_init(struct platform_device *pdev)
+{
+        return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
+
 static const struct mxc_usbh_platform_data otg_pdata __initconst = {
+        .init   = eukrea_cpuimx35_otg_init,
         .portsc = MXC_EHCI_MODE_UTMI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 
+static int eukrea_cpuimx35_usbh1_init(struct platform_device *pdev)
+{
+        return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
+                        MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
+}
+
 static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
+        .init   = eukrea_cpuimx35_usbh1_init,
         .portsc = MXC_EHCI_MODE_SERIAL,
-        .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
-                  MXC_EHCI_IPPUE_DOWN,
 };
 
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
@@ -146,7 +156,7 @@ __setup("otg_mode=", eukrea_cpuimx35_otg_mode);
 /*
  * Board specific initialization.
  */
-static void __init mxc_board_init(void)
+static void __init eukrea_cpuimx35_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
                         ARRAY_SIZE(eukrea_cpuimx35_pads));
@@ -184,9 +194,10 @@ struct sys_timer eukrea_cpuimx35_timer = {
 
 MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
         /* Maintainer: Eukrea Electromatique */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx35_map_io,
-        .init_irq       = mx35_init_irq,
-        .init_machine   = mxc_board_init,
-        .timer          = &eukrea_cpuimx35_timer,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .map_io = mx35_map_io,
+        .init_early = imx35_init_early,
+        .init_irq = mx35_init_irq,
+        .timer = &eukrea_cpuimx35_timer,
+        .init_machine = eukrea_cpuimx35_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index df1a6ce8e3e1..d35621d62b4d 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -266,17 +266,14 @@ static void __init kzm_timer_init(void)
 }
 
 static struct sys_timer kzm_timer = {
-        .init   = kzm_timer_init,
+        .init = kzm_timer_init,
 };
 
-/*
- * The following uses standard kernel macros define in arch.h in order to
- * initialize __mach_desc_KZM_ARM11_01 data structure.
- */
 MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = kzm_map_io,
-        .init_irq       = mx31_init_irq,
-        .init_machine   = kzm_board_init,
-        .timer          = &kzm_timer,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .map_io = kzm_map_io,
+        .init_early = imx31_init_early,
+        .init_irq = mx31_init_irq,
+        .timer = &kzm_timer,
+        .init_machine = kzm_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 0d65db885be7..544d3e414f58 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -21,9 +21,13 @@
 #include <linux/platform_device.h>
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
+#include <linux/spi/l4f00242t03.h>
 #include <linux/regulator/machine.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
+#include <linux/memblock.h>
+
+#include <media/soc_camera.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -35,6 +39,10 @@
 #include <mach/iomux-mx3.h>
 #include <mach/3ds_debugboard.h>
 #include <mach/ulpi.h>
+#include <mach/mmc.h>
+#include <mach/ipu.h>
+#include <mach/mx3fb.h>
+#include <mach/mx3_camera.h>
 
 #include "devices-imx31.h"
 #include "devices.h"
@@ -42,10 +50,6 @@
 /* CPLD IRQ line for external uart, external ethernet etc */
 #define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
 
-/*
- * This file contains the board-specific initialization routines.
- */
-
 static int mx31_3ds_pins[] = {
         /* UART1 */
         MX31_PIN_CTS1__CTS1,
@@ -53,6 +57,12 @@ static int mx31_3ds_pins[] = {
         MX31_PIN_TXD1__TXD1,
         MX31_PIN_RXD1__RXD1,
         IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
+        /*SPI0*/
+        MX31_PIN_CSPI1_SCLK__SCLK,
+        MX31_PIN_CSPI1_MOSI__MOSI,
+        MX31_PIN_CSPI1_MISO__MISO,
+        MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
+        MX31_PIN_CSPI1_SS2__SS2, /* CS for LCD */
         /* SPI 1 */
         MX31_PIN_CSPI2_SCLK__SCLK,
         MX31_PIN_CSPI2_MOSI__MOSI,
@@ -100,6 +110,252 @@ static int mx31_3ds_pins[] = {
         IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
         /* USB Host2 reset */
         IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
+        /* I2C1 */
+        MX31_PIN_I2C_CLK__I2C1_SCL,
+        MX31_PIN_I2C_DAT__I2C1_SDA,
+        /* SDHC1 */
+        MX31_PIN_SD1_DATA3__SD1_DATA3,
+        MX31_PIN_SD1_DATA2__SD1_DATA2,
+        MX31_PIN_SD1_DATA1__SD1_DATA1,
+        MX31_PIN_SD1_DATA0__SD1_DATA0,
+        MX31_PIN_SD1_CLK__SD1_CLK,
+        MX31_PIN_SD1_CMD__SD1_CMD,
+        MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
+        MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
+        /* Framebuffer */
+        MX31_PIN_LD0__LD0,
+        MX31_PIN_LD1__LD1,
+        MX31_PIN_LD2__LD2,
+        MX31_PIN_LD3__LD3,
+        MX31_PIN_LD4__LD4,
+        MX31_PIN_LD5__LD5,
+        MX31_PIN_LD6__LD6,
+        MX31_PIN_LD7__LD7,
+        MX31_PIN_LD8__LD8,
+        MX31_PIN_LD9__LD9,
+        MX31_PIN_LD10__LD10,
+        MX31_PIN_LD11__LD11,
+        MX31_PIN_LD12__LD12,
+        MX31_PIN_LD13__LD13,
+        MX31_PIN_LD14__LD14,
+        MX31_PIN_LD15__LD15,
+        MX31_PIN_LD16__LD16,
+        MX31_PIN_LD17__LD17,
+        MX31_PIN_VSYNC3__VSYNC3,
+        MX31_PIN_HSYNC__HSYNC,
+        MX31_PIN_FPSHIFT__FPSHIFT,
+        MX31_PIN_CONTRAST__CONTRAST,
+        /* CSI */
+        MX31_PIN_CSI_D6__CSI_D6,
+        MX31_PIN_CSI_D7__CSI_D7,
+        MX31_PIN_CSI_D8__CSI_D8,
+        MX31_PIN_CSI_D9__CSI_D9,
+        MX31_PIN_CSI_D10__CSI_D10,
+        MX31_PIN_CSI_D11__CSI_D11,
+        MX31_PIN_CSI_D12__CSI_D12,
+        MX31_PIN_CSI_D13__CSI_D13,
+        MX31_PIN_CSI_D14__CSI_D14,
+        MX31_PIN_CSI_D15__CSI_D15,
+        MX31_PIN_CSI_HSYNC__CSI_HSYNC,
+        MX31_PIN_CSI_MCLK__CSI_MCLK,
+        MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
+        MX31_PIN_CSI_VSYNC__CSI_VSYNC,
+        MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
+        IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
+};
+
+/*
+ * Camera support
+ */
+static phys_addr_t mx3_camera_base __initdata;
+#define MX31_3DS_CAMERA_BUF_SIZE SZ_8M
+
+#define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
+#define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1)
+
+static struct gpio mx31_3ds_camera_gpios[] = {
+        { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" },
+        { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
+};
+
+static int __init mx31_3ds_camera_alloc_dma(void)
+{
+        int dma;
+
+        if (!mx3_camera_base)
+                return -ENOMEM;
+
+        dma = dma_declare_coherent_memory(&mx3_camera.dev,
+                                        mx3_camera_base, mx3_camera_base,
+                                        MX31_3DS_CAMERA_BUF_SIZE,
+                                        DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+
+        if (!(dma & DMA_MEMORY_MAP))
+                return -ENOMEM;
+
+        return 0;
+}
+
+static int mx31_3ds_camera_power(struct device *dev, int on)
+{
+        /* enable or disable the camera */
+        pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
+        gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1);
+
+        if (!on)
+                goto out;
+
+        /* If enabled, give a reset impulse */
+        gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0);
+        msleep(20);
+        gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1);
+        msleep(100);
+
+out:
+        return 0;
+}
+
+static struct i2c_board_info mx31_3ds_i2c_camera = {
+        I2C_BOARD_INFO("ov2640", 0x30),
+};
+
+static struct regulator_bulk_data mx31_3ds_camera_regs[] = {
+        { .supply = "cmos_vcore" },
+        { .supply = "cmos_2v8" },
+};
+
+static struct soc_camera_link iclink_ov2640 = {
+        .bus_id         = 0,
+        .board_info     = &mx31_3ds_i2c_camera,
+        .i2c_adapter_id = 0,
+        .power          = mx31_3ds_camera_power,
+        .regulators     = mx31_3ds_camera_regs,
+        .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs),
+};
+
+static struct platform_device mx31_3ds_ov2640 = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &iclink_ov2640,
+        },
+};
+
+struct mx3_camera_pdata mx31_3ds_camera_pdata = {
+        .dma_dev        = &mx3_ipu.dev,
+        .flags          = MX3_CAMERA_DATAWIDTH_10,
+        .mclk_10khz     = 2600,
+};
+
+/*
+ * FB support
+ */
+static const struct fb_videomode fb_modedb[] = {
+        {       /* 480x640 @ 60 Hz */
+                .name           = "Epson-VGA",
+                .refresh        = 60,
+                .xres           = 480,
+                .yres           = 640,
+                .pixclock       = 41701,
+                .left_margin    = 20,
+                .right_margin   = 41,
+                .upper_margin   = 10,
+                .lower_margin   = 5,
+                .hsync_len      = 20,
+                .vsync_len      = 10,
+                .sync           = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
+        },
+};
+
+static struct ipu_platform_data mx3_ipu_data = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata = {
+        .dma_dev        = &mx3_ipu.dev,
+        .name           = "Epson-VGA",
+        .mode           = fb_modedb,
+        .num_modes      = ARRAY_SIZE(fb_modedb),
+};
+
+/* LCD */
+static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
+        .reset_gpio             = IOMUX_TO_GPIO(MX31_PIN_LCS1),
+        .data_enable_gpio       = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
+        .core_supply            = "lcd_2v8",
+        .io_supply              = "vdd_lcdio",
+};
+
+/*
+ * Support for SD card slot in personality board
+ */
+#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
+#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
+
+static struct gpio mx31_3ds_sdhc1_gpios[] = {
+        { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
+        { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
+};
+
+static int mx31_3ds_sdhc1_init(struct device *dev,
+                               irq_handler_t detect_irq,
+                               void *data)
+{
+        int ret;
+
+        ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
+                                 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
+        if (ret) {
+                pr_warning("Unable to request the SD/MMC GPIOs.\n");
+                return ret;
+        }
+
+        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
+                          detect_irq, IRQF_DISABLED |
+                          IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
+                          "sdhc1-detect", data);
+        if (ret) {
+                pr_warning("Unable to request the SD/MMC card-detect IRQ.\n");
+                goto gpio_free;
+        }
+
+        return 0;
+
+gpio_free:
+        gpio_free_array(mx31_3ds_sdhc1_gpios,
+                        ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
+        return ret;
+}
+
+static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
+{
+        free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
+        gpio_free_array(mx31_3ds_sdhc1_gpios,
+                         ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
+}
+
+static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
+{
+        /*
+         * While the voltage stuff is done by the driver, activate the
+         * Buffer Enable Pin only if there is a card in slot to fix the card
+         * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
+         * Done here because at this stage we have for sure a debounced value
+         * of the presence of the card, showed by the value of vdd.
+         * 7 == ilog2(MMC_VDD_165_195)
+         */
+        if (vdd > 7)
+                gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
+        else
+                gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
+}
+
+static struct imxmmc_platform_data sdhc1_pdata = {
+        .init           = mx31_3ds_sdhc1_init,
+        .exit           = mx31_3ds_sdhc1_exit,
+        .setpower       = mx31_3ds_sdhc1_setpower,
 };
 
 /*
@@ -138,7 +394,71 @@ static struct regulator_init_data gpo_init = {
         }
 };
 
-static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
+static struct regulator_consumer_supply vmmc2_consumers[] = {
+        REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
+};
+
+static struct regulator_init_data vmmc2_init = {
+        .constraints = {
+                .min_uV = 3000000,
+                .max_uV = 3000000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                  REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
+        .consumer_supplies = vmmc2_consumers,
+};
+
+static struct regulator_consumer_supply vmmc1_consumers[] = {
+        REGULATOR_SUPPLY("lcd_2v8", NULL),
+        REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
+};
+
+static struct regulator_init_data vmmc1_init = {
+        .constraints = {
+                .min_uV = 2800000,
+                .max_uV = 2800000,
+                .apply_uV = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                  REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
+        .consumer_supplies = vmmc1_consumers,
+};
+
+static struct regulator_consumer_supply vgen_consumers[] = {
+        REGULATOR_SUPPLY("vdd_lcdio", NULL),
+};
+
+static struct regulator_init_data vgen_init = {
+        .constraints = {
+                .min_uV = 1800000,
+                .max_uV = 1800000,
+                .apply_uV = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                  REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
+        .consumer_supplies = vgen_consumers,
+};
+
+static struct regulator_consumer_supply vvib_consumers[] = {
+        REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
+};
+
+static struct regulator_init_data vvib_init = {
+        .constraints = {
+                .min_uV = 1300000,
+                .max_uV = 1300000,
+                .apply_uV = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                  REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
+        .consumer_supplies = vvib_consumers,
+};
+
+static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
         {
                 .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
                 .init_data = &pwgtx_init,
@@ -152,17 +472,38 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
         }, {
                 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
                 .init_data = &gpo_init,
+        }, {
+                .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
+                .init_data = &vmmc2_init,
+        }, {
+                .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
+                .init_data = &vmmc1_init,
+        }, {
+                .id = MC13783_REG_VGEN,  /* Power LCD */
+                .init_data = &vgen_init,
+        }, {
+                .id = MC13783_REG_VVIB,  /* Power CMOS */
+                .init_data = &vvib_init,
         },
 };
 
 /* MC13783 */
-static struct mc13783_platform_data mc13783_pdata __initdata = {
+static struct mc13xxx_platform_data mc13783_pdata __initdata = {
         .regulators = mx31_3ds_regulators,
         .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
-        .flags  = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN,
+        .flags  = MC13XXX_USE_REGULATOR | MC13XXX_USE_TOUCHSCREEN
 };
 
 /* SPI */
+static int spi0_internal_chipselect[] = {
+        MXC_SPI_CS(2),
+};
+
+static const struct spi_imx_master spi0_pdata __initconst = {
+        .chipselect     = spi0_internal_chipselect,
+        .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect),
+};
+
 static int spi1_internal_chipselect[] = {
         MXC_SPI_CS(0),
         MXC_SPI_CS(2),
@@ -182,6 +523,12 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
                 .platform_data  = &mc13783_pdata,
                 .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
                 .mode = SPI_CS_HIGH,
+        }, {
+                .modalias       = "l4f00242t03",
+                .max_speed_hz   = 5000000,
+                .bus_num        = 0,
+                .chip_select    = 0, /* SS2 */
+                .platform_data  = &mx31_3ds_l4f00242t03_pdata,
         },
 };
 
@@ -245,6 +592,11 @@ usbotg_free_reset:
         return err;
 }
 
+static int mx31_3ds_otg_init(struct platform_device *pdev)
+{
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
+}
+
 static int mx31_3ds_host2_init(struct platform_device *pdev)
 {
         int err;
@@ -276,25 +628,25 @@ static int mx31_3ds_host2_init(struct platform_device *pdev)
 
         mdelay(1);
         gpio_set_value(USBH2_RST_B, 1);
-        return 0;
+
+        mdelay(10);
+
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
 
 usbotg_free_reset:
         gpio_free(USBH2_RST_B);
         return err;
 }
 
-#if defined(CONFIG_USB_ULPI)
 static struct mxc_usbh_platform_data otg_pdata __initdata = {
+        .init   = mx31_3ds_otg_init,
         .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
 
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
         .init = mx31_3ds_host2_init,
         .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
-#endif
 
 static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
@@ -320,19 +672,18 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-/*
- * Set up static virtual mappings.
- */
-static void __init mx31_3ds_map_io(void)
-{
-        mx31_map_io();
-}
+static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
+        .bitrate = 100000,
+};
 
-/*!
- * Board specific initialization.
- */
-static void __init mxc_board_init(void)
+static struct platform_device *devices[] __initdata = {
+        &mx31_3ds_ov2640,
+};
+
+static void __init mx31_3ds_init(void)
 {
+        int ret;
+
         mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
                                       "mx31_3ds");
 
@@ -343,20 +694,22 @@ static void __init mxc_board_init(void)
         spi_register_board_info(mx31_3ds_spi_devs,
                                                 ARRAY_SIZE(mx31_3ds_spi_devs));
 
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+
         imx31_add_imx_keypad(&mx31_3ds_keymap_data);
 
         mx31_3ds_usbotg_init();
-#if defined(CONFIG_USB_ULPI)
         if (otg_mode_host) {
-                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
-                imx31_add_mxc_ehci_otg(&otg_pdata);
+                otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                                ULPI_OTG_DRVVBUS_EXT);
+                if (otg_pdata.otg)
+                        imx31_add_mxc_ehci_otg(&otg_pdata);
         }
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-        imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-#endif
+        usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                        ULPI_OTG_DRVVBUS_EXT);
+        if (usbh2_pdata.otg)
+                imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
+
         if (!otg_mode_host)
                 imx31_add_fsl_usb2_udc(&usbotg_pdata);
 
@@ -364,6 +717,26 @@ static void __init mxc_board_init(void)
                 printk(KERN_WARNING "Init of the debug board failed, all "
                                     "devices on the debug board are unusable.\n");
         imx31_add_imx2_wdt(NULL);
+        imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
+        imx31_add_mxc_mmc(0, &sdhc1_pdata);
+
+        imx31_add_spi_imx0(&spi0_pdata);
+        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
+        mxc_register_device(&mx3_fb, &mx3fb_pdata);
+
+        /* CSI */
+        /* Camera power: default - off */
+        ret = gpio_request_array(mx31_3ds_camera_gpios,
+                                 ARRAY_SIZE(mx31_3ds_camera_gpios));
+        if (ret) {
+                pr_err("Failed to request camera gpios");
+                iclink_ov2640.power = NULL;
+        }
+
+        if (!mx31_3ds_camera_alloc_dma())
+                mxc_register_device(&mx3_camera, &mx31_3ds_camera_pdata);
+        else
+                pr_err("Failed to allocate dma memory for camera");
 }
 
 static void __init mx31_3ds_timer_init(void)
@@ -375,15 +748,22 @@ static struct sys_timer mx31_3ds_timer = {
         .init   = mx31_3ds_timer_init,
 };
 
-/*
- * The following uses standard kernel macros defined in arch.h in order to
- * initialize __mach_desc_MX31_3DS data structure.
- */
+static void __init mx31_3ds_reserve(void)
+{
+        /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
+        mx3_camera_base = memblock_alloc(MX31_3DS_CAMERA_BUF_SIZE,
+                                         MX31_3DS_CAMERA_BUF_SIZE);
+        memblock_free(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
+        memblock_remove(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
+}
+
 MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31_3ds_map_io,
-        .init_irq       = mx31_init_irq,
-        .init_machine   = mxc_board_init,
-        .timer          = &mx31_3ds_timer,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .map_io = mx31_map_io,
+        .init_early = imx31_init_early,
+        .init_irq = mx31_init_irq,
+        .timer = &mx31_3ds_timer,
+        .init_machine = mx31_3ds_init,
+        .reserve = mx31_3ds_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index 88b97d62b57e..4e4b780c481d 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -69,12 +69,8 @@
 #define EXPIO_INT_XUART_INTB    (MXC_EXP_IO_BASE + 11)
 
 #define MXC_MAX_EXP_IO_LINES    16
-/*
- * This file contains the board-specific initialization routines.
- */
 
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
-/*!
+/*
  * The serial port definition structure.
  */
 static struct plat_serial8250_port serial_platform_data[] = {
@@ -110,14 +106,7 @@ static int __init mxc_init_extuart(void)
 {
         return platform_device_register(&serial_device);
 }
-#else
-static inline int mxc_init_extuart(void)
-{
-        return 0;
-}
-#endif
 
-#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -134,11 +123,6 @@ static inline void mxc_init_imx_uart(void)
         mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
         imx31_add_imx_uart0(&uart_pdata);
 }
-#else /* !SERIAL_IMX */
-static inline void mxc_init_imx_uart(void)
-{
-}
-#endif /* !SERIAL_IMX */
 
 static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
 {
@@ -160,7 +144,7 @@ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
 
 /*
  * Disable an expio pin's interrupt by setting the bit in the imr.
- * @param irq           an expio virtual irq number
+ * @param d     an expio virtual irq description
  */
 static void expio_mask_irq(struct irq_data *d)
 {
@@ -172,7 +156,7 @@ static void expio_mask_irq(struct irq_data *d)
 
 /*
  * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
- * @param irq           an expanded io virtual irq number
+ * @param d     an expio virtual irq description
  */
 static void expio_ack_irq(struct irq_data *d)
 {
@@ -183,7 +167,7 @@ static void expio_ack_irq(struct irq_data *d)
 
 /*
  * Enable a expio pin's interrupt by clearing the bit in the imr.
- * @param irq           a expio virtual irq number
+ * @param d     an expio virtual irq description
  */
 static void expio_unmask_irq(struct irq_data *d)
 {
@@ -476,7 +460,6 @@ static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
 };
 #endif
 
-#if defined(CONFIG_I2C_IMX) || defined(CONFIG_I2C_IMX_MODULE)
 static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
         {
@@ -497,11 +480,6 @@ static void mxc_init_i2c(void)
 
         imx31_add_imx_i2c1(NULL);
 }
-#else
-static void mxc_init_i2c(void)
-{
-}
-#endif
 
 static unsigned int ssi_pins[] = {
         MX31_PIN_SFS5__SFS5,
@@ -516,9 +494,7 @@ static void mxc_init_audio(void)
         mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
 }
 
-/*!
- * This structure defines static mappings for the i.MX31ADS board.
- */
+/* static mappings */
 static struct map_desc mx31ads_io_desc[] __initdata = {
         {
                 .virtual        = MX31_CS4_BASE_ADDR_VIRT,
@@ -528,9 +504,6 @@ static struct map_desc mx31ads_io_desc[] __initdata = {
         },
 };
 
-/*!
- * Set up static virtual mappings.
- */
 static void __init mx31ads_map_io(void)
 {
         mx31_map_io();
@@ -543,10 +516,7 @@ static void __init mx31ads_init_irq(void)
         mx31ads_init_expio();
 }
 
-/*!
- * Board specific initialization.
- */
-static void __init mxc_board_init(void)
+static void __init mx31ads_init(void)
 {
         mxc_init_extuart();
         mxc_init_imx_uart();
@@ -563,15 +533,12 @@ static struct sys_timer mx31ads_timer = {
         .init   = mx31ads_timer_init,
 };
 
-/*
- * The following uses standard kernel macros defined in arch.h in order to
- * initialize __mach_desc_MX31ADS data structure.
- */
 MACHINE_START(MX31ADS, "Freescale MX31ADS")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31ads_map_io,
-        .init_irq       = mx31ads_init_irq,
-        .init_machine   = mxc_board_init,
-        .timer          = &mx31ads_timer,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .map_io = mx31ads_map_io,
+        .init_early = imx31_init_early,
+        .init_irq = mx31ads_init_irq,
+        .timer = &mx31ads_timer,
+        .init_machine = mx31ads_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index 2c595483f356..ed95745163b8 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -24,6 +24,7 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/gpio.h>
+#include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/smsc911x.h>
@@ -110,55 +111,9 @@ static struct platform_device physmap_flash_device = {
 
 /* USB */
 
-#if defined(CONFIG_USB_ULPI)
-
 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
                         PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
 
-static int usbotg_init(struct platform_device *pdev)
-{
-        unsigned int pins[] = {
-                MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
-                MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
-                MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
-                MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
-                MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
-                MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
-                MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
-                MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
-                MX31_PIN_USBOTG_CLK__USBOTG_CLK,
-                MX31_PIN_USBOTG_DIR__USBOTG_DIR,
-                MX31_PIN_USBOTG_NXT__USBOTG_NXT,
-                MX31_PIN_USBOTG_STP__USBOTG_STP,
-        };
-
-        mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB OTG");
-
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
-
-        mxc_iomux_set_gpr(MUX_PGP_USB_4WIRE, true);
-        mxc_iomux_set_gpr(MUX_PGP_USB_COMMON, true);
-
-        /* chip select */
-        mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE2, IOMUX_CONFIG_GPIO),
-                                "USBOTG_CS");
-        gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), "USBH1 CS");
-        gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), 0);
-
-        return 0;
-}
-
 static int usbh1_init(struct platform_device *pdev)
 {
         int pins[] = {
@@ -183,7 +138,10 @@ static int usbh1_init(struct platform_device *pdev)
 
         mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
 
-        return 0;
+        mdelay(10);
+
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_INTERFACE_SINGLE_UNI);
 }
 
 static int usbh2_init(struct platform_device *pdev)
@@ -220,41 +178,30 @@ static int usbh2_init(struct platform_device *pdev)
         gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
         gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
 
-        return 0;
-}
+        mdelay(10);
 
-static struct mxc_usbh_platform_data usbotg_pdata = {
-        .init   = usbotg_init,
-        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
-};
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
+}
 
 static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
         .init   = usbh1_init,
         .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
 };
 
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
         .init   = usbh2_init,
         .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
 
 static void lilly1131_usb_init(void)
 {
-        usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
         imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
-        imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-}
 
-#else
-static inline void lilly1131_usb_init(void) {}
-#endif /* CONFIG_USB_ULPI */
+        usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                        ULPI_OTG_DRVVBUS_EXT);
+        if (usbh2_pdata.otg)
+                imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
+}
 
 /* SPI */
 
@@ -274,8 +221,8 @@ static const struct spi_imx_master spi1_pdata __initconst = {
         .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
 
-static struct mc13783_platform_data mc13783_pdata __initdata = {
-        .flags = MC13783_USE_RTC | MC13783_USE_TOUCHSCREEN,
+static struct mc13xxx_platform_data mc13783_pdata __initdata = {
+        .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN,
 };
 
 static struct spi_board_info mc13783_dev __initdata = {
@@ -347,10 +294,10 @@ static struct sys_timer mx31lilly_timer = {
 };
 
 MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31_map_io,
-        .init_irq       = mx31_init_irq,
-        .init_machine   = mx31lilly_board_init,
-        .timer          = &mx31lilly_timer,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .map_io = mx31_map_io,
+        .init_early = imx31_init_early,
+        .init_irq = mx31_init_irq,
+        .timer = &mx31lilly_timer,
+        .init_machine = mx31lilly_board_init,
 MACHINE_END
-
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index 9e64c66396e0..24a21a384bf1 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -27,6 +27,7 @@
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
 #include <linux/mtd/physmap.h>
+#include <linux/delay.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -111,9 +112,9 @@ static const struct spi_imx_master spi1_pdata __initconst = {
         .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
 
-static struct mc13783_platform_data mc13783_pdata __initdata = {
-        .flags  = MC13783_USE_RTC |
-                  MC13783_USE_REGULATOR,
+static struct mc13xxx_platform_data mc13783_pdata __initdata = {
+        .flags  = MC13XXX_USE_RTC |
+                  MC13XXX_USE_REGULATOR,
 };
 
 static struct spi_board_info mc13783_spi_dev __initdata = {
@@ -129,7 +130,6 @@ static struct spi_board_info mc13783_spi_dev __initdata = {
  * USB
  */
 
-#if defined(CONFIG_USB_ULPI)
 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
                         PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
 
@@ -167,15 +167,15 @@ static int usbh2_init(struct platform_device *pdev)
         gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
         gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
 
-        return 0;
+        mdelay(10);
+
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
 }
 
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
         .init   = usbh2_init,
         .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
-#endif
 
 /*
  * NOR flash
@@ -227,7 +227,7 @@ void __init mx31lite_map_io(void)
 static int mx31lite_baseboard;
 core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
 
-static void __init mxc_board_init(void)
+static void __init mx31lite_init(void)
 {
         int ret;
 
@@ -252,13 +252,11 @@ static void __init mxc_board_init(void)
         imx31_add_spi_imx1(&spi1_pdata);
         spi_register_board_info(&mc13783_spi_dev, 1);
 
-#if defined(CONFIG_USB_ULPI)
         /* USB */
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
-        imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-#endif
+        usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                        ULPI_OTG_DRVVBUS_EXT);
+        if (usbh2_pdata.otg)
+                imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
 
         /* SMSC9117 IRQ pin */
         ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
@@ -281,9 +279,10 @@ struct sys_timer mx31lite_timer = {
 
 MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31lite_map_io,
-        .init_irq       = mx31_init_irq,
-        .init_machine   = mxc_board_init,
-        .timer          = &mx31lite_timer,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .map_io = mx31lite_map_io,
+        .init_early = imx31_init_early,
+        .init_irq = mx31_init_irq,
+        .timer = &mx31lite_timer,
+        .init_machine = mx31lite_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 1aa8d65fccbb..6f3692bccb8a 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -214,7 +214,7 @@ static struct regulator_init_data cam_vreg_data = {
         .consumer_supplies = cam_consumers,
 };
 
-static struct mc13783_regulator_init_data moboard_regulators[] = {
+static struct mc13xxx_regulator_init_data moboard_regulators[] = {
         {
                 .id = MC13783_REG_VMMC1,
                 .init_data = &sdhc_vreg_data,
@@ -267,12 +267,12 @@ static struct mc13783_leds_platform_data moboard_leds = {
         .tc2_period = MC13783_LED_PERIOD_10MS,
 };
 
-static struct mc13783_platform_data moboard_pmic = {
+static struct mc13xxx_platform_data moboard_pmic = {
         .regulators = moboard_regulators,
         .num_regulators = ARRAY_SIZE(moboard_regulators),
         .leds = &moboard_leds,
-        .flags = MC13783_USE_REGULATOR | MC13783_USE_RTC |
-                MC13783_USE_ADC | MC13783_USE_LED,
+        .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_RTC |
+                MC13XXX_USE_ADC | MC13XXX_USE_LED,
 };
 
 static struct spi_board_info moboard_spi_board_info[] __initdata = {
@@ -400,19 +400,24 @@ static void usb_xcvr_reset(void)
         mdelay(1);
 }
 
-#if defined(CONFIG_USB_ULPI)
+static int moboard_usbh2_init_hw(struct platform_device *pdev)
+{
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
+}
 
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
+        .init   = moboard_usbh2_init_hw,
         .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
 
 static int __init moboard_usbh2_init(void)
 {
         struct platform_device *pdev;
 
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                        ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+        usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                        ULPI_OTG_DRVVBUS_EXT);
+        if (!usbh2_pdata.otg)
+                return -ENODEV;
 
         pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
         if (IS_ERR(pdev))
@@ -420,10 +425,6 @@ static int __init moboard_usbh2_init(void)
 
         return 0;
 }
-#else
-static inline int moboard_usbh2_init(void) { return 0; }
-#endif
-
 
 static struct gpio_led mx31moboard_leds[] = {
         {
@@ -503,7 +504,7 @@ core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
 /*
  * Board specific initialization.
  */
-static void __init mxc_board_init(void)
+static void __init mx31moboard_init(void)
 {
         mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins),
                 "moboard");
@@ -564,10 +565,10 @@ struct sys_timer mx31moboard_timer = {
 
 MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
         /* Maintainer: Valentin Longchamp, EPFL Mobots group */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31_map_io,
-        .init_irq       = mx31_init_irq,
-        .init_machine   = mxc_board_init,
-        .timer          = &mx31moboard_timer,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .map_io = mx31_map_io,
+        .init_early = imx31_init_early,
+        .init_irq = mx31_init_irq,
+        .timer = &mx31moboard_timer,
+        .init_machine = mx31moboard_init,
 MACHINE_END
-
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
index b1963f257c20..ff5fe231b8d6 100644
--- a/arch/arm/mach-mx3/mach-mx35_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -118,24 +118,42 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
         MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
         MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
         MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
+        /* I2C1 */
+        MX35_PAD_I2C1_CLK__I2C1_SCL,
+        MX35_PAD_I2C1_DAT__I2C1_SDA,
 };
 
+static int mx35_3ds_otg_init(struct platform_device *pdev)
+{
+        return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
+}
+
 /* OTG config */
 static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
+        .workaround     = FLS_USB2_WORKAROUND_ENGCM09152,
+/*
+ * ENGCM09152 also requires a hardware change.
+ * Please check the MX35 Chip Errata document for details.
+ */
 };
 
 static struct mxc_usbh_platform_data otg_pdata __initdata = {
+        .init   = mx35_3ds_otg_init,
         .portsc = MXC_EHCI_MODE_UTMI,
-        .flags  = MXC_EHCI_INTERNAL_PHY,
 };
 
+static int mx35_3ds_usbh_init(struct platform_device *pdev)
+{
+        return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
+                          MXC_EHCI_INTERNAL_PHY);
+}
+
 /* USB HOST config */
 static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
+        .init           = mx35_3ds_usbh_init,
         .portsc         = MXC_EHCI_MODE_SERIAL,
-        .flags          = MXC_EHCI_INTERFACE_SINGLE_UNI |
-                          MXC_EHCI_INTERNAL_PHY,
 };
 
 static int otg_mode_host;
@@ -153,10 +171,14 @@ static int __init mx35_3ds_otg_mode(char *options)
 }
 __setup("otg_mode=", mx35_3ds_otg_mode);
 
+static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
+        .bitrate = 100000,
+};
+
 /*
  * Board specific initialization.
  */
-static void __init mxc_board_init(void)
+static void __init mx35_3ds_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
 
@@ -180,6 +202,7 @@ static void __init mxc_board_init(void)
         if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
                 pr_warn("Init of the debugboard failed, all "
                                 "devices on the debugboard are unusable.\n");
+        imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
 }
 
 static void __init mx35pdk_timer_init(void)
@@ -193,9 +216,10 @@ struct sys_timer mx35pdk_timer = {
 
 MACHINE_START(MX35_3DS, "Freescale MX35PDK")
         /* Maintainer: Freescale Semiconductor, Inc */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx35_map_io,
-        .init_irq       = mx35_init_irq,
-        .init_machine   = mxc_board_init,
-        .timer          = &mx35pdk_timer,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .map_io = mx35_map_io,
+        .init_early = imx35_init_early,
+        .init_irq = mx35_init_irq,
+        .timer = &mx35pdk_timer,
+        .init_machine = mx35_3ds_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index b752f6bc20a2..f07d3bded674 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -533,17 +533,25 @@ static struct platform_device pcm970_sja1000 = {
         .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
 };
 
-#if defined(CONFIG_USB_ULPI)
+static int pcm037_otg_init(struct platform_device *pdev)
+{
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
+
 static struct mxc_usbh_platform_data otg_pdata __initdata = {
+        .init   = pcm037_otg_init,
         .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 
+static int pcm037_usbh2_init(struct platform_device *pdev)
+{
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
+
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
+        .init   = pcm037_usbh2_init,
         .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
-#endif
 
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
@@ -568,7 +576,7 @@ __setup("otg_mode=", pcm037_otg_mode);
 /*
  * Board specific initialization.
  */
-static void __init mxc_board_init(void)
+static void __init pcm037_init(void)
 {
         int ret;
 
@@ -646,19 +654,18 @@ static void __init mxc_board_init(void)
 
         platform_device_register(&pcm970_sja1000);
 
-#if defined(CONFIG_USB_ULPI)
         if (otg_mode_host) {
-                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
-                imx31_add_mxc_ehci_otg(&otg_pdata);
+                otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                                ULPI_OTG_DRVVBUS_EXT);
+                if (otg_pdata.otg)
+                        imx31_add_mxc_ehci_otg(&otg_pdata);
         }
 
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+        usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                        ULPI_OTG_DRVVBUS_EXT);
+        if (usbh2_pdata.otg)
+                imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
 
-        imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-#endif
         if (!otg_mode_host)
                 imx31_add_fsl_usb2_udc(&otg_device_pdata);
 
@@ -675,9 +682,10 @@ struct sys_timer pcm037_timer = {
 
 MACHINE_START(PCM037, "Phytec Phycore pcm037")
         /* Maintainer: Pengutronix */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31_map_io,
-        .init_irq       = mx31_init_irq,
-        .init_machine   = mxc_board_init,
-        .timer          = &pcm037_timer,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .map_io = mx31_map_io,
+        .init_early = imx31_init_early,
+        .init_irq = mx31_init_irq,
+        .timer = &pcm037_timer,
+        .init_machine = pcm037_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c
index fda56545d2fd..df6fb07d037e 100644
--- a/arch/arm/mach-mx3/mach-pcm037_eet.c
+++ b/arch/arm/mach-mx3/mach-pcm037_eet.c
@@ -180,9 +180,7 @@ static int __init eet_init_devices(void)
 
         /* SPI */
         spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
         imx31_add_spi_imx0(&pcm037_spi1_pdata);
-#endif
 
         platform_device_register(&pcm037_gpio_keys_device);
 
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index bcf83fc7e701..b3ecfb22d241 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -115,7 +115,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
 static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
         .bitrate = 50000,
 };
@@ -134,7 +133,6 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
                 I2C_BOARD_INFO("pcf8563", 0x51),
         }
 };
-#endif
 
 static struct platform_device *devices[] __initdata = {
         &pcm043_flash,
@@ -221,9 +219,9 @@ static iomux_v3_cfg_t pcm043_pads[] = {
         MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
 };
 
-#define AC97_GPIO_TXFS  (1 * 32 + 31)
-#define AC97_GPIO_TXD   (1 * 32 + 28)
-#define AC97_GPIO_RESET (1 * 32 + 0)
+#define AC97_GPIO_TXFS  IMX_GPIO_NR(2, 31)
+#define AC97_GPIO_TXD   IMX_GPIO_NR(2, 28)
+#define AC97_GPIO_RESET IMX_GPIO_NR(2, 0)
 
 static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
 {
@@ -307,18 +305,26 @@ pcm037_nand_board_info __initconst = {
         .hw_ecc = 1,
 };
 
-#if defined(CONFIG_USB_ULPI)
+static int pcm043_otg_init(struct platform_device *pdev)
+{
+        return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
+
 static struct mxc_usbh_platform_data otg_pdata __initdata = {
+        .init   = pcm043_otg_init,
         .portsc = MXC_EHCI_MODE_UTMI,
-        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 
+static int pcm043_usbh1_init(struct platform_device *pdev)
+{
+        return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
+                        MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
+}
+
 static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
+        .init   = pcm043_usbh1_init,
         .portsc = MXC_EHCI_MODE_SERIAL,
-        .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
-                  MXC_EHCI_IPPUE_DOWN,
 };
-#endif
 
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
@@ -343,7 +349,7 @@ __setup("otg_mode=", pcm043_otg_mode);
 /*
  * Board specific initialization.
  */
-static void __init mxc_board_init(void)
+static void __init pcm043_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
 
@@ -369,26 +375,22 @@ static void __init mxc_board_init(void)
 
         imx35_add_imx_uart1(&uart_pdata);
 
-#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
         i2c_register_board_info(0, pcm043_i2c_devices,
                         ARRAY_SIZE(pcm043_i2c_devices));
 
         imx35_add_imx_i2c0(&pcm043_i2c0_data);
-#endif
 
         mxc_register_device(&mx3_ipu, &mx3_ipu_data);
         mxc_register_device(&mx3_fb, &mx3fb_pdata);
 
-#if defined(CONFIG_USB_ULPI)
         if (otg_mode_host) {
-                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
-                imx35_add_mxc_ehci_otg(&otg_pdata);
+                otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                                ULPI_OTG_DRVVBUS_EXT);
+                if (otg_pdata.otg)
+                        imx35_add_mxc_ehci_otg(&otg_pdata);
         }
-
         imx35_add_mxc_ehci_hs(&usbh1_pdata);
-#endif
+
         if (!otg_mode_host)
                 imx35_add_fsl_usb2_udc(&otg_device_pdata);
 
@@ -407,10 +409,10 @@ struct sys_timer pcm043_timer = {
 
 MACHINE_START(PCM043, "Phytec Phycore pcm043")
         /* Maintainer: Pengutronix */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx35_map_io,
-        .init_irq       = mx35_init_irq,
-        .init_machine   = mxc_board_init,
-        .timer          = &pcm043_timer,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .map_io = mx35_map_io,
+        .init_early = imx35_init_early,
+        .init_irq = mx35_init_irq,
+        .timer = &pcm043_timer,
+        .init_machine = pcm043_init,
 MACHINE_END
-
diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c
index fd1050c40964..17f758b77623 100644
--- a/arch/arm/mach-mx3/mach-qong.c
+++ b/arch/arm/mach-mx3/mach-qong.c
@@ -54,10 +54,6 @@
 
 #define QONG_FPGA_IRQ           IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
 
-/*
- * This file contains the board-specific initialization routines.
- */
-
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -247,7 +243,7 @@ static void __init qong_init_fpga(void)
 /*
  * Board specific initialization.
  */
-static void __init mxc_board_init(void)
+static void __init qong_init(void)
 {
         mxc_init_imx_uart();
         qong_init_nor_mtd();
@@ -263,16 +259,12 @@ static struct sys_timer qong_timer = {
         .init   = qong_timer_init,
 };
 
-/*
- * The following uses standard kernel macros defined in arch.h in order to
- * initialize __mach_desc_QONG data structure.
- */
-
 MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
         /* Maintainer: DENX Software Engineering GmbH */
-        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31_map_io,
-        .init_irq       = mx31_init_irq,
-        .init_machine   = mxc_board_init,
-        .timer          = &qong_timer,
+        .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .map_io = mx31_map_io,
+        .init_early = imx31_init_early,
+        .init_irq = mx31_init_irq,
+        .timer = &qong_timer,
+        .init_machine = qong_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-vpr200.c b/arch/arm/mach-mx3/mach-vpr200.c
new file mode 100644
index 000000000000..2cf390fbd980
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-vpr200.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix
+ * Copyright 2010 Creative Product Design
+ *
+ * Derived from mx35 3stack.
+ * Original author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/memory.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx35.h>
+#include <mach/irqs.h>
+#include <mach/ipu.h>
+#include <mach/mx3fb.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/mfd/mc13xxx.h>
+#include <linux/gpio_keys.h>
+
+#include "devices-imx35.h"
+#include "devices.h"
+
+#define GPIO_LCDPWR     IMX_GPIO_NR(1, 2)
+#define GPIO_PMIC_INT   IMX_GPIO_NR(2, 0)
+
+#define GPIO_BUTTON1    IMX_GPIO_NR(1, 4)
+#define GPIO_BUTTON2    IMX_GPIO_NR(1, 5)
+#define GPIO_BUTTON3    IMX_GPIO_NR(1, 7)
+#define GPIO_BUTTON4    IMX_GPIO_NR(1, 8)
+#define GPIO_BUTTON5    IMX_GPIO_NR(1, 9)
+#define GPIO_BUTTON6    IMX_GPIO_NR(1, 10)
+#define GPIO_BUTTON7    IMX_GPIO_NR(1, 11)
+#define GPIO_BUTTON8    IMX_GPIO_NR(1, 12)
+
+static const struct fb_videomode fb_modedb[] = {
+        {
+                /* 800x480 @ 60 Hz */
+                .name           = "PT0708048",
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 480,
+                .pixclock       = KHZ2PICOS(33260),
+                .left_margin    = 50,
+                .right_margin   = 156,
+                .upper_margin   = 10,
+                .lower_margin   = 10,
+                .hsync_len      = 1,    /* note: DE only display */
+                .vsync_len      = 1,    /* note: DE only display */
+                .sync           = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
+        }, {
+                /* 800x480 @ 60 Hz */
+                .name           = "CTP-CLAA070LC0ACW",
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 480,
+                .pixclock       = KHZ2PICOS(27000),
+                .left_margin    = 50,
+                .right_margin   = 50,   /* whole line should have 900 clocks */
+                .upper_margin   = 10,
+                .lower_margin   = 10,   /* whole frame should have 500 lines */
+                .hsync_len      = 1,    /* note: DE only display */
+                .vsync_len      = 1,    /* note: DE only display */
+                .sync           = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
+        }
+};
+
+static struct ipu_platform_data mx3_ipu_data = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata = {
+        .dma_dev        = &mx3_ipu.dev,
+        .name           = "PT0708048",
+        .mode           = fb_modedb,
+        .num_modes      = ARRAY_SIZE(fb_modedb),
+};
+
+static struct physmap_flash_data vpr200_flash_data = {
+        .width  = 2,
+};
+
+static struct resource vpr200_flash_resource = {
+        .start  = MX35_CS0_BASE_ADDR,
+        .end    = MX35_CS0_BASE_ADDR + SZ_64M - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device vpr200_flash = {
+        .name   = "physmap-flash",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &vpr200_flash_data,
+        },
+        .resource = &vpr200_flash_resource,
+        .num_resources = 1,
+};
+
+static const struct mxc_nand_platform_data
+                vpr200_nand_board_info __initconst = {
+        .width = 1,
+        .hw_ecc = 1,
+        .flash_bbt = 1,
+};
+
+#define VPR_KEY_DEBOUNCE        500
+static struct gpio_keys_button vpr200_gpio_keys_table[] = {
+        {KEY_F2, GPIO_BUTTON1, 1, "vpr-keys: F2", 0, VPR_KEY_DEBOUNCE},
+        {KEY_F3, GPIO_BUTTON2, 1, "vpr-keys: F3", 0, VPR_KEY_DEBOUNCE},
+        {KEY_F4, GPIO_BUTTON3, 1, "vpr-keys: F4", 0, VPR_KEY_DEBOUNCE},
+        {KEY_F5, GPIO_BUTTON4, 1, "vpr-keys: F5", 0, VPR_KEY_DEBOUNCE},
+        {KEY_F6, GPIO_BUTTON5, 1, "vpr-keys: F6", 0, VPR_KEY_DEBOUNCE},
+        {KEY_F7, GPIO_BUTTON6, 1, "vpr-keys: F7", 0, VPR_KEY_DEBOUNCE},
+        {KEY_F8, GPIO_BUTTON7, 1, "vpr-keys: F8", 1, VPR_KEY_DEBOUNCE},
+        {KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE},
+};
+
+static struct gpio_keys_platform_data vpr200_gpio_keys_data = {
+        .buttons = vpr200_gpio_keys_table,
+        .nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table),
+};
+
+static struct platform_device vpr200_device_gpiokeys = {
+        .name = "gpio-keys",
+        .dev = {
+                .platform_data = &vpr200_gpio_keys_data,
+        }
+};
+
+static struct mc13xxx_platform_data vpr200_pmic = {
+        .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
+};
+
+static const struct imxi2c_platform_data vpr200_i2c0_data __initconst = {
+        .bitrate = 50000,
+};
+
+static struct at24_platform_data vpr200_eeprom = {
+        .byte_len = 2048 / 8,
+        .page_size = 1,
+};
+
+static struct i2c_board_info vpr200_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("at24", 0x50), /* E0=0, E1=0, E2=0 */
+                .platform_data = &vpr200_eeprom,
+        }, {
+                I2C_BOARD_INFO("mc13892", 0x08),
+                .platform_data = &vpr200_pmic,
+                .irq = gpio_to_irq(GPIO_PMIC_INT),
+        }
+};
+
+static iomux_v3_cfg_t vpr200_pads[] = {
+        /* UART1 */
+        MX35_PAD_TXD1__UART1_TXD_MUX,
+        MX35_PAD_RXD1__UART1_RXD_MUX,
+        /* UART3 */
+        MX35_PAD_ATA_DATA10__UART3_RXD_MUX,
+        MX35_PAD_ATA_DATA11__UART3_TXD_MUX,
+        /* FEC */
+        MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+        MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+        MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+        MX35_PAD_FEC_COL__FEC_COL,
+        MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+        MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+        MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+        MX35_PAD_FEC_MDC__FEC_MDC,
+        MX35_PAD_FEC_MDIO__FEC_MDIO,
+        MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+        MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+        MX35_PAD_FEC_CRS__FEC_CRS,
+        MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+        MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+        MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+        MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+        MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+        MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+        /* Display */
+        MX35_PAD_LD0__IPU_DISPB_DAT_0,
+        MX35_PAD_LD1__IPU_DISPB_DAT_1,
+        MX35_PAD_LD2__IPU_DISPB_DAT_2,
+        MX35_PAD_LD3__IPU_DISPB_DAT_3,
+        MX35_PAD_LD4__IPU_DISPB_DAT_4,
+        MX35_PAD_LD5__IPU_DISPB_DAT_5,
+        MX35_PAD_LD6__IPU_DISPB_DAT_6,
+        MX35_PAD_LD7__IPU_DISPB_DAT_7,
+        MX35_PAD_LD8__IPU_DISPB_DAT_8,
+        MX35_PAD_LD9__IPU_DISPB_DAT_9,
+        MX35_PAD_LD10__IPU_DISPB_DAT_10,
+        MX35_PAD_LD11__IPU_DISPB_DAT_11,
+        MX35_PAD_LD12__IPU_DISPB_DAT_12,
+        MX35_PAD_LD13__IPU_DISPB_DAT_13,
+        MX35_PAD_LD14__IPU_DISPB_DAT_14,
+        MX35_PAD_LD15__IPU_DISPB_DAT_15,
+        MX35_PAD_LD16__IPU_DISPB_DAT_16,
+        MX35_PAD_LD17__IPU_DISPB_DAT_17,
+        MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+        MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+        MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+        /* LCD Enable */
+        MX35_PAD_D3_VSYNC__GPIO1_2,
+        /* USBOTG */
+        MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
+        MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
+        /* SDCARD */
+        MX35_PAD_SD1_CMD__ESDHC1_CMD,
+        MX35_PAD_SD1_CLK__ESDHC1_CLK,
+        MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+        MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+        MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+        MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
+        /* PMIC */
+        MX35_PAD_GPIO2_0__GPIO2_0,
+        /* GPIO keys */
+        MX35_PAD_SCKR__GPIO1_4,
+        MX35_PAD_COMPARE__GPIO1_5,
+        MX35_PAD_SCKT__GPIO1_7,
+        MX35_PAD_FST__GPIO1_8,
+        MX35_PAD_HCKT__GPIO1_9,
+        MX35_PAD_TX5_RX0__GPIO1_10,
+        MX35_PAD_TX4_RX1__GPIO1_11,
+        MX35_PAD_TX3_RX2__GPIO1_12,
+};
+
+/* USB Device config */
+static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_UTMI,
+        .workaround     = FLS_USB2_WORKAROUND_ENGCM09152,
+};
+
+/* USB HOST config */
+static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
+        .portsc         = MXC_EHCI_MODE_SERIAL,
+        .flags          = MXC_EHCI_INTERFACE_SINGLE_UNI |
+                          MXC_EHCI_INTERNAL_PHY,
+};
+
+static struct platform_device *devices[] __initdata = {
+        &vpr200_flash,
+        &vpr200_device_gpiokeys,
+};
+
+/*
+ * Board specific initialization.
+ */
+static void __init vpr200_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads));
+
+        imx35_add_fec(NULL);
+        imx35_add_imx2_wdt(NULL);
+
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+
+        if (0 != gpio_request(GPIO_LCDPWR, "LCDPWR"))
+                printk(KERN_WARNING "vpr200: Couldn't get LCDPWR gpio\n");
+        else
+                gpio_direction_output(GPIO_LCDPWR, 0);
+
+        if (0 != gpio_request(GPIO_PMIC_INT, "PMIC_INT"))
+                printk(KERN_WARNING "vpr200: Couldn't get PMIC_INT gpio\n");
+        else
+                gpio_direction_input(GPIO_PMIC_INT);
+
+        imx35_add_imx_uart0(NULL);
+        imx35_add_imx_uart2(NULL);
+
+        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
+        mxc_register_device(&mx3_fb, &mx3fb_pdata);
+
+        imx35_add_fsl_usb2_udc(&otg_device_pdata);
+        imx35_add_mxc_ehci_hs(&usb_host_pdata);
+
+        imx35_add_mxc_nand(&vpr200_nand_board_info);
+        imx35_add_sdhci_esdhc_imx(0, NULL);
+
+        i2c_register_board_info(0, vpr200_i2c_devices,
+                        ARRAY_SIZE(vpr200_i2c_devices));
+
+        imx35_add_imx_i2c0(&vpr200_i2c0_data);
+}
+
+static void __init vpr200_timer_init(void)
+{
+        mx35_clocks_init();
+}
+
+struct sys_timer vpr200_timer = {
+        .init   = vpr200_timer_init,
+};
+
+MACHINE_START(VPR200, "VPR200")
+        /* Maintainer: Creative Product Design */
+        .map_io = mx35_map_io,
+        .init_early = imx35_init_early,
+        .init_irq = mx35_init_irq,
+        .timer = &vpr200_timer,
+        .init_machine = vpr200_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 47118f760244..54d7174b4202 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -27,14 +27,8 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-v3.h>
-
-/*!
- * @file mm.c
- *
- * @brief This file creates static virtual to physical mappings, common to all MX3 boards.
- *
- * @ingroup Memory
- */
+#include <mach/gpio.h>
+#include <mach/irqs.h>
 
 #ifdef CONFIG_SOC_IMX31
 static struct map_desc mx31_io_desc[] __initdata = {
@@ -52,17 +46,25 @@ static struct map_desc mx31_io_desc[] __initdata = {
  */
 void __init mx31_map_io(void)
 {
+        iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
+}
+
+void __init imx31_init_early(void)
+{
         mxc_set_cpu_type(MXC_CPU_MX31);
         mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
-
-        iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
 }
 
-int imx31_register_gpios(void);
+static struct mxc_gpio_port imx31_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
+};
+
 void __init mx31_init_irq(void)
 {
         mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
-        imx31_register_gpios();
+        mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
 }
 #endif /* ifdef CONFIG_SOC_IMX31 */
 
@@ -77,18 +79,26 @@ static struct map_desc mx35_io_desc[] __initdata = {
 
 void __init mx35_map_io(void)
 {
+        iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
+}
+
+void __init imx35_init_early(void)
+{
         mxc_set_cpu_type(MXC_CPU_MX35);
         mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
-
-        iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
 }
 
-int imx35_register_gpios(void);
+static struct mxc_gpio_port imx35_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
+};
+
 void __init mx35_init_irq(void)
 {
         mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
-        imx35_register_gpios();
+        mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
 }
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
@@ -129,4 +139,3 @@ static int mxc_init_l2x0(void)
 
 arch_initcall(mxc_init_l2x0);
 #endif
-
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 94a0b9e4b7f3..6410b9c48a02 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -15,6 +15,7 @@
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/types.h>
@@ -149,7 +150,10 @@ static int devboard_usbh1_hw_init(struct platform_device *pdev)
         mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
         mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
 
-        return 0;
+        mdelay(10);
+
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_INTERFACE_SINGLE_UNI);
 }
 
 #define USBH1_VBUSEN_B  IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
@@ -187,7 +191,6 @@ static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
 static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
         .init   = devboard_usbh1_hw_init,
         .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
 };
 
 static int __init devboard_usbh1_init(void)
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index f449a97ae1a2..57f7b00cb709 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -265,7 +265,10 @@ static int marxbot_usbh1_hw_init(struct platform_device *pdev)
         mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
         mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
 
-        return 0;
+        mdelay(10);
+
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_INTERFACE_SINGLE_UNI);
 }
 
 #define USBH1_VBUSEN_B  IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
@@ -303,7 +306,6 @@ static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
 static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
         .init   = marxbot_usbh1_hw_init,
         .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
 };
 
 static int __init marxbot_usbh1_init(void)
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
index bbec3c82264a..35f806e737c1 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -123,17 +123,24 @@ static const struct fsl_usb2_platform_data usb_pdata __initconst = {
 
 #if defined(CONFIG_USB_ULPI)
 
+static int smartbot_otg_init(struct platform_device *pdev)
+{
+        return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
+}
+
 static struct mxc_usbh_platform_data otg_host_pdata __initdata = {
+        .init   = smartbot_otg_init,
         .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
 
 static int __init smartbot_otg_host_init(void)
 {
         struct platform_device *pdev;
 
-        otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                        ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+        otg_host_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                ULPI_OTG_DRVVBUS_EXT);
+        if (!otg_host_pdata.otg)
+                return -ENODEV;
 
         pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata);
         if (IS_ERR(pdev))
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index de4fa992fc3e..83ee08847d4d 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -1,5 +1,6 @@
 if ARCH_MX5
-# ARCH_MX51 and ARCH_MX50 are left for compatibility
+# ARCH_MX50/51/53 are left to mark places where prevent multi-soc in single
+# image. So for most time, SOC_IMX50/51/53 should be used.
 
 config ARCH_MX50
         bool
@@ -50,6 +51,7 @@ config MACH_MX51_BABBAGE
 config MACH_MX51_3DS
         bool "Support MX51PDK (3DS)"
         select SOC_IMX51
+        select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_KEYPAD
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
@@ -112,19 +114,32 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD
 
 endchoice
 
-config MACH_MX51_EFIKAMX
-        bool "Support MX51 Genesi Efika MX nettop"
+config MX51_EFIKA_COMMON
+        bool
         select SOC_IMX51
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         select IMX_HAVE_PLATFORM_SPI_IMX
+        select MXC_ULPI if USB_ULPI
+
+config MACH_MX51_EFIKAMX
+        bool "Support MX51 Genesi Efika MX nettop"
+        select MX51_EFIKA_COMMON
         help
           Include support for Genesi Efika MX nettop. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_MX51_EFIKASB
+        bool "Support MX51 Genesi Efika Smartbook"
+        select MX51_EFIKA_COMMON
+        help
+          Include support for Genesi Efika Smartbook. This includes specific
+          configurations for the board and its peripherals.
+
 config MACH_MX53_EVK
         bool "Support MX53 EVK platforms"
         select SOC_IMX53
+        select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
@@ -136,6 +151,8 @@ config MACH_MX53_EVK
 config MACH_MX53_SMD
         bool "Support MX53 SMD platforms"
         select SOC_IMX53
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for MX53 SMD platform. This includes specific
@@ -144,7 +161,10 @@ config MACH_MX53_SMD
 config MACH_MX53_LOCO
         bool "Support MX53 LOCO platforms"
         select SOC_IMX53
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         help
           Include support for MX53 LOCO platform. This includes specific
           configurations for the board and its peripherals.
@@ -157,6 +177,7 @@ config MACH_MX50_RDP
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         select IMX_HAVE_PLATFORM_SPI_IMX
+        select IMX_HAVE_PLATFORM_FEC
         help
           Include support for MX50 reference design platform (RDP) board. This
           includes specific configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 0d43be98e51c..4f63048be3ca 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Object file lists.
-obj-y   := cpu.o mm.o clock-mx51-mx53.o devices.o
+obj-y   := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o
 obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
 
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpu_op-mx51.o
@@ -16,5 +16,7 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
+obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
 obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
+obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o
 obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index f8652ef25f85..d0296a94c475 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -60,7 +60,6 @@
 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
 #define MX51_USB_PLL_DIV_24_MHZ         0x02
 
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
 static struct plat_serial8250_port serial_platform_data[] = {
         {
                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
@@ -105,12 +104,9 @@ static struct platform_device serial_device = {
                 .platform_data = serial_platform_data,
         },
 };
-#endif
 
 static struct platform_device *devices[] __initdata = {
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
         &serial_device,
-#endif
 };
 
 static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
@@ -188,7 +184,10 @@ static int initialize_otg_port(struct platform_device *pdev)
         v |= MX51_USB_PLL_DIV_19_2_MHZ;
         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
         iounmap(usb_base);
-        return 0;
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 }
 
 static int initialize_usbh1_port(struct platform_device *pdev)
@@ -206,13 +205,16 @@ static int initialize_usbh1_port(struct platform_device *pdev)
         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
         iounmap(usb_base);
-        return 0;
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_ITC_NO_THRESHOLD);
 }
 
 static struct mxc_usbh_platform_data dr_utmi_config = {
         .init           = initialize_otg_port,
         .portsc = MXC_EHCI_UTMI_16BIT,
-        .flags  = MXC_EHCI_INTERNAL_PHY,
 };
 
 static struct fsl_usb2_platform_data usb_pdata = {
@@ -223,7 +225,6 @@ static struct fsl_usb2_platform_data usb_pdata = {
 static struct mxc_usbh_platform_data usbh1_config = {
         .init           = initialize_usbh1_port,
         .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
 };
 
 static int otg_mode_host;
@@ -298,7 +299,8 @@ MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
         /* Maintainer: Eric Bénard <eric@eukrea.com> */
         .boot_params = MX51_PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
         .init_irq = mx51_init_irq,
-        .init_machine = eukrea_cpuimx51_init,
         .timer = &mxc_timer,
+        .init_machine = eukrea_cpuimx51_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index ad931895d8b6..29b180823bf5 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -42,6 +42,7 @@
 
 #include "devices-imx51.h"
 #include "devices.h"
+#include "cpu_op-mx51.h"
 
 #define USBH1_RST               IMX_GPIO_NR(2, 28)
 #define ETH_RST                 IMX_GPIO_NR(2, 31)
@@ -109,7 +110,7 @@ static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
 
         /* Touchscreen */
         /* IRQ */
-        _MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
+        _MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
                         PAD_CTL_PKE | PAD_CTL_SRE_FAST |
                         PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 };
@@ -118,15 +119,9 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static int ts_get_pendown_state(void)
-{
-        return gpio_get_value(TSC2007_IRQGPIO) ? 0 : 1;
-}
-
 static struct tsc2007_platform_data tsc2007_info = {
         .model                  = 2007,
         .x_plate_ohms           = 180,
-        .get_pendown_state      = ts_get_pendown_state,
 };
 
 static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
@@ -167,7 +162,10 @@ static int initialize_otg_port(struct platform_device *pdev)
         v |= MX51_USB_PLL_DIV_19_2_MHZ;
         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
         iounmap(usb_base);
-        return 0;
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 }
 
 static int initialize_usbh1_port(struct platform_device *pdev)
@@ -186,13 +184,16 @@ static int initialize_usbh1_port(struct platform_device *pdev)
         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
                         usbother_base + MX51_USB_CTRL_1_OFFSET);
         iounmap(usb_base);
-        return 0;
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_ITC_NO_THRESHOLD);
 }
 
 static struct mxc_usbh_platform_data dr_utmi_config = {
         .init           = initialize_otg_port,
         .portsc = MXC_EHCI_UTMI_16BIT,
-        .flags  = MXC_EHCI_INTERNAL_PHY,
 };
 
 static struct fsl_usb2_platform_data usb_pdata = {
@@ -203,7 +204,6 @@ static struct fsl_usb2_platform_data usb_pdata = {
 static struct mxc_usbh_platform_data usbh1_config = {
         .init           = initialize_usbh1_port,
         .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
 };
 
 static int otg_mode_host;
@@ -242,7 +242,7 @@ static struct mcp251x_platform_data mcp251x_info = {
 static struct spi_board_info cpuimx51sd_spi_device[] = {
         {
                 .modalias        = "mcp2515",
-                .max_speed_hz    = 6500000,
+                .max_speed_hz    = 10000000,
                 .bus_num         = 0,
                 .mode           = SPI_MODE_0,
                 .chip_select     = 0,
@@ -269,6 +269,10 @@ static void __init eukrea_cpuimx51sd_init(void)
         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
                                         ARRAY_SIZE(eukrea_cpuimx51sd_pads));
 
+#if defined(CONFIG_CPU_FREQ_IMX)
+        get_cpu_op = mx51_get_cpu_op;
+#endif
+
         imx51_add_imx_uart(0, &uart_pdata);
         imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
 
@@ -329,7 +333,8 @@ MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
         /* Maintainer: Eric Bénard <eric@eukrea.com> */
         .boot_params = MX51_PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
         .init_irq = mx51_init_irq,
-        .init_machine = eukrea_cpuimx51sd_init,
         .timer = &mxc_timer,
+        .init_machine = eukrea_cpuimx51sd_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
index fd32e4c450e8..dedf7f2d6d0f 100644
--- a/arch/arm/mach-mx5/board-mx50_rdp.c
+++ b/arch/arm/mach-mx5/board-mx50_rdp.c
@@ -35,7 +35,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
-#include "devices-mx50.h"
+#include "devices-imx50.h"
+
+#define FEC_EN          IMX_GPIO_NR(6, 23)
+#define FEC_RESET_B     IMX_GPIO_NR(4, 12)
 
 static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
         /* SD1 */
@@ -102,7 +105,7 @@ static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
         MX50_PAD_I2C3_SCL__USBOTG_OC,
 
         MX50_PAD_SSI_RXC__FEC_MDIO,
-        MX50_PAD_SSI_RXC__FEC_MDIO,
+        MX50_PAD_SSI_RXFS__FEC_MDC,
         MX50_PAD_DISP_D0__FEC_TXCLK,
         MX50_PAD_DISP_D1__FEC_RX_ER,
         MX50_PAD_DISP_D2__FEC_RX_DV,
@@ -111,7 +114,6 @@ static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
         MX50_PAD_DISP_D5__FEC_TX_EN,
         MX50_PAD_DISP_D6__FEC_TXD1,
         MX50_PAD_DISP_D7__FEC_TXD0,
-        MX50_PAD_SSI_RXFS__FEC_MDC,
         MX50_PAD_I2C3_SDA__GPIO_6_23,
         MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
 
@@ -168,6 +170,24 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
+static const struct fec_platform_data fec_data __initconst = {
+        .phy = PHY_INTERFACE_MODE_RMII,
+};
+
+static inline void mx50_rdp_fec_reset(void)
+{
+        gpio_request(FEC_EN, "fec-en");
+        gpio_direction_output(FEC_EN, 0);
+        gpio_request(FEC_RESET_B, "fec-reset_b");
+        gpio_direction_output(FEC_RESET_B, 0);
+        msleep(1);
+        gpio_set_value(FEC_RESET_B, 1);
+}
+
+static const struct imxi2c_platform_data i2c_data __initconst = {
+        .bitrate = 100000,
+};
+
 /*
  * Board specific initialization.
  */
@@ -178,6 +198,11 @@ static void __init mx50_rdp_board_init(void)
 
         imx50_add_imx_uart(0, &uart_pdata);
         imx50_add_imx_uart(1, &uart_pdata);
+        mx50_rdp_fec_reset();
+        imx50_add_fec(&fec_data);
+        imx50_add_imx_i2c(0, &i2c_data);
+        imx50_add_imx_i2c(1, &i2c_data);
+        imx50_add_imx_i2c(2, &i2c_data);
 }
 
 static void __init mx50_rdp_timer_init(void)
@@ -191,7 +216,8 @@ static struct sys_timer mx50_rdp_timer = {
 
 MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
         .map_io = mx50_map_io,
+        .init_early = imx50_init_early,
         .init_irq = mx50_init_irq,
-        .init_machine = mx50_rdp_board_init,
         .timer = &mx50_rdp_timer,
+        .init_machine = mx50_rdp_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index 49d644842379..63dfbeafbc1e 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -71,24 +71,10 @@ static iomux_v3_cfg_t mx51_3ds_pads[] = {
 };
 
 /* Serial ports */
-#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static inline void mxc_init_imx_uart(void)
-{
-        imx51_add_imx_uart(0, &uart_pdata);
-        imx51_add_imx_uart(1, &uart_pdata);
-        imx51_add_imx_uart(2, &uart_pdata);
-}
-#else /* !SERIAL_IMX */
-static inline void mxc_init_imx_uart(void)
-{
-}
-#endif /* SERIAL_IMX */
-
-#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
 static int mx51_3ds_board_keymap[] = {
         KEY(0, 0, KEY_1),
         KEY(0, 1, KEY_2),
@@ -124,16 +110,6 @@ static const struct matrix_keymap_data mx51_3ds_map_data __initconst = {
         .keymap_size    = ARRAY_SIZE(mx51_3ds_board_keymap),
 };
 
-static void mxc_init_keypad(void)
-{
-        imx51_add_imx_keypad(&mx51_3ds_map_data);
-}
-#else
-static inline void mxc_init_keypad(void)
-{
-}
-#endif
-
 static int mx51_3ds_spi2_cs[] = {
         MXC_SPI_CS(0),
         MX51_3DS_ECSPI2_CS,
@@ -157,11 +133,14 @@ static struct spi_board_info mx51_3ds_spi_nor_device[] = {
 /*
  * Board specific initialization.
  */
-static void __init mxc_board_init(void)
+static void __init mx51_3ds_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
                                         ARRAY_SIZE(mx51_3ds_pads));
-        mxc_init_imx_uart();
+
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_imx_uart(1, &uart_pdata);
+        imx51_add_imx_uart(2, &uart_pdata);
 
         imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
         spi_register_board_info(mx51_3ds_spi_nor_device,
@@ -172,7 +151,8 @@ static void __init mxc_board_init(void)
                                     "devices on the board are unusable.\n");
 
         imx51_add_sdhci_esdhc_imx(0, NULL);
-        mxc_init_keypad();
+        imx51_add_imx_keypad(&mx51_3ds_map_data);
+        imx51_add_imx2_wdt(0, NULL);
 }
 
 static void __init mx51_3ds_timer_init(void)
@@ -180,15 +160,16 @@ static void __init mx51_3ds_timer_init(void)
         mx51_clocks_init(32768, 24000000, 22579200, 0);
 }
 
-static struct sys_timer mxc_timer = {
-        .init   = mx51_3ds_timer_init,
+static struct sys_timer mx51_3ds_timer = {
+        .init = mx51_3ds_timer_init,
 };
 
 MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
         /* Maintainer: Freescale Semiconductor, Inc. */
         .boot_params = MX51_PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
         .init_irq = mx51_init_irq,
-        .init_machine = mxc_board_init,
-        .timer = &mxc_timer,
+        .timer = &mx51_3ds_timer,
+        .init_machine = mx51_3ds_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 1d231e84107c..b2ecd194e76d 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -161,23 +161,10 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
 };
 
 /* Serial ports */
-#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static inline void mxc_init_imx_uart(void)
-{
-        imx51_add_imx_uart(0, &uart_pdata);
-        imx51_add_imx_uart(1, &uart_pdata);
-        imx51_add_imx_uart(2, &uart_pdata);
-}
-#else /* !SERIAL_IMX */
-static inline void mxc_init_imx_uart(void)
-{
-}
-#endif /* SERIAL_IMX */
-
 static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
         .bitrate = 100000,
 };
@@ -272,7 +259,10 @@ static int initialize_otg_port(struct platform_device *pdev)
         v |= MX51_USB_PLL_DIV_19_2_MHZ;
         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
         iounmap(usb_base);
-        return 0;
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 }
 
 static int initialize_usbh1_port(struct platform_device *pdev)
@@ -290,13 +280,16 @@ static int initialize_usbh1_port(struct platform_device *pdev)
         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
         iounmap(usb_base);
-        return 0;
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_ITC_NO_THRESHOLD);
 }
 
 static struct mxc_usbh_platform_data dr_utmi_config = {
         .init           = initialize_otg_port,
         .portsc = MXC_EHCI_UTMI_16BIT,
-        .flags  = MXC_EHCI_INTERNAL_PHY,
 };
 
 static struct fsl_usb2_platform_data usb_pdata = {
@@ -307,7 +300,6 @@ static struct fsl_usb2_platform_data usb_pdata = {
 static struct mxc_usbh_platform_data usbh1_config = {
         .init           = initialize_usbh1_port,
         .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
 };
 
 static int otg_mode_host;
@@ -349,7 +341,7 @@ static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
 /*
  * Board specific initialization.
  */
-static void __init mxc_board_init(void)
+static void __init mx51_babbage_init(void)
 {
         iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
         iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
@@ -360,7 +352,11 @@ static void __init mxc_board_init(void)
 #endif
         mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
                                         ARRAY_SIZE(mx51babbage_pads));
-        mxc_init_imx_uart();
+
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_imx_uart(1, &uart_pdata);
+        imx51_add_imx_uart(2, &uart_pdata);
+
         babbage_fec_reset();
         imx51_add_fec(NULL);
 
@@ -399,15 +395,16 @@ static void __init mx51_babbage_timer_init(void)
         mx51_clocks_init(32768, 24000000, 22579200, 0);
 }
 
-static struct sys_timer mxc_timer = {
-        .init   = mx51_babbage_timer_init,
+static struct sys_timer mx51_babbage_timer = {
+        .init = mx51_babbage_timer_init,
 };
 
 MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
         /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
         .boot_params = MX51_PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
         .init_irq = mx51_init_irq,
-        .init_machine = mxc_board_init,
-        .timer = &mxc_timer,
+        .timer = &mx51_babbage_timer,
+        .init_machine = mx51_babbage_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
index b7946f8e8d40..acab1911cb3c 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -25,6 +25,9 @@
 #include <linux/fsl_devices.h>
 #include <linux/spi/flash.h>
 #include <linux/spi/spi.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
@@ -40,8 +43,7 @@
 
 #include "devices-imx51.h"
 #include "devices.h"
-
-#define MX51_USB_PLL_DIV_24_MHZ 0x01
+#include "efika.h"
 
 #define EFIKAMX_PCBID0          IMX_GPIO_NR(3, 16)
 #define EFIKAMX_PCBID1          IMX_GPIO_NR(3, 17)
@@ -53,13 +55,14 @@
 
 #define EFIKAMX_POWER_KEY       IMX_GPIO_NR(2, 31)
 
-#define EFIKAMX_SPI_CS0         IMX_GPIO_NR(4, 24)
-#define EFIKAMX_SPI_CS1         IMX_GPIO_NR(4, 25)
-
 /* board 1.1 doesn't have same reset gpio */
 #define EFIKAMX_RESET1_1        IMX_GPIO_NR(3, 2)
 #define EFIKAMX_RESET           IMX_GPIO_NR(1, 4)
 
+#define EFIKAMX_POWEROFF        IMX_GPIO_NR(4, 13)
+
+#define EFIKAMX_PMIC            IMX_GPIO_NR(1, 6)
+
 /* the pci ids pin have pull up. they're driven low according to board id */
 #define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
 #define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
@@ -67,38 +70,11 @@
 #define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
 
 static iomux_v3_cfg_t mx51efikamx_pads[] = {
-        /* UART1 */
-        MX51_PAD_UART1_RXD__UART1_RXD,
-        MX51_PAD_UART1_TXD__UART1_TXD,
-        MX51_PAD_UART1_RTS__UART1_RTS,
-        MX51_PAD_UART1_CTS__UART1_CTS,
         /* board id */
         MX51_PAD_PCBID0,
         MX51_PAD_PCBID1,
         MX51_PAD_PCBID2,
 
-        /* SD 1 */
-        MX51_PAD_SD1_CMD__SD1_CMD,
-        MX51_PAD_SD1_CLK__SD1_CLK,
-        MX51_PAD_SD1_DATA0__SD1_DATA0,
-        MX51_PAD_SD1_DATA1__SD1_DATA1,
-        MX51_PAD_SD1_DATA2__SD1_DATA2,
-        MX51_PAD_SD1_DATA3__SD1_DATA3,
-
-        /* SD 2 */
-        MX51_PAD_SD2_CMD__SD2_CMD,
-        MX51_PAD_SD2_CLK__SD2_CLK,
-        MX51_PAD_SD2_DATA0__SD2_DATA0,
-        MX51_PAD_SD2_DATA1__SD2_DATA1,
-        MX51_PAD_SD2_DATA2__SD2_DATA2,
-        MX51_PAD_SD2_DATA3__SD2_DATA3,
-
-        /* SD/MMC WP/CD */
-        MX51_PAD_GPIO1_0__SD1_CD,
-        MX51_PAD_GPIO1_1__SD1_WP,
-        MX51_PAD_GPIO1_7__SD2_WP,
-        MX51_PAD_GPIO1_8__SD2_CD,
-
         /* leds */
         MX51_PAD_CSI1_D9__GPIO3_13,
         MX51_PAD_CSI1_VSYNC__GPIO3_14,
@@ -107,64 +83,12 @@ static iomux_v3_cfg_t mx51efikamx_pads[] = {
         /* power key */
         MX51_PAD_PWRKEY,
 
-        /* spi */
-        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
-        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
-        MX51_PAD_CSPI1_SS0__GPIO4_24,
-        MX51_PAD_CSPI1_SS1__GPIO4_25,
-        MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
-        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
-
         /* reset */
         MX51_PAD_DI1_PIN13__GPIO3_2,
         MX51_PAD_GPIO1_4__GPIO1_4,
-};
 
-/* Serial ports */
-#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static const struct imxuart_platform_data uart_pdata = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static inline void mxc_init_imx_uart(void)
-{
-        imx51_add_imx_uart(0, &uart_pdata);
-        imx51_add_imx_uart(1, &uart_pdata);
-        imx51_add_imx_uart(2, &uart_pdata);
-}
-#else /* !SERIAL_IMX */
-static inline void mxc_init_imx_uart(void)
-{
-}
-#endif /* SERIAL_IMX */
-
-/* This function is board specific as the bit mask for the plldiv will also
- * be different for other Freescale SoCs, thus a common bitmask is not
- * possible and cannot get place in /plat-mxc/ehci.c.
- */
-static int initialize_otg_port(struct platform_device *pdev)
-{
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base)
-                return -ENOMEM;
-        usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
-
-        /* Set the PHY clock to 19.2MHz */
-        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
-        v |= MX51_USB_PLL_DIV_24_MHZ;
-        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        iounmap(usb_base);
-        return 0;
-}
-
-static struct mxc_usbh_platform_data dr_utmi_config = {
-        .init   = initialize_otg_port,
-        .portsc = MXC_EHCI_UTMI_16BIT,
-        .flags  = MXC_EHCI_INTERNAL_PHY,
+        /* power off */
+        MX51_PAD_CSI2_VSYNC__GPIO4_13,
 };
 
 /*   PCBID2  PCBID1 PCBID0  STATE
@@ -265,47 +189,6 @@ static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initcon
         .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
 };
 
-static struct mtd_partition mx51_efikamx_spi_nor_partitions[] = {
-        {
-         .name = "u-boot",
-         .offset = 0,
-         .size = SZ_256K,
-        },
-        {
-          .name = "config",
-          .offset = MTDPART_OFS_APPEND,
-          .size = SZ_64K,
-        },
-};
-
-static struct flash_platform_data mx51_efikamx_spi_flash_data = {
-        .name           = "spi_flash",
-        .parts          = mx51_efikamx_spi_nor_partitions,
-        .nr_parts       = ARRAY_SIZE(mx51_efikamx_spi_nor_partitions),
-        .type           = "sst25vf032b",
-};
-
-static struct spi_board_info mx51_efikamx_spi_board_info[] __initdata = {
-        {
-                .modalias = "m25p80",
-                .max_speed_hz = 25000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .platform_data = &mx51_efikamx_spi_flash_data,
-                .irq = -1,
-        },
-};
-
-static int mx51_efikamx_spi_cs[] = {
-        EFIKAMX_SPI_CS0,
-        EFIKAMX_SPI_CS1,
-};
-
-static const struct spi_imx_master mx51_efikamx_spi_pdata __initconst = {
-        .chipselect     = mx51_efikamx_spi_cs,
-        .num_chipselect = ARRAY_SIZE(mx51_efikamx_spi_cs),
-};
-
 void mx51_efikamx_reset(void)
 {
         if (system_rev == 0x11)
@@ -314,14 +197,53 @@ void mx51_efikamx_reset(void)
                 gpio_direction_output(EFIKAMX_RESET, 0);
 }
 
-static void __init mxc_board_init(void)
+static struct regulator *pwgt1, *pwgt2, *coincell;
+
+static void mx51_efikamx_power_off(void)
+{
+        if (!IS_ERR(coincell))
+                regulator_disable(coincell);
+
+        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
+                regulator_disable(pwgt2);
+                regulator_disable(pwgt1);
+        }
+        gpio_direction_output(EFIKAMX_POWEROFF, 1);
+}
+
+static int __init mx51_efikamx_power_init(void)
+{
+        if (machine_is_mx51_efikamx()) {
+                pwgt1 = regulator_get(NULL, "pwgt1");
+                pwgt2 = regulator_get(NULL, "pwgt2");
+                if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
+                        regulator_enable(pwgt1);
+                        regulator_enable(pwgt2);
+                }
+                gpio_request(EFIKAMX_POWEROFF, "poweroff");
+                pm_power_off = mx51_efikamx_power_off;
+
+                /* enable coincell charger. maybe need a small power driver ? */
+                coincell = regulator_get(NULL, "coincell");
+                if (!IS_ERR(coincell)) {
+                        regulator_set_voltage(coincell, 3000000, 3000000);
+                        regulator_enable(coincell);
+                }
+
+                regulator_has_full_constraints();
+        }
+
+        return 0;
+}
+late_initcall(mx51_efikamx_power_init);
+
+static void __init mx51_efikamx_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
                                         ARRAY_SIZE(mx51efikamx_pads));
+        efika_board_common_init();
+
         mx51_efikamx_board_id();
-        mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
-        mxc_init_imx_uart();
-        imx51_add_sdhci_esdhc_imx(0, NULL);
 
         /* on < 1.2 boards both SD controllers are used */
         if (system_rev < 0x12) {
@@ -332,10 +254,6 @@ static void __init mxc_board_init(void)
         platform_device_register(&mx51_efikamx_leds_device);
         imx51_add_gpio_keys(&mx51_efikamx_powerkey_data);
 
-        spi_register_board_info(mx51_efikamx_spi_board_info,
-                ARRAY_SIZE(mx51_efikamx_spi_board_info));
-        imx51_add_ecspi(0, &mx51_efikamx_spi_pdata);
-
         if (system_rev == 0x11) {
                 gpio_request(EFIKAMX_RESET1_1, "reset");
                 gpio_direction_output(EFIKAMX_RESET1_1, 1);
@@ -343,6 +261,20 @@ static void __init mxc_board_init(void)
                 gpio_request(EFIKAMX_RESET, "reset");
                 gpio_direction_output(EFIKAMX_RESET, 1);
         }
+
+        /*
+         * enable wifi by default only on mx
+         * sb and mx have same wlan pin but the value to enable it are
+         * different :/
+         */
+        gpio_request(EFIKA_WLAN_EN, "wlan_en");
+        gpio_direction_output(EFIKA_WLAN_EN, 0);
+        msleep(10);
+
+        gpio_request(EFIKA_WLAN_RESET, "wlan_rst");
+        gpio_direction_output(EFIKA_WLAN_RESET, 0);
+        msleep(10);
+        gpio_set_value(EFIKA_WLAN_RESET, 1);
 }
 
 static void __init mx51_efikamx_timer_init(void)
@@ -350,15 +282,16 @@ static void __init mx51_efikamx_timer_init(void)
         mx51_clocks_init(32768, 24000000, 22579200, 24576000);
 }
 
-static struct sys_timer mxc_timer = {
-        .init   = mx51_efikamx_timer_init,
+static struct sys_timer mx51_efikamx_timer = {
+        .init = mx51_efikamx_timer_init,
 };
 
 MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
         /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
         .boot_params = MX51_PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
         .init_irq = mx51_init_irq,
-        .init_machine =  mxc_board_init,
-        .timer = &mxc_timer,
+        .timer = &mx51_efikamx_timer,
+        .init_machine = mx51_efikamx_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
new file mode 100644
index 000000000000..db04ce8462dc
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
@@ -0,0 +1,283 @@
+/*
+ * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org>
+ *
+ * based on code from the following
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
+ * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/input.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/fsl_devices.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <mach/ulpi.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+#include <mach/i2c.h>
+#include <mach/mxc_ehci.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-imx51.h"
+#include "devices.h"
+#include "efika.h"
+
+#define EFIKASB_USBH2_STP       IMX_GPIO_NR(2, 20)
+#define EFIKASB_GREEN_LED       IMX_GPIO_NR(1, 3)
+#define EFIKASB_WHITE_LED       IMX_GPIO_NR(2, 25)
+#define EFIKASB_PCBID0          IMX_GPIO_NR(2, 28)
+#define EFIKASB_PCBID1          IMX_GPIO_NR(2, 29)
+#define EFIKASB_PWRKEY          IMX_GPIO_NR(2, 31)
+#define EFIKASB_LID             IMX_GPIO_NR(3, 14)
+#define EFIKASB_POWEROFF        IMX_GPIO_NR(4, 13)
+#define EFIKASB_RFKILL          IMX_GPIO_NR(3, 1)
+
+#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
+
+static iomux_v3_cfg_t mx51efikasb_pads[] = {
+        /* USB HOST2 */
+        MX51_PAD_EIM_D16__USBH2_DATA0,
+        MX51_PAD_EIM_D17__USBH2_DATA1,
+        MX51_PAD_EIM_D18__USBH2_DATA2,
+        MX51_PAD_EIM_D19__USBH2_DATA3,
+        MX51_PAD_EIM_D20__USBH2_DATA4,
+        MX51_PAD_EIM_D21__USBH2_DATA5,
+        MX51_PAD_EIM_D22__USBH2_DATA6,
+        MX51_PAD_EIM_D23__USBH2_DATA7,
+        MX51_PAD_EIM_A24__USBH2_CLK,
+        MX51_PAD_EIM_A25__USBH2_DIR,
+        MX51_PAD_EIM_A26__USBH2_STP,
+        MX51_PAD_EIM_A27__USBH2_NXT,
+
+        /* leds */
+        MX51_PAD_EIM_CS0__GPIO2_25,
+        MX51_PAD_GPIO1_3__GPIO1_3,
+
+        /* pcb id */
+        MX51_PAD_EIM_CS3__GPIO2_28,
+        MX51_PAD_EIM_CS4__GPIO2_29,
+
+        /* lid */
+        MX51_PAD_CSI1_VSYNC__GPIO3_14,
+
+        /* power key*/
+        MX51_PAD_PWRKEY,
+
+        /* wifi/bt button */
+        MX51_PAD_DI1_PIN12__GPIO3_1,
+
+        /* power off */
+        MX51_PAD_CSI2_VSYNC__GPIO4_13,
+
+        /* wdog reset */
+        MX51_PAD_GPIO1_4__WDOG1_WDOG_B,
+
+        /* BT */
+        MX51_PAD_EIM_A17__GPIO2_11,
+};
+
+static int initialize_usbh2_port(struct platform_device *pdev)
+{
+        iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
+        iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
+
+        mxc_iomux_v3_setup_pad(usbh2gpio);
+        gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
+        gpio_direction_output(EFIKASB_USBH2_STP, 0);
+        msleep(1);
+        gpio_set_value(EFIKASB_USBH2_STP, 1);
+        msleep(1);
+
+        gpio_free(EFIKASB_USBH2_STP);
+        mxc_iomux_v3_setup_pad(usbh2stp);
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
+}
+
+static struct mxc_usbh_platform_data usbh2_config = {
+        .init   = initialize_usbh2_port,
+        .portsc = MXC_EHCI_MODE_ULPI,
+};
+
+static void __init mx51_efikasb_usb(void)
+{
+        usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                        ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
+        if (usbh2_config.otg)
+                mxc_register_device(&mxc_usbh2_device, &usbh2_config);
+}
+
+static struct gpio_led mx51_efikasb_leds[] = {
+        {
+                .name = "efikasb:green",
+                .default_trigger = "default-on",
+                .gpio = EFIKASB_GREEN_LED,
+                .active_low = 1,
+        },
+        {
+                .name = "efikasb:white",
+                .default_trigger = "caps",
+                .gpio = EFIKASB_WHITE_LED,
+        },
+};
+
+static struct gpio_led_platform_data mx51_efikasb_leds_data = {
+        .leds = mx51_efikasb_leds,
+        .num_leds = ARRAY_SIZE(mx51_efikasb_leds),
+};
+
+static struct platform_device mx51_efikasb_leds_device = {
+        .name = "leds-gpio",
+        .id = -1,
+        .dev = {
+                .platform_data = &mx51_efikasb_leds_data,
+        },
+};
+
+static struct gpio_keys_button mx51_efikasb_keys[] = {
+        {
+                .code = KEY_POWER,
+                .gpio = EFIKASB_PWRKEY,
+                .type = EV_PWR,
+                .desc = "Power Button",
+                .wakeup = 1,
+                .debounce_interval = 10, /* ms */
+        },
+        {
+                .code = SW_LID,
+                .gpio = EFIKASB_LID,
+                .type = EV_SW,
+                .desc = "Lid Switch",
+        },
+        {
+                /* SW_RFKILLALL vs KEY_RFKILL ? */
+                .code = SW_RFKILL_ALL,
+                .gpio = EFIKASB_RFKILL,
+                .type = EV_SW,
+                .desc = "rfkill",
+        },
+};
+
+static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = {
+        .buttons = mx51_efikasb_keys,
+        .nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
+};
+
+static struct regulator *pwgt1, *pwgt2;
+
+static void mx51_efikasb_power_off(void)
+{
+        gpio_set_value(EFIKA_USB_PHY_RESET, 0);
+
+        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
+                regulator_disable(pwgt2);
+                regulator_disable(pwgt1);
+        }
+        gpio_direction_output(EFIKASB_POWEROFF, 1);
+}
+
+static int __init mx51_efikasb_power_init(void)
+{
+        if (machine_is_mx51_efikasb()) {
+                pwgt1 = regulator_get(NULL, "pwgt1");
+                pwgt2 = regulator_get(NULL, "pwgt2");
+                if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
+                        regulator_enable(pwgt1);
+                        regulator_enable(pwgt2);
+                }
+                gpio_request(EFIKASB_POWEROFF, "poweroff");
+                pm_power_off = mx51_efikasb_power_off;
+
+                regulator_has_full_constraints();
+        }
+
+        return 0;
+}
+late_initcall(mx51_efikasb_power_init);
+
+/* 01     R1.3 board
+   10     R2.0 board */
+static void __init mx51_efikasb_board_id(void)
+{
+        int id;
+
+        gpio_request(EFIKASB_PCBID0, "pcb id0");
+        gpio_direction_input(EFIKASB_PCBID0);
+        gpio_request(EFIKASB_PCBID1, "pcb id1");
+        gpio_direction_input(EFIKASB_PCBID1);
+
+        id = gpio_get_value(EFIKASB_PCBID0);
+        id |= gpio_get_value(EFIKASB_PCBID1) << 1;
+
+        switch (id) {
+        default:
+                break;
+        case 1:
+                system_rev = 0x13;
+                break;
+        case 2:
+                system_rev = 0x20;
+                break;
+        }
+}
+
+static void __init efikasb_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
+                                        ARRAY_SIZE(mx51efikasb_pads));
+        efika_board_common_init();
+
+        mx51_efikasb_board_id();
+        mx51_efikasb_usb();
+        imx51_add_sdhci_esdhc_imx(1, NULL);
+
+        platform_device_register(&mx51_efikasb_leds_device);
+        imx51_add_gpio_keys(&mx51_efikasb_keys_data);
+
+}
+
+static void __init mx51_efikasb_timer_init(void)
+{
+        mx51_clocks_init(32768, 24000000, 22579200, 24576000);
+}
+
+static struct sys_timer mx51_efikasb_timer = {
+        .init   = mx51_efikasb_timer_init,
+};
+
+MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
+        .boot_params = MX51_PHYS_OFFSET + 0x100,
+        .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
+        .init_irq = mx51_init_irq,
+        .init_machine =  efikasb_board_init,
+        .timer = &mx51_efikasb_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index caee04c08238..7b5735c5ea59 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
  */
 
@@ -42,28 +42,24 @@
 #include "devices-imx53.h"
 
 static iomux_v3_cfg_t mx53_evk_pads[] = {
-        MX53_PAD_CSI0_D10__UART1_TXD,
-        MX53_PAD_CSI0_D11__UART1_RXD,
-        MX53_PAD_ATA_DIOW__UART1_TXD,
-        MX53_PAD_ATA_DMACK__UART1_RXD,
+        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
+        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
 
-        MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
-        MX53_PAD_ATA_DMARQ__UART2_TXD,
-        MX53_PAD_ATA_DIOR__UART2_RTS,
-        MX53_PAD_ATA_INTRQ__UART2_CTS,
+        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
+        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
+        MX53_PAD_PATA_DIOR__UART2_RTS,
+        MX53_PAD_PATA_INTRQ__UART2_CTS,
 
-        MX53_PAD_ATA_CS_0__UART3_TXD,
-        MX53_PAD_ATA_CS_1__UART3_RXD,
-        MX53_PAD_ATA_DA_1__UART3_CTS,
-        MX53_PAD_ATA_DA_2__UART3_RTS,
+        MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
+        MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
 
-        MX53_PAD_EIM_D16__CSPI1_SCLK,
-        MX53_PAD_EIM_D17__CSPI1_MISO,
-        MX53_PAD_EIM_D18__CSPI1_MOSI,
+        MX53_PAD_EIM_D16__ECSPI1_SCLK,
+        MX53_PAD_EIM_D17__ECSPI1_MISO,
+        MX53_PAD_EIM_D18__ECSPI1_MOSI,
 
         /* ecspi chip select lines */
-        MX53_PAD_EIM_EB2__GPIO_2_30,
-        MX53_PAD_EIM_D19__GPIO_3_19,
+        MX53_PAD_EIM_EB2__GPIO2_30,
+        MX53_PAD_EIM_D19__GPIO3_19,
 };
 
 static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
@@ -72,9 +68,9 @@ static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
 
 static inline void mx53_evk_init_uart(void)
 {
-        imx53_add_imx_uart(0, &mx53_evk_uart_pdata);
+        imx53_add_imx_uart(0, NULL);
         imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
-        imx53_add_imx_uart(2, &mx53_evk_uart_pdata);
+        imx53_add_imx_uart(2, NULL);
 }
 
 static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
@@ -139,6 +135,7 @@ static void __init mx53_evk_board_init(void)
         spi_register_board_info(mx53_evk_spi_board_info,
                 ARRAY_SIZE(mx53_evk_spi_board_info));
         imx53_add_ecspi(0, &mx53_evk_spi_data);
+        imx53_add_imx2_wdt(0, NULL);
 }
 
 static void __init mx53_evk_timer_init(void)
@@ -152,7 +149,8 @@ static struct sys_timer mx53_evk_timer = {
 
 MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
         .map_io = mx53_map_io,
+        .init_early = imx53_init_early,
         .init_irq = mx53_init_irq,
-        .init_machine = mx53_evk_board_init,
         .timer = &mx53_evk_timer,
+        .init_machine = mx53_evk_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index d1348e04ace3..0a18f8d23eb0 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -39,33 +39,147 @@
 #define LOCO_FEC_PHY_RST                IMX_GPIO_NR(7, 6)
 
 static iomux_v3_cfg_t mx53_loco_pads[] = {
-        MX53_PAD_CSI0_D10__UART1_TXD,
-        MX53_PAD_CSI0_D11__UART1_RXD,
-        MX53_PAD_ATA_DIOW__UART1_TXD,
-        MX53_PAD_ATA_DMACK__UART1_RXD,
-
-        MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
-        MX53_PAD_ATA_DMARQ__UART2_TXD,
-        MX53_PAD_ATA_DIOR__UART2_RTS,
-        MX53_PAD_ATA_INTRQ__UART2_CTS,
-
-        MX53_PAD_ATA_CS_0__UART3_TXD,
-        MX53_PAD_ATA_CS_1__UART3_RXD,
-        MX53_PAD_ATA_DA_1__UART3_CTS,
-        MX53_PAD_ATA_DA_2__UART3_RTS,
+        /* FEC */
+        MX53_PAD_FEC_MDC__FEC_MDC,
+        MX53_PAD_FEC_MDIO__FEC_MDIO,
+        MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+        MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+        MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+        MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+        MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+        MX53_PAD_FEC_TX_EN__FEC_TX_EN,
+        MX53_PAD_FEC_TXD1__FEC_TDATA_1,
+        MX53_PAD_FEC_TXD0__FEC_TDATA_0,
+        /* FEC_nRST */
+        MX53_PAD_PATA_DA_0__GPIO7_6,
+        /* FEC_nINT */
+        MX53_PAD_PATA_DATA4__GPIO2_4,
+        /* AUDMUX5 */
+        MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
+        MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
+        MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
+        MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
+        /* I2C2 */
+        MX53_PAD_KEY_COL3__I2C2_SCL,
+        MX53_PAD_KEY_ROW3__I2C2_SDA,
+        /* SD1 */
+        MX53_PAD_SD1_CMD__ESDHC1_CMD,
+        MX53_PAD_SD1_CLK__ESDHC1_CLK,
+        MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
+        MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
+        MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
+        MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
+        /* SD3 */
+        MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
+        MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
+        MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
+        MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
+        MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
+        MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
+        MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
+        MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
+        MX53_PAD_PATA_IORDY__ESDHC3_CLK,
+        MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+        /* SD3_CD */
+        MX53_PAD_EIM_DA11__GPIO3_11,
+        /* SD3_WP */
+        MX53_PAD_EIM_DA12__GPIO3_12,
+        /* VGA */
+        MX53_PAD_EIM_OE__IPU_DI1_PIN7,
+        MX53_PAD_EIM_RW__IPU_DI1_PIN8,
+        /* DISPLB */
+        MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
+        MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
+        MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
+        MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
+        /* DISP0_POWER_EN */
+        MX53_PAD_EIM_D24__GPIO3_24,
+        /* DISP0 DET INT */
+        MX53_PAD_EIM_D31__GPIO3_31,
+        /* LVDS */
+        MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
+        MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
+        MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
+        MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
+        MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
+        MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
+        MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
+        MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
+        MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
+        MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
+        /* I2C1 */
+        MX53_PAD_CSI0_DAT8__I2C1_SDA,
+        MX53_PAD_CSI0_DAT9__I2C1_SCL,
+        /* UART1 */
+        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
+        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
+        /* CSI0 */
+        MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
+        MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
+        MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
+        MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
+        MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
+        MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
+        MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
+        MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
+        MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
+        MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
+        MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
+        /* DISPLAY */
+        MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
+        MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
+        MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
+        MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
+        MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
+        MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
+        MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
+        MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
+        MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
+        MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
+        MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
+        MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
+        MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
+        MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
+        MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
+        MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
+        MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
+        MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
+        MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
+        MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
+        MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
+        MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
+        MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
+        MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
+        MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
+        MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
+        MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
+        MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
+        /* Audio CLK*/
+        MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
+        /* PWM */
+        MX53_PAD_GPIO_1__PWM2_PWMO,
+        /* SPDIF */
+        MX53_PAD_GPIO_7__SPDIF_PLOCK,
+        MX53_PAD_GPIO_17__SPDIF_OUT1,
+        /* GPIO */
+        MX53_PAD_PATA_DA_1__GPIO7_7,
+        MX53_PAD_PATA_DA_2__GPIO7_8,
+        MX53_PAD_PATA_DATA5__GPIO2_5,
+        MX53_PAD_PATA_DATA6__GPIO2_6,
+        MX53_PAD_PATA_DATA14__GPIO2_14,
+        MX53_PAD_PATA_DATA15__GPIO2_15,
+        MX53_PAD_PATA_INTRQ__GPIO7_2,
+        MX53_PAD_EIM_WAIT__GPIO5_0,
+        MX53_PAD_NANDF_WP_B__GPIO6_9,
+        MX53_PAD_NANDF_RB0__GPIO6_10,
+        MX53_PAD_NANDF_CS1__GPIO6_14,
+        MX53_PAD_NANDF_CS2__GPIO6_15,
+        MX53_PAD_NANDF_CS3__GPIO6_16,
+        MX53_PAD_GPIO_5__GPIO1_5,
+        MX53_PAD_GPIO_16__GPIO7_11,
+        MX53_PAD_GPIO_8__GPIO1_8,
 };
 
-static const struct imxuart_platform_data mx53_loco_uart_data __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static inline void mx53_loco_init_uart(void)
-{
-        imx53_add_imx_uart(0, &mx53_loco_uart_data);
-        imx53_add_imx_uart(1, &mx53_loco_uart_data);
-        imx53_add_imx_uart(2, &mx53_loco_uart_data);
-}
-
 static inline void mx53_loco_fec_reset(void)
 {
         int ret;
@@ -85,13 +199,22 @@ static struct fec_platform_data mx53_loco_fec_data = {
         .phy = PHY_INTERFACE_MODE_RMII,
 };
 
+static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
+        .bitrate = 100000,
+};
+
 static void __init mx53_loco_board_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
                                         ARRAY_SIZE(mx53_loco_pads));
-        mx53_loco_init_uart();
+        imx53_add_imx_uart(0, NULL);
         mx53_loco_fec_reset();
         imx53_add_fec(&mx53_loco_fec_data);
+        imx53_add_imx2_wdt(0, NULL);
+        imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
+        imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
+        imx53_add_sdhci_esdhc_imx(0, NULL);
+        imx53_add_sdhci_esdhc_imx(2, NULL);
 }
 
 static void __init mx53_loco_timer_init(void)
@@ -105,7 +228,8 @@ static struct sys_timer mx53_loco_timer = {
 
 MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
         .map_io = mx53_map_io,
+        .init_early = imx53_init_early,
         .init_irq = mx53_init_irq,
-        .init_machine = mx53_loco_board_init,
         .timer = &mx53_loco_timer,
+        .init_machine = mx53_loco_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
index 7970f7a48588..31e173267edf 100644
--- a/arch/arm/mach-mx5/board-mx53_smd.c
+++ b/arch/arm/mach-mx5/board-mx53_smd.c
@@ -39,20 +39,19 @@
 #define SMD_FEC_PHY_RST         IMX_GPIO_NR(7, 6)
 
 static iomux_v3_cfg_t mx53_smd_pads[] = {
-        MX53_PAD_CSI0_D10__UART1_TXD,
-        MX53_PAD_CSI0_D11__UART1_RXD,
-        MX53_PAD_ATA_DIOW__UART1_TXD,
-        MX53_PAD_ATA_DMACK__UART1_RXD,
-
-        MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
-        MX53_PAD_ATA_DMARQ__UART2_TXD,
-        MX53_PAD_ATA_DIOR__UART2_RTS,
-        MX53_PAD_ATA_INTRQ__UART2_CTS,
-
-        MX53_PAD_ATA_CS_0__UART3_TXD,
-        MX53_PAD_ATA_CS_1__UART3_RXD,
-        MX53_PAD_ATA_DA_1__UART3_CTS,
-        MX53_PAD_ATA_DA_2__UART3_RTS,
+        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
+        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
+
+        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
+        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
+
+        MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
+        MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
+        MX53_PAD_PATA_DA_1__UART3_CTS,
+        MX53_PAD_PATA_DA_2__UART3_RTS,
+        /* I2C1 */
+        MX53_PAD_CSI0_DAT8__I2C1_SDA,
+        MX53_PAD_CSI0_DAT9__I2C1_SCL,
 };
 
 static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
@@ -61,8 +60,8 @@ static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
 
 static inline void mx53_smd_init_uart(void)
 {
-        imx53_add_imx_uart(0, &mx53_smd_uart_data);
-        imx53_add_imx_uart(1, &mx53_smd_uart_data);
+        imx53_add_imx_uart(0, NULL);
+        imx53_add_imx_uart(1, NULL);
         imx53_add_imx_uart(2, &mx53_smd_uart_data);
 }
 
@@ -85,6 +84,10 @@ static struct fec_platform_data mx53_smd_fec_data = {
         .phy = PHY_INTERFACE_MODE_RMII,
 };
 
+static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
+        .bitrate = 100000,
+};
+
 static void __init mx53_smd_board_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
@@ -92,6 +95,8 @@ static void __init mx53_smd_board_init(void)
         mx53_smd_init_uart();
         mx53_smd_fec_reset();
         imx53_add_fec(&mx53_smd_fec_data);
+        imx53_add_imx2_wdt(0, NULL);
+        imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
 }
 
 static void __init mx53_smd_timer_init(void)
@@ -105,7 +110,8 @@ static struct sys_timer mx53_smd_timer = {
 
 MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
         .map_io = mx53_map_io,
+        .init_early = imx53_init_early,
         .init_irq = mx53_init_irq,
-        .init_machine = mx53_smd_board_init,
         .timer = &mx53_smd_timer,
+        .init_machine = mx53_smd_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 0a19e7567c0b..652ace413825 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -42,6 +42,9 @@ static struct clk usboh3_clk;
 static struct clk emi_fast_clk;
 static struct clk ipu_clk;
 static struct clk mipi_hsc1_clk;
+static struct clk esdhc1_clk;
+static struct clk esdhc2_clk;
+static struct clk esdhc3_mx53_clk;
 
 #define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
 
@@ -867,10 +870,6 @@ static struct clk gpt_32k_clk = {
         .parent = &ckil_clk,
 };
 
-static struct clk kpp_clk = {
-        .id = 0,
-};
-
 static struct clk dummy_clk = {
         .id = 0,
 };
@@ -1147,10 +1146,80 @@ CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
 CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
 CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
 
+/* mx51 specific */
 CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
 CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
 CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
 
+static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CSCMR1);
+        if (parent == &esdhc1_clk)
+                reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
+        else if (parent == &esdhc2_clk)
+                reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
+        else
+                return -EINVAL;
+        __raw_writel(reg, MXC_CCM_CSCMR1);
+
+        return 0;
+}
+
+static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CSCMR1);
+        if (parent == &esdhc1_clk)
+                reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+        else if (parent == &esdhc2_clk)
+                reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+        else
+                return -EINVAL;
+        __raw_writel(reg, MXC_CCM_CSCMR1);
+
+        return 0;
+}
+
+/* mx53 specific */
+static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CSCMR1);
+        if (parent == &esdhc1_clk)
+                reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
+        else if (parent == &esdhc3_mx53_clk)
+                reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
+        else
+                return -EINVAL;
+        __raw_writel(reg, MXC_CCM_CSCMR1);
+
+        return 0;
+}
+
+CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
+CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
+CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
+
+static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CSCMR1);
+        if (parent == &esdhc1_clk)
+                reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+        else if (parent == &esdhc3_mx53_clk)
+                reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+        else
+                return -EINVAL;
+        __raw_writel(reg, MXC_CCM_CSCMR1);
+
+        return 0;
+}
+
 #define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s)          \
         static struct clk name = {                                      \
                 .id             = i,                                    \
@@ -1255,9 +1324,62 @@ DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
         clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
 DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
         NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
+        NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
+        NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+
+/* mx51 specific */
 DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
         clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
 
+static struct clk esdhc3_clk = {
+        .id = 2,
+        .parent = &esdhc1_clk,
+        .set_parent = clk_esdhc3_set_parent,
+        .enable_reg = MXC_CCM_CCGR3,
+        .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+        .enable  = _clk_max_enable,
+        .disable = _clk_max_disable,
+        .secondary = &esdhc3_ipg_clk,
+};
+static struct clk esdhc4_clk = {
+        .id = 3,
+        .parent = &esdhc1_clk,
+        .set_parent = clk_esdhc4_set_parent,
+        .enable_reg = MXC_CCM_CCGR3,
+        .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+        .enable  = _clk_max_enable,
+        .disable = _clk_max_disable,
+        .secondary = &esdhc4_ipg_clk,
+};
+
+/* mx53 specific */
+static struct clk esdhc2_mx53_clk = {
+        .id = 2,
+        .parent = &esdhc1_clk,
+        .set_parent = clk_esdhc2_mx53_set_parent,
+        .enable_reg = MXC_CCM_CCGR3,
+        .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+        .enable  = _clk_max_enable,
+        .disable = _clk_max_disable,
+        .secondary = &esdhc3_ipg_clk,
+};
+
+DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
+        clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
+
+static struct clk esdhc4_mx53_clk = {
+        .id = 3,
+        .parent = &esdhc1_clk,
+        .set_parent = clk_esdhc4_mx53_set_parent,
+        .enable_reg = MXC_CCM_CCGR3,
+        .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+        .enable  = _clk_max_enable,
+        .disable = _clk_max_disable,
+        .secondary = &esdhc4_ipg_clk,
+};
+
 DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
 DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
 DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
@@ -1302,7 +1424,7 @@ static struct clk_lookup mx51_lookups[] = {
         _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
-        _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
+        _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
         _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
@@ -1316,6 +1438,8 @@ static struct clk_lookup mx51_lookups[] = {
         _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_clk)
         _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
@@ -1336,10 +1460,14 @@ static struct clk_lookup mx53_lookups[] = {
         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
-        _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_mx53_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_mx53_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_mx53_clk)
         _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk)
         _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk)
         _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
+        _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
+        _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
 };
 
 static void clk_tree_init(void)
@@ -1427,6 +1555,14 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
         mx53_revision();
         clk_disable(&iim_clk);
 
+        /* Set SDHC parents to be PLL2 */
+        clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
+        clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
+
+        /* set SDHC root clock as 200MHZ*/
+        clk_set_rate(&esdhc1_clk, 200000000);
+        clk_set_rate(&esdhc3_mx53_clk, 200000000);
+
         /* System timer */
         mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
                 MX53_INT_GPT);
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index d40671da4372..df46b5e60857 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -78,11 +78,16 @@ static int get_mx53_srev(void)
         void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
         u32 rev = readl(iim_base + IIM_SREV) & 0xff;
 
-        if (rev == 0x0)
+        switch (rev) {
+        case 0x0:
                 return IMX_CHIP_REVISION_1_0;
-        else if (rev == 0x10)
+        case 0x2:
                 return IMX_CHIP_REVISION_2_0;
-        return 0;
+        case 0x3:
+                return IMX_CHIP_REVISION_2_1;
+        default:
+                return IMX_CHIP_REVISION_UNKNOWN;
+        }
 }
 
 /*
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index b462c22f53d8..87c0c58f27a7 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -217,9 +217,12 @@
 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET      (20)
 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK        (0x3 << 20)
 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL                   (0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL        (0x1 << 19)
 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL                   (0x1 << 18)
 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET      (16)
 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK        (0x3 << 16)
+#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET       (16)
+#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK         (0x3 << 16)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET              (14)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK                (0x3 << 14)
 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET              (12)
@@ -271,6 +274,10 @@
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK       (0x7 << 22)
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET     (19)
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK       (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET      (22)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK        (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET      (19)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK        (0x7 << 19)
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET     (16)
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK       (0x7 << 16)
 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET              (14)
diff --git a/arch/arm/mach-mx5/devices-mx50.h b/arch/arm/mach-mx5/devices-imx50.h
index 98ab07468a0e..c9e42823c7e3 100644
--- a/arch/arm/mach-mx5/devices-mx50.h
+++ b/arch/arm/mach-mx5/devices-imx50.h
@@ -24,3 +24,11 @@
 extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst;
 #define imx50_add_imx_uart(id, pdata)   \
         imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
+
+extern const struct imx_fec_data imx50_fec_data __initconst;
+#define imx50_add_fec(pdata)    \
+        imx_add_fec(&imx50_fec_data, pdata)
+
+extern const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst;
+#define imx50_add_imx_i2c(id, pdata)    \
+        imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index 8639735a117b..9251008dad1f 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -29,3 +29,7 @@ imx53_sdhci_esdhc_imx_data[] __initconst;
 extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst;
 #define imx53_add_ecspi(id, pdata)      \
         imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
+
+extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst;
+#define imx53_add_imx2_wdt(id, pdata)   \
+        imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
diff --git a/arch/arm/mach-mx5/efika.h b/arch/arm/mach-mx5/efika.h
new file mode 100644
index 000000000000..014aa985faae
--- /dev/null
+++ b/arch/arm/mach-mx5/efika.h
@@ -0,0 +1,10 @@
+#ifndef _EFIKA_H
+#define _EFIKA_H
+
+#define EFIKA_WLAN_EN           IMX_GPIO_NR(2, 16)
+#define EFIKA_WLAN_RESET        IMX_GPIO_NR(2, 10)
+#define EFIKA_USB_PHY_RESET     IMX_GPIO_NR(2, 9)
+
+void __init efika_board_common_init(void);
+
+#endif
diff --git a/arch/arm/mach-mx5/ehci.c b/arch/arm/mach-mx5/ehci.c
new file mode 100644
index 000000000000..7ce12c804a32
--- /dev/null
+++ b/arch/arm/mach-mx5/ehci.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
+
+#define MXC_OTG_OFFSET                  0
+#define MXC_H1_OFFSET                   0x200
+#define MXC_H2_OFFSET                   0x400
+
+/* USB_CTRL */
+#define MXC_OTG_UCTRL_OWIE_BIT          (1 << 27)       /* OTG wakeup intr enable */
+#define MXC_OTG_UCTRL_OPM_BIT           (1 << 24)       /* OTG power mask */
+#define MXC_H1_UCTRL_H1UIE_BIT          (1 << 12)       /* Host1 ULPI interrupt enable */
+#define MXC_H1_UCTRL_H1WIE_BIT          (1 << 11)       /* HOST1 wakeup intr enable */
+#define MXC_H1_UCTRL_H1PM_BIT           (1 <<  8)               /* HOST1 power mask */
+
+/* USB_PHY_CTRL_FUNC */
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT      (1 << 8)        /* OTG Disable Overcurrent Event */
+#define MXC_H1_OC_DIS_BIT               (1 << 5)        /* UH1 Disable Overcurrent Event */
+
+/* USBH2CTRL */
+#define MXC_H2_UCTRL_H2UIE_BIT          (1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT          (1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT           (1 << 4)
+
+#define MXC_USBCMD_OFFSET               0x140
+
+/* USBCMD */
+#define MXC_UCMD_ITC_NO_THRESHOLD_MASK  (~(0xff << 16)) /* Interrupt Threshold Control */
+
+int mx51_initialize_usb_hw(int port, unsigned int flags)
+{
+        unsigned int v;
+        void __iomem *usb_base;
+        void __iomem *usbotg_base;
+        void __iomem *usbother_base;
+        int ret = 0;
+
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        if (!usb_base) {
+                printk(KERN_ERR "%s(): ioremap failed\n", __func__);
+                return -ENOMEM;
+        }
+
+        switch (port) {
+        case 0: /* OTG port */
+                usbotg_base = usb_base + MXC_OTG_OFFSET;
+                break;
+        case 1: /* Host 1 port */
+                usbotg_base = usb_base + MXC_H1_OFFSET;
+                break;
+        case 2: /* Host 2 port */
+                usbotg_base = usb_base + MXC_H2_OFFSET;
+                break;
+        default:
+                printk(KERN_ERR"%s no such port %d\n", __func__, port);
+                ret = -ENOENT;
+                goto error;
+        }
+        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+        switch (port) {
+        case 0: /*OTG port */
+                if (flags & MXC_EHCI_INTERNAL_PHY) {
+                        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+
+                        if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
+                                /* OC/USBPWR is not used */
+                                v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
+                        } else {
+                                /* OC/USBPWR is used */
+                                v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+                        }
+                        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+
+                        v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+                        if (flags & MXC_EHCI_WAKEUP_ENABLED)
+                                v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
+                        else
+                                v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
+                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                                v |= MXC_OTG_UCTRL_OPM_BIT;
+                        else
+                                v &= ~MXC_OTG_UCTRL_OPM_BIT;
+                        __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
+                }
+                break;
+        case 1: /* Host 1 */
+                /*Host ULPI */
+                v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+                if (flags & MXC_EHCI_WAKEUP_ENABLED) {
+                        /* HOST1 wakeup/ULPI intr enable */
+                        v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
+                } else {
+                        /* HOST1 wakeup/ULPI intr disable */
+                        v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
+                }
+
+                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                        v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
+                else
+                        v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
+                __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
+
+                v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                        v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
+                else
+                        v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
+                __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+
+                v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
+                if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
+                        /* Interrupt Threshold Control:Immediate (no threshold) */
+                        v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
+                __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
+                break;
+        case 2: /* Host 2 ULPI */
+                v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
+                if (flags & MXC_EHCI_WAKEUP_ENABLED) {
+                        /* HOST1 wakeup/ULPI intr enable */
+                        v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
+                } else {
+                        /* HOST1 wakeup/ULPI intr disable */
+                        v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
+                }
+
+                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                        v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+                else
+                        v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+                __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
+                break;
+        }
+
+error:
+        iounmap(usb_base);
+        return ret;
+}
+
diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c
index 8c6540e58390..b9c363b514a9 100644
--- a/arch/arm/mach-mx5/mm-mx50.c
+++ b/arch/arm/mach-mx5/mm-mx50.c
@@ -26,6 +26,8 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-v3.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
 
 /*
  * Define the MX50 memory map.
@@ -44,16 +46,27 @@ static struct map_desc mx50_io_desc[] __initdata = {
  */
 void __init mx50_map_io(void)
 {
+        iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
+}
+
+void __init imx50_init_early(void)
+{
         mxc_set_cpu_type(MXC_CPU_MX50);
         mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
-        iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
 }
 
-int imx50_register_gpios(void);
+static struct mxc_gpio_port imx50_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+};
 
 void __init mx50_init_irq(void)
 {
         tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
-        imx50_register_gpios();
+        mxc_gpio_init(imx50_gpio_ports, ARRAY_SIZE(imx50_gpio_ports));
 }
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index 457f9f95204b..ff557301b42b 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -47,18 +47,26 @@ static struct map_desc mx53_io_desc[] __initdata = {
  */
 void __init mx51_map_io(void)
 {
+        iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
+}
+
+void __init imx51_init_early(void)
+{
         mxc_set_cpu_type(MXC_CPU_MX51);
         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
-        iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
 }
 
 void __init mx53_map_io(void)
 {
+        iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
+}
+
+void __init imx53_init_early(void)
+{
         mxc_set_cpu_type(MXC_CPU_MX53);
         mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG_BASE_ADDR));
-        iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
+        mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
 }
 
 int imx51_register_gpios(void);
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
new file mode 100644
index 000000000000..51a67fc7f0ef
--- /dev/null
+++ b/arch/arm/mach-mx5/mx51_efika.c
@@ -0,0 +1,636 @@
+/*
+ * based on code from the following
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
+ * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/input.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/fsl_devices.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+#include <mach/i2c.h>
+#include <mach/mxc_ehci.h>
+
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <mach/ulpi.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach-types.h>
+
+#include "devices-imx51.h"
+#include "devices.h"
+#include "efika.h"
+#include "cpu_op-mx51.h"
+
+#define MX51_USB_CTRL_1_OFFSET          0x10
+#define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
+#define MX51_USB_PLL_DIV_19_2_MHZ       0x01
+
+#define EFIKAMX_USB_HUB_RESET   IMX_GPIO_NR(1, 5)
+#define EFIKAMX_USBH1_STP       IMX_GPIO_NR(1, 27)
+
+#define EFIKAMX_SPI_CS0         IMX_GPIO_NR(4, 24)
+#define EFIKAMX_SPI_CS1         IMX_GPIO_NR(4, 25)
+
+#define EFIKAMX_PMIC            IMX_GPIO_NR(1, 6)
+
+static iomux_v3_cfg_t mx51efika_pads[] = {
+        /* UART1 */
+        MX51_PAD_UART1_RXD__UART1_RXD,
+        MX51_PAD_UART1_TXD__UART1_TXD,
+        MX51_PAD_UART1_RTS__UART1_RTS,
+        MX51_PAD_UART1_CTS__UART1_CTS,
+
+        /* SD 1 */
+        MX51_PAD_SD1_CMD__SD1_CMD,
+        MX51_PAD_SD1_CLK__SD1_CLK,
+        MX51_PAD_SD1_DATA0__SD1_DATA0,
+        MX51_PAD_SD1_DATA1__SD1_DATA1,
+        MX51_PAD_SD1_DATA2__SD1_DATA2,
+        MX51_PAD_SD1_DATA3__SD1_DATA3,
+
+        /* SD 2 */
+        MX51_PAD_SD2_CMD__SD2_CMD,
+        MX51_PAD_SD2_CLK__SD2_CLK,
+        MX51_PAD_SD2_DATA0__SD2_DATA0,
+        MX51_PAD_SD2_DATA1__SD2_DATA1,
+        MX51_PAD_SD2_DATA2__SD2_DATA2,
+        MX51_PAD_SD2_DATA3__SD2_DATA3,
+
+        /* SD/MMC WP/CD */
+        MX51_PAD_GPIO1_0__SD1_CD,
+        MX51_PAD_GPIO1_1__SD1_WP,
+        MX51_PAD_GPIO1_7__SD2_WP,
+        MX51_PAD_GPIO1_8__SD2_CD,
+
+        /* spi */
+        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
+        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
+        MX51_PAD_CSPI1_SS0__GPIO4_24,
+        MX51_PAD_CSPI1_SS1__GPIO4_25,
+        MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
+        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
+        MX51_PAD_GPIO1_6__GPIO1_6,
+
+        /* USB HOST1 */
+        MX51_PAD_USBH1_CLK__USBH1_CLK,
+        MX51_PAD_USBH1_DIR__USBH1_DIR,
+        MX51_PAD_USBH1_NXT__USBH1_NXT,
+        MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+        MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+        MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+        MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+        MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+        MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+        MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+        MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+
+        /* USB HUB RESET */
+        MX51_PAD_GPIO1_5__GPIO1_5,
+
+        /* WLAN */
+        MX51_PAD_EIM_A22__GPIO2_16,
+        MX51_PAD_EIM_A16__GPIO2_10,
+
+        /* USB PHY RESET */
+        MX51_PAD_EIM_D27__GPIO2_9,
+};
+
+/* Serial ports */
+static const struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+/* This function is board specific as the bit mask for the plldiv will also
+ * be different for other Freescale SoCs, thus a common bitmask is not
+ * possible and cannot get place in /plat-mxc/ehci.c.
+ */
+static int initialize_otg_port(struct platform_device *pdev)
+{
+        u32 v;
+        void __iomem *usb_base;
+        void __iomem *usbother_base;
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        if (!usb_base)
+                return -ENOMEM;
+        usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
+
+        /* Set the PHY clock to 19.2MHz */
+        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
+        v |= MX51_USB_PLL_DIV_19_2_MHZ;
+        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        iounmap(usb_base);
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
+}
+
+static struct mxc_usbh_platform_data dr_utmi_config = {
+        .init   = initialize_otg_port,
+        .portsc = MXC_EHCI_UTMI_16BIT,
+};
+
+static int initialize_usbh1_port(struct platform_device *pdev)
+{
+        iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
+        iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
+        u32 v;
+        void __iomem *usb_base;
+        void __iomem *socregs_base;
+
+        mxc_iomux_v3_setup_pad(usbh1gpio);
+        gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
+        gpio_direction_output(EFIKAMX_USBH1_STP, 0);
+        msleep(1);
+        gpio_set_value(EFIKAMX_USBH1_STP, 1);
+        msleep(1);
+
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
+
+        /* The clock for the USBH1 ULPI port will come externally */
+        /* from the PHY. */
+        v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
+        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
+                        socregs_base + MX51_USB_CTRL_1_OFFSET);
+
+        iounmap(usb_base);
+
+        gpio_free(EFIKAMX_USBH1_STP);
+        mxc_iomux_v3_setup_pad(usbh1stp);
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(0, MXC_EHCI_ITC_NO_THRESHOLD);
+}
+
+static struct mxc_usbh_platform_data usbh1_config = {
+        .init   = initialize_usbh1_port,
+        .portsc = MXC_EHCI_MODE_ULPI,
+};
+
+static void mx51_efika_hubreset(void)
+{
+        gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
+        gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
+        msleep(1);
+        gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
+        msleep(1);
+        gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
+}
+
+static void __init mx51_efika_usb(void)
+{
+        mx51_efika_hubreset();
+
+        /* pulling it low, means no USB at all... */
+        gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
+        gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
+        msleep(1);
+        gpio_set_value(EFIKA_USB_PHY_RESET, 1);
+
+        usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                        ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
+
+        mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+        if (usbh1_config.otg)
+                mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+}
+
+static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
+        {
+         .name = "u-boot",
+         .offset = 0,
+         .size = SZ_256K,
+        },
+        {
+          .name = "config",
+          .offset = MTDPART_OFS_APPEND,
+          .size = SZ_64K,
+        },
+};
+
+static struct flash_platform_data mx51_efika_spi_flash_data = {
+        .name           = "spi_flash",
+        .parts          = mx51_efika_spi_nor_partitions,
+        .nr_parts       = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
+        .type           = "sst25vf032b",
+};
+
+static struct regulator_consumer_supply sw1_consumers[] = {
+        {
+                .supply = "cpu_vcc",
+        }
+};
+
+static struct regulator_consumer_supply vdig_consumers[] = {
+        /* sgtl5000 */
+        REGULATOR_SUPPLY("VDDA", "1-000a"),
+        REGULATOR_SUPPLY("VDDD", "1-000a"),
+};
+
+static struct regulator_consumer_supply vvideo_consumers[] = {
+        /* sgtl5000 */
+        REGULATOR_SUPPLY("VDDIO", "1-000a"),
+};
+
+static struct regulator_consumer_supply vsd_consumers[] = {
+        REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.0"),
+        REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
+};
+
+static struct regulator_consumer_supply pwgt1_consumer[] = {
+        {
+                .supply = "pwgt1",
+        }
+};
+
+static struct regulator_consumer_supply pwgt2_consumer[] = {
+        {
+                .supply = "pwgt2",
+        }
+};
+
+static struct regulator_consumer_supply coincell_consumer[] = {
+        {
+                .supply = "coincell",
+        }
+};
+
+static struct regulator_init_data sw1_init = {
+        .constraints = {
+                .name = "SW1",
+                .min_uV = 600000,
+                .max_uV = 1375000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .valid_modes_mask = 0,
+                .always_on = 1,
+                .boot_on = 1,
+                .state_mem = {
+                        .uV = 850000,
+                        .mode = REGULATOR_MODE_NORMAL,
+                        .enabled = 1,
+                },
+        },
+        .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
+        .consumer_supplies = sw1_consumers,
+};
+
+static struct regulator_init_data sw2_init = {
+        .constraints = {
+                .name = "SW2",
+                .min_uV = 900000,
+                .max_uV = 1850000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .always_on = 1,
+                .boot_on = 1,
+                .state_mem = {
+                        .uV = 950000,
+                        .mode = REGULATOR_MODE_NORMAL,
+                        .enabled = 1,
+                },
+        }
+};
+
+static struct regulator_init_data sw3_init = {
+        .constraints = {
+                .name = "SW3",
+                .min_uV = 1100000,
+                .max_uV = 1850000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .always_on = 1,
+                .boot_on = 1,
+        }
+};
+
+static struct regulator_init_data sw4_init = {
+        .constraints = {
+                .name = "SW4",
+                .min_uV = 1100000,
+                .max_uV = 1850000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .always_on = 1,
+                .boot_on = 1,
+        }
+};
+
+static struct regulator_init_data viohi_init = {
+        .constraints = {
+                .name = "VIOHI",
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+
+static struct regulator_init_data vusb_init = {
+        .constraints = {
+                .name = "VUSB",
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+
+static struct regulator_init_data swbst_init = {
+        .constraints = {
+                .name = "SWBST",
+        }
+};
+
+static struct regulator_init_data vdig_init = {
+        .constraints = {
+                .name = "VDIG",
+                .min_uV = 1050000,
+                .max_uV = 1800000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .always_on = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
+        .consumer_supplies = vdig_consumers,
+};
+
+static struct regulator_init_data vpll_init = {
+        .constraints = {
+                .name = "VPLL",
+                .min_uV = 1050000,
+                .max_uV = 1800000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+
+static struct regulator_init_data vusb2_init = {
+        .constraints = {
+                .name = "VUSB2",
+                .min_uV = 2400000,
+                .max_uV = 2775000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+
+static struct regulator_init_data vvideo_init = {
+        .constraints = {
+                .name = "VVIDEO",
+                .min_uV = 2775000,
+                .max_uV = 2775000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .apply_uV = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
+        .consumer_supplies = vvideo_consumers,
+};
+
+static struct regulator_init_data vaudio_init = {
+        .constraints = {
+                .name = "VAUDIO",
+                .min_uV = 2300000,
+                .max_uV = 3000000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+        }
+};
+
+static struct regulator_init_data vsd_init = {
+        .constraints = {
+                .name = "VSD",
+                .min_uV = 1800000,
+                .max_uV = 3150000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE,
+                .boot_on = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
+        .consumer_supplies = vsd_consumers,
+};
+
+static struct regulator_init_data vcam_init = {
+        .constraints = {
+                .name = "VCAM",
+                .min_uV = 2500000,
+                .max_uV = 3000000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE |
+                        REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
+                .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
+                .boot_on = 1,
+        }
+};
+
+static struct regulator_init_data vgen1_init = {
+        .constraints = {
+                .name = "VGEN1",
+                .min_uV = 1200000,
+                .max_uV = 3150000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+
+static struct regulator_init_data vgen2_init = {
+        .constraints = {
+                .name = "VGEN2",
+                .min_uV = 1200000,
+                .max_uV = 3150000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+
+static struct regulator_init_data vgen3_init = {
+        .constraints = {
+                .name = "VGEN3",
+                .min_uV = 1800000,
+                .max_uV = 2900000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+
+static struct regulator_init_data gpo1_init = {
+        .constraints = {
+                .name = "GPO1",
+        }
+};
+
+static struct regulator_init_data gpo2_init = {
+        .constraints = {
+                .name = "GPO2",
+        }
+};
+
+static struct regulator_init_data gpo3_init = {
+        .constraints = {
+                .name = "GPO3",
+        }
+};
+
+static struct regulator_init_data gpo4_init = {
+        .constraints = {
+                .name = "GPO4",
+        }
+};
+
+static struct regulator_init_data pwgt1_init = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .boot_on        = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
+        .consumer_supplies = pwgt1_consumer,
+};
+
+static struct regulator_init_data pwgt2_init = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .boot_on        = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
+        .consumer_supplies = pwgt2_consumer,
+};
+
+static struct regulator_init_data vcoincell_init = {
+        .constraints = {
+                .name = "COINCELL",
+                .min_uV = 3000000,
+                .max_uV = 3000000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
+        .consumer_supplies = coincell_consumer,
+};
+
+static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
+        { .id = MC13892_SW1,            .init_data =  &sw1_init },
+        { .id = MC13892_SW2,            .init_data =  &sw2_init },
+        { .id = MC13892_SW3,            .init_data =  &sw3_init },
+        { .id = MC13892_SW4,            .init_data =  &sw4_init },
+        { .id = MC13892_SWBST,          .init_data =  &swbst_init },
+        { .id = MC13892_VIOHI,          .init_data =  &viohi_init },
+        { .id = MC13892_VPLL,           .init_data =  &vpll_init },
+        { .id = MC13892_VDIG,           .init_data =  &vdig_init },
+        { .id = MC13892_VSD,            .init_data =  &vsd_init },
+        { .id = MC13892_VUSB2,          .init_data =  &vusb2_init },
+        { .id = MC13892_VVIDEO,         .init_data =  &vvideo_init },
+        { .id = MC13892_VAUDIO,         .init_data =  &vaudio_init },
+        { .id = MC13892_VCAM,           .init_data =  &vcam_init },
+        { .id = MC13892_VGEN1,          .init_data =  &vgen1_init },
+        { .id = MC13892_VGEN2,          .init_data =  &vgen2_init },
+        { .id = MC13892_VGEN3,          .init_data =  &vgen3_init },
+        { .id = MC13892_VUSB,           .init_data =  &vusb_init },
+        { .id = MC13892_GPO1,           .init_data =  &gpo1_init },
+        { .id = MC13892_GPO2,           .init_data =  &gpo2_init },
+        { .id = MC13892_GPO3,           .init_data =  &gpo3_init },
+        { .id = MC13892_GPO4,           .init_data =  &gpo4_init },
+        { .id = MC13892_PWGT1SPI,       .init_data = &pwgt1_init },
+        { .id = MC13892_PWGT2SPI,       .init_data = &pwgt2_init },
+        { .id = MC13892_VCOINCELL,      .init_data = &vcoincell_init },
+};
+
+static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
+        .flags = MC13XXX_USE_RTC | MC13XXX_USE_REGULATOR,
+        .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
+        .regulators = mx51_efika_regulators,
+};
+
+static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
+        {
+                .modalias = "m25p80",
+                .max_speed_hz = 25000000,
+                .bus_num = 0,
+                .chip_select = 1,
+                .platform_data = &mx51_efika_spi_flash_data,
+                .irq = -1,
+        },
+        {
+                .modalias = "mc13892",
+                .max_speed_hz = 1000000,
+                .bus_num = 0,
+                .chip_select = 0,
+                .platform_data = &mx51_efika_mc13892_data,
+                .irq = gpio_to_irq(EFIKAMX_PMIC),
+        },
+};
+
+static int mx51_efika_spi_cs[] = {
+        EFIKAMX_SPI_CS0,
+        EFIKAMX_SPI_CS1,
+};
+
+static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
+        .chipselect     = mx51_efika_spi_cs,
+        .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
+};
+
+void __init efika_board_common_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
+                                        ARRAY_SIZE(mx51efika_pads));
+        imx51_add_imx_uart(0, &uart_pdata);
+        mx51_efika_usb();
+        imx51_add_sdhci_esdhc_imx(0, NULL);
+
+        /* FIXME: comes from original code. check this. */
+        if (mx51_revision() < IMX_CHIP_REVISION_2_0)
+                sw2_init.constraints.state_mem.uV = 1100000;
+        else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
+                sw2_init.constraints.state_mem.uV = 1250000;
+                sw1_init.constraints.state_mem.uV = 1000000;
+        }
+        if (machine_is_mx51_efikasb())
+                vgen1_init.constraints.max_uV = 1200000;
+
+        gpio_request(EFIKAMX_PMIC, "pmic irq");
+        gpio_direction_input(EFIKAMX_PMIC);
+        spi_register_board_info(mx51_efika_spi_board_info,
+                ARRAY_SIZE(mx51_efika_spi_board_info));
+        imx51_add_ecspi(0, &mx51_efika_spi_pdata);
+
+#if defined(CONFIG_CPU_FREQ_IMX)
+        get_cpu_op = mx51_get_cpu_op;
+#endif
+}
+
diff --git a/arch/arm/mach-mxc91231/iomux.c b/arch/arm/mach-mxc91231/iomux.c
index 405d9b19d891..66fc41cbf2ca 100644
--- a/arch/arm/mach-mxc91231/iomux.c
+++ b/arch/arm/mach-mxc91231/iomux.c
@@ -50,7 +50,7 @@ unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
 /*
  * set the mode for a IOMUX pin.
  */
-int mxc_iomux_mode(const unsigned int pin_mode)
+int mxc_iomux_mode(unsigned int pin_mode)
 {
         u32 side, field, l, mode, ret = 0;
         void __iomem *reg;
@@ -114,7 +114,7 @@ EXPORT_SYMBOL(mxc_iomux_set_pad);
  *      - reserves the pin so that it is not claimed by another driver
  *      - setups the iomux according to the configuration
  */
-int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label)
+int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label)
 {
         unsigned pad = PIN_GLOBAL_NUM(pin_mode);
         if (pad >= (PIN_MAX + 1)) {
@@ -134,10 +134,10 @@ int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label)
 }
 EXPORT_SYMBOL(mxc_iomux_alloc_pin);
 
-int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
                 const char *label)
 {
-        unsigned int *p = pin_list;
+        const unsigned int *p = pin_list;
         int i;
         int ret = -EINVAL;
 
@@ -155,7 +155,7 @@ setup_error:
 }
 EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
 
-void mxc_iomux_release_pin(const unsigned int pin_mode)
+void mxc_iomux_release_pin(unsigned int pin_mode)
 {
         unsigned pad = PIN_GLOBAL_NUM(pin_mode);
 
@@ -164,9 +164,9 @@ void mxc_iomux_release_pin(const unsigned int pin_mode)
 }
 EXPORT_SYMBOL(mxc_iomux_release_pin);
 
-void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
+void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
 {
-        unsigned int *p = pin_list;
+        const unsigned int *p = pin_list;
         int i;
 
         for (i = 0; i < count; i++) {
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
index 395d83be8c98..f31a45e5a0b8 100644
--- a/arch/arm/mach-mxc91231/magx-zn5.c
+++ b/arch/arm/mach-mxc91231/magx-zn5.c
@@ -53,9 +53,10 @@ struct sys_timer zn5_timer = {
 };
 
 MACHINE_START(MAGX_ZN5, "Motorola Zn5")
-        .boot_params    = MXC91231_PHYS_OFFSET + 0x100,
-        .map_io         = mxc91231_map_io,
-        .init_irq       = mxc91231_init_irq,
-        .timer          = &zn5_timer,
-        .init_machine   = zn5_init,
+        .boot_params = MXC91231_PHYS_OFFSET + 0x100,
+        .map_io = mxc91231_map_io,
+        .init_early = mxc91231_init_early,
+        .init_irq = mxc91231_init_irq,
+        .timer = &zn5_timer,
+        .init_machine = zn5_init,
 MACHINE_END
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
index 7652c301da88..a77f6daf6a26 100644
--- a/arch/arm/mach-mxc91231/mm.c
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -45,11 +45,14 @@ static struct map_desc mxc91231_io_desc[] __initdata = {
  */
 void __init mxc91231_map_io(void)
 {
-        mxc_set_cpu_type(MXC_CPU_MXC91231);
-
         iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc));
 }
 
+void __init mxc91231_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MXC91231);
+}
+
 int mxc91231_register_gpios(void);
 
 void __init mxc91231_init_irq(void)
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 8bfc8df54617..4f6f174af6c8 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -2,13 +2,18 @@ if ARCH_MXS
 
 source "arch/arm/mach-mxs/devices/Kconfig"
 
+config MXS_OCOTP
+        bool
+
 config SOC_IMX23
         bool
         select CPU_ARM926T
+        select HAVE_PWM
 
 config SOC_IMX28
         bool
         select CPU_ARM926T
+        select HAVE_PWM
 
 comment "MXS platforms:"
 
@@ -16,6 +21,8 @@ config MACH_MX23EVK
         bool "Support MX23EVK Platform"
         select SOC_IMX23
         select MXS_HAVE_AMBA_DUART
+        select MXS_HAVE_PLATFORM_AUART
+        select MXS_HAVE_PLATFORM_MXSFB
         default y
         help
           Include support for MX23EVK platform. This includes specific
@@ -25,10 +32,27 @@ config MACH_MX28EVK
         bool "Support MX28EVK Platform"
         select SOC_IMX28
         select MXS_HAVE_AMBA_DUART
+        select MXS_HAVE_PLATFORM_AUART
         select MXS_HAVE_PLATFORM_FEC
+        select MXS_HAVE_PLATFORM_FLEXCAN
+        select MXS_HAVE_PLATFORM_MXSFB
+        select MXS_OCOTP
         default y
         help
           Include support for MX28EVK platform. This includes specific
           configurations for the board and its peripherals.
 
+config MODULE_TX28
+        bool
+        select SOC_IMX28
+        select MXS_HAVE_AMBA_DUART
+        select MXS_HAVE_PLATFORM_AUART
+        select MXS_HAVE_PLATFORM_FEC
+        select MXS_HAVE_PLATFORM_MXS_I2C
+        select MXS_HAVE_PLATFORM_MXS_PWM
+
+config MACH_TX28
+        bool "Ka-Ro TX28 module"
+        select MODULE_TX28
+
 endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 39d3f9c2a841..2f1f6141ca71 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,10 +1,15 @@
 # Common support
 obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o
 
+obj-$(CONFIG_MXS_OCOTP) += ocotp.o
+obj-$(CONFIG_PM) += pm.o
+
 obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
 obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
 
 obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
 obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
+obj-$(CONFIG_MODULE_TX28) += module-tx28.o
+obj-$(CONFIG_MACH_TX28)    += mach-tx28.o
 
 obj-y += devices/
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index ca72a05ed9c1..d133c7f30940 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -442,11 +442,18 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
         /* for amba-pl011 driver */
         _REGISTER_CLOCK("duart", NULL, uart_clk)
+        _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
         _REGISTER_CLOCK("rtc", NULL, rtc_clk)
-        _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
+        _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
+        _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
         _REGISTER_CLOCK(NULL, "usb", usb_clk)
         _REGISTER_CLOCK(NULL, "audio", audio_clk)
-        _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
+        _REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk)
 };
 
 static int clk_misc_init(void)
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index fd1c4c54b8e5..5e489a2b2023 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -609,17 +609,30 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("duart", NULL, uart_clk)
         _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
         _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
+        _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
+        _REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk)
+        _REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk)
+        _REGISTER_CLOCK("mxs-auart.3", NULL, uart_clk)
+        _REGISTER_CLOCK("mxs-auart.4", NULL, uart_clk)
         _REGISTER_CLOCK("rtc", NULL, rtc_clk)
         _REGISTER_CLOCK("pll2", NULL, pll2_clk)
-        _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
-        _REGISTER_CLOCK(NULL, "xclk", xbus_clk)
-        _REGISTER_CLOCK(NULL, "can0", can0_clk)
-        _REGISTER_CLOCK(NULL, "can1", can1_clk)
+        _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
+        _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
+        _REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
+        _REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
         _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
         _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
-        _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.5", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.6", NULL, pwm_clk)
+        _REGISTER_CLOCK("mxs-pwm.7", NULL, pwm_clk)
         _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
         _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
+        _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
 };
 
 static int clk_misc_init(void)
@@ -737,6 +750,8 @@ int __init mx28_clocks_init(void)
         clk_enable(&emi_clk);
         clk_enable(&uart_clk);
 
+        clk_set_parent(&lcdif_clk, &ref_pix_clk);
+
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index 1256788561d0..c7e14f4e3669 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -10,7 +10,18 @@
  */
 #include <mach/mx23.h>
 #include <mach/devices-common.h>
+#include <mach/mxsfb.h>
 
 extern const struct amba_device mx23_duart_device __initconst;
 #define mx23_add_duart() \
         mxs_add_duart(&mx23_duart_device)
+
+extern const struct mxs_auart_data mx23_auart_data[] __initconst;
+#define mx23_add_auart(id)      mxs_add_auart(&mx23_auart_data[id])
+#define mx23_add_auart0()               mx23_add_auart(0)
+#define mx23_add_auart1()               mx23_add_auart(1)
+
+#define mx23_add_mxs_pwm(id)            mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id)
+
+struct platform_device *__init mx23_add_mxsfb(
+                const struct mxsfb_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 33773a6333a2..9d08555c4cf0 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -10,11 +10,34 @@
  */
 #include <mach/mx28.h>
 #include <mach/devices-common.h>
+#include <mach/mxsfb.h>
 
 extern const struct amba_device mx28_duart_device __initconst;
 #define mx28_add_duart() \
         mxs_add_duart(&mx28_duart_device)
 
+extern const struct mxs_auart_data mx28_auart_data[] __initconst;
+#define mx28_add_auart(id)      mxs_add_auart(&mx28_auart_data[id])
+#define mx28_add_auart0()               mx28_add_auart(0)
+#define mx28_add_auart1()               mx28_add_auart(1)
+#define mx28_add_auart2()               mx28_add_auart(2)
+#define mx28_add_auart3()               mx28_add_auart(3)
+#define mx28_add_auart4()               mx28_add_auart(4)
+
 extern const struct mxs_fec_data mx28_fec_data[] __initconst;
 #define mx28_add_fec(id, pdata) \
         mxs_add_fec(&mx28_fec_data[id], pdata)
+
+extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst;
+#define mx28_add_flexcan(id, pdata)     \
+        mxs_add_flexcan(&mx28_flexcan_data[id], pdata)
+#define mx28_add_flexcan0(pdata)        mx28_add_flexcan(0, pdata)
+#define mx28_add_flexcan1(pdata)        mx28_add_flexcan(1, pdata)
+
+extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
+#define mx28_add_mxs_i2c(id)            mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id])
+
+#define mx28_add_mxs_pwm(id)            mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id)
+
+struct platform_device *__init mx28_add_mxsfb(
+                const struct mxsfb_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
index c20d54740b0b..cfdb6b284702 100644
--- a/arch/arm/mach-mxs/devices.c
+++ b/arch/arm/mach-mxs/devices.c
@@ -66,6 +66,8 @@ struct platform_device *__init mxs_add_platform_device_dmamask(
         ret = platform_device_add(pdev);
         if (ret) {
 err:
+                if (dmamask)
+                        kfree(pdev->dev.dma_mask);
                 platform_device_put(pdev);
                 return ERR_PTR(ret);
         }
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index cf7dc1ae575b..1451ad060d82 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -2,5 +2,21 @@ config MXS_HAVE_AMBA_DUART
         bool
         select ARM_AMBA
 
+config MXS_HAVE_PLATFORM_AUART
+        bool
+
 config MXS_HAVE_PLATFORM_FEC
         bool
+
+config MXS_HAVE_PLATFORM_FLEXCAN
+        select HAVE_CAN_FLEXCAN if CAN
+        bool
+
+config MXS_HAVE_PLATFORM_MXS_I2C
+        bool
+
+config MXS_HAVE_PLATFORM_MXS_PWM
+        bool
+
+config MXS_HAVE_PLATFORM_MXSFB
+        bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
index d0a09f6934b8..0d9bea30b0a2 100644
--- a/arch/arm/mach-mxs/devices/Makefile
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -1,2 +1,8 @@
 obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
+obj-y += platform-dma.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o
diff --git a/arch/arm/mach-mxs/devices/platform-auart.c b/arch/arm/mach-mxs/devices/platform-auart.c
new file mode 100644
index 000000000000..796606cce0ce
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-auart.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+
+#define mxs_auart_data_entry_single(soc, _id, hwid)                     \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _AUART ## hwid ## _BASE_ADDR,          \
+                .irq = soc ## _INT_AUART ## hwid,                       \
+        }
+
+#define mxs_auart_data_entry(soc, _id, hwid)                            \
+        [_id] = mxs_auart_data_entry_single(soc, _id, hwid)
+
+#ifdef CONFIG_SOC_IMX23
+const struct mxs_auart_data mx23_auart_data[] __initconst = {
+#define mx23_auart_data_entry(_id, hwid)                                \
+        mxs_auart_data_entry(MX23, _id, hwid)
+        mx23_auart_data_entry(0, 1),
+        mx23_auart_data_entry(1, 2),
+};
+#endif
+
+#ifdef CONFIG_SOC_IMX28
+const struct mxs_auart_data mx28_auart_data[] __initconst = {
+#define mx28_auart_data_entry(_id)                                      \
+        mxs_auart_data_entry(MX28, _id, _id)
+        mx28_auart_data_entry(0),
+        mx28_auart_data_entry(1),
+        mx28_auart_data_entry(2),
+        mx28_auart_data_entry(3),
+        mx28_auart_data_entry(4),
+};
+#endif
+
+struct platform_device *__init mxs_add_auart(
+                const struct mxs_auart_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_8K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return mxs_add_platform_device_dmamask("mxs-auart", data->id,
+                                        res, ARRAY_SIZE(res), NULL, 0,
+                                        DMA_BIT_MASK(32));
+}
+
diff --git a/arch/arm/mach-mxs/devices/platform-dma.c b/arch/arm/mach-mxs/devices/platform-dma.c
new file mode 100644
index 000000000000..295c4424d5d9
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-dma.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/compiler.h>
+#include <linux/err.h>
+#include <linux/init.h>
+
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+
+static struct platform_device *__init mxs_add_dma(const char *devid,
+                                                resource_size_t base)
+{
+        struct resource res[] = {
+                {
+                        .start = base,
+                        .end = base + SZ_8K - 1,
+                        .flags = IORESOURCE_MEM,
+                }
+        };
+
+        return mxs_add_platform_device_dmamask(devid, -1,
+                                res, ARRAY_SIZE(res), NULL, 0,
+                                DMA_BIT_MASK(32));
+}
+
+static int __init mxs_add_mxs_dma(void)
+{
+        char *apbh = "mxs-dma-apbh";
+        char *apbx = "mxs-dma-apbx";
+
+        if (cpu_is_mx23()) {
+                mxs_add_dma(apbh, MX23_APBH_DMA_BASE_ADDR);
+                mxs_add_dma(apbx, MX23_APBX_DMA_BASE_ADDR);
+        }
+
+        if (cpu_is_mx28()) {
+                mxs_add_dma(apbh, MX28_APBH_DMA_BASE_ADDR);
+                mxs_add_dma(apbx, MX28_APBX_DMA_BASE_ADDR);
+        }
+
+        return 0;
+}
+arch_initcall(mxs_add_mxs_dma);
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c
index c42dff72b46c..9859cf283335 100644
--- a/arch/arm/mach-mxs/devices/platform-fec.c
+++ b/arch/arm/mach-mxs/devices/platform-fec.c
@@ -45,6 +45,7 @@ struct platform_device *__init mxs_add_fec(
                 },
         };
 
-        return mxs_add_platform_device("imx28-fec", data->id,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+        return mxs_add_platform_device_dmamask("imx28-fec", data->id,
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata),
+                        DMA_BIT_MASK(32));
 }
diff --git a/arch/arm/mach-mxs/devices/platform-flexcan.c b/arch/arm/mach-mxs/devices/platform-flexcan.c
new file mode 100644
index 000000000000..43a6b4bae6fe
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-flexcan.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2010, 2011 Pengutronix,
+ *                          Marc Kleine-Budde <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+
+#define mxs_flexcan_data_entry_single(soc, _id, _hwid, _size)           \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR,           \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_CAN ## _hwid,                        \
+        }
+
+#define mxs_flexcan_data_entry(soc, _id, _hwid, _size)                  \
+        [_id] = mxs_flexcan_data_entry_single(soc, _id, _hwid, _size)
+
+#ifdef CONFIG_SOC_IMX28
+const struct mxs_flexcan_data mx28_flexcan_data[] __initconst = {
+#define mx28_flexcan_data_entry(_id, _hwid)                             \
+        mxs_flexcan_data_entry_single(MX28, _id, _hwid, SZ_8K)
+        mx28_flexcan_data_entry(0, 0),
+        mx28_flexcan_data_entry(1, 1),
+};
+#endif /* ifdef CONFIG_SOC_IMX28 */
+
+struct platform_device *__init mxs_add_flexcan(
+                const struct mxs_flexcan_data *data,
+                const struct flexcan_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return mxs_add_platform_device("flexcan", data->id,
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
new file mode 100644
index 000000000000..eab3a06836d6
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2011 Pengutronix
+ * Wolfram Sang <w.sang@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+
+#define mxs_i2c_data_entry_single(soc, _id)                             \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _I2C ## _id ## _BASE_ADDR,             \
+                .errirq = soc ## _INT_I2C ## _id ## _ERROR,             \
+                .dmairq = soc ## _INT_I2C ## _id ## _DMA,               \
+        }
+
+#define mxs_i2c_data_entry(soc, _id)                                    \
+        [_id] = mxs_i2c_data_entry_single(soc, _id)
+
+#ifdef CONFIG_SOC_IMX28
+const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst = {
+        mxs_i2c_data_entry(MX28, 0),
+        mxs_i2c_data_entry(MX28, 1),
+};
+#endif
+
+struct platform_device *__init mxs_add_mxs_i2c(const struct mxs_i2c_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_8K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->errirq,
+                        .end = data->errirq,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = data->dmairq,
+                        .end = data->dmairq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return mxs_add_platform_device("mxs-i2c", data->id, res,
+                                        ARRAY_SIZE(res), NULL, 0);
+}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
new file mode 100644
index 000000000000..680f5a902936
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/devices-common.h>
+
+struct platform_device *__init mxs_add_mxs_pwm(resource_size_t iobase, int id)
+{
+        struct resource res = {
+                .flags = IORESOURCE_MEM,
+        };
+
+        res.start = iobase + 0x10 + 0x20 * id;
+        res.end = res.start + 0x1f;
+
+        return mxs_add_platform_device("mxs-pwm", id, &res, 1, NULL, 0);
+}
diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c
new file mode 100644
index 000000000000..bf72c9b8dbdd
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxsfb.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+#include <mach/mxsfb.h>
+
+#ifdef CONFIG_SOC_IMX23
+struct platform_device *__init mx23_add_mxsfb(
+                const struct mxsfb_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = MX23_LCDIF_BASE_ADDR,
+                        .end = MX23_LCDIF_BASE_ADDR + SZ_8K - 1,
+                        .flags = IORESOURCE_MEM,
+                },
+        };
+
+        return mxs_add_platform_device_dmamask("imx23-fb", -1,
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
+}
+#endif /* ifdef CONFIG_SOC_IMX23 */
+
+#ifdef CONFIG_SOC_IMX28
+struct platform_device *__init mx28_add_mxsfb(
+                const struct mxsfb_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = MX28_LCDIF_BASE_ADDR,
+                        .end = MX28_LCDIF_BASE_ADDR + SZ_8K - 1,
+                        .flags = IORESOURCE_MEM,
+                },
+        };
+
+        return mxs_add_platform_device_dmamask("imx28-fb", -1,
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
+}
+#endif /* ifdef CONFIG_SOC_IMX28 */
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c
index 61991e4dde44..56fa2ed15222 100644
--- a/arch/arm/mach-mxs/gpio.c
+++ b/arch/arm/mach-mxs/gpio.c
@@ -182,6 +182,7 @@ static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
 }
 
 static struct irq_chip gpio_irq_chip = {
+        .name = "mxs gpio",
         .irq_ack = mxs_gpio_ack_irq,
         .irq_mask = mxs_gpio_mask_irq,
         .irq_unmask = mxs_gpio_unmask_irq,
@@ -289,39 +290,42 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
         return 0;
 }
 
-#define DEFINE_MXS_GPIO_PORT(soc, _id)                                  \
+#define MX23_GPIO_BASE  MX23_IO_ADDRESS(MX23_PINCTRL_BASE_ADDR)
+#define MX28_GPIO_BASE  MX28_IO_ADDRESS(MX28_PINCTRL_BASE_ADDR)
+
+#define DEFINE_MXS_GPIO_PORT(_base, _irq, _id)                          \
         {                                                               \
                 .chip.label = "gpio-" #_id,                             \
                 .id = _id,                                              \
-                .irq = soc ## _INT_GPIO ## _id,                         \
-                .base = soc ## _IO_ADDRESS(                             \
-                                soc ## _PINCTRL ## _BASE_ADDR),         \
+                .irq = _irq,                                            \
+                .base = _base,                                          \
                 .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32,   \
         }
 
-#define DEFINE_REGISTER_FUNCTION(prefix)                                \
-int __init prefix ## _register_gpios(void)                              \
-{                                                                       \
-        return mxs_gpio_init(prefix ## _gpio_ports,                     \
-                        ARRAY_SIZE(prefix ## _gpio_ports));             \
-}
-
 #ifdef CONFIG_SOC_IMX23
 static struct mxs_gpio_port mx23_gpio_ports[] = {
-        DEFINE_MXS_GPIO_PORT(MX23, 0),
-        DEFINE_MXS_GPIO_PORT(MX23, 1),
-        DEFINE_MXS_GPIO_PORT(MX23, 2),
+        DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO0, 0),
+        DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO1, 1),
+        DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO2, 2),
 };
-DEFINE_REGISTER_FUNCTION(mx23)
+
+int __init mx23_register_gpios(void)
+{
+        return mxs_gpio_init(mx23_gpio_ports, ARRAY_SIZE(mx23_gpio_ports));
+}
 #endif
 
 #ifdef CONFIG_SOC_IMX28
 static struct mxs_gpio_port mx28_gpio_ports[] = {
-        DEFINE_MXS_GPIO_PORT(MX28, 0),
-        DEFINE_MXS_GPIO_PORT(MX28, 1),
-        DEFINE_MXS_GPIO_PORT(MX28, 2),
-        DEFINE_MXS_GPIO_PORT(MX28, 3),
-        DEFINE_MXS_GPIO_PORT(MX28, 4),
+        DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO0, 0),
+        DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO1, 1),
+        DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO2, 2),
+        DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO3, 3),
+        DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO4, 4),
 };
-DEFINE_REGISTER_FUNCTION(mx28)
+
+int __init mx28_register_gpios(void)
+{
+        return mxs_gpio_init(mx28_gpio_ports, ARRAY_SIZE(mx28_gpio_ports));
+}
 #endif
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index 59133eb3cc96..635bb5d9a20a 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -13,6 +13,7 @@
 
 struct clk;
 
+extern const u32 *mxs_get_ocotp(void);
 extern int mxs_reset_block(void __iomem *);
 extern void mxs_timer_init(struct clk *, int);
 
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index 6c3d1a103433..71f24484b044 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -30,6 +30,16 @@ int __init mxs_add_amba_device(const struct amba_device *dev);
 /* duart */
 int __init mxs_add_duart(const struct amba_device *dev);
 
+/* auart */
+struct mxs_auart_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init mxs_add_auart(
+                const struct mxs_auart_data *data);
+
 /* fec */
 #include <linux/fec.h>
 struct mxs_fec_data {
@@ -41,3 +51,28 @@ struct mxs_fec_data {
 struct platform_device *__init mxs_add_fec(
                 const struct mxs_fec_data *data,
                 const struct fec_platform_data *pdata);
+
+/* flexcan */
+#include <linux/can/platform/flexcan.h>
+struct mxs_flexcan_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init mxs_add_flexcan(
+                const struct mxs_flexcan_data *data,
+                const struct flexcan_platform_data *pdata);
+
+/* i2c */
+struct mxs_i2c_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t errirq;
+        resource_size_t dmairq;
+};
+struct platform_device * __init mxs_add_mxs_i2c(const struct mxs_i2c_data *data);
+
+/* pwm */
+struct platform_device *__init mxs_add_mxs_pwm(
+                resource_size_t iobase, int id);
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
index 94e5dd83cdb8..b0190a4822f2 100644
--- a/arch/arm/mach-mxs/include/mach/iomux-mx23.h
+++ b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
@@ -254,102 +254,102 @@
 #define MX23_PAD_ROTARYB__GPMI_CE3N             MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_2)
 
 /* MUXSEL_GPIO */
-#define MX23_PAD_GPMI_D00__GPO_0_0              MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D01__GPO_0_1              MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D02__GPO_0_2              MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D03__GPO_0_3              MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D04__GPO_0_4              MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D05__GPO_0_5              MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D06__GPO_0_6              MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D07__GPO_0_7              MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D08__GPO_0_8              MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D09__GPO_0_9              MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D10__GPO_0_10             MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D11__GPO_0_11             MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D12__GPO_0_12             MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D13__GPO_0_13             MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D14__GPO_0_14             MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D15__GPO_0_15             MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CLE__GPO_0_16             MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_ALE__GPO_0_17             MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE2N__GPO_0_18            MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY0__GPO_0_19            MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY1__GPO_0_20            MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY2__GPO_0_21            MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY3__GPO_0_22            MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_WPN__GPO_0_23             MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_WRN__GPO_0_24             MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDN__GPO_0_25             MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_CTS__GPO_0_26           MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_RTS__GPO_0_27           MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_RX__GPO_0_28            MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_TX__GPO_0_29            MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_I2C_SCL__GPO_0_30              MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
-#define MX23_PAD_I2C_SDA__GPO_0_31              MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D00__GPIO_0_0             MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D01__GPIO_0_1             MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D02__GPIO_0_2             MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D03__GPIO_0_3             MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D04__GPIO_0_4             MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D05__GPIO_0_5             MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D06__GPIO_0_6             MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D07__GPIO_0_7             MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D08__GPIO_0_8             MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D09__GPIO_0_9             MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D10__GPIO_0_10            MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D11__GPIO_0_11            MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D12__GPIO_0_12            MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D13__GPIO_0_13            MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D14__GPIO_0_14            MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D15__GPIO_0_15            MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CLE__GPIO_0_16            MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_ALE__GPIO_0_17            MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE2N__GPIO_0_18           MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY0__GPIO_0_19           MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY1__GPIO_0_20           MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY2__GPIO_0_21           MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY3__GPIO_0_22           MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_WPN__GPIO_0_23            MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_WRN__GPIO_0_24            MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDN__GPIO_0_25            MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_CTS__GPIO_0_26          MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_RTS__GPIO_0_27          MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_RX__GPIO_0_28           MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_TX__GPIO_0_29           MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_I2C_SCL__GPIO_0_30             MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_I2C_SDA__GPIO_0_31             MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
 
-#define MX23_PAD_LCD_D00__GPO_1_0               MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D01__GPO_1_1               MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D02__GPO_1_2               MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D03__GPO_1_3               MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D04__GPO_1_4               MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D05__GPO_1_5               MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D06__GPO_1_6               MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D07__GPO_1_7               MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D08__GPO_1_8               MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D09__GPO_1_9               MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D10__GPO_1_10              MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D11__GPO_1_11              MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D12__GPO_1_12              MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D13__GPO_1_13              MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D14__GPO_1_14              MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D15__GPO_1_15              MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D16__GPO_1_16              MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D17__GPO_1_17              MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_RESET__GPO_1_18            MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_RS__GPO_1_19               MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_WR__GPO_1_20               MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_CS__GPO_1_21               MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_DOTCK__GPO_1_22            MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_ENABLE__GPO_1_23           MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_HSYNC__GPO_1_24            MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_VSYNC__GPO_1_25            MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM0__GPO_1_26                 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM1__GPO_1_27                 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM2__GPO_1_28                 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM3__GPO_1_29                 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM4__GPO_1_30                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D00__GPIO_1_0              MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D01__GPIO_1_1              MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D02__GPIO_1_2              MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D03__GPIO_1_3              MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D04__GPIO_1_4              MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D05__GPIO_1_5              MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D06__GPIO_1_6              MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D07__GPIO_1_7              MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D08__GPIO_1_8              MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D09__GPIO_1_9              MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D10__GPIO_1_10             MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D11__GPIO_1_11             MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D12__GPIO_1_12             MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D13__GPIO_1_13             MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D14__GPIO_1_14             MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D15__GPIO_1_15             MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D16__GPIO_1_16             MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D17__GPIO_1_17             MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_RESET__GPIO_1_18           MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_RS__GPIO_1_19              MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_WR__GPIO_1_20              MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_CS__GPIO_1_21              MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_DOTCK__GPIO_1_22           MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_ENABLE__GPIO_1_23          MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_HSYNC__GPIO_1_24           MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_VSYNC__GPIO_1_25           MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM0__GPIO_1_26                MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM1__GPIO_1_27                MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM2__GPIO_1_28                MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM3__GPIO_1_29                MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM4__GPIO_1_30                MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
 
-#define MX23_PAD_SSP1_CMD__GPO_2_0              MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DETECT__GPO_2_1           MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA0__GPO_2_2            MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA1__GPO_2_3            MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA2__GPO_2_4            MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA3__GPO_2_5            MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_SCK__GPO_2_6              MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_ROTARYA__GPO_2_7               MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_ROTARYB__GPO_2_8               MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A00__GPO_2_9               MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A01__GPO_2_10              MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A02__GPO_2_11              MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A03__GPO_2_12              MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A04__GPO_2_13              MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A05__GPO_2_14              MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A06__GPO_2_15              MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A07__GPO_2_16              MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A08__GPO_2_17              MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A09__GPO_2_18              MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A10__GPO_2_19              MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A11__GPO_2_20              MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A12__GPO_2_21              MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_BA0__GPO_2_22              MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_BA1__GPO_2_23              MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CASN__GPO_2_24             MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CE0N__GPO_2_25             MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CE1N__GPO_2_26             MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE1N__GPO_2_27            MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE0N__GPO_2_28            MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CKE__GPO_2_29              MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_RASN__GPO_2_30             MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_WEN__GPO_2_31              MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_CMD__GPIO_2_0             MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DETECT__GPIO_2_1          MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA0__GPIO_2_2           MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA1__GPIO_2_3           MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA2__GPIO_2_4           MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA3__GPIO_2_5           MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_SCK__GPIO_2_6             MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_ROTARYA__GPIO_2_7              MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_ROTARYB__GPIO_2_8              MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A00__GPIO_2_9              MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A01__GPIO_2_10             MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A02__GPIO_2_11             MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A03__GPIO_2_12             MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A04__GPIO_2_13             MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A05__GPIO_2_14             MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A06__GPIO_2_15             MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A07__GPIO_2_16             MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A08__GPIO_2_17             MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A09__GPIO_2_18             MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A10__GPIO_2_19             MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A11__GPIO_2_20             MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A12__GPIO_2_21             MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_BA0__GPIO_2_22             MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_BA1__GPIO_2_23             MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CASN__GPIO_2_24            MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CE0N__GPIO_2_25            MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CE1N__GPIO_2_26            MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE1N__GPIO_2_27           MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE0N__GPIO_2_28           MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CKE__GPIO_2_29             MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_RASN__GPIO_2_30            MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_WEN__GPIO_2_31             MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
 
 #endif /* __MACH_IOMUX_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h
index fe558e3c5a9a..7abdf58b8bb7 100644
--- a/arch/arm/mach-mxs/include/mach/iomux.h
+++ b/arch/arm/mach-mxs/include/mach/iomux.h
@@ -91,6 +91,9 @@ typedef u32 iomux_cfg_t;
 #define MXS_PAD_PULLUP  ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \
                                         MXS_PAD_PULL_VALID_MASK)
 
+/* generic pad control used in most cases */
+#define MXS_PAD_CTRL    (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL)
+
 #define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull)           \
                 (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) |         \
                 ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) |            \
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h
index 9edd02ec8e30..c0a18c23084a 100644
--- a/arch/arm/mach-mxs/include/mach/mx23.h
+++ b/arch/arm/mach-mxs/include/mach/mx23.h
@@ -93,7 +93,7 @@
 #define MX23_INT_USB_WAKEUP             12
 #define MX23_INT_GPMI_DMA               13
 #define MX23_INT_SSP1_DMA               14
-#define MX23_INT_SSP_ERROR              15
+#define MX23_INT_SSP1_ERROR             15
 #define MX23_INT_GPIO0                  16
 #define MX23_INT_GPIO1                  17
 #define MX23_INT_GPIO2                  18
@@ -101,9 +101,9 @@
 #define MX23_INT_SSP2_DMA               20
 #define MX23_INT_ECC8_IRQ               21
 #define MX23_INT_RTC_ALARM              22
-#define MX23_INT_UARTAPP_TX_DMA         23
-#define MX23_INT_UARTAPP_INTERNAL       24
-#define MX23_INT_UARTAPP_RX_DMA         25
+#define MX23_INT_AUART1_TX_DMA          23
+#define MX23_INT_AUART1                 24
+#define MX23_INT_AUART1_RX_DMA          25
 #define MX23_INT_I2C_DMA                26
 #define MX23_INT_I2C_ERROR              27
 #define MX23_INT_TIMER0                 28
@@ -135,11 +135,35 @@
 #define MX23_INT_DCP                    54
 #define MX23_INT_BCH                    56
 #define MX23_INT_PXP                    57
-#define MX23_INT_UARTAPP2_TX_DMA        58
-#define MX23_INT_UARTAPP2_INTERNAL      59
-#define MX23_INT_UARTAPP2_RX_DMA        60
+#define MX23_INT_AUART2_TX_DMA          58
+#define MX23_INT_AUART2                 59
+#define MX23_INT_AUART2_RX_DMA          60
 #define MX23_INT_VDAC_DETECT            61
 #define MX23_INT_VDD5V_DROOP            64
 #define MX23_INT_DCDC4P2_BO             65
 
+/*
+ * APBH DMA
+ */
+#define MX23_DMA_SSP1                   1
+#define MX23_DMA_SSP2                   2
+#define MX23_DMA_GPMI0                  4
+#define MX23_DMA_GPMI1                  5
+#define MX23_DMA_GPMI2                  6
+#define MX23_DMA_GPMI3                  7
+
+/*
+ * APBX DMA
+ */
+#define MX23_DMA_ADC                    0
+#define MX23_DMA_DAC                    1
+#define MX23_DMA_SPDIF                  2
+#define MX23_DMA_I2C                    3
+#define MX23_DMA_SAIF0                  4
+#define MX23_DMA_UART0_RX               6
+#define MX23_DMA_UART0_TX               7
+#define MX23_DMA_UART1_RX               8
+#define MX23_DMA_UART1_TX               9
+#define MX23_DMA_SAIF1                  10
+
 #endif /* __MACH_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h
index 0716745267ad..75d86118b76a 100644
--- a/arch/arm/mach-mxs/include/mach/mx28.h
+++ b/arch/arm/mach-mxs/include/mach/mx28.h
@@ -163,10 +163,10 @@
 #define MX28_INT_USB0                   93
 #define MX28_INT_USB1_WAKEUP            94
 #define MX28_INT_USB0_WAKEUP            95
-#define MX28_INT_SSP0                   96
-#define MX28_INT_SSP1                   97
-#define MX28_INT_SSP2                   98
-#define MX28_INT_SSP3                   99
+#define MX28_INT_SSP0_ERROR             96
+#define MX28_INT_SSP1_ERROR             97
+#define MX28_INT_SSP2_ERROR             98
+#define MX28_INT_SSP3_ERROR             99
 #define MX28_INT_ENET_SWI               100
 #define MX28_INT_ENET_MAC0              101
 #define MX28_INT_ENET_MAC1              102
@@ -185,4 +185,41 @@
 #define MX28_INT_GPIO1                  126
 #define MX28_INT_GPIO0                  127
 
+/*
+ * APBH DMA
+ */
+#define MX28_DMA_SSP0                   0
+#define MX28_DMA_SSP1                   1
+#define MX28_DMA_SSP2                   2
+#define MX28_DMA_SSP3                   3
+#define MX28_DMA_GPMI0                  4
+#define MX28_DMA_GPMI1                  5
+#define MX28_DMA_GPMI2                  6
+#define MX28_DMA_GPMI3                  7
+#define MX28_DMA_GPMI4                  8
+#define MX28_DMA_GPMI5                  9
+#define MX28_DMA_GPMI6                  10
+#define MX28_DMA_GPMI7                  11
+#define MX28_DMA_HSADC                  12
+#define MX28_DMA_LCDIF                  13
+
+/*
+ * APBX DMA
+ */
+#define MX28_DMA_AUART4_RX              0
+#define MX28_DMA_AUART4_TX              1
+#define MX28_DMA_SPDIF_TX               2
+#define MX28_DMA_SAIF0                  4
+#define MX28_DMA_SAIF1                  5
+#define MX28_DMA_I2C0                   6
+#define MX28_DMA_I2C1                   7
+#define MX28_DMA_AUART0_RX              8
+#define MX28_DMA_AUART0_TX              9
+#define MX28_DMA_AUART1_RX              10
+#define MX28_DMA_AUART1_TX              11
+#define MX28_DMA_AUART2_RX              12
+#define MX28_DMA_AUART2_TX              13
+#define MX28_DMA_AUART3_RX              14
+#define MX28_DMA_AUART3_TX              15
+
 #endif /* __MACH_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
index f186c08c2911..35a89dd27242 100644
--- a/arch/arm/mach-mxs/include/mach/mxs.h
+++ b/arch/arm/mach-mxs/include/mach/mxs.h
@@ -28,8 +28,13 @@
 /*
  * MXS CPU types
  */
-#define cpu_is_mx23()           (machine_is_mx23evk())
-#define cpu_is_mx28()           (machine_is_mx28evk())
+#define cpu_is_mx23()           (                                       \
+                machine_is_mx23evk() ||                                 \
+                0)
+#define cpu_is_mx28()           (                                       \
+                machine_is_mx28evk() ||                                 \
+                machine_is_tx28() ||                                    \
+                0)
 
 /*
  * IO addresses common to MXS-based
diff --git a/arch/arm/mach-mxs/include/mach/mxsfb.h b/arch/arm/mach-mxs/include/mach/mxsfb.h
new file mode 100644
index 000000000000..e4d79791515e
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/mxsfb.h
@@ -0,0 +1,49 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __MACH_FB_H
+#define __MACH_FB_H
+
+#include <linux/fb.h>
+
+#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */
+#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */
+#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
+#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
+
+#define FB_SYNC_DATA_ENABLE_HIGH_ACT    (1 << 6)
+#define FB_SYNC_DOTCLK_FAILING_ACT      (1 << 7) /* failing/negtive edge sampling */
+
+struct mxsfb_platform_data {
+        struct fb_videomode *mode_list;
+        unsigned mode_count;
+
+        unsigned default_bpp;
+
+        unsigned dotclk_delay;  /* refer manual HW_LCDIF_VDCTRL4 register */
+        unsigned ld_intf_width; /* refer STMLCDIF_* macros */
+
+        unsigned fb_size;       /* Size of the video memory. If zero a
+                                 * default will be used
+                                 */
+        unsigned long fb_phys;  /* physical address for the video memory. If
+                                 * zero the framebuffer memory will be dynamically
+                                 * allocated. If specified,fb_size must also be specified.
+                                 * fb_phys must be unused by Linux.
+                                 */
+};
+
+#endif /* __MACH_FB_H */
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
index a005e76f34f9..f12a1732d8b8 100644
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -63,6 +63,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 mxs_duart_base = MX23_DUART_BASE_ADDR;
                 break;
         case MACH_TYPE_MX28EVK:
+        case MACH_TYPE_TX28:
                 mxs_duart_base = MX28_DUART_BASE_ADDR;
                 break;
         default:
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index aa0640052f58..a66994f0518f 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -26,17 +26,103 @@
 
 #include "devices-mx23.h"
 
+#define MX23EVK_LCD_ENABLE      MXS_GPIO_NR(1, 18)
+#define MX23EVK_BL_ENABLE       MXS_GPIO_NR(1, 28)
+
 static const iomux_cfg_t mx23evk_pads[] __initconst = {
         /* duart */
-        MX23_PAD_PWM0__DUART_RX | MXS_PAD_4MA,
-        MX23_PAD_PWM1__DUART_TX | MXS_PAD_4MA,
+        MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
+        MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
+
+        /* auart */
+        MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
+        MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
+        MX23_PAD_AUART1_CTS__AUART1_CTS | MXS_PAD_CTRL,
+        MX23_PAD_AUART1_RTS__AUART1_RTS | MXS_PAD_CTRL,
+
+        /* mxsfb (lcdif) */
+        MX23_PAD_LCD_D00__LCD_D00 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D01__LCD_D01 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D02__LCD_D02 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D03__LCD_D03 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D04__LCD_D04 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D05__LCD_D05 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D06__LCD_D06 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D07__LCD_D07 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D08__LCD_D08 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D09__LCD_D09 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
+        MX23_PAD_GPMI_D08__LCD_D18 | MXS_PAD_CTRL,
+        MX23_PAD_GPMI_D09__LCD_D19 | MXS_PAD_CTRL,
+        MX23_PAD_GPMI_D10__LCD_D20 | MXS_PAD_CTRL,
+        MX23_PAD_GPMI_D11__LCD_D21 | MXS_PAD_CTRL,
+        MX23_PAD_GPMI_D12__LCD_D22 | MXS_PAD_CTRL,
+        MX23_PAD_GPMI_D13__LCD_D23 | MXS_PAD_CTRL,
+        MX23_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL,
+        MX23_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL,
+        MX23_PAD_LCD_DOTCK__LCD_DOTCK | MXS_PAD_CTRL,
+        MX23_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL,
+        /* LCD panel enable */
+        MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL,
+        /* backlight control */
+        MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL,
+};
+
+/* mxsfb (lcdif) */
+static struct fb_videomode mx23evk_video_modes[] = {
+        {
+                .name           = "Samsung-LMS430HF02",
+                .refresh        = 60,
+                .xres           = 480,
+                .yres           = 272,
+                .pixclock       = 108096, /* picosecond (9.2 MHz) */
+                .left_margin    = 15,
+                .right_margin   = 8,
+                .upper_margin   = 12,
+                .lower_margin   = 4,
+                .hsync_len      = 1,
+                .vsync_len      = 1,
+                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT |
+                                  FB_SYNC_DOTCLK_FAILING_ACT,
+        },
+};
+
+static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = {
+        .mode_list      = mx23evk_video_modes,
+        .mode_count     = ARRAY_SIZE(mx23evk_video_modes),
+        .default_bpp    = 32,
+        .ld_intf_width  = STMLCDIF_24BIT,
 };
 
 static void __init mx23evk_init(void)
 {
+        int ret;
+
         mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
 
         mx23_add_duart();
+        mx23_add_auart0();
+
+        ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
+        if (ret)
+                pr_warn("failed to request gpio lcd-enable: %d\n", ret);
+        else
+                gpio_set_value(MX23EVK_LCD_ENABLE, 1);
+
+        ret = gpio_request_one(MX23EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
+        if (ret)
+                pr_warn("failed to request gpio bl-enable: %d\n", ret);
+        else
+                gpio_set_value(MX23EVK_BL_ENABLE, 1);
+
+        mx23_add_mxsfb(&mx23evk_mxsfb_pdata);
 }
 
 static void __init mx23evk_timer_init(void)
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index 8e2c5975001e..08002d02267a 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -28,54 +28,93 @@
 #include "devices-mx28.h"
 #include "gpio.h"
 
+#define MX28EVK_FLEXCAN_SWITCH  MXS_GPIO_NR(2, 13)
 #define MX28EVK_FEC_PHY_POWER   MXS_GPIO_NR(2, 15)
+#define MX28EVK_BL_ENABLE       MXS_GPIO_NR(3, 18)
+#define MX28EVK_LCD_ENABLE      MXS_GPIO_NR(3, 30)
 #define MX28EVK_FEC_PHY_RESET   MXS_GPIO_NR(4, 13)
 
 static const iomux_cfg_t mx28evk_pads[] __initconst = {
         /* duart */
-        MX28_PAD_PWM0__DUART_RX |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_PWM1__DUART_TX |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
+        MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
 
+        /* auart0 */
+        MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
+        MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
+        MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL,
+        MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL,
+        /* auart3 */
+        MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
+        MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
+        MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
+        MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
+
+#define MXS_PAD_FEC     (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
         /* fec0 */
-        MX28_PAD_ENET0_MDC__ENET0_MDC |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_MDIO__ENET0_MDIO |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_RXD0__ENET0_RXD0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_RXD1__ENET0_RXD1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_TXD0__ENET0_TXD0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_TXD1__ENET0_TXD1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET_CLK__CLKCTRL_ENET |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
+        MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
+        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
+        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
+        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
+        MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
         /* fec1 */
-        MX28_PAD_ENET0_CRS__ENET1_RX_EN |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_RXD2__ENET1_RXD0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_RXD3__ENET1_RXD1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_COL__ENET1_TX_EN |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_TXD2__ENET1_TXD0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_ENET0_TXD3__ENET1_TXD1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
+        MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
+        MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
         /* phy power line */
-        MX28_PAD_SSP1_DATA3__GPIO_2_15 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        MX28_PAD_SSP1_DATA3__GPIO_2_15 | MXS_PAD_CTRL,
         /* phy reset line */
-        MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MXS_PAD_CTRL,
+
+        /* flexcan0 */
+        MX28_PAD_GPMI_RDY2__CAN0_TX,
+        MX28_PAD_GPMI_RDY3__CAN0_RX,
+        /* flexcan1 */
+        MX28_PAD_GPMI_CE2N__CAN1_TX,
+        MX28_PAD_GPMI_CE3N__CAN1_RX,
+        /* transceiver power control */
+        MX28_PAD_SSP1_CMD__GPIO_2_13,
+
+        /* mxsfb (lcdif) */
+        MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
+        MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
+        MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
+        MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
+        MX28_PAD_LCD_CS__LCD_ENABLE | MXS_PAD_CTRL,
+        /* LCD panel enable */
+        MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
+        /* backlight control */
+        MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL,
 };
 
 /* fec */
@@ -119,7 +158,7 @@ static void __init mx28evk_fec_reset(void)
         gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
 }
 
-static struct fec_platform_data mx28_fec_pdata[] = {
+static struct fec_platform_data mx28_fec_pdata[] __initdata = {
         {
                 /* fec0 */
                 .phy = PHY_INTERFACE_MODE_RMII,
@@ -129,15 +168,135 @@ static struct fec_platform_data mx28_fec_pdata[] = {
         },
 };
 
+static int __init mx28evk_fec_get_mac(void)
+{
+        int i;
+        u32 val;
+        const u32 *ocotp = mxs_get_ocotp();
+
+        if (!ocotp)
+                goto error;
+
+        /*
+         * OCOTP only stores the last 4 octets for each mac address,
+         * so hard-code Freescale OUI (00:04:9f) here.
+         */
+        for (i = 0; i < 2; i++) {
+                val = ocotp[i * 4];
+                mx28_fec_pdata[i].mac[0] = 0x00;
+                mx28_fec_pdata[i].mac[1] = 0x04;
+                mx28_fec_pdata[i].mac[2] = 0x9f;
+                mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
+                mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
+                mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
+        }
+
+        return 0;
+
+error:
+        pr_err("%s: timeout when reading fec mac from OCOTP\n", __func__);
+        return -ETIMEDOUT;
+}
+
+/*
+ * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
+ */
+static int flexcan0_en, flexcan1_en;
+
+static void mx28evk_flexcan_switch(void)
+{
+        if (flexcan0_en || flexcan1_en)
+                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
+        else
+                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
+}
+
+static void mx28evk_flexcan0_switch(int enable)
+{
+        flexcan0_en = enable;
+        mx28evk_flexcan_switch();
+}
+
+static void mx28evk_flexcan1_switch(int enable)
+{
+        flexcan1_en = enable;
+        mx28evk_flexcan_switch();
+}
+
+static const struct flexcan_platform_data
+                mx28evk_flexcan_pdata[] __initconst = {
+        {
+                .transceiver_switch = mx28evk_flexcan0_switch,
+        }, {
+                .transceiver_switch = mx28evk_flexcan1_switch,
+        }
+};
+
+/* mxsfb (lcdif) */
+static struct fb_videomode mx28evk_video_modes[] = {
+        {
+                .name           = "Seiko-43WVF1G",
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 480,
+                .pixclock       = 29851, /* picosecond (33.5 MHz) */
+                .left_margin    = 89,
+                .right_margin   = 164,
+                .upper_margin   = 23,
+                .lower_margin   = 10,
+                .hsync_len      = 10,
+                .vsync_len      = 10,
+                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT |
+                                  FB_SYNC_DOTCLK_FAILING_ACT,
+        },
+};
+
+static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = {
+        .mode_list      = mx28evk_video_modes,
+        .mode_count     = ARRAY_SIZE(mx28evk_video_modes),
+        .default_bpp    = 32,
+        .ld_intf_width  = STMLCDIF_24BIT,
+};
+
 static void __init mx28evk_init(void)
 {
+        int ret;
+
         mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
 
         mx28_add_duart();
+        mx28_add_auart0();
+        mx28_add_auart3();
+
+        if (mx28evk_fec_get_mac())
+                pr_warn("%s: failed on fec mac setup\n", __func__);
 
         mx28evk_fec_reset();
         mx28_add_fec(0, &mx28_fec_pdata[0]);
         mx28_add_fec(1, &mx28_fec_pdata[1]);
+
+        ret = gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
+                                "flexcan-switch");
+        if (ret) {
+                pr_err("failed to request gpio flexcan-switch: %d\n", ret);
+        } else {
+                mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]);
+                mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
+        }
+
+        ret = gpio_request_one(MX28EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
+        if (ret)
+                pr_warn("failed to request gpio lcd-enable: %d\n", ret);
+        else
+                gpio_set_value(MX28EVK_LCD_ENABLE, 1);
+
+        ret = gpio_request_one(MX28EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
+        if (ret)
+                pr_warn("failed to request gpio bl-enable: %d\n", ret);
+        else
+                gpio_set_value(MX28EVK_BL_ENABLE, 1);
+
+        mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
 }
 
 static void __init mx28evk_timer_init(void)
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
new file mode 100644
index 000000000000..b65e3719cbc4
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-tx28.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2010 <LW@KARO-electronics.de>
+ *
+ * based on: mach-mx28_evk.c
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation
+ */
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/i2c.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/common.h>
+#include <mach/iomux-mx28.h>
+
+#include "devices-mx28.h"
+#include "module-tx28.h"
+
+#define TX28_STK5_GPIO_LED              MXS_GPIO_NR(4, 10)
+
+static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = {
+        /* LED */
+        MX28_PAD_ENET0_RXD3__GPIO_4_10 |
+                MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL,
+
+        /* framebuffer */
+#define LCD_MODE (MXS_PAD_3V3 | MXS_PAD_4MA)
+        MX28_PAD_LCD_D00__LCD_D0 | LCD_MODE,
+        MX28_PAD_LCD_D01__LCD_D1 | LCD_MODE,
+        MX28_PAD_LCD_D02__LCD_D2 | LCD_MODE,
+        MX28_PAD_LCD_D03__LCD_D3 | LCD_MODE,
+        MX28_PAD_LCD_D04__LCD_D4 | LCD_MODE,
+        MX28_PAD_LCD_D05__LCD_D5 | LCD_MODE,
+        MX28_PAD_LCD_D06__LCD_D6 | LCD_MODE,
+        MX28_PAD_LCD_D07__LCD_D7 | LCD_MODE,
+        MX28_PAD_LCD_D08__LCD_D8 | LCD_MODE,
+        MX28_PAD_LCD_D09__LCD_D9 | LCD_MODE,
+        MX28_PAD_LCD_D10__LCD_D10 | LCD_MODE,
+        MX28_PAD_LCD_D11__LCD_D11 | LCD_MODE,
+        MX28_PAD_LCD_D12__LCD_D12 | LCD_MODE,
+        MX28_PAD_LCD_D13__LCD_D13 | LCD_MODE,
+        MX28_PAD_LCD_D14__LCD_D14 | LCD_MODE,
+        MX28_PAD_LCD_D15__LCD_D15 | LCD_MODE,
+        MX28_PAD_LCD_D16__LCD_D16 | LCD_MODE,
+        MX28_PAD_LCD_D17__LCD_D17 | LCD_MODE,
+        MX28_PAD_LCD_D18__LCD_D18 | LCD_MODE,
+        MX28_PAD_LCD_D19__LCD_D19 | LCD_MODE,
+        MX28_PAD_LCD_D20__LCD_D20 | LCD_MODE,
+        MX28_PAD_LCD_D21__LCD_D21 | LCD_MODE,
+        MX28_PAD_LCD_D22__LCD_D22 | LCD_MODE,
+        MX28_PAD_LCD_D23__LCD_D23 | LCD_MODE,
+        MX28_PAD_LCD_RD_E__LCD_VSYNC | LCD_MODE,
+        MX28_PAD_LCD_WR_RWN__LCD_HSYNC | LCD_MODE,
+        MX28_PAD_LCD_RS__LCD_DOTCLK | LCD_MODE,
+        MX28_PAD_LCD_CS__LCD_CS | LCD_MODE,
+        MX28_PAD_LCD_VSYNC__LCD_VSYNC | LCD_MODE,
+        MX28_PAD_LCD_HSYNC__LCD_HSYNC | LCD_MODE,
+        MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | LCD_MODE,
+        MX28_PAD_LCD_ENABLE__GPIO_1_31 | LCD_MODE,
+        MX28_PAD_LCD_RESET__GPIO_3_30 | LCD_MODE,
+        MX28_PAD_PWM0__PWM_0 | LCD_MODE,
+
+        /* UART1 */
+        MX28_PAD_AUART0_CTS__DUART_RX,
+        MX28_PAD_AUART0_RTS__DUART_TX,
+        MX28_PAD_AUART0_TX__DUART_RTS,
+        MX28_PAD_AUART0_RX__DUART_CTS,
+
+        /* UART2 */
+        MX28_PAD_AUART1_RX__AUART1_RX,
+        MX28_PAD_AUART1_TX__AUART1_TX,
+        MX28_PAD_AUART1_RTS__AUART1_RTS,
+        MX28_PAD_AUART1_CTS__AUART1_CTS,
+
+        /* CAN */
+        MX28_PAD_GPMI_RDY2__CAN0_TX,
+        MX28_PAD_GPMI_RDY3__CAN0_RX,
+
+        /* I2C */
+        MX28_PAD_I2C0_SCL__I2C0_SCL,
+        MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+        /* TSC2007 */
+        MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP,
+
+        /* MMC0 */
+        MX28_PAD_SSP0_DATA0__SSP0_D0 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA1__SSP0_D1 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA2__SSP0_D2 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA3__SSP0_D3 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA4__SSP0_D4 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA5__SSP0_D5 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA6__SSP0_D6 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA7__SSP0_D7 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_CMD__SSP0_CMD |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        MX28_PAD_SSP0_SCK__SSP0_SCK |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+};
+
+static struct gpio_led tx28_stk5v3_leds[] = {
+        {
+                .name = "GPIO-LED",
+                .default_trigger = "heartbeat",
+                .gpio = TX28_STK5_GPIO_LED,
+        },
+};
+
+static const struct gpio_led_platform_data tx28_stk5v3_led_data __initconst = {
+        .leds = tx28_stk5v3_leds,
+        .num_leds = ARRAY_SIZE(tx28_stk5v3_leds),
+};
+
+static struct spi_board_info tx28_spi_board_info[] = {
+        {
+                .modalias = "spidev",
+                .max_speed_hz = 20000000,
+                .bus_num = 0,
+                .chip_select = 1,
+                .controller_data = (void *)SPI_GPIO_NO_CHIPSELECT,
+                .mode = SPI_MODE_0,
+        },
+};
+
+static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = {
+        {
+                I2C_BOARD_INFO("ds1339", 0x68),
+        },
+};
+
+static void __init tx28_stk5v3_init(void)
+{
+        mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
+                        ARRAY_SIZE(tx28_stk5v3_pads));
+
+        mx28_add_duart(); /* UART1 */
+        mx28_add_auart(1); /* UART2 */
+
+        tx28_add_fec0();
+        /* spi via ssp will be added when available */
+        spi_register_board_info(tx28_spi_board_info,
+                        ARRAY_SIZE(tx28_spi_board_info));
+        mxs_add_platform_device("leds-gpio", 0, NULL, 0,
+                        &tx28_stk5v3_led_data, sizeof(tx28_stk5v3_led_data));
+        mx28_add_mxs_i2c(0);
+        i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo,
+                        ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo));
+}
+
+static void __init tx28_timer_init(void)
+{
+        mx28_clocks_init();
+}
+
+static struct sys_timer tx28_timer = {
+        .init = tx28_timer_init,
+};
+
+MACHINE_START(TX28, "Ka-Ro electronics TX28 module")
+        .map_io = mx28_map_io,
+        .init_irq = mx28_init_irq,
+        .init_machine = tx28_stk5v3_init,
+        .timer = &tx28_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c
new file mode 100644
index 000000000000..fa0b154da67b
--- /dev/null
+++ b/arch/arm/mach-mxs/module-tx28.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2010 <LW@KARO-electronics.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/fec.h>
+#include <linux/gpio.h>
+
+#include <mach/iomux-mx28.h>
+#include "../devices-mx28.h"
+
+#include "module-tx28.h"
+
+#define TX28_FEC_PHY_POWER      MXS_GPIO_NR(3, 29)
+#define TX28_FEC_PHY_RESET      MXS_GPIO_NR(4, 13)
+
+static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = {
+        /* PHY POWER */
+        MX28_PAD_PWM4__GPIO_3_29 |
+                MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
+        /* PHY RESET */
+        MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
+                MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
+        /* Mode strap pins 0-2 */
+        MX28_PAD_ENET0_RXD0__GPIO_4_3 |
+                MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
+        MX28_PAD_ENET0_RXD1__GPIO_4_4 |
+                MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
+        MX28_PAD_ENET0_RX_EN__GPIO_4_2 |
+                MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
+        /* nINT */
+        MX28_PAD_ENET0_TX_CLK__GPIO_4_5 |
+                MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
+
+        MX28_PAD_ENET0_MDC__GPIO_4_0,
+        MX28_PAD_ENET0_MDIO__GPIO_4_1,
+        MX28_PAD_ENET0_TX_EN__GPIO_4_6,
+        MX28_PAD_ENET0_TXD0__GPIO_4_7,
+        MX28_PAD_ENET0_TXD1__GPIO_4_8,
+        MX28_PAD_ENET_CLK__GPIO_4_16,
+};
+
+#define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3)
+static const iomux_cfg_t tx28_fec_pads[] __initconst = {
+        MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE,
+        MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE,
+        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE,
+        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | FEC_MODE,
+        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | FEC_MODE,
+        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | FEC_MODE,
+        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | FEC_MODE,
+        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | FEC_MODE,
+        MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE,
+};
+
+static const struct fec_platform_data tx28_fec_data __initconst = {
+        .phy = PHY_INTERFACE_MODE_RMII,
+};
+
+int __init tx28_add_fec0(void)
+{
+        int i, ret;
+
+        pr_debug("%s: Switching FEC PHY power off\n", __func__);
+        ret = mxs_iomux_setup_multiple_pads(tx28_fec_gpio_pads,
+                        ARRAY_SIZE(tx28_fec_gpio_pads));
+        for (i = 0; i < ARRAY_SIZE(tx28_fec_gpio_pads); i++) {
+                unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
+                        PAD_PIN(tx28_fec_gpio_pads[i]));
+
+                ret = gpio_request(gpio, "FEC");
+                if (ret) {
+                        pr_err("Failed to request GPIO_%d_%d: %d\n",
+                                PAD_BANK(tx28_fec_gpio_pads[i]),
+                                PAD_PIN(tx28_fec_gpio_pads[i]), ret);
+                        goto free_gpios;
+                }
+                ret = gpio_direction_output(gpio, 0);
+                if (ret) {
+                        pr_err("Failed to set direction of GPIO_%d_%d to output: %d\n",
+                                        gpio / 32 + 1, gpio % 32, ret);
+                        goto free_gpios;
+                }
+        }
+
+        /* Power up fec phy */
+        pr_debug("%s: Switching FEC PHY power on\n", __func__);
+        ret = gpio_direction_output(TX28_FEC_PHY_POWER, 1);
+        if (ret) {
+                pr_err("Failed to power on PHY: %d\n", ret);
+                goto free_gpios;
+        }
+        mdelay(26); /* 25ms according to data sheet */
+
+        /* nINT */
+        gpio_direction_input(MXS_GPIO_NR(4, 5));
+        /* Mode strap pins */
+        gpio_direction_output(MXS_GPIO_NR(4, 2), 1);
+        gpio_direction_output(MXS_GPIO_NR(4, 3), 1);
+        gpio_direction_output(MXS_GPIO_NR(4, 4), 1);
+
+        udelay(100); /* minimum assertion time for nRST */
+
+        pr_debug("%s: Deasserting FEC PHY RESET\n", __func__);
+        gpio_set_value(TX28_FEC_PHY_RESET, 1);
+
+        ret = mxs_iomux_setup_multiple_pads(tx28_fec_pads,
+                        ARRAY_SIZE(tx28_fec_pads));
+        if (ret) {
+                pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n",
+                                __func__, ret);
+                goto free_gpios;
+        }
+        pr_debug("%s: Registering FEC device\n", __func__);
+        mx28_add_fec(0, &tx28_fec_data);
+        return 0;
+
+free_gpios:
+        while (--i >= 0) {
+                unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
+                        PAD_PIN(tx28_fec_gpio_pads[i]));
+
+                gpio_free(gpio);
+        }
+
+        return ret;
+}
diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h
new file mode 100644
index 000000000000..df9e1b6e81bf
--- /dev/null
+++ b/arch/arm/mach-mxs/module-tx28.h
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ *   Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+int __init tx28_add_fec0(void);
diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c
new file mode 100644
index 000000000000..65157a35dbba
--- /dev/null
+++ b/arch/arm/mach-mxs/ocotp.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/mutex.h>
+
+#include <mach/mxs.h>
+
+#define OCOTP_WORD_OFFSET               0x20
+#define OCOTP_WORD_COUNT                0x20
+
+#define BM_OCOTP_CTRL_BUSY              (1 << 8)
+#define BM_OCOTP_CTRL_ERROR             (1 << 9)
+#define BM_OCOTP_CTRL_RD_BANK_OPEN      (1 << 12)
+
+static DEFINE_MUTEX(ocotp_mutex);
+static u32 ocotp_words[OCOTP_WORD_COUNT];
+
+const u32 *mxs_get_ocotp(void)
+{
+        void __iomem *ocotp_base = MXS_IO_ADDRESS(MXS_OCOTP_BASE_ADDR);
+        int timeout = 0x400;
+        size_t i;
+        static int once = 0;
+
+        if (once)
+                return ocotp_words;
+
+        mutex_lock(&ocotp_mutex);
+
+        /*
+         * clk_enable(hbus_clk) for ocotp can be skipped
+         * as it must be on when system is running.
+         */
+
+        /* try to clear ERROR bit */
+        __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
+
+        /* check both BUSY and ERROR cleared */
+        while ((__raw_readl(ocotp_base) &
+                (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
+                cpu_relax();
+
+        if (unlikely(!timeout))
+                goto error_unlock;
+
+        /* open OCOTP banks for read */
+        __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
+
+        /* approximately wait 32 hclk cycles */
+        udelay(1);
+
+        /* poll BUSY bit becoming cleared */
+        timeout = 0x400;
+        while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
+                cpu_relax();
+
+        if (unlikely(!timeout))
+                goto error_unlock;
+
+        for (i = 0; i < OCOTP_WORD_COUNT; i++)
+                ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
+                                                i * 0x10);
+
+        /* close banks for power saving */
+        __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
+
+        once = 1;
+
+        mutex_unlock(&ocotp_mutex);
+
+        return ocotp_words;
+
+error_unlock:
+        mutex_unlock(&ocotp_mutex);
+        pr_err("%s: timeout in reading OCOTP\n", __func__);
+        return NULL;
+}
diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c
new file mode 100644
index 000000000000..fb042da29bda
--- /dev/null
+++ b/arch/arm/mach-mxs/pm.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+#include <mach/system.h>
+
+static int mxs_suspend_enter(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_MEM:
+                arch_idle();
+                break;
+
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static struct platform_suspend_ops mxs_suspend_ops = {
+        .enter = mxs_suspend_enter,
+        .valid = suspend_valid_only_mem,
+};
+
+static int __init mxs_pm_init(void)
+{
+        suspend_set_ops(&mxs_suspend_ops);
+        return 0;
+}
+device_initcall(mxs_pm_init);
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
index dbc04747b691..0ea5c9d0e2b2 100644
--- a/arch/arm/mach-mxs/regs-clkctrl-mx23.h
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
@@ -33,10 +33,6 @@
 #define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008)
 #define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c)
 
-#define BP_CLKCTRL_PLLCTRL0_RSRVD6      30
-#define BM_CLKCTRL_PLLCTRL0_RSRVD6      0xC0000000
-#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \
-                (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6)
 #define BP_CLKCTRL_PLLCTRL0_LFR_SEL     28
 #define BM_CLKCTRL_PLLCTRL0_LFR_SEL     0x30000000
 #define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v)  \
@@ -45,10 +41,6 @@
 #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2   0x1
 #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05  0x2
 #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLLCTRL0_RSRVD5      26
-#define BM_CLKCTRL_PLLCTRL0_RSRVD5      0x0C000000
-#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v)  \
-                (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5)
 #define BP_CLKCTRL_PLLCTRL0_CP_SEL      24
 #define BM_CLKCTRL_PLLCTRL0_CP_SEL      0x03000000
 #define BF_CLKCTRL_PLLCTRL0_CP_SEL(v)  \
@@ -57,10 +49,6 @@
 #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2   0x1
 #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05  0x2
 #define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLLCTRL0_RSRVD4      22
-#define BM_CLKCTRL_PLLCTRL0_RSRVD4      0x00C00000
-#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v)  \
-                (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4)
 #define BP_CLKCTRL_PLLCTRL0_DIV_SEL     20
 #define BM_CLKCTRL_PLLCTRL0_DIV_SEL     0x00300000
 #define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v)  \
@@ -69,23 +57,13 @@
 #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER     0x1
 #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST    0x2
 #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_PLLCTRL0_RSRVD3      0x00080000
 #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
-#define BM_CLKCTRL_PLLCTRL0_RSRVD2      0x00020000
 #define BM_CLKCTRL_PLLCTRL0_POWER       0x00010000
-#define BP_CLKCTRL_PLLCTRL0_RSRVD1      0
-#define BM_CLKCTRL_PLLCTRL0_RSRVD1      0x0000FFFF
-#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v)  \
-                (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1)
 
 #define HW_CLKCTRL_PLLCTRL1     (0x00000010)
 
 #define BM_CLKCTRL_PLLCTRL1_LOCK        0x80000000
 #define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK  0x40000000
-#define BP_CLKCTRL_PLLCTRL1_RSRVD1      16
-#define BM_CLKCTRL_PLLCTRL1_RSRVD1      0x3FFF0000
-#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v)  \
-                (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1)
 #define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT  0
 #define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT  0x0000FFFF
 #define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)  \
@@ -96,29 +74,15 @@
 #define HW_CLKCTRL_CPU_CLR      (0x00000028)
 #define HW_CLKCTRL_CPU_TOG      (0x0000002c)
 
-#define BP_CLKCTRL_CPU_RSRVD5   30
-#define BM_CLKCTRL_CPU_RSRVD5   0xC0000000
-#define BF_CLKCTRL_CPU_RSRVD5(v) \
-                (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
 #define BM_CLKCTRL_CPU_BUSY_REF_XTAL    0x20000000
 #define BM_CLKCTRL_CPU_BUSY_REF_CPU     0x10000000
-#define BM_CLKCTRL_CPU_RSRVD4   0x08000000
 #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
 #define BP_CLKCTRL_CPU_DIV_XTAL 16
 #define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
 #define BF_CLKCTRL_CPU_DIV_XTAL(v)  \
                 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
-#define BP_CLKCTRL_CPU_RSRVD3   13
-#define BM_CLKCTRL_CPU_RSRVD3   0x0000E000
-#define BF_CLKCTRL_CPU_RSRVD3(v)  \
-                (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
 #define BM_CLKCTRL_CPU_INTERRUPT_WAIT   0x00001000
-#define BM_CLKCTRL_CPU_RSRVD2   0x00000800
 #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN  0x00000400
-#define BP_CLKCTRL_CPU_RSRVD1   6
-#define BM_CLKCTRL_CPU_RSRVD1   0x000003C0
-#define BF_CLKCTRL_CPU_RSRVD1(v)  \
-                (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
 #define BP_CLKCTRL_CPU_DIV_CPU  0
 #define BM_CLKCTRL_CPU_DIV_CPU  0x0000003F
 #define BF_CLKCTRL_CPU_DIV_CPU(v)  \
@@ -129,10 +93,6 @@
 #define HW_CLKCTRL_HBUS_CLR     (0x00000038)
 #define HW_CLKCTRL_HBUS_TOG     (0x0000003c)
 
-#define BP_CLKCTRL_HBUS_RSRVD4  30
-#define BM_CLKCTRL_HBUS_RSRVD4  0xC0000000
-#define BF_CLKCTRL_HBUS_RSRVD4(v) \
-                (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4)
 #define BM_CLKCTRL_HBUS_BUSY    0x20000000
 #define BM_CLKCTRL_HBUS_DCP_AS_ENABLE   0x10000000
 #define BM_CLKCTRL_HBUS_PXP_AS_ENABLE   0x08000000
@@ -143,7 +103,6 @@
 #define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE      0x00400000
 #define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE     0x00200000
 #define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE  0x00100000
-#define BM_CLKCTRL_HBUS_RSRVD2  0x00080000
 #define BP_CLKCTRL_HBUS_SLOW_DIV        16
 #define BM_CLKCTRL_HBUS_SLOW_DIV        0x00070000
 #define BF_CLKCTRL_HBUS_SLOW_DIV(v)  \
@@ -154,10 +113,6 @@
 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8  0x3
 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
-#define BP_CLKCTRL_HBUS_RSRVD1  6
-#define BM_CLKCTRL_HBUS_RSRVD1  0x0000FFC0
-#define BF_CLKCTRL_HBUS_RSRVD1(v)  \
-                (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
 #define BM_CLKCTRL_HBUS_DIV_FRAC_EN     0x00000020
 #define BP_CLKCTRL_HBUS_DIV     0
 #define BM_CLKCTRL_HBUS_DIV     0x0000001F
@@ -167,10 +122,6 @@
 #define HW_CLKCTRL_XBUS (0x00000040)
 
 #define BM_CLKCTRL_XBUS_BUSY    0x80000000
-#define BP_CLKCTRL_XBUS_RSRVD1  11
-#define BM_CLKCTRL_XBUS_RSRVD1  0x7FFFF800
-#define BF_CLKCTRL_XBUS_RSRVD1(v)  \
-                (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1)
 #define BM_CLKCTRL_XBUS_DIV_FRAC_EN     0x00000400
 #define BP_CLKCTRL_XBUS_DIV     0
 #define BM_CLKCTRL_XBUS_DIV     0x000003FF
@@ -192,10 +143,6 @@
 #define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      0x08000000
 #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      26
 #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      0x04000000
-#define BP_CLKCTRL_XTAL_RSRVD1  2
-#define BM_CLKCTRL_XTAL_RSRVD1  0x03FFFFFC
-#define BF_CLKCTRL_XTAL_RSRVD1(v)  \
-                (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
 #define BP_CLKCTRL_XTAL_DIV_UART        0
 #define BM_CLKCTRL_XTAL_DIV_UART        0x00000003
 #define BF_CLKCTRL_XTAL_DIV_UART(v)  \
@@ -205,12 +152,7 @@
 
 #define BP_CLKCTRL_PIX_CLKGATE  31
 #define BM_CLKCTRL_PIX_CLKGATE  0x80000000
-#define BM_CLKCTRL_PIX_RSRVD2   0x40000000
 #define BM_CLKCTRL_PIX_BUSY     0x20000000
-#define BP_CLKCTRL_PIX_RSRVD1   13
-#define BM_CLKCTRL_PIX_RSRVD1   0x1FFFE000
-#define BF_CLKCTRL_PIX_RSRVD1(v)  \
-                (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1)
 #define BM_CLKCTRL_PIX_DIV_FRAC_EN      0x00001000
 #define BP_CLKCTRL_PIX_DIV      0
 #define BM_CLKCTRL_PIX_DIV      0x00000FFF
@@ -221,12 +163,7 @@
 
 #define BP_CLKCTRL_SSP_CLKGATE  31
 #define BM_CLKCTRL_SSP_CLKGATE  0x80000000
-#define BM_CLKCTRL_SSP_RSRVD2   0x40000000
 #define BM_CLKCTRL_SSP_BUSY     0x20000000
-#define BP_CLKCTRL_SSP_RSRVD1   10
-#define BM_CLKCTRL_SSP_RSRVD1   0x1FFFFC00
-#define BF_CLKCTRL_SSP_RSRVD1(v)  \
-                (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1)
 #define BM_CLKCTRL_SSP_DIV_FRAC_EN      0x00000200
 #define BP_CLKCTRL_SSP_DIV      0
 #define BM_CLKCTRL_SSP_DIV      0x000001FF
@@ -237,12 +174,7 @@
 
 #define BP_CLKCTRL_GPMI_CLKGATE 31
 #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
-#define BM_CLKCTRL_GPMI_RSRVD2  0x40000000
 #define BM_CLKCTRL_GPMI_BUSY    0x20000000
-#define BP_CLKCTRL_GPMI_RSRVD1  11
-#define BM_CLKCTRL_GPMI_RSRVD1  0x1FFFF800
-#define BF_CLKCTRL_GPMI_RSRVD1(v)  \
-                (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
 #define BM_CLKCTRL_GPMI_DIV_FRAC_EN     0x00000400
 #define BP_CLKCTRL_GPMI_DIV     0
 #define BM_CLKCTRL_GPMI_DIV     0x000003FF
@@ -252,10 +184,6 @@
 #define HW_CLKCTRL_SPDIF        (0x00000090)
 
 #define BM_CLKCTRL_SPDIF_CLKGATE        0x80000000
-#define BP_CLKCTRL_SPDIF_RSRVD  0
-#define BM_CLKCTRL_SPDIF_RSRVD  0x7FFFFFFF
-#define BF_CLKCTRL_SPDIF_RSRVD(v)  \
-                (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
 
 #define HW_CLKCTRL_EMI  (0x000000a0)
 
@@ -266,24 +194,12 @@
 #define BM_CLKCTRL_EMI_BUSY_REF_EMI     0x10000000
 #define BM_CLKCTRL_EMI_BUSY_REF_CPU     0x08000000
 #define BM_CLKCTRL_EMI_BUSY_SYNC_MODE   0x04000000
-#define BP_CLKCTRL_EMI_RSRVD3   18
-#define BM_CLKCTRL_EMI_RSRVD3   0x03FC0000
-#define BF_CLKCTRL_EMI_RSRVD3(v)  \
-                (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
 #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC  0x00020000
 #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE        0x00010000
-#define BP_CLKCTRL_EMI_RSRVD2   12
-#define BM_CLKCTRL_EMI_RSRVD2   0x0000F000
-#define BF_CLKCTRL_EMI_RSRVD2(v)  \
-                (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
 #define BP_CLKCTRL_EMI_DIV_XTAL 8
 #define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
 #define BF_CLKCTRL_EMI_DIV_XTAL(v)  \
                 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
-#define BP_CLKCTRL_EMI_RSRVD1   6
-#define BM_CLKCTRL_EMI_RSRVD1   0x000000C0
-#define BF_CLKCTRL_EMI_RSRVD1(v)  \
-                (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
 #define BP_CLKCTRL_EMI_DIV_EMI  0
 #define BM_CLKCTRL_EMI_DIV_EMI  0x0000003F
 #define BF_CLKCTRL_EMI_DIV_EMI(v)  \
@@ -292,22 +208,13 @@
 #define HW_CLKCTRL_IR   (0x000000b0)
 
 #define BM_CLKCTRL_IR_CLKGATE   0x80000000
-#define BM_CLKCTRL_IR_RSRVD3    0x40000000
 #define BM_CLKCTRL_IR_AUTO_DIV  0x20000000
 #define BM_CLKCTRL_IR_IR_BUSY   0x10000000
 #define BM_CLKCTRL_IR_IROV_BUSY 0x08000000
-#define BP_CLKCTRL_IR_RSRVD2    25
-#define BM_CLKCTRL_IR_RSRVD2    0x06000000
-#define BF_CLKCTRL_IR_RSRVD2(v)  \
-                (((v) << 25) & BM_CLKCTRL_IR_RSRVD2)
 #define BP_CLKCTRL_IR_IROV_DIV  16
 #define BM_CLKCTRL_IR_IROV_DIV  0x01FF0000
 #define BF_CLKCTRL_IR_IROV_DIV(v)  \
                 (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
-#define BP_CLKCTRL_IR_RSRVD1    10
-#define BM_CLKCTRL_IR_RSRVD1    0x0000FC00
-#define BF_CLKCTRL_IR_RSRVD1(v)  \
-                (((v) << 10) & BM_CLKCTRL_IR_RSRVD1)
 #define BP_CLKCTRL_IR_IR_DIV    0
 #define BM_CLKCTRL_IR_IR_DIV    0x000003FF
 #define BF_CLKCTRL_IR_IR_DIV(v)  \
@@ -316,12 +223,7 @@
 #define HW_CLKCTRL_SAIF (0x000000c0)
 
 #define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
-#define BM_CLKCTRL_SAIF_RSRVD2  0x40000000
 #define BM_CLKCTRL_SAIF_BUSY    0x20000000
-#define BP_CLKCTRL_SAIF_RSRVD1  17
-#define BM_CLKCTRL_SAIF_RSRVD1  0x1FFE0000
-#define BF_CLKCTRL_SAIF_RSRVD1(v)  \
-                (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1)
 #define BM_CLKCTRL_SAIF_DIV_FRAC_EN     0x00010000
 #define BP_CLKCTRL_SAIF_DIV     0
 #define BM_CLKCTRL_SAIF_DIV     0x0000FFFF
@@ -332,20 +234,11 @@
 
 #define BM_CLKCTRL_TV_CLK_TV108M_GATE   0x80000000
 #define BM_CLKCTRL_TV_CLK_TV_GATE       0x40000000
-#define BP_CLKCTRL_TV_RSRVD     0
-#define BM_CLKCTRL_TV_RSRVD     0x3FFFFFFF
-#define BF_CLKCTRL_TV_RSRVD(v)  \
-                (((v) << 0) & BM_CLKCTRL_TV_RSRVD)
 
 #define HW_CLKCTRL_ETM  (0x000000e0)
 
 #define BM_CLKCTRL_ETM_CLKGATE  0x80000000
-#define BM_CLKCTRL_ETM_RSRVD2   0x40000000
 #define BM_CLKCTRL_ETM_BUSY     0x20000000
-#define BP_CLKCTRL_ETM_RSRVD1   7
-#define BM_CLKCTRL_ETM_RSRVD1   0x1FFFFF80
-#define BF_CLKCTRL_ETM_RSRVD1(v)  \
-                (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1)
 #define BM_CLKCTRL_ETM_DIV_FRAC_EN      0x00000040
 #define BP_CLKCTRL_ETM_DIV      0
 #define BM_CLKCTRL_ETM_DIV      0x0000003F
@@ -393,36 +286,23 @@
 
 #define BM_CLKCTRL_FRAC1_CLKGATEVID     0x80000000
 #define BM_CLKCTRL_FRAC1_VID_STABLE     0x40000000
-#define BP_CLKCTRL_FRAC1_RSRVD1 0
-#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF
-#define BF_CLKCTRL_FRAC1_RSRVD1(v)  \
-                (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1)
 
 #define HW_CLKCTRL_CLKSEQ       (0x00000110)
 #define HW_CLKCTRL_CLKSEQ_SET   (0x00000114)
 #define HW_CLKCTRL_CLKSEQ_CLR   (0x00000118)
 #define HW_CLKCTRL_CLKSEQ_TOG   (0x0000011c)
 
-#define BP_CLKCTRL_CLKSEQ_RSRVD1        9
-#define BM_CLKCTRL_CLKSEQ_RSRVD1        0xFFFFFE00
-#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
-                (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1)
 #define BM_CLKCTRL_CLKSEQ_BYPASS_ETM    0x00000100
 #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU    0x00000080
 #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI    0x00000040
 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP    0x00000020
 #define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI   0x00000010
 #define BM_CLKCTRL_CLKSEQ_BYPASS_IR     0x00000008
-#define BM_CLKCTRL_CLKSEQ_RSRVD0        0x00000004
 #define BM_CLKCTRL_CLKSEQ_BYPASS_PIX    0x00000002
 #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF   0x00000001
 
 #define HW_CLKCTRL_RESET        (0x00000120)
 
-#define BP_CLKCTRL_RESET_RSRVD  2
-#define BM_CLKCTRL_RESET_RSRVD  0xFFFFFFFC
-#define BF_CLKCTRL_RESET_RSRVD(v) \
-                (((v) << 2) & BM_CLKCTRL_RESET_RSRVD)
 #define BM_CLKCTRL_RESET_CHIP   0x00000002
 #define BM_CLKCTRL_RESET_DIG    0x00000001
 
@@ -432,10 +312,6 @@
 #define BM_CLKCTRL_STATUS_CPU_LIMIT     0xC0000000
 #define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
                 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
-#define BP_CLKCTRL_STATUS_RSRVD 0
-#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
-#define BF_CLKCTRL_STATUS_RSRVD(v)  \
-                (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
 
 #define HW_CLKCTRL_VERSION      (0x00000140)
 
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
index 661df18755f7..7d1b061d7943 100644
--- a/arch/arm/mach-mxs/regs-clkctrl-mx28.h
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
@@ -31,10 +31,6 @@
 #define HW_CLKCTRL_PLL0CTRL0_CLR        (0x00000008)
 #define HW_CLKCTRL_PLL0CTRL0_TOG        (0x0000000c)
 
-#define BP_CLKCTRL_PLL0CTRL0_RSRVD6     30
-#define BM_CLKCTRL_PLL0CTRL0_RSRVD6     0xC0000000
-#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \
-                (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6)
 #define BP_CLKCTRL_PLL0CTRL0_LFR_SEL    28
 #define BM_CLKCTRL_PLL0CTRL0_LFR_SEL    0x30000000
 #define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v)  \
@@ -43,10 +39,6 @@
 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2   0x1
 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05  0x2
 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL0CTRL0_RSRVD5     26
-#define BM_CLKCTRL_PLL0CTRL0_RSRVD5     0x0C000000
-#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v)  \
-                (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5)
 #define BP_CLKCTRL_PLL0CTRL0_CP_SEL     24
 #define BM_CLKCTRL_PLL0CTRL0_CP_SEL     0x03000000
 #define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v)  \
@@ -55,10 +47,6 @@
 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2   0x1
 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05  0x2
 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL0CTRL0_RSRVD4     22
-#define BM_CLKCTRL_PLL0CTRL0_RSRVD4     0x00C00000
-#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v)  \
-                (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4)
 #define BP_CLKCTRL_PLL0CTRL0_DIV_SEL    20
 #define BM_CLKCTRL_PLL0CTRL0_DIV_SEL    0x00300000
 #define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v)  \
@@ -67,22 +55,13 @@
 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER     0x1
 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST    0x2
 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_PLL0CTRL0_RSRVD3     0x00080000
 #define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS        0x00040000
 #define BM_CLKCTRL_PLL0CTRL0_POWER      0x00020000
-#define BP_CLKCTRL_PLL0CTRL0_RSRVD1     0
-#define BM_CLKCTRL_PLL0CTRL0_RSRVD1     0x0001FFFF
-#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v)  \
-                (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1)
 
 #define HW_CLKCTRL_PLL0CTRL1    (0x00000010)
 
 #define BM_CLKCTRL_PLL0CTRL1_LOCK       0x80000000
 #define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000
-#define BP_CLKCTRL_PLL0CTRL1_RSRVD1     16
-#define BM_CLKCTRL_PLL0CTRL1_RSRVD1     0x3FFF0000
-#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v)  \
-                (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1)
 #define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0
 #define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF
 #define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v)  \
@@ -94,7 +73,6 @@
 #define HW_CLKCTRL_PLL1CTRL0_TOG        (0x0000002c)
 
 #define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000
-#define BM_CLKCTRL_PLL1CTRL0_RSRVD6     0x40000000
 #define BP_CLKCTRL_PLL1CTRL0_LFR_SEL    28
 #define BM_CLKCTRL_PLL1CTRL0_LFR_SEL    0x30000000
 #define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v)  \
@@ -103,10 +81,6 @@
 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2   0x1
 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05  0x2
 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL1CTRL0_RSRVD5     26
-#define BM_CLKCTRL_PLL1CTRL0_RSRVD5     0x0C000000
-#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v)  \
-                (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5)
 #define BP_CLKCTRL_PLL1CTRL0_CP_SEL     24
 #define BM_CLKCTRL_PLL1CTRL0_CP_SEL     0x03000000
 #define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v)  \
@@ -115,10 +89,6 @@
 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2   0x1
 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05  0x2
 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL1CTRL0_RSRVD4     22
-#define BM_CLKCTRL_PLL1CTRL0_RSRVD4     0x00C00000
-#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v)  \
-                (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4)
 #define BP_CLKCTRL_PLL1CTRL0_DIV_SEL    20
 #define BM_CLKCTRL_PLL1CTRL0_DIV_SEL    0x00300000
 #define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v)  \
@@ -127,22 +97,13 @@
 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER     0x1
 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST    0x2
 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_PLL1CTRL0_RSRVD3     0x00080000
 #define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS        0x00040000
 #define BM_CLKCTRL_PLL1CTRL0_POWER      0x00020000
-#define BP_CLKCTRL_PLL1CTRL0_RSRVD1     0
-#define BM_CLKCTRL_PLL1CTRL0_RSRVD1     0x0001FFFF
-#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v)  \
-                (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1)
 
 #define HW_CLKCTRL_PLL1CTRL1    (0x00000030)
 
 #define BM_CLKCTRL_PLL1CTRL1_LOCK       0x80000000
 #define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000
-#define BP_CLKCTRL_PLL1CTRL1_RSRVD1     16
-#define BM_CLKCTRL_PLL1CTRL1_RSRVD1     0x3FFF0000
-#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v)  \
-                (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1)
 #define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0
 #define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF
 #define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v)  \
@@ -154,51 +115,31 @@
 #define HW_CLKCTRL_PLL2CTRL0_TOG        (0x0000004c)
 
 #define BM_CLKCTRL_PLL2CTRL0_CLKGATE    0x80000000
-#define BM_CLKCTRL_PLL2CTRL0_RSRVD3     0x40000000
 #define BP_CLKCTRL_PLL2CTRL0_LFR_SEL    28
 #define BM_CLKCTRL_PLL2CTRL0_LFR_SEL    0x30000000
 #define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v)  \
                 (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL)
-#define BM_CLKCTRL_PLL2CTRL0_RSRVD2     0x08000000
 #define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B    0x04000000
 #define BP_CLKCTRL_PLL2CTRL0_CP_SEL     24
 #define BM_CLKCTRL_PLL2CTRL0_CP_SEL     0x03000000
 #define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v)  \
                 (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL)
 #define BM_CLKCTRL_PLL2CTRL0_POWER      0x00800000
-#define BP_CLKCTRL_PLL2CTRL0_RSRVD1     0
-#define BM_CLKCTRL_PLL2CTRL0_RSRVD1     0x007FFFFF
-#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v)  \
-                (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1)
 
 #define HW_CLKCTRL_CPU  (0x00000050)
 #define HW_CLKCTRL_CPU_SET      (0x00000054)
 #define HW_CLKCTRL_CPU_CLR      (0x00000058)
 #define HW_CLKCTRL_CPU_TOG      (0x0000005c)
 
-#define BP_CLKCTRL_CPU_RSRVD5   30
-#define BM_CLKCTRL_CPU_RSRVD5   0xC0000000
-#define BF_CLKCTRL_CPU_RSRVD5(v) \
-                (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
 #define BM_CLKCTRL_CPU_BUSY_REF_XTAL    0x20000000
 #define BM_CLKCTRL_CPU_BUSY_REF_CPU     0x10000000
-#define BM_CLKCTRL_CPU_RSRVD4   0x08000000
 #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
 #define BP_CLKCTRL_CPU_DIV_XTAL 16
 #define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
 #define BF_CLKCTRL_CPU_DIV_XTAL(v)  \
                 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
-#define BP_CLKCTRL_CPU_RSRVD3   13
-#define BM_CLKCTRL_CPU_RSRVD3   0x0000E000
-#define BF_CLKCTRL_CPU_RSRVD3(v)  \
-                (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
 #define BM_CLKCTRL_CPU_INTERRUPT_WAIT   0x00001000
-#define BM_CLKCTRL_CPU_RSRVD2   0x00000800
 #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN  0x00000400
-#define BP_CLKCTRL_CPU_RSRVD1   6
-#define BM_CLKCTRL_CPU_RSRVD1   0x000003C0
-#define BF_CLKCTRL_CPU_RSRVD1(v)  \
-                (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
 #define BP_CLKCTRL_CPU_DIV_CPU  0
 #define BM_CLKCTRL_CPU_DIV_CPU  0x0000003F
 #define BF_CLKCTRL_CPU_DIV_CPU(v)  \
@@ -212,7 +153,6 @@
 #define BM_CLKCTRL_HBUS_ASM_BUSY        0x80000000
 #define BM_CLKCTRL_HBUS_DCP_AS_ENABLE   0x40000000
 #define BM_CLKCTRL_HBUS_PXP_AS_ENABLE   0x20000000
-#define BM_CLKCTRL_HBUS_RSRVD2  0x10000000
 #define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE   0x08000000
 #define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE       0x04000000
 #define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE       0x02000000
@@ -232,10 +172,6 @@
 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8  0x3
 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
-#define BP_CLKCTRL_HBUS_RSRVD1  6
-#define BM_CLKCTRL_HBUS_RSRVD1  0x0000FFC0
-#define BF_CLKCTRL_HBUS_RSRVD1(v)  \
-                (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
 #define BM_CLKCTRL_HBUS_DIV_FRAC_EN     0x00000020
 #define BP_CLKCTRL_HBUS_DIV     0
 #define BM_CLKCTRL_HBUS_DIV     0x0000001F
@@ -245,10 +181,6 @@
 #define HW_CLKCTRL_XBUS (0x00000070)
 
 #define BM_CLKCTRL_XBUS_BUSY    0x80000000
-#define BP_CLKCTRL_XBUS_RSRVD1  12
-#define BM_CLKCTRL_XBUS_RSRVD1  0x7FFFF000
-#define BF_CLKCTRL_XBUS_RSRVD1(v)  \
-                (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1)
 #define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE   0x00000800
 #define BM_CLKCTRL_XBUS_DIV_FRAC_EN     0x00000400
 #define BP_CLKCTRL_XBUS_DIV     0
@@ -263,19 +195,10 @@
 
 #define BP_CLKCTRL_XTAL_UART_CLK_GATE   31
 #define BM_CLKCTRL_XTAL_UART_CLK_GATE   0x80000000
-#define BM_CLKCTRL_XTAL_RSRVD3  0x40000000
 #define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
 #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
-#define BP_CLKCTRL_XTAL_RSRVD2  27
-#define BM_CLKCTRL_XTAL_RSRVD2  0x18000000
-#define BF_CLKCTRL_XTAL_RSRVD2(v)  \
-                (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2)
 #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      26
 #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      0x04000000
-#define BP_CLKCTRL_XTAL_RSRVD1  2
-#define BM_CLKCTRL_XTAL_RSRVD1  0x03FFFFFC
-#define BF_CLKCTRL_XTAL_RSRVD1(v)  \
-                (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
 #define BP_CLKCTRL_XTAL_DIV_UART        0
 #define BM_CLKCTRL_XTAL_DIV_UART        0x00000003
 #define BF_CLKCTRL_XTAL_DIV_UART(v)  \
@@ -285,12 +208,7 @@
 
 #define BP_CLKCTRL_SSP0_CLKGATE 31
 #define BM_CLKCTRL_SSP0_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP0_RSRVD2  0x40000000
 #define BM_CLKCTRL_SSP0_BUSY    0x20000000
-#define BP_CLKCTRL_SSP0_RSRVD1  10
-#define BM_CLKCTRL_SSP0_RSRVD1  0x1FFFFC00
-#define BF_CLKCTRL_SSP0_RSRVD1(v)  \
-                (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1)
 #define BM_CLKCTRL_SSP0_DIV_FRAC_EN     0x00000200
 #define BP_CLKCTRL_SSP0_DIV     0
 #define BM_CLKCTRL_SSP0_DIV     0x000001FF
@@ -301,12 +219,7 @@
 
 #define BP_CLKCTRL_SSP1_CLKGATE 31
 #define BM_CLKCTRL_SSP1_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP1_RSRVD2  0x40000000
 #define BM_CLKCTRL_SSP1_BUSY    0x20000000
-#define BP_CLKCTRL_SSP1_RSRVD1  10
-#define BM_CLKCTRL_SSP1_RSRVD1  0x1FFFFC00
-#define BF_CLKCTRL_SSP1_RSRVD1(v)  \
-                (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1)
 #define BM_CLKCTRL_SSP1_DIV_FRAC_EN     0x00000200
 #define BP_CLKCTRL_SSP1_DIV     0
 #define BM_CLKCTRL_SSP1_DIV     0x000001FF
@@ -317,12 +230,7 @@
 
 #define BP_CLKCTRL_SSP2_CLKGATE 31
 #define BM_CLKCTRL_SSP2_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP2_RSRVD2  0x40000000
 #define BM_CLKCTRL_SSP2_BUSY    0x20000000
-#define BP_CLKCTRL_SSP2_RSRVD1  10
-#define BM_CLKCTRL_SSP2_RSRVD1  0x1FFFFC00
-#define BF_CLKCTRL_SSP2_RSRVD1(v)  \
-                (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1)
 #define BM_CLKCTRL_SSP2_DIV_FRAC_EN     0x00000200
 #define BP_CLKCTRL_SSP2_DIV     0
 #define BM_CLKCTRL_SSP2_DIV     0x000001FF
@@ -333,12 +241,7 @@
 
 #define BP_CLKCTRL_SSP3_CLKGATE 31
 #define BM_CLKCTRL_SSP3_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP3_RSRVD2  0x40000000
 #define BM_CLKCTRL_SSP3_BUSY    0x20000000
-#define BP_CLKCTRL_SSP3_RSRVD1  10
-#define BM_CLKCTRL_SSP3_RSRVD1  0x1FFFFC00
-#define BF_CLKCTRL_SSP3_RSRVD1(v)  \
-                (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1)
 #define BM_CLKCTRL_SSP3_DIV_FRAC_EN     0x00000200
 #define BP_CLKCTRL_SSP3_DIV     0
 #define BM_CLKCTRL_SSP3_DIV     0x000001FF
@@ -349,12 +252,7 @@
 
 #define BP_CLKCTRL_GPMI_CLKGATE 31
 #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
-#define BM_CLKCTRL_GPMI_RSRVD2  0x40000000
 #define BM_CLKCTRL_GPMI_BUSY    0x20000000
-#define BP_CLKCTRL_GPMI_RSRVD1  11
-#define BM_CLKCTRL_GPMI_RSRVD1  0x1FFFF800
-#define BF_CLKCTRL_GPMI_RSRVD1(v)  \
-                (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
 #define BM_CLKCTRL_GPMI_DIV_FRAC_EN     0x00000400
 #define BP_CLKCTRL_GPMI_DIV     0
 #define BM_CLKCTRL_GPMI_DIV     0x000003FF
@@ -365,10 +263,6 @@
 
 #define BP_CLKCTRL_SPDIF_CLKGATE        31
 #define BM_CLKCTRL_SPDIF_CLKGATE        0x80000000
-#define BP_CLKCTRL_SPDIF_RSRVD  0
-#define BM_CLKCTRL_SPDIF_RSRVD  0x7FFFFFFF
-#define BF_CLKCTRL_SPDIF_RSRVD(v)  \
-                (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
 
 #define HW_CLKCTRL_EMI  (0x000000f0)
 
@@ -379,24 +273,12 @@
 #define BM_CLKCTRL_EMI_BUSY_REF_EMI     0x10000000
 #define BM_CLKCTRL_EMI_BUSY_REF_CPU     0x08000000
 #define BM_CLKCTRL_EMI_BUSY_SYNC_MODE   0x04000000
-#define BP_CLKCTRL_EMI_RSRVD3   18
-#define BM_CLKCTRL_EMI_RSRVD3   0x03FC0000
-#define BF_CLKCTRL_EMI_RSRVD3(v)  \
-                (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
 #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC  0x00020000
 #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE        0x00010000
-#define BP_CLKCTRL_EMI_RSRVD2   12
-#define BM_CLKCTRL_EMI_RSRVD2   0x0000F000
-#define BF_CLKCTRL_EMI_RSRVD2(v)  \
-                (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
 #define BP_CLKCTRL_EMI_DIV_XTAL 8
 #define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
 #define BF_CLKCTRL_EMI_DIV_XTAL(v)  \
                 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
-#define BP_CLKCTRL_EMI_RSRVD1   6
-#define BM_CLKCTRL_EMI_RSRVD1   0x000000C0
-#define BF_CLKCTRL_EMI_RSRVD1(v)  \
-                (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
 #define BP_CLKCTRL_EMI_DIV_EMI  0
 #define BM_CLKCTRL_EMI_DIV_EMI  0x0000003F
 #define BF_CLKCTRL_EMI_DIV_EMI(v)  \
@@ -406,12 +288,7 @@
 
 #define BP_CLKCTRL_SAIF0_CLKGATE        31
 #define BM_CLKCTRL_SAIF0_CLKGATE        0x80000000
-#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000
 #define BM_CLKCTRL_SAIF0_BUSY   0x20000000
-#define BP_CLKCTRL_SAIF0_RSRVD1 17
-#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000
-#define BF_CLKCTRL_SAIF0_RSRVD1(v)  \
-                (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1)
 #define BM_CLKCTRL_SAIF0_DIV_FRAC_EN    0x00010000
 #define BP_CLKCTRL_SAIF0_DIV    0
 #define BM_CLKCTRL_SAIF0_DIV    0x0000FFFF
@@ -422,12 +299,7 @@
 
 #define BP_CLKCTRL_SAIF1_CLKGATE        31
 #define BM_CLKCTRL_SAIF1_CLKGATE        0x80000000
-#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000
 #define BM_CLKCTRL_SAIF1_BUSY   0x20000000
-#define BP_CLKCTRL_SAIF1_RSRVD1 17
-#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000
-#define BF_CLKCTRL_SAIF1_RSRVD1(v)  \
-                (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1)
 #define BM_CLKCTRL_SAIF1_DIV_FRAC_EN    0x00010000
 #define BP_CLKCTRL_SAIF1_DIV    0
 #define BM_CLKCTRL_SAIF1_DIV    0x0000FFFF
@@ -438,12 +310,7 @@
 
 #define BP_CLKCTRL_DIS_LCDIF_CLKGATE    31
 #define BM_CLKCTRL_DIS_LCDIF_CLKGATE    0x80000000
-#define BM_CLKCTRL_DIS_LCDIF_RSRVD2     0x40000000
 #define BM_CLKCTRL_DIS_LCDIF_BUSY       0x20000000
-#define BP_CLKCTRL_DIS_LCDIF_RSRVD1     14
-#define BM_CLKCTRL_DIS_LCDIF_RSRVD1     0x1FFFC000
-#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v)  \
-                (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1)
 #define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN        0x00002000
 #define BP_CLKCTRL_DIS_LCDIF_DIV        0
 #define BM_CLKCTRL_DIS_LCDIF_DIV        0x00001FFF
@@ -453,12 +320,7 @@
 #define HW_CLKCTRL_ETM  (0x00000130)
 
 #define BM_CLKCTRL_ETM_CLKGATE  0x80000000
-#define BM_CLKCTRL_ETM_RSRVD2   0x40000000
 #define BM_CLKCTRL_ETM_BUSY     0x20000000
-#define BP_CLKCTRL_ETM_RSRVD1   8
-#define BM_CLKCTRL_ETM_RSRVD1   0x1FFFFF00
-#define BF_CLKCTRL_ETM_RSRVD1(v)  \
-                (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1)
 #define BM_CLKCTRL_ETM_DIV_FRAC_EN      0x00000080
 #define BP_CLKCTRL_ETM_DIV      0
 #define BM_CLKCTRL_ETM_DIV      0x0000007F
@@ -471,7 +333,6 @@
 #define BP_CLKCTRL_ENET_DISABLE 30
 #define BM_CLKCTRL_ENET_DISABLE 0x40000000
 #define BM_CLKCTRL_ENET_STATUS  0x20000000
-#define BM_CLKCTRL_ENET_RSRVD1  0x10000000
 #define BM_CLKCTRL_ENET_BUSY_TIME       0x08000000
 #define BP_CLKCTRL_ENET_DIV_TIME        21
 #define BM_CLKCTRL_ENET_DIV_TIME        0x07E00000
@@ -493,37 +354,23 @@
 #define BM_CLKCTRL_ENET_CLK_OUT_EN      0x00040000
 #define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP        0x00020000
 #define BM_CLKCTRL_ENET_RESET_BY_SW     0x00010000
-#define BP_CLKCTRL_ENET_RSRVD0  0
-#define BM_CLKCTRL_ENET_RSRVD0  0x0000FFFF
-#define BF_CLKCTRL_ENET_RSRVD0(v)  \
-                (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0)
 
 #define HW_CLKCTRL_HSADC        (0x00000150)
 
-#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000
 #define BM_CLKCTRL_HSADC_RESETB 0x40000000
 #define BP_CLKCTRL_HSADC_FREQDIV        28
 #define BM_CLKCTRL_HSADC_FREQDIV        0x30000000
 #define BF_CLKCTRL_HSADC_FREQDIV(v)  \
                 (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV)
-#define BP_CLKCTRL_HSADC_RSRVD1 0
-#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF
-#define BF_CLKCTRL_HSADC_RSRVD1(v)  \
-                (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1)
 
 #define HW_CLKCTRL_FLEXCAN      (0x00000160)
 
-#define BM_CLKCTRL_FLEXCAN_RSRVD2       0x80000000
 #define BP_CLKCTRL_FLEXCAN_STOP_CAN0    30
 #define BM_CLKCTRL_FLEXCAN_STOP_CAN0    0x40000000
 #define BM_CLKCTRL_FLEXCAN_CAN0_STATUS  0x20000000
 #define BP_CLKCTRL_FLEXCAN_STOP_CAN1    28
 #define BM_CLKCTRL_FLEXCAN_STOP_CAN1    0x10000000
 #define BM_CLKCTRL_FLEXCAN_CAN1_STATUS  0x08000000
-#define BP_CLKCTRL_FLEXCAN_RSRVD1       0
-#define BM_CLKCTRL_FLEXCAN_RSRVD1       0x07FFFFFF
-#define BF_CLKCTRL_FLEXCAN_RSRVD1(v)  \
-                (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1)
 
 #define HW_CLKCTRL_FRAC0        (0x000001b0)
 #define HW_CLKCTRL_FRAC0_SET    (0x000001b4)
@@ -564,10 +411,6 @@
 #define HW_CLKCTRL_FRAC1_CLR    (0x000001c8)
 #define HW_CLKCTRL_FRAC1_TOG    (0x000001cc)
 
-#define BP_CLKCTRL_FRAC1_RSRVD2 24
-#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000
-#define BF_CLKCTRL_FRAC1_RSRVD2(v) \
-                (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2)
 #define BP_CLKCTRL_FRAC1_CLKGATEGPMI    23
 #define BM_CLKCTRL_FRAC1_CLKGATEGPMI    0x00800000
 #define BM_CLKCTRL_FRAC1_GPMI_STABLE    0x00400000
@@ -595,22 +438,10 @@
 #define HW_CLKCTRL_CLKSEQ_CLR   (0x000001d8)
 #define HW_CLKCTRL_CLKSEQ_TOG   (0x000001dc)
 
-#define BP_CLKCTRL_CLKSEQ_RSRVD0        19
-#define BM_CLKCTRL_CLKSEQ_RSRVD0        0xFFF80000
-#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \
-                (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0)
 #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU    0x00040000
-#define BP_CLKCTRL_CLKSEQ_RSRVD1        15
-#define BM_CLKCTRL_CLKSEQ_RSRVD1        0x00038000
-#define BF_CLKCTRL_CLKSEQ_RSRVD1(v)  \
-                (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1)
 #define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF      0x00004000
 #define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1
 #define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD    0x0
-#define BP_CLKCTRL_CLKSEQ_RSRVD2        9
-#define BM_CLKCTRL_CLKSEQ_RSRVD2        0x00003E00
-#define BF_CLKCTRL_CLKSEQ_RSRVD2(v)  \
-                (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2)
 #define BM_CLKCTRL_CLKSEQ_BYPASS_ETM    0x00000100
 #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI    0x00000080
 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3   0x00000040
@@ -623,10 +454,6 @@
 
 #define HW_CLKCTRL_RESET        (0x000001e0)
 
-#define BP_CLKCTRL_RESET_RSRVD  6
-#define BM_CLKCTRL_RESET_RSRVD  0xFFFFFFC0
-#define BF_CLKCTRL_RESET_RSRVD(v) \
-                (((v) << 6) & BM_CLKCTRL_RESET_RSRVD)
 #define BM_CLKCTRL_RESET_WDOG_POR_DISABLE       0x00000020
 #define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE  0x00000010
 #define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE   0x00000008
@@ -640,10 +467,6 @@
 #define BM_CLKCTRL_STATUS_CPU_LIMIT     0xC0000000
 #define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
                 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
-#define BP_CLKCTRL_STATUS_RSRVD 0
-#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
-#define BF_CLKCTRL_STATUS_RSRVD(v)  \
-                (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
 
 #define HW_CLKCTRL_VERSION      (0x00000200)
 
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 9343d7edd4f6..20ec3bddf7cd 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -22,6 +22,7 @@
 #include <linux/err.h>
 #include <linux/delay.h>
 #include <linux/init.h>
+#include <linux/module.h>
 
 #include <asm/proc-fns.h>
 #include <asm/system.h>
@@ -135,3 +136,4 @@ error:
         pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
         return -ETIMEDOUT;
 }
+EXPORT_SYMBOL(mxs_reset_block);
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 8dc2c76d2260..986c3bf4e6b8 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -26,6 +26,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <mach/bridge-regs.h>
 #include <mach/hardware.h>
 #include <mach/orion5x.h>
 #include <plat/ehci-orion.h>
@@ -599,6 +600,11 @@ void __init orion5x_wdt_init(void)
 /*****************************************************************************
  * Time handling
  ****************************************************************************/
+void __init orion5x_init_early(void)
+{
+        orion_time_set_base(TIMER_VIRT_BASE);
+}
+
 int orion5x_tclk;
 
 int __init orion5x_find_tclk(void)
@@ -616,7 +622,9 @@ int __init orion5x_find_tclk(void)
 static void orion5x_timer_init(void)
 {
         orion5x_tclk = orion5x_find_tclk();
-        orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk);
+
+        orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+                        IRQ_ORION5X_BRIDGE, orion5x_tclk);
 }
 
 struct sys_timer orion5x_timer = {
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 8f004503c96d..f2b2b35e8646 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -9,6 +9,7 @@ struct mv_sata_platform_data;
  * Basic Orion init functions used early by machine-setup.
  */
 void orion5x_map_io(void);
+void orion5x_init_early(void);
 void orion5x_init_irq(void);
 void orion5x_init(void);
 extern int orion5x_tclk;
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index b1c451f5ee27..425807579303 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -339,6 +339,7 @@ MACHINE_START(D2NET, "LaCie d2 Network")
         .boot_params    = 0x00000100,
         .init_machine   = d2net_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
@@ -350,6 +351,7 @@ MACHINE_START(BIGDISK, "LaCie Big Disk Network")
         .boot_params    = 0x00000100,
         .init_machine   = d2net_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index df1083f5b6eb..c10a11715376 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -361,6 +361,7 @@ MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
         .boot_params    = 0x00000100,
         .init_machine   = db88f5281_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 3a7bc0e36982..90ab022eabeb 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -733,6 +733,7 @@ MACHINE_START(DNS323, "D-Link DNS-323")
         .boot_params    = 0x00000100,
         .init_machine   = dns323_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index ba98459f44b0..d037a90c216c 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -254,6 +254,7 @@ MACHINE_START(EDMINI_V2, "LaCie Ethernet Disk mini V2")
         .boot_params    = 0x00000100,
         .init_machine   = edmini_v2_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
index 5c9744cd8ef6..96484bcd34ca 100644
--- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -22,14 +22,12 @@
 
 #define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
 
+#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE | 0x110)
+
 #define POWER_MNG_CTRL_REG      (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
 
-#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE | 0x110)
 #define WDT_INT_REQ             0x0008
 
-#define BRIDGE_MASK             (ORION5X_BRIDGE_VIRT_BASE | 0x114)
-#define BRIDGE_INT_TIMER0       0x0002
-#define BRIDGE_INT_TIMER1       0x0004
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 
 #define MAIN_IRQ_CAUSE          (ORION5X_BRIDGE_VIRT_BASE | 0x200)
diff --git a/arch/arm/mach-orion5x/include/mach/gpio.h b/arch/arm/mach-orion5x/include/mach/gpio.h
index d8182e87ac16..a1d0b78decb1 100644
--- a/arch/arm/mach-orion5x/include/mach/gpio.h
+++ b/arch/arm/mach-orion5x/include/mach/gpio.h
@@ -6,32 +6,4 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#include <mach/irqs.h>
 #include <plat/gpio.h>
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-
-#define GPIO_MAX                32
-#define GPIO_OUT(pin)           ORION5X_DEV_BUS_REG(0x100)
-#define GPIO_IO_CONF(pin)       ORION5X_DEV_BUS_REG(0x104)
-#define GPIO_BLINK_EN(pin)      ORION5X_DEV_BUS_REG(0x108)
-#define GPIO_IN_POL(pin)        ORION5X_DEV_BUS_REG(0x10c)
-#define GPIO_DATA_IN(pin)       ORION5X_DEV_BUS_REG(0x110)
-#define GPIO_EDGE_CAUSE(pin)    ORION5X_DEV_BUS_REG(0x114)
-#define GPIO_EDGE_MASK(pin)     ORION5X_DEV_BUS_REG(0x118)
-#define GPIO_LEVEL_MASK(pin)    ORION5X_DEV_BUS_REG(0x11c)
-
-static inline int gpio_to_irq(int pin)
-{
-        return pin + IRQ_ORION5X_GPIO_START;
-}
-
-static inline int irq_to_gpio(int irq)
-{
-        return irq - IRQ_ORION5X_GPIO_START;
-}
-
-
-#endif
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 2d8766570531..0a28bbc76891 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -73,6 +73,7 @@
 #define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
 #define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
 #define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
+#define  GPIO_VIRT_BASE                 ORION5X_DEV_BUS_REG(0x0100)
 #define  SPI_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
 #define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
 #define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index d7512b925a85..ed85891f8699 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -28,27 +28,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
 void __init orion5x_init_irq(void)
 {
-        int i;
-
         orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
 
         /*
-         * Mask and clear GPIO IRQ interrupts
-         */
-        writel(0x0, GPIO_LEVEL_MASK(0));
-        writel(0x0, GPIO_EDGE_MASK(0));
-        writel(0x0, GPIO_EDGE_CAUSE(0));
-
-        /*
-         * Register chained level handlers for GPIO IRQs by default.
-         * User can use set_type() if he wants to use edge types handlers.
+         * Initialize gpiolib for GPIOs 0-31.
          */
-        for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
-                set_irq_chip(i, &orion_gpio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                irq_desc[i].status |= IRQ_LEVEL;
-                set_irq_flags(i, IRQF_VALID);
-        }
+        orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START);
         set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
         set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
         set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 4be9aa08de69..47497c76162a 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -382,6 +382,7 @@ MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
         .boot_params    = 0x00000100,
         .init_machine   = kurobox_pro_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
@@ -394,6 +395,7 @@ MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
         .boot_params    = 0x00000100,
         .init_machine   = kurobox_pro_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 20a9b66cbafa..6ae12aa6d759 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -321,6 +321,7 @@ MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)")
         .boot_params    = 0x00000100,
         .init_machine   = lschl_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 437364b7168e..7adafd79cf98 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -268,6 +268,7 @@ MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL")
         .boot_params    = 0x00000100,
         .init_machine   = ls_hgl_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index ab9b0cf0a90b..869958f5c394 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -270,6 +270,7 @@ MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini")
         .boot_params    = 0x00000100,
         .init_machine   = lsmini_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index db485d3b8144..2288207726e4 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -124,9 +124,6 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
         u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
         u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
 
-        /* Initialize gpiolib. */
-        orion_gpio_init();
-
         for ( ; mode->mpp >= 0; mode++) {
                 u32 *reg;
                 int num_type;
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 2f0e16cd7e81..b43b208153cb 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -264,6 +264,7 @@ MACHINE_START(MSS2, "Maxtor Shared Storage II")
         .boot_params    = 0x00000100,
         .init_machine   = mss2_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index b3d90f25de9f..c55d071707f5 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -232,6 +232,7 @@ MACHINE_START(MV2120, "HP Media Vault mv2120")
         .boot_params    = 0x00000100,
         .init_machine   = mv2120_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index d6665b31665f..429ecafe9fdd 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -422,6 +422,7 @@ MACHINE_START(NET2BIG, "LaCie 2Big Network")
         .boot_params    = 0x00000100,
         .init_machine   = net2big_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index f4c26fd731f4..34310ab56e29 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -172,6 +172,7 @@ MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
         .boot_params    = 0x00000100,
         .init_machine   = rd88f5181l_fxo_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index b5942909bab0..c1f79fa014ed 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -184,6 +184,7 @@ MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
         .boot_params    = 0x00000100,
         .init_machine   = rd88f5181l_ge_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 165ed87029b2..67ec6959b267 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -308,6 +308,7 @@ MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
         .boot_params    = 0x00000100,
         .init_machine   = rd88f5182_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index 02ff45f3e2e3..b080c6966d10 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -126,6 +126,7 @@ MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design")
         .boot_params    = 0x00000100,
         .init_machine   = rd88f6183ap_ge_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 4403fae5ab0e..5653ee6c71d8 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -361,6 +361,7 @@ MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live")
         .boot_params    = 0x00000100,
         .init_machine   = tsp2_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 1e196129d763..8bbd27ea6735 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -325,6 +325,7 @@ MACHINE_START(TS209, "QNAP TS-109/TS-209")
         .boot_params    = 0x00000100,
         .init_machine   = qnap_ts209_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 428af2046e36..92f393f08fa4 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -314,6 +314,7 @@ MACHINE_START(TS409, "QNAP TS-409")
         .boot_params    = 0x00000100,
         .init_machine   = qnap_ts409_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ts78xx-fpga.h b/arch/arm/mach-orion5x/ts78xx-fpga.h
index 37b3d4875291..151e89e1e676 100644
--- a/arch/arm/mach-orion5x/ts78xx-fpga.h
+++ b/arch/arm/mach-orion5x/ts78xx-fpga.h
@@ -1,3 +1,4 @@
+#define TS7800_FPGA_MAGIC 0x00b480
 #define FPGAID(_magic, _rev) ((_magic << 8) + _rev)
 
 /*
@@ -6,11 +7,15 @@
  */
 enum fpga_ids {
         /* Technologic Systems */
-        TS7800_REV_1    = FPGAID(0x00b480, 0x01),
-        TS7800_REV_2    = FPGAID(0x00b480, 0x02),
-        TS7800_REV_3    = FPGAID(0x00b480, 0x03),
-        TS7800_REV_4    = FPGAID(0x00b480, 0x04),
-        TS7800_REV_5    = FPGAID(0x00b480, 0x05),
+        TS7800_REV_1    = FPGAID(TS7800_FPGA_MAGIC, 0x01),
+        TS7800_REV_2    = FPGAID(TS7800_FPGA_MAGIC, 0x02),
+        TS7800_REV_3    = FPGAID(TS7800_FPGA_MAGIC, 0x03),
+        TS7800_REV_4    = FPGAID(TS7800_FPGA_MAGIC, 0x04),
+        TS7800_REV_5    = FPGAID(TS7800_FPGA_MAGIC, 0x05),
+        TS7800_REV_6    = FPGAID(TS7800_FPGA_MAGIC, 0x06),
+        TS7800_REV_7    = FPGAID(TS7800_FPGA_MAGIC, 0x07),
+        TS7800_REV_8    = FPGAID(TS7800_FPGA_MAGIC, 0x08),
+        TS7800_REV_9    = FPGAID(TS7800_FPGA_MAGIC, 0x09),
 
         /* Unaffordable & Expensive */
         UAE_DUMMY       = FPGAID(0xffffff, 0x01),
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index c1c1cd04bdde..8554707d20a9 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -191,6 +191,60 @@ static int ts78xx_ts_nand_dev_ready(struct mtd_info *mtd)
         return readb(TS_NAND_CTRL) & 0x20;
 }
 
+static void ts78xx_ts_nand_write_buf(struct mtd_info *mtd,
+                        const uint8_t *buf, int len)
+{
+        struct nand_chip *chip = mtd->priv;
+        void __iomem *io_base = chip->IO_ADDR_W;
+        unsigned long off = ((unsigned long)buf & 3);
+        int sz;
+
+        if (off) {
+                sz = min_t(int, 4 - off, len);
+                writesb(io_base, buf, sz);
+                buf += sz;
+                len -= sz;
+        }
+
+        sz = len >> 2;
+        if (sz) {
+                u32 *buf32 = (u32 *)buf;
+                writesl(io_base, buf32, sz);
+                buf += sz << 2;
+                len -= sz << 2;
+        }
+
+        if (len)
+                writesb(io_base, buf, len);
+}
+
+static void ts78xx_ts_nand_read_buf(struct mtd_info *mtd,
+                        uint8_t *buf, int len)
+{
+        struct nand_chip *chip = mtd->priv;
+        void __iomem *io_base = chip->IO_ADDR_R;
+        unsigned long off = ((unsigned long)buf & 3);
+        int sz;
+
+        if (off) {
+                sz = min_t(int, 4 - off, len);
+                readsb(io_base, buf, sz);
+                buf += sz;
+                len -= sz;
+        }
+
+        sz = len >> 2;
+        if (sz) {
+                u32 *buf32 = (u32 *)buf;
+                readsl(io_base, buf32, sz);
+                buf += sz << 2;
+                len -= sz << 2;
+        }
+
+        if (len)
+                readsb(io_base, buf, len);
+}
+
 const char *ts_nand_part_probes[] = { "cmdlinepart", NULL };
 
 static struct mtd_partition ts78xx_ts_nand_parts[] = {
@@ -233,6 +287,8 @@ static struct platform_nand_data ts78xx_ts_nand_data = {
                  */
                 .cmd_ctrl               = ts78xx_ts_nand_cmd_ctrl,
                 .dev_ready              = ts78xx_ts_nand_dev_ready,
+                .write_buf              = ts78xx_ts_nand_write_buf,
+                .read_buf               = ts78xx_ts_nand_read_buf,
         },
 };
 
@@ -334,14 +390,29 @@ static void ts78xx_fpga_supports(void)
         case TS7800_REV_3:
         case TS7800_REV_4:
         case TS7800_REV_5:
+        case TS7800_REV_6:
+        case TS7800_REV_7:
+        case TS7800_REV_8:
+        case TS7800_REV_9:
                 ts78xx_fpga.supports.ts_rtc.present = 1;
                 ts78xx_fpga.supports.ts_nand.present = 1;
                 ts78xx_fpga.supports.ts_rng.present = 1;
                 break;
         default:
-                ts78xx_fpga.supports.ts_rtc.present = 0;
-                ts78xx_fpga.supports.ts_nand.present = 0;
-                ts78xx_fpga.supports.ts_rng.present = 0;
+                /* enable devices if magic matches */
+                switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
+                case TS7800_FPGA_MAGIC:
+                        printk(KERN_WARNING "TS-7800 FPGA: unrecognized revision 0x%.2x\n",
+                                        ts78xx_fpga.id & 0xff);
+                        ts78xx_fpga.supports.ts_rtc.present = 1;
+                        ts78xx_fpga.supports.ts_nand.present = 1;
+                        ts78xx_fpga.supports.ts_rng.present = 1;
+                        break;
+                default:
+                        ts78xx_fpga.supports.ts_rtc.present = 0;
+                        ts78xx_fpga.supports.ts_nand.present = 0;
+                        ts78xx_fpga.supports.ts_rng.present = 0;
+                }
         }
 }
 
@@ -553,6 +624,7 @@ MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
         .boot_params    = 0x00000100,
         .init_machine   = ts78xx_init,
         .map_io         = ts78xx_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 7994d6ec08a8..4e5216be0745 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -175,6 +175,7 @@ MACHINE_START(WNR854T, "Netgear WNR854T")
         .boot_params    = 0x00000100,
         .init_machine   = wnr854t_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index a5989b7eb53e..fab79d09cc5c 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -263,6 +263,7 @@ MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
         .boot_params    = 0x00000100,
         .init_machine   = wrt350n_v2_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
index 37405d9abe32..0db2411ef4bb 100644
--- a/arch/arm/mach-s3c2440/mach-gta02.c
+++ b/arch/arm/mach-s3c2440/mach-gta02.c
@@ -58,6 +58,9 @@
 #include <linux/mfd/pcf50633/pmic.h>
 #include <linux/mfd/pcf50633/backlight.h>
 
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -86,6 +89,8 @@
 #include <plat/udc.h>
 #include <plat/gpio-cfg.h>
 #include <plat/iic.h>
+#include <plat/ts.h>
+
 
 static struct pcf50633 *gta02_pcf;
 
@@ -280,9 +285,6 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
                                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
                                 .always_on = 1,
                                 .apply_uV = 1,
-                                .state_mem = {
-                                        .enabled = 1,
-                                },
                         },
                 },
                 [PCF50633_REGULATOR_DOWN1] = {
@@ -301,9 +303,6 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
                                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
                                 .apply_uV = 1,
                                 .always_on = 1,
-                                .state_mem = {
-                                        .enabled = 1,
-                                },
                         },
                 },
                 [PCF50633_REGULATOR_HCLDO] = {
@@ -311,8 +310,8 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
                                 .min_uV = 2000000,
                                 .max_uV = 3300000,
                                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                                .always_on = 1,
+                                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                                REGULATOR_CHANGE_STATUS,
                         },
                 },
                 [PCF50633_REGULATOR_LDO1] = {
@@ -320,10 +319,8 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
                                 .min_uV = 3300000,
                                 .max_uV = 3300000,
                                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                                 .apply_uV = 1,
-                                .state_mem = {
-                                        .enabled = 0,
-                                },
                         },
                 },
                 [PCF50633_REGULATOR_LDO2] = {
@@ -347,6 +344,7 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
                                 .min_uV = 3200000,
                                 .max_uV = 3200000,
                                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                                 .apply_uV = 1,
                         },
                 },
@@ -355,10 +353,8 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
                                 .min_uV = 3000000,
                                 .max_uV = 3000000,
                                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                                 .apply_uV = 1,
-                                .state_mem = {
-                                        .enabled = 1,
-                                },
                         },
                 },
                 [PCF50633_REGULATOR_LDO6] = {
@@ -373,9 +369,6 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
                                 .min_uV = 1800000,
                                 .max_uV = 1800000,
                                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .state_mem = {
-                                        .enabled = 1,
-                                },
                         },
                 },
 
@@ -471,6 +464,43 @@ static struct s3c2410_hcd_info gta02_usb_info __initdata = {
         },
 };
 
+/* Touchscreen */
+static struct s3c2410_ts_mach_info gta02_ts_info = {
+        .delay                  = 10000,
+        .presc                  = 0xff, /* slow as we can go */
+        .oversampling_shift     = 2,
+};
+
+/* Buttons */
+static struct gpio_keys_button gta02_buttons[] = {
+        {
+                .gpio = GTA02_GPIO_AUX_KEY,
+                .code = KEY_PHONE,
+                .desc = "Aux",
+                .type = EV_KEY,
+                .debounce_interval = 100,
+        },
+        {
+                .gpio = GTA02_GPIO_HOLD_KEY,
+                .code = KEY_PAUSE,
+                .desc = "Hold",
+                .type = EV_KEY,
+                .debounce_interval = 100,
+        },
+};
+
+static struct gpio_keys_platform_data gta02_buttons_pdata = {
+        .buttons = gta02_buttons,
+        .nbuttons = ARRAY_SIZE(gta02_buttons),
+};
+
+static struct platform_device gta02_buttons_device = {
+        .name = "gpio-keys",
+        .id = -1,
+        .dev = {
+                .platform_data = &gta02_buttons_pdata,
+        },
+};
 
 static void __init gta02_map_io(void)
 {
@@ -491,7 +521,11 @@ static struct platform_device *gta02_devices[] __initdata = {
         &gta02_nor_flash,
         &s3c24xx_pwm_device,
         &s3c_device_iis,
+        &samsung_asoc_dma,
         &s3c_device_i2c0,
+        &gta02_buttons_device,
+        &s3c_device_adc,
+        &s3c_device_ts,
 };
 
 /* These guys DO need to be children of PMU. */
@@ -541,6 +575,7 @@ static void __init gta02_machine_init(void)
 #endif
 
         s3c24xx_udc_set_platdata(&gta02_udc_cfg);
+        s3c24xx_ts_set_platdata(&gta02_ts_info);
         s3c_ohci_set_platdata(&gta02_usb_info);
         s3c_nand_set_platdata(&gta02_nand_info);
         s3c_i2c0_set_platdata(NULL);
@@ -549,6 +584,8 @@ static void __init gta02_machine_init(void)
 
         platform_add_devices(gta02_devices, ARRAY_SIZE(gta02_devices));
         pm_power_off = gta02_poweroff;
+
+        regulator_has_full_constraints();
 }
 
 
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 579d2f0f4dd0..e4177e22557b 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -143,6 +143,7 @@ config MACH_SMDK6410
         select S3C_DEV_USB_HSOTG
         select S3C_DEV_WDT
         select SAMSUNG_DEV_KEYPAD
+        select SAMSUNG_DEV_PWM
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select S3C64XX_SETUP_SDHCI
         select S3C64XX_SETUP_I2C1
@@ -231,7 +232,7 @@ config MACH_HMT
         select S3C_DEV_NAND
         select S3C_DEV_USB_HOST
         select S3C64XX_SETUP_FB_24BPP
-        select HAVE_PWM
+        select SAMSUNG_DEV_PWM
         help
           Machine support for the Airgoo HMT
 
@@ -249,8 +250,8 @@ config MACH_SMARTQ
         select S3C64XX_SETUP_SDHCI
         select S3C64XX_SETUP_FB_24BPP
         select SAMSUNG_DEV_ADC
+        select SAMSUNG_DEV_PWM
         select SAMSUNG_DEV_TS
-        select HAVE_PWM
         help
             Shared machine support for SmartQ 5/7
 
diff --git a/arch/arm/mach-s3c64xx/cpufreq.c b/arch/arm/mach-s3c64xx/cpufreq.c
index 74c0e8347de5..4375b97588b8 100644
--- a/arch/arm/mach-s3c64xx/cpufreq.c
+++ b/arch/arm/mach-s3c64xx/cpufreq.c
@@ -181,7 +181,7 @@ static void __init s3c64xx_cpufreq_config_regulator(void)
 }
 #endif
 
-static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
+static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
 {
         int ret;
         struct cpufreq_frequency_table *freq;
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index a80a3163dd30..686a4f270b12 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -29,6 +29,7 @@
 #include <linux/smsc911x.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
+#include <linux/pwm_backlight.h>
 
 #ifdef CONFIG_SMDK6410_WM1190_EV1
 #include <linux/mfd/wm8350/core.h>
@@ -49,6 +50,7 @@
 #include <mach/hardware.h>
 #include <mach/regs-fb.h>
 #include <mach/map.h>
+#include <mach/gpio-bank-f.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -119,7 +121,6 @@ static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
 {
         if (power) {
                 gpio_direction_output(S3C64XX_GPF(13), 1);
-                gpio_direction_output(S3C64XX_GPF(15), 1);
 
                 /* fire nRESET on power up */
                 gpio_direction_output(S3C64XX_GPN(5), 0);
@@ -127,7 +128,6 @@ static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
                 gpio_direction_output(S3C64XX_GPN(5), 1);
                 msleep(1);
         } else {
-                gpio_direction_output(S3C64XX_GPF(15), 0);
                 gpio_direction_output(S3C64XX_GPF(13), 0);
         }
 }
@@ -270,6 +270,45 @@ static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = {
         .cols           = 8,
 };
 
+static int smdk6410_backlight_init(struct device *dev)
+{
+        int ret;
+
+        ret = gpio_request(S3C64XX_GPF(15), "Backlight");
+        if (ret) {
+                printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
+                return ret;
+        }
+
+        /* Configure GPIO pin with S3C64XX_GPF15_PWM_TOUT1 */
+        s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2));
+
+        return 0;
+}
+
+static void smdk6410_backlight_exit(struct device *dev)
+{
+        s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_OUTPUT);
+        gpio_free(S3C64XX_GPF(15));
+}
+
+static struct platform_pwm_backlight_data smdk6410_backlight_data = {
+        .pwm_id         = 1,
+        .max_brightness = 255,
+        .dft_brightness = 255,
+        .pwm_period_ns  = 78770,
+        .init           = smdk6410_backlight_init,
+        .exit           = smdk6410_backlight_exit,
+};
+
+static struct platform_device smdk6410_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent         = &s3c_device_timer[1].dev,
+                .platform_data  = &smdk6410_backlight_data,
+        },
+};
+
 static struct map_desc smdk6410_iodesc[] = {};
 
 static struct platform_device *smdk6410_devices[] __initdata = {
@@ -299,6 +338,8 @@ static struct platform_device *smdk6410_devices[] __initdata = {
         &s3c_device_rtc,
         &s3c_device_ts,
         &s3c_device_wdt,
+        &s3c_device_timer[1],
+        &smdk6410_backlight_device,
 };
 
 #ifdef CONFIG_REGULATOR
@@ -694,7 +735,6 @@ static void __init smdk6410_machine_init(void)
 
         gpio_request(S3C64XX_GPN(5), "LCD power");
         gpio_request(S3C64XX_GPF(13), "LCD power");
-        gpio_request(S3C64XX_GPF(15), "LCD power");
 
         i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
         i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 164d2783d381..017af4c4293c 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -10,12 +10,14 @@ if ARCH_S5P64X0
 config CPU_S5P6440
         bool
         select S3C_PL330_DMA
+        select S5P_HRT
         help
           Enable S5P6440 CPU support
 
 config CPU_S5P6450
         bool
         select S3C_PL330_DMA
+        select S5P_HRT
         help
           Enable S5P6450 CPU support
 
@@ -34,6 +36,7 @@ config MACH_SMDK6440
         select S3C_DEV_WDT
         select S3C64XX_DEV_SPI
         select SAMSUNG_DEV_ADC
+        select SAMSUNG_DEV_PWM
         select SAMSUNG_DEV_TS
         select S5P64X0_SETUP_I2C1
         help
@@ -47,6 +50,7 @@ config MACH_SMDK6450
         select S3C_DEV_WDT
         select S3C64XX_DEV_SPI
         select SAMSUNG_DEV_ADC
+        select SAMSUNG_DEV_PWM
         select SAMSUNG_DEV_TS
         select S5P64X0_SETUP_I2C1
         help
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index e5beb84e2393..2d559f10fd47 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -22,6 +22,7 @@
 #include <linux/module.h>
 #include <linux/clk.h>
 #include <linux/gpio.h>
+#include <linux/pwm_backlight.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -32,6 +33,7 @@
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 #include <mach/i2c.h>
+#include <mach/regs-gpio.h>
 
 #include <plat/regs-serial.h>
 #include <plat/gpio-cfg.h>
@@ -43,6 +45,7 @@
 #include <plat/pll.h>
 #include <plat/adc.h>
 #include <plat/ts.h>
+#include <plat/s5p-time.h>
 
 #define SMDK6440_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |         \
@@ -88,6 +91,45 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
         },
 };
 
+static int smdk6440_backlight_init(struct device *dev)
+{
+        int ret;
+
+        ret = gpio_request(S5P6440_GPF(15), "Backlight");
+        if (ret) {
+                printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
+                return ret;
+        }
+
+        /* Configure GPIO pin with S5P6440_GPF15_PWM_TOUT1 */
+        s3c_gpio_cfgpin(S5P6440_GPF(15), S3C_GPIO_SFN(2));
+
+        return 0;
+}
+
+static void smdk6440_backlight_exit(struct device *dev)
+{
+        s3c_gpio_cfgpin(S5P6440_GPF(15), S3C_GPIO_OUTPUT);
+        gpio_free(S5P6440_GPF(15));
+}
+
+static struct platform_pwm_backlight_data smdk6440_backlight_data = {
+        .pwm_id         = 1,
+        .max_brightness = 255,
+        .dft_brightness = 255,
+        .pwm_period_ns  = 78770,
+        .init           = smdk6440_backlight_init,
+        .exit           = smdk6440_backlight_exit,
+};
+
+static struct platform_device smdk6440_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent         = &s3c_device_timer[1].dev,
+                .platform_data  = &smdk6440_backlight_data,
+        },
+};
+
 static struct platform_device *smdk6440_devices[] __initdata = {
         &s3c_device_adc,
         &s3c_device_rtc,
@@ -97,6 +139,8 @@ static struct platform_device *smdk6440_devices[] __initdata = {
         &s3c_device_wdt,
         &samsung_asoc_dma,
         &s5p6440_device_iis,
+        &s3c_device_timer[1],
+        &smdk6440_backlight_device,
 };
 
 static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
@@ -136,6 +180,7 @@ static void __init smdk6440_map_io(void)
         s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
+        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
 }
 
 static void __init smdk6440_machine_init(void)
@@ -159,5 +204,5 @@ MACHINE_START(SMDK6440, "SMDK6440")
         .init_irq       = s5p6440_init_irq,
         .map_io         = smdk6440_map_io,
         .init_machine   = smdk6440_machine_init,
-        .timer          = &s3c24xx_timer,
+        .timer          = &s5p_timer,
 MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 3a20de0a9264..d19c4690ee97 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -22,6 +22,7 @@
 #include <linux/module.h>
 #include <linux/clk.h>
 #include <linux/gpio.h>
+#include <linux/pwm_backlight.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -32,6 +33,7 @@
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 #include <mach/i2c.h>
+#include <mach/regs-gpio.h>
 
 #include <plat/regs-serial.h>
 #include <plat/gpio-cfg.h>
@@ -43,6 +45,7 @@
 #include <plat/pll.h>
 #include <plat/adc.h>
 #include <plat/ts.h>
+#include <plat/s5p-time.h>
 
 #define SMDK6450_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |         \
@@ -106,6 +109,45 @@ static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
 #endif
 };
 
+static int smdk6450_backlight_init(struct device *dev)
+{
+        int ret;
+
+        ret = gpio_request(S5P6450_GPF(15), "Backlight");
+        if (ret) {
+                printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
+                return ret;
+        }
+
+        /* Configure GPIO pin with S5P6450_GPF15_PWM_TOUT1 */
+        s3c_gpio_cfgpin(S5P6450_GPF(15), S3C_GPIO_SFN(2));
+
+        return 0;
+}
+
+static void smdk6450_backlight_exit(struct device *dev)
+{
+        s3c_gpio_cfgpin(S5P6450_GPF(15), S3C_GPIO_OUTPUT);
+        gpio_free(S5P6450_GPF(15));
+}
+
+static struct platform_pwm_backlight_data smdk6450_backlight_data = {
+        .pwm_id         = 1,
+        .max_brightness = 255,
+        .dft_brightness = 255,
+        .pwm_period_ns  = 78770,
+        .init           = smdk6450_backlight_init,
+        .exit           = smdk6450_backlight_exit,
+};
+
+static struct platform_device smdk6450_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent         = &s3c_device_timer[1].dev,
+                .platform_data  = &smdk6450_backlight_data,
+        },
+};
+
 static struct platform_device *smdk6450_devices[] __initdata = {
         &s3c_device_adc,
         &s3c_device_rtc,
@@ -115,6 +157,8 @@ static struct platform_device *smdk6450_devices[] __initdata = {
         &s3c_device_wdt,
         &samsung_asoc_dma,
         &s5p6450_device_iis0,
+        &s3c_device_timer[1],
+        &smdk6450_backlight_device,
         /* s5p6450_device_spi0 will be added */
 };
 
@@ -155,6 +199,7 @@ static void __init smdk6450_map_io(void)
         s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
         s3c24xx_init_clocks(19200000);
         s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
+        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
 }
 
 static void __init smdk6450_machine_init(void)
@@ -178,5 +223,5 @@ MACHINE_START(SMDK6450, "SMDK6450")
         .init_irq       = s5p6450_init_irq,
         .map_io         = smdk6450_map_io,
         .init_machine   = smdk6450_machine_init,
-        .timer          = &s3c24xx_timer,
+        .timer          = &s5p_timer,
 MACHINE_END
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index b8fbf2fcba6f..608722ff4f28 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -58,6 +58,7 @@ config MACH_SMDKC100
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_IDE
         select SAMSUNG_DEV_KEYPAD
+        select SAMSUNG_DEV_PWM
         select SAMSUNG_DEV_TS
         select S5PC100_SETUP_FB_24BPP
         select S5PC100_SETUP_I2C1
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
index 20856eb7dd51..2842394b28b5 100644
--- a/arch/arm/mach-s5pc100/gpiolib.c
+++ b/arch/arm/mach-s5pc100/gpiolib.c
@@ -348,6 +348,7 @@ static __init int s5pc100_gpiolib_init(void)
         }
 
         samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips);
+        s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
 
         return 0;
 }
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index dd192a27524d..0525cb3ef406 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -23,12 +23,15 @@
 #include <linux/fb.h>
 #include <linux/delay.h>
 #include <linux/input.h>
+#include <linux/pwm_backlight.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include <mach/map.h>
 #include <mach/regs-fb.h>
+#include <mach/regs-gpio.h>
+
 #include <video/platform_lcd.h>
 
 #include <asm/irq.h>
@@ -107,9 +110,6 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
 static void smdkc100_lcd_power_set(struct plat_lcd_data *pd,
                                    unsigned int power)
 {
-        /* backlight */
-        gpio_direction_output(S5PC100_GPD(0), power);
-
         if (power) {
                 /* module reset */
                 gpio_direction_output(S5PC100_GPH0(6), 1);
@@ -179,6 +179,45 @@ static struct samsung_keypad_platdata smdkc100_keypad_data __initdata = {
         .cols           = 8,
 };
 
+static int smdkc100_backlight_init(struct device *dev)
+{
+        int ret;
+
+        ret = gpio_request(S5PC100_GPD(0), "Backlight");
+        if (ret) {
+                printk(KERN_ERR "failed to request GPF for PWM-OUT0\n");
+                return ret;
+        }
+
+        /* Configure GPIO pin with S5PC100_GPD_TOUT_0 */
+        s3c_gpio_cfgpin(S5PC100_GPD(0), S3C_GPIO_SFN(2));
+
+        return 0;
+}
+
+static void smdkc100_backlight_exit(struct device *dev)
+{
+        s3c_gpio_cfgpin(S5PC100_GPD(0), S3C_GPIO_OUTPUT);
+        gpio_free(S5PC100_GPD(0));
+}
+
+static struct platform_pwm_backlight_data smdkc100_backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = 255,
+        .dft_brightness = 255,
+        .pwm_period_ns  = 78770,
+        .init           = smdkc100_backlight_init,
+        .exit           = smdkc100_backlight_exit,
+};
+
+static struct platform_device smdkc100_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent         = &s3c_device_timer[0].dev,
+                .platform_data  = &smdkc100_backlight_data,
+        },
+};
+
 static struct platform_device *smdkc100_devices[] __initdata = {
         &s3c_device_adc,
         &s3c_device_cfcon,
@@ -200,6 +239,8 @@ static struct platform_device *smdkc100_devices[] __initdata = {
         &s5p_device_fimc1,
         &s5p_device_fimc2,
         &s5pc100_device_spdif,
+        &s3c_device_timer[0],
+        &smdkc100_backlight_device,
 };
 
 static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
@@ -233,7 +274,6 @@ static void __init smdkc100_machine_init(void)
         s5pc100_spdif_setup_gpio(S5PC100_SPDIF_GPD);
 
         /* LCD init */
-        gpio_request(S5PC100_GPD(0), "GPD");
         gpio_request(S5PC100_GPH0(6), "GPH0");
         smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0);
         platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 53aabef1e9ce..37b5a97594a5 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -13,6 +13,7 @@ config CPU_S5PV210
         bool
         select S3C_PL330_DMA
         select S5P_EXT_INT
+        select S5P_HRT
         select S5PV210_PM if PM
         help
           Enable S5PV210 CPU support
@@ -53,6 +54,11 @@ config S5PV210_SETUP_SDHCI_GPIO
         help
           Common setup code for SDHCI gpio.
 
+config S5PV210_SETUP_FIMC
+        bool
+        help
+          Common setup code for the camera interfaces.
+
 menu "S5PC110 Machines"
 
 config MACH_AQUILA
@@ -130,6 +136,7 @@ config MACH_SMDKV210
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_IDE
         select SAMSUNG_DEV_KEYPAD
+        select SAMSUNG_DEV_PWM
         select SAMSUNG_DEV_TS
         select S5PV210_SETUP_FB_24BPP
         select S5PV210_SETUP_I2C1
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index ff1a0db57a2f..11f17907b4e8 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -31,6 +31,7 @@ obj-y				+= dev-audio.o
 obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
 
 obj-$(CONFIG_S5PV210_SETUP_FB_24BPP)    += setup-fb-24bpp.o
+obj-$(CONFIG_S5PV210_SETUP_FIMC)        += setup-fimc.o
 obj-$(CONFIG_S5PV210_SETUP_I2C1)        += setup-i2c1.o
 obj-$(CONFIG_S5PV210_SETUP_I2C2)        += setup-i2c2.o
 obj-$(CONFIG_S5PV210_SETUP_IDE)         += setup-ide.o
diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c
index ab673effd767..1ba20a703e05 100644
--- a/arch/arm/mach-s5pv210/gpiolib.c
+++ b/arch/arm/mach-s5pv210/gpiolib.c
@@ -281,6 +281,7 @@ static __init int s5pv210_gpiolib_init(void)
         }
 
         samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips);
+        s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
 
         return 0;
 }
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index 4c45b74def5f..78925c516346 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -146,6 +146,10 @@
 #define S5P_OM_STAT             S5P_CLKREG(0xE100)
 #define S5P_USB_PHY_CONTROL     S5P_CLKREG(0xE80C)
 #define S5P_DAC_CONTROL         S5P_CLKREG(0xE810)
+#define S5P_MIPI_DPHY_CONTROL(x) S5P_CLKREG(0xE814)
+#define S5P_MIPI_DPHY_ENABLE    (1 << 0)
+#define S5P_MIPI_DPHY_SRESETN   (1 << 1)
+#define S5P_MIPI_DPHY_MRESETN   (1 << 2)
 
 #define S5P_INFORM0             S5P_CLKREG(0xF000)
 #define S5P_INFORM1             S5P_CLKREG(0xF004)
@@ -161,7 +165,6 @@
 #define S5P_MDNIE_SEL           S5P_CLKREG(0x7008)
 #define S5P_MIPI_PHY_CON0       S5P_CLKREG(0x7200)
 #define S5P_MIPI_PHY_CON1       S5P_CLKREG(0x7204)
-#define S5P_MIPI_DPHY_CONTROL   S5P_CLKREG(0xE814)
 
 #define S5P_IDLE_CFG_TL_MASK    (3 << 30)
 #define S5P_IDLE_CFG_TM_MASK    (3 << 28)
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 557add4fc56c..4e1d8ff5ae59 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -39,6 +39,7 @@
 #include <plat/fb.h>
 #include <plat/fimc-core.h>
 #include <plat/sdhci.h>
+#include <plat/s5p-time.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define AQUILA_UCON_DEFAULT     (S3C2410_UCON_TXILEVEL |        \
@@ -296,13 +297,11 @@ static struct regulator_init_data aquila_ldo17_data = {
 };
 
 /* BUCK */
-static struct regulator_consumer_supply buck1_consumer[] = {
-        {       .supply = "vddarm", },
-};
+static struct regulator_consumer_supply buck1_consumer =
+        REGULATOR_SUPPLY("vddarm", NULL);
 
-static struct regulator_consumer_supply buck2_consumer[] = {
-        {       .supply = "vddint", },
-};
+static struct regulator_consumer_supply buck2_consumer =
+        REGULATOR_SUPPLY("vddint", NULL);
 
 static struct regulator_init_data aquila_buck1_data = {
         .constraints    = {
@@ -313,8 +312,8 @@ static struct regulator_init_data aquila_buck1_data = {
                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
                                   REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = ARRAY_SIZE(buck1_consumer),
-        .consumer_supplies      = buck1_consumer,
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &buck1_consumer,
 };
 
 static struct regulator_init_data aquila_buck2_data = {
@@ -326,8 +325,8 @@ static struct regulator_init_data aquila_buck2_data = {
                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
                                   REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = ARRAY_SIZE(buck2_consumer),
-        .consumer_supplies      = buck2_consumer,
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &buck2_consumer,
 };
 
 static struct regulator_init_data aquila_buck3_data = {
@@ -391,26 +390,14 @@ static struct max8998_platform_data aquila_max8998_pdata = {
 #endif
 
 static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
-        {
-                .dev_name       = "5-001a",
-                .supply         = "DBVDD",
-        }, {
-                .dev_name       = "5-001a",
-                .supply         = "AVDD2",
-        }, {
-                .dev_name       = "5-001a",
-                .supply         = "CPVDD",
-        },
+        REGULATOR_SUPPLY("DBVDD", "5-001a"),
+        REGULATOR_SUPPLY("AVDD2", "5-001a"),
+        REGULATOR_SUPPLY("CPVDD", "5-001a"),
 };
 
 static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
-        {
-                .dev_name       = "5-001a",
-                .supply         = "SPKVDD1",
-        }, {
-                .dev_name       = "5-001a",
-                .supply         = "SPKVDD2",
-        },
+        REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
+        REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
 };
 
 static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
@@ -459,15 +446,11 @@ static struct platform_device wm8994_fixed_voltage1 = {
         },
 };
 
-static struct regulator_consumer_supply wm8994_avdd1_supply = {
-        .dev_name       = "5-001a",
-        .supply         = "AVDD1",
-};
+static struct regulator_consumer_supply wm8994_avdd1_supply =
+        REGULATOR_SUPPLY("AVDD1", "5-001a");
 
-static struct regulator_consumer_supply wm8994_dcvdd_supply = {
-        .dev_name       = "5-001a",
-        .supply         = "DCVDD",
-};
+static struct regulator_consumer_supply wm8994_dcvdd_supply =
+        REGULATOR_SUPPLY("DCVDD", "5-001a");
 
 static struct regulator_init_data wm8994_ldo1_data = {
         .constraints    = {
@@ -664,6 +647,7 @@ static void __init aquila_map_io(void)
         s5p_init_io(NULL, 0, S5P_VA_CHIPID);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
+        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
 }
 
 static void __init aquila_machine_init(void)
@@ -698,5 +682,5 @@ MACHINE_START(AQUILA, "Aquila")
         .init_irq       = s5pv210_init_irq,
         .map_io         = aquila_map_io,
         .init_machine   = aquila_machine_init,
-        .timer          = &s3c24xx_timer,
+        .timer          = &s5p_timer,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 056f5c769b0a..243291722c66 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -45,6 +45,7 @@
 #include <plat/keypad.h>
 #include <plat/sdhci.h>
 #include <plat/clock.h>
+#include <plat/s5p-time.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define GONI_UCON_DEFAULT       (S3C2410_UCON_TXILEVEL |        \
@@ -108,6 +109,8 @@ static struct s3c_fb_pd_win goni_fb_win0 = {
         },
         .max_bpp        = 32,
         .default_bpp    = 16,
+        .virtual_x      = 480,
+        .virtual_y      = 2 * 800,
 };
 
 static struct s3c_fb_platdata goni_lcd_pdata __initdata = {
@@ -269,10 +272,30 @@ static void __init goni_tsp_init(void)
 /* MAX8998 regulators */
 #if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
 
+static struct regulator_consumer_supply goni_ldo3_consumers[] = {
+        REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
+};
+
 static struct regulator_consumer_supply goni_ldo5_consumers[] = {
         REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
 };
 
+static struct regulator_consumer_supply goni_ldo8_consumers[] = {
+        REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"),
+};
+
+static struct regulator_consumer_supply goni_ldo11_consumers[] = {
+        REGULATOR_SUPPLY("vddio", "0-0030"), /* "CAM_IO_2.8V" */
+};
+
+static struct regulator_consumer_supply goni_ldo13_consumers[] = {
+        REGULATOR_SUPPLY("vdda", "0-0030"), /* "CAM_A_2.8V" */
+};
+
+static struct regulator_consumer_supply goni_ldo14_consumers[] = {
+        REGULATOR_SUPPLY("vdd_core", "0-0030"), /* "CAM_CIF_1.8V" */
+};
+
 static struct regulator_init_data goni_ldo2_data = {
         .constraints    = {
                 .name           = "VALIVE_1.1V",
@@ -292,8 +315,10 @@ static struct regulator_init_data goni_ldo3_data = {
                 .min_uV         = 1100000,
                 .max_uV         = 1100000,
                 .apply_uV       = 1,
-                .always_on      = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
         },
+        .num_consumer_supplies = ARRAY_SIZE(goni_ldo3_consumers),
+        .consumer_supplies = goni_ldo3_consumers,
 };
 
 static struct regulator_init_data goni_ldo4_data = {
@@ -311,6 +336,7 @@ static struct regulator_init_data goni_ldo5_data = {
                 .min_uV         = 2800000,
                 .max_uV         = 2800000,
                 .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
         },
         .num_consumer_supplies = ARRAY_SIZE(goni_ldo5_consumers),
         .consumer_supplies = goni_ldo5_consumers,
@@ -341,8 +367,10 @@ static struct regulator_init_data goni_ldo8_data = {
                 .min_uV         = 3300000,
                 .max_uV         = 3300000,
                 .apply_uV       = 1,
-                .always_on      = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
         },
+        .num_consumer_supplies = ARRAY_SIZE(goni_ldo8_consumers),
+        .consumer_supplies = goni_ldo8_consumers,
 };
 
 static struct regulator_init_data goni_ldo9_data = {
@@ -351,7 +379,6 @@ static struct regulator_init_data goni_ldo9_data = {
                 .min_uV         = 2800000,
                 .max_uV         = 2800000,
                 .apply_uV       = 1,
-                .always_on      = 1,
         },
 };
 
@@ -371,8 +398,10 @@ static struct regulator_init_data goni_ldo11_data = {
                 .min_uV         = 2800000,
                 .max_uV         = 2800000,
                 .apply_uV       = 1,
-                .always_on      = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
         },
+        .num_consumer_supplies  = ARRAY_SIZE(goni_ldo11_consumers),
+        .consumer_supplies      = goni_ldo11_consumers,
 };
 
 static struct regulator_init_data goni_ldo12_data = {
@@ -381,7 +410,6 @@ static struct regulator_init_data goni_ldo12_data = {
                 .min_uV         = 1200000,
                 .max_uV         = 1200000,
                 .apply_uV       = 1,
-                .always_on      = 1,
         },
 };
 
@@ -391,8 +419,10 @@ static struct regulator_init_data goni_ldo13_data = {
                 .min_uV         = 2800000,
                 .max_uV         = 2800000,
                 .apply_uV       = 1,
-                .always_on      = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
         },
+        .num_consumer_supplies  = ARRAY_SIZE(goni_ldo13_consumers),
+        .consumer_supplies      = goni_ldo13_consumers,
 };
 
 static struct regulator_init_data goni_ldo14_data = {
@@ -401,8 +431,10 @@ static struct regulator_init_data goni_ldo14_data = {
                 .min_uV         = 1800000,
                 .max_uV         = 1800000,
                 .apply_uV       = 1,
-                .always_on      = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
         },
+        .num_consumer_supplies  = ARRAY_SIZE(goni_ldo14_consumers),
+        .consumer_supplies      = goni_ldo14_consumers,
 };
 
 static struct regulator_init_data goni_ldo15_data = {
@@ -411,7 +443,6 @@ static struct regulator_init_data goni_ldo15_data = {
                 .min_uV         = 3300000,
                 .max_uV         = 3300000,
                 .apply_uV       = 1,
-                .always_on      = 1,
         },
 };
 
@@ -421,7 +452,6 @@ static struct regulator_init_data goni_ldo16_data = {
                 .min_uV         = 1800000,
                 .max_uV         = 1800000,
                 .apply_uV       = 1,
-                .always_on      = 1,
         },
 };
 
@@ -436,13 +466,11 @@ static struct regulator_init_data goni_ldo17_data = {
 };
 
 /* BUCK */
-static struct regulator_consumer_supply buck1_consumer[] = {
-        {       .supply = "vddarm", },
-};
+static struct regulator_consumer_supply buck1_consumer =
+        REGULATOR_SUPPLY("vddarm", NULL);
 
-static struct regulator_consumer_supply buck2_consumer[] = {
-        {       .supply = "vddint", },
-};
+static struct regulator_consumer_supply buck2_consumer =
+        REGULATOR_SUPPLY("vddint", NULL);
 
 static struct regulator_init_data goni_buck1_data = {
         .constraints    = {
@@ -453,8 +481,8 @@ static struct regulator_init_data goni_buck1_data = {
                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
                                   REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = ARRAY_SIZE(buck1_consumer),
-        .consumer_supplies      = buck1_consumer,
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &buck1_consumer,
 };
 
 static struct regulator_init_data goni_buck2_data = {
@@ -466,8 +494,8 @@ static struct regulator_init_data goni_buck2_data = {
                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
                                   REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = ARRAY_SIZE(buck2_consumer),
-        .consumer_supplies      = buck2_consumer,
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &buck2_consumer,
 };
 
 static struct regulator_init_data goni_buck3_data = {
@@ -531,26 +559,14 @@ static struct max8998_platform_data goni_max8998_pdata = {
 #endif
 
 static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
-        {
-                .dev_name       = "5-001a",
-                .supply         = "DBVDD",
-        }, {
-                .dev_name       = "5-001a",
-                .supply         = "AVDD2",
-        }, {
-                .dev_name       = "5-001a",
-                .supply         = "CPVDD",
-        },
+        REGULATOR_SUPPLY("DBVDD", "5-001a"),
+        REGULATOR_SUPPLY("AVDD2", "5-001a"),
+        REGULATOR_SUPPLY("CPVDD", "5-001a"),
 };
 
 static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
-        {
-                .dev_name       = "5-001a",
-                .supply         = "SPKVDD1",
-        }, {
-                .dev_name       = "5-001a",
-                .supply         = "SPKVDD2",
-        },
+        REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
+        REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
 };
 
 static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
@@ -599,15 +615,11 @@ static struct platform_device wm8994_fixed_voltage1 = {
         },
 };
 
-static struct regulator_consumer_supply wm8994_avdd1_supply = {
-        .dev_name       = "5-001a",
-        .supply         = "AVDD1",
-};
+static struct regulator_consumer_supply wm8994_avdd1_supply =
+        REGULATOR_SUPPLY("AVDD1", "5-001a");
 
-static struct regulator_consumer_supply wm8994_dcvdd_supply = {
-        .dev_name       = "5-001a",
-        .supply         = "DCVDD",
-};
+static struct regulator_consumer_supply wm8994_dcvdd_supply =
+        REGULATOR_SUPPLY("DCVDD", "5-001a");
 
 static struct regulator_init_data wm8994_ldo1_data = {
         .constraints    = {
@@ -794,6 +806,7 @@ static struct platform_device *goni_devices[] __initdata = {
         &goni_i2c_gpio5,
         &mmc2_fixed_voltage,
         &goni_device_gpiokeys,
+        &s3c_device_i2c0,
         &s5p_device_fimc0,
         &s5p_device_fimc1,
         &s5p_device_fimc2,
@@ -823,6 +836,7 @@ static void __init goni_map_io(void)
         s5p_init_io(NULL, 0, S5P_VA_CHIPID);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs));
+        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
 }
 
 static void __init goni_machine_init(void)
@@ -830,6 +844,9 @@ static void __init goni_machine_init(void)
         /* Radio: call before I2C 1 registeration */
         goni_radio_init();
 
+        /* I2C0 */
+        s3c_i2c0_set_platdata(NULL);
+
         /* I2C1 */
         s3c_i2c1_set_platdata(NULL);
         i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
@@ -873,5 +890,5 @@ MACHINE_START(GONI, "GONI")
         .init_irq       = s5pv210_init_irq,
         .map_io         = goni_map_io,
         .init_machine   = goni_machine_init,
-        .timer          = &s3c24xx_timer,
+        .timer          = &s5p_timer,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index ce11a02eabf3..6c412c8ceccc 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -30,6 +30,7 @@
 #include <plat/ata.h>
 #include <plat/iic.h>
 #include <plat/pm.h>
+#include <plat/s5p-time.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDKC110_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
@@ -111,6 +112,7 @@ static void __init smdkc110_map_io(void)
         s5p_init_io(NULL, 0, S5P_VA_CHIPID);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
+        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
 }
 
 static void __init smdkc110_machine_init(void)
@@ -138,5 +140,5 @@ MACHINE_START(SMDKC110, "SMDKC110")
         .init_irq       = s5pv210_init_irq,
         .map_io         = smdkc110_map_io,
         .init_machine   = smdkc110_machine_init,
-        .timer          = &s3c24xx_timer,
+        .timer          = &s5p_timer,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index bc9fdb52a020..bc08ac42e7cc 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -18,6 +18,7 @@
 #include <linux/fb.h>
 #include <linux/gpio.h>
 #include <linux/delay.h>
+#include <linux/pwm_backlight.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -43,6 +44,8 @@
 #include <plat/keypad.h>
 #include <plat/pm.h>
 #include <plat/fb.h>
+#include <plat/gpio-cfg.h>
+#include <plat/s5p-time.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDKV210_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
@@ -208,6 +211,45 @@ static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
         .setup_gpio     = s5pv210_fb_gpio_setup_24bpp,
 };
 
+static int smdkv210_backlight_init(struct device *dev)
+{
+        int ret;
+
+        ret = gpio_request(S5PV210_GPD0(3), "Backlight");
+        if (ret) {
+                printk(KERN_ERR "failed to request GPD for PWM-OUT 3\n");
+                return ret;
+        }
+
+        /* Configure GPIO pin with S5PV210_GPD_0_3_TOUT_3 */
+        s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_SFN(2));
+
+        return 0;
+}
+
+static void smdkv210_backlight_exit(struct device *dev)
+{
+        s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_OUTPUT);
+        gpio_free(S5PV210_GPD0(3));
+}
+
+static struct platform_pwm_backlight_data smdkv210_backlight_data = {
+        .pwm_id         = 3,
+        .max_brightness = 255,
+        .dft_brightness = 255,
+        .pwm_period_ns  = 78770,
+        .init           = smdkv210_backlight_init,
+        .exit           = smdkv210_backlight_exit,
+};
+
+static struct platform_device smdkv210_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent         = &s3c_device_timer[3].dev,
+                .platform_data  = &smdkv210_backlight_data,
+        },
+};
+
 static struct platform_device *smdkv210_devices[] __initdata = {
         &s3c_device_adc,
         &s3c_device_cfcon,
@@ -229,6 +271,8 @@ static struct platform_device *smdkv210_devices[] __initdata = {
         &samsung_device_keypad,
         &smdkv210_dm9000,
         &smdkv210_lcd_lte480wv,
+        &s3c_device_timer[3],
+        &smdkv210_backlight_device,
 };
 
 static void __init smdkv210_dm9000_init(void)
@@ -272,6 +316,7 @@ static void __init smdkv210_map_io(void)
         s5p_init_io(NULL, 0, S5P_VA_CHIPID);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
+        s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
 }
 
 static void __init smdkv210_machine_init(void)
@@ -306,5 +351,5 @@ MACHINE_START(SMDKV210, "SMDKV210")
         .init_irq       = s5pv210_init_irq,
         .map_io         = smdkv210_map_io,
         .init_machine   = smdkv210_machine_init,
-        .timer          = &s3c24xx_timer,
+        .timer          = &s5p_timer,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
index 043c938806b0..925fc0dc6252 100644
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
@@ -27,6 +27,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/iic.h>
+#include <plat/s5p-time.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define TORBRECK_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
@@ -104,6 +105,7 @@ static void __init torbreck_map_io(void)
         s5p_init_io(NULL, 0, S5P_VA_CHIPID);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
+        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
 }
 
 static void __init torbreck_machine_init(void)
@@ -127,5 +129,5 @@ MACHINE_START(TORBRECK, "TORBRECK")
         .init_irq       = s5pv210_init_irq,
         .map_io         = torbreck_map_io,
         .init_machine   = torbreck_machine_init,
-        .timer          = &s3c24xx_timer,
+        .timer          = &s5p_timer,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/setup-fimc.c b/arch/arm/mach-s5pv210/setup-fimc.c
new file mode 100644
index 000000000000..54cc5b11be0b
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-fimc.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *
+ * S5PV210 camera interface GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+#include <plat/camport.h>
+
+int s5pv210_fimc_setup_gpio(enum s5p_camport_id id)
+{
+        u32 gpio8, gpio5;
+        int ret;
+
+        switch (id) {
+        case S5P_CAMPORT_A:
+                gpio8 = S5PV210_GPE0(0);
+                gpio5 = S5PV210_GPE1(0);
+                break;
+
+        case S5P_CAMPORT_B:
+                gpio8 = S5PV210_GPJ0(0);
+                gpio5 = S5PV210_GPJ1(0);
+                break;
+
+        default:
+                WARN(1, "Wrong camport id: %d\n", id);
+                return -EINVAL;
+        }
+
+        ret = s3c_gpio_cfgall_range(gpio8, 8, S3C_GPIO_SFN(2),
+                                    S3C_GPIO_PULL_UP);
+        if (ret)
+                return ret;
+
+        return s3c_gpio_cfgall_range(gpio5, 5, S3C_GPIO_SFN(2),
+                                     S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig
deleted file mode 100644
index b2a9acc5185f..000000000000
--- a/arch/arm/mach-s5pv310/Kconfig
+++ /dev/null
@@ -1,151 +0,0 @@
-# arch/arm/mach-s5pv310/Kconfig
-#
-# Copyright (c) 2010 Samsung Electronics Co., Ltd.
-#               http://www.samsung.com/
-#
-# Licensed under GPLv2
-
-# Configuration options for the S5PV310
-
-if ARCH_S5PV310
-
-config CPU_S5PV310
-        bool
-        select S3C_PL330_DMA
-        help
-          Enable S5PV310 CPU support
-
-config S5PV310_DEV_PD
-        bool
-        help
-          Compile in platform device definitions for Power Domain
-
-config S5PV310_SETUP_I2C1
-        bool
-        help
-          Common setup code for i2c bus 1.
-
-config S5PV310_SETUP_I2C2
-        bool
-        help
-          Common setup code for i2c bus 2.
-
-config S5PV310_SETUP_I2C3
-        bool
-        help
-          Common setup code for i2c bus 3.
-
-config S5PV310_SETUP_I2C4
-        bool
-        help
-          Common setup code for i2c bus 4.
-
-config S5PV310_SETUP_I2C5
-        bool
-        help
-          Common setup code for i2c bus 5.
-
-config S5PV310_SETUP_I2C6
-        bool
-        help
-          Common setup code for i2c bus 6.
-
-config S5PV310_SETUP_I2C7
-        bool
-        help
-          Common setup code for i2c bus 7.
-
-config S5PV310_SETUP_SDHCI
-        bool
-        select S5PV310_SETUP_SDHCI_GPIO
-        help
-          Internal helper functions for S5PV310 based SDHCI systems.
-
-config S5PV310_SETUP_SDHCI_GPIO
-        bool
-        help
-          Common setup code for SDHCI gpio.
-
-config S5PV310_DEV_SYSMMU
-        bool
-        help
-          Common setup code for SYSTEM MMU in S5PV310
-
-# machine support
-
-menu "S5PC210 Machines"
-
-config MACH_SMDKC210
-        bool "SMDKC210"
-        select CPU_S5PV310
-        select S3C_DEV_RTC
-        select S3C_DEV_WDT
-        select S3C_DEV_I2C1
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S5PV310_DEV_PD
-        select S5PV310_SETUP_I2C1
-        select S5PV310_SETUP_SDHCI
-        select S5PV310_DEV_SYSMMU
-        help
-          Machine support for Samsung SMDKC210
-          S5PC210(MCP) is one of package option of S5PV310
-
-config MACH_UNIVERSAL_C210
-        bool "Mobile UNIVERSAL_C210 Board"
-        select CPU_S5PV310
-        select S5P_DEV_ONENAND
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S5PV310_SETUP_SDHCI
-        select S3C_DEV_I2C1
-        select S5PV310_SETUP_I2C1
-        help
-          Machine support for Samsung Mobile Universal S5PC210 Reference
-          Board. S5PC210(MCP) is one of package option of S5PV310
-
-endmenu
-
-menu "S5PV310 Machines"
-
-config MACH_SMDKV310
-        bool "SMDKV310"
-        select CPU_S5PV310
-        select S3C_DEV_RTC
-        select S3C_DEV_WDT
-        select S3C_DEV_I2C1
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S5PV310_DEV_PD
-        select S5PV310_DEV_SYSMMU
-        select S5PV310_SETUP_I2C1
-        select S5PV310_SETUP_SDHCI
-        help
-          Machine support for Samsung SMDKV310
-
-endmenu
-
-comment "Configuration for HSMMC bus width"
-
-menu "Use 8-bit bus width"
-
-config S5PV310_SDHCI_CH0_8BIT
-        bool "Channel 0 with 8-bit bus"
-        help
-          Support HSMMC Channel 0 8-bit bus.
-          If selected, Channel 1 is disabled.
-
-config S5PV310_SDHCI_CH2_8BIT
-        bool "Channel 2 with 8-bit bus"
-        help
-          Support HSMMC Channel 2 8-bit bus.
-          If selected, Channel 3 is disabled.
-
-endmenu
-
-endif
diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
deleted file mode 100644
index 036fb383b830..000000000000
--- a/arch/arm/mach-s5pv310/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
-# arch/arm/mach-s5pv310/Makefile
-#
-# Copyright (c) 2010 Samsung Electronics Co., Ltd.
-#               http://www.samsung.com/
-#
-# Licensed under GPLv2
-
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-
-# Core support for S5PV310 system
-
-obj-$(CONFIG_CPU_S5PV310)       += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_S5PV310)       += setup-i2c0.o time.o gpiolib.o irq-eint.o dma.o
-obj-$(CONFIG_CPU_FREQ)          += cpufreq.o
-
-obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
-obj-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
-obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
-
-# machine support
-
-obj-$(CONFIG_MACH_SMDKC210)     += mach-smdkc210.o
-obj-$(CONFIG_MACH_SMDKV310)     += mach-smdkv310.o
-obj-$(CONFIG_MACH_UNIVERSAL_C210)       += mach-universal_c210.o
-
-# device support
-
-obj-y                                   += dev-audio.o
-obj-$(CONFIG_S5PV310_DEV_PD)            += dev-pd.o
-obj-$(CONFIG_S5PV310_DEV_SYSMMU)        += dev-sysmmu.o
-
-obj-$(CONFIG_S5PV310_SETUP_I2C1)        += setup-i2c1.o
-obj-$(CONFIG_S5PV310_SETUP_I2C2)        += setup-i2c2.o
-obj-$(CONFIG_S5PV310_SETUP_I2C3)        += setup-i2c3.o
-obj-$(CONFIG_S5PV310_SETUP_I2C4)        += setup-i2c4.o
-obj-$(CONFIG_S5PV310_SETUP_I2C5)        += setup-i2c5.o
-obj-$(CONFIG_S5PV310_SETUP_I2C6)        += setup-i2c6.o
-obj-$(CONFIG_S5PV310_SETUP_I2C7)        += setup-i2c7.o
-obj-$(CONFIG_S5PV310_SETUP_SDHCI)       += setup-sdhci.o
-obj-$(CONFIG_S5PV310_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5pv310/gpiolib.c b/arch/arm/mach-s5pv310/gpiolib.c
deleted file mode 100644
index 55217b8923ec..000000000000
--- a/arch/arm/mach-s5pv310/gpiolib.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/* linux/arch/arm/mach-s5pv310/gpiolib.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5PV310 - GPIOlib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <mach/map.h>
-
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
-
-static struct s3c_gpio_cfg gpio_cfg = {
-        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
-        .set_pull       = s3c_gpio_setpull_updown,
-        .get_pull       = s3c_gpio_getpull_updown,
-};
-
-static struct s3c_gpio_cfg gpio_cfg_noint = {
-        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
-        .set_pull       = s3c_gpio_setpull_updown,
-        .get_pull       = s3c_gpio_getpull_updown,
-};
-
-/*
- * Following are the gpio banks in v310.
- *
- * The 'config' member when left to NULL, is initialized to the default
- * structure gpio_cfg in the init function below.
- *
- * The 'base' member is also initialized in the init function below.
- * Note: The initialization of 'base' member of s3c_gpio_chip structure
- * uses the above macro and depends on the banks being listed in order here.
- */
-static struct s3c_gpio_chip s5pv310_gpio_part1_4bit[] = {
-        {
-                .chip   = {
-                        .base   = S5PV310_GPA0(0),
-                        .ngpio  = S5PV310_GPIO_A0_NR,
-                        .label  = "GPA0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPA1(0),
-                        .ngpio  = S5PV310_GPIO_A1_NR,
-                        .label  = "GPA1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPB(0),
-                        .ngpio  = S5PV310_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPC0(0),
-                        .ngpio  = S5PV310_GPIO_C0_NR,
-                        .label  = "GPC0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPC1(0),
-                        .ngpio  = S5PV310_GPIO_C1_NR,
-                        .label  = "GPC1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPD0(0),
-                        .ngpio  = S5PV310_GPIO_D0_NR,
-                        .label  = "GPD0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPD1(0),
-                        .ngpio  = S5PV310_GPIO_D1_NR,
-                        .label  = "GPD1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPE0(0),
-                        .ngpio  = S5PV310_GPIO_E0_NR,
-                        .label  = "GPE0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPE1(0),
-                        .ngpio  = S5PV310_GPIO_E1_NR,
-                        .label  = "GPE1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPE2(0),
-                        .ngpio  = S5PV310_GPIO_E2_NR,
-                        .label  = "GPE2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPE3(0),
-                        .ngpio  = S5PV310_GPIO_E3_NR,
-                        .label  = "GPE3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPE4(0),
-                        .ngpio  = S5PV310_GPIO_E4_NR,
-                        .label  = "GPE4",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPF0(0),
-                        .ngpio  = S5PV310_GPIO_F0_NR,
-                        .label  = "GPF0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPF1(0),
-                        .ngpio  = S5PV310_GPIO_F1_NR,
-                        .label  = "GPF1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPF2(0),
-                        .ngpio  = S5PV310_GPIO_F2_NR,
-                        .label  = "GPF2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPF3(0),
-                        .ngpio  = S5PV310_GPIO_F3_NR,
-                        .label  = "GPF3",
-                },
-        },
-};
-
-static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
-        {
-                .chip   = {
-                        .base   = S5PV310_GPJ0(0),
-                        .ngpio  = S5PV310_GPIO_J0_NR,
-                        .label  = "GPJ0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPJ1(0),
-                        .ngpio  = S5PV310_GPIO_J1_NR,
-                        .label  = "GPJ1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPK0(0),
-                        .ngpio  = S5PV310_GPIO_K0_NR,
-                        .label  = "GPK0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPK1(0),
-                        .ngpio  = S5PV310_GPIO_K1_NR,
-                        .label  = "GPK1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPK2(0),
-                        .ngpio  = S5PV310_GPIO_K2_NR,
-                        .label  = "GPK2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPK3(0),
-                        .ngpio  = S5PV310_GPIO_K3_NR,
-                        .label  = "GPK3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPL0(0),
-                        .ngpio  = S5PV310_GPIO_L0_NR,
-                        .label  = "GPL0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPL1(0),
-                        .ngpio  = S5PV310_GPIO_L1_NR,
-                        .label  = "GPL1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV310_GPL2(0),
-                        .ngpio  = S5PV310_GPIO_L2_NR,
-                        .label  = "GPL2",
-                },
-        }, {
-                .base   = (S5P_VA_GPIO2 + 0xC00),
-                .config = &gpio_cfg_noint,
-                .irq_base = IRQ_EINT(0),
-                .chip   = {
-                        .base   = S5PV310_GPX0(0),
-                        .ngpio  = S5PV310_GPIO_X0_NR,
-                        .label  = "GPX0",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO2 + 0xC20),
-                .config = &gpio_cfg_noint,
-                .irq_base = IRQ_EINT(8),
-                .chip   = {
-                        .base   = S5PV310_GPX1(0),
-                        .ngpio  = S5PV310_GPIO_X1_NR,
-                        .label  = "GPX1",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO2 + 0xC40),
-                .config = &gpio_cfg_noint,
-                .irq_base = IRQ_EINT(16),
-                .chip   = {
-                        .base   = S5PV310_GPX2(0),
-                        .ngpio  = S5PV310_GPIO_X2_NR,
-                        .label  = "GPX2",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO2 + 0xC60),
-                .config = &gpio_cfg_noint,
-                .irq_base = IRQ_EINT(24),
-                .chip   = {
-                        .base   = S5PV310_GPX3(0),
-                        .ngpio  = S5PV310_GPIO_X3_NR,
-                        .label  = "GPX3",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        },
-};
-
-static struct s3c_gpio_chip s5pv310_gpio_part3_4bit[] = {
-        {
-                .chip   = {
-                        .base   = S5PV310_GPZ(0),
-                        .ngpio  = S5PV310_GPIO_Z_NR,
-                        .label  = "GPZ",
-                },
-        },
-};
-
-static __init int s5pv310_gpiolib_init(void)
-{
-        struct s3c_gpio_chip *chip;
-        int i;
-        int nr_chips;
-
-        /* GPIO part 1 */
-
-        chip = s5pv310_gpio_part1_4bit;
-        nr_chips = ARRAY_SIZE(s5pv310_gpio_part1_4bit);
-
-        for (i = 0; i < nr_chips; i++, chip++) {
-                if (chip->config == NULL)
-                        chip->config = &gpio_cfg;
-                if (chip->base == NULL)
-                        chip->base = S5P_VA_GPIO1 + (i) * 0x20;
-        }
-
-        samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part1_4bit, nr_chips);
-
-        /* GPIO part 2 */
-
-        chip = s5pv310_gpio_part2_4bit;
-        nr_chips = ARRAY_SIZE(s5pv310_gpio_part2_4bit);
-
-        for (i = 0; i < nr_chips; i++, chip++) {
-                if (chip->config == NULL)
-                        chip->config = &gpio_cfg;
-                if (chip->base == NULL)
-                        chip->base = S5P_VA_GPIO2 + (i) * 0x20;
-        }
-
-        samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part2_4bit, nr_chips);
-
-        /* GPIO part 3 */
-
-        chip = s5pv310_gpio_part3_4bit;
-        nr_chips = ARRAY_SIZE(s5pv310_gpio_part3_4bit);
-
-        for (i = 0; i < nr_chips; i++, chip++) {
-                if (chip->config == NULL)
-                        chip->config = &gpio_cfg;
-                if (chip->base == NULL)
-                        chip->base = S5P_VA_GPIO3 + (i) * 0x20;
-        }
-
-        samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part3_4bit, nr_chips);
-
-        return 0;
-}
-core_initcall(s5pv310_gpiolib_init);
diff --git a/arch/arm/mach-s5pv310/include/mach/gpio.h b/arch/arm/mach-s5pv310/include/mach/gpio.h
deleted file mode 100644
index 20cb80c23466..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/gpio.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/gpio.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV310 - GPIO lib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H __FILE__
-
-#define gpio_get_value  __gpio_get_value
-#define gpio_set_value  __gpio_set_value
-#define gpio_cansleep   __gpio_cansleep
-#define gpio_to_irq     __gpio_to_irq
-
-/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
-
-/* GPIO bank sizes */
-#define S5PV310_GPIO_A0_NR      (8)
-#define S5PV310_GPIO_A1_NR      (6)
-#define S5PV310_GPIO_B_NR       (8)
-#define S5PV310_GPIO_C0_NR      (5)
-#define S5PV310_GPIO_C1_NR      (5)
-#define S5PV310_GPIO_D0_NR      (4)
-#define S5PV310_GPIO_D1_NR      (4)
-#define S5PV310_GPIO_E0_NR      (5)
-#define S5PV310_GPIO_E1_NR      (8)
-#define S5PV310_GPIO_E2_NR      (6)
-#define S5PV310_GPIO_E3_NR      (8)
-#define S5PV310_GPIO_E4_NR      (8)
-#define S5PV310_GPIO_F0_NR      (8)
-#define S5PV310_GPIO_F1_NR      (8)
-#define S5PV310_GPIO_F2_NR      (8)
-#define S5PV310_GPIO_F3_NR      (6)
-#define S5PV310_GPIO_J0_NR      (8)
-#define S5PV310_GPIO_J1_NR      (5)
-#define S5PV310_GPIO_K0_NR      (7)
-#define S5PV310_GPIO_K1_NR      (7)
-#define S5PV310_GPIO_K2_NR      (7)
-#define S5PV310_GPIO_K3_NR      (7)
-#define S5PV310_GPIO_L0_NR      (8)
-#define S5PV310_GPIO_L1_NR      (3)
-#define S5PV310_GPIO_L2_NR      (8)
-#define S5PV310_GPIO_X0_NR      (8)
-#define S5PV310_GPIO_X1_NR      (8)
-#define S5PV310_GPIO_X2_NR      (8)
-#define S5PV310_GPIO_X3_NR      (8)
-#define S5PV310_GPIO_Z_NR       (7)
-
-/* GPIO bank numbers */
-
-#define S5PV310_GPIO_NEXT(__gpio) \
-        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
-
-enum s5p_gpio_number {
-        S5PV310_GPIO_A0_START   = 0,
-        S5PV310_GPIO_A1_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_A0),
-        S5PV310_GPIO_B_START    = S5PV310_GPIO_NEXT(S5PV310_GPIO_A1),
-        S5PV310_GPIO_C0_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_B),
-        S5PV310_GPIO_C1_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_C0),
-        S5PV310_GPIO_D0_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_C1),
-        S5PV310_GPIO_D1_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_D0),
-        S5PV310_GPIO_E0_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_D1),
-        S5PV310_GPIO_E1_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_E0),
-        S5PV310_GPIO_E2_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_E1),
-        S5PV310_GPIO_E3_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_E2),
-        S5PV310_GPIO_E4_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_E3),
-        S5PV310_GPIO_F0_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_E4),
-        S5PV310_GPIO_F1_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_F0),
-        S5PV310_GPIO_F2_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_F1),
-        S5PV310_GPIO_F3_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_F2),
-        S5PV310_GPIO_J0_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_F3),
-        S5PV310_GPIO_J1_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_J0),
-        S5PV310_GPIO_K0_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_J1),
-        S5PV310_GPIO_K1_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_K0),
-        S5PV310_GPIO_K2_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_K1),
-        S5PV310_GPIO_K3_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_K2),
-        S5PV310_GPIO_L0_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_K3),
-        S5PV310_GPIO_L1_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_L0),
-        S5PV310_GPIO_L2_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_L1),
-        S5PV310_GPIO_X0_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_L2),
-        S5PV310_GPIO_X1_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_X0),
-        S5PV310_GPIO_X2_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_X1),
-        S5PV310_GPIO_X3_START   = S5PV310_GPIO_NEXT(S5PV310_GPIO_X2),
-        S5PV310_GPIO_Z_START    = S5PV310_GPIO_NEXT(S5PV310_GPIO_X3),
-};
-
-/* S5PV310 GPIO number definitions */
-#define S5PV310_GPA0(_nr)       (S5PV310_GPIO_A0_START + (_nr))
-#define S5PV310_GPA1(_nr)       (S5PV310_GPIO_A1_START + (_nr))
-#define S5PV310_GPB(_nr)        (S5PV310_GPIO_B_START + (_nr))
-#define S5PV310_GPC0(_nr)       (S5PV310_GPIO_C0_START + (_nr))
-#define S5PV310_GPC1(_nr)       (S5PV310_GPIO_C1_START + (_nr))
-#define S5PV310_GPD0(_nr)       (S5PV310_GPIO_D0_START + (_nr))
-#define S5PV310_GPD1(_nr)       (S5PV310_GPIO_D1_START + (_nr))
-#define S5PV310_GPE0(_nr)       (S5PV310_GPIO_E0_START + (_nr))
-#define S5PV310_GPE1(_nr)       (S5PV310_GPIO_E1_START + (_nr))
-#define S5PV310_GPE2(_nr)       (S5PV310_GPIO_E2_START + (_nr))
-#define S5PV310_GPE3(_nr)       (S5PV310_GPIO_E3_START + (_nr))
-#define S5PV310_GPE4(_nr)       (S5PV310_GPIO_E4_START + (_nr))
-#define S5PV310_GPF0(_nr)       (S5PV310_GPIO_F0_START + (_nr))
-#define S5PV310_GPF1(_nr)       (S5PV310_GPIO_F1_START + (_nr))
-#define S5PV310_GPF2(_nr)       (S5PV310_GPIO_F2_START + (_nr))
-#define S5PV310_GPF3(_nr)       (S5PV310_GPIO_F3_START + (_nr))
-#define S5PV310_GPJ0(_nr)       (S5PV310_GPIO_J0_START + (_nr))
-#define S5PV310_GPJ1(_nr)       (S5PV310_GPIO_J1_START + (_nr))
-#define S5PV310_GPK0(_nr)       (S5PV310_GPIO_K0_START + (_nr))
-#define S5PV310_GPK1(_nr)       (S5PV310_GPIO_K1_START + (_nr))
-#define S5PV310_GPK2(_nr)       (S5PV310_GPIO_K2_START + (_nr))
-#define S5PV310_GPK3(_nr)       (S5PV310_GPIO_K3_START + (_nr))
-#define S5PV310_GPL0(_nr)       (S5PV310_GPIO_L0_START + (_nr))
-#define S5PV310_GPL1(_nr)       (S5PV310_GPIO_L1_START + (_nr))
-#define S5PV310_GPL2(_nr)       (S5PV310_GPIO_L2_START + (_nr))
-#define S5PV310_GPX0(_nr)       (S5PV310_GPIO_X0_START + (_nr))
-#define S5PV310_GPX1(_nr)       (S5PV310_GPIO_X1_START + (_nr))
-#define S5PV310_GPX2(_nr)       (S5PV310_GPIO_X2_START + (_nr))
-#define S5PV310_GPX3(_nr)       (S5PV310_GPIO_X3_START + (_nr))
-#define S5PV310_GPZ(_nr)        (S5PV310_GPIO_Z_START + (_nr))
-
-/* the end of the S5PV310 specific gpios */
-#define S5PV310_GPIO_END        (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + 1)
-#define S3C_GPIO_END            S5PV310_GPIO_END
-
-/* define the number of gpios we need to the one after the GPZ() range */
-#define ARCH_NR_GPIOS           (S5PV310_GPZ(S5PV310_GPIO_Z_NR) +       \
-                                 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
-
-#include <asm-generic/gpio.h>
-
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
deleted file mode 100644
index 901657fa7a12..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/map.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV310 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MAP_H
-#define __ASM_ARCH_MAP_H __FILE__
-
-#include <plat/map-base.h>
-
-/*
- * S5PV310 UART offset is 0x10000 but the older S5P SoCs are 0x400.
- * So need to define it, and here is to avoid redefinition warning.
- */
-#define S3C_UART_OFFSET                 (0x10000)
-
-#include <plat/map-s5p.h>
-
-#define S5PV310_PA_SYSRAM               0x02025000
-
-#define S5PV310_PA_I2S0                 0x03830000
-#define S5PV310_PA_I2S1                 0xE3100000
-#define S5PV310_PA_I2S2                 0xE2A00000
-
-#define S5PV310_PA_PCM0                 0x03840000
-#define S5PV310_PA_PCM1                 0x13980000
-#define S5PV310_PA_PCM2                 0x13990000
-
-#define S5PV310_PA_SROM_BANK(x)         (0x04000000 + ((x) * 0x01000000))
-
-#define S5PC210_PA_ONENAND              0x0C000000
-#define S5PC210_PA_ONENAND_DMA          0x0C600000
-
-#define S5PV310_PA_CHIPID               0x10000000
-
-#define S5PV310_PA_SYSCON               0x10010000
-#define S5PV310_PA_PMU                  0x10020000
-#define S5PV310_PA_CMU                  0x10030000
-
-#define S5PV310_PA_WATCHDOG             0x10060000
-#define S5PV310_PA_RTC                  0x10070000
-
-#define S5PV310_PA_DMC0                 0x10400000
-
-#define S5PV310_PA_COMBINER             0x10448000
-
-#define S5PV310_PA_COREPERI             0x10500000
-#define S5PV310_PA_GIC_CPU              0x10500100
-#define S5PV310_PA_TWD                  0x10500600
-#define S5PV310_PA_GIC_DIST             0x10501000
-#define S5PV310_PA_L2CC                 0x10502000
-
-#define S5PV310_PA_MDMA                 0x10810000
-#define S5PV310_PA_PDMA0                0x12680000
-#define S5PV310_PA_PDMA1                0x12690000
-
-#define S5PV310_PA_SYSMMU_MDMA          0x10A40000
-#define S5PV310_PA_SYSMMU_SSS           0x10A50000
-#define S5PV310_PA_SYSMMU_FIMC0         0x11A20000
-#define S5PV310_PA_SYSMMU_FIMC1         0x11A30000
-#define S5PV310_PA_SYSMMU_FIMC2         0x11A40000
-#define S5PV310_PA_SYSMMU_FIMC3         0x11A50000
-#define S5PV310_PA_SYSMMU_JPEG          0x11A60000
-#define S5PV310_PA_SYSMMU_FIMD0         0x11E20000
-#define S5PV310_PA_SYSMMU_FIMD1         0x12220000
-#define S5PV310_PA_SYSMMU_PCIe          0x12620000
-#define S5PV310_PA_SYSMMU_G2D           0x12A20000
-#define S5PV310_PA_SYSMMU_ROTATOR       0x12A30000
-#define S5PV310_PA_SYSMMU_MDMA2         0x12A40000
-#define S5PV310_PA_SYSMMU_TV            0x12E20000
-#define S5PV310_PA_SYSMMU_MFC_L         0x13620000
-#define S5PV310_PA_SYSMMU_MFC_R         0x13630000
-
-#define S5PV310_PA_GPIO1                0x11400000
-#define S5PV310_PA_GPIO2                0x11000000
-#define S5PV310_PA_GPIO3                0x03860000
-
-#define S5PV310_PA_MIPI_CSIS0           0x11880000
-#define S5PV310_PA_MIPI_CSIS1           0x11890000
-
-#define S5PV310_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
-
-#define S5PV310_PA_SROMC                0x12570000
-
-#define S5PV310_PA_UART                 0x13800000
-
-#define S5PV310_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
-
-#define S5PV310_PA_AC97                 0x139A0000
-
-#define S5PV310_PA_TIMER                0x139D0000
-
-#define S5PV310_PA_SDRAM                0x40000000
-
-#define S5PV310_PA_SPDIF                0xE1100000
-
-/* Compatibiltiy Defines */
-
-#define S3C_PA_HSMMC0                   S5PV310_PA_HSMMC(0)
-#define S3C_PA_HSMMC1                   S5PV310_PA_HSMMC(1)
-#define S3C_PA_HSMMC2                   S5PV310_PA_HSMMC(2)
-#define S3C_PA_HSMMC3                   S5PV310_PA_HSMMC(3)
-#define S3C_PA_IIC                      S5PV310_PA_IIC(0)
-#define S3C_PA_IIC1                     S5PV310_PA_IIC(1)
-#define S3C_PA_IIC2                     S5PV310_PA_IIC(2)
-#define S3C_PA_IIC3                     S5PV310_PA_IIC(3)
-#define S3C_PA_IIC4                     S5PV310_PA_IIC(4)
-#define S3C_PA_IIC5                     S5PV310_PA_IIC(5)
-#define S3C_PA_IIC6                     S5PV310_PA_IIC(6)
-#define S3C_PA_IIC7                     S5PV310_PA_IIC(7)
-#define S3C_PA_RTC                      S5PV310_PA_RTC
-#define S3C_PA_WDT                      S5PV310_PA_WATCHDOG
-
-#define S5P_PA_CHIPID                   S5PV310_PA_CHIPID
-#define S5P_PA_MIPI_CSIS0               S5PV310_PA_MIPI_CSIS0
-#define S5P_PA_MIPI_CSIS1               S5PV310_PA_MIPI_CSIS1
-#define S5P_PA_ONENAND                  S5PC210_PA_ONENAND
-#define S5P_PA_ONENAND_DMA              S5PC210_PA_ONENAND_DMA
-#define S5P_PA_SDRAM                    S5PV310_PA_SDRAM
-#define S5P_PA_SROMC                    S5PV310_PA_SROMC
-#define S5P_PA_SYSCON                   S5PV310_PA_SYSCON
-#define S5P_PA_TIMER                    S5PV310_PA_TIMER
-
-/* UART */
-
-#define S3C_PA_UART                     S5PV310_PA_UART
-
-#define S5P_PA_UART(x)                  (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_PA_UART0                    S5P_PA_UART(0)
-#define S5P_PA_UART1                    S5P_PA_UART(1)
-#define S5P_PA_UART2                    S5P_PA_UART(2)
-#define S5P_PA_UART3                    S5P_PA_UART(3)
-#define S5P_PA_UART4                    S5P_PA_UART(4)
-
-#define S5P_SZ_UART                     SZ_256
-
-#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-gpio.h b/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
deleted file mode 100644
index 82e9e0c9d452..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5PV310 - GPIO (including EINT) register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_GPIO_H
-#define __ASM_ARCH_REGS_GPIO_H __FILE__
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-
-#define S5PV310_EINT40CON               (S5P_VA_GPIO2 + 0xE00)
-#define S5P_EINT_CON(x)                 (S5PV310_EINT40CON + ((x) * 0x4))
-
-#define S5PV310_EINT40FLTCON0           (S5P_VA_GPIO2 + 0xE80)
-#define S5P_EINT_FLTCON(x)              (S5PV310_EINT40FLTCON0 + ((x) * 0x4))
-
-#define S5PV310_EINT40MASK              (S5P_VA_GPIO2 + 0xF00)
-#define S5P_EINT_MASK(x)                (S5PV310_EINT40MASK + ((x) * 0x4))
-
-#define S5PV310_EINT40PEND              (S5P_VA_GPIO2 + 0xF40)
-#define S5P_EINT_PEND(x)                (S5PV310_EINT40PEND + ((x) * 0x4))
-
-#define EINT_REG_NR(x)                  (EINT_OFFSET(x) >> 3)
-
-#define eint_irq_to_bit(irq)            (1 << (EINT_OFFSET(irq) & 0x7))
-
-#define EINT_MODE                       S3C_GPIO_SFN(0xf)
-
-#define EINT_GPIO_0(x)                  S5PV310_GPX0(x)
-#define EINT_GPIO_1(x)                  S5PV310_GPX1(x)
-#define EINT_GPIO_2(x)                  S5PV310_GPX2(x)
-#define EINT_GPIO_3(x)                  S5PV310_GPX3(x)
-
-#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h b/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
deleted file mode 100644
index fb333d0f6073..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5PV310 - Power management unit definition
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_PMU_H
-#define __ASM_ARCH_REGS_PMU_H __FILE__
-
-#include <mach/map.h>
-
-#define S5P_PMUREG(x)                   (S5P_VA_PMU + (x))
-
-#define S5P_PMU_CAM_CONF                S5P_PMUREG(0x3C00)
-#define S5P_PMU_TV_CONF         S5P_PMUREG(0x3C20)
-#define S5P_PMU_MFC_CONF                S5P_PMUREG(0x3C40)
-#define S5P_PMU_G3D_CONF                S5P_PMUREG(0x3C60)
-#define S5P_PMU_LCD0_CONF               S5P_PMUREG(0x3C80)
-#define S5P_PMU_LCD1_CONF               S5P_PMUREG(0x3CA0)
-#define S5P_PMU_GPS_CONF                S5P_PMUREG(0x3CE0)
-
-#define S5P_INT_LOCAL_PWR_EN            0x7
-
-#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/sysmmu.h b/arch/arm/mach-s5pv310/include/mach/sysmmu.h
deleted file mode 100644
index 598fc5c9211b..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/sysmmu.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/* linux/arch/arm/mach-s5pv310/include/mach/sysmmu.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Samsung sysmmu driver for S5PV310
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARM_ARCH_SYSMMU_H
-#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
-
-#define S5PV310_SYSMMU_TOTAL_IPNUM      16
-#define S5P_SYSMMU_TOTAL_IPNUM          S5PV310_SYSMMU_TOTAL_IPNUM
-
-enum s5pv310_sysmmu_ips {
-        SYSMMU_MDMA,
-        SYSMMU_SSS,
-        SYSMMU_FIMC0,
-        SYSMMU_FIMC1,
-        SYSMMU_FIMC2,
-        SYSMMU_FIMC3,
-        SYSMMU_JPEG,
-        SYSMMU_FIMD0,
-        SYSMMU_FIMD1,
-        SYSMMU_PCIe,
-        SYSMMU_G2D,
-        SYSMMU_ROTATOR,
-        SYSMMU_MDMA2,
-        SYSMMU_TV,
-        SYSMMU_MFC_L,
-        SYSMMU_MFC_R,
-};
-
-static char *sysmmu_ips_name[S5PV310_SYSMMU_TOTAL_IPNUM] = {
-        "SYSMMU_MDMA"   ,
-        "SYSMMU_SSS"    ,
-        "SYSMMU_FIMC0"  ,
-        "SYSMMU_FIMC1"  ,
-        "SYSMMU_FIMC2"  ,
-        "SYSMMU_FIMC3"  ,
-        "SYSMMU_JPEG"   ,
-        "SYSMMU_FIMD0"  ,
-        "SYSMMU_FIMD1"  ,
-        "SYSMMU_PCIe"   ,
-        "SYSMMU_G2D"    ,
-        "SYSMMU_ROTATOR",
-        "SYSMMU_MDMA2"  ,
-        "SYSMMU_TV"     ,
-        "SYSMMU_MFC_L"  ,
-        "SYSMMU_MFC_R"  ,
-};
-
-typedef enum s5pv310_sysmmu_ips sysmmu_ips;
-
-struct sysmmu_tt_info {
-        unsigned long *pgd;
-        unsigned long pgd_paddr;
-        unsigned long *pte;
-};
-
-struct sysmmu_controller {
-        const char              *name;
-
-        /* channels registers */
-        void __iomem            *regs;
-
-        /* channel irq */
-        unsigned int            irq;
-
-        sysmmu_ips              ips;
-
-        /* Translation Table Info. */
-        struct sysmmu_tt_info   *tt_info;
-
-        struct resource         *mem;
-        struct device           *dev;
-
-        /* SysMMU controller enable - true : enable */
-        bool                    enable;
-};
-
-/**
- * s5p_sysmmu_enable() - enable system mmu of ip
- * @ips: The ip connected system mmu.
- *
- * This function enable system mmu to transfer address
- * from virtual address to physical address
- */
-int s5p_sysmmu_enable(sysmmu_ips ips);
-
-/**
- * s5p_sysmmu_disable() - disable sysmmu mmu of ip
- * @ips: The ip connected system mmu.
- *
- * This function disable system mmu to transfer address
- * from virtual address to physical address
- */
-int s5p_sysmmu_disable(sysmmu_ips ips);
-
-/**
- * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
- * @ips: The ip connected system mmu.
- * @pgd: The page table base address.
- *
- * This function set page table base address
- * When system mmu transfer address from virtaul address to physical address,
- * system mmu refer address information from page table
- */
-int s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
-
-/**
- * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
- * @ips: The ip connected system mmu.
- *
- * This function flush all TLB entry in system mmu
- */
-int s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
-#endif /* __ASM_ARM_ARCH_SYSMMU_H */
diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c
deleted file mode 100644
index 36bc3cf825e3..000000000000
--- a/arch/arm/mach-s5pv310/mach-universal_c210.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/* linux/arch/arm/mach-s5pv310/mach-universal_c210.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/mmc/host.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <plat/regs-serial.h>
-#include <plat/s5pv310.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/sdhci.h>
-
-#include <mach/map.h>
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define UNIVERSAL_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
-
-#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG256 |      \
-                                 S5PV210_UFCON_RXTRIG256)
-
-static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .ucon           = UNIVERSAL_UCON_DEFAULT,
-                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .ucon           = UNIVERSAL_UCON_DEFAULT,
-                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .ucon           = UNIVERSAL_UCON_DEFAULT,
-                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .ucon           = UNIVERSAL_UCON_DEFAULT,
-                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-        },
-};
-
-static struct gpio_keys_button universal_gpio_keys_tables[] = {
-        {
-                .code                   = KEY_VOLUMEUP,
-                .gpio                   = S5PV310_GPX2(0),      /* XEINT16 */
-                .desc                   = "gpio-keys: KEY_VOLUMEUP",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_VOLUMEDOWN,
-                .gpio                   = S5PV310_GPX2(1),      /* XEINT17 */
-                .desc                   = "gpio-keys: KEY_VOLUMEDOWN",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_CONFIG,
-                .gpio                   = S5PV310_GPX2(2),      /* XEINT18 */
-                .desc                   = "gpio-keys: KEY_CONFIG",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_CAMERA,
-                .gpio                   = S5PV310_GPX2(3),      /* XEINT19 */
-                .desc                   = "gpio-keys: KEY_CAMERA",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_OK,
-                .gpio                   = S5PV310_GPX3(5),      /* XEINT29 */
-                .desc                   = "gpio-keys: KEY_OK",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        },
-};
-
-static struct gpio_keys_platform_data universal_gpio_keys_data = {
-        .buttons        = universal_gpio_keys_tables,
-        .nbuttons       = ARRAY_SIZE(universal_gpio_keys_tables),
-};
-
-static struct platform_device universal_gpio_keys = {
-        .name                   = "gpio-keys",
-        .dev                    = {
-                .platform_data  = &universal_gpio_keys_data,
-        },
-};
-
-/* eMMC */
-static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
-        .max_width              = 8,
-        .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-                                MMC_CAP_DISABLE),
-        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-static struct regulator_consumer_supply mmc0_supplies[] = {
-        REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
-};
-
-static struct regulator_init_data mmc0_fixed_voltage_init_data = {
-        .constraints            = {
-                .name           = "VMEM_VDD_2.8V",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(mmc0_supplies),
-        .consumer_supplies      = mmc0_supplies,
-};
-
-static struct fixed_voltage_config mmc0_fixed_voltage_config = {
-        .supply_name            = "MASSMEMORY_EN",
-        .microvolts             = 2800000,
-        .gpio                   = S5PV310_GPE1(3),
-        .enable_high            = true,
-        .init_data              = &mmc0_fixed_voltage_init_data,
-};
-
-static struct platform_device mmc0_fixed_voltage = {
-        .name                   = "reg-fixed-voltage",
-        .id                     = 0,
-        .dev                    = {
-                .platform_data  = &mmc0_fixed_voltage_config,
-        },
-};
-
-/* SD */
-static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
-        .max_width              = 4,
-        .host_caps              = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-                                MMC_CAP_DISABLE,
-        .ext_cd_gpio            = S5PV310_GPX3(4),      /* XEINT_28 */
-        .ext_cd_gpio_invert     = 1,
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-/* WiFi */
-static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
-        .max_width              = 4,
-        .host_caps              = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-                                MMC_CAP_DISABLE,
-        .cd_type                = S3C_SDHCI_CD_EXTERNAL,
-};
-
-static void __init universal_sdhci_init(void)
-{
-        s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
-        s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
-        s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
-}
-
-/* I2C0 */
-static struct i2c_board_info i2c0_devs[] __initdata = {
-        /* Camera, To be updated */
-};
-
-/* I2C1 */
-static struct i2c_board_info i2c1_devs[] __initdata = {
-        /* Gyro, To be updated */
-};
-
-static struct platform_device *universal_devices[] __initdata = {
-        /* Samsung Platform Devices */
-        &mmc0_fixed_voltage,
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-
-        /* Universal Devices */
-        &universal_gpio_keys,
-        &s5p_device_onenand,
-};
-
-static void __init universal_map_io(void)
-{
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
-        s3c24xx_init_clocks(24000000);
-        s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
-}
-
-static void __init universal_machine_init(void)
-{
-        universal_sdhci_init();
-
-        i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
-        i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
-
-        /* Last */
-        platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
-}
-
-MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
-        /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
-        .boot_params    = S5P_PA_SDRAM + 0x100,
-        .init_irq       = s5pv310_init_irq,
-        .map_io         = universal_map_io,
-        .init_machine   = universal_machine_init,
-        .timer          = &s5pv310_timer,
-MACHINE_END
diff --git a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
index fb6426ddeb77..4cb3c2dd905c 100644
--- a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
+++ b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
@@ -6,6 +6,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
@@ -17,6 +18,8 @@
 #include <asm/mach/time.h>
 
 #include <mach/clock.h>
+#include <mach/tcc-nand.h>
+#include <mach/tcc8k-regs.h>
 
 #include "common.h"
 
@@ -51,6 +54,22 @@ static struct sys_timer tcc8k_timer = {
 static void __init tcc8k_map_io(void)
 {
         tcc8k_map_common_io();
+
+        /* set PLL0 clock to 96MHz, adapt UART0 divisor */
+        __raw_writel(0x00026003, CKC_BASE + PLL0CFG_OFFS);
+        __raw_writel(0x10000001, CKC_BASE + ACLKUART0_OFFS);
+
+        /* set PLL1 clock to 192MHz */
+        __raw_writel(0x00016003, CKC_BASE + PLL1CFG_OFFS);
+
+        /* set PLL2 clock to 48MHz */
+        __raw_writel(0x00036003, CKC_BASE + PLL2CFG_OFFS);
+
+        /* with CPU freq higher than 150 MHz, need extra DTCM wait */
+        __raw_writel(0x00000001, SCFG_BASE + DTCMWAIT_OFFS);
+
+        /* PLL locking time as specified */
+        udelay(300);
 }
 
 MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board")
diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c
index 3970a9cdce26..e7cdae5c77a4 100644
--- a/arch/arm/mach-tcc8k/clock.c
+++ b/arch/arm/mach-tcc8k/clock.c
@@ -45,11 +45,12 @@
 #define ACLKGSB1        (CKC_BASE + ACLKGSB1_OFFS)
 #define ACLKGSB2        (CKC_BASE + ACLKGSB2_OFFS)
 #define ACLKGSB3        (CKC_BASE + ACLKGSB3_OFFS)
-#define ACLKUSBH        (CKC_BASE + ACLKUSBH_OFFS)
 #define ACLKTCT         (CKC_BASE + ACLKTCT_OFFS)
 #define ACLKTCX         (CKC_BASE + ACLKTCX_OFFS)
 #define ACLKTCZ         (CKC_BASE + ACLKTCZ_OFFS)
 
+#define ACLK_MAX_DIV    (0xfff + 1)
+
 /* Crystal frequencies */
 static unsigned long xi_rate, xti_rate;
 
@@ -106,9 +107,9 @@ static int root_clk_enable(enum root_clks src)
         return 0;
 }
 
-static int root_clk_disable(enum root_clks root_src)
+static int root_clk_disable(enum root_clks src)
 {
-        switch (root_src) {
+        switch (src) {
         case CLK_SRC_PLL0: return pll_enable(0, 0);
         case CLK_SRC_PLL1: return pll_enable(1, 0);
         case CLK_SRC_PLL2: return pll_enable(2, 0);
@@ -197,7 +198,7 @@ static unsigned long get_rate_pll_div(int pll)
                 addr = CKC_BASE + CLKDIVC1_OFFS;
                 reg = __raw_readl(addr);
                 if (reg & CLKDIVC1_P2E)
-                        div = __raw_readl(addr) & 0x3f;
+                        div = reg & 0x3f;
                 break;
         }
         return get_rate_pll(pll) / (div + 1);
@@ -258,14 +259,19 @@ static unsigned long aclk_best_div(struct clk *clk, unsigned long rate)
 {
         unsigned long div, src, freq, r1, r2;
 
+        if (!rate)
+                return ACLK_MAX_DIV;
+
         src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
         src &= CLK_SRC_MASK;
         freq = root_clk_get_rate(src);
-        div = freq / rate + 1;
+        div = freq / rate;
+        if (!div)
+                return 1;
+        if (div >= ACLK_MAX_DIV)
+                return ACLK_MAX_DIV;
         r1 = freq / div;
         r2 = freq / (div + 1);
-        if (r2 >= rate)
-                return div + 1;
         if ((rate - r2) < (r1 - rate))
                 return div + 1;
 
@@ -287,7 +293,8 @@ static int aclk_set_rate(struct clk *clk, unsigned long rate)
         u32 reg;
 
         reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK;
-        reg |= aclk_best_div(clk, rate);
+        reg |= aclk_best_div(clk, rate) - 1;
+        __raw_writel(reg, clk->aclkreg);
         return 0;
 }
 
@@ -296,15 +303,22 @@ static unsigned long get_rate_sys(struct clk *clk)
         unsigned int src;
 
         src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK;
-                return root_clk_get_rate(src);
+        return root_clk_get_rate(src);
 }
 
 static unsigned long get_rate_bus(struct clk *clk)
 {
-        unsigned int div;
+        unsigned int reg, sdiv, bdiv, rate;
 
-        div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff;
-        return get_rate_sys(clk) / (div + 1);
+        reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
+        rate = get_rate_sys(clk);
+        sdiv = (reg >> 20) & 3;
+        if (sdiv)
+                rate /= sdiv + 1;
+        bdiv = (reg >> 4) & 0xff;
+        if (bdiv)
+                rate /= bdiv + 1;
+        return rate;
 }
 
 static unsigned long get_rate_cpu(struct clk *clk)
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index aa53ee22438f..513d6abec1f5 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/core.c
  *
  *
- * Copyright (C) 2007-2010 ST-Ericsson AB
+ * Copyright (C) 2007-2010 ST-Ericsson SA
  * License terms: GNU General Public License (GPL) version 2
  * Core platform support, IRQ handling and device definitions.
  * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -16,7 +16,9 @@
 #include <linux/device.h>
 #include <linux/mm.h>
 #include <linux/termios.h>
+#include <linux/dmaengine.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/serial.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/clk.h>
@@ -96,10 +98,20 @@ void __init u300_map_io(void)
  * Declaration of devices found on the U300 board and
  * their respective memory locations.
  */
+
+static struct amba_pl011_data uart0_plat_data = {
+#ifdef CONFIG_COH901318
+        .dma_filter = coh901318_filter_id,
+        .dma_rx_param = (void *) U300_DMA_UART0_RX,
+        .dma_tx_param = (void *) U300_DMA_UART0_TX,
+#endif
+};
+
 static struct amba_device uart0_device = {
         .dev = {
+                .coherent_dma_mask = ~0,
                 .init_name = "uart0", /* Slow device at 0x3000 offset */
-                .platform_data = NULL,
+                .platform_data = &uart0_plat_data,
         },
         .res = {
                 .start = U300_UART0_BASE,
@@ -111,10 +123,19 @@ static struct amba_device uart0_device = {
 
 /* The U335 have an additional UART1 on the APP CPU */
 #ifdef CONFIG_MACH_U300_BS335
+static struct amba_pl011_data uart1_plat_data = {
+#ifdef CONFIG_COH901318
+        .dma_filter = coh901318_filter_id,
+        .dma_rx_param = (void *) U300_DMA_UART1_RX,
+        .dma_tx_param = (void *) U300_DMA_UART1_TX,
+#endif
+};
+
 static struct amba_device uart1_device = {
         .dev = {
+                .coherent_dma_mask = ~0,
                 .init_name = "uart1", /* Fast device at 0x7000 offset */
-                .platform_data = NULL,
+                .platform_data = &uart1_plat_data,
         },
         .res = {
                 .start = U300_UART1_BASE,
@@ -960,42 +981,37 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                 .priority_high = 0,
                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
         },
+        /*
+         * Don't set up device address, burst count or size of src
+         * or dst bus for this peripheral - handled by PrimeCell
+         * DMA extension.
+         */
         {
                 .number = U300_DMA_MMCSD_RX_TX,
                 .name = "MMCSD RX TX",
                 .priority_high = 0,
-                .dev_addr =  U300_MMCSD_BASE + 0x080,
                 .param.config = COH901318_CX_CFG_CH_DISABLE |
                                 COH901318_CX_CFG_LCR_DISABLE |
                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
                 .param.ctrl_lli_chained = 0 |
                                 COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
                                 COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
                                 COH901318_CX_CTRL_HSP_ENABLE |
                                 COH901318_CX_CTRL_HSS_DISABLE |
                                 COH901318_CX_CTRL_DDMA_LEGACY,
                 .param.ctrl_lli = 0 |
                                 COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
                                 COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
                                 COH901318_CX_CTRL_HSP_ENABLE |
                                 COH901318_CX_CTRL_HSS_DISABLE |
                                 COH901318_CX_CTRL_DDMA_LEGACY,
                 .param.ctrl_lli_last = 0 |
                                 COH901318_CX_CTRL_TC_ENABLE |
-                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
                                 COH901318_CX_CTRL_TCP_DISABLE |
                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
@@ -1014,15 +1030,76 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                 .name = "MSPRO RX",
                 .priority_high = 0,
         },
+        /*
+         * Don't set up device address, burst count or size of src
+         * or dst bus for this peripheral - handled by PrimeCell
+         * DMA extension.
+         */
         {
                 .number = U300_DMA_UART0_TX,
                 .name = "UART0 TX",
                 .priority_high = 0,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
         },
         {
                 .number = U300_DMA_UART0_RX,
                 .name = "UART0 RX",
                 .priority_high = 0,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
         },
         {
                 .number = U300_DMA_APEX_TX,
@@ -1080,7 +1157,7 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
                                 COH901318_CX_CTRL_TCP_ENABLE |
-                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
                                 COH901318_CX_CTRL_HSP_ENABLE |
                                 COH901318_CX_CTRL_HSS_DISABLE |
                                 COH901318_CX_CTRL_DDMA_LEGACY |
@@ -1252,15 +1329,77 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                 .name = "XGAM PDI",
                 .priority_high = 0,
         },
+        /*
+         * Don't set up device address, burst count or size of src
+         * or dst bus for this peripheral - handled by PrimeCell
+         * DMA extension.
+         */
         {
                 .number = U300_DMA_SPI_TX,
                 .name = "SPI TX",
                 .priority_high = 0,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
         },
         {
                 .number = U300_DMA_SPI_RX,
                 .name = "SPI RX",
                 .priority_high = 0,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+
         },
         {
                 .number = U300_DMA_GENERAL_PURPOSE_0,
@@ -1617,7 +1756,7 @@ static void __init u300_init_check_chip(void)
 #endif
 #ifdef CONFIG_MACH_U300_BS335
         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
-                printk(KERN_ERR "Platform configured for BS365 " \
+                printk(KERN_ERR "Platform configured for BS335 " \
                        " with DB3350 but %s detected, expect problems!",
                        chipname);
         }
@@ -1692,12 +1831,12 @@ void __init u300_init_devices(void)
         /* Register subdevices on the I2C buses */
         u300_i2c_register_board_devices();
 
-        /* Register subdevices on the SPI bus */
-        u300_spi_register_board_devices();
-
         /* Register the platform devices */
         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
 
+        /* Register subdevices on the SPI bus */
+        u300_spi_register_board_devices();
+
 #ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
         /*
          * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
diff --git a/arch/arm/mach-u300/include/mach/coh901318.h b/arch/arm/mach-u300/include/mach/coh901318.h
index 6193aaa47794..7c3b2b2d25b6 100644
--- a/arch/arm/mach-u300/include/mach/coh901318.h
+++ b/arch/arm/mach-u300/include/mach/coh901318.h
@@ -102,6 +102,7 @@ struct coh901318_platform {
         const int max_channels;
 };
 
+#ifdef CONFIG_COH901318
 /**
  * coh901318_filter_id() - DMA channel filter function
  * @chan: dma channel handle
@@ -110,6 +111,12 @@ struct coh901318_platform {
  * In dma_request_channel() it specifies what channel id to be requested
  */
 bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
+#else
+static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
+{
+        return false;
+}
+#endif
 
 /*
  * DMA Controller - this access the static mappings of the coh901318 dma.
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c
index de1ac9ad2213..677ccef5cd32 100644
--- a/arch/arm/mach-u300/mmc.c
+++ b/arch/arm/mach-u300/mmc.c
@@ -3,159 +3,52 @@
  * arch/arm/mach-u300/mmc.c
  *
  *
- * Copyright (C) 2009 ST-Ericsson AB
+ * Copyright (C) 2009 ST-Ericsson SA
  * License terms: GNU General Public License (GPL) version 2
  *
  * Author: Linus Walleij <linus.walleij@stericsson.com>
- * Author: Johan Lundin <johan.lundin@stericsson.com>
+ * Author: Johan Lundin
  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
  */
 #include <linux/device.h>
 #include <linux/amba/bus.h>
 #include <linux/mmc/host.h>
-#include <linux/input.h>
-#include <linux/workqueue.h>
-#include <linux/delay.h>
-#include <linux/regulator/consumer.h>
-#include <linux/regulator/machine.h>
 #include <linux/gpio.h>
+#include <linux/dmaengine.h>
 #include <linux/amba/mmci.h>
 #include <linux/slab.h>
+#include <mach/coh901318.h>
+#include <mach/dma_channels.h>
 
 #include "mmc.h"
 #include "padmux.h"
 
-struct mmci_card_event {
-        struct input_dev *mmc_input;
-        int mmc_inserted;
-        struct work_struct workq;
-        struct mmci_platform_data mmc0_plat_data;
+static struct mmci_platform_data mmc0_plat_data = {
+        /*
+         * Do not set ocr_mask or voltage translation function,
+         * we have a regulator we can control instead.
+         */
+        /* Nominally 2.85V on our platform */
+        .f_max = 24000000,
+        .gpio_wp = -1,
+        .gpio_cd = U300_GPIO_PIN_MMC_CD,
+        .cd_invert = true,
+        .capabilities = MMC_CAP_MMC_HIGHSPEED |
+        MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+#ifdef CONFIG_COH901318
+        .dma_filter = coh901318_filter_id,
+        .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
+        /* Don't specify a TX channel, this RX channel is bidirectional */
+#endif
 };
 
-static unsigned int mmc_status(struct device *dev)
-{
-        struct mmci_card_event *mmci_card = container_of(
-                dev->platform_data,
-                struct mmci_card_event, mmc0_plat_data);
-
-        return mmci_card->mmc_inserted;
-}
-
-static int mmci_callback(void *data)
-{
-        struct mmci_card_event *mmci_card = data;
-
-        disable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD);
-        schedule_work(&mmci_card->workq);
-
-        return 0;
-}
-
-
-static ssize_t gpio_show(struct device *dev, struct device_attribute *attr,
-                  char *buf)
-{
-        struct mmci_card_event *mmci_card = container_of(
-                dev->platform_data,
-                struct mmci_card_event, mmc0_plat_data);
-
-
-        return sprintf(buf, "%d\n", !mmci_card->mmc_inserted);
-}
-
-static DEVICE_ATTR(mmc_inserted, S_IRUGO, gpio_show, NULL);
-
-static void _mmci_callback(struct work_struct *ws)
-{
-
-        struct mmci_card_event *mmci_card = container_of(
-                ws,
-                struct mmci_card_event, workq);
-
-        mdelay(20);
-
-        mmci_card->mmc_inserted = !gpio_get_value(U300_GPIO_PIN_MMC_CD);
-
-        input_report_switch(mmci_card->mmc_input, KEY_INSERT,
-                            mmci_card->mmc_inserted);
-        input_sync(mmci_card->mmc_input);
-
-        pr_debug("MMC/SD card was %s\n",
-                 mmci_card->mmc_inserted ? "inserted" : "removed");
-
-        enable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD, mmci_card->mmc_inserted);
-}
-
 int __devinit mmc_init(struct amba_device *adev)
 {
-        struct mmci_card_event *mmci_card;
         struct device *mmcsd_device = &adev->dev;
         struct pmx *pmx;
         int ret = 0;
 
-        mmci_card = kzalloc(sizeof(struct mmci_card_event), GFP_KERNEL);
-        if (!mmci_card)
-                return -ENOMEM;
-
-        /*
-         * Do not set ocr_mask or voltage translation function,
-         * we have a regulator we can control instead.
-         */
-        /* Nominally 2.85V on our platform */
-        mmci_card->mmc0_plat_data.f_max = 24000000;
-        mmci_card->mmc0_plat_data.status = mmc_status;
-        mmci_card->mmc0_plat_data.gpio_wp = -1;
-        mmci_card->mmc0_plat_data.gpio_cd = -1;
-        mmci_card->mmc0_plat_data.capabilities = MMC_CAP_MMC_HIGHSPEED |
-                MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
-
-        mmcsd_device->platform_data = (void *) &mmci_card->mmc0_plat_data;
-
-        INIT_WORK(&mmci_card->workq, _mmci_callback);
-
-        ret = gpio_request(U300_GPIO_PIN_MMC_CD, "MMC card detection");
-        if (ret) {
-                printk(KERN_CRIT "Could not allocate MMC card detection " \
-                       "GPIO pin\n");
-                goto out;
-        }
-
-        ret = gpio_direction_input(U300_GPIO_PIN_MMC_CD);
-        if (ret) {
-                printk(KERN_CRIT "Invalid GPIO pin requested\n");
-                goto out;
-        }
-
-        ret = sysfs_create_file(&mmcsd_device->kobj,
-                               &dev_attr_mmc_inserted.attr);
-        if (ret)
-                goto out;
-
-        mmci_card->mmc_input = input_allocate_device();
-        if (!mmci_card->mmc_input) {
-                printk(KERN_CRIT "Could not allocate MMC input device\n");
-                return -ENOMEM;
-        }
-
-        mmci_card->mmc_input->name = "MMC insert notification";
-        mmci_card->mmc_input->id.bustype = BUS_HOST;
-        mmci_card->mmc_input->id.vendor = 0;
-        mmci_card->mmc_input->id.product = 0;
-        mmci_card->mmc_input->id.version = 0x0100;
-        mmci_card->mmc_input->dev.parent = mmcsd_device;
-        input_set_capability(mmci_card->mmc_input, EV_SW, KEY_INSERT);
-
-        /*
-         * Since this must always be compiled into the kernel, this input
-         * is never unregistered or free:ed.
-         */
-        ret = input_register_device(mmci_card->mmc_input);
-        if (ret) {
-                input_free_device(mmci_card->mmc_input);
-                goto out;
-        }
-
-        input_set_drvdata(mmci_card->mmc_input, mmci_card);
+        mmcsd_device->platform_data = &mmc0_plat_data;
 
         /*
          * Setup padmuxing for MMC. Since this must always be
@@ -171,12 +64,5 @@ int __devinit mmc_init(struct amba_device *adev)
                         pr_warning("Could not activate padmuxing\n");
         }
 
-        ret = gpio_register_callback(U300_GPIO_PIN_MMC_CD, mmci_callback,
-                                     mmci_card);
-
-        schedule_work(&mmci_card->workq);
-
-        printk(KERN_INFO "Registered MMC insert/remove notification\n");
-out:
         return ret;
 }
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index 00869def5420..5767208f1c1d 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -11,6 +11,9 @@
 #include <linux/spi/spi.h>
 #include <linux/amba/pl022.h>
 #include <linux/err.h>
+#include <mach/coh901318.h>
+#include <mach/dma_channels.h>
+
 #include "padmux.h"
 
 /*
@@ -30,11 +33,8 @@ static void select_dummy_chip(u32 chipselect)
 }
 
 struct pl022_config_chip dummy_chip_info = {
-        /*
-         * available POLLING_TRANSFER and INTERRUPT_TRANSFER,
-         * DMA_TRANSFER does not work
-         */
-        .com_mode = INTERRUPT_TRANSFER,
+        /* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */
+        .com_mode = DMA_TRANSFER,
         .iface = SSP_INTERFACE_MOTOROLA_SPI,
         /* We can only act as master but SSP_SLAVE is possible in theory */
         .hierarchy = SSP_MASTER,
@@ -75,8 +75,6 @@ static struct spi_board_info u300_spi_devices[] = {
 static struct pl022_ssp_controller ssp_platform_data = {
         /* If you have several SPI buses this varies, we have only bus 0 */
         .bus_id = 0,
-        /* Set this to 1 when we think we got DMA working */
-        .enable_dma = 0,
         /*
          * On the APP CPU GPIO 4, 5 and 6 are connected as generic
          * chip selects for SPI. (Same on U330, U335 and U365.)
@@ -84,6 +82,14 @@ static struct pl022_ssp_controller ssp_platform_data = {
          * and do padmuxing accordingly too.
          */
         .num_chipselect = 3,
+#ifdef CONFIG_COH901318
+        .enable_dma = 1,
+        .dma_filter = coh901318_filter_id,
+        .dma_rx_param = (void *) U300_DMA_SPI_RX,
+        .dma_tx_param = (void *) U300_DMA_SPI_TX,
+#else
+        .enable_dma = 0,
+#endif
 };
 
 
@@ -109,6 +115,7 @@ void __init u300_spi_init(struct amba_device *adev)
         }
 
 }
+
 void __init u300_spi_register_board_devices(void)
 {
         /* Register any SPI devices */
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 53ebb429e971..b549a8fb4231 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -3,16 +3,18 @@
 #
 
 obj-y                           := clock.o cpu.o devices.o devices-common.o \
-                                   id.o
+                                   id.o usb.o
 obj-$(CONFIG_UX500_SOC_DB5500)  += cpu-db5500.o dma-db5500.o
 obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o prcmu.o
 obj-$(CONFIG_MACH_U8500)        += board-mop500.o board-mop500-sdi.o \
-                                board-mop500-keypads.o
+                                board-mop500-regulators.o \
+                                board-mop500-uib.o board-mop500-stuib.o \
+                                board-mop500-u8500uib.o \
+                                board-mop500-pins.o
 obj-$(CONFIG_MACH_U5500)        += board-u5500.o board-u5500-sdi.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
-obj-$(CONFIG_REGULATOR_AB8500)  += board-mop500-regulators.o
 obj-$(CONFIG_U5500_MODEM_IRQ)   += modem-irq-db5500.o
 obj-$(CONFIG_U5500_MBOX)        += mbox-db5500.o
 obj-$(CONFIG_CPU_FREQ)          += cpufreq.o
diff --git a/arch/arm/mach-ux500/board-mop500-keypads.c b/arch/arm/mach-ux500/board-mop500-keypads.c
deleted file mode 100644
index 70318c354d32..000000000000
--- a/arch/arm/mach-ux500/board-mop500-keypads.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License Terms: GNU General Public License v2
- *
- * Keypad layouts for various boards
- */
-
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/mfd/stmpe.h>
-#include <linux/mfd/tc3589x.h>
-#include <linux/input/matrix_keypad.h>
-
-#include <plat/pincfg.h>
-#include <plat/ske.h>
-
-#include <mach/devices.h>
-#include <mach/hardware.h>
-
-#include "devices-db8500.h"
-#include "board-mop500.h"
-
-/* STMPE/SKE keypad use this key layout */
-static const unsigned int mop500_keymap[] = {
-        KEY(2, 5, KEY_END),
-        KEY(4, 1, KEY_POWER),
-        KEY(3, 5, KEY_VOLUMEDOWN),
-        KEY(1, 3, KEY_3),
-        KEY(5, 2, KEY_RIGHT),
-        KEY(5, 0, KEY_9),
-
-        KEY(0, 5, KEY_MENU),
-        KEY(7, 6, KEY_ENTER),
-        KEY(4, 5, KEY_0),
-        KEY(6, 7, KEY_2),
-        KEY(3, 4, KEY_UP),
-        KEY(3, 3, KEY_DOWN),
-
-        KEY(6, 4, KEY_SEND),
-        KEY(6, 2, KEY_BACK),
-        KEY(4, 2, KEY_VOLUMEUP),
-        KEY(5, 5, KEY_1),
-        KEY(4, 3, KEY_LEFT),
-        KEY(3, 2, KEY_7),
-};
-
-static const struct matrix_keymap_data mop500_keymap_data = {
-        .keymap         = mop500_keymap,
-        .keymap_size    = ARRAY_SIZE(mop500_keymap),
-};
-
-/*
- * Nomadik SKE keypad
- */
-#define ROW_PIN_I0      164
-#define ROW_PIN_I1      163
-#define ROW_PIN_I2      162
-#define ROW_PIN_I3      161
-#define ROW_PIN_I4      156
-#define ROW_PIN_I5      155
-#define ROW_PIN_I6      154
-#define ROW_PIN_I7      153
-#define COL_PIN_O0      168
-#define COL_PIN_O1      167
-#define COL_PIN_O2      166
-#define COL_PIN_O3      165
-#define COL_PIN_O4      160
-#define COL_PIN_O5      159
-#define COL_PIN_O6      158
-#define COL_PIN_O7      157
-
-#define SKE_KPD_MAX_ROWS        8
-#define SKE_KPD_MAX_COLS        8
-
-static int ske_kp_rows[] = {
-        ROW_PIN_I0, ROW_PIN_I1, ROW_PIN_I2, ROW_PIN_I3,
-        ROW_PIN_I4, ROW_PIN_I5, ROW_PIN_I6, ROW_PIN_I7,
-};
-
-/*
- * ske_set_gpio_row: request and set gpio rows
- */
-static int ske_set_gpio_row(int gpio)
-{
-        int ret;
-
-        ret = gpio_request(gpio, "ske-kp");
-        if (ret < 0) {
-                pr_err("ske_set_gpio_row: gpio request failed\n");
-                return ret;
-        }
-
-        ret = gpio_direction_output(gpio, 1);
-        if (ret < 0) {
-                pr_err("ske_set_gpio_row: gpio direction failed\n");
-                gpio_free(gpio);
-        }
-
-        return ret;
-}
-
-/*
- * ske_kp_init - enable the gpio configuration
- */
-static int ske_kp_init(void)
-{
-        int ret, i;
-
-        for (i = 0; i < SKE_KPD_MAX_ROWS; i++) {
-                ret = ske_set_gpio_row(ske_kp_rows[i]);
-                if (ret < 0) {
-                        pr_err("ske_kp_init: failed init\n");
-                        return ret;
-                }
-        }
-
-        return 0;
-}
-
-static struct ske_keypad_platform_data ske_keypad_board = {
-        .init           = ske_kp_init,
-        .keymap_data    = &mop500_keymap_data,
-        .no_autorepeat  = true,
-        .krow           = SKE_KPD_MAX_ROWS,     /* 8x8 matrix */
-        .kcol           = SKE_KPD_MAX_COLS,
-        .debounce_ms    = 40,                   /* in millisecs */
-};
-
-/*
- * STMPE1601
- */
-static struct stmpe_keypad_platform_data stmpe1601_keypad_data = {
-        .debounce_ms    = 64,
-        .scan_count     = 8,
-        .no_autorepeat  = true,
-        .keymap_data    = &mop500_keymap_data,
-};
-
-static struct stmpe_platform_data stmpe1601_data = {
-        .id             = 1,
-        .blocks         = STMPE_BLOCK_KEYPAD,
-        .irq_trigger    = IRQF_TRIGGER_FALLING,
-        .irq_base       = MOP500_STMPE1601_IRQ(0),
-        .keypad         = &stmpe1601_keypad_data,
-        .autosleep      = true,
-        .autosleep_timeout = 1024,
-};
-
-static struct i2c_board_info mop500_i2c0_devices_stuib[] = {
-        {
-                I2C_BOARD_INFO("stmpe1601", 0x40),
-                .irq = NOMADIK_GPIO_TO_IRQ(218),
-                .platform_data = &stmpe1601_data,
-                .flags = I2C_CLIENT_WAKE,
-        },
-};
-
-/*
- * TC35893
- */
-
-static const unsigned int uib_keymap[] = {
-        KEY(3, 1, KEY_END),
-        KEY(4, 1, KEY_POWER),
-        KEY(6, 4, KEY_VOLUMEDOWN),
-        KEY(4, 2, KEY_EMAIL),
-        KEY(3, 3, KEY_RIGHT),
-        KEY(2, 5, KEY_BACKSPACE),
-
-        KEY(6, 7, KEY_MENU),
-        KEY(5, 0, KEY_ENTER),
-        KEY(4, 3, KEY_0),
-        KEY(3, 4, KEY_DOT),
-        KEY(5, 2, KEY_UP),
-        KEY(3, 5, KEY_DOWN),
-
-        KEY(4, 5, KEY_SEND),
-        KEY(0, 5, KEY_BACK),
-        KEY(6, 2, KEY_VOLUMEUP),
-        KEY(1, 3, KEY_SPACE),
-        KEY(7, 6, KEY_LEFT),
-        KEY(5, 5, KEY_SEARCH),
-};
-
-static struct matrix_keymap_data uib_keymap_data = {
-        .keymap         = uib_keymap,
-        .keymap_size    = ARRAY_SIZE(uib_keymap),
-};
-
-static struct tc3589x_keypad_platform_data tc35893_data = {
-        .krow = TC_KPD_ROWS,
-        .kcol = TC_KPD_COLUMNS,
-        .debounce_period = TC_KPD_DEBOUNCE_PERIOD,
-        .settle_time = TC_KPD_SETTLE_TIME,
-        .irqtype = IRQF_TRIGGER_FALLING,
-        .enable_wakeup = true,
-        .keymap_data    = &uib_keymap_data,
-        .no_autorepeat  = true,
-};
-
-static struct tc3589x_platform_data tc3589x_keypad_data = {
-        .block = TC3589x_BLOCK_KEYPAD,
-        .keypad = &tc35893_data,
-        .irq_base = MOP500_EGPIO_IRQ_BASE,
-};
-
-static struct i2c_board_info mop500_i2c0_devices_uib[] = {
-        {
-                I2C_BOARD_INFO("tc3589x", 0x44),
-                .platform_data = &tc3589x_keypad_data,
-                .irq = NOMADIK_GPIO_TO_IRQ(218),
-                .flags = I2C_CLIENT_WAKE,
-        },
-};
-
-void mop500_keypad_init(void)
-{
-        db8500_add_ske_keypad(&ske_keypad_board);
-
-        i2c_register_board_info(0, mop500_i2c0_devices_stuib,
-                        ARRAY_SIZE(mop500_i2c0_devices_stuib));
-
-        i2c_register_board_info(0, mop500_i2c0_devices_uib,
-                        ARRAY_SIZE(mop500_i2c0_devices_uib));
-
-}
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
new file mode 100644
index 000000000000..fd4cf1ca5efd
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-types.h>
+#include <plat/pincfg.h>
+#include <mach/hardware.h>
+
+#include "pins-db8500.h"
+
+static pin_cfg_t mop500_pins_common[] = {
+        /* I2C */
+        GPIO147_I2C0_SCL,
+        GPIO148_I2C0_SDA,
+        GPIO16_I2C1_SCL,
+        GPIO17_I2C1_SDA,
+        GPIO10_I2C2_SDA,
+        GPIO11_I2C2_SCL,
+        GPIO229_I2C3_SDA,
+        GPIO230_I2C3_SCL,
+
+        /* MSP0 */
+        GPIO12_MSP0_TXD,
+        GPIO13_MSP0_TFS,
+        GPIO14_MSP0_TCK,
+        GPIO15_MSP0_RXD,
+
+        /* MSP2: HDMI */
+        GPIO193_MSP2_TXD,
+        GPIO194_MSP2_TCK,
+        GPIO195_MSP2_TFS,
+        GPIO196_MSP2_RXD | PIN_OUTPUT_LOW,
+
+        /* Touch screen INTERFACE */
+        GPIO84_GPIO     | PIN_INPUT_PULLUP, /* TOUCH_INT1 */
+
+        /* STMPE1601/tc35893 keypad  IRQ */
+        GPIO218_GPIO    | PIN_INPUT_PULLUP,
+
+        /* MMC0 (MicroSD card) */
+        GPIO18_MC0_CMDDIR       | PIN_OUTPUT_HIGH,
+        GPIO19_MC0_DAT0DIR      | PIN_OUTPUT_HIGH,
+        GPIO20_MC0_DAT2DIR      | PIN_OUTPUT_HIGH,
+
+        GPIO22_MC0_FBCLK        | PIN_INPUT_NOPULL,
+        GPIO23_MC0_CLK          | PIN_OUTPUT_LOW,
+        GPIO24_MC0_CMD          | PIN_INPUT_PULLUP,
+        GPIO25_MC0_DAT0         | PIN_INPUT_PULLUP,
+        GPIO26_MC0_DAT1         | PIN_INPUT_PULLUP,
+        GPIO27_MC0_DAT2         | PIN_INPUT_PULLUP,
+        GPIO28_MC0_DAT3         | PIN_INPUT_PULLUP,
+
+        /* SDI1 (SDIO) */
+        GPIO208_MC1_CLK         | PIN_OUTPUT_LOW,
+        GPIO209_MC1_FBCLK       | PIN_INPUT_NOPULL,
+        GPIO210_MC1_CMD         | PIN_INPUT_PULLUP,
+        GPIO211_MC1_DAT0        | PIN_INPUT_PULLUP,
+        GPIO212_MC1_DAT1        | PIN_INPUT_PULLUP,
+        GPIO213_MC1_DAT2        | PIN_INPUT_PULLUP,
+        GPIO214_MC1_DAT3        | PIN_INPUT_PULLUP,
+
+        /* MMC2 (On-board DATA INTERFACE eMMC) */
+        GPIO128_MC2_CLK         | PIN_OUTPUT_LOW,
+        GPIO129_MC2_CMD         | PIN_INPUT_PULLUP,
+        GPIO130_MC2_FBCLK       | PIN_INPUT_NOPULL,
+        GPIO131_MC2_DAT0        | PIN_INPUT_PULLUP,
+        GPIO132_MC2_DAT1        | PIN_INPUT_PULLUP,
+        GPIO133_MC2_DAT2        | PIN_INPUT_PULLUP,
+        GPIO134_MC2_DAT3        | PIN_INPUT_PULLUP,
+        GPIO135_MC2_DAT4        | PIN_INPUT_PULLUP,
+        GPIO136_MC2_DAT5        | PIN_INPUT_PULLUP,
+        GPIO137_MC2_DAT6        | PIN_INPUT_PULLUP,
+        GPIO138_MC2_DAT7        | PIN_INPUT_PULLUP,
+
+        /* MMC4 (On-board STORAGE INTERFACE eMMC) */
+        GPIO197_MC4_DAT3        | PIN_INPUT_PULLUP,
+        GPIO198_MC4_DAT2        | PIN_INPUT_PULLUP,
+        GPIO199_MC4_DAT1        | PIN_INPUT_PULLUP,
+        GPIO200_MC4_DAT0        | PIN_INPUT_PULLUP,
+        GPIO201_MC4_CMD         | PIN_INPUT_PULLUP,
+        GPIO202_MC4_FBCLK       | PIN_INPUT_NOPULL,
+        GPIO203_MC4_CLK         | PIN_OUTPUT_LOW,
+        GPIO204_MC4_DAT7        | PIN_INPUT_PULLUP,
+        GPIO205_MC4_DAT6        | PIN_INPUT_PULLUP,
+        GPIO206_MC4_DAT5        | PIN_INPUT_PULLUP,
+        GPIO207_MC4_DAT4        | PIN_INPUT_PULLUP,
+
+        /* SKE keypad */
+        GPIO153_KP_I7,
+        GPIO154_KP_I6,
+        GPIO155_KP_I5,
+        GPIO156_KP_I4,
+        GPIO157_KP_O7,
+        GPIO158_KP_O6,
+        GPIO159_KP_O5,
+        GPIO160_KP_O4,
+        GPIO161_KP_I3,
+        GPIO162_KP_I2,
+        GPIO163_KP_I1,
+        GPIO164_KP_I0,
+        GPIO165_KP_O3,
+        GPIO166_KP_O2,
+        GPIO167_KP_O1,
+        GPIO168_KP_O0,
+
+        /* UART */
+        GPIO0_U0_CTSn   | PIN_INPUT_PULLUP,
+        GPIO1_U0_RTSn   | PIN_OUTPUT_HIGH,
+        GPIO2_U0_RXD    | PIN_INPUT_PULLUP,
+        GPIO3_U0_TXD    | PIN_OUTPUT_HIGH,
+
+        GPIO29_U2_RXD   | PIN_INPUT_PULLUP,
+        GPIO30_U2_TXD   | PIN_OUTPUT_HIGH,
+        GPIO31_U2_CTSn  | PIN_INPUT_PULLUP,
+        GPIO32_U2_RTSn  | PIN_OUTPUT_HIGH,
+
+        /* Display & HDMI HW sync */
+        GPIO68_LCD_VSI0 | PIN_INPUT_PULLUP,
+        GPIO69_LCD_VSI1 | PIN_INPUT_PULLUP,
+};
+
+static pin_cfg_t mop500_pins_default[] = {
+        /* SSP0 */
+        GPIO143_SSP0_CLK,
+        GPIO144_SSP0_FRM,
+        GPIO145_SSP0_RXD | PIN_PULL_DOWN,
+        GPIO146_SSP0_TXD,
+
+
+        GPIO217_GPIO    | PIN_INPUT_PULLUP, /* TC35892 IRQ */
+
+        /* SDI0 (MicroSD card) */
+        GPIO21_MC0_DAT31DIR     | PIN_OUTPUT_HIGH,
+
+        /* UART */
+        GPIO4_U1_RXD    | PIN_INPUT_PULLUP,
+        GPIO5_U1_TXD    | PIN_OUTPUT_HIGH,
+        GPIO6_U1_CTSn   | PIN_INPUT_PULLUP,
+        GPIO7_U1_RTSn   | PIN_OUTPUT_HIGH,
+};
+
+static pin_cfg_t mop500_pins_hrefv60[] = {
+        /* WLAN */
+        GPIO4_GPIO              | PIN_INPUT_PULLUP,/* WLAN_IRQ */
+        GPIO85_GPIO             | PIN_OUTPUT_LOW,/* WLAN_ENA */
+
+        /* XENON Flashgun INTERFACE */
+        GPIO6_IP_GPIO0  | PIN_INPUT_PULLUP,/* XENON_FLASH_ID */
+        GPIO7_IP_GPIO1  | PIN_INPUT_PULLUP,/* XENON_READY */
+        GPIO170_GPIO    | PIN_OUTPUT_LOW, /* XENON_CHARGE */
+
+        /* Assistant LED INTERFACE */
+        GPIO21_GPIO | PIN_OUTPUT_LOW,  /* XENON_EN1 */
+        GPIO64_IP_GPIO4 | PIN_OUTPUT_LOW,  /* XENON_EN2 */
+
+        /* Magnetometer */
+        GPIO31_GPIO | PIN_INPUT_PULLUP,  /* magnetometer_INT */
+        GPIO32_GPIO | PIN_INPUT_PULLDOWN, /* Magnetometer DRDY */
+
+        /* Display Interface */
+        GPIO65_GPIO             | PIN_OUTPUT_LOW, /* DISP1 RST */
+        GPIO66_GPIO             | PIN_OUTPUT_LOW, /* DISP2 RST */
+
+        /* Touch screen INTERFACE */
+        GPIO143_GPIO    | PIN_OUTPUT_LOW,/*TOUCH_RST1 */
+
+        /* Touch screen INTERFACE 2 */
+        GPIO67_GPIO     | PIN_INPUT_PULLUP, /* TOUCH_INT2 */
+        GPIO146_GPIO    | PIN_OUTPUT_LOW,/*TOUCH_RST2 */
+
+        /* ETM_PTM_TRACE INTERFACE */
+        GPIO70_GPIO     | PIN_OUTPUT_LOW,/* ETM_PTM_DATA23 */
+        GPIO71_GPIO     | PIN_OUTPUT_LOW,/* ETM_PTM_DATA22 */
+        GPIO72_GPIO     | PIN_OUTPUT_LOW,/* ETM_PTM_DATA21 */
+        GPIO73_GPIO     | PIN_OUTPUT_LOW,/* ETM_PTM_DATA20 */
+        GPIO74_GPIO     | PIN_OUTPUT_LOW,/* ETM_PTM_DATA19 */
+
+        /* NAHJ INTERFACE */
+        GPIO76_GPIO     | PIN_OUTPUT_LOW,/* NAHJ_CTRL */
+        GPIO216_GPIO    | PIN_OUTPUT_HIGH,/* NAHJ_CTRL_INV */
+
+        /* NFC INTERFACE */
+        GPIO77_GPIO     | PIN_OUTPUT_LOW, /* NFC_ENA */
+        GPIO144_GPIO    | PIN_INPUT_PULLDOWN, /* NFC_IRQ */
+        GPIO142_GPIO    | PIN_OUTPUT_LOW, /* NFC_RESET */
+
+        /* Keyboard MATRIX INTERFACE */
+        GPIO90_MC5_CMD  | PIN_OUTPUT_LOW, /* KP_O_1 */
+        GPIO87_MC5_DAT1 | PIN_OUTPUT_LOW, /* KP_O_2 */
+        GPIO86_MC5_DAT0 | PIN_OUTPUT_LOW, /* KP_O_3 */
+        GPIO96_KP_O6    | PIN_OUTPUT_LOW, /* KP_O_6 */
+        GPIO94_KP_O7    | PIN_OUTPUT_LOW, /* KP_O_7 */
+        GPIO93_MC5_DAT4 | PIN_INPUT_PULLUP, /* KP_I_0 */
+        GPIO89_MC5_DAT3 | PIN_INPUT_PULLUP, /* KP_I_2 */
+        GPIO88_MC5_DAT2 | PIN_INPUT_PULLUP, /* KP_I_3 */
+        GPIO91_GPIO     | PIN_INPUT_PULLUP, /* FORCE_SENSING_INT */
+        GPIO92_GPIO     | PIN_OUTPUT_LOW, /* FORCE_SENSING_RST */
+        GPIO97_GPIO     | PIN_OUTPUT_LOW, /* FORCE_SENSING_WU */
+
+        /* DiPro Sensor Interface */
+        GPIO139_GPIO    | PIN_INPUT_PULLUP, /* DIPRO_INT */
+
+        /* HAL SWITCH INTERFACE */
+        GPIO145_GPIO    | PIN_INPUT_PULLDOWN,/* HAL_SW */
+
+        /* Audio Amplifier Interface */
+        GPIO149_GPIO    | PIN_OUTPUT_LOW, /* VAUDIO_HF_EN */
+
+        /* GBF INTERFACE */
+        GPIO171_GPIO    | PIN_OUTPUT_LOW, /* GBF_ENA_RESET */
+
+        /* MSP : HDTV INTERFACE */
+        GPIO192_GPIO    | PIN_INPUT_PULLDOWN,
+
+        /* ACCELEROMETER_INTERFACE */
+        GPIO82_GPIO             | PIN_INPUT_PULLUP, /* ACC_INT1 */
+        GPIO83_GPIO             | PIN_INPUT_PULLUP, /* ACC_INT2 */
+
+        /* Proximity Sensor */
+        GPIO217_GPIO            | PIN_INPUT_PULLUP,
+
+
+};
+
+void __init mop500_pins_init(void)
+{
+        nmk_config_pins(mop500_pins_common,
+                                ARRAY_SIZE(mop500_pins_common));
+        if (machine_is_hrefv60())
+                nmk_config_pins(mop500_pins_hrefv60,
+                                ARRAY_SIZE(mop500_pins_hrefv60));
+        else
+                nmk_config_pins(mop500_pins_default,
+                                ARRAY_SIZE(mop500_pins_default));
+}
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 533967c2d095..875c91b2f8a4 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -11,6 +11,56 @@
 #include <linux/kernel.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/ab8500.h>
+#include "board-mop500-regulators.h"
+
+static struct regulator_consumer_supply ab8500_vaux1_consumers[] = {
+        /* External displays, connector on board 2v5 power supply */
+        REGULATOR_SUPPLY("vaux12v5", "mcde.0"),
+        /* SFH7741 proximity sensor */
+        REGULATOR_SUPPLY("vcc", "gpio-keys.0"),
+        /* BH1780GLS ambient light sensor */
+        REGULATOR_SUPPLY("vcc", "2-0029"),
+        /* lsm303dlh accelerometer */
+        REGULATOR_SUPPLY("vdd", "3-0018"),
+        /* lsm303dlh magnetometer */
+        REGULATOR_SUPPLY("vdd", "3-001e"),
+        /* Rohm BU21013 Touchscreen devices */
+        REGULATOR_SUPPLY("avdd", "3-005c"),
+        REGULATOR_SUPPLY("avdd", "3-005d"),
+        /* Synaptics RMI4 Touchscreen device */
+        REGULATOR_SUPPLY("vdd", "3-004b"),
+};
+
+static struct regulator_consumer_supply ab8500_vaux2_consumers[] = {
+        /* On-board eMMC power */
+        REGULATOR_SUPPLY("vmmc", "sdi4"),
+        /* AB8500 audio codec */
+        REGULATOR_SUPPLY("vcc-N2158", "ab8500-codec.0"),
+};
+
+static struct regulator_consumer_supply ab8500_vaux3_consumers[] = {
+        /* External MMC slot power */
+        REGULATOR_SUPPLY("vmmc", "sdi0"),
+};
+
+static struct regulator_consumer_supply ab8500_vtvout_consumers[] = {
+        /* TV-out DENC supply */
+        REGULATOR_SUPPLY("vtvout", "ab8500-denc.0"),
+        /* Internal general-purpose ADC */
+        REGULATOR_SUPPLY("vddadc", "ab8500-gpadc.0"),
+};
+
+static struct regulator_consumer_supply ab8500_vintcore_consumers[] = {
+        /* SoC core supply, no device */
+        REGULATOR_SUPPLY("v-intcore", NULL),
+        /* USB Transciever */
+        REGULATOR_SUPPLY("vddulpivio18", "ab8500-usb.0"),
+};
+
+static struct regulator_consumer_supply ab8500_vana_consumers[] = {
+        /* External displays, connector on board, 1v8 power supply */
+        REGULATOR_SUPPLY("vsmps2", "mcde.0"),
+};
 
 /* AB8500 regulators */
 struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
@@ -23,6 +73,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
                                           REGULATOR_CHANGE_STATUS,
                 },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers),
+                .consumer_supplies = ab8500_vaux1_consumers,
         },
         /* supplies to the on-board eMMC */
         [AB8500_LDO_AUX2] = {
@@ -33,6 +85,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
                                           REGULATOR_CHANGE_STATUS,
                 },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux2_consumers),
+                .consumer_supplies = ab8500_vaux2_consumers,
         },
         /* supply for VAUX3, supplies to SDcard slots */
         [AB8500_LDO_AUX3] = {
@@ -43,6 +97,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
                                           REGULATOR_CHANGE_STATUS,
                 },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux3_consumers),
+                .consumer_supplies = ab8500_vaux3_consumers,
         },
         /* supply for tvout, gpadc, TVOUT LDO */
         [AB8500_LDO_TVOUT] = {
@@ -50,6 +106,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .name = "V-TVOUT",
                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vtvout_consumers),
+                .consumer_supplies = ab8500_vtvout_consumers,
         },
         /* supply for ab8500-vaudio, VAUDIO LDO */
         [AB8500_LDO_AUDIO] = {
@@ -85,6 +143,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .name = "V-INTCORE",
                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vintcore_consumers),
+                .consumer_supplies = ab8500_vintcore_consumers,
         },
         /* supply for U8500 CSI/DSI, VANA LDO */
         [AB8500_LDO_ANA] = {
@@ -92,5 +152,7 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .name = "V-CSI/DSI",
                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vana_consumers),
+                .consumer_supplies = ab8500_vana_consumers,
         },
 };
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 4b996676594e..bf0b02414e5b 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -12,56 +12,14 @@
 #include <linux/mmc/host.h>
 #include <linux/platform_device.h>
 
-#include <plat/pincfg.h>
+#include <asm/mach-types.h>
+#include <plat/ste_dma40.h>
 #include <mach/devices.h>
 #include <mach/hardware.h>
 
 #include "devices-db8500.h"
-#include "pins-db8500.h"
 #include "board-mop500.h"
-
-static pin_cfg_t mop500_sdi_pins[] = {
-        /* SDI0 (MicroSD slot) */
-        GPIO18_MC0_CMDDIR,
-        GPIO19_MC0_DAT0DIR,
-        GPIO20_MC0_DAT2DIR,
-        GPIO21_MC0_DAT31DIR,
-        GPIO22_MC0_FBCLK,
-        GPIO23_MC0_CLK,
-        GPIO24_MC0_CMD,
-        GPIO25_MC0_DAT0,
-        GPIO26_MC0_DAT1,
-        GPIO27_MC0_DAT2,
-        GPIO28_MC0_DAT3,
-
-        /* SDI4 (on-board eMMC) */
-        GPIO197_MC4_DAT3,
-        GPIO198_MC4_DAT2,
-        GPIO199_MC4_DAT1,
-        GPIO200_MC4_DAT0,
-        GPIO201_MC4_CMD,
-        GPIO202_MC4_FBCLK,
-        GPIO203_MC4_CLK,
-        GPIO204_MC4_DAT7,
-        GPIO205_MC4_DAT6,
-        GPIO206_MC4_DAT5,
-        GPIO207_MC4_DAT4,
-};
-
-static pin_cfg_t mop500_sdi2_pins[] = {
-        /* SDI2 (POP eMMC) */
-        GPIO128_MC2_CLK,
-        GPIO129_MC2_CMD,
-        GPIO130_MC2_FBCLK,
-        GPIO131_MC2_DAT0,
-        GPIO132_MC2_DAT1,
-        GPIO133_MC2_DAT2,
-        GPIO134_MC2_DAT3,
-        GPIO135_MC2_DAT4,
-        GPIO136_MC2_DAT5,
-        GPIO137_MC2_DAT6,
-        GPIO138_MC2_DAT7,
-};
+#include "ste-dma40-db8500.h"
 
 /*
  * SDI 0 (MicroSD slot)
@@ -86,48 +44,134 @@ static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
                MCI_DATA2DIREN | MCI_DATA31DIREN;
 }
 
+#ifdef CONFIG_STE_DMA40
+struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+
+static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+#endif
+
 static struct mmci_platform_data mop500_sdi0_data = {
         .vdd_handler    = mop500_sdi0_vdd_handler,
         .ocr_mask       = MMC_VDD_29_30,
         .f_max          = 100000000,
         .capabilities   = MMC_CAP_4_BIT_DATA,
-        .gpio_cd        = GPIO_SDMMC_CD,
         .gpio_wp        = -1,
+#ifdef CONFIG_STE_DMA40
+        .dma_filter     = stedma40_filter,
+        .dma_rx_param   = &mop500_sdi0_dma_cfg_rx,
+        .dma_tx_param   = &mop500_sdi0_dma_cfg_tx,
+#endif
 };
 
-void mop500_sdi_tc35892_init(void)
+/* GPIO pins used by the sdi0 level shifter */
+static int sdi0_en = -1;
+static int sdi0_vsel = -1;
+
+static void sdi0_configure(void)
 {
         int ret;
 
-        ret = gpio_request(GPIO_SDMMC_EN, "SDMMC_EN");
+        ret = gpio_request(sdi0_en, "level shifter enable");
         if (!ret)
-                ret = gpio_request(GPIO_SDMMC_1V8_3V_SEL,
-                                   "GPIO_SDMMC_1V8_3V_SEL");
-        if (ret)
+                ret = gpio_request(sdi0_vsel,
+                                   "level shifter 1v8-3v select");
+
+        if (ret) {
+                pr_warning("unable to config sdi0 gpios for level shifter.\n");
                 return;
+        }
 
-        gpio_direction_output(GPIO_SDMMC_1V8_3V_SEL, 1);
-        gpio_direction_output(GPIO_SDMMC_EN, 0);
+        /* Select the default 2.9V and enable level shifter */
+        gpio_direction_output(sdi0_vsel, 0);
+        gpio_direction_output(sdi0_en, 1);
 
+        /* Add the device */
         db8500_add_sdi0(&mop500_sdi0_data);
 }
 
+void mop500_sdi_tc35892_init(void)
+{
+        mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
+        sdi0_en = GPIO_SDMMC_EN;
+        sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL;
+        sdi0_configure();
+}
+
 /*
  * SDI 2 (POP eMMC, not on DB8500ed)
  */
 
+#ifdef CONFIG_STE_DMA40
+struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type =  DB8500_DMA_DEV28_SD_MM2_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+
+static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+#endif
+
 static struct mmci_platform_data mop500_sdi2_data = {
         .ocr_mask       = MMC_VDD_165_195,
         .f_max          = 100000000,
         .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
         .gpio_cd        = -1,
         .gpio_wp        = -1,
+#ifdef CONFIG_STE_DMA40
+        .dma_filter     = stedma40_filter,
+        .dma_rx_param   = &mop500_sdi2_dma_cfg_rx,
+        .dma_tx_param   = &mop500_sdi2_dma_cfg_tx,
+#endif
 };
 
 /*
  * SDI 4 (on-board eMMC)
  */
 
+#ifdef CONFIG_STE_DMA40
+struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type =  DB8500_DMA_DEV42_SD_MM4_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+
+static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+#endif
+
 static struct mmci_platform_data mop500_sdi4_data = {
         .ocr_mask       = MMC_VDD_29_30,
         .f_max          = 100000000,
@@ -135,26 +179,32 @@ static struct mmci_platform_data mop500_sdi4_data = {
                           MMC_CAP_MMC_HIGHSPEED,
         .gpio_cd        = -1,
         .gpio_wp        = -1,
+#ifdef CONFIG_STE_DMA40
+        .dma_filter     = stedma40_filter,
+        .dma_rx_param   = &mop500_sdi4_dma_cfg_rx,
+        .dma_tx_param   = &mop500_sdi4_dma_cfg_tx,
+#endif
 };
 
 void __init mop500_sdi_init(void)
 {
-        nmk_config_pins(mop500_sdi_pins, ARRAY_SIZE(mop500_sdi_pins));
+        /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
+        if (!cpu_is_u8500v10())
+                mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
+        db8500_add_sdi2(&mop500_sdi2_data);
+
+        /* On-board eMMC */
+        db8500_add_sdi4(&mop500_sdi4_data);
 
+        if (machine_is_hrefv60()) {
+                mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
+                sdi0_en = HREFV60_SDMMC_EN_GPIO;
+                sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
+                sdi0_configure();
+        }
         /*
-         * sdi0 will finally be added when the TC35892 initializes and calls
+         * On boards with the TC35892 GPIO expander, sdi0 will finally
+         * be added when the TC35892 initializes and calls
          * mop500_sdi_tc35892_init() above.
          */
-
-        /* PoP:ed eMMC */
-        if (!cpu_is_u8500ed()) {
-                nmk_config_pins(mop500_sdi2_pins, ARRAY_SIZE(mop500_sdi2_pins));
-                /* POP eMMC on v1.0 has problems with high speed */
-                if (!cpu_is_u8500v10())
-                        mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
-                db8500_add_sdi2(&mop500_sdi2_data);
-        }
-
-        /* On-board eMMC */
-        db8500_add_sdi4(&mop500_sdi4_data);
 }
diff --git a/arch/arm/mach-ux500/board-mop500-stuib.c b/arch/arm/mach-ux500/board-mop500-stuib.c
new file mode 100644
index 000000000000..8c979770d872
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-stuib.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mfd/stmpe.h>
+#include <linux/input/bu21013.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/input/matrix_keypad.h>
+#include <asm/mach-types.h>
+
+#include "board-mop500.h"
+
+/* STMPE/SKE keypad use this key layout */
+static const unsigned int mop500_keymap[] = {
+        KEY(2, 5, KEY_END),
+        KEY(4, 1, KEY_POWER),
+        KEY(3, 5, KEY_VOLUMEDOWN),
+        KEY(1, 3, KEY_3),
+        KEY(5, 2, KEY_RIGHT),
+        KEY(5, 0, KEY_9),
+
+        KEY(0, 5, KEY_MENU),
+        KEY(7, 6, KEY_ENTER),
+        KEY(4, 5, KEY_0),
+        KEY(6, 7, KEY_2),
+        KEY(3, 4, KEY_UP),
+        KEY(3, 3, KEY_DOWN),
+
+        KEY(6, 4, KEY_SEND),
+        KEY(6, 2, KEY_BACK),
+        KEY(4, 2, KEY_VOLUMEUP),
+        KEY(5, 5, KEY_1),
+        KEY(4, 3, KEY_LEFT),
+        KEY(3, 2, KEY_7),
+};
+
+static const struct matrix_keymap_data mop500_keymap_data = {
+        .keymap         = mop500_keymap,
+        .keymap_size    = ARRAY_SIZE(mop500_keymap),
+};
+/*
+ * STMPE1601
+ */
+static struct stmpe_keypad_platform_data stmpe1601_keypad_data = {
+        .debounce_ms    = 64,
+        .scan_count     = 8,
+        .no_autorepeat  = true,
+        .keymap_data    = &mop500_keymap_data,
+};
+
+static struct stmpe_platform_data stmpe1601_data = {
+        .id             = 1,
+        .blocks         = STMPE_BLOCK_KEYPAD,
+        .irq_trigger    = IRQF_TRIGGER_FALLING,
+        .irq_base       = MOP500_STMPE1601_IRQ(0),
+        .keypad         = &stmpe1601_keypad_data,
+        .autosleep      = true,
+        .autosleep_timeout = 1024,
+};
+
+static struct i2c_board_info __initdata mop500_i2c0_devices_stuib[] = {
+        {
+                I2C_BOARD_INFO("stmpe1601", 0x40),
+                .irq = NOMADIK_GPIO_TO_IRQ(218),
+                .platform_data = &stmpe1601_data,
+                .flags = I2C_CLIENT_WAKE,
+        },
+};
+
+/*
+ * BU21013 ROHM touchscreen interface on the STUIBs
+ */
+
+/* tracks number of bu21013 devices being enabled */
+static int bu21013_devices;
+
+#define TOUCH_GPIO_PIN  84
+
+#define TOUCH_XMAX      384
+#define TOUCH_YMAX      704
+
+#define PRCMU_CLOCK_OCR         0x1CC
+#define TSC_EXT_CLOCK_9_6MHZ    0x840000
+
+/**
+ * bu21013_gpio_board_init : configures the touch panel.
+ * @reset_pin: reset pin number
+ * This function can be used to configures
+ * the voltage and reset the touch panel controller.
+ */
+static int bu21013_gpio_board_init(int reset_pin)
+{
+        int retval = 0;
+
+        bu21013_devices++;
+        if (bu21013_devices == 1) {
+                retval = gpio_request(reset_pin, "touchp_reset");
+                if (retval) {
+                        printk(KERN_ERR "Unable to request gpio reset_pin");
+                        return retval;
+                }
+                retval = gpio_direction_output(reset_pin, 1);
+                if (retval < 0) {
+                        printk(KERN_ERR "%s: gpio direction failed\n",
+                                        __func__);
+                        return retval;
+                }
+        }
+
+        return retval;
+}
+
+/**
+ * bu21013_gpio_board_exit : deconfigures the touch panel controller
+ * @reset_pin: reset pin number
+ * This function can be used to deconfigures the chip selection
+ * for touch panel controller.
+ */
+static int bu21013_gpio_board_exit(int reset_pin)
+{
+        int retval = 0;
+
+        if (bu21013_devices == 1) {
+                retval = gpio_direction_output(reset_pin, 0);
+                if (retval < 0) {
+                        printk(KERN_ERR "%s: gpio direction failed\n",
+                                        __func__);
+                        return retval;
+                }
+                gpio_set_value(reset_pin, 0);
+        }
+        bu21013_devices--;
+
+        return retval;
+}
+
+/**
+ * bu21013_read_pin_val : get the interrupt pin value
+ * This function can be used to get the interrupt pin value for touch panel
+ * controller.
+ */
+static int bu21013_read_pin_val(void)
+{
+        return gpio_get_value(TOUCH_GPIO_PIN);
+}
+
+static struct bu21013_platform_device tsc_plat_device = {
+        .cs_en = bu21013_gpio_board_init,
+        .cs_dis = bu21013_gpio_board_exit,
+        .irq_read_val = bu21013_read_pin_val,
+        .irq = NOMADIK_GPIO_TO_IRQ(TOUCH_GPIO_PIN),
+        .touch_x_max = TOUCH_XMAX,
+        .touch_y_max = TOUCH_YMAX,
+        .ext_clk = false,
+        .x_flip = false,
+        .y_flip = true,
+};
+
+static struct bu21013_platform_device tsc_plat2_device = {
+        .cs_en = bu21013_gpio_board_init,
+        .cs_dis = bu21013_gpio_board_exit,
+        .irq_read_val = bu21013_read_pin_val,
+        .irq = NOMADIK_GPIO_TO_IRQ(TOUCH_GPIO_PIN),
+        .touch_x_max = TOUCH_XMAX,
+        .touch_y_max = TOUCH_YMAX,
+        .ext_clk = false,
+        .x_flip = false,
+        .y_flip = true,
+};
+
+static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = {
+        {
+                I2C_BOARD_INFO("bu21013_tp", 0x5C),
+                .platform_data = &tsc_plat_device,
+        },
+        {
+                I2C_BOARD_INFO("bu21013_tp", 0x5D),
+                .platform_data = &tsc_plat2_device,
+        },
+
+};
+
+void __init mop500_stuib_init(void)
+{
+        if (machine_is_hrefv60()) {
+                tsc_plat_device.cs_pin = HREFV60_TOUCH_RST_GPIO;
+                tsc_plat2_device.cs_pin = HREFV60_TOUCH_RST_GPIO;
+        } else {
+                tsc_plat_device.cs_pin = GPIO_BU21013_CS;
+                tsc_plat2_device.cs_pin = GPIO_BU21013_CS;
+
+        }
+
+        mop500_uib_i2c_add(0, mop500_i2c0_devices_stuib,
+                        ARRAY_SIZE(mop500_i2c0_devices_stuib));
+
+        mop500_uib_i2c_add(3, u8500_i2c3_devices_stuib,
+                        ARRAY_SIZE(u8500_i2c3_devices_stuib));
+}
diff --git a/arch/arm/mach-ux500/board-mop500-u8500uib.c b/arch/arm/mach-ux500/board-mop500-u8500uib.c
new file mode 100644
index 000000000000..d8a8734a0eba
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-u8500uib.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Board data for the U8500 UIB, also known as the New UIB
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/tc3589x.h>
+#include <linux/input/matrix_keypad.h>
+#include <../drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h>
+
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+
+#include "board-mop500.h"
+
+/*
+ * Synaptics RMI4 touchscreen interface on the U8500 UIB
+ */
+
+/*
+ * Descriptor structure.
+ * Describes the number of i2c devices on the bus that speak RMI.
+ */
+static struct synaptics_rmi4_platform_data rmi4_i2c_dev_platformdata = {
+        .irq_number     = NOMADIK_GPIO_TO_IRQ(84),
+        .irq_type       = (IRQF_TRIGGER_FALLING | IRQF_SHARED),
+        .x_flip         = false,
+        .y_flip         = true,
+        .regulator_en   = false,
+};
+
+static struct i2c_board_info __initdata mop500_i2c3_devices_u8500[] = {
+        {
+                I2C_BOARD_INFO("synaptics_rmi4_i2c", 0x4B),
+                .platform_data = &rmi4_i2c_dev_platformdata,
+        },
+};
+
+/*
+ * TC35893
+ */
+static const unsigned int u8500_keymap[] = {
+        KEY(3, 1, KEY_END),
+        KEY(4, 1, KEY_POWER),
+        KEY(6, 4, KEY_VOLUMEDOWN),
+        KEY(4, 2, KEY_EMAIL),
+        KEY(3, 3, KEY_RIGHT),
+        KEY(2, 5, KEY_BACKSPACE),
+
+        KEY(6, 7, KEY_MENU),
+        KEY(5, 0, KEY_ENTER),
+        KEY(4, 3, KEY_0),
+        KEY(3, 4, KEY_DOT),
+        KEY(5, 2, KEY_UP),
+        KEY(3, 5, KEY_DOWN),
+
+        KEY(4, 5, KEY_SEND),
+        KEY(0, 5, KEY_BACK),
+        KEY(6, 2, KEY_VOLUMEUP),
+        KEY(1, 3, KEY_SPACE),
+        KEY(7, 6, KEY_LEFT),
+        KEY(5, 5, KEY_SEARCH),
+};
+
+static struct matrix_keymap_data u8500_keymap_data = {
+        .keymap         = u8500_keymap,
+        .keymap_size    = ARRAY_SIZE(u8500_keymap),
+};
+
+static struct tc3589x_keypad_platform_data tc35893_data = {
+        .krow = TC_KPD_ROWS,
+        .kcol = TC_KPD_COLUMNS,
+        .debounce_period = TC_KPD_DEBOUNCE_PERIOD,
+        .settle_time = TC_KPD_SETTLE_TIME,
+        .irqtype = IRQF_TRIGGER_FALLING,
+        .enable_wakeup = true,
+        .keymap_data    = &u8500_keymap_data,
+        .no_autorepeat  = true,
+};
+
+static struct tc3589x_platform_data tc3589x_keypad_data = {
+        .block = TC3589x_BLOCK_KEYPAD,
+        .keypad = &tc35893_data,
+        .irq_base = MOP500_EGPIO_IRQ_BASE,
+};
+
+static struct i2c_board_info __initdata mop500_i2c0_devices_u8500[] = {
+        {
+                I2C_BOARD_INFO("tc3589x", 0x44),
+                .platform_data = &tc3589x_keypad_data,
+                .irq = NOMADIK_GPIO_TO_IRQ(218),
+                .flags = I2C_CLIENT_WAKE,
+        },
+};
+
+
+void __init mop500_u8500uib_init(void)
+{
+        mop500_uib_i2c_add(3, mop500_i2c3_devices_u8500,
+                        ARRAY_SIZE(mop500_i2c3_devices_u8500));
+
+        mop500_uib_i2c_add(0, mop500_i2c0_devices_u8500,
+                        ARRAY_SIZE(mop500_i2c0_devices_u8500));
+
+}
diff --git a/arch/arm/mach-ux500/board-mop500-uib.c b/arch/arm/mach-ux500/board-mop500-uib.c
new file mode 100644
index 000000000000..69cce41f602a
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-uib.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#define pr_fmt(fmt)     "mop500-uib: " fmt
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+
+#include <mach/hardware.h>
+#include "board-mop500.h"
+
+enum mop500_uib {
+        STUIB,
+        U8500UIB,
+};
+
+struct uib {
+        const char *name;
+        const char *option;
+        void (*init)(void);
+};
+
+static struct __initdata uib mop500_uibs[] = {
+        [STUIB] = {
+                .name   = "ST-UIB",
+                .option = "stuib",
+                .init   = mop500_stuib_init,
+        },
+        [U8500UIB] = {
+                .name   = "U8500-UIB",
+                .option = "u8500uib",
+                .init   = mop500_u8500uib_init,
+        },
+};
+
+static struct uib *mop500_uib;
+
+static int __init mop500_uib_setup(char *str)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(mop500_uibs); i++) {
+                struct uib *uib = &mop500_uibs[i];
+
+                if (!strcmp(str, uib->option)) {
+                        mop500_uib = uib;
+                        break;
+                }
+        }
+
+        if (i == ARRAY_SIZE(mop500_uibs))
+                pr_err("invalid uib= option (%s)\n", str);
+
+        return 1;
+}
+__setup("uib=", mop500_uib_setup);
+
+/*
+ * The UIBs are detected after the I2C host controllers are registered, so
+ * i2c_register_board_info() can't be used.
+ */
+void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
+                unsigned n)
+{
+        struct i2c_adapter *adap;
+        struct i2c_client *client;
+        int i;
+
+        adap = i2c_get_adapter(busnum);
+        if (!adap) {
+                pr_err("failed to get adapter i2c%d\n", busnum);
+                return;
+        }
+
+        for (i = 0; i < n; i++) {
+                client = i2c_new_device(adap, &info[i]);
+                if (!client)
+                        pr_err("failed to register %s to i2c%d\n",
+                                        info[i].type, busnum);
+        }
+
+        i2c_put_adapter(adap);
+}
+
+static void __init __mop500_uib_init(struct uib *uib, const char *why)
+{
+        pr_info("%s (%s)\n", uib->name, why);
+        uib->init();
+}
+
+/*
+ * Detect the UIB attached based on the presence or absence of i2c devices.
+ */
+static int __init mop500_uib_init(void)
+{
+        struct uib *uib = mop500_uib;
+        struct i2c_adapter *i2c0;
+        int ret;
+
+        if (!cpu_is_u8500())
+                return -ENODEV;
+
+        if (uib) {
+                __mop500_uib_init(uib, "from uib= boot argument");
+                return 0;
+        }
+
+        i2c0 = i2c_get_adapter(0);
+        if (!i2c0) {
+                __mop500_uib_init(&mop500_uibs[STUIB],
+                                "fallback, could not get i2c0");
+                return -ENODEV;
+        }
+
+        /* U8500-UIB has the TC35893 at 0x44 on I2C0, the ST-UIB doesn't. */
+        ret = i2c_smbus_xfer(i2c0, 0x44, 0, I2C_SMBUS_WRITE, 0,
+                        I2C_SMBUS_QUICK, NULL);
+        i2c_put_adapter(i2c0);
+
+        if (ret == 0)
+                uib = &mop500_uibs[U8500UIB];
+        else
+                uib = &mop500_uibs[STUIB];
+
+        __mop500_uib_init(uib, "detected");
+
+        return 0;
+}
+
+module_init(mop500_uib_init);
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index a393f57ed2a8..8790d984cac8 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -17,68 +17,30 @@
 #include <linux/gpio.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl022.h>
+#include <linux/amba/serial.h>
 #include <linux/spi/spi.h>
 #include <linux/mfd/ab8500.h>
 #include <linux/mfd/tc3589x.h>
+#include <linux/leds-lp5521.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <plat/pincfg.h>
 #include <plat/i2c.h>
+#include <plat/ste_dma40.h>
 
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
 #include <mach/irqs.h>
 
+#include "ste-dma40-db8500.h"
 #include "devices-db8500.h"
-#include "pins-db8500.h"
 #include "board-mop500.h"
 #include "board-mop500-regulators.h"
 
-static pin_cfg_t mop500_pins[] = {
-        /* SSP0 */
-        GPIO143_SSP0_CLK,
-        GPIO144_SSP0_FRM,
-        GPIO145_SSP0_RXD,
-        GPIO146_SSP0_TXD,
-
-        /* I2C */
-        GPIO147_I2C0_SCL,
-        GPIO148_I2C0_SDA,
-        GPIO16_I2C1_SCL,
-        GPIO17_I2C1_SDA,
-        GPIO10_I2C2_SDA,
-        GPIO11_I2C2_SCL,
-        GPIO229_I2C3_SDA,
-        GPIO230_I2C3_SCL,
-
-        /* SKE keypad */
-        GPIO153_KP_I7,
-        GPIO154_KP_I6,
-        GPIO155_KP_I5,
-        GPIO156_KP_I4,
-        GPIO157_KP_O7,
-        GPIO158_KP_O6,
-        GPIO159_KP_O5,
-        GPIO160_KP_O4,
-        GPIO161_KP_I3,
-        GPIO162_KP_I2,
-        GPIO163_KP_I1,
-        GPIO164_KP_I0,
-        GPIO165_KP_O3,
-        GPIO166_KP_O2,
-        GPIO167_KP_O1,
-        GPIO168_KP_O0,
-
-        /* GPIO_EXP_INT */
-        GPIO217_GPIO,
-
-        /* STMPE1601 IRQ */
-        GPIO218_GPIO    | PIN_INPUT_PULLUP,
-};
-
 static struct ab8500_platform_data ab8500_platdata = {
         .irq_base       = MOP500_AB8500_IRQ_BASE,
         .regulator      = ab8500_regulators,
@@ -103,16 +65,6 @@ struct platform_device ab8500_device = {
         .resource = ab8500_resources,
 };
 
-static struct pl022_ssp_controller ssp0_platform_data = {
-        .bus_id = 0,
-        /* pl022 not yet supports dma */
-        .enable_dma = 0,
-        /* on this platform, gpio 31,142,144,214 &
-         * 224 are connected as chip selects
-         */
-        .num_chipselect = 5,
-};
-
 /*
  * TC35892
  */
@@ -133,14 +85,81 @@ static struct tc3589x_platform_data mop500_tc35892_data = {
         .irq_base       = MOP500_EGPIO_IRQ_BASE,
 };
 
+static struct lp5521_led_config lp5521_pri_led[] = {
+       [0] = {
+               .chan_nr = 0,
+               .led_current = 0x2f,
+               .max_current = 0x5f,
+       },
+       [1] = {
+               .chan_nr = 1,
+               .led_current = 0x2f,
+               .max_current = 0x5f,
+       },
+       [2] = {
+               .chan_nr = 2,
+               .led_current = 0x2f,
+               .max_current = 0x5f,
+       },
+};
+
+static struct lp5521_platform_data __initdata lp5521_pri_data = {
+       .label = "lp5521_pri",
+       .led_config     = &lp5521_pri_led[0],
+       .num_channels   = 3,
+       .clock_mode     = LP5521_CLOCK_EXT,
+};
+
+static struct lp5521_led_config lp5521_sec_led[] = {
+       [0] = {
+               .chan_nr = 0,
+               .led_current = 0x2f,
+               .max_current = 0x5f,
+       },
+       [1] = {
+               .chan_nr = 1,
+               .led_current = 0x2f,
+               .max_current = 0x5f,
+       },
+       [2] = {
+               .chan_nr = 2,
+               .led_current = 0x2f,
+               .max_current = 0x5f,
+       },
+};
+
+static struct lp5521_platform_data __initdata lp5521_sec_data = {
+       .label = "lp5521_sec",
+       .led_config     = &lp5521_sec_led[0],
+       .num_channels   = 3,
+       .clock_mode     = LP5521_CLOCK_EXT,
+};
+
 static struct i2c_board_info mop500_i2c0_devices[] = {
         {
                 I2C_BOARD_INFO("tc3589x", 0x42),
-                .irq            = NOMADIK_GPIO_TO_IRQ(217),
+                .irq            = NOMADIK_GPIO_TO_IRQ(217),
                 .platform_data  = &mop500_tc35892_data,
         },
 };
 
+static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
+        {
+                /* lp5521 LED driver, 1st device */
+                I2C_BOARD_INFO("lp5521", 0x33),
+                .platform_data = &lp5521_pri_data,
+        },
+        {
+                /* lp5521 LED driver, 2st device */
+                I2C_BOARD_INFO("lp5521", 0x34),
+                .platform_data = &lp5521_sec_data,
+        },
+        {
+                /* Light sensor Rohm BH1780GLI */
+                I2C_BOARD_INFO("bh1780", 0x29),
+        },
+};
+
 #define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
 static struct nmk_i2c_controller u8500_i2c##id##_data = { \
         /*                              \
@@ -178,8 +197,93 @@ static void __init mop500_i2c_init(void)
         db8500_add_i2c3(&u8500_i2c3_data);
 }
 
+static struct gpio_keys_button mop500_gpio_keys[] = {
+        {
+                .desc                   = "SFH7741 Proximity Sensor",
+                .type                   = EV_SW,
+                .code                   = SW_FRONT_PROXIMITY,
+                .active_low             = 0,
+                .can_disable            = 1,
+        }
+};
+
+static struct regulator *prox_regulator;
+static int mop500_prox_activate(struct device *dev);
+static void mop500_prox_deactivate(struct device *dev);
+
+static struct gpio_keys_platform_data mop500_gpio_keys_data = {
+        .buttons        = mop500_gpio_keys,
+        .nbuttons       = ARRAY_SIZE(mop500_gpio_keys),
+        .enable         = mop500_prox_activate,
+        .disable        = mop500_prox_deactivate,
+};
+
+static struct platform_device mop500_gpio_keys_device = {
+        .name   = "gpio-keys",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &mop500_gpio_keys_data,
+        },
+};
+
+static int mop500_prox_activate(struct device *dev)
+{
+        prox_regulator = regulator_get(&mop500_gpio_keys_device.dev,
+                                                "vcc");
+        if (IS_ERR(prox_regulator)) {
+                dev_err(&mop500_gpio_keys_device.dev,
+                        "no regulator\n");
+                return PTR_ERR(prox_regulator);
+        }
+        regulator_enable(prox_regulator);
+        return 0;
+}
+
+static void mop500_prox_deactivate(struct device *dev)
+{
+        regulator_disable(prox_regulator);
+        regulator_put(prox_regulator);
+}
+
 /* add any platform devices here - TODO */
 static struct platform_device *platform_devs[] __initdata = {
+        &mop500_gpio_keys_device,
+};
+
+#ifdef CONFIG_STE_DMA40
+static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type =  DB8500_DMA_DEV8_SSP0_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV8_SSP0_TX,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+#endif
+
+static struct pl022_ssp_controller ssp0_platform_data = {
+        .bus_id = 0,
+#ifdef CONFIG_STE_DMA40
+        .enable_dma = 1,
+        .dma_filter = stedma40_filter,
+        .dma_rx_param = &ssp0_dma_cfg_rx,
+        .dma_tx_param = &ssp0_dma_cfg_tx,
+#else
+        .enable_dma = 0,
+#endif
+        /* on this platform, gpio 31,142,144,214 &
+         * 224 are connected as chip selects
+         */
+        .num_chipselect = 5,
 };
 
 static void __init mop500_spi_init(void)
@@ -187,18 +291,108 @@ static void __init mop500_spi_init(void)
         db8500_add_ssp0(&ssp0_platform_data);
 }
 
+#ifdef CONFIG_STE_DMA40
+static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type =  DB8500_DMA_DEV13_UART0_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV13_UART0_TX,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type =  DB8500_DMA_DEV12_UART1_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV12_UART1_TX,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type =  DB8500_DMA_DEV11_UART2_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV11_UART2_TX,
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+#endif
+
+static struct amba_pl011_data uart0_plat = {
+#ifdef CONFIG_STE_DMA40
+        .dma_filter = stedma40_filter,
+        .dma_rx_param = &uart0_dma_cfg_rx,
+        .dma_tx_param = &uart0_dma_cfg_tx,
+#endif
+};
+
+static struct amba_pl011_data uart1_plat = {
+#ifdef CONFIG_STE_DMA40
+        .dma_filter = stedma40_filter,
+        .dma_rx_param = &uart1_dma_cfg_rx,
+        .dma_tx_param = &uart1_dma_cfg_tx,
+#endif
+};
+
+static struct amba_pl011_data uart2_plat = {
+#ifdef CONFIG_STE_DMA40
+        .dma_filter = stedma40_filter,
+        .dma_rx_param = &uart2_dma_cfg_rx,
+        .dma_tx_param = &uart2_dma_cfg_tx,
+#endif
+};
+
 static void __init mop500_uart_init(void)
 {
-        db8500_add_uart0();
-        db8500_add_uart1();
-        db8500_add_uart2();
+        db8500_add_uart0(&uart0_plat);
+        db8500_add_uart1(&uart1_plat);
+        db8500_add_uart2(&uart2_plat);
 }
 
-static void __init u8500_init_machine(void)
+static void __init mop500_init_machine(void)
 {
+        /*
+         * The HREFv60 board removed a GPIO expander and routed
+         * all these GPIO pins to the internal GPIO controller
+         * instead.
+         */
+        if (machine_is_hrefv60())
+                mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
+        else
+                mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
+
         u8500_init_devices();
 
-        nmk_config_pins(mop500_pins, ARRAY_SIZE(mop500_pins));
+        mop500_pins_init();
 
         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
 
@@ -207,12 +401,12 @@ static void __init u8500_init_machine(void)
         mop500_spi_init();
         mop500_uart_init();
 
-        mop500_keypad_init();
-
         platform_device_register(&ab8500_device);
 
         i2c_register_board_info(0, mop500_i2c0_devices,
                                 ARRAY_SIZE(mop500_i2c0_devices));
+        i2c_register_board_info(2, mop500_i2c2_devices,
+                                ARRAY_SIZE(mop500_i2c2_devices));
 }
 
 MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
@@ -222,5 +416,13 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
         .init_irq       = ux500_init_irq,
         /* we re-use nomadik timer here */
         .timer          = &ux500_timer,
-        .init_machine   = u8500_init_machine,
+        .init_machine   = mop500_init_machine,
+MACHINE_END
+
+MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
+        .boot_params    = 0x100,
+        .map_io         = u8500_map_io,
+        .init_irq       = ux500_init_irq,
+        .timer          = &ux500_timer,
+        .init_machine   = mop500_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 3104ae2a02c2..56722f4be71b 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -7,15 +7,36 @@
 #ifndef __BOARD_MOP500_H
 #define __BOARD_MOP500_H
 
-#define MOP500_EGPIO(x)                 (NOMADIK_NR_GPIO + (x))
+/* HREFv60-specific GPIO assignments, this board has no GPIO expander */
+#define HREFV60_TOUCH_RST_GPIO          143
+#define HREFV60_PROX_SENSE_GPIO         217
+#define HREFV60_HAL_SW_GPIO             145
+#define HREFV60_SDMMC_EN_GPIO           169
+#define HREFV60_SDMMC_1V8_3V_GPIO       5
+#define HREFV60_SDMMC_CD_GPIO           95
+#define HREFV60_ACCEL_INT1_GPIO         82
+#define HREFV60_ACCEL_INT2_GPIO         83
+#define HREFV60_MAGNET_DRDY_GPIO        32
+#define HREFV60_DISP1_RST_GPIO          65
+#define HREFV60_DISP2_RST_GPIO          66
 
 /* GPIOs on the TC35892 expander */
+#define MOP500_EGPIO(x)                 (NOMADIK_NR_GPIO + (x))
 #define GPIO_SDMMC_CD                   MOP500_EGPIO(3)
+#define GPIO_PROX_SENSOR                MOP500_EGPIO(7)
+#define GPIO_BU21013_CS                 MOP500_EGPIO(13)
 #define GPIO_SDMMC_EN                   MOP500_EGPIO(17)
 #define GPIO_SDMMC_1V8_3V_SEL           MOP500_EGPIO(18)
 
+struct i2c_board_info;
+
 extern void mop500_sdi_init(void);
 extern void mop500_sdi_tc35892_init(void);
-extern void mop500_keypad_init(void);
+void __init mop500_u8500uib_init(void);
+void __init mop500_stuib_init(void);
+void __init mop500_pins_init(void);
+
+void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
+                unsigned n);
 
 #endif
diff --git a/arch/arm/mach-ux500/board-u5500-sdi.c b/arch/arm/mach-ux500/board-u5500-sdi.c
index 54712acc0394..739fb4c5b160 100644
--- a/arch/arm/mach-ux500/board-u5500-sdi.c
+++ b/arch/arm/mach-ux500/board-u5500-sdi.c
@@ -31,6 +31,26 @@ static pin_cfg_t u5500_sdi_pins[] = {
         GPIO14_MC0_CLK          | PIN_DIR_OUTPUT | PIN_VAL_LOW,
 };
 
+#ifdef CONFIG_STE_DMA40
+struct stedma40_chan_cfg u5500_sdi0_dma_cfg_rx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type = DB5500_DMA_DEV24_SDMMC0_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+
+static struct stedma40_chan_cfg u5500_sdi0_dma_cfg_tx = {
+        .mode = STEDMA40_MODE_LOGICAL,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+        .dst_dev_type = DB5500_DMA_DEV24_SDMMC0_TX,
+        .src_info.data_width = STEDMA40_WORD_WIDTH,
+        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+};
+#endif
+
 static struct mmci_platform_data u5500_sdi0_data = {
         .ocr_mask       = MMC_VDD_165_195,
         .f_max          = 50000000,
@@ -39,6 +59,11 @@ static struct mmci_platform_data u5500_sdi0_data = {
                                 MMC_CAP_MMC_HIGHSPEED,
         .gpio_cd        = -1,
         .gpio_wp        = -1,
+#ifdef CONFIG_STE_DMA40
+        .dma_filter     = stedma40_filter,
+        .dma_rx_param   = &u5500_sdi0_dma_cfg_rx,
+        .dma_tx_param   = &u5500_sdi0_dma_cfg_tx,
+#endif
 };
 
 void __init u5500_sdi_init(void)
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
index 39d370c1f3b4..44fd3b5c33ec 100644
--- a/arch/arm/mach-ux500/board-u5500.c
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -22,9 +22,9 @@
 
 static void __init u5500_uart_init(void)
 {
-        db5500_add_uart0();
-        db5500_add_uart1();
-        db5500_add_uart2();
+        db5500_add_uart0(NULL);
+        db5500_add_uart1(NULL);
+        db5500_add_uart2(NULL);
 }
 
 static void __init u5500_init_machine(void)
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index b2b0a3b9be8f..32ce90840ee1 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -313,7 +313,7 @@ static DEFINE_PRCMU_CLK_RATE(uartclk,	0x0, 5, UARTCLK, 38400000);
 static DEFINE_PRCMU_CLK(msp02clk,       0x0, 6, MSP02CLK);
 static DEFINE_PRCMU_CLK(msp1clk,        0x0, 7, MSP1CLK); /* v1 */
 static DEFINE_PRCMU_CLK_RATE(i2cclk,    0x0, 8, I2CCLK, 48000000);
-static DEFINE_PRCMU_CLK_RATE(sdmmcclk,  0x0, 9, SDMMCCLK, 50000000);
+static DEFINE_PRCMU_CLK_RATE(sdmmcclk,  0x0, 9, SDMMCCLK, 100000000);
 static DEFINE_PRCMU_CLK(slimclk,        0x0, 10, SLIMCLK);
 static DEFINE_PRCMU_CLK(per1clk,        0x0, 11, PER1CLK);
 static DEFINE_PRCMU_CLK(per2clk,        0x0, 12, PER2CLK);
@@ -520,7 +520,7 @@ static struct clk_lookup u8500_ed_clks[] = {
         CLK(ssp0_ed,    "ssp0",         NULL),
 
         /* Peripheral Cluster #5 */
-        CLK(usb_ed,     "musb_hdrc.0",  "usb"),
+        CLK(usb_ed,     "musb-ux500.0", "usb"),
 
         /* Peripheral Cluster #6 */
         CLK(dmc_ed,     "dmc",          NULL),
@@ -561,7 +561,7 @@ static struct clk_lookup u8500_v1_clks[] = {
         CLK(ssp0_v1,    "ssp0",         NULL),
 
         /* Peripheral Cluster #5 */
-        CLK(usb_v1,     "musb_hdrc.0",  "usb"),
+        CLK(usb_v1,     "musb-ux500.0", "usb"),
 
         /* Peripheral Cluster #6 */
         CLK(mtu1_v1,    "mtu1",         NULL),
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index af04e0891a78..c9dc2eff3cb2 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -11,6 +11,7 @@
 #include <linux/irq.h>
 
 #include <asm/mach/map.h>
+#include <asm/pmu.h>
 
 #include <plat/gpio.h>
 
@@ -18,8 +19,10 @@
 #include <mach/devices.h>
 #include <mach/setup.h>
 #include <mach/irqs.h>
+#include <mach/usb.h>
 
 #include "devices-db5500.h"
+#include "ste-dma40-db5500.h"
 
 static struct map_desc u5500_uart_io_desc[] __initdata = {
         __IO_DEV_DESC(U5500_UART0_BASE, SZ_4K),
@@ -43,6 +46,26 @@ static struct map_desc u5500_io_desc[] __initdata = {
         __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K),
 };
 
+static struct resource db5500_pmu_resources[] = {
+        [0] = {
+                .start          = IRQ_DB5500_PMU0,
+                .end            = IRQ_DB5500_PMU0,
+                .flags          = IORESOURCE_IRQ,
+        },
+        [1] = {
+                .start          = IRQ_DB5500_PMU1,
+                .end            = IRQ_DB5500_PMU1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device db5500_pmu_device = {
+        .name                   = "arm-pmu",
+        .id                     = ARM_PMU_DEVICE_CPU,
+        .num_resources          = ARRAY_SIZE(db5500_pmu_resources),
+        .resource               = db5500_pmu_resources,
+};
+
 static struct resource mbox0_resources[] = {
         {
                 .name = "mbox_peer",
@@ -127,7 +150,8 @@ static struct platform_device mbox2_device = {
         .num_resources = ARRAY_SIZE(mbox2_resources),
 };
 
-static struct platform_device *u5500_platform_devs[] __initdata = {
+static struct platform_device *db5500_platform_devs[] __initdata = {
+        &db5500_pmu_device,
         &mbox0_device,
         &mbox1_device,
         &mbox2_device,
@@ -166,12 +190,35 @@ void __init u5500_map_io(void)
         iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc));
 }
 
+static int usb_db5500_rx_dma_cfg[] = {
+        DB5500_DMA_DEV4_USB_OTG_IEP_1_9,
+        DB5500_DMA_DEV5_USB_OTG_IEP_2_10,
+        DB5500_DMA_DEV6_USB_OTG_IEP_3_11,
+        DB5500_DMA_DEV20_USB_OTG_IEP_4_12,
+        DB5500_DMA_DEV21_USB_OTG_IEP_5_13,
+        DB5500_DMA_DEV22_USB_OTG_IEP_6_14,
+        DB5500_DMA_DEV23_USB_OTG_IEP_7_15,
+        DB5500_DMA_DEV38_USB_OTG_IEP_8
+};
+
+static int usb_db5500_tx_dma_cfg[] = {
+        DB5500_DMA_DEV4_USB_OTG_OEP_1_9,
+        DB5500_DMA_DEV5_USB_OTG_OEP_2_10,
+        DB5500_DMA_DEV6_USB_OTG_OEP_3_11,
+        DB5500_DMA_DEV20_USB_OTG_OEP_4_12,
+        DB5500_DMA_DEV21_USB_OTG_OEP_5_13,
+        DB5500_DMA_DEV22_USB_OTG_OEP_6_14,
+        DB5500_DMA_DEV23_USB_OTG_OEP_7_15,
+        DB5500_DMA_DEV38_USB_OTG_OEP_8
+};
+
 void __init u5500_init_devices(void)
 {
         db5500_add_gpios();
         db5500_dma_init();
         db5500_add_rtc();
+        db5500_add_usb(usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg);
 
-        platform_add_devices(u5500_platform_devs,
-                             ARRAY_SIZE(u5500_platform_devs));
+        platform_add_devices(db5500_platform_devs,
+                             ARRAY_SIZE(db5500_platform_devs));
 }
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 1748fbc58530..516126cb357d 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -12,21 +12,21 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/amba/bus.h>
+#include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 
 #include <asm/mach/map.h>
+#include <asm/pmu.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
+#include <mach/usb.h>
 
 #include "devices-db8500.h"
-
-static struct platform_device *platform_devs[] __initdata = {
-        &u8500_dma40_device,
-};
+#include "ste-dma40-db8500.h"
 
 /* minimum static i/o mapping required to boot U8500 platforms */
 static struct map_desc u8500_uart_io_desc[] __initdata = {
@@ -89,6 +89,51 @@ void __init u8500_map_io(void)
                 iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
 }
 
+static struct resource db8500_pmu_resources[] = {
+        [0] = {
+                .start          = IRQ_DB8500_PMU,
+                .end            = IRQ_DB8500_PMU,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+/*
+ * The PMU IRQ lines of two cores are wired together into a single interrupt.
+ * Bounce the interrupt to the other core if it's not ours.
+ */
+static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler)
+{
+        irqreturn_t ret = handler(irq, dev);
+        int other = !smp_processor_id();
+
+        if (ret == IRQ_NONE && cpu_online(other))
+                irq_set_affinity(irq, cpumask_of(other));
+
+        /*
+         * We should be able to get away with the amount of IRQ_NONEs we give,
+         * while still having the spurious IRQ detection code kick in if the
+         * interrupt really starts hitting spuriously.
+         */
+        return ret;
+}
+
+static struct arm_pmu_platdata db8500_pmu_platdata = {
+        .handle_irq             = db8500_pmu_handler,
+};
+
+static struct platform_device db8500_pmu_device = {
+        .name                   = "arm-pmu",
+        .id                     = ARM_PMU_DEVICE_CPU,
+        .num_resources          = ARRAY_SIZE(db8500_pmu_resources),
+        .resource               = db8500_pmu_resources,
+        .dev.platform_data      = &db8500_pmu_platdata,
+};
+
+static struct platform_device *platform_devs[] __initdata = {
+        &u8500_dma40_device,
+        &db8500_pmu_device,
+};
+
 static resource_size_t __initdata db8500_gpio_base[] = {
         U8500_GPIOBANK0_BASE,
         U8500_GPIOBANK1_BASE,
@@ -111,6 +156,28 @@ static void __init db8500_add_gpios(void)
                          IRQ_DB8500_GPIO0, &pdata);
 }
 
+static int usb_db8500_rx_dma_cfg[] = {
+        DB8500_DMA_DEV38_USB_OTG_IEP_1_9,
+        DB8500_DMA_DEV37_USB_OTG_IEP_2_10,
+        DB8500_DMA_DEV36_USB_OTG_IEP_3_11,
+        DB8500_DMA_DEV19_USB_OTG_IEP_4_12,
+        DB8500_DMA_DEV18_USB_OTG_IEP_5_13,
+        DB8500_DMA_DEV17_USB_OTG_IEP_6_14,
+        DB8500_DMA_DEV16_USB_OTG_IEP_7_15,
+        DB8500_DMA_DEV39_USB_OTG_IEP_8
+};
+
+static int usb_db8500_tx_dma_cfg[] = {
+        DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
+        DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
+        DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
+        DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
+        DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
+        DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
+        DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
+        DB8500_DMA_DEV39_USB_OTG_OEP_8
+};
+
 /*
  * This function is called from the board init
  */
@@ -121,6 +188,7 @@ void __init u8500_init_devices(void)
 
         db8500_add_rtc();
         db8500_add_gpios();
+        db8500_add_usb(usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
 
         platform_device_register_simple("cpufreq-u8500", -1, NULL, 0);
         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c
index fe69f5fac1bb..13a4ce046ae5 100644
--- a/arch/arm/mach-ux500/devices-common.c
+++ b/arch/arm/mach-ux500/devices-common.c
@@ -139,6 +139,7 @@ void dbx500_add_gpios(resource_size_t *base, int num, int irq,
         for (i = 0; i < num; i++, first += 32, irq++) {
                 pdata->first_gpio = first;
                 pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first);
+                pdata->num_gpio = 32;
 
                 dbx500_add_gpio(i, base[i], irq, pdata);
         }
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index cbadc117d2db..c719b5a1d913 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -42,10 +42,13 @@ dbx500_add_sdi(const char *name, resource_size_t base, int irq,
         return dbx500_add_amba_device(name, base, irq, pdata, 0);
 }
 
+struct amba_pl011_data;
+
 static inline struct amba_device *
-dbx500_add_uart(const char *name, resource_size_t base, int irq)
+dbx500_add_uart(const char *name, resource_size_t base, int irq,
+                struct amba_pl011_data *pdata)
 {
-        return dbx500_add_amba_device(name, base, irq, NULL, 0);
+        return dbx500_add_amba_device(name, base, irq, pdata, 0);
 }
 
 struct nmk_i2c_controller;
diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h
index c8d7901c1f2d..94627f7783b0 100644
--- a/arch/arm/mach-ux500/devices-db5500.h
+++ b/arch/arm/mach-ux500/devices-db5500.h
@@ -34,6 +34,9 @@
 #define db5500_add_rtc() \
         dbx500_add_rtc(U5500_RTC_BASE, IRQ_DB5500_RTC);
 
+#define db5500_add_usb(rx_cfg, tx_cfg) \
+        ux500_add_usb(U5500_USBOTG_BASE, IRQ_DB5500_USBOTG, rx_cfg, tx_cfg)
+
 #define db5500_add_sdi0(pdata) \
         dbx500_add_sdi("sdi0", U5500_SDI0_BASE, IRQ_DB5500_SDMMC0, pdata)
 #define db5500_add_sdi1(pdata) \
@@ -54,13 +57,13 @@
 #define db5500_add_spi3(pdata) \
         dbx500_add_spi("spi3", U5500_SPI3_BASE, IRQ_DB5500_SPI3, pdata)
 
-#define db5500_add_uart0() \
-        dbx500_add_uart("uart0", U5500_UART0_BASE, IRQ_DB5500_UART0)
-#define db5500_add_uart1() \
-        dbx500_add_uart("uart1", U5500_UART1_BASE, IRQ_DB5500_UART1)
-#define db5500_add_uart2() \
-        dbx500_add_uart("uart2", U5500_UART2_BASE, IRQ_DB5500_UART2)
-#define db5500_add_uart3() \
-        dbx500_add_uart("uart3", U5500_UART3_BASE, IRQ_DB5500_UART3)
+#define db5500_add_uart0(plat) \
+        dbx500_add_uart("uart0", U5500_UART0_BASE, IRQ_DB5500_UART0, plat)
+#define db5500_add_uart1(plat) \
+        dbx500_add_uart("uart1", U5500_UART1_BASE, IRQ_DB5500_UART1, plat)
+#define db5500_add_uart2(plat) \
+        dbx500_add_uart("uart2", U5500_UART2_BASE, IRQ_DB5500_UART2, plat)
+#define db5500_add_uart3(plat) \
+        dbx500_add_uart("uart3", U5500_UART3_BASE, IRQ_DB5500_UART3, plat)
 
 #endif
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 23c695d54977..73b17404b194 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -11,6 +11,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/pl022.h>
 
 #include <plat/ste_dma40.h>
 
@@ -67,12 +68,72 @@ struct stedma40_chan_cfg dma40_memcpy_conf_log = {
 
 /*
  * Mapping between destination event lines and physical device address.
- * The event line is tied to a device and therefor the address is constant.
+ * The event line is tied to a device and therefore the address is constant.
+ * When the address comes from a primecell it will be configured in runtime
+ * and we set the address to -1 as a placeholder.
  */
-static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV];
+static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
+        /* MUSB - these will be runtime-reconfigured */
+        [DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,
+        [DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,
+        [DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,
+        [DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,
+        [DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,
+        [DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,
+        [DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,
+        [DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,
+        /* PrimeCells - run-time configured */
+        [DB8500_DMA_DEV0_SPI0_TX] = -1,
+        [DB8500_DMA_DEV1_SD_MMC0_TX] = -1,
+        [DB8500_DMA_DEV2_SD_MMC1_TX] = -1,
+        [DB8500_DMA_DEV3_SD_MMC2_TX] = -1,
+        [DB8500_DMA_DEV8_SSP0_TX] = -1,
+        [DB8500_DMA_DEV9_SSP1_TX] = -1,
+        [DB8500_DMA_DEV11_UART2_TX] = -1,
+        [DB8500_DMA_DEV12_UART1_TX] = -1,
+        [DB8500_DMA_DEV13_UART0_TX] = -1,
+        [DB8500_DMA_DEV28_SD_MM2_TX] = -1,
+        [DB8500_DMA_DEV29_SD_MM0_TX] = -1,
+        [DB8500_DMA_DEV32_SD_MM1_TX] = -1,
+        [DB8500_DMA_DEV33_SPI2_TX] = -1,
+        [DB8500_DMA_DEV35_SPI1_TX] = -1,
+        [DB8500_DMA_DEV40_SPI3_TX] = -1,
+        [DB8500_DMA_DEV41_SD_MM3_TX] = -1,
+        [DB8500_DMA_DEV42_SD_MM4_TX] = -1,
+        [DB8500_DMA_DEV43_SD_MM5_TX] = -1,
+};
 
 /* Mapping between source event lines and physical device address */
-static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV];
+static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
+        /* MUSB - these will be runtime-reconfigured */
+        [DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,
+        [DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,
+        [DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,
+        [DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,
+        [DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,
+        [DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,
+        [DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,
+        [DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,
+        /* PrimeCells */
+        [DB8500_DMA_DEV0_SPI0_RX] = -1,
+        [DB8500_DMA_DEV1_SD_MMC0_RX] = -1,
+        [DB8500_DMA_DEV2_SD_MMC1_RX] = -1,
+        [DB8500_DMA_DEV3_SD_MMC2_RX] = -1,
+        [DB8500_DMA_DEV8_SSP0_RX] = -1,
+        [DB8500_DMA_DEV9_SSP1_RX] = -1,
+        [DB8500_DMA_DEV11_UART2_RX] = -1,
+        [DB8500_DMA_DEV12_UART1_RX] = -1,
+        [DB8500_DMA_DEV13_UART0_RX] = -1,
+        [DB8500_DMA_DEV28_SD_MM2_RX] = -1,
+        [DB8500_DMA_DEV29_SD_MM0_RX] = -1,
+        [DB8500_DMA_DEV32_SD_MM1_RX] = -1,
+        [DB8500_DMA_DEV33_SPI2_RX] = -1,
+        [DB8500_DMA_DEV35_SPI1_RX] = -1,
+        [DB8500_DMA_DEV40_SPI3_RX] = -1,
+        [DB8500_DMA_DEV41_SD_MM3_RX] = -1,
+        [DB8500_DMA_DEV42_SD_MM4_RX] = -1,
+        [DB8500_DMA_DEV43_SD_MM5_RX] = -1,
+};
 
 /* Reserved event lines for memcpy only */
 static int dma40_memcpy_event[] = {
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index 3a770c756979..9cc6f8f5d3e6 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -61,6 +61,9 @@ db8500_add_ssp(const char *name, resource_size_t base, int irq,
 #define db8500_add_rtc() \
         dbx500_add_rtc(U8500_RTC_BASE, IRQ_DB8500_RTC);
 
+#define db8500_add_usb(rx_cfg, tx_cfg) \
+        ux500_add_usb(U8500_USBOTG_BASE, IRQ_DB8500_USBOTG, rx_cfg, tx_cfg)
+
 #define db8500_add_sdi0(pdata) \
         dbx500_add_sdi("sdi0", U8500_SDI0_BASE, IRQ_DB8500_SDMMC0, pdata)
 #define db8500_add_sdi1(pdata) \
@@ -88,11 +91,11 @@ db8500_add_ssp(const char *name, resource_size_t base, int irq,
 #define db8500_add_spi3(pdata) \
         dbx500_add_spi("spi3", U8500_SPI3_BASE, IRQ_DB8500_SPI3, pdata)
 
-#define db8500_add_uart0() \
-        dbx500_add_uart("uart0", U8500_UART0_BASE, IRQ_DB8500_UART0)
-#define db8500_add_uart1() \
-        dbx500_add_uart("uart1", U8500_UART1_BASE, IRQ_DB8500_UART1)
-#define db8500_add_uart2() \
-        dbx500_add_uart("uart2", U8500_UART2_BASE, IRQ_DB8500_UART2)
+#define db8500_add_uart0(pdata) \
+        dbx500_add_uart("uart0", U8500_UART0_BASE, IRQ_DB8500_UART0, pdata)
+#define db8500_add_uart1(pdata) \
+        dbx500_add_uart("uart1", U8500_UART1_BASE, IRQ_DB8500_UART1, pdata)
+#define db8500_add_uart2(pdata) \
+        dbx500_add_uart("uart2", U8500_UART2_BASE, IRQ_DB8500_UART2, pdata)
 
 #endif
diff --git a/arch/arm/mach-ux500/dma-db5500.c b/arch/arm/mach-ux500/dma-db5500.c
index 32a061f8a95b..1cfab68ae417 100644
--- a/arch/arm/mach-ux500/dma-db5500.c
+++ b/arch/arm/mach-ux500/dma-db5500.c
@@ -73,11 +73,27 @@ static struct stedma40_chan_cfg dma40_memcpy_conf_log = {
  */
 static const dma_addr_t dma40_rx_map[DB5500_DMA_NR_DEV] = {
         [DB5500_DMA_DEV24_SDMMC0_RX] = -1,
+        [DB5500_DMA_DEV38_USB_OTG_IEP_8] = -1,
+        [DB5500_DMA_DEV23_USB_OTG_IEP_7_15] = -1,
+        [DB5500_DMA_DEV22_USB_OTG_IEP_6_14] = -1,
+        [DB5500_DMA_DEV21_USB_OTG_IEP_5_13] = -1,
+        [DB5500_DMA_DEV20_USB_OTG_IEP_4_12] = -1,
+        [DB5500_DMA_DEV6_USB_OTG_IEP_3_11] = -1,
+        [DB5500_DMA_DEV5_USB_OTG_IEP_2_10] = -1,
+        [DB5500_DMA_DEV4_USB_OTG_IEP_1_9] = -1,
 };
 
 /* Mapping between destination event lines and physical device address */
 static const dma_addr_t dma40_tx_map[DB5500_DMA_NR_DEV] = {
         [DB5500_DMA_DEV24_SDMMC0_TX] = -1,
+        [DB5500_DMA_DEV38_USB_OTG_OEP_8] = -1,
+        [DB5500_DMA_DEV23_USB_OTG_OEP_7_15] = -1,
+        [DB5500_DMA_DEV22_USB_OTG_OEP_6_14] = -1,
+        [DB5500_DMA_DEV21_USB_OTG_OEP_5_13] = -1,
+        [DB5500_DMA_DEV20_USB_OTG_OEP_4_12] = -1,
+        [DB5500_DMA_DEV6_USB_OTG_OEP_3_11] = -1,
+        [DB5500_DMA_DEV5_USB_OTG_OEP_2_10] = -1,
+        [DB5500_DMA_DEV4_USB_OTG_OEP_1_9] = -1,
 };
 
 static int dma40_memcpy_event[] = {
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 9a6614c6808e..ab0fe1432fae 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -50,7 +50,11 @@ static void flush(void)
 
 static inline void arch_decomp_setup(void)
 {
-        if (machine_is_u8500())
+        /* Check in run time if we run on an U8500 or U5500 */
+        if (machine_is_u8500() ||
+            machine_is_svp8500v1() ||
+            machine_is_svp8500v2() ||
+            machine_is_hrefv60())
                 ux500_uart_base = U8500_UART2_BASE;
         else if (machine_is_u5500())
                 ux500_uart_base = U5500_UART0_BASE;
diff --git a/arch/arm/mach-ux500/include/mach/usb.h b/arch/arm/mach-ux500/include/mach/usb.h
new file mode 100644
index 000000000000..d3739d418813
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/usb.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2011
+ *
+ * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef __ASM_ARCH_USB_H
+#define __ASM_ARCH_USB_H
+
+#include <linux/dmaengine.h>
+
+#define UX500_MUSB_DMA_NUM_RX_CHANNELS 8
+#define UX500_MUSB_DMA_NUM_TX_CHANNELS 8
+
+struct ux500_musb_board_data {
+        void    **dma_rx_param_array;
+        void    **dma_tx_param_array;
+        u32     num_rx_channels;
+        u32     num_tx_channels;
+        bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
+};
+
+void ux500_add_usb(resource_size_t base, int irq, int *dma_rx_cfg,
+        int *dma_tx_cfg);
+#endif
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
new file mode 100644
index 000000000000..82e535953fd9
--- /dev/null
+++ b/arch/arm/mach-ux500/usb.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2011
+ *
+ * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#include <linux/platform_device.h>
+#include <linux/usb/musb.h>
+#include <plat/ste_dma40.h>
+#include <mach/hardware.h>
+#include <mach/usb.h>
+
+#define MUSB_DMA40_RX_CH { \
+                .mode = STEDMA40_MODE_LOGICAL, \
+                .dir = STEDMA40_PERIPH_TO_MEM, \
+                .dst_dev_type = STEDMA40_DEV_DST_MEMORY, \
+                .src_info.data_width = STEDMA40_WORD_WIDTH, \
+                .dst_info.data_width = STEDMA40_WORD_WIDTH, \
+                .src_info.psize = STEDMA40_PSIZE_LOG_16, \
+                .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
+        }
+
+#define MUSB_DMA40_TX_CH { \
+                .mode = STEDMA40_MODE_LOGICAL, \
+                .dir = STEDMA40_MEM_TO_PERIPH, \
+                .src_dev_type = STEDMA40_DEV_SRC_MEMORY, \
+                .src_info.data_width = STEDMA40_WORD_WIDTH, \
+                .dst_info.data_width = STEDMA40_WORD_WIDTH, \
+                .src_info.psize = STEDMA40_PSIZE_LOG_16, \
+                .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
+        }
+
+static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
+        = {
+        MUSB_DMA40_RX_CH,
+        MUSB_DMA40_RX_CH,
+        MUSB_DMA40_RX_CH,
+        MUSB_DMA40_RX_CH,
+        MUSB_DMA40_RX_CH,
+        MUSB_DMA40_RX_CH,
+        MUSB_DMA40_RX_CH,
+        MUSB_DMA40_RX_CH
+};
+
+static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS]
+        = {
+        MUSB_DMA40_TX_CH,
+        MUSB_DMA40_TX_CH,
+        MUSB_DMA40_TX_CH,
+        MUSB_DMA40_TX_CH,
+        MUSB_DMA40_TX_CH,
+        MUSB_DMA40_TX_CH,
+        MUSB_DMA40_TX_CH,
+        MUSB_DMA40_TX_CH,
+};
+
+static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = {
+        &musb_dma_rx_ch[0],
+        &musb_dma_rx_ch[1],
+        &musb_dma_rx_ch[2],
+        &musb_dma_rx_ch[3],
+        &musb_dma_rx_ch[4],
+        &musb_dma_rx_ch[5],
+        &musb_dma_rx_ch[6],
+        &musb_dma_rx_ch[7]
+};
+
+static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = {
+        &musb_dma_tx_ch[0],
+        &musb_dma_tx_ch[1],
+        &musb_dma_tx_ch[2],
+        &musb_dma_tx_ch[3],
+        &musb_dma_tx_ch[4],
+        &musb_dma_tx_ch[5],
+        &musb_dma_tx_ch[6],
+        &musb_dma_tx_ch[7]
+};
+
+static struct ux500_musb_board_data musb_board_data = {
+        .dma_rx_param_array = ux500_dma_rx_param_array,
+        .dma_tx_param_array = ux500_dma_tx_param_array,
+        .num_rx_channels = UX500_MUSB_DMA_NUM_RX_CHANNELS,
+        .num_tx_channels = UX500_MUSB_DMA_NUM_TX_CHANNELS,
+        .dma_filter = stedma40_filter,
+};
+
+static u64 ux500_musb_dmamask = DMA_BIT_MASK(32);
+
+static struct musb_hdrc_config musb_hdrc_config = {
+        .multipoint     = true,
+        .dyn_fifo       = true,
+        .num_eps        = 16,
+        .ram_bits       = 16,
+};
+
+static struct musb_hdrc_platform_data musb_platform_data = {
+#if defined(CONFIG_USB_MUSB_OTG)
+        .mode = MUSB_OTG,
+#elif defined(CONFIG_USB_MUSB_PERIPHERAL)
+        .mode = MUSB_PERIPHERAL,
+#else /* defined(CONFIG_USB_MUSB_HOST) */
+        .mode = MUSB_HOST,
+#endif
+        .config = &musb_hdrc_config,
+        .board_data = &musb_board_data,
+};
+
+static struct resource usb_resources[] = {
+        [0] = {
+                .name   = "usb-mem",
+                .flags  =  IORESOURCE_MEM,
+        },
+
+        [1] = {
+                .name   = "mc", /* hard-coded in musb */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device ux500_musb_device = {
+        .name = "musb-ux500",
+        .id = 0,
+        .dev = {
+                .platform_data = &musb_platform_data,
+                .dma_mask = &ux500_musb_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .num_resources = ARRAY_SIZE(usb_resources),
+        .resource = usb_resources,
+};
+
+static inline void ux500_usb_dma_update_rx_ch_config(int *src_dev_type)
+{
+        u32 idx;
+
+        for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_CHANNELS; idx++)
+                musb_dma_rx_ch[idx].src_dev_type = src_dev_type[idx];
+}
+
+static inline void ux500_usb_dma_update_tx_ch_config(int *dst_dev_type)
+{
+        u32 idx;
+
+        for (idx = 0; idx < UX500_MUSB_DMA_NUM_TX_CHANNELS; idx++)
+                musb_dma_tx_ch[idx].dst_dev_type = dst_dev_type[idx];
+}
+
+void ux500_add_usb(resource_size_t base, int irq, int *dma_rx_cfg,
+        int *dma_tx_cfg)
+{
+        ux500_musb_device.resource[0].start = base;
+        ux500_musb_device.resource[0].end = base + SZ_64K - 1;
+        ux500_musb_device.resource[1].start = irq;
+        ux500_musb_device.resource[1].end = irq;
+
+        ux500_usb_dma_update_rx_ch_config(dma_rx_cfg);
+        ux500_usb_dma_update_tx_ch_config(dma_tx_cfg);
+
+        platform_device_register(&ux500_musb_device);
+}
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 89266382b536..0074b8dba793 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -819,8 +819,8 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 config CACHE_L2X0
         bool "Enable the L2x0 outer cache controller"
         depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
-                   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \
+                   REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
+                   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
                    ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
         default y
         select OUTER_CACHE
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 389f21795015..b0cb4258e382 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -33,6 +33,7 @@ config ARCH_MX3
 config ARCH_MXC91231
         bool "MXC91231-based"
         select CPU_V6
+        select MXC_AVIC
         help
           This enables support for systems based on the Freescale MXC91231 family
 
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 5fd20e96876c..a1387875a491 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -13,7 +13,6 @@ obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
-obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index e9bcefe79a43..eee1b6096a08 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -81,6 +81,8 @@ struct platform_device *__init imx_add_platform_device_dmamask(
         ret = platform_device_add(pdev);
         if (ret) {
 err:
+                if (dmamask)
+                        kfree(pdev->dev.dma_mask);
                 platform_device_put(pdev);
                 return ERR_PTR(ret);
         }
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c
index b50c3517d083..6561c9df5f0d 100644
--- a/arch/arm/plat-mxc/devices/platform-fec.c
+++ b/arch/arm/plat-mxc/devices/platform-fec.c
@@ -31,6 +31,11 @@ const struct imx_fec_data imx35_fec_data __initconst =
         imx_fec_data_entry_single(MX35);
 #endif
 
+#ifdef CONFIG_SOC_IMX50
+const struct imx_fec_data imx50_fec_data __initconst =
+        imx_fec_data_entry_single(MX50);
+#endif
+
 #ifdef CONFIG_SOC_IMX51
 const struct imx_fec_data imx51_fec_data __initconst =
         imx_fec_data_entry_single(MX51);
@@ -57,7 +62,7 @@ struct platform_device *__init imx_add_fec(
                 },
         };
 
-        return imx_add_platform_device("fec", 0 /* -1? */,
+        return imx_add_platform_device_dmamask("fec", 0,
                         res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata));
+                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
 }
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c
index 33530d2d5ed1..3538b85ede91 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-dma.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c
@@ -94,7 +94,7 @@ static struct sdma_script_start_addrs addr_imx25_to1 = {
 };
 #endif
 
-#ifdef CONFIG_ARCH_MX31
+#ifdef CONFIG_SOC_IMX31
 static struct sdma_script_start_addrs addr_imx31_to1 = {
         .per_2_per_addr = 1677,
 };
@@ -106,7 +106,7 @@ static struct sdma_script_start_addrs addr_imx31_to2 = {
 };
 #endif
 
-#ifdef CONFIG_ARCH_MX35
+#ifdef CONFIG_SOC_IMX35
 static struct sdma_script_start_addrs addr_imx35_to1 = {
         .ap_2_ap_addr = 642,
         .uart_2_mcu_addr = 817,
@@ -194,7 +194,7 @@ static int __init imxXX_add_imx_dma(void)
         } else
 #endif
 
-#if defined(CONFIG_ARCH_MX51)
+#if defined(CONFIG_SOC_IMX51)
         if (cpu_is_mx51()) {
                 imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1;
                 ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c
index 6100a7d824dd..79a1cb18a5b0 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-fb.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c
@@ -16,6 +16,11 @@
                 .irq = soc ## _INT_LCDC,                                \
         }
 
+#ifdef CONFIG_SOC_IMX1
+const struct imx_imx_fb_data imx1_imx_fb_data __initconst =
+        imx_imx_fb_data_entry_single(MX1, SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX1 */
+
 #ifdef CONFIG_SOC_IMX21
 const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
         imx_imx_fb_data_entry_single(MX21, SZ_4K);
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index 7ba94e1bbda3..2ab74f0da9a6 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -69,6 +69,16 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
+#ifdef CONFIG_SOC_IMX50
+const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst = {
+#define imx50_imx_i2c_data_entry(_id, _hwid)                            \
+        imx_imx_i2c_data_entry(MX50, _id, _hwid, SZ_4K)
+        imx50_imx_i2c_data_entry(0, 1),
+        imx50_imx_i2c_data_entry(1, 2),
+        imx50_imx_i2c_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
 #ifdef CONFIG_SOC_IMX51
 const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
 #define imx51_imx_i2c_data_entry(_id, _hwid)                            \
diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
index e0aec61177f4..5e07ef2bf1c4 100644
--- a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
+++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
@@ -53,6 +53,15 @@ const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX51 */
 
+#ifdef CONFIG_SOC_IMX53
+const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst = {
+#define imx53_imx2_wdt_data_entry(_id, _hwid)                           \
+        imx_imx2_wdt_data_entry(MX53, _id, _hwid, SZ_16K)
+        imx53_imx2_wdt_data_entry(0, 1),
+        imx53_imx2_wdt_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
 struct platform_device *__init imx_add_imx2_wdt(
                 const struct imx_imx2_wdt_data *data)
 {
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 013c85f20b58..f4a60ab6763b 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -21,6 +21,15 @@
 #define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size)        \
         [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size)
 
+#ifdef CONFIG_SOC_IMX1
+const struct imx_spi_imx_data imx1_cspi_data[] __initconst = {
+#define imx1_cspi_data_entry(_id, _hwid) \
+        imx_spi_imx_data_entry(MX1, CSPI, "imx1-cspi", _id, _hwid, SZ_4K)
+        imx1_cspi_data_entry(0, 1),
+        imx1_cspi_data_entry(1, 2),
+};
+#endif
+
 #ifdef CONFIG_SOC_IMX21
 const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
 #define imx21_cspi_data_entry(_id, _hwid)                            \
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
deleted file mode 100644
index 8772ce346a58..000000000000
--- a/arch/arm/plat-mxc/ehci.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * for more details.
- */
-
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/mxc_ehci.h>
-
-#define USBCTRL_OTGBASE_OFFSET  0x600
-
-#define MX31_OTG_SIC_SHIFT      29
-#define MX31_OTG_SIC_MASK       (0x3 << MX31_OTG_SIC_SHIFT)
-#define MX31_OTG_PM_BIT         (1 << 24)
-
-#define MX31_H2_SIC_SHIFT       21
-#define MX31_H2_SIC_MASK        (0x3 << MX31_H2_SIC_SHIFT)
-#define MX31_H2_PM_BIT          (1 << 16)
-#define MX31_H2_DT_BIT          (1 << 5)
-
-#define MX31_H1_SIC_SHIFT       13
-#define MX31_H1_SIC_MASK        (0x3 << MX31_H1_SIC_SHIFT)
-#define MX31_H1_PM_BIT          (1 << 8)
-#define MX31_H1_DT_BIT          (1 << 4)
-
-#define MX35_OTG_SIC_SHIFT      29
-#define MX35_OTG_SIC_MASK       (0x3 << MX35_OTG_SIC_SHIFT)
-#define MX35_OTG_PM_BIT         (1 << 24)
-
-#define MX35_H1_SIC_SHIFT       21
-#define MX35_H1_SIC_MASK        (0x3 << MX35_H1_SIC_SHIFT)
-#define MX35_H1_PM_BIT          (1 << 8)
-#define MX35_H1_IPPUE_UP_BIT    (1 << 7)
-#define MX35_H1_IPPUE_DOWN_BIT  (1 << 6)
-#define MX35_H1_TLL_BIT         (1 << 5)
-#define MX35_H1_USBTE_BIT       (1 << 4)
-
-#define MXC_OTG_OFFSET          0
-#define MXC_H1_OFFSET           0x200
-#define MXC_H2_OFFSET           0x400
-
-/* USB_CTRL */
-#define MXC_OTG_UCTRL_OWIE_BIT          (1 << 27)       /* OTG wakeup intr enable */
-#define MXC_OTG_UCTRL_OPM_BIT           (1 << 24)       /* OTG power mask */
-#define MXC_H1_UCTRL_H1UIE_BIT          (1 << 12)       /* Host1 ULPI interrupt enable */
-#define MXC_H1_UCTRL_H1WIE_BIT          (1 << 11)       /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT           (1 <<  8)               /* HOST1 power mask */
-
-/* USB_PHY_CTRL_FUNC */
-#define MXC_OTG_PHYCTRL_OC_DIS_BIT      (1 << 8)        /* OTG Disable Overcurrent Event */
-#define MXC_H1_OC_DIS_BIT                       (1 << 5)        /* UH1 Disable Overcurrent Event */
-
-/* USBH2CTRL */
-#define MXC_H2_UCTRL_H2UIE_BIT          (1 << 8)
-#define MXC_H2_UCTRL_H2WIE_BIT          (1 << 7)
-#define MXC_H2_UCTRL_H2PM_BIT           (1 << 4)
-
-#define MXC_USBCMD_OFFSET                       0x140
-
-/* USBCMD */
-#define MXC_UCMD_ITC_NO_THRESHOLD_MASK  (~(0xff << 16)) /* Interrupt Threshold Control */
-
-int mxc_initialize_usb_hw(int port, unsigned int flags)
-{
-        unsigned int v;
-#if defined(CONFIG_SOC_IMX25)
-        if (cpu_is_mx25()) {
-                v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
-                                     USBCTRL_OTGBASE_OFFSET));
-
-                switch (port) {
-                case 0: /* OTG port */
-                        v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                        << MX35_OTG_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX35_OTG_PM_BIT;
-
-                        break;
-                case 1: /* H1 port */
-                        v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
-                                MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                                << MX35_H1_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX35_H1_PM_BIT;
-
-                        if (!(flags & MXC_EHCI_TTL_ENABLED))
-                                v |= MX35_H1_TLL_BIT;
-
-                        if (flags & MXC_EHCI_INTERNAL_PHY)
-                                v |= MX35_H1_USBTE_BIT;
-
-                        if (flags & MXC_EHCI_IPPUE_DOWN)
-                                v |= MX35_H1_IPPUE_DOWN_BIT;
-
-                        if (flags & MXC_EHCI_IPPUE_UP)
-                                v |= MX35_H1_IPPUE_UP_BIT;
-
-                        break;
-                default:
-                        return -EINVAL;
-                }
-
-                writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
-                                     USBCTRL_OTGBASE_OFFSET));
-                return 0;
-        }
-#endif /* if defined(CONFIG_SOC_IMX25) */
-#if defined(CONFIG_ARCH_MX3)
-        if (cpu_is_mx31()) {
-                v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
-                                     USBCTRL_OTGBASE_OFFSET));
-
-                switch (port) {
-                case 0: /* OTG port */
-                        v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                        << MX31_OTG_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX31_OTG_PM_BIT;
-
-                        break;
-                case 1: /* H1 port */
-                        v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                                << MX31_H1_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX31_H1_PM_BIT;
-
-                        if (!(flags & MXC_EHCI_TTL_ENABLED))
-                                v |= MX31_H1_DT_BIT;
-
-                        break;
-                case 2: /* H2 port */
-                        v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                                << MX31_H2_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX31_H2_PM_BIT;
-
-                        if (!(flags & MXC_EHCI_TTL_ENABLED))
-                                v |= MX31_H2_DT_BIT;
-
-                        break;
-                default:
-                        return -EINVAL;
-                }
-
-                writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
-                                     USBCTRL_OTGBASE_OFFSET));
-                return 0;
-        }
-
-        if (cpu_is_mx35()) {
-                v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
-                                     USBCTRL_OTGBASE_OFFSET));
-
-                switch (port) {
-                case 0: /* OTG port */
-                        v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                        << MX35_OTG_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX35_OTG_PM_BIT;
-
-                        break;
-                case 1: /* H1 port */
-                        v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
-                                MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                                << MX35_H1_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX35_H1_PM_BIT;
-
-                        if (!(flags & MXC_EHCI_TTL_ENABLED))
-                                v |= MX35_H1_TLL_BIT;
-
-                        if (flags & MXC_EHCI_INTERNAL_PHY)
-                                v |= MX35_H1_USBTE_BIT;
-
-                        if (flags & MXC_EHCI_IPPUE_DOWN)
-                                v |= MX35_H1_IPPUE_DOWN_BIT;
-
-                        if (flags & MXC_EHCI_IPPUE_UP)
-                                v |= MX35_H1_IPPUE_UP_BIT;
-
-                        break;
-                default:
-                        return -EINVAL;
-                }
-
-                writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
-                                     USBCTRL_OTGBASE_OFFSET));
-                return 0;
-        }
-#endif /* CONFIG_ARCH_MX3 */
-#ifdef CONFIG_MACH_MX27
-        if (cpu_is_mx27()) {
-                /* On i.MX27 we can use the i.MX31 USBCTRL bits, they
-                 * are identical
-                 */
-                v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
-                                     USBCTRL_OTGBASE_OFFSET));
-                switch (port) {
-                case 0: /* OTG port */
-                        v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                        << MX31_OTG_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX31_OTG_PM_BIT;
-                        break;
-                case 1: /* H1 port */
-                        v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                                << MX31_H1_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX31_H1_PM_BIT;
-
-                        if (!(flags & MXC_EHCI_TTL_ENABLED))
-                                v |= MX31_H1_DT_BIT;
-
-                        break;
-                case 2: /* H2 port */
-                        v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
-                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
-                                                << MX31_H2_SIC_SHIFT;
-                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                                v |= MX31_H2_PM_BIT;
-
-                        if (!(flags & MXC_EHCI_TTL_ENABLED))
-                                v |= MX31_H2_DT_BIT;
-
-                        break;
-                default:
-                        return -EINVAL;
-                }
-                writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
-                                     USBCTRL_OTGBASE_OFFSET));
-                return 0;
-        }
-#endif /* CONFIG_MACH_MX27 */
-#ifdef CONFIG_SOC_IMX51
-        if (cpu_is_mx51()) {
-                void __iomem *usb_base;
-                void __iomem *usbotg_base;
-                void __iomem *usbother_base;
-                int ret = 0;
-
-                usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
-                if (!usb_base) {
-                        printk(KERN_ERR "%s(): ioremap failed\n", __func__);
-                        return -ENOMEM;
-                }
-
-                switch (port) {
-                case 0: /* OTG port */
-                        usbotg_base = usb_base + MXC_OTG_OFFSET;
-                        break;
-                case 1: /* Host 1 port */
-                        usbotg_base = usb_base + MXC_H1_OFFSET;
-                        break;
-                case 2: /* Host 2 port */
-                        usbotg_base = usb_base + MXC_H2_OFFSET;
-                        break;
-                default:
-                        printk(KERN_ERR"%s no such port %d\n", __func__, port);
-                        ret = -ENOENT;
-                        goto error;
-                }
-                usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-
-                switch (port) {
-                case 0: /*OTG port */
-                        if (flags & MXC_EHCI_INTERNAL_PHY) {
-                                v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-
-                                if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
-                                        /* OC/USBPWR is not used */
-                                        v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
-                                } else {
-                                        /* OC/USBPWR is used */
-                                        v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
-                                }
-                                __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-
-                                v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
-                                if (flags & MXC_EHCI_WAKEUP_ENABLED)
-                                        v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
-                                else
-                                        v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
-                                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                                        v |= MXC_OTG_UCTRL_OPM_BIT;
-                                else
-                                        v &= ~MXC_OTG_UCTRL_OPM_BIT;
-                                __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
-                        }
-                        break;
-                case 1: /* Host 1 */
-                        /*Host ULPI */
-                        v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
-                        if (flags & MXC_EHCI_WAKEUP_ENABLED) {
-                                /* HOST1 wakeup/ULPI intr enable */
-                                v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
-                        } else {
-                                /* HOST1 wakeup/ULPI intr disable */
-                                v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
-                        }
-
-                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                                v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
-                        else
-                                v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
-                        __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
-
-                        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                                v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
-                        else
-                                v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
-                        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-
-                        v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
-                        if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
-                                /* Interrupt Threshold Control:Immediate (no threshold) */
-                                v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
-                        __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
-                        break;
-                case 2: /* Host 2 ULPI */
-                        v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
-                        if (flags & MXC_EHCI_WAKEUP_ENABLED) {
-                                /* HOST1 wakeup/ULPI intr enable */
-                                v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
-                        } else {
-                                /* HOST1 wakeup/ULPI intr disable */
-                                v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
-                        }
-
-                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                                v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
-                        else
-                                v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
-                        __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
-                        break;
-                }
-
-error:
-                iounmap(usb_base);
-                return ret;
-        }
-#endif
-        printk(KERN_WARNING
-                "%s() unable to setup USBCONTROL for this CPU\n", __func__);
-        return -EINVAL;
-}
-EXPORT_SYMBOL(mxc_initialize_usb_hw);
-
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index d17b3c996b84..57d59855f9ec 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -233,6 +233,7 @@ static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
 }
 
 static struct irq_chip gpio_irq_chip = {
+        .name = "GPIO",
         .irq_ack = gpio_ack_irq,
         .irq_mask = gpio_mask_irq,
         .irq_unmask = gpio_unmask_irq,
@@ -349,113 +350,3 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
 
         return 0;
 }
-
-#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
-        {                                                               \
-                .chip.label = "gpio-" #_id,                             \
-                .irq = _irq,                                            \
-                .irq_high = _irq_high,                                  \
-                .base = soc ## _IO_ADDRESS(                             \
-                                soc ## _GPIO ## _hwid ## _BASE_ADDR),   \
-                .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32,   \
-        }
-
-#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq)                 \
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
-#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid)                           \
-        DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
-
-#define DEFINE_REGISTER_FUNCTION(prefix)                                \
-int __init prefix ## _register_gpios(void)                              \
-{                                                                       \
-        return mxc_gpio_init(prefix ## _gpio_ports,                     \
-                        ARRAY_SIZE(prefix ## _gpio_ports));             \
-}
-
-#if defined(CONFIG_SOC_IMX1)
-static struct mxc_gpio_port imx1_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
-};
-
-DEFINE_REGISTER_FUNCTION(imx1)
-
-#endif /* if defined(CONFIG_SOC_IMX1) */
-
-#if defined(CONFIG_SOC_IMX21)
-static struct mxc_gpio_port imx21_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
-        DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
-        DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
-        DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
-        DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
-        DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
-};
-
-DEFINE_REGISTER_FUNCTION(imx21)
-
-#endif /* if defined(CONFIG_SOC_IMX21) */
-
-#if defined(CONFIG_SOC_IMX25)
-static struct mxc_gpio_port imx25_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
-};
-
-DEFINE_REGISTER_FUNCTION(imx25)
-
-#endif /* if defined(CONFIG_SOC_IMX25) */
-
-#if defined(CONFIG_SOC_IMX27)
-static struct mxc_gpio_port imx27_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
-        DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
-        DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
-        DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
-        DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
-        DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
-};
-
-DEFINE_REGISTER_FUNCTION(imx27)
-
-#endif /* if defined(CONFIG_SOC_IMX27) */
-
-#if defined(CONFIG_SOC_IMX31)
-static struct mxc_gpio_port imx31_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
-};
-
-DEFINE_REGISTER_FUNCTION(imx31)
-
-#endif /* if defined(CONFIG_SOC_IMX31) */
-
-#if defined(CONFIG_SOC_IMX35)
-static struct mxc_gpio_port imx35_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
-};
-
-DEFINE_REGISTER_FUNCTION(imx35)
-
-#endif /* if defined(CONFIG_SOC_IMX35) */
-
-#if defined(CONFIG_SOC_IMX50)
-static struct mxc_gpio_port imx50_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
-        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
-};
-
-DEFINE_REGISTER_FUNCTION(imx50)
-
-#endif /* if defined(CONFIG_SOC_IMX50) */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index aea2cd3b6d15..a22ebe11a602 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -24,6 +24,16 @@ extern void mx50_map_io(void);
 extern void mx51_map_io(void);
 extern void mx53_map_io(void);
 extern void mxc91231_map_io(void);
+extern void imx1_init_early(void);
+extern void imx21_init_early(void);
+extern void imx25_init_early(void);
+extern void imx27_init_early(void);
+extern void imx31_init_early(void);
+extern void imx35_init_early(void);
+extern void imx50_init_early(void);
+extern void imx51_init_early(void);
+extern void imx53_init_early(void);
+extern void mxc91231_init_early(void);
 extern void mxc_init_irq(void __iomem *);
 extern void tzic_init_irq(void __iomem *);
 extern void mx1_init_irq(void);
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index 0044e2f1bea8..a2747f12813e 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -46,6 +46,21 @@ struct mxc_gpio_port {
         spinlock_t lock;
 };
 
+#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
+        {                                                               \
+                .chip.label = "gpio-" #_id,                             \
+                .irq = _irq,                                            \
+                .irq_high = _irq_high,                                  \
+                .base = soc ## _IO_ADDRESS(                             \
+                                soc ## _GPIO ## _hwid ## _BASE_ADDR),   \
+                .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32,   \
+        }
+
+#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq)                 \
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
+#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid)                           \
+        DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
+
 int mxc_gpio_init(struct mxc_gpio_port*, int);
 
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index cbaed295a2bf..c92f0b1f216f 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -112,12 +112,12 @@ enum iomux_gp_func {
  *      - setups the iomux according to the configuration
  *      - if the pin is configured as a GPIO, we claim it through kernel gpiolib
  */
-int mxc_iomux_alloc_pin(const unsigned int pin, const char *label);
+int mxc_iomux_alloc_pin(unsigned int pin, const char *label);
 /*
  * setups mutliple pins
  * convenient way to call the above function with tables
  */
-int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
                 const char *label);
 
 /*
@@ -126,12 +126,12 @@ int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
  *      - frees the GPIO if the pin was configured as GPIO
  *      - DOES NOT reconfigure the IOMUX in its reset state
  */
-void mxc_iomux_release_pin(const unsigned int pin);
+void mxc_iomux_release_pin(unsigned int pin);
 /*
  * releases multiple pins
  * convenvient way to call the above function with tables
  */
-void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count);
+void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count);
 
 /*
  * This function enables/disables the general purpose function for a particular
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
index 2a24bae1b878..3117c18bbbd9 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx35.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
@@ -989,13 +989,13 @@
 #define MX35_PAD_ATA_DATA2__IPU_DIAGB_9                         IOMUX_PAD(0x6e8, 0x284, 6, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28                 IOMUX_PAD(0x6e8, 0x284, 7, 0x0,   0, NO_PAD_CTRL)
 
-#define MX35_PAD_ATA_DATA3__ATA_DATA_3                          IOMUX_PAD(0x6e8, 0x288, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__ESDHC3_CLK                          IOMUX_PAD(0x6e8, 0x288, 1, 0x814, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5               IOMUX_PAD(0x6e8, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__CSPI2_SCLK                          IOMUX_PAD(0x6e8, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__GPIO2_16                            IOMUX_PAD(0x6e8, 0x288, 5, 0x884, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10                        IOMUX_PAD(0x6e8, 0x288, 6, 0x0,   0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29                 IOMUX_PAD(0x6e8, 0x288, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__ATA_DATA_3                          IOMUX_PAD(0x6ec, 0x288, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__ESDHC3_CLK                          IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5               IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__CSPI2_SCLK                          IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__GPIO2_16                            IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10                        IOMUX_PAD(0x6ec, 0x288, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29                 IOMUX_PAD(0x6ec, 0x288, 7, 0x0,   0, NO_PAD_CTRL)
 
 #define MX35_PAD_ATA_DATA4__ATA_DATA_4                          IOMUX_PAD(0x6f0, 0x28c, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_ATA_DATA4__ESDHC3_CMD                          IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/plat-mxc/include/mach/iomux-mx50.h
index 058a922ca147..98e7fd0b9083 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx50.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx50.h
@@ -86,7 +86,7 @@
 #define MX50_PAD_I2C1_SCL__I2C1_SCL     IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \
                                                         MX50_I2C_PAD_CTRL)
 #define MX50_PAD_I2C1_SCL__GPIO_6_18    IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C1_SCL__UART2_TXD    IOMUX_PAD(0x2EC, 0x40, 2, 0x7cc, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_I2C1_SCL__UART2_TXD    IOMUX_PAD(0x2EC, 0x40, 2, 0x0, 0, MX50_UART_PAD_CTRL)
 
 #define MX50_PAD_I2C1_SDA__I2C1_SDA     IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \
                                                         MX50_I2C_PAD_CTRL)
@@ -96,7 +96,7 @@
 #define MX50_PAD_I2C2_SCL__I2C2_SCL     IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \
                                                         MX50_I2C_PAD_CTRL)
 #define MX50_PAD_I2C2_SCL__GPIO_6_20    IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_I2C2_SCL__UART2_CTS    IOMUX_PAD(0x2F4, 0x48, 2, 0x7c8, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_I2C2_SCL__UART2_CTS    IOMUX_PAD(0x2F4, 0x48, 2, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_I2C2_SCL__DCDC_OK      IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL)
 
 #define MX50_PAD_I2C2_SDA__I2C2_SDA     IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \
@@ -172,7 +172,7 @@
 
 #define MX50_PAD_SSI_RXFS__AUD3_RXFS    IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_SSI_RXFS__GPIO_6_4     IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_SSI_RXFS__UART5_TXD    IOMUX_PAD(0x328, 0x7C, 2, 0x7e4, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_SSI_RXFS__UART5_TXD    IOMUX_PAD(0x328, 0x7C, 2, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_SSI_RXFS__WEIM_D6      IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL)
 #define MX50_PAD_SSI_RXFS__CSPI_SS2     IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD)
 #define MX50_PAD_SSI_RXFS__FEC_COL      IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH)
@@ -186,25 +186,25 @@
 #define MX50_PAD_SSI_RXC__FEC_RX_CLK    IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL)
 #define MX50_PAD_SSI_RXC__FEC_MDIO      IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL)
 
-#define MX50_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x330, 0x84, 0, 0x7c4, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x330, 0x84, 0, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART1_TXD__GPIO_6_6    IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL)
 
 #define MX50_PAD_UART1_RXD__UART1_RXD   IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART1_RXD__GPIO_6_7    IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL)
 
-#define MX50_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x338, 0x8C, 0, 0x7c0, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x338, 0x8C, 0, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART1_CTS__GPIO_6_8    IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART1_CTS__UART5_TXD   IOMUX_PAD(0x338, 0x8C, 2, 0x7e4, 2, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART1_CTS__UART5_TXD   IOMUX_PAD(0x338, 0x8C, 2, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART1_CTS__SD4_D4      IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART1_CTS__SD4_CMD     IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL)
 
 #define MX50_PAD_UART1_RTS__UART1_RTS   IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART1_RTS__GPIO_6_9    IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_UART1_RTS__UART5_RXD   IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__SD4_D5      IOMUX_PAD(0x33C, 0x90, 4, 0x0, 1, MX50_SD_PAD_CTRL)
-#define MX50_PAD_UART1_RTS__SD4_CLK     IOMUX_PAD(0x33C, 0x90, 5, 0x0, 1, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART1_RTS__SD4_D5      IOMUX_PAD(0x33C, 0x90, 4, 0x764, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART1_RTS__SD4_CLK     IOMUX_PAD(0x33C, 0x90, 5, 0x748, 0, MX50_SD_PAD_CTRL)
 
-#define MX50_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x340, 0x94, 0, 0x7cc, 2, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x340, 0x94, 0, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART2_TXD__GPIO_6_10   IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_UART2_TXD__SD4_D6      IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART2_TXD__SD4_D4      IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL)
@@ -214,7 +214,7 @@
 #define MX50_PAD_UART2_RXD__SD4_D7      IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART2_RXD__SD4_D5      IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL)
 
-#define MX50_PAD_UART2_CTS__UART2_CTS   IOMUX_PAD(0x348, 0x9C, 0, 0x7c8, 2, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART2_CTS__UART2_CTS   IOMUX_PAD(0x348, 0x9C, 0, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART2_CTS__GPIO_6_12   IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_UART2_CTS__SD4_CMD     IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART2_CTS__SD4_D6      IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL)
@@ -224,7 +224,7 @@
 #define MX50_PAD_UART2_RTS__SD4_CLK     IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART2_RTS__SD4_D7      IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL)
 
-#define MX50_PAD_UART3_TXD__UART3_TXD   IOMUX_PAD(0x350, 0xA4, 0, 0x7d4, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART3_TXD__UART3_TXD   IOMUX_PAD(0x350, 0xA4, 0, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART3_TXD__GPIO_6_14   IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_UART3_TXD__SD1_D4      IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART3_TXD__SD4_D0      IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL)
@@ -238,9 +238,9 @@
 #define MX50_PAD_UART3_RXD__SD2_CD      IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART3_RXD__WEIM_D13    IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL)
 
-#define MX50_PAD_UART4_TXD__UART4_TXD   IOMUX_PAD(0x358, 0xAC, 0, 0x7dc, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART4_TXD__UART4_TXD   IOMUX_PAD(0x358, 0xAC, 0, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART4_TXD__GPIO_6_16   IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_UART4_TXD__UART3_CTS   IOMUX_PAD(0x358, 0xAC, 2, 0x7d0, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART4_TXD__UART3_CTS   IOMUX_PAD(0x358, 0xAC, 2, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_UART4_TXD__SD1_D6      IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART4_TXD__SD4_D2      IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL)
 #define MX50_PAD_UART4_TXD__SD2_LCTL    IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL)
@@ -278,7 +278,7 @@
 #define MX50_PAD_ECSPI1_MOSI__GPIO_4_13         IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI1_MOSI__CSPI_SS1          IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD)
 #define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1        IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_MOSI__UART3_CTS         IOMUX_PAD(0x374, 0xC8, 4, 0x7d0, 3, MX50_UART_PAD_CTRL)
+#define MX50_PAD_ECSPI1_MOSI__UART3_CTS         IOMUX_PAD(0x374, 0xC8, 4, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7        IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI1_MOSI__WEIM_D9           IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL)
 
@@ -294,7 +294,7 @@
 #define MX50_PAD_ECSPI1_SS0__GPIO_4_15          IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
 #define MX50_PAD_ECSPI1_SS0__CSPI_SS3           IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD)
 #define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3         IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI1_SS0__UART4_CTS          IOMUX_PAD(0x37C, 0xD0, 4, 0x7d8, 1, MX50_UART_PAD_CTRL)
+#define MX50_PAD_ECSPI1_SS0__UART4_CTS          IOMUX_PAD(0x37C, 0xD0, 4, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9         IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI1_SS0__WEIM_D11           IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL)
 
@@ -311,17 +311,17 @@
 #define MX50_PAD_ECSPI2_MOSI__GPIO_4_17         IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD         IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1        IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI2_MOSI__UART5_CTS         IOMUX_PAD(0x384, 0xD8, 4, 0x7e0, 1, MX50_UART_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MOSI__UART5_CTS         IOMUX_PAD(0x384, 0xD8, 4, 0x0, 0, MX50_UART_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN         IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5        IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MOSI__WEIM_D9           IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL)
 
-#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO       IOMUX_PAD(0x388, 0xDC, 0, 0x73c, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO       IOMUX_PAD(0x388, 0xDC, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MISO__GPIO_4_18         IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
 #define MX50_PAD_ECSPI2_MISO__ELCDIF_RS         IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2        IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
-#define MX50_PAD_ECSPI2_MISO__UART5_TXD         IOMUX_PAD(0x388, 0xDC, 4, 0x7e4, 4, MX50_UART_PAD_CTRL)
-#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC      IOMUX_PAD(0x388, 0xDC, 5, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MISO__UART5_TXD         IOMUX_PAD(0x388, 0xDC, 4, 0x0, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC      IOMUX_PAD(0x388, 0xDC, 5, 0x73c, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MISO__NANDF_CEN6        IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_ECSPI2_MISO__WEIM_D10          IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL)
 
@@ -503,7 +503,7 @@
 #define MX50_PAD_DISP_RD__ELCDIF_EN     IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
 #define MX50_PAD_DISP_RD__WEIM_A25      IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
 
-#define MX50_PAD_DISP_RS__ELCDIF_RS     IOMUX_PAD(0x434, 0x154, 0, 0x73c, 1, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_RS__ELCDIF_RS     IOMUX_PAD(0x434, 0x154, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
 #define MX50_PAD_DISP_RS__GPIO_2_17     IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_DISP_RS__ELCDIF_VSYNC  IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL)
 #define MX50_PAD_DISP_RS__WEIM_A26      IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
@@ -691,8 +691,8 @@
 
 #define MX50_PAD_EPDC_D9__EPDC_D9       IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_EPDC_D9__GPIO_3_9      IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__WEIM_D9       IOMUX_PAD(0x570, 0x1D4, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX50_PAD_EPDC_D9__ELCDIF_D25    IOMUX_PAD(0x570, 0x1D4, 3, 0x810, 2, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_D9__WEIM_D9       IOMUX_PAD(0x570, 0x1D4, 2, 0x810, 2, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D9__ELCDIF_D25    IOMUX_PAD(0x570, 0x1D4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
 
 #define MX50_PAD_EPDC_D10__EPDC_D10     IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX50_PAD_EPDC_D10__GPIO_3_10    IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index b6767f90ef14..df6acc066fb1 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -473,7 +473,7 @@
 #define _MX51_PAD_UART2_RXD__UART2_RXD          IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0)
 #define _MX51_PAD_UART2_TXD__FIRI_RXD           IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0)
 #define _MX51_PAD_UART2_TXD__GPIO1_21           IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0)
-#define _MX51_PAD_UART2_TXD__UART2_TXD          IOMUX_PAD(0x62c, 0x23c, 0, 0x09ec, 3, 0)
+#define _MX51_PAD_UART2_TXD__UART2_TXD          IOMUX_PAD(0x62c, 0x23c, 0, 0x0000, 0, 0)
 #define _MX51_PAD_UART3_RXD__CSI1_D0            IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0)
 #define _MX51_PAD_UART3_RXD__GPIO1_22           IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0)
 #define _MX51_PAD_UART3_RXD__UART1_DTR          IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0)
@@ -528,7 +528,7 @@
 #define _MX51_PAD_USBH1_DATA1__UART2_RXD        IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0)
 #define _MX51_PAD_USBH1_DATA1__USBH1_DATA1      IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0)
 #define _MX51_PAD_USBH1_DATA2__GPIO1_13         IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0)
-#define _MX51_PAD_USBH1_DATA2__UART2_TXD        IOMUX_PAD(0x690, 0x290, 1, 0x09ec, 5, 0)
+#define _MX51_PAD_USBH1_DATA2__UART2_TXD        IOMUX_PAD(0x690, 0x290, 1, 0x0000, 0, 0)
 #define _MX51_PAD_USBH1_DATA2__USBH1_DATA2      IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0)
 #define _MX51_PAD_USBH1_DATA3__GPIO1_14         IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0)
 #define _MX51_PAD_USBH1_DATA3__UART2_RTS        IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0)
@@ -985,11 +985,11 @@
 #define MX51_PAD_NANDF_WE_B__GPIO3_3            (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_WE_B__NANDF_WE_B         (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_WE_B__PATA_DIOW          (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_WE_B__SD3_DATA0          (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_WE_B__SD3_DATA0          (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_RE_B__GPIO3_4            (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_RE_B__NANDF_RE_B         (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_RE_B__PATA_DIOR          (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RE_B__SD3_DATA1          (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RE_B__SD3_DATA1          (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_ALE__GPIO3_5             (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_ALE__NANDF_ALE           (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN      (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -999,18 +999,18 @@
 #define MX51_PAD_NANDF_WP_B__GPIO3_7            (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_WP_B__NANDF_WP_B         (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_WP_B__PATA_DMACK         (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_WP_B__SD3_DATA2          (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_WP_B__SD3_DATA2          (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_RB0__ECSPI2_SS1          (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_NANDF_RB0__GPIO3_8             (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_RB0__NANDF_RB0           (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_RB0__PATA_DMARQ          (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB0__SD3_DATA3           (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB0__SD3_DATA3           (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_RB1__CSPI_MOSI           (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_NANDF_RB1__ECSPI2_RDY          (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_NANDF_RB1__GPIO3_9             (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_RB1__NANDF_RB1           (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_RB1__PATA_IORDY          (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RB1__SD4_CMD             (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB1__SD4_CMD             (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_RB2__DISP2_WAIT          (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_NANDF_RB2__FEC_COL             (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
@@ -1036,41 +1036,41 @@
 #define MX51_PAD_NANDF_CS2__GPIO3_18            (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS2__NANDF_CS2           (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS2__PATA_CS_0           (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS2__SD4_CLK             (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS2__SD4_CLK             (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
 #define MX51_PAD_NANDF_CS2__USBH3_H1_DP         (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS3__FEC_MDC             (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
 #define MX51_PAD_NANDF_CS3__GPIO3_19            (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS3__NANDF_CS3           (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS3__PATA_CS_1           (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS3__SD4_DAT0            (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS3__SD4_DAT0            (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_CS3__USBH3_H1_DM         (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS4__FEC_TDATA1          (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
 #define MX51_PAD_NANDF_CS4__GPIO3_20            (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS4__NANDF_CS4           (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS4__PATA_DA_0           (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS4__SD4_DAT1            (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS4__SD4_DAT1            (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_CS4__USBH3_STP           (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS5__FEC_TDATA2          (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
 #define MX51_PAD_NANDF_CS5__GPIO3_21            (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS5__NANDF_CS5           (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS5__PATA_DA_1           (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS5__SD4_DAT2            (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS5__SD4_DAT2            (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_CS5__USBH3_DIR           (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS6__CSPI_SS3            (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_NANDF_CS6__FEC_TDATA3          (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
 #define MX51_PAD_NANDF_CS6__GPIO3_22            (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS6__NANDF_CS6           (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS6__PATA_DA_2           (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS6__SD4_DAT3            (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS6__SD4_DAT3            (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_CS7__FEC_TX_EN           (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
 #define MX51_PAD_NANDF_CS7__GPIO3_23            (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_CS7__NANDF_CS7           (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_CS7__SD3_CLK             (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS7__SD3_CLK             (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
 #define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0      (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
 #define MX51_PAD_NANDF_RDY_INT__GPIO3_24        (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT   (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_NANDF_RDY_INT__SD3_CMD         (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RDY_INT__SD3_CMD         (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_NANDF_D15__ECSPI2_MOSI         (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_NANDF_D15__GPIO3_25            (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
 #define MX51_PAD_NANDF_D15__NANDF_D15           (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1479,26 +1479,26 @@
 #define MX51_PAD_SD1_CLK__SD1_CLK               (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
 #define MX51_PAD_SD1_DATA0__AUD5_TXD            (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_SD1_DATA0__CSPI_MISO           (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_SD1_DATA0__SD1_DATA0           (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA0__SD1_DATA0           (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_EIM_DA0__EIM_DA0               (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA1__EIM_DA1               (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA2__EIM_DA2               (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA3__EIM_DA3               (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_SD1_DATA1__AUD5_RXD            (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD1_DATA1__SD1_DATA1           (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA1__SD1_DATA1           (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_EIM_DA4__EIM_DA4               (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA5__EIM_DA5               (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA6__EIM_DA6               (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA7__EIM_DA7               (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_SD1_DATA2__AUD5_TXC            (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD1_DATA2__SD1_DATA2           (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA2__SD1_DATA2           (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_EIM_DA10__EIM_DA10             (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA11__EIM_DA11             (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA8__EIM_DA8               (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_EIM_DA9__EIM_DA9               (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_SD1_DATA3__AUD5_TXFS           (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_SD1_DATA3__CSPI_SS1            (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
-#define MX51_PAD_SD1_DATA3__SD1_DATA3           (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA3__SD1_DATA3           (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_GPIO1_0__CSPI_SS2              (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_GPIO1_0__GPIO1_0               (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_GPIO1_0__SD1_CD                (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
@@ -1517,16 +1517,16 @@
 #define MX51_PAD_SD2_CLK__SD2_CLK               (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
 #define MX51_PAD_SD2_DATA0__CSPI_MISO           (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_SD2_DATA0__SD1_DAT4            (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD2_DATA0__SD2_DATA0           (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA0__SD2_DATA0           (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_SD2_DATA1__SD1_DAT5            (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD2_DATA1__SD2_DATA1           (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA1__SD2_DATA1           (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_SD2_DATA1__USBH3_H2_DP         (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_SD2_DATA2__SD1_DAT6            (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD2_DATA2__SD2_DATA2           (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA2__SD2_DATA2           (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_SD2_DATA2__USBH3_H2_DM         (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_SD2_DATA3__CSPI_SS2            (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
 #define MX51_PAD_SD2_DATA3__SD1_DAT7            (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX51_PAD_SD2_DATA3__SD2_DATA3           (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA3__SD2_DATA3           (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
 #define MX51_PAD_GPIO1_2__CCM_OUT_2             (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_GPIO1_2__GPIO1_2               (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define MX51_PAD_GPIO1_2__I2C2_SCL              (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
index 68e11d7ab79d..e95d9cb8aeb7 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,305 +21,2358 @@
 
 #include <mach/iomux-v3.h>
 
-/*
- * various IOMUX alternate output functions (1-7)
- */
-typedef enum iomux_config {
-        IOMUX_CONFIG_ALT0,
-        IOMUX_CONFIG_ALT1,
-        IOMUX_CONFIG_ALT2,
-        IOMUX_CONFIG_ALT3,
-        IOMUX_CONFIG_ALT4,
-        IOMUX_CONFIG_ALT5,
-        IOMUX_CONFIG_ALT6,
-        IOMUX_CONFIG_ALT7,
-        IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
-} iomux_pin_cfg_t;
-
 /* These 2 defines are for pins that may not have a mux register, but could
  * have a pad setting register, and vice-versa. */
-#define NON_MUX_I       0x00
 #define NON_PAD_I       0x00
 
 #define MX53_UART_PAD_CTRL              (PAD_CTL_PKE | PAD_CTL_PUE |    \
                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-/* UART1 */
-#define MX53_PAD_CSI0_D10__UART1_TXD    IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_D11__UART1_RXD    IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_ATA_DIOW__UART1_TXD    IOMUX_PAD(0x5F0, 0x270, 3, 0x0, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_ATA_DMACK__UART1_RXD   IOMUX_PAD(0x5F4, 0x274, 3, 0x880, 3, MX53_UART_PAD_CTRL)
-
-/* UART2 */
-#define MX53_PAD_ATA_BUFFER_EN__UART2_RXD       IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_ATA_DMARQ__UART2_TXD   IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_ATA_DIOR__UART2_RTS    IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_ATA_INTRQ__UART2_CTS   IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, MX53_UART_PAD_CTRL)
+#define MX53_SDHC_PAD_CTRL      (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+                                PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
+                                PAD_CTL_SRE_FAST)
 
-/* UART3 */
-#define MX53_PAD_ATA_CS_0__UART3_TXD    IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_ATA_CS_1__UART3_RXD    IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_ATA_DA_1__UART3_CTS    IOMUX_PAD(0x614, 0x294, 4, 0x0, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_ATA_DA_2__UART3_RTS    IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL)
+#define _MX53_PAD_GPIO_19__KPP_COL_5            IOMUX_PAD(0x348, 0x20, 0, 0x840, 0, 0)
+#define _MX53_PAD_GPIO_19__GPIO4_5              IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_19__CCM_CLKO             IOMUX_PAD(0x348, 0x20, 2, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_19__SPDIF_OUT1   IOMUX_PAD(0x348, 0x20, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x20, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_19__ECSPI1_RDY   IOMUX_PAD(0x348, 0x20, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_19__FEC_TDATA_3  IOMUX_PAD(0x348, 0x20, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x20,7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL0__KPP_COL_0   IOMUX_PAD(0x34C, 0x24, o, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL0__GPIO4_6             IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC     IOMUX_PAD(0x34C, 0x24, 2, 0x758, 0, 0)
+#define _MX53_PAD_KEY_COL0__UART4_TXD_MUX       IOMUX_PAD(0x34C, 0x24, 4, 0x890, 0, 0)
+#define _MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x24, 5, 0x79C, 0, 0)
+#define _MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x24, 6, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL0__SRC_ANY_PU_RST      IOMUX_PAD(0x34C, 0x24, 7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW0__KPP_ROW_0   IOMUX_PAD(0x350, 0x28, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW0__GPIO4_7             IOMUX_PAD(0x350, 0x28, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD     IOMUX_PAD(0x350, 0x28, 2, 0x74C, 0, 0)
+#define _MX53_PAD_KEY_ROW0__UART4_RXD_MUX       IOMUX_PAD(0x350, 0x28, 4, 0x890, 1, 0)
+#define _MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x28, 5, 0x7A4, 0, 0)
+#define _MX53_PAD_KEY_ROW0__FEC_TX_ER   IOMUX_PAD(0x350, 0x28, 6, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL1__KPP_COL_1   IOMUX_PAD(0x354, 0x2C, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL1__GPIO4_8             IOMUX_PAD(0x354, 0x2C, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS    IOMUX_PAD(0x354, 0x2C, 2, 0x75C, 0, 0)
+#define _MX53_PAD_KEY_COL1__UART5_TXD_MUX       IOMUX_PAD(0x354, 0x2C, 4, 0x898, 0, 0)
+#define _MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x2C, 5, 0x7A0, 0, 0)
+#define _MX53_PAD_KEY_COL1__FEC_RX_CLK  IOMUX_PAD(0x354, 0x2C, 6, 0x808, 0, 0)
+#define _MX53_PAD_KEY_COL1__USBPHY1_TXREADY     IOMUX_PAD(0x354, 0x2C, 7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW1__KPP_ROW_1   IOMUX_PAD(0x358, 0x30, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW1__GPIO4_9             IOMUX_PAD(0x358, 0x30, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD     IOMUX_PAD(0x358, 0x30, 2, 0x748, 0, 0)
+#define _MX53_PAD_KEY_ROW1__UART5_RXD_MUX       IOMUX_PAD(0x358, 0x30, 4, 0x898, 1, 0)
+#define _MX53_PAD_KEY_ROW1__ECSPI1_SS0  IOMUX_PAD(0x358, 0x30, 5, 0x7A8, 0, 0)
+#define _MX53_PAD_KEY_ROW1__FEC_COL             IOMUX_PAD(0x358, 0x30, 6, 0x800, 0, 0)
+#define _MX53_PAD_KEY_ROW1__USBPHY1_RXVALID     IOMUX_PAD(0x358, 0x30, 7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL2__KPP_COL_2   IOMUX_PAD(0x35C, 0x34, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL2__GPIO4_10            IOMUX_PAD(0x35C, 0x34, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL2__CAN1_TXCAN  IOMUX_PAD(0x35C, 0x34, 2, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL2__FEC_MDIO            IOMUX_PAD(0x35C, 0x34, 4, 0x804, 0, 0)
+#define _MX53_PAD_KEY_COL2__ECSPI1_SS1  IOMUX_PAD(0x35C, 0x34, 5, 0x7AC, 0, 0)
+#define _MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x34, 6, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE    IOMUX_PAD(0x35C, 0x34, 7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW2__KPP_ROW_2   IOMUX_PAD(0x360, 0x38, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW2__GPIO4_11    IOMUX_PAD(0x360, 0x38, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW2__CAN1_RXCAN  IOMUX_PAD(0x360, 0x38, 2, 0x760, 0, 0)
+#define _MX53_PAD_KEY_ROW2__FEC_MDC             IOMUX_PAD(0x360, 0x38, 4, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW2__ECSPI1_SS2  IOMUX_PAD(0x360, 0x38, 5, 0x7B0, 0, 0)
+#define _MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x38, 6, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW2__USBPHY1_RXERROR     IOMUX_PAD(0x360, 0x38, 7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL3__KPP_COL_3   IOMUX_PAD(0x364, 0x3C, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL3__GPIO4_12            IOMUX_PAD(0x364, 0x3C, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL3__USBOH3_H2_DP        IOMUX_PAD(0x364, 0x3C, 2, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL3__SPDIF_IN1   IOMUX_PAD(0x364, 0x3C, 3, 0x870, 0, 0)
+#define _MX53_PAD_KEY_COL3__I2C2_SCL            IOMUX_PAD(0x364, 0x3C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, 0)
+#define _MX53_PAD_KEY_COL3__ECSPI1_SS3  IOMUX_PAD(0x364, 0x3C, 5, 0x7B4, 0, 0)
+#define _MX53_PAD_KEY_COL3__FEC_CRS             IOMUX_PAD(0x364, 0x3C, 6, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK    IOMUX_PAD(0x364, 0x3C, 7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW3__KPP_ROW_3   IOMUX_PAD(0x368, 0x40, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW3__GPIO4_13    IOMUX_PAD(0x368, 0x40, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW3__USBOH3_H2_DM        IOMUX_PAD(0x368, 0x40, 2, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK    IOMUX_PAD(0x368, 0x40, 3, 0x768, 0, 0)
+#define _MX53_PAD_KEY_ROW3__I2C2_SDA    IOMUX_PAD(0x368, 0x40, 4 | IOMUX_CONFIG_SION, 0x820, 0, 0)
+#define _MX53_PAD_KEY_ROW3__OSC32K_32K_OUT      IOMUX_PAD(0x368, 0x40, 5, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW3__CCM_PLL4_BYP        IOMUX_PAD(0x368, 0x40, 6, 0x77C, 0, 0)
+#define _MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x40, 7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL4__KPP_COL_4   IOMUX_PAD(0x36C, 0x44, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL4__GPIO4_14            IOMUX_PAD(0x36C, 0x44, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL4__CAN2_TXCAN  IOMUX_PAD(0x36C, 0x44, 2, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL4__IPU_SISG_4  IOMUX_PAD(0x36C, 0x44, 3, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL4__UART5_RTS   IOMUX_PAD(0x36C, 0x44, 4, 0x894, 0, 0)
+#define _MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC    IOMUX_PAD(0x36C, 0x44, 5, 0x89C, 0, 0)
+#define _MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x44, 7, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW4__KPP_ROW_4   IOMUX_PAD(0x370, 0x48, 0, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW4__GPIO4_15    IOMUX_PAD(0x370, 0x48, 1, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW4__CAN2_RXCAN  IOMUX_PAD(0x370, 0x48, 2, 0x764, 0, 0)
+#define _MX53_PAD_KEY_ROW4__IPU_SISG_5  IOMUX_PAD(0x370, 0x48, 3, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW4__UART5_CTS   IOMUX_PAD(0x370, 0x48, 4, 0x894, 1, 0)
+#define _MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR   IOMUX_PAD(0x370, 0x48, 5, 0x0, 0, 0)
+#define _MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID   IOMUX_PAD(0x370, 0x48, 7, 0x0, 0, 0)
+#define _MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK        IOMUX_PAD(0x378, 0x4C, 0, 0x0, 0, 0)
+#define _MX53_PAD_DI0_DISP_CLK__GPIO4_16                IOMUX_PAD(0x378, 0x4C, 1, 0x0, 0, 0)
+#define _MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR        IOMUX_PAD(0x378, 0x4C, 2, 0x0, 0, 0)
+#define _MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x4C, 5, 0x0, 0, 0)
+#define _MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x4C, 6, 0x0, 0, 0)
+#define _MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID  IOMUX_PAD(0x378, 0x4C, 7, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN15__IPU_DI0_PIN15              IOMUX_PAD(0x37C, 0x50, 0, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN15__GPIO4_17           IOMUX_PAD(0x37C, 0x50, 1, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC    IOMUX_PAD(0x37C, 0x50, 2, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1    IOMUX_PAD(0x37C, 0x50, 5, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1    IOMUX_PAD(0x37C, 0x50, 6, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN15__USBPHY1_BVALID             IOMUX_PAD(0x37C, 0x50, 7, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN2__IPU_DI0_PIN2                IOMUX_PAD(0x380, 0x54, 0, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN2__GPIO4_18                    IOMUX_PAD(0x380, 0x54, 1, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD     IOMUX_PAD(0x380, 0x54, 2, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2     IOMUX_PAD(0x380, 0x54, 5, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2             IOMUX_PAD(0x380, 0x54, 6, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION  IOMUX_PAD(0x380, 0x54, 7, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                IOMUX_PAD(0x384, 0x58, 0, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN3__GPIO4_19                    IOMUX_PAD(0x384, 0x58, 1, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS    IOMUX_PAD(0x384, 0x58, 2, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3     IOMUX_PAD(0x384, 0x58, 5, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3             IOMUX_PAD(0x384, 0x58, 6, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN3__USBPHY1_IDDIG               IOMUX_PAD(0x384, 0x58, 7, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN4__IPU_DI0_PIN4                IOMUX_PAD(0x388, 0x5C, 0, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN4__GPIO4_20                    IOMUX_PAD(0x388, 0x5C, 1, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD     IOMUX_PAD(0x388, 0x5C, 2, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN4__ESDHC1_WP           IOMUX_PAD(0x388, 0x5C, 3, 0x7FC, 0, 0)
+#define _MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD    IOMUX_PAD(0x388, 0x5C, 5, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4             IOMUX_PAD(0x388, 0x5C, 6, 0x0, 0, 0)
+#define _MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT      IOMUX_PAD(0x388, 0x5C, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0   IOMUX_PAD(0x38C, 0x60, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT0__GPIO4_21          IOMUX_PAD(0x38C, 0x60, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT0__CSPI_SCLK         IOMUX_PAD(0x38C, 0x60, 2, 0x780, 0, 0)
+#define _MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0       IOMUX_PAD(0x38C, 0x60, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN       IOMUX_PAD(0x38C, 0x60, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5   IOMUX_PAD(0x38C, 0x60, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY   IOMUX_PAD(0x38C, 0x60, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1   IOMUX_PAD(0x390, 0x64, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT1__GPIO4_22          IOMUX_PAD(0x390, 0x64, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT1__CSPI_MOSI         IOMUX_PAD(0x390, 0x64, 2, 0x788, 0, 0)
+#define _MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1       IOMUX_PAD(0x390, 0x64, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL      IOMUX_PAD(0x390, 0x64, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6   IOMUX_PAD(0x390, 0x64, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID   IOMUX_PAD(0x390, 0x64, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2   IOMUX_PAD(0x394, 0x68, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT2__GPIO4_23          IOMUX_PAD(0x394, 0x68, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT2__CSPI_MISO         IOMUX_PAD(0x394, 0x68, 2, 0x784, 0, 0)
+#define _MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2       IOMUX_PAD(0x394, 0x68, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE   IOMUX_PAD(0x394, 0x68, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7   IOMUX_PAD(0x394, 0x68, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE  IOMUX_PAD(0x394, 0x68, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3   IOMUX_PAD(0x398, 0x6C, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT3__GPIO4_24          IOMUX_PAD(0x398, 0x6C, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT3__CSPI_SS0          IOMUX_PAD(0x398, 0x6C, 2, 0x78C, 0, 0)
+#define _MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3       IOMUX_PAD(0x398, 0x6C, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR      IOMUX_PAD(0x398, 0x6C, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8   IOMUX_PAD(0x398, 0x6C, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR   IOMUX_PAD(0x398, 0x6C, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4   IOMUX_PAD(0x39C, 0x70, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT4__GPIO4_25          IOMUX_PAD(0x39C, 0x70, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT4__CSPI_SS1          IOMUX_PAD(0x39C, 0x70, 2, 0x790, 0, 0)
+#define _MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4       IOMUX_PAD(0x39C, 0x70, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB        IOMUX_PAD(0x39C, 0x70, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9   IOMUX_PAD(0x39C, 0x70, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK  IOMUX_PAD(0x39C, 0x70, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5   IOMUX_PAD(0x3A0, 0x74, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT5__GPIO4_26          IOMUX_PAD(0x3A0, 0x74, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT5__CSPI_SS2          IOMUX_PAD(0x3A0, 0x74, 2, 0x794, 0, 0)
+#define _MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5       IOMUX_PAD(0x3A0, 0x74, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS  IOMUX_PAD(0x3A0, 0x74, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10  IOMUX_PAD(0x3A0, 0x74, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0       IOMUX_PAD(0x3A0, 0x74, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6   IOMUX_PAD(0x3A4, 0x78, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT6__GPIO4_27          IOMUX_PAD(0x3A4, 0x78, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT6__CSPI_SS3          IOMUX_PAD(0x3A4, 0x78, 2, 0x798, 0, 0)
+#define _MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6       IOMUX_PAD(0x3A4, 0x78, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x78, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11  IOMUX_PAD(0x3A4, 0x78, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1       IOMUX_PAD(0x3A4, 0x78, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7   IOMUX_PAD(0x3A8, 0x7C, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT7__GPIO4_28          IOMUX_PAD(0x3A8, 0x7C, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT7__CSPI_RDY          IOMUX_PAD(0x3A8, 0x7C, 2, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7       IOMUX_PAD(0x3A8, 0x7C, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0        IOMUX_PAD(0x3A8, 0x7C, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12  IOMUX_PAD(0x3A8, 0x7C, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x7C, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8   IOMUX_PAD(0x3AC, 0x80, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT8__GPIO4_29          IOMUX_PAD(0x3AC, 0x80, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT8__PWM1_PWMO         IOMUX_PAD(0x3AC, 0x80, 2, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B      IOMUX_PAD(0x3AC, 0x80, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1        IOMUX_PAD(0x3AC, 0x80, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13  IOMUX_PAD(0x3AC, 0x80, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT8__USBPHY2_AVALID    IOMUX_PAD(0x3AC, 0x80, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9   IOMUX_PAD(0x3B0, 0x84, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT9__GPIO4_30          IOMUX_PAD(0x3B0, 0x84, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT9__PWM2_PWMO         IOMUX_PAD(0x3B0, 0x84, 2, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B      IOMUX_PAD(0x3B0, 0x84, 3, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2                IOMUX_PAD(0x3B0, 0x84, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14  IOMUX_PAD(0x3B0, 0x84, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x84, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x88, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT10__GPIO4_31         IOMUX_PAD(0x3B4, 0x88, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x88, 2, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3       IOMUX_PAD(0x3B4, 0x88, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x88, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1        IOMUX_PAD(0x3B4, 0x88, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x8C, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT11__GPIO5_5          IOMUX_PAD(0x3B8, 0x8C, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x8C, 2, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4       IOMUX_PAD(0x3B8, 0x8C, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x8C, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2        IOMUX_PAD(0x3B8, 0x8C, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x90, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT12__GPIO5_6          IOMUX_PAD(0x3BC, 0x90, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x90, 2, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5       IOMUX_PAD(0x3BC, 0x90, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x90, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3        IOMUX_PAD(0x3BC, 0x90, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x94, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT13__GPIO5_7          IOMUX_PAD(0x3C0, 0x94, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x94, 3, 0x754, 0, 0)
+#define _MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0       IOMUX_PAD(0x3C0, 0x94, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x94, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4        IOMUX_PAD(0x3C0, 0x94, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x98, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT14__GPIO5_8          IOMUX_PAD(0x3C4, 0x98, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC  IOMUX_PAD(0x3C4, 0x98, 3, 0x750, 0, 0)
+#define _MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1       IOMUX_PAD(0x3C4, 0x98, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x98, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5        IOMUX_PAD(0x3C4, 0x98, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x9C, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT15__GPIO5_9          IOMUX_PAD(0x3C8, 0x9C, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT15__ECSPI1_SS1               IOMUX_PAD(0x3C8, 0x9C, 2, 0x7AC, 1, 0)
+#define _MX53_PAD_DISP0_DAT15__ECSPI2_SS1               IOMUX_PAD(0x3C8, 0x9C, 3, 0x7C8, 0, 0)
+#define _MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2       IOMUX_PAD(0x3C8, 0x9C, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x9C, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6        IOMUX_PAD(0x3C8, 0x9C, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0xA0, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT16__GPIO5_10         IOMUX_PAD(0x3CC, 0xA0, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT16__ECSPI2_MOSI              IOMUX_PAD(0x3CC, 0xA0, 2, 0x7C0, 0, 0)
+#define _MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC  IOMUX_PAD(0x3CC, 0xA0, 3, 0x758, 1, 0)
+#define _MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0xA0, 4, 0x868, 0, 0)
+#define _MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3       IOMUX_PAD(0x3CC, 0xA0, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0xA0, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7        IOMUX_PAD(0x3CC, 0xA0, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0xA4, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT17__GPIO5_11         IOMUX_PAD(0x3D0, 0xA4, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT17__ECSPI2_MISO              IOMUX_PAD(0x3D0, 0xA4, 2, 0x7BC, 0, 0)
+#define _MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD  IOMUX_PAD(0x3D0, 0xA4, 3, 0x74C, 1, 0)
+#define _MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0xA4, 4, 0x86C, 0, 0)
+#define _MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4       IOMUX_PAD(0x3D0, 0xA4, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0xA4, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0xA8, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT18__GPIO5_12         IOMUX_PAD(0x3D4, 0xA8, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT18__ECSPI2_SS0               IOMUX_PAD(0x3D4, 0xA8, 2, 0x7C4, 0, 0)
+#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0xA8, 3, 0x75C, 1, 0)
+#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0xA8, 4, 0x73C, 0, 0)
+#define _MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5       IOMUX_PAD(0x3D4, 0xA8, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0xA8, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2    IOMUX_PAD(0x3D4, 0xA8, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0xAC, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT19__GPIO5_13         IOMUX_PAD(0x3D8, 0xAC, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT19__ECSPI2_SCLK              IOMUX_PAD(0x3D8, 0xAC, 2, 0x7B8, 0, 0)
+#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD  IOMUX_PAD(0x3D8, 0xAC, 3, 0x748, 1, 0)
+#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC  IOMUX_PAD(0x3D8, 0xAC, 4, 0x738, 0, 0)
+#define _MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6       IOMUX_PAD(0x3D8, 0xAC, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0xAC, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3    IOMUX_PAD(0x3D8, 0xAC, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0xB0, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT20__GPIO5_14         IOMUX_PAD(0x3DC, 0xB0, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT20__ECSPI1_SCLK              IOMUX_PAD(0x3DC, 0xB0, 2, 0x79C, 1, 0)
+#define _MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC  IOMUX_PAD(0x3DC, 0xB0, 3, 0x740, 0, 0)
+#define _MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7       IOMUX_PAD(0x3DC, 0xB0, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0xB0, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT20__SATA_PHY_TDI             IOMUX_PAD(0x3DC, 0xB0, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0xB4, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT21__GPIO5_15         IOMUX_PAD(0x3E0, 0xB4, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT21__ECSPI1_MOSI              IOMUX_PAD(0x3E0, 0xB4, 2, 0x7A4, 1, 0)
+#define _MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD  IOMUX_PAD(0x3E0, 0xB4, 3, 0x734, 0, 0)
+#define _MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0  IOMUX_PAD(0x3E0, 0xB4, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0xB4, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT21__SATA_PHY_TDO     IOMUX_PAD(0x3E0, 0xB4, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0xB8, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT22__GPIO5_16         IOMUX_PAD(0x3E4, 0xB8, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT22__ECSPI1_MISO              IOMUX_PAD(0x3E4, 0xB8, 2, 0x7A0, 1, 0)
+#define _MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0xB8, 3, 0x744, 0, 0)
+#define _MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1  IOMUX_PAD(0x3E4, 0xB8, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0xB8, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT22__SATA_PHY_TCK     IOMUX_PAD(0x3E4, 0xB8, 7, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0xBC, 0, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT23__GPIO5_17         IOMUX_PAD(0x3E8, 0xBC, 1, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT23__ECSPI1_SS0               IOMUX_PAD(0x3E8, 0xBC, 2, 0x7A8, 1, 0)
+#define _MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD  IOMUX_PAD(0x3E8, 0xBC, 3, 0x730, 0, 0)
+#define _MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2  IOMUX_PAD(0x3E8, 0xBC, 5, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0xBC, 6, 0x0, 0, 0)
+#define _MX53_PAD_DISP0_DAT23__SATA_PHY_TMS     IOMUX_PAD(0x3E8, 0xBC, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK  IOMUX_PAD(0x3EC, 0xC0, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_PIXCLK__GPIO5_18         IOMUX_PAD(0x3EC, 0xC0, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0  IOMUX_PAD(0x3EC, 0xC0, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0xC0, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC             IOMUX_PAD(0x3F0, 0xC4, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_MCLK__GPIO5_19           IOMUX_PAD(0x3F0, 0xC4, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK              IOMUX_PAD(0x3F0, 0xC4, 2, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1    IOMUX_PAD(0x3F0, 0xC4, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30   IOMUX_PAD(0x3F0, 0xC4, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_MCLK__TPIU_TRCTL         IOMUX_PAD(0x3F0, 0xC4, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN        IOMUX_PAD(0x3F4, 0xC8, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DATA_EN__GPIO5_20                IOMUX_PAD(0x3F4, 0xC8, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0xC8, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31        IOMUX_PAD(0x3F4, 0xC8, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK              IOMUX_PAD(0x3F4, 0xC8, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC    IOMUX_PAD(0x3F8, 0xCC, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_VSYNC__GPIO5_21          IOMUX_PAD(0x3F8, 0xCC, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3   IOMUX_PAD(0x3F8, 0xCC, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32  IOMUX_PAD(0x3F8, 0xCC, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0              IOMUX_PAD(0x3F8, 0xCC, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4               IOMUX_PAD(0x3FC, 0xD0, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT4__GPIO5_22           IOMUX_PAD(0x3FC, 0xD0, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT4__KPP_COL_5          IOMUX_PAD(0x3FC, 0xD0, 2, 0x840, 1, 0)
+#define _MX53_PAD_CSI0_DAT4__ECSPI1_SCLK                IOMUX_PAD(0x3FC, 0xD0, 3, 0x79C, 2, 0)
+#define _MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP   IOMUX_PAD(0x3FC, 0xD0, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC    IOMUX_PAD(0x3FC, 0xD0, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33   IOMUX_PAD(0x3FC, 0xD0, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT4__TPIU_TRACE_1               IOMUX_PAD(0x3FC, 0xD0, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5               IOMUX_PAD(0x400, 0xD4, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT5__GPIO5_23           IOMUX_PAD(0x400, 0xD4, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT5__KPP_ROW_5          IOMUX_PAD(0x400, 0xD4, 2, 0x84C, 0, 0)
+#define _MX53_PAD_CSI0_DAT5__ECSPI1_MOSI                IOMUX_PAD(0x400, 0xD4, 3, 0x7A4, 2, 0)
+#define _MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT   IOMUX_PAD(0x400, 0xD4, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD    IOMUX_PAD(0x400, 0xD4, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34   IOMUX_PAD(0x400, 0xD4, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT5__TPIU_TRACE_2               IOMUX_PAD(0x400, 0xD4, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6               IOMUX_PAD(0x404, 0xD8, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT6__GPIO5_24           IOMUX_PAD(0x404, 0xD8, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT6__KPP_COL_6          IOMUX_PAD(0x404, 0xD8, 2, 0x844, 0, 0)
+#define _MX53_PAD_CSI0_DAT6__ECSPI1_MISO                IOMUX_PAD(0x404, 0xD8, 3, 0x7A0, 2, 0)
+#define _MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK   IOMUX_PAD(0x404, 0xD8, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS   IOMUX_PAD(0x404, 0xD8, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35   IOMUX_PAD(0x404, 0xD8, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT6__TPIU_TRACE_3               IOMUX_PAD(0x404, 0xD8, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7               IOMUX_PAD(0x408, 0xDC, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT7__GPIO5_25           IOMUX_PAD(0x408, 0xDC, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT7__KPP_ROW_6          IOMUX_PAD(0x408, 0xDC, 2, 0x850, 0, 0)
+#define _MX53_PAD_CSI0_DAT7__ECSPI1_SS0         IOMUX_PAD(0x408, 0xDC, 3, 0x7A8, 2, 0)
+#define _MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR   IOMUX_PAD(0x408, 0xDC, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD    IOMUX_PAD(0x408, 0xDC, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36   IOMUX_PAD(0x408, 0xDC, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT7__TPIU_TRACE_4               IOMUX_PAD(0x408, 0xDC, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8               IOMUX_PAD(0x40C, 0xE0, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT8__GPIO5_26           IOMUX_PAD(0x40C, 0xE0, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT8__KPP_COL_7          IOMUX_PAD(0x40C, 0xE0, 2, 0x848, 0, 0)
+#define _MX53_PAD_CSI0_DAT8__ECSPI2_SCLK                IOMUX_PAD(0x40C, 0xE0, 3, 0x7B8, 1, 0)
+#define _MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC    IOMUX_PAD(0x40C, 0xE0, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT8__I2C1_SDA           IOMUX_PAD(0x40C, 0xE0, 5 | IOMUX_CONFIG_SION, 0x818, 0, 0)
+#define _MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37   IOMUX_PAD(0x40C, 0xE0, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT8__TPIU_TRACE_5               IOMUX_PAD(0x40C, 0xE0, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9               IOMUX_PAD(0x410, 0xE4, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT9__GPIO5_27           IOMUX_PAD(0x410, 0xE4, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT9__KPP_ROW_7          IOMUX_PAD(0x410, 0xE4, 2, 0x854, 0, 0)
+#define _MX53_PAD_CSI0_DAT9__ECSPI2_MOSI                IOMUX_PAD(0x410, 0xE4, 3, 0x7C0, 1, 0)
+#define _MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR   IOMUX_PAD(0x410, 0xE4, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT9__I2C1_SCL           IOMUX_PAD(0x410, 0xE4, 5 | IOMUX_CONFIG_SION, 0x814, 0, 0)
+#define _MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38   IOMUX_PAD(0x410, 0xE4, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT9__TPIU_TRACE_6               IOMUX_PAD(0x410, 0xE4, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10             IOMUX_PAD(0x414, 0xE8, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT10__GPIO5_28          IOMUX_PAD(0x414, 0xE8, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT10__UART1_TXD_MUX     IOMUX_PAD(0x414, 0xE8, 2, 0x878, 0, 0)
+#define _MX53_PAD_CSI0_DAT10__ECSPI2_MISO               IOMUX_PAD(0x414, 0xE8, 3, 0x7BC, 1, 0)
+#define _MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC   IOMUX_PAD(0x414, 0xE8, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4   IOMUX_PAD(0x414, 0xE8, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39  IOMUX_PAD(0x414, 0xE8, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT10__TPIU_TRACE_7              IOMUX_PAD(0x414, 0xE8, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11             IOMUX_PAD(0x418, 0xEC, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT11__GPIO5_29          IOMUX_PAD(0x418, 0xEC, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT11__UART1_RXD_MUX     IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, 0)
+#define _MX53_PAD_CSI0_DAT11__ECSPI2_SS0                IOMUX_PAD(0x418, 0xEC, 3, 0x7C4, 1, 0)
+#define _MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS  IOMUX_PAD(0x418, 0xEC, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5   IOMUX_PAD(0x418, 0xEC, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40  IOMUX_PAD(0x418, 0xEC, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT11__TPIU_TRACE_8              IOMUX_PAD(0x418, 0xEC, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12             IOMUX_PAD(0x41C, 0xF0, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT12__GPIO5_30          IOMUX_PAD(0x41C, 0xF0, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT12__UART4_TXD_MUX     IOMUX_PAD(0x41C, 0xF0, 2, 0x890, 2, 0)
+#define _MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0       IOMUX_PAD(0x41C, 0xF0, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6   IOMUX_PAD(0x41C, 0xF0, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41  IOMUX_PAD(0x41C, 0xF0, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT12__TPIU_TRACE_9              IOMUX_PAD(0x41C, 0xF0, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13             IOMUX_PAD(0x420, 0xF4, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT13__GPIO5_31          IOMUX_PAD(0x420, 0xF4, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT13__UART4_RXD_MUX     IOMUX_PAD(0x420, 0xF4, 2, 0x890, 3, 0)
+#define _MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1       IOMUX_PAD(0x420, 0xF4, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7   IOMUX_PAD(0x420, 0xF4, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42  IOMUX_PAD(0x420, 0xF4, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT13__TPIU_TRACE_10             IOMUX_PAD(0x420, 0xF4, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14             IOMUX_PAD(0x424, 0xF8, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT14__GPIO6_0           IOMUX_PAD(0x424, 0xF8, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT14__UART5_TXD_MUX     IOMUX_PAD(0x424, 0xF8, 2, 0x898, 2, 0)
+#define _MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2       IOMUX_PAD(0x424, 0xF8, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8   IOMUX_PAD(0x424, 0xF8, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43  IOMUX_PAD(0x424, 0xF8, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT14__TPIU_TRACE_11             IOMUX_PAD(0x424, 0xF8, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15             IOMUX_PAD(0x428, 0xFC, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT15__GPIO6_1           IOMUX_PAD(0x428, 0xFC, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT15__UART5_RXD_MUX     IOMUX_PAD(0x428, 0xFC, 2, 0x898, 3, 0)
+#define _MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3       IOMUX_PAD(0x428, 0xFC, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9   IOMUX_PAD(0x428, 0xFC, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44  IOMUX_PAD(0x428, 0xFC, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT15__TPIU_TRACE_12             IOMUX_PAD(0x428, 0xFC, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16             IOMUX_PAD(0x42C, 0x100, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT16__GPIO6_2           IOMUX_PAD(0x42C, 0x100, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT16__UART4_RTS         IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, 0)
+#define _MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4       IOMUX_PAD(0x42C, 0x100, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10  IOMUX_PAD(0x42C, 0x100, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45  IOMUX_PAD(0x42C, 0x100, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT16__TPIU_TRACE_13             IOMUX_PAD(0x42C, 0x100, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17             IOMUX_PAD(0x430, 0x104, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT17__GPIO6_3           IOMUX_PAD(0x430, 0x104, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT17__UART4_CTS         IOMUX_PAD(0x430, 0x104, 2, 0x88C, 1, 0)
+#define _MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5       IOMUX_PAD(0x430, 0x104, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11  IOMUX_PAD(0x430, 0x104, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46  IOMUX_PAD(0x430, 0x104, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT17__TPIU_TRACE_14             IOMUX_PAD(0x430, 0x104, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18             IOMUX_PAD(0x434, 0x108, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT18__GPIO6_4           IOMUX_PAD(0x434, 0x108, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT18__UART5_RTS         IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, 0)
+#define _MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6       IOMUX_PAD(0x434, 0x108, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12  IOMUX_PAD(0x434, 0x108, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47  IOMUX_PAD(0x434, 0x108, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT18__TPIU_TRACE_15             IOMUX_PAD(0x434, 0x108, 7, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19             IOMUX_PAD(0x438, 0x10C, 0, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT19__GPIO6_5           IOMUX_PAD(0x438, 0x10C, 1, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT19__UART5_CTS         IOMUX_PAD(0x438, 0x10C, 2, 0x894, 3, 0)
+#define _MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7       IOMUX_PAD(0x438, 0x10C, 4, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13  IOMUX_PAD(0x438, 0x10C, 5, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48  IOMUX_PAD(0x438, 0x10C, 6, 0x0, 0, 0)
+#define _MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK    IOMUX_PAD(0x438, 0x10C, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A25__EMI_WEIM_A_25                IOMUX_PAD(0x458, 0x110, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A25__GPIO5_2                      IOMUX_PAD(0x458, 0x110, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A25__ECSPI2_RDY           IOMUX_PAD(0x458, 0x110, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A25__IPU_DI1_PIN12                IOMUX_PAD(0x458, 0x110, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A25__CSPI_SS1                     IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, 0)
+#define _MX53_PAD_EIM_A25__IPU_DI0_D1_CS                IOMUX_PAD(0x458, 0x110, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A25__USBPHY1_BISTOK               IOMUX_PAD(0x458, 0x110, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB2__EMI_WEIM_EB_2                IOMUX_PAD(0x45C, 0x114, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB2__GPIO2_30                     IOMUX_PAD(0x45C, 0x114, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK              IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, 0)
+#define _MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS             IOMUX_PAD(0x45C, 0x114, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB2__ECSPI1_SS0           IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, 0)
+#define _MX53_PAD_EIM_EB2__I2C2_SCL                     IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, 0)
+#define _MX53_PAD_EIM_D16__EMI_WEIM_D_16                IOMUX_PAD(0x460, 0x118, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D16__GPIO3_16                     IOMUX_PAD(0x460, 0x118, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D16__IPU_DI0_PIN5         IOMUX_PAD(0x460, 0x118, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK   IOMUX_PAD(0x460, 0x118, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D16__ECSPI1_SCLK          IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, 0)
+#define _MX53_PAD_EIM_D16__I2C2_SDA                     IOMUX_PAD(0x460, 0x118, 5, 0x820, 1, 0)
+#define _MX53_PAD_EIM_D17__EMI_WEIM_D_17                IOMUX_PAD(0x464, 0x11C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D17__GPIO3_17                     IOMUX_PAD(0x464, 0x11C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D17__IPU_DI0_PIN6         IOMUX_PAD(0x464, 0x11C, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN   IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, 0)
+#define _MX53_PAD_EIM_D17__ECSPI1_MISO          IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, 0)
+#define _MX53_PAD_EIM_D17__I2C3_SCL                     IOMUX_PAD(0x464, 0x11C, 5, 0x824, 0, 0)
+#define _MX53_PAD_EIM_D18__EMI_WEIM_D_18                IOMUX_PAD(0x468, 0x120, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D18__GPIO3_18                     IOMUX_PAD(0x468, 0x120, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D18__IPU_DI0_PIN7         IOMUX_PAD(0x468, 0x120, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO   IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, 0)
+#define _MX53_PAD_EIM_D18__ECSPI1_MOSI          IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, 0)
+#define _MX53_PAD_EIM_D18__I2C3_SDA                     IOMUX_PAD(0x468, 0x120, 5, 0x828, 0, 0)
+#define _MX53_PAD_EIM_D18__IPU_DI1_D0_CS                IOMUX_PAD(0x468, 0x120, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D19__EMI_WEIM_D_19                IOMUX_PAD(0x46C, 0x124, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D19__GPIO3_19                     IOMUX_PAD(0x46C, 0x124, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D19__IPU_DI0_PIN8         IOMUX_PAD(0x46C, 0x124, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS    IOMUX_PAD(0x46C, 0x124, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D19__ECSPI1_SS1           IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, 0)
+#define _MX53_PAD_EIM_D19__EPIT1_EPITO          IOMUX_PAD(0x46C, 0x124, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D19__UART1_CTS                    IOMUX_PAD(0x46C, 0x124, 6, 0x874, 0, 0)
+#define _MX53_PAD_EIM_D19__USBOH3_USBH2_OC              IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, 0)
+#define _MX53_PAD_EIM_D20__EMI_WEIM_D_20                IOMUX_PAD(0x470, 0x128, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D20__GPIO3_20                     IOMUX_PAD(0x470, 0x128, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D20__IPU_DI0_PIN16                IOMUX_PAD(0x470, 0x128, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D20__IPU_SER_DISP0_CS             IOMUX_PAD(0x470, 0x128, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D20__CSPI_SS0                     IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, 0)
+#define _MX53_PAD_EIM_D20__EPIT2_EPITO          IOMUX_PAD(0x470, 0x128, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D20__UART1_RTS                    IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, 0)
+#define _MX53_PAD_EIM_D20__USBOH3_USBH2_PWR     IOMUX_PAD(0x470, 0x128, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D21__EMI_WEIM_D_21                IOMUX_PAD(0x474, 0x12C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D21__GPIO3_21                     IOMUX_PAD(0x474, 0x12C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D21__IPU_DI0_PIN17                IOMUX_PAD(0x474, 0x12C, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK   IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D21__CSPI_SCLK                    IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, 0)
+#define _MX53_PAD_EIM_D21__I2C1_SCL                     IOMUX_PAD(0x474, 0x12C, 5, 0x814, 1, 0)
+#define _MX53_PAD_EIM_D21__USBOH3_USBOTG_OC     IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, 0)
+#define _MX53_PAD_EIM_D22__EMI_WEIM_D_22                IOMUX_PAD(0x478, 0x130, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D22__GPIO3_22                     IOMUX_PAD(0x478, 0x130, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D22__IPU_DI0_PIN1         IOMUX_PAD(0x478, 0x130, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN   IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, 0)
+#define _MX53_PAD_EIM_D22__CSPI_MISO                    IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, 0)
+#define _MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR    IOMUX_PAD(0x478, 0x130, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D23__EMI_WEIM_D_23                IOMUX_PAD(0x47C, 0x134, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D23__GPIO3_23                     IOMUX_PAD(0x47C, 0x134, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D23__UART3_CTS                    IOMUX_PAD(0x47C, 0x134, 2, 0x884, 0, 0)
+#define _MX53_PAD_EIM_D23__UART1_DCD            IOMUX_PAD(0x47C, 0x134, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D23__IPU_DI0_D0_CS                IOMUX_PAD(0x47C, 0x134, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D23__IPU_DI1_PIN2         IOMUX_PAD(0x47C, 0x134, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN             IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, 0)
+#define _MX53_PAD_EIM_D23__IPU_DI1_PIN14                IOMUX_PAD(0x47C, 0x134, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB3__EMI_WEIM_EB_3                IOMUX_PAD(0x480, 0x138, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB3__GPIO2_31                     IOMUX_PAD(0x480, 0x138, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB3__UART3_RTS                    IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, 0)
+#define _MX53_PAD_EIM_EB3__UART1_RI                     IOMUX_PAD(0x480, 0x138, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN3         IOMUX_PAD(0x480, 0x138, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC               IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, 0)
+#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN16                IOMUX_PAD(0x480, 0x138, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D24__EMI_WEIM_D_24                IOMUX_PAD(0x484, 0x13C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D24__GPIO3_24                     IOMUX_PAD(0x484, 0x13C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D24__UART3_TXD_MUX                IOMUX_PAD(0x484, 0x13C, 2, 0x888, 0, 0)
+#define _MX53_PAD_EIM_D24__ECSPI1_SS2           IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, 0)
+#define _MX53_PAD_EIM_D24__CSPI_SS2                     IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, 0)
+#define _MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS     IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, 0)
+#define _MX53_PAD_EIM_D24__ECSPI2_SS2           IOMUX_PAD(0x484, 0x13C, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D24__UART1_DTR            IOMUX_PAD(0x484, 0x13C, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D25__EMI_WEIM_D_25                IOMUX_PAD(0x488, 0x140, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D25__GPIO3_25                     IOMUX_PAD(0x488, 0x140, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D25__UART3_RXD_MUX                IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, 0)
+#define _MX53_PAD_EIM_D25__ECSPI1_SS3           IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, 0)
+#define _MX53_PAD_EIM_D25__CSPI_SS3                     IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, 0)
+#define _MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC              IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, 0)
+#define _MX53_PAD_EIM_D25__ECSPI2_SS3           IOMUX_PAD(0x488, 0x140, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D25__UART1_DSR            IOMUX_PAD(0x488, 0x140, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D26__EMI_WEIM_D_26                IOMUX_PAD(0x48C, 0x144, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D26__GPIO3_26                     IOMUX_PAD(0x48C, 0x144, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D26__UART2_TXD_MUX                IOMUX_PAD(0x48C, 0x144, 2, 0x880, 0, 0)
+#define _MX53_PAD_EIM_D26__FIRI_RXD                     IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, 0)
+#define _MX53_PAD_EIM_D26__IPU_CSI0_D_1         IOMUX_PAD(0x48C, 0x144, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D26__IPU_DI1_PIN11                IOMUX_PAD(0x48C, 0x144, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D26__IPU_SISG_2           IOMUX_PAD(0x48C, 0x144, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D26__IPU_DISP1_DAT_22             IOMUX_PAD(0x48C, 0x144, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D27__EMI_WEIM_D_27                IOMUX_PAD(0x490, 0x148, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D27__GPIO3_27                     IOMUX_PAD(0x490, 0x148, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D27__UART2_RXD_MUX                IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, 0)
+#define _MX53_PAD_EIM_D27__FIRI_TXD                     IOMUX_PAD(0x490, 0x148, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D27__IPU_CSI0_D_0         IOMUX_PAD(0x490, 0x148, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D27__IPU_DI1_PIN13                IOMUX_PAD(0x490, 0x148, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D27__IPU_SISG_3           IOMUX_PAD(0x490, 0x148, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D27__IPU_DISP1_DAT_23             IOMUX_PAD(0x490, 0x148, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D28__EMI_WEIM_D_28                IOMUX_PAD(0x494, 0x14C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D28__GPIO3_28                     IOMUX_PAD(0x494, 0x14C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D28__UART2_CTS                    IOMUX_PAD(0x494, 0x14C, 2, 0x87C, 0, 0)
+#define _MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO   IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, 0)
+#define _MX53_PAD_EIM_D28__CSPI_MOSI                    IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, 0)
+#define _MX53_PAD_EIM_D28__I2C1_SDA                     IOMUX_PAD(0x494, 0x14C, 5, 0x818, 1, 0)
+#define _MX53_PAD_EIM_D28__IPU_EXT_TRIG         IOMUX_PAD(0x494, 0x14C, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D28__IPU_DI0_PIN13                IOMUX_PAD(0x494, 0x14C, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D29__EMI_WEIM_D_29                IOMUX_PAD(0x498, 0x150, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D29__GPIO3_29                     IOMUX_PAD(0x498, 0x150, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D29__UART2_RTS                    IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, 0)
+#define _MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS    IOMUX_PAD(0x498, 0x150, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D29__CSPI_SS0                     IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, 0)
+#define _MX53_PAD_EIM_D29__IPU_DI1_PIN15                IOMUX_PAD(0x498, 0x150, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D29__IPU_CSI1_VSYNC               IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, 0)
+#define _MX53_PAD_EIM_D29__IPU_DI0_PIN14                IOMUX_PAD(0x498, 0x150, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D30__EMI_WEIM_D_30                IOMUX_PAD(0x49C, 0x154, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D30__GPIO3_30                     IOMUX_PAD(0x49C, 0x154, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D30__UART3_CTS                    IOMUX_PAD(0x49C, 0x154, 2, 0x884, 2, 0)
+#define _MX53_PAD_EIM_D30__IPU_CSI0_D_3         IOMUX_PAD(0x49C, 0x154, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D30__IPU_DI0_PIN11                IOMUX_PAD(0x49C, 0x154, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D30__IPU_DISP1_DAT_21             IOMUX_PAD(0x49C, 0x154, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D30__USBOH3_USBH1_OC              IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, 0)
+#define _MX53_PAD_EIM_D30__USBOH3_USBH2_OC              IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, 0)
+#define _MX53_PAD_EIM_D31__EMI_WEIM_D_31                IOMUX_PAD(0x4A0, 0x158, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D31__GPIO3_31                     IOMUX_PAD(0x4A0, 0x158, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D31__UART3_RTS                    IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, 0)
+#define _MX53_PAD_EIM_D31__IPU_CSI0_D_2         IOMUX_PAD(0x4A0, 0x158, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D31__IPU_DI0_PIN12                IOMUX_PAD(0x4A0, 0x158, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D31__IPU_DISP1_DAT_20             IOMUX_PAD(0x4A0, 0x158, 5, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D31__USBOH3_USBH1_PWR     IOMUX_PAD(0x4A0, 0x158, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_D31__USBOH3_USBH2_PWR     IOMUX_PAD(0x4A0, 0x158, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A24__EMI_WEIM_A_24                IOMUX_PAD(0x4A8, 0x15C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A24__GPIO5_4                      IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A24__IPU_DISP1_DAT_19             IOMUX_PAD(0x4A8, 0x15C, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A24__IPU_CSI1_D_19                IOMUX_PAD(0x4A8, 0x15C, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A24__IPU_SISG_2           IOMUX_PAD(0x4A8, 0x15C, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A24__USBPHY2_BVALID               IOMUX_PAD(0x4A8, 0x15C, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A23__EMI_WEIM_A_23                IOMUX_PAD(0x4AC, 0x160, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A23__GPIO6_6                      IOMUX_PAD(0x4AC, 0x160, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A23__IPU_DISP1_DAT_18             IOMUX_PAD(0x4AC, 0x160, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A23__IPU_CSI1_D_18                IOMUX_PAD(0x4AC, 0x160, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A23__IPU_SISG_3           IOMUX_PAD(0x4AC, 0x160, 6, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A23__USBPHY2_ENDSESSION   IOMUX_PAD(0x4AC, 0x160, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A22__EMI_WEIM_A_22                IOMUX_PAD(0x4B0, 0x164, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A22__GPIO2_16                     IOMUX_PAD(0x4B0, 0x164, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A22__IPU_DISP1_DAT_17             IOMUX_PAD(0x4B0, 0x164, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A22__IPU_CSI1_D_17                IOMUX_PAD(0x4B0, 0x164, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A22__SRC_BT_CFG1_7                IOMUX_PAD(0x4B0, 0x164, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A21__EMI_WEIM_A_21                IOMUX_PAD(0x4B4, 0x168, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A21__GPIO2_17                     IOMUX_PAD(0x4B4, 0x168, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A21__IPU_DISP1_DAT_16             IOMUX_PAD(0x4B4, 0x168, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A21__IPU_CSI1_D_16                IOMUX_PAD(0x4B4, 0x168, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A21__SRC_BT_CFG1_6                IOMUX_PAD(0x4B4, 0x168, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A20__EMI_WEIM_A_20                IOMUX_PAD(0x4B8, 0x16C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A20__GPIO2_18                     IOMUX_PAD(0x4B8, 0x16C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A20__IPU_DISP1_DAT_15             IOMUX_PAD(0x4B8, 0x16C, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A20__IPU_CSI1_D_15                IOMUX_PAD(0x4B8, 0x16C, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A20__SRC_BT_CFG1_5                IOMUX_PAD(0x4B8, 0x16C, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A19__EMI_WEIM_A_19                IOMUX_PAD(0x4BC, 0x170, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A19__GPIO2_19                     IOMUX_PAD(0x4BC, 0x170, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A19__IPU_DISP1_DAT_14             IOMUX_PAD(0x4BC, 0x170, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A19__IPU_CSI1_D_14                IOMUX_PAD(0x4BC, 0x170, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A19__SRC_BT_CFG1_4                IOMUX_PAD(0x4BC, 0x170, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A18__EMI_WEIM_A_18                IOMUX_PAD(0x4C0, 0x174, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A18__GPIO2_20                     IOMUX_PAD(0x4C0, 0x174, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A18__IPU_DISP1_DAT_13             IOMUX_PAD(0x4C0, 0x174, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A18__IPU_CSI1_D_13                IOMUX_PAD(0x4C0, 0x174, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A18__SRC_BT_CFG1_3                IOMUX_PAD(0x4C0, 0x174, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A17__EMI_WEIM_A_17                IOMUX_PAD(0x4C4, 0x178, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A17__GPIO2_21                     IOMUX_PAD(0x4C4, 0x178, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A17__IPU_DISP1_DAT_12             IOMUX_PAD(0x4C4, 0x178, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A17__IPU_CSI1_D_12                IOMUX_PAD(0x4C4, 0x178, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A17__SRC_BT_CFG1_2                IOMUX_PAD(0x4C4, 0x178, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A16__EMI_WEIM_A_16                IOMUX_PAD(0x4C8, 0x17C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A16__GPIO2_22                     IOMUX_PAD(0x4C8, 0x17C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK             IOMUX_PAD(0x4C8, 0x17C, 2, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK              IOMUX_PAD(0x4C8, 0x17C, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_A16__SRC_BT_CFG1_1                IOMUX_PAD(0x4C8, 0x17C, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_CS0__EMI_WEIM_CS_0                IOMUX_PAD(0x4CC, 0x180, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_CS0__GPIO2_23                     IOMUX_PAD(0x4CC, 0x180, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_CS0__ECSPI2_SCLK          IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, 0)
+#define _MX53_PAD_EIM_CS0__IPU_DI1_PIN5         IOMUX_PAD(0x4CC, 0x180, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_CS1__EMI_WEIM_CS_1                IOMUX_PAD(0x4D0, 0x184, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_CS1__GPIO2_24                     IOMUX_PAD(0x4D0, 0x184, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_CS1__ECSPI2_MOSI          IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, 0)
+#define _MX53_PAD_EIM_CS1__IPU_DI1_PIN6         IOMUX_PAD(0x4D0, 0x184, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_OE__EMI_WEIM_OE           IOMUX_PAD(0x4D4, 0x188, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_OE__GPIO2_25                      IOMUX_PAD(0x4D4, 0x188, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_OE__ECSPI2_MISO           IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, 0)
+#define _MX53_PAD_EIM_OE__IPU_DI1_PIN7          IOMUX_PAD(0x4D4, 0x188, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_OE__USBPHY2_IDDIG         IOMUX_PAD(0x4D4, 0x188, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_RW__EMI_WEIM_RW           IOMUX_PAD(0x4D8, 0x18C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_RW__GPIO2_26                      IOMUX_PAD(0x4D8, 0x18C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_RW__ECSPI2_SS0                    IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, 0)
+#define _MX53_PAD_EIM_RW__IPU_DI1_PIN8          IOMUX_PAD(0x4D8, 0x18C, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT        IOMUX_PAD(0x4D8, 0x18C, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_LBA__EMI_WEIM_LBA         IOMUX_PAD(0x4DC, 0x190, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_LBA__GPIO2_27                     IOMUX_PAD(0x4DC, 0x190, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_LBA__ECSPI2_SS1           IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, 0)
+#define _MX53_PAD_EIM_LBA__IPU_DI1_PIN17                IOMUX_PAD(0x4DC, 0x190, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_LBA__SRC_BT_CFG1_0                IOMUX_PAD(0x4DC, 0x190, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB0__EMI_WEIM_EB_0                IOMUX_PAD(0x4E4, 0x194, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB0__GPIO2_28                     IOMUX_PAD(0x4E4, 0x194, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11             IOMUX_PAD(0x4E4, 0x194, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB0__IPU_CSI1_D_11                IOMUX_PAD(0x4E4, 0x194, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB0__GPC_PMIC_RDY         IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, 0)
+#define _MX53_PAD_EIM_EB0__SRC_BT_CFG2_7                IOMUX_PAD(0x4E4, 0x194, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB1__EMI_WEIM_EB_1                IOMUX_PAD(0x4E8, 0x198, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB1__GPIO2_29                     IOMUX_PAD(0x4E8, 0x198, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10             IOMUX_PAD(0x4E8, 0x198, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB1__IPU_CSI1_D_10                IOMUX_PAD(0x4E8, 0x198, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_EB1__SRC_BT_CFG2_6                IOMUX_PAD(0x4E8, 0x198, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0   IOMUX_PAD(0x4EC, 0x19C, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA0__GPIO3_0                      IOMUX_PAD(0x4EC, 0x19C, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9              IOMUX_PAD(0x4EC, 0x19C, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA0__IPU_CSI1_D_9         IOMUX_PAD(0x4EC, 0x19C, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA0__SRC_BT_CFG2_5                IOMUX_PAD(0x4EC, 0x19C, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1   IOMUX_PAD(0x4F0, 0x1A0, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA1__GPIO3_1                      IOMUX_PAD(0x4F0, 0x1A0, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8              IOMUX_PAD(0x4F0, 0x1A0, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA1__IPU_CSI1_D_8         IOMUX_PAD(0x4F0, 0x1A0, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA1__SRC_BT_CFG2_4                IOMUX_PAD(0x4F0, 0x1A0, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2   IOMUX_PAD(0x4F4, 0x1A4, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA2__GPIO3_2                      IOMUX_PAD(0x4F4, 0x1A4, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7              IOMUX_PAD(0x4F4, 0x1A4, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA2__IPU_CSI1_D_7         IOMUX_PAD(0x4F4, 0x1A4, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA2__SRC_BT_CFG2_3                IOMUX_PAD(0x4F4, 0x1A4, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3   IOMUX_PAD(0x4F8, 0x1A8, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA3__GPIO3_3                      IOMUX_PAD(0x4F8, 0x1A8, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6              IOMUX_PAD(0x4F8, 0x1A8, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA3__IPU_CSI1_D_6         IOMUX_PAD(0x4F8, 0x1A8, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA3__SRC_BT_CFG2_2                IOMUX_PAD(0x4F8, 0x1A8, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4   IOMUX_PAD(0x4FC, 0x1AC, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA4__GPIO3_4                      IOMUX_PAD(0x4FC, 0x1AC, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5              IOMUX_PAD(0x4FC, 0x1AC, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA4__IPU_CSI1_D_5         IOMUX_PAD(0x4FC, 0x1AC, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA4__SRC_BT_CFG3_7                IOMUX_PAD(0x4FC, 0x1AC, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5   IOMUX_PAD(0x500, 0x1B0, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA5__GPIO3_5                      IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4              IOMUX_PAD(0x500, 0x1B0, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA5__IPU_CSI1_D_4         IOMUX_PAD(0x500, 0x1B0, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA5__SRC_BT_CFG3_6                IOMUX_PAD(0x500, 0x1B0, 17, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6   IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA6__GPIO3_6                      IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3              IOMUX_PAD(0x504, 0x1B4, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA6__IPU_CSI1_D_3         IOMUX_PAD(0x504, 0x1B4, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA6__SRC_BT_CFG3_5                IOMUX_PAD(0x504, 0x1B4, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7   IOMUX_PAD(0x508, 0x1B8, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA7__GPIO3_7                      IOMUX_PAD(0x508, 0x1B8, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2              IOMUX_PAD(0x508, 0x1B8, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA7__IPU_CSI1_D_2         IOMUX_PAD(0x508, 0x1B8, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA7__SRC_BT_CFG3_4                IOMUX_PAD(0x508, 0x1B8, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8   IOMUX_PAD(0x50C, 0x1BC, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA8__GPIO3_8                      IOMUX_PAD(0x50C, 0x1BC, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1              IOMUX_PAD(0x50C, 0x1BC, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA8__IPU_CSI1_D_1         IOMUX_PAD(0x50C, 0x1BC, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA8__SRC_BT_CFG3_3                IOMUX_PAD(0x50C, 0x1BC, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9   IOMUX_PAD(0x510, 0x1C0, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA9__GPIO3_9                      IOMUX_PAD(0x510, 0x1C0, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0              IOMUX_PAD(0x510, 0x1C0, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA9__IPU_CSI1_D_0         IOMUX_PAD(0x510, 0x1C0, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA9__SRC_BT_CFG3_2                IOMUX_PAD(0x510, 0x1C0, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA10__GPIO3_10                    IOMUX_PAD(0x514, 0x1C4, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA10__IPU_DI1_PIN15               IOMUX_PAD(0x514, 0x1C4, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN    IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, 0)
+#define _MX53_PAD_EIM_DA10__SRC_BT_CFG3_1               IOMUX_PAD(0x514, 0x1C4, 7, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA11__GPIO3_11                    IOMUX_PAD(0x518, 0x1C8, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA11__IPU_DI1_PIN2                IOMUX_PAD(0x518, 0x1C8, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC              IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, 0)
+#define _MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA12__GPIO3_12                    IOMUX_PAD(0x51C, 0x1CC, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA12__IPU_DI1_PIN3                IOMUX_PAD(0x51C, 0x1CC, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC              IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, 0)
+#define _MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA13__GPIO3_13                    IOMUX_PAD(0x520, 0x1D0, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA13__IPU_DI1_D0_CS               IOMUX_PAD(0x520, 0x1D0, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK             IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, 0)
+#define _MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA14__GPIO3_14                    IOMUX_PAD(0x524, 0x1D4, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA14__IPU_DI1_D1_CS               IOMUX_PAD(0x524, 0x1D4, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK             IOMUX_PAD(0x524, 0x1D4, 4, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA15__GPIO3_15                    IOMUX_PAD(0x528, 0x1D8, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN1                IOMUX_PAD(0x528, 0x1D8, 3, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN4                IOMUX_PAD(0x528, 0x1D8, 4, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B    IOMUX_PAD(0x52C, 0x1DC, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_WE_B__GPIO6_12          IOMUX_PAD(0x52C, 0x1DC, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B    IOMUX_PAD(0x530, 0x1E0, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_RE_B__GPIO6_13          IOMUX_PAD(0x530, 0x1E0, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT               IOMUX_PAD(0x534, 0x1E4, 0, 0x0, 0, 0)
+#define _MX53_PAD_EIM_WAIT__GPIO5_0                     IOMUX_PAD(0x534, 0x1E4, 1, 0x0, 0, 0)
+#define _MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B    IOMUX_PAD(0x534, 0x1E4, 2, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_TX3_P__GPIO6_22         IOMUX_PAD(NON_PAD_I, 0x1EC, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3    IOMUX_PAD(NON_PAD_I, 0x1EC, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_TX2_P__GPIO6_24         IOMUX_PAD(NON_PAD_I, 0x1F0, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2    IOMUX_PAD(NON_PAD_I, 0x1F0, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_CLK_P__GPIO6_26         IOMUX_PAD(NON_PAD_I, 0x1F4, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK    IOMUX_PAD(NON_PAD_I, 0x1F4, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_TX1_P__GPIO6_28         IOMUX_PAD(NON_PAD_I, 0x1F8, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1    IOMUX_PAD(NON_PAD_I, 0x1F8, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_TX0_P__GPIO6_30         IOMUX_PAD(NON_PAD_I, 0x1FC, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0    IOMUX_PAD(NON_PAD_I, 0x1FC, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_TX3_P__GPIO7_22         IOMUX_PAD(NON_PAD_I, 0x200, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3    IOMUX_PAD(NON_PAD_I, 0x200, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_CLK_P__GPIO7_24         IOMUX_PAD(NON_PAD_I, 0x204, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK    IOMUX_PAD(NON_PAD_I, 0x204, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_TX2_P__GPIO7_26         IOMUX_PAD(NON_PAD_I, 0x208, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2    IOMUX_PAD(NON_PAD_I, 0x208, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_TX1_P__GPIO7_28         IOMUX_PAD(NON_PAD_I, 0x20C, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1    IOMUX_PAD(NON_PAD_I, 0x20C, 1, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_TX0_P__GPIO7_30         IOMUX_PAD(NON_PAD_I, 0x210, 0, 0x0, 0, 0)
+#define _MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0    IOMUX_PAD(NON_PAD_I, 0x210, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_10__GPIO4_0                      IOMUX_PAD(0x540, 0x214, 0, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_10__OSC32k_32K_OUT               IOMUX_PAD(0x540, 0x214, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_11__GPIO4_1                      IOMUX_PAD(0x544, 0x218, 0, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_12__GPIO4_2                      IOMUX_PAD(0x548, 0x21C, 0, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_13__GPIO4_3                      IOMUX_PAD(0x54C, 0x220, 0, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_14__GPIO4_4                      IOMUX_PAD(0x550, 0x224, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CLE__EMI_NANDF_CLE              IOMUX_PAD(0x5A0, 0x228, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CLE__GPIO6_7                    IOMUX_PAD(0x5A0, 0x228, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0  IOMUX_PAD(0x5A0, 0x228, 7, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_ALE__EMI_NANDF_ALE              IOMUX_PAD(0x5A4, 0x22C, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_ALE__GPIO6_8            IOMUX_PAD(0x5A4, 0x22C, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1  IOMUX_PAD(0x5A4, 0x22C, 7, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B    IOMUX_PAD(0x5A8, 0x230, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_WP_B__GPIO6_9           IOMUX_PAD(0x5A8, 0x230, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0     IOMUX_PAD(0x5AC, 0x234, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_RB0__GPIO6_10           IOMUX_PAD(0x5AC, 0x234, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3  IOMUX_PAD(0x5AC, 0x234, 7, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0     IOMUX_PAD(0x5B0, 0x238, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS0__GPIO6_11           IOMUX_PAD(0x5B0, 0x238, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4  IOMUX_PAD(0x5B0, 0x238, 7, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1     IOMUX_PAD(0x5B4, 0x23C, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS1__GPIO6_14           IOMUX_PAD(0x5B4, 0x23C, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS1__MLB_MLBCLK         IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, 0)
+#define _MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5  IOMUX_PAD(0x5B4, 0x23C, 7, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2     IOMUX_PAD(0x5B8, 0x240, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS2__GPIO6_15           IOMUX_PAD(0x5B8, 0x240, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS2__IPU_SISG_0         IOMUX_PAD(0x5B8, 0x240, 2, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS2__ESAI1_TX0          IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, 0)
+#define _MX53_PAD_NANDF_CS2__EMI_WEIM_CRE               IOMUX_PAD(0x5B8, 0x240, 4, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK              IOMUX_PAD(0x5B8, 0x240, 5, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS2__MLB_MLBSIG         IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, 0)
+#define _MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6  IOMUX_PAD(0x5B8, 0x240, 7, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3     IOMUX_PAD(0x5BC, 0x244, 0, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS3__GPIO6_16           IOMUX_PAD(0x5BC, 0x244, 1, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS3__IPU_SISG_1         IOMUX_PAD(0x5BC, 0x244, 2, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS3__ESAI1_TX1          IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, 0)
+#define _MX53_PAD_NANDF_CS3__EMI_WEIM_A_26              IOMUX_PAD(0x5BC, 0x244, 4, 0x0, 0, 0)
+#define _MX53_PAD_NANDF_CS3__MLB_MLBDAT         IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, 0)
+#define _MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7  IOMUX_PAD(0x5BC, 0x244, 7, 0x0, 0, 0)
+#define _MX53_PAD_FEC_MDIO__FEC_MDIO            IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, 0)
+#define _MX53_PAD_FEC_MDIO__GPIO1_22                    IOMUX_PAD(0x5C4, 0x248, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_MDIO__ESAI1_SCKR          IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, 0)
+#define _MX53_PAD_FEC_MDIO__FEC_COL                     IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, 0)
+#define _MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2              IOMUX_PAD(0x5C4, 0x248, 4, 0x0, 0, 0)
+#define _MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3     IOMUX_PAD(0x5C4, 0x248, 5, 0x0, 0, 0)
+#define _MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49    IOMUX_PAD(0x5C4, 0x248, 6, 0x0, 0, 0)
+#define _MX53_PAD_FEC_REF_CLK__FEC_TX_CLK               IOMUX_PAD(0x5C8, 0x24C, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_REF_CLK__GPIO1_23         IOMUX_PAD(0x5C8, 0x24C, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_REF_CLK__ESAI1_FSR                IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, 0)
+#define _MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4  IOMUX_PAD(0x5C8, 0x24C, 5, 0x0, 0, 0)
+#define _MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, 0x0, 0, 0)
+#define _MX53_PAD_FEC_RX_ER__FEC_RX_ER          IOMUX_PAD(0x5CC, 0x250, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_RX_ER__GPIO1_24           IOMUX_PAD(0x5CC, 0x250, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_RX_ER__ESAI1_HCKR         IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, 0)
+#define _MX53_PAD_FEC_RX_ER__FEC_RX_CLK         IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, 0)
+#define _MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3             IOMUX_PAD(0x5CC, 0x250, 4, 0x0, 0, 0)
+#define _MX53_PAD_FEC_CRS_DV__FEC_RX_DV         IOMUX_PAD(0x5D0, 0x254, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_CRS_DV__GPIO1_25          IOMUX_PAD(0x5D0, 0x254, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_CRS_DV__ESAI1_SCKT                IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, 0)
+#define _MX53_PAD_FEC_RXD1__FEC_RDATA_1         IOMUX_PAD(0x5D4, 0x258, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_RXD1__GPIO1_26                    IOMUX_PAD(0x5D4, 0x258, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_RXD1__ESAI1_FST           IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, 0)
+#define _MX53_PAD_FEC_RXD1__MLB_MLBSIG          IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, 0)
+#define _MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1              IOMUX_PAD(0x5D4, 0x258, 4, 0x0, 0, 0)
+#define _MX53_PAD_FEC_RXD0__FEC_RDATA_0         IOMUX_PAD(0x5D8, 0x25C, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_RXD0__GPIO1_27                    IOMUX_PAD(0x5D8, 0x25C, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_RXD0__ESAI1_HCKT          IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, 0)
+#define _MX53_PAD_FEC_RXD0__OSC32k_32K_OUT              IOMUX_PAD(0x5D8, 0x25C, 3, 0x0, 0, 0)
+#define _MX53_PAD_FEC_TX_EN__FEC_TX_EN          IOMUX_PAD(0x5DC, 0x260, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_TX_EN__GPIO1_28           IOMUX_PAD(0x5DC, 0x260, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2              IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, 0)
+#define _MX53_PAD_FEC_TXD1__FEC_TDATA_1         IOMUX_PAD(0x5E0, 0x264, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_TXD1__GPIO1_29                    IOMUX_PAD(0x5E0, 0x264, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3               IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, 0)
+#define _MX53_PAD_FEC_TXD1__MLB_MLBCLK          IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, 0)
+#define _MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, 0x0, 0, 0)
+#define _MX53_PAD_FEC_TXD0__FEC_TDATA_0         IOMUX_PAD(0x5E4, 0x268, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_TXD0__GPIO1_30                    IOMUX_PAD(0x5E4, 0x268, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1               IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, 0)
+#define _MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0   IOMUX_PAD(0x5E4, 0x268, 7, 0x0, 0, 0)
+#define _MX53_PAD_FEC_MDC__FEC_MDC                      IOMUX_PAD(0x5E8, 0x26C, 0, 0x0, 0, 0)
+#define _MX53_PAD_FEC_MDC__GPIO1_31                     IOMUX_PAD(0x5E8, 0x26C, 1, 0x0, 0, 0)
+#define _MX53_PAD_FEC_MDC__ESAI1_TX5_RX0                IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, 0)
+#define _MX53_PAD_FEC_MDC__MLB_MLBDAT           IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, 0)
+#define _MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG       IOMUX_PAD(0x5E8, 0x26C, 4, 0x0, 0, 0)
+#define _MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1    IOMUX_PAD(0x5E8, 0x26C, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DIOW__PATA_DIOW          IOMUX_PAD(0x5F0, 0x270, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DIOW__GPIO6_17           IOMUX_PAD(0x5F0, 0x270, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DIOW__UART1_TXD_MUX      IOMUX_PAD(0x5F0, 0x270, 3, 0x878, 2, 0)
+#define _MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2  IOMUX_PAD(0x5F0, 0x270, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DMACK__PATA_DMACK                IOMUX_PAD(0x5F4, 0x274, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DMACK__GPIO6_18          IOMUX_PAD(0x5F4, 0x274, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DMACK__UART1_RXD_MUX     IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, 0)
+#define _MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DMARQ__PATA_DMARQ                IOMUX_PAD(0x5F8, 0x278, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DMARQ__GPIO7_0           IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     IOMUX_PAD(0x5F8, 0x278, 3, 0x880, 2, 0)
+#define _MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0     IOMUX_PAD(0x5F8, 0x278, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN        IOMUX_PAD(0x5FC, 0x27C, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_BUFFER_EN__GPIO7_1               IOMUX_PAD(0x5FC, 0x27C, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, 0)
+#define _MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5     IOMUX_PAD(0x5FC, 0x27C, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_INTRQ__PATA_INTRQ                IOMUX_PAD(0x600, 0x280, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_INTRQ__GPIO7_2           IOMUX_PAD(0x600, 0x280, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_INTRQ__UART2_CTS         IOMUX_PAD(0x600, 0x280, 3, 0x87C, 2, 0)
+#define _MX53_PAD_PATA_INTRQ__CAN1_TXCAN                IOMUX_PAD(0x600, 0x280, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2     IOMUX_PAD(0x600, 0x280, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DIOR__PATA_DIOR          IOMUX_PAD(0x604, 0x284, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DIOR__GPIO7_3                    IOMUX_PAD(0x604, 0x284, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DIOR__UART2_RTS          IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, 0)
+#define _MX53_PAD_PATA_DIOR__CAN1_RXCAN         IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, 0)
+#define _MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7  IOMUX_PAD(0x604, 0x284, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B       IOMUX_PAD(0x608, 0x288, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_RESET_B__GPIO7_4         IOMUX_PAD(0x608, 0x288, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_RESET_B__ESDHC3_CMD              IOMUX_PAD(0x608, 0x288, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_RESET_B__UART1_CTS               IOMUX_PAD(0x608, 0x288, 3, 0x874, 2, 0)
+#define _MX53_PAD_PATA_RESET_B__CAN2_TXCAN              IOMUX_PAD(0x608, 0x288, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0       IOMUX_PAD(0x608, 0x288, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_IORDY__PATA_IORDY                IOMUX_PAD(0x60C, 0x28C, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_IORDY__GPIO7_5           IOMUX_PAD(0x60C, 0x28C, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_IORDY__ESDHC3_CLK                IOMUX_PAD(0x60C, 0x28C, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_IORDY__UART1_RTS         IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, 0)
+#define _MX53_PAD_PATA_IORDY__CAN2_RXCAN                IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, 0)
+#define _MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_0__PATA_DA_0          IOMUX_PAD(0x610, 0x290, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_0__GPIO7_6            IOMUX_PAD(0x610, 0x290, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_0__ESDHC3_RST         IOMUX_PAD(0x610, 0x290, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_0__OWIRE_LINE         IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, 0)
+#define _MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2  IOMUX_PAD(0x610, 0x290, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_1__PATA_DA_1          IOMUX_PAD(0x614, 0x294, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_1__GPIO7_7            IOMUX_PAD(0x614, 0x294, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_1__ESDHC4_CMD         IOMUX_PAD(0x614, 0x294, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_1__UART3_CTS          IOMUX_PAD(0x614, 0x294, 4, 0x884, 4, 0)
+#define _MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3  IOMUX_PAD(0x614, 0x294, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_2__PATA_DA_2          IOMUX_PAD(0x618, 0x298, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_2__GPIO7_8            IOMUX_PAD(0x618, 0x298, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_2__ESDHC4_CLK         IOMUX_PAD(0x618, 0x298, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DA_2__UART3_RTS          IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, 0)
+#define _MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4  IOMUX_PAD(0x618, 0x298, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_CS_0__PATA_CS_0          IOMUX_PAD(0x61C, 0x29C, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_CS_0__GPIO7_9                    IOMUX_PAD(0x61C, 0x29C, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_CS_0__UART3_TXD_MUX              IOMUX_PAD(0x61C, 0x29C, 4, 0x888, 2, 0)
+#define _MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5  IOMUX_PAD(0x61C, 0x29C, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_CS_1__PATA_CS_1          IOMUX_PAD(0x620, 0x2A0, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_CS_1__GPIO7_10           IOMUX_PAD(0x620, 0x2A0, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_CS_1__UART3_RXD_MUX              IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, 0)
+#define _MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6  IOMUX_PAD(0x620, 0x2A0, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA0__PATA_DATA_0               IOMUX_PAD(0x628, 0x2A4, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA0__GPIO2_0           IOMUX_PAD(0x628, 0x2A4, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA0__EMI_NANDF_D_0     IOMUX_PAD(0x628, 0x2A4, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA0__ESDHC3_DAT4               IOMUX_PAD(0x628, 0x2A4, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0     IOMUX_PAD(0x628, 0x2A4, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0    IOMUX_PAD(0x628, 0x2A4, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA1__PATA_DATA_1               IOMUX_PAD(0x62C, 0x2A8, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA1__GPIO2_1           IOMUX_PAD(0x62C, 0x2A8, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA1__EMI_NANDF_D_1     IOMUX_PAD(0x62C, 0x2A8, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA1__ESDHC3_DAT5               IOMUX_PAD(0x62C, 0x2A8, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1     IOMUX_PAD(0x62C, 0x2A8, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1    IOMUX_PAD(0x62C, 0x2A8, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA2__PATA_DATA_2               IOMUX_PAD(0x630, 0x2AC, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA2__GPIO2_2           IOMUX_PAD(0x630, 0x2AC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA2__EMI_NANDF_D_2     IOMUX_PAD(0x630, 0x2AC, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA2__ESDHC3_DAT6               IOMUX_PAD(0x630, 0x2AC, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2     IOMUX_PAD(0x630, 0x2AC, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2    IOMUX_PAD(0x630, 0x2AC, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA3__PATA_DATA_3               IOMUX_PAD(0x634, 0x2B0, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA3__GPIO2_3           IOMUX_PAD(0x634, 0x2B0, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA3__EMI_NANDF_D_3     IOMUX_PAD(0x634, 0x2B0, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA3__ESDHC3_DAT7               IOMUX_PAD(0x634, 0x2B0, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3     IOMUX_PAD(0x634, 0x2B0, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3    IOMUX_PAD(0x634, 0x2B0, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA4__PATA_DATA_4               IOMUX_PAD(0x638, 0x2B4, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA4__GPIO2_4           IOMUX_PAD(0x638, 0x2B4, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA4__EMI_NANDF_D_4     IOMUX_PAD(0x638, 0x2B4, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA4__ESDHC4_DAT4               IOMUX_PAD(0x638, 0x2B4, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4     IOMUX_PAD(0x638, 0x2B4, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4    IOMUX_PAD(0x638, 0x2B4, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA5__PATA_DATA_5       IOMUX_PAD(0x63C, 0x2B8, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA5__GPIO2_5           IOMUX_PAD(0x63C, 0x2B8, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA5__EMI_NANDF_D_5     IOMUX_PAD(0x63C, 0x2B8, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA5__ESDHC4_DAT5               IOMUX_PAD(0x63C, 0x2B8, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5     IOMUX_PAD(0x63C, 0x2B8, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5    IOMUX_PAD(0x63C, 0x2B8, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__PATA_DATA_6       IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__GPIO2_6           IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__EMI_NANDF_D_6     IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__ESDHC4_DAT6               IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6     IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6    IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA7__PATA_DATA_7               IOMUX_PAD(0x644, 0x2C0, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA7__GPIO2_7           IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA7__EMI_NANDF_D_7     IOMUX_PAD(0x644, 0x2C0, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA7__ESDHC4_DAT7               IOMUX_PAD(0x644, 0x2C0, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7     IOMUX_PAD(0x644, 0x2C0, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7    IOMUX_PAD(0x644, 0x2C0, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA8__PATA_DATA_8               IOMUX_PAD(0x648, 0x2C4, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA8__GPIO2_8           IOMUX_PAD(0x648, 0x2C4, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA8__ESDHC1_DAT4               IOMUX_PAD(0x648, 0x2C4, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA8__EMI_NANDF_D_8     IOMUX_PAD(0x648, 0x2C4, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA8__ESDHC3_DAT0               IOMUX_PAD(0x648, 0x2C4, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8     IOMUX_PAD(0x648, 0x2C4, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8    IOMUX_PAD(0x648, 0x2C4, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA9__PATA_DATA_9               IOMUX_PAD(0x64C, 0x2C8, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA9__GPIO2_9           IOMUX_PAD(0x64C, 0x2C8, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA9__ESDHC1_DAT5               IOMUX_PAD(0x64C, 0x2C8, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA9__EMI_NANDF_D_9     IOMUX_PAD(0x64C, 0x2C8, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA9__ESDHC3_DAT1               IOMUX_PAD(0x64C, 0x2C8, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9     IOMUX_PAD(0x64C, 0x2C8, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9    IOMUX_PAD(0x64C, 0x2C8, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA10__PATA_DATA_10     IOMUX_PAD(0x650, 0x2CC, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA10__GPIO2_10         IOMUX_PAD(0x650, 0x2CC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA10__ESDHC1_DAT6              IOMUX_PAD(0x650, 0x2CC, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA10__EMI_NANDF_D_10   IOMUX_PAD(0x650, 0x2CC, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA10__ESDHC3_DAT2              IOMUX_PAD(0x650, 0x2CC, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10   IOMUX_PAD(0x650, 0x2CC, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10  IOMUX_PAD(0x650, 0x2CC, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA11__PATA_DATA_11     IOMUX_PAD(0x654, 0x2D0, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA11__GPIO2_11         IOMUX_PAD(0x654, 0x2D0, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA11__ESDHC1_DAT7              IOMUX_PAD(0x654, 0x2D0, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA11__EMI_NANDF_D_11   IOMUX_PAD(0x654, 0x2D0, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA11__ESDHC3_DAT3              IOMUX_PAD(0x654, 0x2D0, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11   IOMUX_PAD(0x654, 0x2D0, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11  IOMUX_PAD(0x654, 0x2D0, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA12__PATA_DATA_12     IOMUX_PAD(0x658, 0x2D4, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA12__GPIO2_12         IOMUX_PAD(0x658, 0x2D4, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA12__ESDHC2_DAT4              IOMUX_PAD(0x658, 0x2D4, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA12__EMI_NANDF_D_12   IOMUX_PAD(0x658, 0x2D4, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA12__ESDHC4_DAT0              IOMUX_PAD(0x658, 0x2D4, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12   IOMUX_PAD(0x658, 0x2D4, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12  IOMUX_PAD(0x658, 0x2D4, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA13__PATA_DATA_13     IOMUX_PAD(0x65C, 0x2D8, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA13__GPIO2_13         IOMUX_PAD(0x65C, 0x2D8, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA13__ESDHC2_DAT5              IOMUX_PAD(0x65C, 0x2D8, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA13__EMI_NANDF_D_13   IOMUX_PAD(0x65C, 0x2D8, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA13__ESDHC4_DAT1              IOMUX_PAD(0x65C, 0x2D8, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13   IOMUX_PAD(0x65C, 0x2D8, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13  IOMUX_PAD(0x65C, 0x2D8, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA14__PATA_DATA_14     IOMUX_PAD(0x660, 0x2DC, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA14__GPIO2_14         IOMUX_PAD(0x660, 0x2DC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA14__ESDHC2_DAT6              IOMUX_PAD(0x660, 0x2DC, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA14__EMI_NANDF_D_14   IOMUX_PAD(0x660, 0x2DC, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA14__ESDHC4_DAT2              IOMUX_PAD(0x660, 0x2DC, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14   IOMUX_PAD(0x660, 0x2DC, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14  IOMUX_PAD(0x660, 0x2DC, 6, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA15__PATA_DATA_15     IOMUX_PAD(0x664, 0x2E0, 0, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA15__GPIO2_15         IOMUX_PAD(0x664, 0x2E0, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA15__ESDHC2_DAT7              IOMUX_PAD(0x664, 0x2E0, 2, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA15__EMI_NANDF_D_15   IOMUX_PAD(0x664, 0x2E0, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA15__ESDHC4_DAT3              IOMUX_PAD(0x664, 0x2E0, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15   IOMUX_PAD(0x664, 0x2E0, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15  IOMUX_PAD(0x664, 0x2E0, 6, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA0__ESDHC1_DAT0        IOMUX_PAD(0x66C, 0x2E4, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA0__GPIO1_16   IOMUX_PAD(0x66C, 0x2E4, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA0__CSPI_MISO  IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, 0)
+#define _MX53_PAD_SD1_DATA0__CCM_PLL3_BYP       IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, 0)
+#define _MX53_PAD_SD1_DATA1__ESDHC1_DAT1        IOMUX_PAD(0x670, 0x2E8, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA1__GPIO1_17   IOMUX_PAD(0x670, 0x2E8, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA1__CSPI_SS0   IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, 0)
+#define _MX53_PAD_SD1_DATA1__CCM_PLL4_BYP       IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, 0)
+#define _MX53_PAD_SD1_CMD__ESDHC1_CMD   IOMUX_PAD(0x674, 0x2EC, IOMUX_CONFIG_SION, 0x0, 0, 0)
+#define _MX53_PAD_SD1_CMD__GPIO1_18             IOMUX_PAD(0x674, 0x2EC, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD1_CMD__GPT_CMPOUT1  IOMUX_PAD(0x674, 0x2EC, 3, 0x0, 0, 0)
+#define _MX53_PAD_SD1_CMD__CSPI_MOSI            IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, 0)
+#define _MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, 0)
+#define _MX53_PAD_SD1_DATA2__ESDHC1_DAT2                IOMUX_PAD(0x678, 0x2F0, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA2__GPIO1_19           IOMUX_PAD(0x678, 0x2F0, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA2__GPT_CMPOUT2                IOMUX_PAD(0x678, 0x2F0, 2, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA2__PWM2_PWMO          IOMUX_PAD(0x678, 0x2F0, 3, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_B               IOMUX_PAD(0x678, 0x2F0, 4, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA2__CSPI_SS1           IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, 0)
+#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB       IOMUX_PAD(0x678, 0x2F0, 6, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA2__CCM_PLL2_BYP               IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, 0)
+#define _MX53_PAD_SD1_CLK__ESDHC1_CLK   IOMUX_PAD(0x67C, 0x2F4, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD1_CLK__GPIO1_20             IOMUX_PAD(0x67C, 0x2F4, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD1_CLK__OSC32k_32K_OUT       IOMUX_PAD(0x67C, 0x2F4, 2, 0x0, 0, 0)
+#define _MX53_PAD_SD1_CLK__GPT_CLKIN            IOMUX_PAD(0x67C, 0x2F4, 3, 0x0, 0, 0)
+#define _MX53_PAD_SD1_CLK__CSPI_SCLK            IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, 0)
+#define _MX53_PAD_SD1_CLK__SATA_PHY_DTB_0       IOMUX_PAD(0x67C, 0x2F4, 7, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA3__ESDHC1_DAT3        IOMUX_PAD(0x680, 0x2F8, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA3__GPIO1_21   IOMUX_PAD(0x680, 0x2F8, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA3__GPT_CMPOUT3        IOMUX_PAD(0x680, 0x2F8, 2, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA3__PWM1_PWMO  IOMUX_PAD(0x680, 0x2F8, 3, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_B       IOMUX_PAD(0x680, 0x2F8, 4, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA3__CSPI_SS2   IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, 0)
+#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB       IOMUX_PAD(0x680, 0x2F8, 6, 0x0, 0, 0)
+#define _MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1     IOMUX_PAD(0x680, 0x2F8, 7, 0x0, 0, 0)
+#define _MX53_PAD_SD2_CLK__ESDHC2_CLK   IOMUX_PAD(0x688, 0x2FC, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD2_CLK__GPIO1_10             IOMUX_PAD(0x688, 0x2FC, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD2_CLK__KPP_COL_5            IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, 0)
+#define _MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS     IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, 0)
+#define _MX53_PAD_SD2_CLK__CSPI_SCLK            IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, 0)
+#define _MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, 0x0, 0, 0)
+#define _MX53_PAD_SD2_CMD__ESDHC2_CMD   IOMUX_PAD(0x68C, 0x300, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD2_CMD__GPIO1_11             IOMUX_PAD(0x68C, 0x300, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD2_CMD__KPP_ROW_5    IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, 0)
+#define _MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC      IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, 0)
+#define _MX53_PAD_SD2_CMD__CSPI_MOSI            IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, 0)
+#define _MX53_PAD_SD2_CMD__SCC_RANDOM   IOMUX_PAD(0x68C, 0x300, 7, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA3__ESDHC2_DAT3        IOMUX_PAD(0x690, 0x304, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA3__GPIO1_12   IOMUX_PAD(0x690, 0x304, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA3__KPP_COL_6  IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, 0)
+#define _MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC    IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, 0)
+#define _MX53_PAD_SD2_DATA3__CSPI_SS2   IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, 0)
+#define _MX53_PAD_SD2_DATA3__SJC_DONE   IOMUX_PAD(0x690, 0x304, 7, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA2__ESDHC2_DAT2        IOMUX_PAD(0x694, 0x308, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA2__GPIO1_13   IOMUX_PAD(0x694, 0x308, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA2__KPP_ROW_6  IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, 0)
+#define _MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD    IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, 0)
+#define _MX53_PAD_SD2_DATA2__CSPI_SS1   IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, 0)
+#define _MX53_PAD_SD2_DATA2__SJC_FAIL   IOMUX_PAD(0x694, 0x308, 7, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA1__ESDHC2_DAT1        IOMUX_PAD(0x698, 0x30C, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA1__GPIO1_14   IOMUX_PAD(0x698, 0x30C, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA1__KPP_COL_7  IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, 0)
+#define _MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS   IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, 0)
+#define _MX53_PAD_SD2_DATA1__CSPI_SS0   IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, 0)
+#define _MX53_PAD_SD2_DATA1__RTIC_SEC_VIO       IOMUX_PAD(0x698, 0x30C, 7, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA0__ESDHC2_DAT0        IOMUX_PAD(0x69C, 0x310, 0, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA0__GPIO1_15   IOMUX_PAD(0x69C, 0x310, 1, 0x0, 0, 0)
+#define _MX53_PAD_SD2_DATA0__KPP_ROW_7  IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, 0)
+#define _MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD    IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, 0)
+#define _MX53_PAD_SD2_DATA0__CSPI_MISO  IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, 0)
+#define _MX53_PAD_SD2_DATA0__RTIC_DONE_INT      IOMUX_PAD(0x69C, 0x310, 7, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_0__CCM_CLKO              IOMUX_PAD(0x6A4, 0x314, 0, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_0__GPIO1_0               IOMUX_PAD(0x6A4, 0x314, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_0__KPP_COL_5             IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, 0)
+#define _MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK      IOMUX_PAD(0x6A4, 0x314, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_0__EPIT1_EPITO   IOMUX_PAD(0x6A4, 0x314, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_0__SRTC_ALARM_DEB        IOMUX_PAD(0x6A4, 0x314, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_0__USBOH3_USBH1_PWR      IOMUX_PAD(0x6A4, 0x314, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_0__CSU_TD                IOMUX_PAD(0x6A4, 0x314, 7, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_1__ESAI1_SCKR            IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, 0)
+#define _MX53_PAD_GPIO_1__GPIO1_1               IOMUX_PAD(0x6A8, 0x318, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_1__KPP_ROW_5             IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, 0)
+#define _MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK      IOMUX_PAD(0x6A8, 0x318, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_1__PWM2_PWMO     IOMUX_PAD(0x6A8, 0x318, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_1__WDOG2_WDOG_B  IOMUX_PAD(0x6A8, 0x318, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_1__ESDHC1_CD             IOMUX_PAD(0x6A8, 0x318, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_1__SRC_TESTER_ACK        IOMUX_PAD(0x6A8, 0x318, 7, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_9__ESAI1_FSR             IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, 0)
+#define _MX53_PAD_GPIO_9__GPIO1_9               IOMUX_PAD(0x6AC, 0x31C, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_9__KPP_COL_6             IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, 0)
+#define _MX53_PAD_GPIO_9__CCM_REF_EN_B  IOMUX_PAD(0x6AC, 0x31C, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_9__PWM1_PWMO     IOMUX_PAD(0x6AC, 0x31C, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_9__WDOG1_WDOG_B  IOMUX_PAD(0x6AC, 0x31C, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_9__ESDHC1_WP             IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, 0)
+#define _MX53_PAD_GPIO_9__SCC_FAIL_STATE        IOMUX_PAD(0x6AC, 0x31C, 7, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_3__ESAI1_HCKR            IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, 0)
+#define _MX53_PAD_GPIO_3__GPIO1_3               IOMUX_PAD(0x6B0, 0x320, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_3__I2C3_SCL              IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, 0)
+#define _MX53_PAD_GPIO_3__DPLLIP1_TOG_EN        IOMUX_PAD(0x6B0, 0x320, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_3__CCM_CLKO2             IOMUX_PAD(0x6B0, 0x320, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0    IOMUX_PAD(0x6B0, 0x320, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_3__USBOH3_USBH1_OC       IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, 0)
+#define _MX53_PAD_GPIO_3__MLB_MLBCLK            IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, 0)
+#define _MX53_PAD_GPIO_6__ESAI1_SCKT            IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, 0)
+#define _MX53_PAD_GPIO_6__GPIO1_6               IOMUX_PAD(0x6B4, 0x324, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_6__I2C3_SDA              IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, 0)
+#define _MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_6__CSU_CSU_INT_DEB       IOMUX_PAD(0x6B4, 0x324, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1    IOMUX_PAD(0x6B4, 0x324, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_6__ESDHC2_LCTL   IOMUX_PAD(0x6B4, 0x324, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_6__MLB_MLBSIG            IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, 0)
+#define _MX53_PAD_GPIO_2__ESAI1_FST             IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, 0)
+#define _MX53_PAD_GPIO_2__GPIO1_2               IOMUX_PAD(0x6B8, 0x328, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_2__KPP_ROW_6             IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, 0)
+#define _MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0   IOMUX_PAD(0x6B8, 0x328, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2    IOMUX_PAD(0x6B8, 0x328, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_2__ESDHC2_WP             IOMUX_PAD(0x6B8, 0x328, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_2__MLB_MLBDAT    IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, 0)
+#define _MX53_PAD_GPIO_4__ESAI1_HCKT            IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, 0)
+#define _MX53_PAD_GPIO_4__GPIO1_4               IOMUX_PAD(0x6BC, 0x32C, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_4__KPP_COL_7             IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, 0)
+#define _MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1   IOMUX_PAD(0x6BC, 0x32C, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3    IOMUX_PAD(0x6BC, 0x32C, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_4__ESDHC2_CD             IOMUX_PAD(0x6BC, 0x32C, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, 0)
+#define _MX53_PAD_GPIO_5__GPIO1_5               IOMUX_PAD(0x6C0, 0x330, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_5__KPP_ROW_7             IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, 0)
+#define _MX53_PAD_GPIO_5__CCM_CLKO              IOMUX_PAD(0x6C0, 0x330, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2   IOMUX_PAD(0x6C0, 0x330, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4    IOMUX_PAD(0x6C0, 0x330, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_5__I2C3_SCL              IOMUX_PAD(0x6C0, 0x330, 6, 0x824, 2, 0)
+#define _MX53_PAD_GPIO_5__CCM_PLL1_BYP  IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, 0)
+#define _MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, 0)
+#define _MX53_PAD_GPIO_7__GPIO1_7               IOMUX_PAD(0x6C4, 0x334, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_7__EPIT1_EPITO   IOMUX_PAD(0x6C4, 0x334, 2, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_7__CAN1_TXCAN    IOMUX_PAD(0x6C4, 0x334, 3, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, 0x880, 4, 0)
+#define _MX53_PAD_GPIO_7__FIRI_RXD              IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, 0)
+#define _MX53_PAD_GPIO_7__SPDIF_PLOCK   IOMUX_PAD(0x6C4, 0x334, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_7__CCM_PLL2_BYP  IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, 0)
+#define _MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, 0)
+#define _MX53_PAD_GPIO_8__GPIO1_8               IOMUX_PAD(0x6C8, 0x338, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_8__EPIT2_EPITO   IOMUX_PAD(0x6C8, 0x338, 2, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_8__CAN1_RXCAN    IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, 0)
+#define _MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, 0)
+#define _MX53_PAD_GPIO_8__FIRI_TXD              IOMUX_PAD(0x6C8, 0x338, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_8__SPDIF_SRCLK   IOMUX_PAD(0x6C8, 0x338, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_8__CCM_PLL3_BYP  IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, 0)
+#define _MX53_PAD_GPIO_16__ESAI1_TX3_RX2        IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, 0)
+#define _MX53_PAD_GPIO_16__GPIO7_11             IOMUX_PAD(0x6CC, 0x33C, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT     IOMUX_PAD(0x6CC, 0x33C, 2, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_16__SPDIF_IN1            IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, 0)
+#define _MX53_PAD_GPIO_16__I2C3_SDA             IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, 0)
+#define _MX53_PAD_GPIO_16__SJC_DE_B             IOMUX_PAD(0x6CC, 0x33C, 7, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_17__ESAI1_TX0            IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, 0)
+#define _MX53_PAD_GPIO_17__GPIO7_12             IOMUX_PAD(0x6D0, 0x340, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0     IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, 0)
+#define _MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, 0)
+#define _MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG  IOMUX_PAD(0x6D0, 0x340, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_17__SPDIF_OUT1   IOMUX_PAD(0x6D0, 0x340, 5, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_17__IPU_SNOOP2   IOMUX_PAD(0x6D0, 0x340, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_18__ESAI1_TX1            IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, 0)
+#define _MX53_PAD_GPIO_18__GPIO7_13             IOMUX_PAD(0x6D4, 0x344, 1, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1     IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, 0)
+#define _MX53_PAD_GPIO_18__OWIRE_LINE   IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, 0)
+#define _MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG       IOMUX_PAD(0x6D4, 0x344, 4, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK     IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, 0)
+#define _MX53_PAD_GPIO_18__ESDHC1_LCTL  IOMUX_PAD(0x6D4, 0x344, 6, 0x0, 0, 0)
+#define _MX53_PAD_GPIO_18__SRC_SYSTEM_RST       IOMUX_PAD(0x6D4, 0x344, 7, 0x0, 0, 0)
 
-#define MX53_PAD_GPIO_19__GPIO_4_5              IOMUX_PAD(0x348, 0x20,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__GPIO_4_6             IOMUX_PAD(0x34C, 0x24,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__GPIO_4_7             IOMUX_PAD(0x350, 0x28,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__GPIO_4_8             IOMUX_PAD(0x354, 0x2C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__GPIO_4_9             IOMUX_PAD(0x358, 0x30,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__GPIO_4_10            IOMUX_PAD(0x35C, 0x34,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__GPIO_4_11    IOMUX_PAD(0x360, 0x38,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__GPIO_4_12            IOMUX_PAD(0x364, 0x3C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__GPIO_4_13    IOMUX_PAD(0x368, 0x40,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__GPIO_4_14            IOMUX_PAD(0x36C, 0x44,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__GPIO_4_15    IOMUX_PAD(0x370, 0x48,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NVCC_KEYPAD__NVCC_KEYPAD       IOMUX_PAD(0x374, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__GPIO_4_16        IOMUX_PAD(0x378, 0x4C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__GPIO_4_17   IOMUX_PAD(0x37C, 0x50,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__GPIO_4_18            IOMUX_PAD(0x380, 0x54,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__GPIO_4_19            IOMUX_PAD(0x384, 0x58,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__GPIO_4_20            IOMUX_PAD(0x388, 0x5C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__GPIO_4_21  IOMUX_PAD(0x38C, 0x60,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__GPIO_4_22  IOMUX_PAD(0x390, 0x64,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__GPIO_4_23  IOMUX_PAD(0x394, 0x68,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__GPIO_4_24  IOMUX_PAD(0x398, 0x6C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__GPIO_4_25  IOMUX_PAD(0x39C, 0x70,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__GPIO_4_26  IOMUX_PAD(0x3A0, 0x74,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__GPIO_4_27  IOMUX_PAD(0x3A4, 0x78,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__GPIO_4_28  IOMUX_PAD(0x3A8, 0x7C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__GPIO_4_29  IOMUX_PAD(0x3AC, 0x80,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__GPIO_4_30  IOMUX_PAD(0x3B0, 0x84,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x3B4, 0x88,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__GPIO_5_5  IOMUX_PAD(0x3B8, 0x8C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__GPIO_5_6  IOMUX_PAD(0x3BC, 0x90,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__GPIO_5_7  IOMUX_PAD(0x3C0, 0x94,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__GPIO_5_8  IOMUX_PAD(0x3C4, 0x98,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__GPIO_5_9  IOMUX_PAD(0x3C8, 0x9C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x3CC, 0xA0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x3D0, 0xA4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x3D4, 0xA8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x3D8, 0xAC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x3DC, 0xB0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x3E0, 0xB4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x3E4, 0xB8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x3E8, 0xBC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x3EC, 0xC0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__GPIO_5_19   IOMUX_PAD(0x3F0, 0xC4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__GPIO_5_20        IOMUX_PAD(0x3F4, 0xC8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__GPIO_5_21  IOMUX_PAD(0x3F8, 0xCC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_D4__GPIO_5_22             IOMUX_PAD(0x3FC, 0xD0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_D5__GPIO_5_23             IOMUX_PAD(0x400, 0xD4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_D6__GPIO_5_24             IOMUX_PAD(0x404, 0xD8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_D7__GPIO_5_25             IOMUX_PAD(0x408, 0xDC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_D8__GPIO_5_26             IOMUX_PAD(0x40C, 0xE0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_D9__GPIO_5_27             IOMUX_PAD(0x410, 0xE4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_D10__GPIO_5_28            IOMUX_PAD(0x414, 0xE8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_D11__GPIO_5_29            IOMUX_PAD(0x418, 0xEC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_D12__GPIO_5_30            IOMUX_PAD(0x41C, 0xF0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_D13__GPIO_5_31            IOMUX_PAD(0x420, 0xF4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_D14__GPIO_6_0             IOMUX_PAD(0x424, 0xF8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_D15__GPIO_6_1             IOMUX_PAD(0x428, 0xFC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_D16__GPIO_6_2             IOMUX_PAD(0x42C, 0x100,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_D17__GPIO_6_3             IOMUX_PAD(0x430, 0x104,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_D18__GPIO_6_4             IOMUX_PAD(0x434, 0x108,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_D19__GPIO_6_5             IOMUX_PAD(0x438, 0x10C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NVCC_CSI0__NVCC_CSI0   IOMUX_PAD(0x43C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_JTAG_TMS__JTAG_TMS             IOMUX_PAD(0x440, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_JTAG_MOD__JTAG_MOD             IOMUX_PAD(0x444, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_JTAG_TRSTB__JTAG_TRSTB IOMUX_PAD(0x448, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_JTAG_TDI__JTAG_TDI             IOMUX_PAD(0x44C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_JTAG_TCK__JTAG_TCK             IOMUX_PAD(0x450, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_JTAG_TDO__JTAG_TDO             IOMUX_PAD(0x454, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__GPIO_5_2              IOMUX_PAD(0x458, 0x110,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__GPIO_2_30             IOMUX_PAD(0x45C, 0x114,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__GPIO_3_16             IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__GPIO_3_17             IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__GPIO_3_18             IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__CSPI1_SCLK            IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT4, 0x79c, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__CSPI1_MISO            IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT4, 0x7a0, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__CSPI1_MOSI            IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT4, 0x7a4, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__GPIO_3_19             IOMUX_PAD(0x46C, 0x124,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__GPIO_3_20             IOMUX_PAD(0x470, 0x128,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__GPIO_3_21             IOMUX_PAD(0x474, 0x12C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__GPIO_3_22             IOMUX_PAD(0x478, 0x130,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__GPIO_3_23             IOMUX_PAD(0x47C, 0x134,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__GPIO_2_31             IOMUX_PAD(0x480, 0x138,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__GPIO_3_24             IOMUX_PAD(0x484, 0x13C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__GPIO_3_25             IOMUX_PAD(0x488, 0x140,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__GPIO_3_26             IOMUX_PAD(0x48C, 0x144,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__GPIO_3_27             IOMUX_PAD(0x490, 0x148,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__GPIO_3_28             IOMUX_PAD(0x494, 0x14C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__GPIO_3_29             IOMUX_PAD(0x498, 0x150,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__GPIO_3_30             IOMUX_PAD(0x49C, 0x154,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__GPIO_3_31             IOMUX_PAD(0x4A0, 0x158,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NVCC_EIM1__NVCC_EIM1   IOMUX_PAD(0x4A4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__GPIO_5_4              IOMUX_PAD(0x4A8, 0x15C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__GPIO_6_6              IOMUX_PAD(0x4AC, 0x160,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__GPIO_2_16             IOMUX_PAD(0x4B0, 0x164,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__GPIO_2_17             IOMUX_PAD(0x4B4, 0x168,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__GPIO_2_18             IOMUX_PAD(0x4B8, 0x16C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__GPIO_2_19             IOMUX_PAD(0x4BC, 0x170,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__GPIO_2_20             IOMUX_PAD(0x4C0, 0x174,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__GPIO_2_21             IOMUX_PAD(0x4C4, 0x178,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__GPIO_2_22             IOMUX_PAD(0x4C8, 0x17C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__GPIO_2_23             IOMUX_PAD(0x4CC, 0x180,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__GPIO_2_24             IOMUX_PAD(0x4D0, 0x184,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__GPIO_2_25              IOMUX_PAD(0x4D4, 0x188,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__GPIO_2_26              IOMUX_PAD(0x4D8, 0x18C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__GPIO_2_27             IOMUX_PAD(0x4DC, 0x190,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NVCC_EIM4__NVCC_EIM4   IOMUX_PAD(0x4E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__GPIO_2_28             IOMUX_PAD(0x4E4, 0x194,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__GPIO_2_29             IOMUX_PAD(0x4E8, 0x198,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__GPIO_3_0              IOMUX_PAD(0x4EC, 0x19C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__GPIO_3_1              IOMUX_PAD(0x4F0, 0x1A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__GPIO_3_2              IOMUX_PAD(0x4F4, 0x1A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__GPIO_3_3              IOMUX_PAD(0x4F8, 0x1A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__GPIO_3_4              IOMUX_PAD(0x4FC, 0x1AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__GPIO_3_5              IOMUX_PAD(0x500, 0x1B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__GPIO_3_6              IOMUX_PAD(0x504, 0x1B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__GPIO_3_7              IOMUX_PAD(0x508, 0x1B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__GPIO_3_8              IOMUX_PAD(0x50C, 0x1BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__GPIO_3_9              IOMUX_PAD(0x510, 0x1C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__GPIO_3_10            IOMUX_PAD(0x514, 0x1C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__GPIO_3_11            IOMUX_PAD(0x518, 0x1C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__GPIO_3_12            IOMUX_PAD(0x51C, 0x1CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__GPIO_3_13            IOMUX_PAD(0x520, 0x1D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__GPIO_3_14            IOMUX_PAD(0x524, 0x1D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__GPIO_3_15            IOMUX_PAD(0x528, 0x1D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WE_B__GPIO_6_12  IOMUX_PAD(0x52C, 0x1DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RE_B__GPIO_6_13  IOMUX_PAD(0x530, 0x1E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__GPIO_5_0             IOMUX_PAD(0x534, 0x1E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_BCLK__EIM_BCLK             IOMUX_PAD(0x538, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NVCC_EIM7__NVCC_EIM7   IOMUX_PAD(0x53C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX3_P__GPIO_6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX2_P__GPIO_6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_CLK_P__GPIO_6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX1_P__GPIO_6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX0_P__GPIO_6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX3_P__GPIO_7_22 IOMUX_PAD(NON_PAD_I, 0x200, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_CLK_P__GPIO_7_24 IOMUX_PAD(NON_PAD_I, 0x204, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX2_P__GPIO_7_26 IOMUX_PAD(NON_PAD_I, 0x208, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX1_P__GPIO_7_28 IOMUX_PAD(NON_PAD_I, 0x20C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX0_P__GPIO_7_30 IOMUX_PAD(NON_PAD_I, 0x210, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_10__GPIO_4_0              IOMUX_PAD(0x540, 0x214, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_11__GPIO_4_1              IOMUX_PAD(0x544, 0x218, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_12__GPIO_4_2              IOMUX_PAD(0x548, 0x21C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_13__GPIO_4_3              IOMUX_PAD(0x54C, 0x220, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_14__GPIO_4_4              IOMUX_PAD(0x550, 0x224, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_DQM3__DRAM_DQM3   IOMUX_PAD(0x554, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_SDQS3__DRAM_SDQS3 IOMUX_PAD(0x558, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_SDCKE1__DRAM_SDCKE1       IOMUX_PAD(0x55C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_DQM2__DRAM_DQM2   IOMUX_PAD(0x560, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_SDODT1__DRAM_SDODT1       IOMUX_PAD(0x564, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_SDQS2__DRAM_SDQS2 IOMUX_PAD(0x568, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_RESET__DRAM_RESET IOMUX_PAD(0x56C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_SDCLK1__DRAM_SDCLK1       IOMUX_PAD(0x570, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_CAS__DRAM_CAS             IOMUX_PAD(0x574, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_SDCLK0__DRAM_SDCLK0       IOMUX_PAD(0x578, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_SDQS0__DRAM_SDQS0 IOMUX_PAD(0x57C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_SDODT0__DRAM_SDODT0       IOMUX_PAD(0x580, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_DQM0__DRAM_DQM0   IOMUX_PAD(0x584, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_RAS__DRAM_RAS             IOMUX_PAD(0x588, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_SDCKE0__DRAM_SDCKE0       IOMUX_PAD(0x58C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_SDQS1__DRAM_SDQS1 IOMUX_PAD(0x590, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DRAM_DQM1__DRAM_DQM1   IOMUX_PAD(0x594, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_PMIC_ON_REQ__PMIC_ON_REQ       IOMUX_PAD(0x598, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ   IOMUX_PAD(0x59C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__GPIO_6_7            IOMUX_PAD(0x5A0, 0x228,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__GPIO_6_8    IOMUX_PAD(0x5A4, 0x22C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__GPIO_6_9   IOMUX_PAD(0x5A8, 0x230,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__GPIO_6_10   IOMUX_PAD(0x5AC, 0x234,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__GPIO_6_11   IOMUX_PAD(0x5B0, 0x238,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__GPIO_6_14   IOMUX_PAD(0x5B4, 0x23C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__GPIO_6_15   IOMUX_PAD(0x5B8, 0x240,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__GPIO_6_16   IOMUX_PAD(0x5BC, 0x244,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NVCC_NANDF__NVCC_NANDF IOMUX_PAD(0x5C0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__GPIO_1_22            IOMUX_PAD(0x5C4, 0x248,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__GPIO_1_23 IOMUX_PAD(0x5C8, 0x24C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__GPIO_1_24   IOMUX_PAD(0x5CC, 0x250,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__GPIO_1_25  IOMUX_PAD(0x5D0, 0x254,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__GPIO_1_26            IOMUX_PAD(0x5D4, 0x258,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__GPIO_1_27            IOMUX_PAD(0x5D8, 0x25C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__GPIO_1_28   IOMUX_PAD(0x5DC, 0x260,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__GPIO_1_29            IOMUX_PAD(0x5E0, 0x264,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__GPIO_1_30            IOMUX_PAD(0x5E4, 0x268,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__GPIO_1_31             IOMUX_PAD(0x5E8, 0x26C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NVCC_FEC__NVCC_FEC             IOMUX_PAD(0x5EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DIOW__GPIO_6_17    IOMUX_PAD(0x5F0, 0x270,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DMACK__GPIO_6_18   IOMUX_PAD(0x5F4, 0x274,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DMARQ__GPIO_7_0    IOMUX_PAD(0x5F8, 0x278,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_BUFFER_EN__GPIO_7_1        IOMUX_PAD(0x5FC, 0x27C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_INTRQ__GPIO_7_2            IOMUX_PAD(0x600, 0x280,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DIOR__GPIO_7_3             IOMUX_PAD(0x604, 0x284,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_RESET_B__GPIO_7_4  IOMUX_PAD(0x608, 0x288,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_IORDY__GPIO_7_5            IOMUX_PAD(0x60C, 0x28C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DA_0__GPIO_7_6             IOMUX_PAD(0x610, 0x290,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DA_1__GPIO_7_7             IOMUX_PAD(0x614, 0x294,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DA_2__GPIO_7_8             IOMUX_PAD(0x618, 0x298,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_CS_0__GPIO_7_9             IOMUX_PAD(0x61C, 0x29C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_CS_1__GPIO_7_10            IOMUX_PAD(0x620, 0x2A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NVCC_ATA2__NVCC_ATA2   IOMUX_PAD(0x624, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DATA0__GPIO_2_0    IOMUX_PAD(0x628, 0x2A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DATA1__GPIO_2_1    IOMUX_PAD(0x62C, 0x2A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DATA2__GPIO_2_2    IOMUX_PAD(0x630, 0x2AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DATA3__GPIO_2_3    IOMUX_PAD(0x634, 0x2B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DATA4__GPIO_2_4    IOMUX_PAD(0x638, 0x2B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DATA5__GPIO_2_5    IOMUX_PAD(0x63C, 0x2B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DATA6__GPIO_2_6    IOMUX_PAD(0x640, 0x2BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DATA7__GPIO_2_7    IOMUX_PAD(0x644, 0x2C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DATA8__GPIO_2_8    IOMUX_PAD(0x648, 0x2C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DATA9__GPIO_2_9    IOMUX_PAD(0x64C, 0x2C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DATA10__GPIO_2_10  IOMUX_PAD(0x650, 0x2CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DATA11__GPIO_2_11  IOMUX_PAD(0x654, 0x2D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DATA12__GPIO_2_12  IOMUX_PAD(0x658, 0x2D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DATA13__GPIO_2_13  IOMUX_PAD(0x65C, 0x2D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DATA14__GPIO_2_14  IOMUX_PAD(0x660, 0x2DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_ATA_DATA15__GPIO_2_15  IOMUX_PAD(0x664, 0x2E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NVCC_ATA0__NVCC_ATA0   IOMUX_PAD(0x668, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__GPIO_1_16   IOMUX_PAD(0x66C, 0x2E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__GPIO_1_17   IOMUX_PAD(0x670, 0x2E8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__GPIO_1_18             IOMUX_PAD(0x674, 0x2EC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__GPIO_1_19   IOMUX_PAD(0x678, 0x2F0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__GPIO_1_20             IOMUX_PAD(0x67C, 0x2F4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__GPIO_1_21   IOMUX_PAD(0x680, 0x2F8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NVCC_SD1__NVCC_SD1             IOMUX_PAD(0x684, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__GPIO_1_10             IOMUX_PAD(0x688, 0x2FC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__GPIO_1_11             IOMUX_PAD(0x68C, 0x300,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__GPIO_1_12   IOMUX_PAD(0x690, 0x304,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__GPIO_1_13   IOMUX_PAD(0x694, 0x308,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__GPIO_1_14   IOMUX_PAD(0x698, 0x30C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__GPIO_1_15   IOMUX_PAD(0x69C, 0x310,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NVCC_SD2__NVCC_SD2             IOMUX_PAD(0x6A0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__GPIO_1_0               IOMUX_PAD(0x6A4, 0x314,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__GPIO_1_1               IOMUX_PAD(0x6A8, 0x318,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__GPIO_1_9               IOMUX_PAD(0x6AC, 0x31C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__GPIO_1_3               IOMUX_PAD(0x6B0, 0x320,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__GPIO_1_6               IOMUX_PAD(0x6B4, 0x324,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__GPIO_1_2               IOMUX_PAD(0x6B8, 0x328,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__GPIO_1_4               IOMUX_PAD(0x6BC, 0x32C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__GPIO_1_5               IOMUX_PAD(0x6C0, 0x330,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__GPIO_1_7               IOMUX_PAD(0x6C4, 0x334,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__GPIO_1_8               IOMUX_PAD(0x6C8, 0x338,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__GPIO_7_11             IOMUX_PAD(0x6CC, 0x33C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__GPIO_7_12             IOMUX_PAD(0x6D0, 0x340,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__GPIO_7_13             IOMUX_PAD(0x6D4, 0x344,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_NVCC_GPIO__NVCC_GPIO   IOMUX_PAD(0x6D8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_POR_B__POR_B                   IOMUX_PAD(0x6DC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x6E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_RESET_IN_B__RESET_IN_B IOMUX_PAD(0x6E4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x6E8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_TEST_MODE__TEST_MODE   IOMUX_PAD(0x6EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GRP_ADDDS__GRP_ADDDS   IOMUX_PAD(0x6F0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GRP_DDRMODE_CTL__GRP_DDRMODE_CTL       IOMUX_PAD(0x6F4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GRP_DDRPKE__GRP_DDRPKE IOMUX_PAD(0x6FC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GRP_DDRPK__GRP_DDRPK   IOMUX_PAD(0x708, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GRP_TERM_CTL3__GRP_TERM_CTL3   IOMUX_PAD(0x70C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GRP_DDRHYS__GRP_DDRHYS IOMUX_PAD(0x710, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GRP_DDRMODE__GRP_DDRMODE       IOMUX_PAD(0x714, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GRP_B0DS__GRP_B0DS             IOMUX_PAD(0x718, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GRP_B1DS__GRP_B1DS             IOMUX_PAD(0x71C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GRP_CTLDS__GRP_CTLDS   IOMUX_PAD(0x720, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GRP_DDR_TYPE__GRP_DDR_TYPE     IOMUX_PAD(0x724, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GRP_B2DS__GRP_B2DS             IOMUX_PAD(0x728, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_GRP_B3DS__GRP_B3DS             IOMUX_PAD(0x72C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__KPP_COL_5             (_MX53_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_19__GPIO4_5               (_MX53_PAD_GPIO_19__GPIO4_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_19__CCM_CLKO              (_MX53_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_19__SPDIF_OUT1            (_MX53_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2          (_MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_19__ECSPI1_RDY            (_MX53_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_19__FEC_TDATA_3           (_MX53_PAD_GPIO_19__FEC_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_19__SRC_INT_BOOT          (_MX53_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL0__KPP_COL_0            (_MX53_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL0__GPIO4_6              (_MX53_PAD_KEY_COL0__GPIO4_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC              (_MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL0__UART4_TXD_MUX                (_MX53_PAD_KEY_COL0__UART4_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL0__ECSPI1_SCLK          (_MX53_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL0__FEC_RDATA_3          (_MX53_PAD_KEY_COL0__FEC_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST               (_MX53_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW0__KPP_ROW_0            (_MX53_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW0__GPIO4_7              (_MX53_PAD_KEY_ROW0__GPIO4_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD              (_MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX                (_MX53_PAD_KEY_ROW0__UART4_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI          (_MX53_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW0__FEC_TX_ER            (_MX53_PAD_KEY_ROW0__FEC_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL1__KPP_COL_1            (_MX53_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL1__GPIO4_8              (_MX53_PAD_KEY_COL1__GPIO4_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS             (_MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL1__UART5_TXD_MUX                (_MX53_PAD_KEY_COL1__UART5_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL1__ECSPI1_MISO          (_MX53_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL1__FEC_RX_CLK           (_MX53_PAD_KEY_COL1__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY              (_MX53_PAD_KEY_COL1__USBPHY1_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW1__KPP_ROW_1            (_MX53_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW1__GPIO4_9              (_MX53_PAD_KEY_ROW1__GPIO4_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD              (_MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX                (_MX53_PAD_KEY_ROW1__UART5_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW1__ECSPI1_SS0           (_MX53_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW1__FEC_COL              (_MX53_PAD_KEY_ROW1__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID              (_MX53_PAD_KEY_ROW1__USBPHY1_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL2__KPP_COL_2            (_MX53_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL2__GPIO4_10             (_MX53_PAD_KEY_COL2__GPIO4_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL2__CAN1_TXCAN           (_MX53_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL2__FEC_MDIO             (_MX53_PAD_KEY_COL2__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL2__ECSPI1_SS1           (_MX53_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL2__FEC_RDATA_2          (_MX53_PAD_KEY_COL2__FEC_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE             (_MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW2__KPP_ROW_2            (_MX53_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW2__GPIO4_11             (_MX53_PAD_KEY_ROW2__GPIO4_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW2__CAN1_RXCAN           (_MX53_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW2__FEC_MDC              (_MX53_PAD_KEY_ROW2__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW2__ECSPI1_SS2           (_MX53_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW2__FEC_TDATA_2          (_MX53_PAD_KEY_ROW2__FEC_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR              (_MX53_PAD_KEY_ROW2__USBPHY1_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL3__KPP_COL_3            (_MX53_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL3__GPIO4_12             (_MX53_PAD_KEY_COL3__GPIO4_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL3__USBOH3_H2_DP         (_MX53_PAD_KEY_COL3__USBOH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL3__SPDIF_IN1            (_MX53_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL3__I2C2_SCL             (_MX53_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL3__ECSPI1_SS3           (_MX53_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL3__FEC_CRS              (_MX53_PAD_KEY_COL3__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK             (_MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW3__KPP_ROW_3            (_MX53_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW3__GPIO4_13             (_MX53_PAD_KEY_ROW3__GPIO4_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM         (_MX53_PAD_KEY_ROW3__USBOH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK             (_MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW3__I2C2_SDA             (_MX53_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT               (_MX53_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP         (_MX53_PAD_KEY_ROW3__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0          (_MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL4__KPP_COL_4            (_MX53_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL4__GPIO4_14             (_MX53_PAD_KEY_COL4__GPIO4_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL4__CAN2_TXCAN           (_MX53_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL4__IPU_SISG_4           (_MX53_PAD_KEY_COL4__IPU_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL4__UART5_RTS            (_MX53_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC             (_MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1          (_MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW4__KPP_ROW_4            (_MX53_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW4__GPIO4_15             (_MX53_PAD_KEY_ROW4__GPIO4_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW4__CAN2_RXCAN           (_MX53_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW4__IPU_SISG_5           (_MX53_PAD_KEY_ROW4__IPU_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW4__UART5_CTS            (_MX53_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR            (_MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID            (_MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK         (_MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_DISP_CLK__GPIO4_16         (_MX53_PAD_DI0_DISP_CLK__GPIO4_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR         (_MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0          (_MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0          (_MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID           (_MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               (_MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN15__GPIO4_17            (_MX53_PAD_DI0_PIN15__GPIO4_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC             (_MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1             (_MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1             (_MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID              (_MX53_PAD_DI0_PIN15__USBPHY1_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2         (_MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN2__GPIO4_18             (_MX53_PAD_DI0_PIN2__GPIO4_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD              (_MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2              (_MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2              (_MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION           (_MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3         (_MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN3__GPIO4_19             (_MX53_PAD_DI0_PIN3__GPIO4_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS             (_MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3              (_MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3              (_MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG                (_MX53_PAD_DI0_PIN3__USBPHY1_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4         (_MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN4__GPIO4_20             (_MX53_PAD_DI0_PIN4__GPIO4_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD              (_MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN4__ESDHC1_WP            (_MX53_PAD_DI0_PIN4__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD             (_MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4              (_MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT               (_MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            (_MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT0__GPIO4_21           (_MX53_PAD_DISP0_DAT0__GPIO4_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT0__CSPI_SCLK          (_MX53_PAD_DISP0_DAT0__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0                (_MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN                (_MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5            (_MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY            (_MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            (_MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT1__GPIO4_22           (_MX53_PAD_DISP0_DAT1__GPIO4_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT1__CSPI_MOSI          (_MX53_PAD_DISP0_DAT1__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1                (_MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL               (_MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6            (_MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID            (_MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            (_MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT2__GPIO4_23           (_MX53_PAD_DISP0_DAT2__GPIO4_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT2__CSPI_MISO          (_MX53_PAD_DISP0_DAT2__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2                (_MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE            (_MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7            (_MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE           (_MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            (_MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT3__GPIO4_24           (_MX53_PAD_DISP0_DAT3__GPIO4_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT3__CSPI_SS0           (_MX53_PAD_DISP0_DAT3__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3                (_MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR               (_MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8            (_MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR            (_MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            (_MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT4__GPIO4_25           (_MX53_PAD_DISP0_DAT4__GPIO4_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT4__CSPI_SS1           (_MX53_PAD_DISP0_DAT4__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4                (_MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB         (_MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9            (_MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK           (_MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            (_MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT5__GPIO4_26           (_MX53_PAD_DISP0_DAT5__GPIO4_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT5__CSPI_SS2           (_MX53_PAD_DISP0_DAT5__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5                (_MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS           (_MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10           (_MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0                (_MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            (_MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT6__GPIO4_27           (_MX53_PAD_DISP0_DAT6__GPIO4_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT6__CSPI_SS3           (_MX53_PAD_DISP0_DAT6__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6                (_MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE          (_MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11           (_MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1                (_MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            (_MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT7__GPIO4_28           (_MX53_PAD_DISP0_DAT7__GPIO4_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT7__CSPI_RDY           (_MX53_PAD_DISP0_DAT7__CSPI_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7                (_MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0         (_MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12           (_MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID          (_MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            (_MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT8__GPIO4_29           (_MX53_PAD_DISP0_DAT8__GPIO4_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT8__PWM1_PWMO          (_MX53_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B               (_MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1         (_MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13           (_MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID             (_MX53_PAD_DISP0_DAT8__USBPHY2_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            (_MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT9__GPIO4_30           (_MX53_PAD_DISP0_DAT9__GPIO4_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT9__PWM2_PWMO          (_MX53_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B               (_MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2         (_MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14           (_MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0          (_MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          (_MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT10__GPIO4_31          (_MX53_PAD_DISP0_DAT10__GPIO4_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP          (_MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3                (_MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15          (_MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1         (_MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          (_MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT11__GPIO5_5           (_MX53_PAD_DISP0_DAT11__GPIO5_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT          (_MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4                (_MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16          (_MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2         (_MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          (_MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT12__GPIO5_6           (_MX53_PAD_DISP0_DAT12__GPIO5_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK          (_MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5                (_MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17          (_MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3         (_MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          (_MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT13__GPIO5_7           (_MX53_PAD_DISP0_DAT13__GPIO5_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS          (_MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0                (_MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18          (_MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4         (_MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          (_MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT14__GPIO5_8           (_MX53_PAD_DISP0_DAT14__GPIO5_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC           (_MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1                (_MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19          (_MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5         (_MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          (_MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT15__GPIO5_9           (_MX53_PAD_DISP0_DAT15__GPIO5_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1                (_MX53_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1                (_MX53_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2                (_MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20          (_MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6         (_MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          (_MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT16__GPIO5_10          (_MX53_PAD_DISP0_DAT16__GPIO5_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI               (_MX53_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC           (_MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0          (_MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3                (_MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21          (_MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7         (_MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          (_MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT17__GPIO5_11          (_MX53_PAD_DISP0_DAT17__GPIO5_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO               (_MX53_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD           (_MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1          (_MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4                (_MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22          (_MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          (_MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT18__GPIO5_12          (_MX53_PAD_DISP0_DAT18__GPIO5_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0                (_MX53_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS          (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS          (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5                (_MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23          (_MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2             (_MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          (_MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT19__GPIO5_13          (_MX53_PAD_DISP0_DAT19__GPIO5_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK               (_MX53_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD           (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC           (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6                (_MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24          (_MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3             (_MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          (_MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT20__GPIO5_14          (_MX53_PAD_DISP0_DAT20__GPIO5_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK               (_MX53_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC           (_MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7                (_MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25          (_MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI              (_MX53_PAD_DISP0_DAT20__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          (_MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT21__GPIO5_15          (_MX53_PAD_DISP0_DAT21__GPIO5_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI               (_MX53_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD           (_MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0           (_MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26          (_MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO              (_MX53_PAD_DISP0_DAT21__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          (_MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__GPIO5_16          (_MX53_PAD_DISP0_DAT22__GPIO5_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO               (_MX53_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS          (_MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1           (_MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27          (_MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK              (_MX53_PAD_DISP0_DAT22__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          (_MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__GPIO5_17          (_MX53_PAD_DISP0_DAT23__GPIO5_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0                (_MX53_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD           (_MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2           (_MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28          (_MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS              (_MX53_PAD_DISP0_DAT23__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK           (_MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_PIXCLK__GPIO5_18          (_MX53_PAD_CSI0_PIXCLK__GPIO5_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0           (_MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29          (_MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC              (_MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__GPIO5_19            (_MX53_PAD_CSI0_MCLK__GPIO5_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK               (_MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1             (_MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30            (_MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL          (_MX53_PAD_CSI0_MCLK__TPIU_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN         (_MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DATA_EN__GPIO5_20         (_MX53_PAD_CSI0_DATA_EN__GPIO5_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2          (_MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31         (_MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK               (_MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC             (_MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_VSYNC__GPIO5_21           (_MX53_PAD_CSI0_VSYNC__GPIO5_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3            (_MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32           (_MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0               (_MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4                (_MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__GPIO5_22            (_MX53_PAD_CSI0_DAT4__GPIO5_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__KPP_COL_5           (_MX53_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK         (_MX53_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP            (_MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC             (_MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33            (_MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1                (_MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5                (_MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__GPIO5_23            (_MX53_PAD_CSI0_DAT5__GPIO5_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__KPP_ROW_5           (_MX53_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI         (_MX53_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT            (_MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD             (_MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34            (_MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2                (_MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6                (_MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__GPIO5_24            (_MX53_PAD_CSI0_DAT6__GPIO5_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__KPP_COL_6           (_MX53_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO         (_MX53_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK            (_MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS            (_MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35            (_MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3                (_MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7                (_MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__GPIO5_25            (_MX53_PAD_CSI0_DAT7__GPIO5_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__KPP_ROW_6           (_MX53_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0          (_MX53_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR            (_MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD             (_MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36            (_MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4                (_MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8                (_MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__GPIO5_26            (_MX53_PAD_CSI0_DAT8__GPIO5_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__KPP_COL_7           (_MX53_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK         (_MX53_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC             (_MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__I2C1_SDA            (_MX53_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37            (_MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5                (_MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9                (_MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__GPIO5_27            (_MX53_PAD_CSI0_DAT9__GPIO5_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__KPP_ROW_7           (_MX53_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI         (_MX53_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR            (_MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__I2C1_SCL            (_MX53_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38            (_MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6                (_MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10              (_MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__GPIO5_28           (_MX53_PAD_CSI0_DAT10__GPIO5_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX              (_MX53_PAD_CSI0_DAT10__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO                (_MX53_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC            (_MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4            (_MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39           (_MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7               (_MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11              (_MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__GPIO5_29           (_MX53_PAD_CSI0_DAT11__GPIO5_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX              (_MX53_PAD_CSI0_DAT11__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0         (_MX53_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS           (_MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5            (_MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40           (_MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8               (_MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12              (_MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__GPIO5_30           (_MX53_PAD_CSI0_DAT12__GPIO5_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX              (_MX53_PAD_CSI0_DAT12__UART4_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0                (_MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6            (_MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41           (_MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9               (_MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13              (_MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__GPIO5_31           (_MX53_PAD_CSI0_DAT13__GPIO5_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX              (_MX53_PAD_CSI0_DAT13__UART4_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1                (_MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7            (_MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42           (_MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10              (_MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14              (_MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__GPIO6_0            (_MX53_PAD_CSI0_DAT14__GPIO6_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX              (_MX53_PAD_CSI0_DAT14__UART5_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2                (_MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8            (_MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43           (_MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11              (_MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15              (_MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__GPIO6_1            (_MX53_PAD_CSI0_DAT15__GPIO6_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX              (_MX53_PAD_CSI0_DAT15__UART5_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3                (_MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9            (_MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44           (_MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12              (_MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16              (_MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__GPIO6_2            (_MX53_PAD_CSI0_DAT16__GPIO6_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__UART4_RTS          (_MX53_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4                (_MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10           (_MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45           (_MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13              (_MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17              (_MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__GPIO6_3            (_MX53_PAD_CSI0_DAT17__GPIO6_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__UART4_CTS          (_MX53_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5                (_MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11           (_MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46           (_MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14              (_MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18              (_MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__GPIO6_4            (_MX53_PAD_CSI0_DAT18__GPIO6_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__UART5_RTS          (_MX53_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6                (_MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12           (_MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47           (_MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15              (_MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19              (_MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__GPIO6_5            (_MX53_PAD_CSI0_DAT19__GPIO6_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__UART5_CTS          (_MX53_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7                (_MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13           (_MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48           (_MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK             (_MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__EMI_WEIM_A_25         (_MX53_PAD_EIM_A25__EMI_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__GPIO5_2               (_MX53_PAD_EIM_A25__GPIO5_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__ECSPI2_RDY            (_MX53_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__IPU_DI1_PIN12         (_MX53_PAD_EIM_A25__IPU_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__CSPI_SS1              (_MX53_PAD_EIM_A25__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS         (_MX53_PAD_EIM_A25__IPU_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A25__USBPHY1_BISTOK                (_MX53_PAD_EIM_A25__USBPHY1_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2         (_MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__GPIO2_30              (_MX53_PAD_EIM_EB2__GPIO2_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK               (_MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS              (_MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__ECSPI1_SS0            (_MX53_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB2__I2C2_SCL              (_MX53_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__EMI_WEIM_D_16         (_MX53_PAD_EIM_D16__EMI_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__GPIO3_16              (_MX53_PAD_EIM_D16__GPIO3_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__IPU_DI0_PIN5          (_MX53_PAD_EIM_D16__IPU_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK            (_MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__ECSPI1_SCLK           (_MX53_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D16__I2C2_SDA              (_MX53_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__EMI_WEIM_D_17         (_MX53_PAD_EIM_D17__EMI_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__GPIO3_17              (_MX53_PAD_EIM_D17__GPIO3_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__IPU_DI0_PIN6          (_MX53_PAD_EIM_D17__IPU_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN            (_MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__ECSPI1_MISO           (_MX53_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D17__I2C3_SCL              (_MX53_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__EMI_WEIM_D_18         (_MX53_PAD_EIM_D18__EMI_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__GPIO3_18              (_MX53_PAD_EIM_D18__GPIO3_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__IPU_DI0_PIN7          (_MX53_PAD_EIM_D18__IPU_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO            (_MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__ECSPI1_MOSI           (_MX53_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__I2C3_SDA              (_MX53_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS         (_MX53_PAD_EIM_D18__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__EMI_WEIM_D_19         (_MX53_PAD_EIM_D19__EMI_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__GPIO3_19              (_MX53_PAD_EIM_D19__GPIO3_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__IPU_DI0_PIN8          (_MX53_PAD_EIM_D19__IPU_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS             (_MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__ECSPI1_SS1            (_MX53_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__EPIT1_EPITO           (_MX53_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__UART1_CTS             (_MX53_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC               (_MX53_PAD_EIM_D19__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__EMI_WEIM_D_20         (_MX53_PAD_EIM_D20__EMI_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__GPIO3_20              (_MX53_PAD_EIM_D20__GPIO3_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__IPU_DI0_PIN16         (_MX53_PAD_EIM_D20__IPU_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS              (_MX53_PAD_EIM_D20__IPU_SER_DISP0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__CSPI_SS0              (_MX53_PAD_EIM_D20__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__EPIT2_EPITO           (_MX53_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__UART1_RTS             (_MX53_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR              (_MX53_PAD_EIM_D20__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__EMI_WEIM_D_21         (_MX53_PAD_EIM_D21__EMI_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__GPIO3_21              (_MX53_PAD_EIM_D21__GPIO3_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__IPU_DI0_PIN17         (_MX53_PAD_EIM_D21__IPU_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK            (_MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__CSPI_SCLK             (_MX53_PAD_EIM_D21__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__I2C1_SCL              (_MX53_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC              (_MX53_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__EMI_WEIM_D_22         (_MX53_PAD_EIM_D22__EMI_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__GPIO3_22              (_MX53_PAD_EIM_D22__GPIO3_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__IPU_DI0_PIN1          (_MX53_PAD_EIM_D22__IPU_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN            (_MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__CSPI_MISO             (_MX53_PAD_EIM_D22__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR             (_MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__EMI_WEIM_D_23         (_MX53_PAD_EIM_D23__EMI_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__GPIO3_23              (_MX53_PAD_EIM_D23__GPIO3_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__UART3_CTS             (_MX53_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__UART1_DCD             (_MX53_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS         (_MX53_PAD_EIM_D23__IPU_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN2          (_MX53_PAD_EIM_D23__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN              (_MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN14         (_MX53_PAD_EIM_D23__IPU_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3         (_MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__GPIO2_31              (_MX53_PAD_EIM_EB3__GPIO2_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__UART3_RTS             (_MX53_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__UART1_RI              (_MX53_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3          (_MX53_PAD_EIM_EB3__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC                (_MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16         (_MX53_PAD_EIM_EB3__IPU_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__EMI_WEIM_D_24         (_MX53_PAD_EIM_D24__EMI_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__GPIO3_24              (_MX53_PAD_EIM_D24__GPIO3_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__UART3_TXD_MUX         (_MX53_PAD_EIM_D24__UART3_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__ECSPI1_SS2            (_MX53_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__CSPI_SS2              (_MX53_PAD_EIM_D24__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS              (_MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__ECSPI2_SS2            (_MX53_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__UART1_DTR             (_MX53_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__EMI_WEIM_D_25         (_MX53_PAD_EIM_D25__EMI_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__GPIO3_25              (_MX53_PAD_EIM_D25__GPIO3_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__UART3_RXD_MUX         (_MX53_PAD_EIM_D25__UART3_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__ECSPI1_SS3            (_MX53_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__CSPI_SS3              (_MX53_PAD_EIM_D25__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC               (_MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__ECSPI2_SS3            (_MX53_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__UART1_DSR             (_MX53_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__EMI_WEIM_D_26         (_MX53_PAD_EIM_D26__EMI_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__GPIO3_26              (_MX53_PAD_EIM_D26__GPIO3_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__UART2_TXD_MUX         (_MX53_PAD_EIM_D26__UART2_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__FIRI_RXD              (_MX53_PAD_EIM_D26__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__IPU_CSI0_D_1          (_MX53_PAD_EIM_D26__IPU_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__IPU_DI1_PIN11         (_MX53_PAD_EIM_D26__IPU_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__IPU_SISG_2            (_MX53_PAD_EIM_D26__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22              (_MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__EMI_WEIM_D_27         (_MX53_PAD_EIM_D27__EMI_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__GPIO3_27              (_MX53_PAD_EIM_D27__GPIO3_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__UART2_RXD_MUX         (_MX53_PAD_EIM_D27__UART2_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__FIRI_TXD              (_MX53_PAD_EIM_D27__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__IPU_CSI0_D_0          (_MX53_PAD_EIM_D27__IPU_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__IPU_DI1_PIN13         (_MX53_PAD_EIM_D27__IPU_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__IPU_SISG_3            (_MX53_PAD_EIM_D27__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23              (_MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__EMI_WEIM_D_28         (_MX53_PAD_EIM_D28__EMI_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__GPIO3_28              (_MX53_PAD_EIM_D28__GPIO3_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__UART2_CTS             (_MX53_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO            (_MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__CSPI_MOSI             (_MX53_PAD_EIM_D28__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__I2C1_SDA              (_MX53_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__IPU_EXT_TRIG          (_MX53_PAD_EIM_D28__IPU_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__IPU_DI0_PIN13         (_MX53_PAD_EIM_D28__IPU_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__EMI_WEIM_D_29         (_MX53_PAD_EIM_D29__EMI_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__GPIO3_29              (_MX53_PAD_EIM_D29__GPIO3_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__UART2_RTS             (_MX53_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS             (_MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__CSPI_SS0              (_MX53_PAD_EIM_D29__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__IPU_DI1_PIN15         (_MX53_PAD_EIM_D29__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC                (_MX53_PAD_EIM_D29__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__IPU_DI0_PIN14         (_MX53_PAD_EIM_D29__IPU_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__EMI_WEIM_D_30         (_MX53_PAD_EIM_D30__EMI_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__GPIO3_30              (_MX53_PAD_EIM_D30__GPIO3_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__UART3_CTS             (_MX53_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__IPU_CSI0_D_3          (_MX53_PAD_EIM_D30__IPU_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__IPU_DI0_PIN11         (_MX53_PAD_EIM_D30__IPU_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21              (_MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC               (_MX53_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC               (_MX53_PAD_EIM_D30__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__EMI_WEIM_D_31         (_MX53_PAD_EIM_D31__EMI_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__GPIO3_31              (_MX53_PAD_EIM_D31__GPIO3_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__UART3_RTS             (_MX53_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__IPU_CSI0_D_2          (_MX53_PAD_EIM_D31__IPU_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__IPU_DI0_PIN12         (_MX53_PAD_EIM_D31__IPU_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20              (_MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR              (_MX53_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR              (_MX53_PAD_EIM_D31__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__EMI_WEIM_A_24         (_MX53_PAD_EIM_A24__EMI_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__GPIO5_4               (_MX53_PAD_EIM_A24__GPIO5_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19              (_MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__IPU_CSI1_D_19         (_MX53_PAD_EIM_A24__IPU_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__IPU_SISG_2            (_MX53_PAD_EIM_A24__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A24__USBPHY2_BVALID                (_MX53_PAD_EIM_A24__USBPHY2_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__EMI_WEIM_A_23         (_MX53_PAD_EIM_A23__EMI_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__GPIO6_6               (_MX53_PAD_EIM_A23__GPIO6_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18              (_MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__IPU_CSI1_D_18         (_MX53_PAD_EIM_A23__IPU_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__IPU_SISG_3            (_MX53_PAD_EIM_A23__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION            (_MX53_PAD_EIM_A23__USBPHY2_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A22__EMI_WEIM_A_22         (_MX53_PAD_EIM_A22__EMI_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A22__GPIO2_16              (_MX53_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17              (_MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A22__IPU_CSI1_D_17         (_MX53_PAD_EIM_A22__IPU_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7         (_MX53_PAD_EIM_A22__SRC_BT_CFG1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A21__EMI_WEIM_A_21         (_MX53_PAD_EIM_A21__EMI_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A21__GPIO2_17              (_MX53_PAD_EIM_A21__GPIO2_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16              (_MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A21__IPU_CSI1_D_16         (_MX53_PAD_EIM_A21__IPU_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6         (_MX53_PAD_EIM_A21__SRC_BT_CFG1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A20__EMI_WEIM_A_20         (_MX53_PAD_EIM_A20__EMI_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A20__GPIO2_18              (_MX53_PAD_EIM_A20__GPIO2_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15              (_MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A20__IPU_CSI1_D_15         (_MX53_PAD_EIM_A20__IPU_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5         (_MX53_PAD_EIM_A20__SRC_BT_CFG1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A19__EMI_WEIM_A_19         (_MX53_PAD_EIM_A19__EMI_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A19__GPIO2_19              (_MX53_PAD_EIM_A19__GPIO2_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14              (_MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A19__IPU_CSI1_D_14         (_MX53_PAD_EIM_A19__IPU_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4         (_MX53_PAD_EIM_A19__SRC_BT_CFG1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A18__EMI_WEIM_A_18         (_MX53_PAD_EIM_A18__EMI_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A18__GPIO2_20              (_MX53_PAD_EIM_A18__GPIO2_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13              (_MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A18__IPU_CSI1_D_13         (_MX53_PAD_EIM_A18__IPU_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3         (_MX53_PAD_EIM_A18__SRC_BT_CFG1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A17__EMI_WEIM_A_17         (_MX53_PAD_EIM_A17__EMI_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A17__GPIO2_21              (_MX53_PAD_EIM_A17__GPIO2_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12              (_MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A17__IPU_CSI1_D_12         (_MX53_PAD_EIM_A17__IPU_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2         (_MX53_PAD_EIM_A17__SRC_BT_CFG1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A16__EMI_WEIM_A_16         (_MX53_PAD_EIM_A16__EMI_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A16__GPIO2_22              (_MX53_PAD_EIM_A16__GPIO2_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK              (_MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK               (_MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1         (_MX53_PAD_EIM_A16__SRC_BT_CFG1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0         (_MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS0__GPIO2_23              (_MX53_PAD_EIM_CS0__GPIO2_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS0__ECSPI2_SCLK           (_MX53_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5          (_MX53_PAD_EIM_CS0__IPU_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1         (_MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS1__GPIO2_24              (_MX53_PAD_EIM_CS1__GPIO2_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS1__ECSPI2_MOSI           (_MX53_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6          (_MX53_PAD_EIM_CS1__IPU_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_OE__EMI_WEIM_OE            (_MX53_PAD_EIM_OE__EMI_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_OE__GPIO2_25               (_MX53_PAD_EIM_OE__GPIO2_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_OE__ECSPI2_MISO            (_MX53_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_OE__IPU_DI1_PIN7           (_MX53_PAD_EIM_OE__IPU_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_OE__USBPHY2_IDDIG          (_MX53_PAD_EIM_OE__USBPHY2_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_RW__EMI_WEIM_RW            (_MX53_PAD_EIM_RW__EMI_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_RW__GPIO2_26               (_MX53_PAD_EIM_RW__GPIO2_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_RW__ECSPI2_SS0             (_MX53_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_RW__IPU_DI1_PIN8           (_MX53_PAD_EIM_RW__IPU_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT         (_MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA          (_MX53_PAD_EIM_LBA__EMI_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_LBA__GPIO2_27              (_MX53_PAD_EIM_LBA__GPIO2_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_LBA__ECSPI2_SS1            (_MX53_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17         (_MX53_PAD_EIM_LBA__IPU_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0         (_MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0         (_MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__GPIO2_28              (_MX53_PAD_EIM_EB0__GPIO2_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11              (_MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11         (_MX53_PAD_EIM_EB0__IPU_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY          (_MX53_PAD_EIM_EB0__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7         (_MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1         (_MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB1__GPIO2_29              (_MX53_PAD_EIM_EB1__GPIO2_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10              (_MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10         (_MX53_PAD_EIM_EB1__IPU_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6         (_MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0            (_MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA0__GPIO3_0               (_MX53_PAD_EIM_DA0__GPIO3_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9               (_MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9          (_MX53_PAD_EIM_DA0__IPU_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5         (_MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1            (_MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA1__GPIO3_1               (_MX53_PAD_EIM_DA1__GPIO3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8               (_MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8          (_MX53_PAD_EIM_DA1__IPU_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4         (_MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2            (_MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA2__GPIO3_2               (_MX53_PAD_EIM_DA2__GPIO3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7               (_MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7          (_MX53_PAD_EIM_DA2__IPU_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3         (_MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3            (_MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA3__GPIO3_3               (_MX53_PAD_EIM_DA3__GPIO3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6               (_MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6          (_MX53_PAD_EIM_DA3__IPU_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2         (_MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4            (_MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA4__GPIO3_4               (_MX53_PAD_EIM_DA4__GPIO3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5               (_MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5          (_MX53_PAD_EIM_DA4__IPU_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7         (_MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5            (_MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA5__GPIO3_5               (_MX53_PAD_EIM_DA5__GPIO3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4               (_MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4          (_MX53_PAD_EIM_DA5__IPU_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6         (_MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6            (_MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA6__GPIO3_6               (_MX53_PAD_EIM_DA6__GPIO3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3               (_MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3          (_MX53_PAD_EIM_DA6__IPU_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5         (_MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7            (_MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA7__GPIO3_7               (_MX53_PAD_EIM_DA7__GPIO3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2               (_MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2          (_MX53_PAD_EIM_DA7__IPU_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4         (_MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8            (_MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA8__GPIO3_8               (_MX53_PAD_EIM_DA8__GPIO3_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1               (_MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1          (_MX53_PAD_EIM_DA8__IPU_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3         (_MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9            (_MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA9__GPIO3_9               (_MX53_PAD_EIM_DA9__GPIO3_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0               (_MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0          (_MX53_PAD_EIM_DA9__IPU_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2         (_MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10          (_MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA10__GPIO3_10             (_MX53_PAD_EIM_DA10__GPIO3_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15                (_MX53_PAD_EIM_DA10__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN             (_MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1                (_MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11          (_MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA11__GPIO3_11             (_MX53_PAD_EIM_DA11__GPIO3_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2         (_MX53_PAD_EIM_DA11__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC               (_MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12          (_MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA12__GPIO3_12             (_MX53_PAD_EIM_DA12__GPIO3_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3         (_MX53_PAD_EIM_DA12__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC               (_MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13          (_MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA13__GPIO3_13             (_MX53_PAD_EIM_DA13__GPIO3_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS                (_MX53_PAD_EIM_DA13__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK              (_MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14          (_MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA14__GPIO3_14             (_MX53_PAD_EIM_DA14__GPIO3_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS                (_MX53_PAD_EIM_DA14__IPU_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK              (_MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15          (_MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA15__GPIO3_15             (_MX53_PAD_EIM_DA15__GPIO3_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1         (_MX53_PAD_EIM_DA15__IPU_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4         (_MX53_PAD_EIM_DA15__IPU_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B             (_MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_WE_B__GPIO6_12           (_MX53_PAD_NANDF_WE_B__GPIO6_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B             (_MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_RE_B__GPIO6_13           (_MX53_PAD_NANDF_RE_B__GPIO6_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT                (_MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_WAIT__GPIO5_0              (_MX53_PAD_EIM_WAIT__GPIO5_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B             (_MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX3_P__GPIO6_22          (_MX53_PAD_LVDS1_TX3_P__GPIO6_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3             (_MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX2_P__GPIO6_24          (_MX53_PAD_LVDS1_TX2_P__GPIO6_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2             (_MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_CLK_P__GPIO6_26          (_MX53_PAD_LVDS1_CLK_P__GPIO6_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK             (_MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX1_P__GPIO6_28          (_MX53_PAD_LVDS1_TX1_P__GPIO6_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1             (_MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX0_P__GPIO6_30          (_MX53_PAD_LVDS1_TX0_P__GPIO6_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0             (_MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX3_P__GPIO7_22          (_MX53_PAD_LVDS0_TX3_P__GPIO7_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3             (_MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_CLK_P__GPIO7_24          (_MX53_PAD_LVDS0_CLK_P__GPIO7_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK             (_MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX2_P__GPIO7_26          (_MX53_PAD_LVDS0_TX2_P__GPIO7_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2             (_MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX1_P__GPIO7_28          (_MX53_PAD_LVDS0_TX1_P__GPIO7_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1             (_MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX0_P__GPIO7_30          (_MX53_PAD_LVDS0_TX0_P__GPIO7_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0             (_MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_10__GPIO4_0               (_MX53_PAD_GPIO_10__GPIO4_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_10__OSC32k_32K_OUT                (_MX53_PAD_GPIO_10__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_11__GPIO4_1               (_MX53_PAD_GPIO_11__GPIO4_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_12__GPIO4_2               (_MX53_PAD_GPIO_12__GPIO4_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_13__GPIO4_3               (_MX53_PAD_GPIO_13__GPIO4_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_14__GPIO4_4               (_MX53_PAD_GPIO_14__GPIO4_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE               (_MX53_PAD_NANDF_CLE__EMI_NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CLE__GPIO6_7             (_MX53_PAD_NANDF_CLE__GPIO6_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0           (_MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE               (_MX53_PAD_NANDF_ALE__EMI_NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_ALE__GPIO6_8             (_MX53_PAD_NANDF_ALE__GPIO6_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1           (_MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B             (_MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_WP_B__GPIO6_9            (_MX53_PAD_NANDF_WP_B__GPIO6_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2          (_MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0              (_MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_RB0__GPIO6_10            (_MX53_PAD_NANDF_RB0__GPIO6_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3           (_MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0              (_MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS0__GPIO6_11            (_MX53_PAD_NANDF_CS0__GPIO6_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4           (_MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1              (_MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS1__GPIO6_14            (_MX53_PAD_NANDF_CS1__GPIO6_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS1__MLB_MLBCLK          (_MX53_PAD_NANDF_CS1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5           (_MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2              (_MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__GPIO6_15            (_MX53_PAD_NANDF_CS2__GPIO6_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__IPU_SISG_0          (_MX53_PAD_NANDF_CS2__IPU_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__ESAI1_TX0           (_MX53_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE                (_MX53_PAD_NANDF_CS2__EMI_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK               (_MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__MLB_MLBSIG          (_MX53_PAD_NANDF_CS2__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6           (_MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3              (_MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__GPIO6_16            (_MX53_PAD_NANDF_CS3__GPIO6_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__IPU_SISG_1          (_MX53_PAD_NANDF_CS3__IPU_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__ESAI1_TX1           (_MX53_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26               (_MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__MLB_MLBDAT          (_MX53_PAD_NANDF_CS3__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7           (_MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__FEC_MDIO             (_MX53_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__GPIO1_22             (_MX53_PAD_FEC_MDIO__GPIO1_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__ESAI1_SCKR           (_MX53_PAD_FEC_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__FEC_COL              (_MX53_PAD_FEC_MDIO__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2               (_MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3              (_MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49             (_MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK                (_MX53_PAD_FEC_REF_CLK__FEC_TX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_REF_CLK__GPIO1_23          (_MX53_PAD_FEC_REF_CLK__GPIO1_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR         (_MX53_PAD_FEC_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4           (_MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50          (_MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RX_ER__FEC_RX_ER           (_MX53_PAD_FEC_RX_ER__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RX_ER__GPIO1_24            (_MX53_PAD_FEC_RX_ER__GPIO1_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR          (_MX53_PAD_FEC_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK          (_MX53_PAD_FEC_RX_ER__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3              (_MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV          (_MX53_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_CRS_DV__GPIO1_25           (_MX53_PAD_FEC_CRS_DV__GPIO1_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT         (_MX53_PAD_FEC_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD1__FEC_RDATA_1          (_MX53_PAD_FEC_RXD1__FEC_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD1__GPIO1_26             (_MX53_PAD_FEC_RXD1__GPIO1_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD1__ESAI1_FST            (_MX53_PAD_FEC_RXD1__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD1__MLB_MLBSIG           (_MX53_PAD_FEC_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1               (_MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD0__FEC_RDATA_0          (_MX53_PAD_FEC_RXD0__FEC_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD0__GPIO1_27             (_MX53_PAD_FEC_RXD0__GPIO1_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD0__ESAI1_HCKT           (_MX53_PAD_FEC_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT               (_MX53_PAD_FEC_RXD0__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TX_EN__FEC_TX_EN           (_MX53_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TX_EN__GPIO1_28            (_MX53_PAD_FEC_TX_EN__GPIO1_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2               (_MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD1__FEC_TDATA_1          (_MX53_PAD_FEC_TXD1__FEC_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD1__GPIO1_29             (_MX53_PAD_FEC_TXD1__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3                (_MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD1__MLB_MLBCLK           (_MX53_PAD_FEC_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK          (_MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD0__FEC_TDATA_0          (_MX53_PAD_FEC_TXD0__FEC_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD0__GPIO1_30             (_MX53_PAD_FEC_TXD0__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1                (_MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0            (_MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__FEC_MDC               (_MX53_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__GPIO1_31              (_MX53_PAD_FEC_MDC__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0         (_MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__MLB_MLBDAT            (_MX53_PAD_FEC_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG                (_MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1             (_MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOW__PATA_DIOW           (_MX53_PAD_PATA_DIOW__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOW__GPIO6_17            (_MX53_PAD_PATA_DIOW__GPIO6_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX               (_MX53_PAD_PATA_DIOW__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2           (_MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMACK__PATA_DMACK         (_MX53_PAD_PATA_DMACK__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMACK__GPIO6_18           (_MX53_PAD_PATA_DMACK__GPIO6_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX              (_MX53_PAD_PATA_DMACK__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3          (_MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMARQ__PATA_DMARQ         (_MX53_PAD_PATA_DMARQ__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMARQ__GPIO7_0            (_MX53_PAD_PATA_DMARQ__GPIO7_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX              (_MX53_PAD_PATA_DMARQ__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0              (_MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4          (_MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN         (_MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1                (_MX53_PAD_PATA_BUFFER_EN__GPIO7_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX          (_MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1          (_MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5              (_MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__PATA_INTRQ         (_MX53_PAD_PATA_INTRQ__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__GPIO7_2            (_MX53_PAD_PATA_INTRQ__GPIO7_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__UART2_CTS          (_MX53_PAD_PATA_INTRQ__UART2_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN         (_MX53_PAD_PATA_INTRQ__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2              (_MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6          (_MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOR__PATA_DIOR           (_MX53_PAD_PATA_DIOR__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOR__GPIO7_3             (_MX53_PAD_PATA_DIOR__GPIO7_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOR__UART2_RTS           (_MX53_PAD_PATA_DIOR__UART2_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DIOR__CAN1_RXCAN          (_MX53_PAD_PATA_DIOR__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7           (_MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B                (_MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__GPIO7_4          (_MX53_PAD_PATA_RESET_B__GPIO7_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD               (_MX53_PAD_PATA_RESET_B__ESDHC3_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__UART1_CTS                (_MX53_PAD_PATA_RESET_B__UART1_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN               (_MX53_PAD_PATA_RESET_B__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0                (_MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__PATA_IORDY         (_MX53_PAD_PATA_IORDY__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__GPIO7_5            (_MX53_PAD_PATA_IORDY__GPIO7_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__ESDHC3_CLK         (_MX53_PAD_PATA_IORDY__ESDHC3_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__UART1_RTS          (_MX53_PAD_PATA_IORDY__UART1_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__CAN2_RXCAN         (_MX53_PAD_PATA_IORDY__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1          (_MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_0__PATA_DA_0           (_MX53_PAD_PATA_DA_0__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_0__GPIO7_6             (_MX53_PAD_PATA_DA_0__GPIO7_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_0__ESDHC3_RST          (_MX53_PAD_PATA_DA_0__ESDHC3_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_0__OWIRE_LINE          (_MX53_PAD_PATA_DA_0__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2           (_MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_1__PATA_DA_1           (_MX53_PAD_PATA_DA_1__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_1__GPIO7_7             (_MX53_PAD_PATA_DA_1__GPIO7_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_1__ESDHC4_CMD          (_MX53_PAD_PATA_DA_1__ESDHC4_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DA_1__UART3_CTS           (_MX53_PAD_PATA_DA_1__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3           (_MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_2__PATA_DA_2           (_MX53_PAD_PATA_DA_2__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_2__GPIO7_8             (_MX53_PAD_PATA_DA_2__GPIO7_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DA_2__ESDHC4_CLK          (_MX53_PAD_PATA_DA_2__ESDHC4_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DA_2__UART3_RTS           (_MX53_PAD_PATA_DA_2__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4           (_MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_0__PATA_CS_0           (_MX53_PAD_PATA_CS_0__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_0__GPIO7_9             (_MX53_PAD_PATA_CS_0__GPIO7_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX               (_MX53_PAD_PATA_CS_0__UART3_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5           (_MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_1__PATA_CS_1           (_MX53_PAD_PATA_CS_1__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_1__GPIO7_10            (_MX53_PAD_PATA_CS_1__GPIO7_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX               (_MX53_PAD_PATA_CS_1__UART3_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
+#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6           (_MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__PATA_DATA_0                (_MX53_PAD_PATA_DATA0__PATA_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__GPIO2_0            (_MX53_PAD_PATA_DATA0__GPIO2_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0              (_MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4                (_MX53_PAD_PATA_DATA0__ESDHC3_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0              (_MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0             (_MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7          (_MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__PATA_DATA_1                (_MX53_PAD_PATA_DATA1__PATA_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__GPIO2_1            (_MX53_PAD_PATA_DATA1__GPIO2_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1              (_MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5                (_MX53_PAD_PATA_DATA1__ESDHC3_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1              (_MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1             (_MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__PATA_DATA_2                (_MX53_PAD_PATA_DATA2__PATA_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__GPIO2_2            (_MX53_PAD_PATA_DATA2__GPIO2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2              (_MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6                (_MX53_PAD_PATA_DATA2__ESDHC3_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2              (_MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2             (_MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__PATA_DATA_3                (_MX53_PAD_PATA_DATA3__PATA_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__GPIO2_3            (_MX53_PAD_PATA_DATA3__GPIO2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3              (_MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7                (_MX53_PAD_PATA_DATA3__ESDHC3_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3              (_MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3             (_MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__PATA_DATA_4                (_MX53_PAD_PATA_DATA4__PATA_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__GPIO2_4            (_MX53_PAD_PATA_DATA4__GPIO2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4              (_MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4                (_MX53_PAD_PATA_DATA4__ESDHC4_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4              (_MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4             (_MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__PATA_DATA_5                (_MX53_PAD_PATA_DATA5__PATA_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__GPIO2_5            (_MX53_PAD_PATA_DATA5__GPIO2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5              (_MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5                (_MX53_PAD_PATA_DATA5__ESDHC4_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5              (_MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5             (_MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__PATA_DATA_6                (_MX53_PAD_PATA_DATA6__PATA_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__GPIO2_6            (_MX53_PAD_PATA_DATA6__GPIO2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6              (_MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6                (_MX53_PAD_PATA_DATA6__ESDHC4_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6              (_MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6             (_MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__PATA_DATA_7                (_MX53_PAD_PATA_DATA7__PATA_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__GPIO2_7            (_MX53_PAD_PATA_DATA7__GPIO2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7              (_MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7                (_MX53_PAD_PATA_DATA7__ESDHC4_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7              (_MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7             (_MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__PATA_DATA_8                (_MX53_PAD_PATA_DATA8__PATA_DATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__GPIO2_8            (_MX53_PAD_PATA_DATA8__GPIO2_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4                (_MX53_PAD_PATA_DATA8__ESDHC1_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8              (_MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0                (_MX53_PAD_PATA_DATA8__ESDHC3_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8              (_MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8             (_MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__PATA_DATA_9                (_MX53_PAD_PATA_DATA9__PATA_DATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__GPIO2_9            (_MX53_PAD_PATA_DATA9__GPIO2_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5                (_MX53_PAD_PATA_DATA9__ESDHC1_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9              (_MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1                (_MX53_PAD_PATA_DATA9__ESDHC3_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9              (_MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9             (_MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__PATA_DATA_10              (_MX53_PAD_PATA_DATA10__PATA_DATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__GPIO2_10          (_MX53_PAD_PATA_DATA10__GPIO2_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6               (_MX53_PAD_PATA_DATA10__ESDHC1_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10            (_MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2               (_MX53_PAD_PATA_DATA10__ESDHC3_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10            (_MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10           (_MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__PATA_DATA_11              (_MX53_PAD_PATA_DATA11__PATA_DATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__GPIO2_11          (_MX53_PAD_PATA_DATA11__GPIO2_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7               (_MX53_PAD_PATA_DATA11__ESDHC1_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11            (_MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3               (_MX53_PAD_PATA_DATA11__ESDHC3_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11            (_MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11           (_MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__PATA_DATA_12              (_MX53_PAD_PATA_DATA12__PATA_DATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__GPIO2_12          (_MX53_PAD_PATA_DATA12__GPIO2_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4               (_MX53_PAD_PATA_DATA12__ESDHC2_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12            (_MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0               (_MX53_PAD_PATA_DATA12__ESDHC4_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12            (_MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12           (_MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__PATA_DATA_13              (_MX53_PAD_PATA_DATA13__PATA_DATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__GPIO2_13          (_MX53_PAD_PATA_DATA13__GPIO2_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5               (_MX53_PAD_PATA_DATA13__ESDHC2_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13            (_MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1               (_MX53_PAD_PATA_DATA13__ESDHC4_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13            (_MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13           (_MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__PATA_DATA_14              (_MX53_PAD_PATA_DATA14__PATA_DATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__GPIO2_14          (_MX53_PAD_PATA_DATA14__GPIO2_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6               (_MX53_PAD_PATA_DATA14__ESDHC2_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14            (_MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2               (_MX53_PAD_PATA_DATA14__ESDHC4_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14            (_MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14           (_MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__PATA_DATA_15              (_MX53_PAD_PATA_DATA15__PATA_DATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__GPIO2_15          (_MX53_PAD_PATA_DATA15__GPIO2_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7               (_MX53_PAD_PATA_DATA15__ESDHC2_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15            (_MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3               (_MX53_PAD_PATA_DATA15__ESDHC4_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15            (_MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15           (_MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0         (_MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_DATA0__GPIO1_16            (_MX53_PAD_SD1_DATA0__GPIO1_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA0__GPT_CAPIN1          (_MX53_PAD_SD1_DATA0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA0__CSPI_MISO           (_MX53_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP                (_MX53_PAD_SD1_DATA0__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1         (_MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_DATA1__GPIO1_17            (_MX53_PAD_SD1_DATA1__GPIO1_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA1__GPT_CAPIN2          (_MX53_PAD_SD1_DATA1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA1__CSPI_SS0            (_MX53_PAD_SD1_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP                (_MX53_PAD_SD1_DATA1__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CMD__ESDHC1_CMD            (_MX53_PAD_SD1_CMD__ESDHC1_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_CMD__GPIO1_18              (_MX53_PAD_SD1_CMD__GPIO1_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CMD__GPT_CMPOUT1           (_MX53_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CMD__CSPI_MOSI             (_MX53_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP          (_MX53_PAD_SD1_CMD__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2         (_MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__GPIO1_19            (_MX53_PAD_SD1_DATA2__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2         (_MX53_PAD_SD1_DATA2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__PWM2_PWMO           (_MX53_PAD_SD1_DATA2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B                (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__CSPI_SS1            (_MX53_PAD_SD1_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB                (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP                (_MX53_PAD_SD1_DATA2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__ESDHC1_CLK            (_MX53_PAD_SD1_CLK__ESDHC1_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__GPIO1_20              (_MX53_PAD_SD1_CLK__GPIO1_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT                (_MX53_PAD_SD1_CLK__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__GPT_CLKIN             (_MX53_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__CSPI_SCLK             (_MX53_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0                (_MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3         (_MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__GPIO1_21            (_MX53_PAD_SD1_DATA3__GPIO1_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3         (_MX53_PAD_SD1_DATA3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__PWM1_PWMO           (_MX53_PAD_SD1_DATA3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B                (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__CSPI_SS2            (_MX53_PAD_SD1_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB                (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1              (_MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__ESDHC2_CLK            (_MX53_PAD_SD2_CLK__ESDHC2_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__GPIO1_10              (_MX53_PAD_SD2_CLK__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__KPP_COL_5             (_MX53_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS              (_MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__CSPI_SCLK             (_MX53_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CLK__SCC_RANDOM_V          (_MX53_PAD_SD2_CLK__SCC_RANDOM_V | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__ESDHC2_CMD            (_MX53_PAD_SD2_CMD__ESDHC2_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__GPIO1_11              (_MX53_PAD_SD2_CMD__GPIO1_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__KPP_ROW_5             (_MX53_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC               (_MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__CSPI_MOSI             (_MX53_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_CMD__SCC_RANDOM            (_MX53_PAD_SD2_CMD__SCC_RANDOM | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3         (_MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__GPIO1_12            (_MX53_PAD_SD2_DATA3__GPIO1_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__KPP_COL_6           (_MX53_PAD_SD2_DATA3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC             (_MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__CSPI_SS2            (_MX53_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA3__SJC_DONE            (_MX53_PAD_SD2_DATA3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2         (_MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__GPIO1_13            (_MX53_PAD_SD2_DATA2__GPIO1_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__KPP_ROW_6           (_MX53_PAD_SD2_DATA2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD             (_MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__CSPI_SS1            (_MX53_PAD_SD2_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA2__SJC_FAIL            (_MX53_PAD_SD2_DATA2__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1         (_MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__GPIO1_14            (_MX53_PAD_SD2_DATA1__GPIO1_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__KPP_COL_7           (_MX53_PAD_SD2_DATA1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS            (_MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__CSPI_SS0            (_MX53_PAD_SD2_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO                (_MX53_PAD_SD2_DATA1__RTIC_SEC_VIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0         (_MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__GPIO1_15            (_MX53_PAD_SD2_DATA0__GPIO1_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__KPP_ROW_7           (_MX53_PAD_SD2_DATA0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD             (_MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__CSPI_MISO           (_MX53_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT               (_MX53_PAD_SD2_DATA0__RTIC_DONE_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__CCM_CLKO               (_MX53_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__GPIO1_0                (_MX53_PAD_GPIO_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__KPP_COL_5              (_MX53_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK               (_MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__EPIT1_EPITO            (_MX53_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB         (_MX53_PAD_GPIO_0__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR               (_MX53_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_0__CSU_TD         (_MX53_PAD_GPIO_0__CSU_TD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__ESAI1_SCKR             (_MX53_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__GPIO1_1                (_MX53_PAD_GPIO_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__KPP_ROW_5              (_MX53_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK               (_MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__PWM2_PWMO              (_MX53_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__WDOG2_WDOG_B           (_MX53_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__ESDHC1_CD              (_MX53_PAD_GPIO_1__ESDHC1_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_1__SRC_TESTER_ACK         (_MX53_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__ESAI1_FSR              (_MX53_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__GPIO1_9                (_MX53_PAD_GPIO_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__KPP_COL_6              (_MX53_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__CCM_REF_EN_B           (_MX53_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__PWM1_PWMO              (_MX53_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__WDOG1_WDOG_B           (_MX53_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__ESDHC1_WP              (_MX53_PAD_GPIO_9__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_9__SCC_FAIL_STATE         (_MX53_PAD_GPIO_9__SCC_FAIL_STATE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__ESAI1_HCKR             (_MX53_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__GPIO1_3                (_MX53_PAD_GPIO_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__I2C3_SCL               (_MX53_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN         (_MX53_PAD_GPIO_3__DPLLIP1_TOG_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__CCM_CLKO2              (_MX53_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0             (_MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC                (_MX53_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_3__MLB_MLBCLK             (_MX53_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__ESAI1_SCKT             (_MX53_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__GPIO1_6                (_MX53_PAD_GPIO_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__I2C3_SDA               (_MX53_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0          (_MX53_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB                (_MX53_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1             (_MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__ESDHC2_LCTL            (_MX53_PAD_GPIO_6__ESDHC2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_6__MLB_MLBSIG             (_MX53_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__ESAI1_FST              (_MX53_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__GPIO1_2                (_MX53_PAD_GPIO_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__KPP_ROW_6              (_MX53_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1          (_MX53_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0            (_MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2             (_MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__ESDHC2_WP              (_MX53_PAD_GPIO_2__ESDHC2_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_2__MLB_MLBDAT             (_MX53_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__ESAI1_HCKT             (_MX53_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__GPIO1_4                (_MX53_PAD_GPIO_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__KPP_COL_7              (_MX53_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2          (_MX53_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1            (_MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3             (_MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__ESDHC2_CD              (_MX53_PAD_GPIO_4__ESDHC2_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_4__SCC_SEC_STATE          (_MX53_PAD_GPIO_4__SCC_SEC_STATE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3          (_MX53_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__GPIO1_5                (_MX53_PAD_GPIO_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__KPP_ROW_7              (_MX53_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__CCM_CLKO               (_MX53_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2            (_MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4             (_MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__I2C3_SCL               (_MX53_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_5__CCM_PLL1_BYP           (_MX53_PAD_GPIO_5__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1          (_MX53_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__GPIO1_7                (_MX53_PAD_GPIO_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__EPIT1_EPITO            (_MX53_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__CAN1_TXCAN             (_MX53_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__UART2_TXD_MUX          (_MX53_PAD_GPIO_7__UART2_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__FIRI_RXD               (_MX53_PAD_GPIO_7__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__SPDIF_PLOCK            (_MX53_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__CCM_PLL2_BYP           (_MX53_PAD_GPIO_7__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0          (_MX53_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__GPIO1_8                (_MX53_PAD_GPIO_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__EPIT2_EPITO            (_MX53_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__CAN1_RXCAN             (_MX53_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__UART2_RXD_MUX          (_MX53_PAD_GPIO_8__UART2_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__FIRI_TXD               (_MX53_PAD_GPIO_8__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__SPDIF_SRCLK            (_MX53_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__CCM_PLL3_BYP           (_MX53_PAD_GPIO_8__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2         (_MX53_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__GPIO7_11              (_MX53_PAD_GPIO_16__GPIO7_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT              (_MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1          (_MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__SPDIF_IN1             (_MX53_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__I2C3_SDA              (_MX53_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_16__SJC_DE_B              (_MX53_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__ESAI1_TX0             (_MX53_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__GPIO7_12              (_MX53_PAD_GPIO_17__GPIO7_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0              (_MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__GPC_PMIC_RDY          (_MX53_PAD_GPIO_17__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG           (_MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__SPDIF_OUT1            (_MX53_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__IPU_SNOOP2            (_MX53_PAD_GPIO_17__IPU_SNOOP2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_17__SJC_JTAG_ACT          (_MX53_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_18__ESAI1_TX1             (_MX53_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_18__GPIO7_13              (_MX53_PAD_GPIO_18__GPIO7_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1              (_MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_18__OWIRE_LINE            (_MX53_PAD_GPIO_18__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG                (_MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK              (_MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_18__ESDHC1_LCTL           (_MX53_PAD_GPIO_18__ESDHC1_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST                (_MX53_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
 
 #endif  /* __MACH_IOMUX_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
index 15d59510f597..bf28df0d58b7 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -46,12 +46,12 @@
  *      - setups the iomux according to the configuration
  *      - if the pin is configured as a GPIO, we claim it through kernel gpiolib
  */
-int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label);
+int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label);
 /*
  * setups mutliple pins
  * convenient way to call the above function with tables
  */
-int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
                 const char *label);
 
 /*
@@ -60,12 +60,12 @@ int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
  *      - frees the GPIO if the pin was configured as GPIO
  *      - DOES NOT reconfigure the IOMUX in its reset state
  */
-void mxc_iomux_release_pin(const unsigned int pin_mode);
+void mxc_iomux_release_pin(unsigned int pin_mode);
 /*
  * releases multiple pins
  * convenvient way to call the above function with tables
  */
-void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count);
+void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count);
 
 #define MUX_SIDE_AP             (0)
 #define MUX_SIDE_SP             (1)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h
index 884f5753f279..c07d30210c57 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v1.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h
@@ -100,4 +100,6 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
                 const char *label);
 extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
 
+extern int __init imx_iomuxv1_init(void __iomem *base, int numports);
+
 #endif /* __MACH_IOMUX_V1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index ba65c9231a78..a3d930d3e65d 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -23,17 +23,17 @@
 #define MXC_GPIO_IRQ_START      MXC_INTERNAL_IRQS
 
 /* these are ordered by size to support multi-SoC kernels */
-#if defined CONFIG_ARCH_MX53
+#if defined CONFIG_SOC_IMX53
 #define MXC_GPIO_IRQS           (32 * 7)
 #elif defined CONFIG_ARCH_MX2
 #define MXC_GPIO_IRQS           (32 * 6)
-#elif defined CONFIG_ARCH_MX50
+#elif defined CONFIG_SOC_IMX50
 #define MXC_GPIO_IRQS           (32 * 6)
 #elif defined CONFIG_ARCH_MX1
 #define MXC_GPIO_IRQS           (32 * 4)
 #elif defined CONFIG_ARCH_MX25
 #define MXC_GPIO_IRQS           (32 * 4)
-#elif defined CONFIG_ARCH_MX51
+#elif defined CONFIG_SOC_IMX51
 #define MXC_GPIO_IRQS           (32 * 4)
 #elif defined CONFIG_ARCH_MXC91231
 #define MXC_GPIO_IRQS           (32 * 4)
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 75d96214b831..97b19e7800bc 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -54,13 +54,13 @@
 #define MX1_AIPI2_BASE_ADDR             (0x10000 + MX1_IO_BASE_ADDR)
 #define MX1_SIM_BASE_ADDR               (0x11000 + MX1_IO_BASE_ADDR)
 #define MX1_USBD_BASE_ADDR              (0x12000 + MX1_IO_BASE_ADDR)
-#define MX1_SPI1_BASE_ADDR              (0x13000 + MX1_IO_BASE_ADDR)
+#define MX1_CSPI1_BASE_ADDR             (0x13000 + MX1_IO_BASE_ADDR)
 #define MX1_MMC_BASE_ADDR               (0x14000 + MX1_IO_BASE_ADDR)
 #define MX1_ASP_BASE_ADDR               (0x15000 + MX1_IO_BASE_ADDR)
 #define MX1_BTA_BASE_ADDR               (0x16000 + MX1_IO_BASE_ADDR)
 #define MX1_I2C_BASE_ADDR               (0x17000 + MX1_IO_BASE_ADDR)
 #define MX1_SSI_BASE_ADDR               (0x18000 + MX1_IO_BASE_ADDR)
-#define MX1_SPI2_BASE_ADDR              (0x19000 + MX1_IO_BASE_ADDR)
+#define MX1_CSPI2_BASE_ADDR             (0x19000 + MX1_IO_BASE_ADDR)
 #define MX1_MSHC_BASE_ADDR              (0x1A000 + MX1_IO_BASE_ADDR)
 #define MX1_CCM_BASE_ADDR               (0x1B000 + MX1_IO_BASE_ADDR)
 #define MX1_SCM_BASE_ADDR               (0x1B804 + MX1_IO_BASE_ADDR)
@@ -89,7 +89,7 @@
 #define MX1_GPIO_INT_PORTA      11
 #define MX1_GPIO_INT_PORTB      12
 #define MX1_GPIO_INT_PORTC      13
-#define MX1_LCDC_INT            14
+#define MX1_INT_LCDC            14
 #define MX1_SIM_INT             15
 #define MX1_SIM_DATA_INT        16
 #define MX1_RTC_INT             17
@@ -112,7 +112,8 @@
 #define MX1_PWM_INT             34
 #define MX1_SDHC_INT            35
 #define MX1_INT_I2C             39
-#define MX1_CSPI_INT            41
+#define MX1_INT_CSPI2           40
+#define MX1_INT_CSPI1           41
 #define MX1_SSI_TX_INT          42
 #define MX1_SSI_TX_ERR_INT      43
 #define MX1_SSI_RX_INT          44
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index d7a8e52181ea..ace17864575e 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -79,7 +79,7 @@
 #define MX53_GPIO3_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x0008C000)
 #define MX53_GPIO4_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00090000)
 #define MX53_KPP_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x00094000)
-#define MX53_WDOG_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x00098000)
+#define MX53_WDOG1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00098000)
 #define MX53_WDOG2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x0009C000)
 #define MX53_GPT1_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000A0000)
 #define MX53_SRTC_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000A4000)
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 04c7a26b1f26..7e072637eefa 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -103,7 +103,7 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx27()          (0)
 #endif
 
-#ifdef CONFIG_ARCH_MX31
+#ifdef CONFIG_SOC_IMX31
 # ifdef mxc_cpu_type
 #  undef mxc_cpu_type
 #  define mxc_cpu_type __mxc_cpu_type
@@ -115,7 +115,7 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx31()          (0)
 #endif
 
-#ifdef CONFIG_ARCH_MX35
+#ifdef CONFIG_SOC_IMX35
 # ifdef mxc_cpu_type
 #  undef mxc_cpu_type
 #  define mxc_cpu_type __mxc_cpu_type
@@ -127,7 +127,7 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx35()          (0)
 #endif
 
-#ifdef CONFIG_ARCH_MX50
+#ifdef CONFIG_SOC_IMX50
 # ifdef mxc_cpu_type
 #  undef mxc_cpu_type
 #  define mxc_cpu_type __mxc_cpu_type
@@ -139,7 +139,7 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx50()          (0)
 #endif
 
-#ifdef CONFIG_ARCH_MX51
+#ifdef CONFIG_SOC_IMX51
 # ifdef mxc_cpu_type
 #  undef mxc_cpu_type
 #  define mxc_cpu_type __mxc_cpu_type
@@ -151,7 +151,7 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx51()          (0)
 #endif
 
-#ifdef CONFIG_ARCH_MX53
+#ifdef CONFIG_SOC_IMX53
 # ifdef mxc_cpu_type
 #  undef mxc_cpu_type
 #  define mxc_cpu_type __mxc_cpu_type
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
index a523a4079299..2c159dc2398b 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -44,11 +44,14 @@ struct mxc_usbh_platform_data {
         int (*exit)(struct platform_device *pdev);
 
         unsigned int             portsc;
-        unsigned int             flags;
         struct otg_transceiver  *otg;
 };
 
-int mxc_initialize_usb_hw(int port, unsigned int flags);
+int mx51_initialize_usb_hw(int port, unsigned int flags);
+int mx25_initialize_usb_hw(int port, unsigned int flags);
+int mx31_initialize_usb_hw(int port, unsigned int flags);
+int mx35_initialize_usb_hw(int port, unsigned int flags);
+int mx27_initialize_usb_hw(int port, unsigned int flags);
 
 #endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */
 
diff --git a/arch/arm/plat-mxc/include/mach/ulpi.h b/arch/arm/plat-mxc/include/mach/ulpi.h
index 96b6ab4c40c3..f9161c96d7bd 100644
--- a/arch/arm/plat-mxc/include/mach/ulpi.h
+++ b/arch/arm/plat-mxc/include/mach/ulpi.h
@@ -1,6 +1,15 @@
 #ifndef __MACH_ULPI_H
 #define __MACH_ULPI_H
 
+#ifdef CONFIG_USB_ULPI
+struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags);
+#else
+static inline struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags)
+{
+        return NULL;
+}
+#endif
+
 extern struct otg_io_access_ops mxc_ulpi_access_ops;
 
 #endif /* __MACH_ULPI_H */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index ff469c4f1d76..4864b0afd440 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -62,6 +62,7 @@ static inline void flush(void)
 #define MX2X_UART1_BASE_ADDR    0x1000a000
 #define MX3X_UART1_BASE_ADDR    0x43F90000
 #define MX3X_UART2_BASE_ADDR    0x43F94000
+#define MX3X_UART5_BASE_ADDR    0x43FB4000
 #define MX51_UART1_BASE_ADDR    0x73fbc000
 #define MX50_UART1_BASE_ADDR    0x53fbc000
 #define MX53_UART1_BASE_ADDR    0x53fbc000
@@ -83,6 +84,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
         case MACH_TYPE_MX21ADS:
         case MACH_TYPE_PCA100:
         case MACH_TYPE_MXT_TD60:
+        case MACH_TYPE_IMX27IPCAM:
                 uart_base = MX2X_UART1_BASE_ADDR;
                 break;
         case MACH_TYPE_MX31LITE:
@@ -101,6 +103,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
         case MACH_TYPE_MAGX_ZN5:
                 uart_base = MX3X_UART2_BASE_ADDR;
                 break;
+        case MACH_TYPE_BUG:
+                uart_base = MX3X_UART5_BASE_ADDR;
+                break;
         case MACH_TYPE_MX51_BABBAGE:
         case MACH_TYPE_EUKREA_CPUIMX51SD:
         case MACH_TYPE_MX51_3DS:
@@ -110,6 +115,8 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
                 uart_base = MX50_UART1_BASE_ADDR;
                 break;
         case MACH_TYPE_MX53_EVK:
+        case MACH_TYPE_MX53_LOCO:
+        case MACH_TYPE_MX53_SMD:
                 uart_base = MX53_UART1_BASE_ADDR;
                 break;
         default:
diff --git a/arch/arm/plat-mxc/iomux-v1.c b/arch/arm/plat-mxc/iomux-v1.c
index 960a02cbcbaf..3238c10d4e02 100644
--- a/arch/arm/plat-mxc/iomux-v1.c
+++ b/arch/arm/plat-mxc/iomux-v1.c
@@ -211,28 +211,10 @@ void mxc_gpio_release_multiple_pins(const int *pin_list, int count)
 }
 EXPORT_SYMBOL(mxc_gpio_release_multiple_pins);
 
-static int imx_iomuxv1_init(void)
+int __init imx_iomuxv1_init(void __iomem *base, int numports)
 {
-#ifdef CONFIG_ARCH_MX1
-        if (cpu_is_mx1()) {
-                imx_iomuxv1_baseaddr = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR);
-                imx_iomuxv1_numports = MX1_NUM_GPIO_PORT;
-        } else
-#endif
-#ifdef CONFIG_MACH_MX21
-        if (cpu_is_mx21()) {
-                imx_iomuxv1_baseaddr = MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR);
-                imx_iomuxv1_numports = MX21_NUM_GPIO_PORT;
-        } else
-#endif
-#ifdef CONFIG_MACH_MX27
-        if (cpu_is_mx27()) {
-                imx_iomuxv1_baseaddr = MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR);
-                imx_iomuxv1_numports = MX27_NUM_GPIO_PORT;
-        } else
-#endif
-                return -ENODEV;
+        imx_iomuxv1_baseaddr = base;
+        imx_iomuxv1_numports = numports;
 
         return 0;
 }
-pure_initcall(imx_iomuxv1_init);
diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c
index 582c6dfaba4a..477e45bea1be 100644
--- a/arch/arm/plat-mxc/ulpi.c
+++ b/arch/arm/plat-mxc/ulpi.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
 
 #include <mach/ulpi.h>
 
@@ -111,3 +112,7 @@ struct otg_io_access_ops mxc_ulpi_access_ops = {
 };
 EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
 
+struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags)
+{
+        return otg_ulpi_create(&mxc_ulpi_access_ops, flags);
+}
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 1e88ecb846d1..70620426ee55 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -30,23 +30,39 @@
 /*
  * The GPIO module in the Nomadik family of Systems-on-Chip is an
  * AMBA device, managing 32 pins and alternate functions.  The logic block
- * is currently only used in the Nomadik.
+ * is currently used in the Nomadik and ux500.
  *
  * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
  */
 
-#define NMK_GPIO_PER_CHIP 32
+#define NMK_GPIO_PER_CHIP       32
+
 struct nmk_gpio_chip {
         struct gpio_chip chip;
         void __iomem *addr;
         struct clk *clk;
+        unsigned int bank;
         unsigned int parent_irq;
+        int secondary_parent_irq;
+        u32 (*get_secondary_status)(unsigned int bank);
+        void (*set_ioforce)(bool enable);
         spinlock_t lock;
         /* Keep track of configured edges */
         u32 edge_rising;
         u32 edge_falling;
+        u32 real_wake;
+        u32 rwimsc;
+        u32 fwimsc;
+        u32 slpm;
 };
 
+static struct nmk_gpio_chip *
+nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
+
+static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
+
+#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
+
 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
                                 unsigned offset, int gpio_mode)
 {
@@ -118,8 +134,35 @@ static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
         __nmk_gpio_set_output(nmk_chip, offset, val);
 }
 
+static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
+                                     unsigned offset, int gpio_mode,
+                                     bool glitch)
+{
+        u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
+        u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
+
+        if (glitch && nmk_chip->set_ioforce) {
+                u32 bit = BIT(offset);
+
+                /* Prevent spurious wakeups */
+                writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
+                writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
+
+                nmk_chip->set_ioforce(true);
+        }
+
+        __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
+
+        if (glitch && nmk_chip->set_ioforce) {
+                nmk_chip->set_ioforce(false);
+
+                writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
+                writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
+        }
+}
+
 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
-                             pin_cfg_t cfg, bool sleep)
+                             pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
 {
         static const char *afnames[] = {
                 [NMK_GPIO_ALT_GPIO]     = "GPIO",
@@ -144,6 +187,7 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
         int slpm = PIN_SLPM(cfg);
         int output = PIN_DIR(cfg);
         int val = PIN_VAL(cfg);
+        bool glitch = af == NMK_GPIO_ALT_C;
 
         dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
                 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
@@ -155,6 +199,8 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
                 int slpm_output = PIN_SLPM_DIR(cfg);
                 int slpm_val = PIN_SLPM_VAL(cfg);
 
+                af = NMK_GPIO_ALT_GPIO;
+
                 /*
                  * The SLPM_* values are normal values + 1 to allow zero to
                  * mean "same as normal".
@@ -180,8 +226,116 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
                 __nmk_gpio_set_pull(nmk_chip, offset, pull);
         }
 
-        __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
-        __nmk_gpio_set_mode(nmk_chip, offset, af);
+        /*
+         * If we've backed up the SLPM registers (glitch workaround), modify
+         * the backups since they will be restored.
+         */
+        if (slpmregs) {
+                if (slpm == NMK_GPIO_SLPM_NOCHANGE)
+                        slpmregs[nmk_chip->bank] |= BIT(offset);
+                else
+                        slpmregs[nmk_chip->bank] &= ~BIT(offset);
+        } else
+                __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
+
+        __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
+}
+
+/*
+ * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
+ *  - Save SLPM registers
+ *  - Set SLPM=0 for the IOs you want to switch and others to 1
+ *  - Configure the GPIO registers for the IOs that are being switched
+ *  - Set IOFORCE=1
+ *  - Modify the AFLSA/B registers for the IOs that are being switched
+ *  - Set IOFORCE=0
+ *  - Restore SLPM registers
+ *  - Any spurious wake up event during switch sequence to be ignored and
+ *    cleared
+ */
+static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
+{
+        int i;
+
+        for (i = 0; i < NUM_BANKS; i++) {
+                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
+                unsigned int temp = slpm[i];
+
+                if (!chip)
+                        break;
+
+                slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
+                writel(temp, chip->addr + NMK_GPIO_SLPC);
+        }
+}
+
+static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
+{
+        int i;
+
+        for (i = 0; i < NUM_BANKS; i++) {
+                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
+
+                if (!chip)
+                        break;
+
+                writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
+        }
+}
+
+static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
+{
+        static unsigned int slpm[NUM_BANKS];
+        unsigned long flags;
+        bool glitch = false;
+        int ret = 0;
+        int i;
+
+        for (i = 0; i < num; i++) {
+                if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
+                        glitch = true;
+                        break;
+                }
+        }
+
+        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
+
+        if (glitch) {
+                memset(slpm, 0xff, sizeof(slpm));
+
+                for (i = 0; i < num; i++) {
+                        int pin = PIN_NUM(cfgs[i]);
+                        int offset = pin % NMK_GPIO_PER_CHIP;
+
+                        if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
+                                slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
+                }
+
+                nmk_gpio_glitch_slpm_init(slpm);
+        }
+
+        for (i = 0; i < num; i++) {
+                struct nmk_gpio_chip *nmk_chip;
+                int pin = PIN_NUM(cfgs[i]);
+
+                nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
+                if (!nmk_chip) {
+                        ret = -EINVAL;
+                        break;
+                }
+
+                spin_lock(&nmk_chip->lock);
+                __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base,
+                                 cfgs[i], sleep, glitch ? slpm : NULL);
+                spin_unlock(&nmk_chip->lock);
+        }
+
+        if (glitch)
+                nmk_gpio_glitch_slpm_restore(slpm);
+
+        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
+
+        return ret;
 }
 
 /**
@@ -200,19 +354,7 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
  */
 int nmk_config_pin(pin_cfg_t cfg, bool sleep)
 {
-        struct nmk_gpio_chip *nmk_chip;
-        int gpio = PIN_NUM(cfg);
-        unsigned long flags;
-
-        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
-        if (!nmk_chip)
-                return -EINVAL;
-
-        spin_lock_irqsave(&nmk_chip->lock, flags);
-        __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg, sleep);
-        spin_unlock_irqrestore(&nmk_chip->lock, flags);
-
-        return 0;
+        return __nmk_config_pins(&cfg, 1, sleep);
 }
 EXPORT_SYMBOL(nmk_config_pin);
 
@@ -226,31 +368,13 @@ EXPORT_SYMBOL(nmk_config_pin);
  */
 int nmk_config_pins(pin_cfg_t *cfgs, int num)
 {
-        int ret = 0;
-        int i;
-
-        for (i = 0; i < num; i++) {
-                ret = nmk_config_pin(cfgs[i], false);
-                if (ret)
-                        break;
-        }
-
-        return ret;
+        return __nmk_config_pins(cfgs, num, false);
 }
 EXPORT_SYMBOL(nmk_config_pins);
 
 int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
 {
-        int ret = 0;
-        int i;
-
-        for (i = 0; i < num; i++) {
-                ret = nmk_config_pin(cfgs[i], true);
-                if (ret)
-                        break;
-        }
-
-        return ret;
+        return __nmk_config_pins(cfgs, num, true);
 }
 EXPORT_SYMBOL(nmk_config_pins_sleep);
 
@@ -277,9 +401,13 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
         if (!nmk_chip)
                 return -EINVAL;
 
-        spin_lock_irqsave(&nmk_chip->lock, flags);
+        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
+        spin_lock(&nmk_chip->lock);
+
         __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
-        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+        spin_unlock(&nmk_chip->lock);
+        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
 
         return 0;
 }
@@ -314,6 +442,15 @@ int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
 }
 
 /* Mode functions */
+/**
+ * nmk_gpio_set_mode() - set the mux mode of a gpio pin
+ * @gpio: pin number
+ * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
+ *             NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
+ *
+ * Sets the mode of the specified pin to one of the alternate functions or
+ * plain GPIO.
+ */
 int nmk_gpio_set_mode(int gpio, int gpio_mode)
 {
         struct nmk_gpio_chip *nmk_chip;
@@ -401,8 +538,20 @@ static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
         }
 }
 
-static int nmk_gpio_irq_modify(struct irq_data *d, enum nmk_gpio_irq_type which,
-                               bool enable)
+static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
+                                int gpio, bool on)
+{
+#ifdef CONFIG_ARCH_U8500
+        if (cpu_is_u8500v2()) {
+                __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base,
+                                    on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
+                                       : NMK_GPIO_SLPM_WAKEUP_DISABLE);
+        }
+#endif
+        __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
+}
+
+static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
 {
         int gpio;
         struct nmk_gpio_chip *nmk_chip;
@@ -415,44 +564,58 @@ static int nmk_gpio_irq_modify(struct irq_data *d, enum nmk_gpio_irq_type which,
         if (!nmk_chip)
                 return -EINVAL;
 
-        spin_lock_irqsave(&nmk_chip->lock, flags);
-        __nmk_gpio_irq_modify(nmk_chip, gpio, which, enable);
-        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
+        spin_lock(&nmk_chip->lock);
+
+        __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable);
+
+        if (!(nmk_chip->real_wake & bitmask))
+                __nmk_gpio_set_wake(nmk_chip, gpio, enable);
+
+        spin_unlock(&nmk_chip->lock);
+        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
 
         return 0;
 }
 
 static void nmk_gpio_irq_mask(struct irq_data *d)
 {
-        nmk_gpio_irq_modify(d, NORMAL, false);
+        nmk_gpio_irq_maskunmask(d, false);
 }
 
 static void nmk_gpio_irq_unmask(struct irq_data *d)
 {
-        nmk_gpio_irq_modify(d, NORMAL, true);
+        nmk_gpio_irq_maskunmask(d, true);
 }
 
 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 {
+        struct irq_desc *desc = irq_to_desc(d->irq);
+        bool enabled = !(desc->status & IRQ_DISABLED);
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
+        u32 bitmask;
         int gpio;
 
         gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
         nmk_chip = irq_data_get_irq_chip_data(d);
         if (!nmk_chip)
                 return -EINVAL;
+        bitmask = nmk_gpio_get_bitmask(gpio);
 
-        spin_lock_irqsave(&nmk_chip->lock, flags);
-#ifdef CONFIG_ARCH_U8500
-        if (cpu_is_u8500v2()) {
-                __nmk_gpio_set_slpm(nmk_chip, gpio,
-                                    on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
-                                       : NMK_GPIO_SLPM_WAKEUP_DISABLE);
-        }
-#endif
-        __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
-        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
+        spin_lock(&nmk_chip->lock);
+
+        if (!enabled)
+                __nmk_gpio_set_wake(nmk_chip, gpio, on);
+
+        if (on)
+                nmk_chip->real_wake |= bitmask;
+        else
+                nmk_chip->real_wake &= ~bitmask;
+
+        spin_unlock(&nmk_chip->lock);
+        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
 
         return 0;
 }
@@ -483,7 +646,7 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
         if (enabled)
                 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
 
-        if (wake)
+        if (enabled || wake)
                 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
 
         nmk_chip->edge_rising &= ~bitmask;
@@ -497,7 +660,7 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
         if (enabled)
                 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
 
-        if (wake)
+        if (enabled || wake)
                 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
 
         spin_unlock_irqrestore(&nmk_chip->lock, flags);
@@ -514,12 +677,11 @@ static struct irq_chip nmk_gpio_irq_chip = {
         .irq_set_wake   = nmk_gpio_irq_set_wake,
 };
 
-static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
+                                   u32 status)
 {
         struct nmk_gpio_chip *nmk_chip;
         struct irq_chip *host_chip = get_irq_chip(irq);
-        unsigned int gpio_irq;
-        u32 pending;
         unsigned int first_irq;
 
         if (host_chip->irq_mask_ack)
@@ -532,29 +694,56 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
         nmk_chip = get_irq_data(irq);
         first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
-        while ( (pending = readl(nmk_chip->addr + NMK_GPIO_IS)) ) {
-                gpio_irq = first_irq + __ffs(pending);
-                generic_handle_irq(gpio_irq);
+        while (status) {
+                int bit = __ffs(status);
+
+                generic_handle_irq(first_irq + bit);
+                status &= ~BIT(bit);
         }
 
         host_chip->irq_unmask(&desc->irq_data);
 }
 
+static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        struct nmk_gpio_chip *nmk_chip = get_irq_data(irq);
+        u32 status = readl(nmk_chip->addr + NMK_GPIO_IS);
+
+        __nmk_gpio_irq_handler(irq, desc, status);
+}
+
+static void nmk_gpio_secondary_irq_handler(unsigned int irq,
+                                           struct irq_desc *desc)
+{
+        struct nmk_gpio_chip *nmk_chip = get_irq_data(irq);
+        u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
+
+        __nmk_gpio_irq_handler(irq, desc, status);
+}
+
 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
 {
         unsigned int first_irq;
         int i;
 
         first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
-        for (i = first_irq; i < first_irq + NMK_GPIO_PER_CHIP; i++) {
+        for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
                 set_irq_chip(i, &nmk_gpio_irq_chip);
                 set_irq_handler(i, handle_edge_irq);
                 set_irq_flags(i, IRQF_VALID);
                 set_irq_chip_data(i, nmk_chip);
                 set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
         }
+
         set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
         set_irq_data(nmk_chip->parent_irq, nmk_chip);
+
+        if (nmk_chip->secondary_parent_irq >= 0) {
+                set_irq_chained_handler(nmk_chip->secondary_parent_irq,
+                                        nmk_gpio_secondary_irq_handler);
+                set_irq_data(nmk_chip->secondary_parent_irq, nmk_chip);
+        }
+
         return 0;
 }
 
@@ -605,6 +794,97 @@ static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
         return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
 }
 
+#ifdef CONFIG_DEBUG_FS
+
+#include <linux/seq_file.h>
+
+static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+        int mode;
+        unsigned                i;
+        unsigned                gpio = chip->base;
+        int                     is_out;
+        struct nmk_gpio_chip *nmk_chip =
+                container_of(chip, struct nmk_gpio_chip, chip);
+        const char *modes[] = {
+                [NMK_GPIO_ALT_GPIO]     = "gpio",
+                [NMK_GPIO_ALT_A]        = "altA",
+                [NMK_GPIO_ALT_B]        = "altB",
+                [NMK_GPIO_ALT_C]        = "altC",
+        };
+
+        for (i = 0; i < chip->ngpio; i++, gpio++) {
+                const char *label = gpiochip_is_requested(chip, i);
+                bool pull;
+                u32 bit = 1 << i;
+
+                if (!label)
+                        continue;
+
+                is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit;
+                pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
+                mode = nmk_gpio_get_mode(gpio);
+                seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
+                        gpio, label,
+                        is_out ? "out" : "in ",
+                        chip->get
+                                ? (chip->get(chip, i) ? "hi" : "lo")
+                                : "?  ",
+                        (mode < 0) ? "unknown" : modes[mode],
+                        pull ? "pull" : "none");
+
+                if (!is_out) {
+                        int             irq = gpio_to_irq(gpio);
+                        struct irq_desc *desc = irq_to_desc(irq);
+
+                        /* This races with request_irq(), set_irq_type(),
+                         * and set_irq_wake() ... but those are "rare".
+                         *
+                         * More significantly, trigger type flags aren't
+                         * currently maintained by genirq.
+                         */
+                        if (irq >= 0 && desc->action) {
+                                char *trigger;
+
+                                switch (desc->status & IRQ_TYPE_SENSE_MASK) {
+                                case IRQ_TYPE_NONE:
+                                        trigger = "(default)";
+                                        break;
+                                case IRQ_TYPE_EDGE_FALLING:
+                                        trigger = "edge-falling";
+                                        break;
+                                case IRQ_TYPE_EDGE_RISING:
+                                        trigger = "edge-rising";
+                                        break;
+                                case IRQ_TYPE_EDGE_BOTH:
+                                        trigger = "edge-both";
+                                        break;
+                                case IRQ_TYPE_LEVEL_HIGH:
+                                        trigger = "level-high";
+                                        break;
+                                case IRQ_TYPE_LEVEL_LOW:
+                                        trigger = "level-low";
+                                        break;
+                                default:
+                                        trigger = "?trigger?";
+                                        break;
+                                }
+
+                                seq_printf(s, " irq-%d %s%s",
+                                        irq, trigger,
+                                        (desc->status & IRQ_WAKEUP)
+                                                ? " wakeup" : "");
+                        }
+                }
+
+                seq_printf(s, "\n");
+        }
+}
+
+#else
+#define nmk_gpio_dbg_show       NULL
+#endif
+
 /* This structure is replicated for each GPIO block allocated at probe time */
 static struct gpio_chip nmk_gpio_template = {
         .direction_input        = nmk_gpio_make_input,
@@ -612,10 +892,64 @@ static struct gpio_chip nmk_gpio_template = {
         .direction_output       = nmk_gpio_make_output,
         .set                    = nmk_gpio_set_output,
         .to_irq                 = nmk_gpio_to_irq,
-        .ngpio                  = NMK_GPIO_PER_CHIP,
+        .dbg_show               = nmk_gpio_dbg_show,
         .can_sleep              = 0,
 };
 
+/*
+ * Called from the suspend/resume path to only keep the real wakeup interrupts
+ * (those that have had set_irq_wake() called on them) as wakeup interrupts,
+ * and not the rest of the interrupts which we needed to have as wakeups for
+ * cpuidle.
+ *
+ * PM ops are not used since this needs to be done at the end, after all the
+ * other drivers are done with their suspend callbacks.
+ */
+void nmk_gpio_wakeups_suspend(void)
+{
+        int i;
+
+        for (i = 0; i < NUM_BANKS; i++) {
+                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
+
+                if (!chip)
+                        break;
+
+                chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC);
+                chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC);
+
+                writel(chip->rwimsc & chip->real_wake,
+                       chip->addr + NMK_GPIO_RWIMSC);
+                writel(chip->fwimsc & chip->real_wake,
+                       chip->addr + NMK_GPIO_FWIMSC);
+
+                if (cpu_is_u8500v2()) {
+                        chip->slpm = readl(chip->addr + NMK_GPIO_SLPC);
+
+                        /* 0 -> wakeup enable */
+                        writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC);
+                }
+        }
+}
+
+void nmk_gpio_wakeups_resume(void)
+{
+        int i;
+
+        for (i = 0; i < NUM_BANKS; i++) {
+                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
+
+                if (!chip)
+                        break;
+
+                writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
+                writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
+
+                if (cpu_is_u8500v2())
+                        writel(chip->slpm, chip->addr + NMK_GPIO_SLPC);
+        }
+}
+
 static int __devinit nmk_gpio_probe(struct platform_device *dev)
 {
         struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
@@ -623,6 +957,7 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
         struct gpio_chip *chip;
         struct resource *res;
         struct clk *clk;
+        int secondary_irq;
         int irq;
         int ret;
 
@@ -641,6 +976,12 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
                 goto out;
         }
 
+        secondary_irq = platform_get_irq(dev, 1);
+        if (secondary_irq >= 0 && !pdata->get_secondary_status) {
+                ret = -EINVAL;
+                goto out;
+        }
+
         if (request_mem_region(res->start, resource_size(res),
                                dev_name(&dev->dev)) == NULL) {
                 ret = -EBUSY;
@@ -664,14 +1005,19 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
          * The virt address in nmk_chip->addr is in the nomadik register space,
          * so we can simply convert the resource address, without remapping
          */
+        nmk_chip->bank = dev->id;
         nmk_chip->clk = clk;
         nmk_chip->addr = io_p2v(res->start);
         nmk_chip->chip = nmk_gpio_template;
         nmk_chip->parent_irq = irq;
+        nmk_chip->secondary_parent_irq = secondary_irq;
+        nmk_chip->get_secondary_status = pdata->get_secondary_status;
+        nmk_chip->set_ioforce = pdata->set_ioforce;
         spin_lock_init(&nmk_chip->lock);
 
         chip = &nmk_chip->chip;
         chip->base = pdata->first_gpio;
+        chip->ngpio = pdata->num_gpio;
         chip->label = pdata->name ?: dev_name(&dev->dev);
         chip->dev = &dev->dev;
         chip->owner = THIS_MODULE;
@@ -680,6 +1026,9 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
         if (ret)
                 goto out_free;
 
+        BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
+
+        nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
         platform_set_drvdata(dev, nmk_chip);
 
         nmk_gpio_init_irq(nmk_chip);
@@ -705,10 +1054,8 @@ static struct platform_driver nmk_gpio_driver = {
         .driver = {
                 .owner = THIS_MODULE,
                 .name = "gpio",
-                },
+        },
         .probe = nmk_gpio_probe,
-        .suspend = NULL, /* to be done */
-        .resume = NULL,
 };
 
 static int __init nmk_gpio_init(void)
diff --git a/arch/arm/plat-nomadik/include/plat/gpio.h b/arch/arm/plat-nomadik/include/plat/gpio.h
index 67b113d639d8..1b9f6f0843d1 100644
--- a/arch/arm/plat-nomadik/include/plat/gpio.h
+++ b/arch/arm/plat-nomadik/include/plat/gpio.h
@@ -75,6 +75,9 @@ extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull);
 extern int nmk_gpio_set_mode(int gpio, int gpio_mode);
 extern int nmk_gpio_get_mode(int gpio);
 
+extern void nmk_gpio_wakeups_suspend(void);
+extern void nmk_gpio_wakeups_resume(void);
+
 /*
  * Platform data to register a block: only the initial gpio/irq number.
  */
@@ -82,6 +85,9 @@ struct nmk_gpio_platform_data {
         char *name;
         int first_gpio;
         int first_irq;
+        int num_gpio;
+        u32 (*get_secondary_status)(unsigned int bank);
+        void (*set_ioforce)(bool enable);
 };
 
 #endif /* __ASM_PLAT_GPIO_H */
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 5f3522314815..078894bc3b9a 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -17,55 +17,123 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 
-static DEFINE_SPINLOCK(gpio_lock);
-static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
-static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)];
+/*
+ * GPIO unit register offsets.
+ */
+#define GPIO_OUT_OFF            0x0000
+#define GPIO_IO_CONF_OFF        0x0004
+#define GPIO_BLINK_EN_OFF       0x0008
+#define GPIO_IN_POL_OFF         0x000c
+#define GPIO_DATA_IN_OFF        0x0010
+#define GPIO_EDGE_CAUSE_OFF     0x0014
+#define GPIO_EDGE_MASK_OFF      0x0018
+#define GPIO_LEVEL_MASK_OFF     0x001c
+
+struct orion_gpio_chip {
+        struct gpio_chip        chip;
+        spinlock_t              lock;
+        void __iomem            *base;
+        unsigned long           valid_input;
+        unsigned long           valid_output;
+        int                     mask_offset;
+        int                     secondary_irq_base;
+};
+
+static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_OUT_OFF;
+}
+
+static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_IO_CONF_OFF;
+}
+
+static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_BLINK_EN_OFF;
+}
+
+static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_IN_POL_OFF;
+}
+
+static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_DATA_IN_OFF;
+}
+
+static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_EDGE_CAUSE_OFF;
+}
+
+static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
+}
+
+static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
+}
+
 
-static inline void __set_direction(unsigned pin, int input)
+static struct orion_gpio_chip orion_gpio_chips[2];
+static int orion_gpio_chip_count;
+
+static inline void
+__set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
 {
         u32 u;
 
-        u = readl(GPIO_IO_CONF(pin));
+        u = readl(GPIO_IO_CONF(ochip));
         if (input)
-                u |= 1 << (pin & 31);
+                u |= 1 << pin;
         else
-                u &= ~(1 << (pin & 31));
-        writel(u, GPIO_IO_CONF(pin));
+                u &= ~(1 << pin);
+        writel(u, GPIO_IO_CONF(ochip));
 }
 
-static void __set_level(unsigned pin, int high)
+static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
 {
         u32 u;
 
-        u = readl(GPIO_OUT(pin));
+        u = readl(GPIO_OUT(ochip));
         if (high)
-                u |= 1 << (pin & 31);
+                u |= 1 << pin;
         else
-                u &= ~(1 << (pin & 31));
-        writel(u, GPIO_OUT(pin));
+                u &= ~(1 << pin);
+        writel(u, GPIO_OUT(ochip));
 }
 
-static inline void __set_blinking(unsigned pin, int blink)
+static inline void
+__set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
 {
         u32 u;
 
-        u = readl(GPIO_BLINK_EN(pin));
+        u = readl(GPIO_BLINK_EN(ochip));
         if (blink)
-                u |= 1 << (pin & 31);
+                u |= 1 << pin;
         else
-                u &= ~(1 << (pin & 31));
-        writel(u, GPIO_BLINK_EN(pin));
+                u &= ~(1 << pin);
+        writel(u, GPIO_BLINK_EN(ochip));
 }
 
-static inline int orion_gpio_is_valid(unsigned pin, int mode)
+static inline int
+orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
 {
-        if (pin < GPIO_MAX) {
-                if ((mode & GPIO_INPUT_OK) && !test_bit(pin, gpio_valid_input))
-                        goto err_out;
-                if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, gpio_valid_output))
-                        goto err_out;
-                return true;
-        }
+        if (pin >= ochip->chip.ngpio)
+                goto err_out;
+
+        if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
+                goto err_out;
+
+        if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
+                goto err_out;
+
+        return 1;
 
 err_out:
         pr_debug("%s: invalid GPIO %d\n", __func__, pin);
@@ -75,134 +143,155 @@ err_out:
 /*
  * GENERIC_GPIO primitives.
  */
+static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
+{
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
+
+        if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
+            orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
+                return 0;
+
+        return -EINVAL;
+}
+
 static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
 {
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
         unsigned long flags;
 
-        if (!orion_gpio_is_valid(pin, GPIO_INPUT_OK))
+        if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
                 return -EINVAL;
 
-        spin_lock_irqsave(&gpio_lock, flags);
-
-        /* Configure GPIO direction. */
-        __set_direction(pin, 1);
-
-        spin_unlock_irqrestore(&gpio_lock, flags);
+        spin_lock_irqsave(&ochip->lock, flags);
+        __set_direction(ochip, pin, 1);
+        spin_unlock_irqrestore(&ochip->lock, flags);
 
         return 0;
 }
 
-static int orion_gpio_get_value(struct gpio_chip *chip, unsigned pin)
+static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
 {
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
         int val;
 
-        if (readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)))
-                val = readl(GPIO_DATA_IN(pin)) ^ readl(GPIO_IN_POL(pin));
-        else
-                val = readl(GPIO_OUT(pin));
+        if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
+                val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
+        } else {
+                val = readl(GPIO_OUT(ochip));
+        }
 
-        return (val >> (pin & 31)) & 1;
+        return (val >> pin) & 1;
 }
 
-static int orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
-        int value)
+static int
+orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
 {
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
         unsigned long flags;
 
-        if (!orion_gpio_is_valid(pin, GPIO_OUTPUT_OK))
+        if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
                 return -EINVAL;
 
-        spin_lock_irqsave(&gpio_lock, flags);
-
-        /* Disable blinking. */
-        __set_blinking(pin, 0);
-
-        /* Configure GPIO output value. */
-        __set_level(pin, value);
-
-        /* Configure GPIO direction. */
-        __set_direction(pin, 0);
-
-        spin_unlock_irqrestore(&gpio_lock, flags);
+        spin_lock_irqsave(&ochip->lock, flags);
+        __set_blinking(ochip, pin, 0);
+        __set_level(ochip, pin, value);
+        __set_direction(ochip, pin, 0);
+        spin_unlock_irqrestore(&ochip->lock, flags);
 
         return 0;
 }
 
-static void orion_gpio_set_value(struct gpio_chip *chip, unsigned pin,
-        int value)
+static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
 {
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
         unsigned long flags;
 
-        spin_lock_irqsave(&gpio_lock, flags);
-
-        /* Configure GPIO output value. */
-        __set_level(pin, value);
-
-        spin_unlock_irqrestore(&gpio_lock, flags);
+        spin_lock_irqsave(&ochip->lock, flags);
+        __set_level(ochip, pin, value);
+        spin_unlock_irqrestore(&ochip->lock, flags);
 }
 
-static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
+static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
 {
-        if (orion_gpio_is_valid(pin, GPIO_INPUT_OK) ||
-            orion_gpio_is_valid(pin, GPIO_OUTPUT_OK))
-                return 0;
-        return -EINVAL;
-}
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
 
-static struct gpio_chip orion_gpiochip = {
-        .label                  = "orion_gpio",
-        .direction_input        = orion_gpio_direction_input,
-        .get                    = orion_gpio_get_value,
-        .direction_output       = orion_gpio_direction_output,
-        .set                    = orion_gpio_set_value,
-        .request                = orion_gpio_request,
-        .base                   = 0,
-        .ngpio                  = GPIO_MAX,
-        .can_sleep              = 0,
-};
-
-void __init orion_gpio_init(void)
-{
-        gpiochip_add(&orion_gpiochip);
+        return ochip->secondary_irq_base + pin;
 }
 
+
 /*
  * Orion-specific GPIO API extensions.
  */
+static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
+{
+        int i;
+
+        for (i = 0; i < orion_gpio_chip_count; i++) {
+                struct orion_gpio_chip *ochip = orion_gpio_chips + i;
+                struct gpio_chip *chip = &ochip->chip;
+
+                if (pin >= chip->base && pin < chip->base + chip->ngpio)
+                        return ochip;
+        }
+
+        return NULL;
+}
+
 void __init orion_gpio_set_unused(unsigned pin)
 {
+        struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
+
+        if (ochip == NULL)
+                return;
+
+        pin -= ochip->chip.base;
+
         /* Configure as output, drive low. */
-        __set_level(pin, 0);
-        __set_direction(pin, 0);
+        __set_level(ochip, pin, 0);
+        __set_direction(ochip, pin, 0);
 }
 
 void __init orion_gpio_set_valid(unsigned pin, int mode)
 {
+        struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
+
+        if (ochip == NULL)
+                return;
+
+        pin -= ochip->chip.base;
+
         if (mode == 1)
                 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
+
         if (mode & GPIO_INPUT_OK)
-                __set_bit(pin, gpio_valid_input);
+                __set_bit(pin, &ochip->valid_input);
         else
-                __clear_bit(pin, gpio_valid_input);
+                __clear_bit(pin, &ochip->valid_input);
+
         if (mode & GPIO_OUTPUT_OK)
-                __set_bit(pin, gpio_valid_output);
+                __set_bit(pin, &ochip->valid_output);
         else
-                __clear_bit(pin, gpio_valid_output);
+                __clear_bit(pin, &ochip->valid_output);
 }
 
 void orion_gpio_set_blink(unsigned pin, int blink)
 {
+        struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
         unsigned long flags;
 
-        spin_lock_irqsave(&gpio_lock, flags);
+        if (ochip == NULL)
+                return;
 
-        /* Set output value to zero. */
-        __set_level(pin, 0);
-
-        /* Set blinking. */
-        __set_blinking(pin, blink);
-
-        spin_unlock_irqrestore(&gpio_lock, flags);
+        spin_lock_irqsave(&ochip->lock, flags);
+        __set_level(ochip, pin, 0);
+        __set_blinking(ochip, pin, blink);
+        spin_unlock_irqrestore(&ochip->lock, flags);
 }
 EXPORT_SYMBOL(orion_gpio_set_blink);
 
@@ -234,59 +323,78 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
  ****************************************************************************/
 static void gpio_irq_ack(struct irq_data *d)
 {
-        int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
+        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
+        int type;
+
+        type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
-                int pin = irq_to_gpio(d->irq);
-                writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
+                int pin = d->irq - ochip->secondary_irq_base;
+
+                writel(~(1 << pin), GPIO_EDGE_CAUSE(ochip));
         }
 }
 
 static void gpio_irq_mask(struct irq_data *d)
 {
-        int pin = irq_to_gpio(d->irq);
-        int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
-        u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
-                GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
-        u32 u = readl(reg);
-        u &= ~(1 << (pin & 31));
-        writel(u, reg);
+        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
+        int type;
+        void __iomem *reg;
+        int pin;
+
+        type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
+        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+                reg = GPIO_EDGE_MASK(ochip);
+        else
+                reg = GPIO_LEVEL_MASK(ochip);
+
+        pin = d->irq - ochip->secondary_irq_base;
+
+        writel(readl(reg) & ~(1 << pin), reg);
 }
 
 static void gpio_irq_unmask(struct irq_data *d)
 {
-        int pin = irq_to_gpio(d->irq);
-        int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
-        u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
-                GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
-        u32 u = readl(reg);
-        u |= 1 << (pin & 31);
-        writel(u, reg);
+        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
+        int type;
+        void __iomem *reg;
+        int pin;
+
+        type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
+        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+                reg = GPIO_EDGE_MASK(ochip);
+        else
+                reg = GPIO_LEVEL_MASK(ochip);
+
+        pin = d->irq - ochip->secondary_irq_base;
+
+        writel(readl(reg) | (1 << pin), reg);
 }
 
 static int gpio_irq_set_type(struct irq_data *d, u32 type)
 {
-        int pin = irq_to_gpio(d->irq);
-        struct irq_desc *desc;
+        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
+        int pin;
         u32 u;
 
-        u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31));
+        pin = d->irq - ochip->secondary_irq_base;
+
+        u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
         if (!u) {
                 printk(KERN_ERR "orion gpio_irq_set_type failed "
                                 "(irq %d, pin %d).\n", d->irq, pin);
                 return -EINVAL;
         }
 
-        desc = irq_desc + d->irq;
-
         /*
          * Set edge/level type.
          */
         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
-                desc->handle_irq = handle_edge_irq;
+                set_irq_handler(d->irq, handle_edge_irq);
         } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
-                desc->handle_irq = handle_level_irq;
+                set_irq_handler(d->irq, handle_level_irq);
         } else {
-                printk(KERN_ERR "failed to set irq=%d (type=%d)\n", d->irq, type);
+                printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
+                       d->irq, type);
                 return -EINVAL;
         }
 
@@ -294,31 +402,29 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
          * Configure interrupt polarity.
          */
         if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
-                u = readl(GPIO_IN_POL(pin));
-                u &= ~(1 << (pin & 31));
-                writel(u, GPIO_IN_POL(pin));
+                u = readl(GPIO_IN_POL(ochip));
+                u &= ~(1 << pin);
+                writel(u, GPIO_IN_POL(ochip));
         } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
-                u = readl(GPIO_IN_POL(pin));
-                u |= 1 << (pin & 31);
-                writel(u, GPIO_IN_POL(pin));
+                u = readl(GPIO_IN_POL(ochip));
+                u |= 1 << pin;
+                writel(u, GPIO_IN_POL(ochip));
         } else if (type == IRQ_TYPE_EDGE_BOTH) {
                 u32 v;
 
-                v = readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin));
+                v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
 
                 /*
                  * set initial polarity based on current input level
                  */
-                u = readl(GPIO_IN_POL(pin));
-                if (v & (1 << (pin & 31)))
-                        u |= 1 << (pin & 31);           /* falling */
+                u = readl(GPIO_IN_POL(ochip));
+                if (v & (1 << pin))
+                        u |= 1 << pin;          /* falling */
                 else
-                        u &= ~(1 << (pin & 31));        /* rising */
-                writel(u, GPIO_IN_POL(pin));
+                        u &= ~(1 << pin);       /* rising */
+                writel(u, GPIO_IN_POL(ochip));
         }
 
-        desc->status = (desc->status & ~IRQ_TYPE_SENSE_MASK) | type;
-
         return 0;
 }
 
@@ -330,29 +436,87 @@ struct irq_chip orion_gpio_irq_chip = {
         .irq_set_type   = gpio_irq_set_type,
 };
 
+void __init orion_gpio_init(int gpio_base, int ngpio,
+                            u32 base, int mask_offset, int secondary_irq_base)
+{
+        struct orion_gpio_chip *ochip;
+        int i;
+
+        if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
+                return;
+
+        ochip = orion_gpio_chips + orion_gpio_chip_count;
+        ochip->chip.label = "orion_gpio";
+        ochip->chip.request = orion_gpio_request;
+        ochip->chip.direction_input = orion_gpio_direction_input;
+        ochip->chip.get = orion_gpio_get;
+        ochip->chip.direction_output = orion_gpio_direction_output;
+        ochip->chip.set = orion_gpio_set;
+        ochip->chip.to_irq = orion_gpio_to_irq;
+        ochip->chip.base = gpio_base;
+        ochip->chip.ngpio = ngpio;
+        ochip->chip.can_sleep = 0;
+        spin_lock_init(&ochip->lock);
+        ochip->base = (void __iomem *)base;
+        ochip->valid_input = 0;
+        ochip->valid_output = 0;
+        ochip->mask_offset = mask_offset;
+        ochip->secondary_irq_base = secondary_irq_base;
+
+        gpiochip_add(&ochip->chip);
+
+        orion_gpio_chip_count++;
+
+        /*
+         * Mask and clear GPIO interrupts.
+         */
+        writel(0, GPIO_EDGE_CAUSE(ochip));
+        writel(0, GPIO_EDGE_MASK(ochip));
+        writel(0, GPIO_LEVEL_MASK(ochip));
+
+        for (i = 0; i < ngpio; i++) {
+                unsigned int irq = secondary_irq_base + i;
+
+                set_irq_chip(irq, &orion_gpio_irq_chip);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_chip_data(irq, ochip);
+                irq_desc[irq].status |= IRQ_LEVEL;
+                set_irq_flags(irq, IRQF_VALID);
+        }
+}
+
 void orion_gpio_irq_handler(int pinoff)
 {
+        struct orion_gpio_chip *ochip;
         u32 cause;
-        int pin;
+        int i;
 
-        cause = readl(GPIO_DATA_IN(pinoff)) & readl(GPIO_LEVEL_MASK(pinoff));
-        cause |= readl(GPIO_EDGE_CAUSE(pinoff)) & readl(GPIO_EDGE_MASK(pinoff));
+        ochip = orion_gpio_chip_find(pinoff);
+        if (ochip == NULL)
+                return;
 
-        for (pin = pinoff; pin < pinoff + 8; pin++) {
-                int irq = gpio_to_irq(pin);
-                struct irq_desc *desc = irq_desc + irq;
+        cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
+        cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
 
-                if (!(cause & (1 << (pin & 31))))
+        for (i = 0; i < ochip->chip.ngpio; i++) {
+                int irq;
+                struct irq_desc *desc;
+
+                irq = ochip->secondary_irq_base + i;
+
+                if (!(cause & (1 << i)))
                         continue;
 
+                desc = irq_desc + irq;
                 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
                         /* Swap polarity (race with GPIO line) */
                         u32 polarity;
 
-                        polarity = readl(GPIO_IN_POL(pin));
-                        polarity ^= 1 << (pin & 31);
-                        writel(polarity, GPIO_IN_POL(pin));
+                        polarity = readl(GPIO_IN_POL(ochip));
+                        polarity ^= 1 << i;
+                        writel(polarity, GPIO_IN_POL(ochip));
                 }
+
                 desc_handle_irq(irq, desc);
         }
 }
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index 07c430fdc9ef..5578b9803fc6 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -12,6 +12,7 @@
 #define __PLAT_GPIO_H
 
 #include <linux/init.h>
+#include <asm-generic/gpio.h>
 
 /*
  * GENERIC_GPIO primitives.
@@ -19,6 +20,7 @@
 #define gpio_get_value  __gpio_get_value
 #define gpio_set_value  __gpio_set_value
 #define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
 
 /*
  * Orion-specific GPIO API extensions.
@@ -31,7 +33,8 @@ void orion_gpio_set_blink(unsigned pin, int blink);
 void orion_gpio_set_valid(unsigned pin, int mode);
 
 /* Initialize gpiolib. */
-void __init orion_gpio_init(void);
+void __init orion_gpio_init(int gpio_base, int ngpio,
+                            u32 base, int mask_offset, int secondary_irq_base);
 
 /*
  * GPIO interrupt handling.
diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h
index c06ca35f3613..4d5f1f6e18df 100644
--- a/arch/arm/plat-orion/include/plat/time.h
+++ b/arch/arm/plat-orion/include/plat/time.h
@@ -11,7 +11,10 @@
 #ifndef __PLAT_TIME_H
 #define __PLAT_TIME_H
 
-void orion_time_init(unsigned int irq, unsigned int tclk);
+void orion_time_set_base(u32 timer_base);
+
+void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask,
+                     unsigned int irq, unsigned int tclk);
 
 
 #endif
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index c3da2478b2aa..742b0323c57b 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -18,28 +18,42 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <asm/sched_clock.h>
-#include <asm/mach/time.h>
-#include <mach/bridge-regs.h>
-#include <mach/hardware.h>
 
 /*
- * Number of timer ticks per jiffy.
+ * MBus bridge block registers.
  */
-static u32 ticks_per_jiffy;
+#define BRIDGE_CAUSE_OFF        0x0110
+#define BRIDGE_MASK_OFF         0x0114
+#define  BRIDGE_INT_TIMER0       0x0002
+#define  BRIDGE_INT_TIMER1       0x0004
 
 
 /*
  * Timer block registers.
  */
-#define TIMER_CTRL              (TIMER_VIRT_BASE + 0x0000)
-#define  TIMER0_EN              0x0001
-#define  TIMER0_RELOAD_EN       0x0002
-#define  TIMER1_EN              0x0004
-#define  TIMER1_RELOAD_EN       0x0008
-#define TIMER0_RELOAD           (TIMER_VIRT_BASE + 0x0010)
-#define TIMER0_VAL              (TIMER_VIRT_BASE + 0x0014)
-#define TIMER1_RELOAD           (TIMER_VIRT_BASE + 0x0018)
-#define TIMER1_VAL              (TIMER_VIRT_BASE + 0x001c)
+#define TIMER_CTRL_OFF          0x0000
+#define  TIMER0_EN               0x0001
+#define  TIMER0_RELOAD_EN        0x0002
+#define  TIMER1_EN               0x0004
+#define  TIMER1_RELOAD_EN        0x0008
+#define TIMER0_RELOAD_OFF       0x0010
+#define TIMER0_VAL_OFF          0x0014
+#define TIMER1_RELOAD_OFF       0x0018
+#define TIMER1_VAL_OFF          0x001c
+
+
+/*
+ * SoC-specific data.
+ */
+static void __iomem *bridge_base;
+static u32 bridge_timer1_clr_mask;
+static void __iomem *timer_base;
+
+
+/*
+ * Number of timer ticks per jiffy.
+ */
+static u32 ticks_per_jiffy;
 
 
 /*
@@ -50,14 +64,14 @@ static DEFINE_CLOCK_DATA(cd);
 
 unsigned long long notrace sched_clock(void)
 {
-        u32 cyc = 0xffffffff - readl(TIMER0_VAL);
+        u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
         return cyc_to_sched_clock(&cd, cyc, (u32)~0);
 }
 
 
 static void notrace orion_update_sched_clock(void)
 {
-        u32 cyc = 0xffffffff - readl(TIMER0_VAL);
+        u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
         update_sched_clock(&cd, cyc, (u32)~0);
 }
 
@@ -71,7 +85,7 @@ static void __init setup_sched_clock(unsigned long tclk)
  */
 static cycle_t orion_clksrc_read(struct clocksource *cs)
 {
-        return 0xffffffff - readl(TIMER0_VAL);
+        return 0xffffffff - readl(timer_base + TIMER0_VAL_OFF);
 }
 
 static struct clocksource orion_clksrc = {
@@ -101,23 +115,23 @@ orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
         /*
          * Clear and enable clockevent timer interrupt.
          */
-        writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
+        writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
 
-        u = readl(BRIDGE_MASK);
+        u = readl(bridge_base + BRIDGE_MASK_OFF);
         u |= BRIDGE_INT_TIMER1;
-        writel(u, BRIDGE_MASK);
+        writel(u, bridge_base + BRIDGE_MASK_OFF);
 
         /*
          * Setup new clockevent timer value.
          */
-        writel(delta, TIMER1_VAL);
+        writel(delta, timer_base + TIMER1_VAL_OFF);
 
         /*
          * Enable the timer.
          */
-        u = readl(TIMER_CTRL);
+        u = readl(timer_base + TIMER_CTRL_OFF);
         u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
-        writel(u, TIMER_CTRL);
+        writel(u, timer_base + TIMER_CTRL_OFF);
 
         local_irq_restore(flags);
 
@@ -135,37 +149,38 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
                 /*
                  * Setup timer to fire at 1/HZ intervals.
                  */
-                writel(ticks_per_jiffy - 1, TIMER1_RELOAD);
-                writel(ticks_per_jiffy - 1, TIMER1_VAL);
+                writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
+                writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
 
                 /*
                  * Enable timer interrupt.
                  */
-                u = readl(BRIDGE_MASK);
-                writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK);
+                u = readl(bridge_base + BRIDGE_MASK_OFF);
+                writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
 
                 /*
                  * Enable timer.
                  */
-                u = readl(TIMER_CTRL);
-                writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL);
+                u = readl(timer_base + TIMER_CTRL_OFF);
+                writel(u | TIMER1_EN | TIMER1_RELOAD_EN,
+                       timer_base + TIMER_CTRL_OFF);
         } else {
                 /*
                  * Disable timer.
                  */
-                u = readl(TIMER_CTRL);
-                writel(u & ~TIMER1_EN, TIMER_CTRL);
+                u = readl(timer_base + TIMER_CTRL_OFF);
+                writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
 
                 /*
                  * Disable timer interrupt.
                  */
-                u = readl(BRIDGE_MASK);
-                writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK);
+                u = readl(bridge_base + BRIDGE_MASK_OFF);
+                writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
 
                 /*
                  * ACK pending timer interrupt.
                  */
-                writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
+                writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
 
         }
         local_irq_restore(flags);
@@ -185,7 +200,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
         /*
          * ACK timer interrupt and call event handler.
          */
-        writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
+        writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
         orion_clkevt.event_handler(&orion_clkevt);
 
         return IRQ_HANDLED;
@@ -197,31 +212,45 @@ static struct irqaction orion_timer_irq = {
         .handler        = orion_timer_interrupt
 };
 
-void __init orion_time_init(unsigned int irq, unsigned int tclk)
+void __init
+orion_time_set_base(u32 _timer_base)
+{
+        timer_base = (void __iomem *)_timer_base;
+}
+
+void __init
+orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
+                unsigned int irq, unsigned int tclk)
 {
         u32 u;
 
+        /*
+         * Set SoC-specific data.
+         */
+        bridge_base = (void __iomem *)_bridge_base;
+        bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
+
         ticks_per_jiffy = (tclk + HZ/2) / HZ;
 
         /*
-         * Set scale and timer for sched_clock
+         * Set scale and timer for sched_clock.
          */
         setup_sched_clock(tclk);
 
         /*
          * Setup free-running clocksource timer (interrupts
-         * disabled.)
+         * disabled).
          */
-        writel(0xffffffff, TIMER0_VAL);
-        writel(0xffffffff, TIMER0_RELOAD);
-        u = readl(BRIDGE_MASK);
-        writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
-        u = readl(TIMER_CTRL);
-        writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
+        writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
+        writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
+        u = readl(bridge_base + BRIDGE_MASK_OFF);
+        writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
+        u = readl(timer_base + TIMER_CTRL_OFF);
+        writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
         clocksource_register_hz(&orion_clksrc, tclk);
 
         /*
-         * Setup clockevent timer (interrupt-driven.)
+         * Setup clockevent timer (interrupt-driven).
          */
         setup_irq(irq, &orion_timer_irq);
         orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index eb105e61c746..d9c4096ebf45 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -56,13 +56,6 @@ config S3C24XX_DCLK
         help
           Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
 
-config S3C24XX_PWM
-        bool "PWM device support"
-        select HAVE_PWM
-        help
-          Support for exporting the PWM timer blocks via the pwm device
-          system.
-
 # gpio configurations
 
 config S3C24XX_GPIO_EXTRA
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 557f8c507f6d..849229716586 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -7,10 +7,10 @@
 
 config PLAT_S5P
         bool
-        depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310)
+        depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4)
         default y
-        select ARM_VIC if !ARCH_S5PV310
-        select ARM_GIC if ARCH_S5PV310
+        select ARM_VIC if !ARCH_EXYNOS4
+        select ARM_GIC if ARCH_EXYNOS4
         select NO_IOPORT
         select ARCH_REQUIRE_GPIOLIB
         select S3C_GPIO_TRACK
@@ -37,11 +37,16 @@ config S5P_GPIO_INT
         help
           Common code for the GPIO interrupts (other than external interrupts.)
 
+config S5P_HRT
+        bool
+        help
+          Use the High Resolution timer support
+
 comment "System MMU"
 
 config S5P_SYSTEM_MMU
         bool "S5P SYSTEM MMU"
-        depends on ARCH_S5PV310
+        depends on ARCH_EXYNOS4
         help
           Say Y here if you want to enable System MMU
 
@@ -60,6 +65,11 @@ config S5P_DEV_FIMC2
         help
           Compile in platform device definitions for FIMC controller 2
 
+config S5P_DEV_FIMC3
+        bool
+        help
+          Compile in platform device definitions for FIMC controller 3
+
 config S5P_DEV_ONENAND
         bool
         help
@@ -74,3 +84,8 @@ config S5P_DEV_CSIS1
         bool
         help
           Compile in platform device definitions for MIPI-CSIS channel 1
+
+config S5P_SETUP_MIPIPHY
+        bool
+        help
+          Compile in common setup code for MIPI-CSIS and MIPI-DSIM devices
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 4bd5cf908977..42afff7f60be 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -22,12 +22,15 @@ obj-$(CONFIG_S5P_GPIO_INT)	+= irq-gpioint.o
 obj-$(CONFIG_S5P_SYSTEM_MMU)    += sysmmu.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_PM)                += irq-pm.o
+obj-$(CONFIG_S5P_HRT)           += s5p-time.o
 
 # devices
 
 obj-$(CONFIG_S5P_DEV_FIMC0)     += dev-fimc0.o
 obj-$(CONFIG_S5P_DEV_FIMC1)     += dev-fimc1.o
 obj-$(CONFIG_S5P_DEV_FIMC2)     += dev-fimc2.o
+obj-$(CONFIG_S5P_DEV_FIMC3)     += dev-fimc3.o
 obj-$(CONFIG_S5P_DEV_ONENAND)   += dev-onenand.o
 obj-$(CONFIG_S5P_DEV_CSIS0)     += dev-csis0.o
 obj-$(CONFIG_S5P_DEV_CSIS1)     += dev-csis1.o
+obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index 047d31c1bbd8..c3bfe9b13acf 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -1,7 +1,7 @@
 /* linux/arch/arm/plat-s5p/cpu.c
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * S5P CPU Support
  *
@@ -12,17 +12,20 @@
 
 #include <linux/init.h>
 #include <linux/module.h>
-#include <mach/map.h>
+
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+
+#include <mach/map.h>
 #include <mach/regs-clock.h>
+
 #include <plat/cpu.h>
 #include <plat/s5p6440.h>
 #include <plat/s5p6442.h>
 #include <plat/s5p6450.h>
 #include <plat/s5pc100.h>
 #include <plat/s5pv210.h>
-#include <plat/s5pv310.h>
+#include <plat/exynos4.h>
 
 /* table of supported CPUs */
 
@@ -31,7 +34,7 @@ static const char name_s5p6442[] = "S5P6442";
 static const char name_s5p6450[] = "S5P6450";
 static const char name_s5pc100[] = "S5PC100";
 static const char name_s5pv210[] = "S5PV210/S5PC110";
-static const char name_s5pv310[] = "S5PV310";
+static const char name_exynos4210[] = "EXYNOS4210";
 
 static struct cpu_table cpu_ids[] __initdata = {
         {
@@ -75,13 +78,13 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .init           = s5pv210_init,
                 .name           = name_s5pv210,
         }, {
-                .idcode         = 0x43200000,
+                .idcode         = 0x43210000,
                 .idmask         = 0xfffff000,
-                .map_io         = s5pv310_map_io,
-                .init_clocks    = s5pv310_init_clocks,
-                .init_uarts     = s5pv310_init_uarts,
-                .init           = s5pv310_init,
-                .name           = name_s5pv310,
+                .map_io         = exynos4_map_io,
+                .init_clocks    = exynos4_init_clocks,
+                .init_uarts     = exynos4_init_uarts,
+                .init           = exynos4_init,
+                .name           = name_exynos4210,
         },
 };
 
diff --git a/arch/arm/plat-s5p/dev-csis0.c b/arch/arm/plat-s5p/dev-csis0.c
index dfab1c85f54f..e3aabef5e347 100644
--- a/arch/arm/plat-s5p/dev-csis0.c
+++ b/arch/arm/plat-s5p/dev-csis0.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 Samsung Electronics
+ * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
  *
  * S5P series device definition for MIPI-CSIS channel 0
  *
diff --git a/arch/arm/plat-s5p/dev-csis1.c b/arch/arm/plat-s5p/dev-csis1.c
index e3053f27fbbf..08b91b580207 100644
--- a/arch/arm/plat-s5p/dev-csis1.c
+++ b/arch/arm/plat-s5p/dev-csis1.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 Samsung Electronics
+ * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
  *
  * S5P series device definition for MIPI-CSIS channel 1
  *
diff --git a/arch/arm/plat-s5p/dev-fimc3.c b/arch/arm/plat-s5p/dev-fimc3.c
new file mode 100644
index 000000000000..ef31beca386c
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-fimc3.c
@@ -0,0 +1,43 @@
+/* linux/arch/arm/plat-s5p/dev-fimc3.c
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * Base S5P FIMC3 resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <mach/map.h>
+
+static struct resource s5p_fimc3_resource[] = {
+        [0] = {
+                .start  = S5P_PA_FIMC3,
+                .end    = S5P_PA_FIMC3 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_FIMC3,
+                .end    = IRQ_FIMC3,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 s5p_fimc3_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device s5p_device_fimc3 = {
+        .name           = "s5p-fimc",
+        .id             = 3,
+        .num_resources  = ARRAY_SIZE(s5p_fimc3_resource),
+        .resource       = s5p_fimc3_resource,
+        .dev            = {
+                .dma_mask               = &s5p_fimc3_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
diff --git a/arch/arm/plat-s5p/include/plat/camport.h b/arch/arm/plat-s5p/include/plat/camport.h
new file mode 100644
index 000000000000..71688c8ba288
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/camport.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *
+ * S5P series camera interface helper functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef PLAT_S5P_CAMPORT_H_
+#define PLAT_S5P_CAMPORT_H_ __FILE__
+
+enum s5p_camport_id {
+        S5P_CAMPORT_A,
+        S5P_CAMPORT_B,
+};
+
+/*
+ * The helper functions to configure GPIO for the camera parallel bus.
+ * The camera port can be multiplexed with any FIMC entity, even multiple
+ * FIMC entities are allowed to be attached to a single port simultaneously.
+ * These functions are to be used in the board setup code.
+ */
+int s5pv210_fimc_setup_gpio(enum s5p_camport_id id);
+int exynos4_fimc_setup_gpio(enum s5p_camport_id id);
+
+#endif
diff --git a/arch/arm/plat-s5p/include/plat/csis.h b/arch/arm/plat-s5p/include/plat/csis.h
deleted file mode 100644
index 51e308c7981d..000000000000
--- a/arch/arm/plat-s5p/include/plat/csis.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) 2010 Samsung Electronics
- *
- * S5P series MIPI CSI slave device support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef PLAT_S5P_CSIS_H_
-#define PLAT_S5P_CSIS_H_ __FILE__
-
-/**
- * struct s5p_platform_mipi_csis - platform data for MIPI-CSIS
- * @clk_rate: bus clock frequency
- * @lanes: number of data lanes used
- * @alignment: data alignment in bits
- * @hs_settle: HS-RX settle time
- */
-struct s5p_platform_mipi_csis {
-        unsigned long clk_rate;
-        u8 lanes;
-        u8 alignment;
-        u8 hs_settle;
-};
-
-#endif /* PLAT_S5P_CSIS_H_ */
diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-s5p/include/plat/exynos4.h
new file mode 100644
index 000000000000..907caab53dcf
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/exynos4.h
@@ -0,0 +1,34 @@
+/* linux/arch/arm/plat-s5p/include/plat/exynos4.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Header file for exynos4 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Common init code for EXYNOS4 related SoCs */
+
+extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void exynos4_register_clocks(void);
+extern void exynos4_setup_clocks(void);
+
+#ifdef CONFIG_CPU_EXYNOS4210
+
+extern  int exynos4_init(void);
+extern void exynos4_init_irq(void);
+extern void exynos4_map_io(void);
+extern void exynos4_init_clocks(int xtal);
+extern struct sys_timer exynos4_timer;
+
+#define exynos4_init_uarts exynos4_common_init_uarts
+
+#else
+#define exynos4_init_clocks NULL
+#define exynos4_init_uarts NULL
+#define exynos4_map_io NULL
+#define exynos4_init NULL
+#endif
diff --git a/arch/arm/plat-s5p/include/plat/mipi_csis.h b/arch/arm/plat-s5p/include/plat/mipi_csis.h
new file mode 100644
index 000000000000..9bd254c5ed22
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/mipi_csis.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
+ *
+ * S5P series MIPI CSI slave device support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef PLAT_S5P_MIPI_CSIS_H_
+#define PLAT_S5P_MIPI_CSIS_H_ __FILE__
+
+struct platform_device;
+
+/**
+ * struct s5p_platform_mipi_csis - platform data for S5P MIPI-CSIS driver
+ * @clk_rate: bus clock frequency
+ * @lanes: number of data lanes used
+ * @alignment: data alignment in bits
+ * @hs_settle: HS-RX settle time
+ * @fixed_phy_vdd: false to enable external D-PHY regulator management in the
+ *                 driver or true in case this regulator has no enable function
+ * @phy_enable: pointer to a callback controlling D-PHY enable/reset
+ */
+struct s5p_platform_mipi_csis {
+        unsigned long clk_rate;
+        u8 lanes;
+        u8 alignment;
+        u8 hs_settle;
+        bool fixed_phy_vdd;
+        int (*phy_enable)(struct platform_device *pdev, bool on);
+};
+
+/**
+ * s5p_csis_phy_enable - global MIPI-CSI receiver D-PHY control
+ * @pdev: MIPI-CSIS platform device
+ * @on: true to enable D-PHY and deassert its reset
+ *      false to disable D-PHY
+ */
+int s5p_csis_phy_enable(struct platform_device *pdev, bool on);
+
+#endif /* PLAT_S5P_MIPI_CSIS_H_ */
diff --git a/arch/arm/plat-s5p/include/plat/s5p-time.h b/arch/arm/plat-s5p/include/plat/s5p-time.h
new file mode 100644
index 000000000000..575e88109db8
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/s5p-time.h
@@ -0,0 +1,40 @@
+/* linux/arch/arm/plat-s5p/include/plat/s5p-time.h
+ *
+ * Copyright 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Header file for s5p time support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_S5P_TIME_H
+#define __ASM_PLAT_S5P_TIME_H __FILE__
+
+/* S5P HR-Timer Clock mode */
+enum s5p_timer_mode {
+        S5P_PWM0,
+        S5P_PWM1,
+        S5P_PWM2,
+        S5P_PWM3,
+        S5P_PWM4,
+};
+
+struct s5p_timer_source {
+        unsigned int event_id;
+        unsigned int source_id;
+};
+
+/* Be able to sleep for atleast 4 seconds (usually more) */
+#define S5PTIMER_MIN_RANGE      4
+
+#define TCNT_MAX                0xffffffff
+#define NON_PERIODIC            0
+#define PERIODIC                1
+
+extern void __init s5p_set_timer_source(enum s5p_timer_mode event,
+                                        enum s5p_timer_mode source);
+extern  struct sys_timer s5p_timer;
+#endif /* __ASM_PLAT_S5P_TIME_H */
diff --git a/arch/arm/plat-s5p/include/plat/s5pv310.h b/arch/arm/plat-s5p/include/plat/s5pv310.h
deleted file mode 100644
index 769c991ceb37..000000000000
--- a/arch/arm/plat-s5p/include/plat/s5pv310.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* linux/arch/arm/plat-s5p/include/plat/s5pv310.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Header file for s5pv310 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* Common init code for S5PV310 related SoCs */
-
-extern void s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-extern void s5pv310_register_clocks(void);
-extern void s5pv310_setup_clocks(void);
-
-#ifdef CONFIG_CPU_S5PV310
-
-extern  int s5pv310_init(void);
-extern void s5pv310_init_irq(void);
-extern void s5pv310_map_io(void);
-extern void s5pv310_init_clocks(int xtal);
-extern struct sys_timer s5pv310_timer;
-
-#define s5pv310_init_uarts s5pv310_common_init_uarts
-
-#else
-#define s5pv310_init_clocks NULL
-#define s5pv310_init_uarts NULL
-#define s5pv310_map_io NULL
-#define s5pv310_init NULL
-#endif
diff --git a/arch/arm/plat-s5p/include/plat/sysmmu.h b/arch/arm/plat-s5p/include/plat/sysmmu.h
new file mode 100644
index 000000000000..bf5283c2a19d
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/sysmmu.h
@@ -0,0 +1,95 @@
+/* linux/arch/arm/plat-s5p/include/plat/sysmmu.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung System MMU driver for S5P platform
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM__PLAT_SYSMMU_H
+#define __ASM__PLAT_SYSMMU_H __FILE__
+
+enum S5P_SYSMMU_INTERRUPT_TYPE {
+        SYSMMU_PAGEFAULT,
+        SYSMMU_AR_MULTIHIT,
+        SYSMMU_AW_MULTIHIT,
+        SYSMMU_BUSERROR,
+        SYSMMU_AR_SECURITY,
+        SYSMMU_AR_ACCESS,
+        SYSMMU_AW_SECURITY,
+        SYSMMU_AW_PROTECTION, /* 7 */
+        SYSMMU_FAULTS_NUM
+};
+
+#ifdef CONFIG_S5P_SYSTEM_MMU
+
+#include <mach/sysmmu.h>
+
+/**
+ * s5p_sysmmu_enable() - enable system mmu of ip
+ * @ips: The ip connected system mmu.
+ * #pgd: Base physical address of the 1st level page table
+ *
+ * This function enable system mmu to transfer address
+ * from virtual address to physical address
+ */
+void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd);
+
+/**
+ * s5p_sysmmu_disable() - disable sysmmu mmu of ip
+ * @ips: The ip connected system mmu.
+ *
+ * This function disable system mmu to transfer address
+ * from virtual address to physical address
+ */
+void s5p_sysmmu_disable(sysmmu_ips ips);
+
+/**
+ * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
+ * @ips: The ip connected system mmu.
+ * @pgd: The page table base address.
+ *
+ * This function set page table base address
+ * When system mmu transfer address from virtaul address to physical address,
+ * system mmu refer address information from page table
+ */
+void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
+
+/**
+ * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
+ * @ips: The ip connected system mmu.
+ *
+ * This function flush all TLB entry in system mmu
+ */
+void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
+
+/** s5p_sysmmu_set_fault_handler() - Fault handler for System MMUs
+ * @itype: type of fault.
+ * @pgtable_base: the physical address of page table base. This is 0 if @ips is
+ *               SYSMMU_BUSERROR.
+ * @fault_addr: the device (virtual) address that the System MMU tried to
+ *             translated. This is 0 if @ips is SYSMMU_BUSERROR.
+ * Called when interrupt occurred by the System MMUs
+ * The device drivers of peripheral devices that has a System MMU can implement
+ * a fault handler to resolve address translation fault by System MMU.
+ * The meanings of return value and parameters are described below.
+
+ * return value: non-zero if the fault is correctly resolved.
+ *         zero if the fault is not handled.
+ */
+void s5p_sysmmu_set_fault_handler(sysmmu_ips ips,
+                        int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
+                                        unsigned long pgtable_base,
+                                        unsigned long fault_addr));
+#else
+#define s5p_sysmmu_enable(ips, pgd) do { } while (0)
+#define s5p_sysmmu_disable(ips) do { } while (0)
+#define s5p_sysmmu_set_tablebase_pgd(ips, pgd) do { } while (0)
+#define s5p_sysmmu_tlb_invalidate(ips) do { } while (0)
+#define s5p_sysmmu_set_fault_handler(ips, handler) do { } while (0)
+#endif
+#endif /* __ASM_PLAT_SYSMMU_H */
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index 3b6bf89d1739..cd87d3256e03 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -17,82 +17,79 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/slab.h>
 
 #include <mach/map.h>
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 
-#define S5P_GPIOREG(x)                  (S5P_VA_GPIO + (x))
+#define GPIO_BASE(chip)         (((unsigned long)(chip)->base) & 0xFFFFF000u)
 
-#define GPIOINT_CON_OFFSET              0x700
-#define GPIOINT_MASK_OFFSET             0x900
-#define GPIOINT_PEND_OFFSET             0xA00
+#define CON_OFFSET              0x700
+#define MASK_OFFSET             0x900
+#define PEND_OFFSET             0xA00
+#define REG_OFFSET(x)           ((x) << 2)
 
-static struct s3c_gpio_chip *irq_chips[S5P_GPIOINT_GROUP_MAXNR];
-
-static int s5p_gpioint_get_group(struct irq_data *data)
-{
-        struct gpio_chip *chip = irq_data_get_irq_data(data);
-        struct s3c_gpio_chip *s3c_chip = container_of(chip,
-                        struct s3c_gpio_chip, chip);
-        int group;
-
-        for (group = 0; group < S5P_GPIOINT_GROUP_MAXNR; group++)
-                if (s3c_chip == irq_chips[group])
-                        break;
+struct s5p_gpioint_bank {
+        struct list_head        list;
+        int                     start;
+        int                     nr_groups;
+        int                     irq;
+        struct s3c_gpio_chip    **chips;
+        void                    (*handler)(unsigned int, struct irq_desc *);
+};
 
-        return group;
-}
+LIST_HEAD(banks);
 
 static int s5p_gpioint_get_offset(struct irq_data *data)
 {
-        struct gpio_chip *chip = irq_data_get_irq_data(data);
-        struct s3c_gpio_chip *s3c_chip = container_of(chip,
-                        struct s3c_gpio_chip, chip);
-
-        return data->irq - s3c_chip->irq_base;
+        struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
+        return data->irq - chip->irq_base;
 }
 
 static void s5p_gpioint_ack(struct irq_data *data)
 {
+        struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
         int group, offset, pend_offset;
         unsigned int value;
 
-        group = s5p_gpioint_get_group(data);
+        group = chip->group;
         offset = s5p_gpioint_get_offset(data);
-        pend_offset = group << 2;
+        pend_offset = REG_OFFSET(group);
 
-        value = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
-        value |= 1 << offset;
-        __raw_writel(value, S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
+        value = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
+        value |= BIT(offset);
+        __raw_writel(value, GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
 }
 
 static void s5p_gpioint_mask(struct irq_data *data)
 {
+        struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
         int group, offset, mask_offset;
         unsigned int value;
 
-        group = s5p_gpioint_get_group(data);
+        group = chip->group;
         offset = s5p_gpioint_get_offset(data);
-        mask_offset = group << 2;
+        mask_offset = REG_OFFSET(group);
 
-        value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
-        value |= 1 << offset;
-        __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+        value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
+        value |= BIT(offset);
+        __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
 }
 
 static void s5p_gpioint_unmask(struct irq_data *data)
 {
+        struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
         int group, offset, mask_offset;
         unsigned int value;
 
-        group = s5p_gpioint_get_group(data);
+        group = chip->group;
         offset = s5p_gpioint_get_offset(data);
-        mask_offset = group << 2;
+        mask_offset = REG_OFFSET(group);
 
-        value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
-        value &= ~(1 << offset);
-        __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+        value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
+        value &= ~BIT(offset);
+        __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
 }
 
 static void s5p_gpioint_mask_ack(struct irq_data *data)
@@ -103,12 +100,13 @@ static void s5p_gpioint_mask_ack(struct irq_data *data)
 
 static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
 {
+        struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
         int group, offset, con_offset;
         unsigned int value;
 
-        group = s5p_gpioint_get_group(data);
+        group = chip->group;
         offset = s5p_gpioint_get_offset(data);
-        con_offset = group << 2;
+        con_offset = REG_OFFSET(group);
 
         switch (type) {
         case IRQ_TYPE_EDGE_RISING:
@@ -132,15 +130,15 @@ static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
                 return -EINVAL;
         }
 
-        value = __raw_readl(S5P_GPIOREG(GPIOINT_CON_OFFSET) + con_offset);
+        value = __raw_readl(GPIO_BASE(chip) + CON_OFFSET + con_offset);
         value &= ~(0x7 << (offset * 0x4));
         value |= (type << (offset * 0x4));
-        __raw_writel(value, S5P_GPIOREG(GPIOINT_CON_OFFSET) + con_offset);
+        __raw_writel(value, GPIO_BASE(chip) + CON_OFFSET + con_offset);
 
         return 0;
 }
 
-struct irq_chip s5p_gpioint = {
+static struct irq_chip s5p_gpioint = {
         .name           = "s5p_gpioint",
         .irq_ack        = s5p_gpioint_ack,
         .irq_mask       = s5p_gpioint_mask,
@@ -151,30 +149,29 @@ struct irq_chip s5p_gpioint = {
 
 static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
 {
-        int group, offset, pend_offset, mask_offset;
-        int real_irq;
+        struct s5p_gpioint_bank *bank = get_irq_data(irq);
+        int group, pend_offset, mask_offset;
         unsigned int pend, mask;
 
-        for (group = 0; group < S5P_GPIOINT_GROUP_MAXNR; group++) {
-                pend_offset = group << 2;
-                pend = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) +
-                                pend_offset);
+        for (group = 0; group < bank->nr_groups; group++) {
+                struct s3c_gpio_chip *chip = bank->chips[group];
+                if (!chip)
+                        continue;
+
+                pend_offset = REG_OFFSET(group);
+                pend = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
                 if (!pend)
                         continue;
 
-                mask_offset = group << 2;
-                mask = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) +
-                                mask_offset);
+                mask_offset = REG_OFFSET(group);
+                mask = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
                 pend &= ~mask;
 
-                for (offset = 0; offset < 8; offset++) {
-                        if (pend & (1 << offset)) {
-                                struct s3c_gpio_chip *chip = irq_chips[group];
-                                if (chip) {
-                                        real_irq = chip->irq_base + offset;
-                                        generic_handle_irq(real_irq);
-                                }
-                        }
+                while (pend) {
+                        int offset = fls(pend) - 1;
+                        int real_irq = chip->irq_base + offset;
+                        generic_handle_irq(real_irq);
+                        pend &= ~BIT(offset);
                 }
         }
 }
@@ -182,27 +179,48 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
 static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
 {
         static int used_gpioint_groups = 0;
-        static bool handler_registered = 0;
         int irq, group = chip->group;
         int i;
+        struct s5p_gpioint_bank *bank = NULL;
 
         if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
                 return -ENOMEM;
 
+        list_for_each_entry(bank, &banks, list) {
+                if (group >= bank->start &&
+                    group < bank->start + bank->nr_groups)
+                        break;
+        }
+        if (!bank)
+                return -EINVAL;
+
+        if (!bank->handler) {
+                bank->chips = kzalloc(sizeof(struct s3c_gpio_chip *) *
+                                      bank->nr_groups, GFP_KERNEL);
+                if (!bank->chips)
+                        return -ENOMEM;
+
+                set_irq_chained_handler(bank->irq, s5p_gpioint_handler);
+                set_irq_data(bank->irq, bank);
+                bank->handler = s5p_gpioint_handler;
+                printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
+                       bank->irq);
+        }
+
+        /*
+         * chained GPIO irq has been sucessfully registered, allocate new gpio
+         * int group and assign irq nubmers
+         */
+
         chip->irq_base = S5P_GPIOINT_BASE +
                          used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
         used_gpioint_groups++;
 
-        if (!handler_registered) {
-                set_irq_chained_handler(IRQ_GPIOINT, s5p_gpioint_handler);
-                handler_registered = 1;
-        }
-
-        irq_chips[group] = chip;
+        bank->chips[group - bank->start] = chip;
         for (i = 0; i < chip->chip.ngpio; i++) {
                 irq = chip->irq_base + i;
                 set_irq_chip(irq, &s5p_gpioint);
-                set_irq_data(irq, &chip->chip);
+                set_irq_data(irq, chip);
                 set_irq_handler(irq, handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
@@ -235,3 +253,19 @@ int __init s5p_register_gpio_interrupt(int pin)
         }
         return ret;
 }
+
+int __init s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups)
+{
+        struct s5p_gpioint_bank *bank;
+
+        bank = kzalloc(sizeof(*bank), GFP_KERNEL);
+        if (!bank)
+                return -ENOMEM;
+
+        bank->start = start;
+        bank->nr_groups = nr_groups;
+        bank->irq = chain_irq;
+
+        list_add_tail(&bank->list, &banks);
+        return 0;
+}
diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c
new file mode 100644
index 000000000000..8090403eec0f
--- /dev/null
+++ b/arch/arm/plat-s5p/s5p-time.c
@@ -0,0 +1,448 @@
+/* linux/arch/arm/plat-s5p/s5p-time.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5P - Common hr-timer support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/platform_device.h>
+
+#include <asm/smp_twd.h>
+#include <asm/mach/time.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/sched_clock.h>
+
+#include <mach/map.h>
+#include <plat/devs.h>
+#include <plat/regs-timer.h>
+#include <plat/s5p-time.h>
+
+static struct clk *tin_event;
+static struct clk *tin_source;
+static struct clk *tdiv_event;
+static struct clk *tdiv_source;
+static struct clk *timerclk;
+static struct s5p_timer_source timer_source;
+static unsigned long clock_count_per_tick;
+static void s5p_timer_resume(void);
+
+static void s5p_time_stop(enum s5p_timer_mode mode)
+{
+        unsigned long tcon;
+
+        tcon = __raw_readl(S3C2410_TCON);
+
+        switch (mode) {
+        case S5P_PWM0:
+                tcon &= ~S3C2410_TCON_T0START;
+                break;
+
+        case S5P_PWM1:
+                tcon &= ~S3C2410_TCON_T1START;
+                break;
+
+        case S5P_PWM2:
+                tcon &= ~S3C2410_TCON_T2START;
+                break;
+
+        case S5P_PWM3:
+                tcon &= ~S3C2410_TCON_T3START;
+                break;
+
+        case S5P_PWM4:
+                tcon &= ~S3C2410_TCON_T4START;
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Timer %d\n", mode);
+                break;
+        }
+        __raw_writel(tcon, S3C2410_TCON);
+}
+
+static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
+{
+        unsigned long tcon;
+
+        tcon = __raw_readl(S3C2410_TCON);
+
+        tcnt--;
+
+        switch (mode) {
+        case S5P_PWM0:
+                tcon &= ~(0x0f << 0);
+                tcon |= S3C2410_TCON_T0MANUALUPD;
+                break;
+
+        case S5P_PWM1:
+                tcon &= ~(0x0f << 8);
+                tcon |= S3C2410_TCON_T1MANUALUPD;
+                break;
+
+        case S5P_PWM2:
+                tcon &= ~(0x0f << 12);
+                tcon |= S3C2410_TCON_T2MANUALUPD;
+                break;
+
+        case S5P_PWM3:
+                tcon &= ~(0x0f << 16);
+                tcon |= S3C2410_TCON_T3MANUALUPD;
+                break;
+
+        case S5P_PWM4:
+                tcon &= ~(0x07 << 20);
+                tcon |= S3C2410_TCON_T4MANUALUPD;
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Timer %d\n", mode);
+                break;
+        }
+
+        __raw_writel(tcnt, S3C2410_TCNTB(mode));
+        __raw_writel(tcnt, S3C2410_TCMPB(mode));
+        __raw_writel(tcon, S3C2410_TCON);
+}
+
+static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
+{
+        unsigned long tcon;
+
+        tcon  = __raw_readl(S3C2410_TCON);
+
+        switch (mode) {
+        case S5P_PWM0:
+                tcon |= S3C2410_TCON_T0START;
+                tcon &= ~S3C2410_TCON_T0MANUALUPD;
+
+                if (periodic)
+                        tcon |= S3C2410_TCON_T0RELOAD;
+                else
+                        tcon &= ~S3C2410_TCON_T0RELOAD;
+                break;
+
+        case S5P_PWM1:
+                tcon |= S3C2410_TCON_T1START;
+                tcon &= ~S3C2410_TCON_T1MANUALUPD;
+
+                if (periodic)
+                        tcon |= S3C2410_TCON_T1RELOAD;
+                else
+                        tcon &= ~S3C2410_TCON_T1RELOAD;
+                break;
+
+        case S5P_PWM2:
+                tcon |= S3C2410_TCON_T2START;
+                tcon &= ~S3C2410_TCON_T2MANUALUPD;
+
+                if (periodic)
+                        tcon |= S3C2410_TCON_T2RELOAD;
+                else
+                        tcon &= ~S3C2410_TCON_T2RELOAD;
+                break;
+
+        case S5P_PWM3:
+                tcon |= S3C2410_TCON_T3START;
+                tcon &= ~S3C2410_TCON_T3MANUALUPD;
+
+                if (periodic)
+                        tcon |= S3C2410_TCON_T3RELOAD;
+                else
+                        tcon &= ~S3C2410_TCON_T3RELOAD;
+                break;
+
+        case S5P_PWM4:
+                tcon |= S3C2410_TCON_T4START;
+                tcon &= ~S3C2410_TCON_T4MANUALUPD;
+
+                if (periodic)
+                        tcon |= S3C2410_TCON_T4RELOAD;
+                else
+                        tcon &= ~S3C2410_TCON_T4RELOAD;
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Timer %d\n", mode);
+                break;
+        }
+        __raw_writel(tcon, S3C2410_TCON);
+}
+
+static int s5p_set_next_event(unsigned long cycles,
+                                struct clock_event_device *evt)
+{
+        s5p_time_setup(timer_source.event_id, cycles);
+        s5p_time_start(timer_source.event_id, NON_PERIODIC);
+
+        return 0;
+}
+
+static void s5p_set_mode(enum clock_event_mode mode,
+                                struct clock_event_device *evt)
+{
+        s5p_time_stop(timer_source.event_id);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                s5p_time_setup(timer_source.event_id, clock_count_per_tick);
+                s5p_time_start(timer_source.event_id, PERIODIC);
+                break;
+
+        case CLOCK_EVT_MODE_ONESHOT:
+                break;
+
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                break;
+
+        case CLOCK_EVT_MODE_RESUME:
+                s5p_timer_resume();
+                break;
+        }
+}
+
+static void s5p_timer_resume(void)
+{
+        /* event timer restart */
+        s5p_time_setup(timer_source.event_id, clock_count_per_tick);
+        s5p_time_start(timer_source.event_id, PERIODIC);
+
+        /* source timer restart */
+        s5p_time_setup(timer_source.source_id, TCNT_MAX);
+        s5p_time_start(timer_source.source_id, PERIODIC);
+}
+
+void __init s5p_set_timer_source(enum s5p_timer_mode event,
+                                 enum s5p_timer_mode source)
+{
+        s3c_device_timer[event].dev.bus = &platform_bus_type;
+        s3c_device_timer[source].dev.bus = &platform_bus_type;
+
+        timer_source.event_id = event;
+        timer_source.source_id = source;
+}
+
+static struct clock_event_device time_event_device = {
+        .name           = "s5p_event_timer",
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .rating         = 200,
+        .set_next_event = s5p_set_next_event,
+        .set_mode       = s5p_set_mode,
+};
+
+static irqreturn_t s5p_clock_event_isr(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = dev_id;
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction s5p_clock_event_irq = {
+        .name           = "s5p_time_irq",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = s5p_clock_event_isr,
+        .dev_id         = &time_event_device,
+};
+
+static void __init s5p_clockevent_init(void)
+{
+        unsigned long pclk;
+        unsigned long clock_rate;
+        unsigned int irq_number;
+        struct clk *tscaler;
+
+        pclk = clk_get_rate(timerclk);
+
+        tscaler = clk_get_parent(tdiv_event);
+
+        clk_set_rate(tscaler, pclk / 2);
+        clk_set_rate(tdiv_event, pclk / 2);
+        clk_set_parent(tin_event, tdiv_event);
+
+        clock_rate = clk_get_rate(tin_event);
+        clock_count_per_tick = clock_rate / HZ;
+
+        clockevents_calc_mult_shift(&time_event_device,
+                                    clock_rate, S5PTIMER_MIN_RANGE);
+        time_event_device.max_delta_ns =
+                clockevent_delta2ns(-1, &time_event_device);
+        time_event_device.min_delta_ns =
+                clockevent_delta2ns(1, &time_event_device);
+
+        time_event_device.cpumask = cpumask_of(0);
+        clockevents_register_device(&time_event_device);
+
+        irq_number = timer_source.event_id + IRQ_TIMER0;
+        setup_irq(irq_number, &s5p_clock_event_irq);
+}
+
+static cycle_t s5p_timer_read(struct clocksource *cs)
+{
+        unsigned long offset = 0;
+
+        switch (timer_source.source_id) {
+        case S5P_PWM0:
+        case S5P_PWM1:
+        case S5P_PWM2:
+        case S5P_PWM3:
+                offset = (timer_source.source_id * 0x0c) + 0x14;
+                break;
+
+        case S5P_PWM4:
+                offset = 0x40;
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
+                return 0;
+        }
+
+        return (cycle_t) ~__raw_readl(S3C_TIMERREG(offset));
+}
+
+/*
+ * Override the global weak sched_clock symbol with this
+ * local implementation which uses the clocksource to get some
+ * better resolution when scheduling the kernel. We accept that
+ * this wraps around for now, since it is just a relative time
+ * stamp. (Inspired by U300 implementation.)
+ */
+static DEFINE_CLOCK_DATA(cd);
+
+unsigned long long notrace sched_clock(void)
+{
+        u32 cyc;
+        unsigned long offset = 0;
+
+        switch (timer_source.source_id) {
+        case S5P_PWM0:
+        case S5P_PWM1:
+        case S5P_PWM2:
+        case S5P_PWM3:
+                offset = (timer_source.source_id * 0x0c) + 0x14;
+                break;
+
+        case S5P_PWM4:
+                offset = 0x40;
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
+                return 0;
+        }
+
+        cyc = ~__raw_readl(S3C_TIMERREG(offset));
+        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+}
+
+static void notrace s5p_update_sched_clock(void)
+{
+        u32 cyc;
+        unsigned long offset = 0;
+
+        switch (timer_source.source_id) {
+        case S5P_PWM0:
+        case S5P_PWM1:
+        case S5P_PWM2:
+        case S5P_PWM3:
+                offset = (timer_source.source_id * 0x0c) + 0x14;
+                break;
+
+        case S5P_PWM4:
+                offset = 0x40;
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
+        }
+
+        cyc = ~__raw_readl(S3C_TIMERREG(offset));
+        update_sched_clock(&cd, cyc, (u32)~0);
+}
+
+struct clocksource time_clocksource = {
+        .name           = "s5p_clocksource_timer",
+        .rating         = 250,
+        .read           = s5p_timer_read,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __init s5p_clocksource_init(void)
+{
+        unsigned long pclk;
+        unsigned long clock_rate;
+
+        pclk = clk_get_rate(timerclk);
+
+        clk_set_rate(tdiv_source, pclk / 2);
+        clk_set_parent(tin_source, tdiv_source);
+
+        clock_rate = clk_get_rate(tin_source);
+
+        init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate);
+
+        s5p_time_setup(timer_source.source_id, TCNT_MAX);
+        s5p_time_start(timer_source.source_id, PERIODIC);
+
+        if (clocksource_register_hz(&time_clocksource, clock_rate))
+                panic("%s: can't register clocksource\n", time_clocksource.name);
+}
+
+static void __init s5p_timer_resources(void)
+{
+
+        unsigned long event_id = timer_source.event_id;
+        unsigned long source_id = timer_source.source_id;
+
+        timerclk = clk_get(NULL, "timers");
+        if (IS_ERR(timerclk))
+                panic("failed to get timers clock for timer");
+
+        clk_enable(timerclk);
+
+        tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin");
+        if (IS_ERR(tin_event))
+                panic("failed to get pwm-tin clock for event timer");
+
+        tdiv_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tdiv");
+        if (IS_ERR(tdiv_event))
+                panic("failed to get pwm-tdiv clock for event timer");
+
+        clk_enable(tin_event);
+
+        tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin");
+        if (IS_ERR(tin_source))
+                panic("failed to get pwm-tin clock for source timer");
+
+        tdiv_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tdiv");
+        if (IS_ERR(tdiv_source))
+                panic("failed to get pwm-tdiv clock for source timer");
+
+        clk_enable(tin_source);
+}
+
+static void __init s5p_timer_init(void)
+{
+        s5p_timer_resources();
+        s5p_clockevent_init();
+        s5p_clocksource_init();
+}
+
+struct sys_timer s5p_timer = {
+        .init           = s5p_timer_init,
+};
diff --git a/arch/arm/plat-s5p/setup-mipiphy.c b/arch/arm/plat-s5p/setup-mipiphy.c
new file mode 100644
index 000000000000..683c466c0e6a
--- /dev/null
+++ b/arch/arm/plat-s5p/setup-mipiphy.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *
+ * S5P - Helper functions for MIPI-CSIS and MIPI-DSIM D-PHY control
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <mach/regs-clock.h>
+
+static int __s5p_mipi_phy_control(struct platform_device *pdev,
+                                  bool on, u32 reset)
+{
+        static DEFINE_SPINLOCK(lock);
+        void __iomem *addr;
+        unsigned long flags;
+        int pid;
+        u32 cfg;
+
+        if (!pdev)
+                return -EINVAL;
+
+        pid = (pdev->id == -1) ? 0 : pdev->id;
+
+        if (pid != 0 && pid != 1)
+                return -EINVAL;
+
+        addr = S5P_MIPI_DPHY_CONTROL(pid);
+
+        spin_lock_irqsave(&lock, flags);
+
+        cfg = __raw_readl(addr);
+        cfg = on ? (cfg | reset) : (cfg & ~reset);
+        __raw_writel(cfg, addr);
+
+        if (on) {
+                cfg |= S5P_MIPI_DPHY_ENABLE;
+        } else if (!(cfg & (S5P_MIPI_DPHY_SRESETN |
+                            S5P_MIPI_DPHY_MRESETN) & ~reset)) {
+                cfg &= ~S5P_MIPI_DPHY_ENABLE;
+        }
+
+        __raw_writel(cfg, addr);
+        spin_unlock_irqrestore(&lock, flags);
+
+        return 0;
+}
+
+int s5p_csis_phy_enable(struct platform_device *pdev, bool on)
+{
+        return __s5p_mipi_phy_control(pdev, on, S5P_MIPI_DPHY_SRESETN);
+}
+
+int s5p_dsim_phy_enable(struct platform_device *pdev, bool on)
+{
+        return __s5p_mipi_phy_control(pdev, on, S5P_MIPI_DPHY_MRESETN);
+}
diff --git a/arch/arm/plat-s5p/sysmmu.c b/arch/arm/plat-s5p/sysmmu.c
index ffe8a48bc3c1..54f5eddc921d 100644
--- a/arch/arm/plat-s5p/sysmmu.c
+++ b/arch/arm/plat-s5p/sysmmu.c
@@ -12,280 +12,266 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 
+#include <asm/pgtable.h>
+
 #include <mach/map.h>
 #include <mach/regs-sysmmu.h>
-#include <mach/sysmmu.h>
+#include <plat/sysmmu.h>
+
+#define CTRL_ENABLE     0x5
+#define CTRL_BLOCK      0x7
+#define CTRL_DISABLE    0x0
+
+static struct device *dev;
+
+static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
+        S5P_PAGE_FAULT_ADDR,
+        S5P_AR_FAULT_ADDR,
+        S5P_AW_FAULT_ADDR,
+        S5P_DEFAULT_SLAVE_ADDR,
+        S5P_AR_FAULT_ADDR,
+        S5P_AR_FAULT_ADDR,
+        S5P_AW_FAULT_ADDR,
+        S5P_AW_FAULT_ADDR
+};
+
+static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
+        "PAGE FAULT",
+        "AR MULTI-HIT FAULT",
+        "AW MULTI-HIT FAULT",
+        "BUS ERROR",
+        "AR SECURITY PROTECTION FAULT",
+        "AR ACCESS PROTECTION FAULT",
+        "AW SECURITY PROTECTION FAULT",
+        "AW ACCESS PROTECTION FAULT"
+};
 
-struct sysmmu_controller s5p_sysmmu_cntlrs[S5P_SYSMMU_TOTAL_IPNUM];
+static int (*fault_handlers[S5P_SYSMMU_TOTAL_IPNUM])(
+                enum S5P_SYSMMU_INTERRUPT_TYPE itype,
+                unsigned long pgtable_base,
+                unsigned long fault_addr);
 
-void s5p_sysmmu_register(struct sysmmu_controller *sysmmuconp)
+/*
+ * If adjacent 2 bits are true, the system MMU is enabled.
+ * The system MMU is disabled, otherwise.
+ */
+static unsigned long sysmmu_states;
+
+static inline void set_sysmmu_active(sysmmu_ips ips)
 {
-        unsigned int reg_mmu_ctrl;
-        unsigned int reg_mmu_status;
-        unsigned int reg_pt_base_addr;
-        unsigned int reg_int_status;
-        unsigned int reg_page_ft_addr;
-
-        reg_int_status = __raw_readl(sysmmuconp->regs + S5P_INT_STATUS);
-        reg_mmu_ctrl = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL);
-        reg_mmu_status = __raw_readl(sysmmuconp->regs + S5P_MMU_STATUS);
-        reg_pt_base_addr = __raw_readl(sysmmuconp->regs + S5P_PT_BASE_ADDR);
-        reg_page_ft_addr = __raw_readl(sysmmuconp->regs + S5P_PAGE_FAULT_ADDR);
-
-        printk(KERN_INFO "%s: ips:%s\n", __func__, sysmmuconp->name);
-        printk(KERN_INFO "%s: MMU_CTRL:0x%X, ", __func__, reg_mmu_ctrl);
-        printk(KERN_INFO "MMU_STATUS:0x%X, PT_BASE_ADDR:0x%X\n", reg_mmu_status, reg_pt_base_addr);
-        printk(KERN_INFO "%s: INT_STATUS:0x%X, PAGE_FAULT_ADDR:0x%X\n", __func__, reg_int_status, reg_page_ft_addr);
-
-        switch (reg_int_status & 0xFF) {
-        case 0x1:
-                printk(KERN_INFO "%s: Page fault\n", __func__);
-                printk(KERN_INFO "%s: Virtual address causing last page fault or bus error : 0x%x\n", __func__ , reg_page_ft_addr);
-                break;
-        case 0x2:
-                printk(KERN_INFO "%s: AR multi-hit fault\n", __func__);
-                break;
-        case 0x4:
-                printk(KERN_INFO "%s: AW multi-hit fault\n", __func__);
-                break;
-        case 0x8:
-                printk(KERN_INFO "%s: Bus error\n", __func__);
-                break;
-        case 0x10:
-                printk(KERN_INFO "%s: AR Security protection fault\n", __func__);
-                break;
-        case 0x20:
-                printk(KERN_INFO "%s: AR Access protection fault\n", __func__);
-                break;
-        case 0x40:
-                printk(KERN_INFO "%s: AW Security protection fault\n", __func__);
-                break;
-        case 0x80:
-                printk(KERN_INFO "%s: AW Access protection fault\n", __func__);
-                break;
-        }
+        sysmmu_states |= 3 << (ips * 2);
 }
 
-static irqreturn_t s5p_sysmmu_irq(int irq, void *dev_id)
+static inline void set_sysmmu_inactive(sysmmu_ips ips)
 {
-        unsigned int i;
-        unsigned int reg_int_status;
-        struct sysmmu_controller *sysmmuconp;
-
-        for (i = 0; i < S5P_SYSMMU_TOTAL_IPNUM; i++) {
-                sysmmuconp = &s5p_sysmmu_cntlrs[i];
-
-                if (sysmmuconp->enable == true) {
-                        reg_int_status = __raw_readl(sysmmuconp->regs + S5P_INT_STATUS);
-
-                        if (reg_int_status & 0xFF)
-                                s5p_sysmmu_register(sysmmuconp);
-                }
-        }
-        return IRQ_HANDLED;
+        sysmmu_states &= ~(3 << (ips * 2));
 }
 
-int s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd)
+static inline int is_sysmmu_active(sysmmu_ips ips)
 {
-        struct sysmmu_controller *sysmmuconp = NULL;
-
-        sysmmuconp = &s5p_sysmmu_cntlrs[ips];
-
-        if (sysmmuconp == NULL) {
-                printk(KERN_ERR "failed to get ip's sysmmu info\n");
-                return 1;
-        }
-
-        /* Set sysmmu page table base address */
-        __raw_writel(pgd, sysmmuconp->regs + S5P_PT_BASE_ADDR);
+        return sysmmu_states & (3 << (ips * 2));
+}
 
-        if (s5p_sysmmu_tlb_invalidate(ips) != 0)
-                printk(KERN_ERR "failed s5p_sysmmu_tlb_invalidate\n");
+static void __iomem *sysmmusfrs[S5P_SYSMMU_TOTAL_IPNUM];
 
-        return 0;
+static inline void sysmmu_block(sysmmu_ips ips)
+{
+        __raw_writel(CTRL_BLOCK, sysmmusfrs[ips] + S5P_MMU_CTRL);
+        dev_dbg(dev, "%s is blocked.\n", sysmmu_ips_name[ips]);
 }
 
-static int s5p_sysmmu_set_tablebase(sysmmu_ips ips)
+static inline void sysmmu_unblock(sysmmu_ips ips)
 {
-        unsigned int pg;
-        struct sysmmu_controller *sysmmuconp;
+        __raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
+        dev_dbg(dev, "%s is unblocked.\n", sysmmu_ips_name[ips]);
+}
 
-        sysmmuconp = &s5p_sysmmu_cntlrs[ips];
+static inline void __sysmmu_tlb_invalidate(sysmmu_ips ips)
+{
+        __raw_writel(0x1, sysmmusfrs[ips] + S5P_MMU_FLUSH);
+        dev_dbg(dev, "TLB of %s is invalidated.\n", sysmmu_ips_name[ips]);
+}
 
-        if (sysmmuconp == NULL) {
-                printk(KERN_ERR "failed to get ip's sysmmu info\n");
-                return 1;
+static inline void __sysmmu_set_ptbase(sysmmu_ips ips, unsigned long pgd)
+{
+        if (unlikely(pgd == 0)) {
+                pgd = (unsigned long)ZERO_PAGE(0);
+                __raw_writel(0x20, sysmmusfrs[ips] + S5P_MMU_CFG); /* 4KB LV1 */
+        } else {
+                __raw_writel(0x0, sysmmusfrs[ips] + S5P_MMU_CFG); /* 16KB LV1 */
         }
 
-        __asm__("mrc    p15, 0, %0, c2, c0, 0"  \
-                : "=r" (pg) : : "cc");          \
-                pg &= ~0x3fff;
+        __raw_writel(pgd, sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
 
-        printk(KERN_INFO "%s: CP15 TTBR0 : 0x%x\n", __func__, pg);
-
-        /* Set sysmmu page table base address */
-        __raw_writel(pg, sysmmuconp->regs + S5P_PT_BASE_ADDR);
+        dev_dbg(dev, "Page table base of %s is initialized with 0x%08lX.\n",
+                                                sysmmu_ips_name[ips], pgd);
+        __sysmmu_tlb_invalidate(ips);
+}
 
-        return 0;
+void sysmmu_set_fault_handler(sysmmu_ips ips,
+                        int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
+                                        unsigned long pgtable_base,
+                                        unsigned long fault_addr))
+{
+        BUG_ON(!((ips >= SYSMMU_MDMA) && (ips < S5P_SYSMMU_TOTAL_IPNUM)));
+        fault_handlers[ips] = handler;
 }
 
-int s5p_sysmmu_enable(sysmmu_ips ips)
+static irqreturn_t s5p_sysmmu_irq(int irq, void *dev_id)
 {
-        unsigned int reg;
+        /* SYSMMU is in blocked when interrupt occurred. */
+        unsigned long base = 0;
+        sysmmu_ips ips = (sysmmu_ips)dev_id;
+        enum S5P_SYSMMU_INTERRUPT_TYPE itype;
 
-        struct sysmmu_controller *sysmmuconp;
+        itype = (enum S5P_SYSMMU_INTERRUPT_TYPE)
+                __ffs(__raw_readl(sysmmusfrs[ips] + S5P_INT_STATUS));
 
-        sysmmuconp = &s5p_sysmmu_cntlrs[ips];
+        BUG_ON(!((itype >= 0) && (itype < 8)));
 
-        if (sysmmuconp == NULL) {
-                printk(KERN_ERR "failed to get ip's sysmmu info\n");
-                return 1;
-        }
+        dev_alert(dev, "%s occurred by %s.\n", sysmmu_fault_name[itype],
+                                                        sysmmu_ips_name[ips]);
 
-        s5p_sysmmu_set_tablebase(ips);
+        if (fault_handlers[ips]) {
+                unsigned long addr;
 
-        /* replacement policy : LRU */
-        reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CFG);
-        reg |= 0x1;
-        __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CFG);
+                base = __raw_readl(sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
+                addr = __raw_readl(sysmmusfrs[ips] + fault_reg_offset[itype]);
 
-        /* Enable interrupt, Enable MMU */
-        reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL);
-        reg |= (0x1 << 2) | (0x1 << 0);
+                if (fault_handlers[ips](itype, base, addr)) {
+                        __raw_writel(1 << itype,
+                                        sysmmusfrs[ips] + S5P_INT_CLEAR);
+                        dev_notice(dev, "%s from %s is resolved."
+                                        " Retrying translation.\n",
+                                sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
+                } else {
+                        base = 0;
+                }
+        }
 
-        __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CTRL);
+        sysmmu_unblock(ips);
 
-        sysmmuconp->enable = true;
+        if (!base)
+                dev_notice(dev, "%s from %s is not handled.\n",
+                        sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
 
-        return 0;
+        return IRQ_HANDLED;
 }
 
-int s5p_sysmmu_disable(sysmmu_ips ips)
+void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd)
 {
-        unsigned int reg;
-
-        struct sysmmu_controller *sysmmuconp = NULL;
-
-        if (ips > S5P_SYSMMU_TOTAL_IPNUM)
-                printk(KERN_ERR "failed to get ips parameter\n");
-
-        sysmmuconp = &s5p_sysmmu_cntlrs[ips];
-
-        if (sysmmuconp == NULL) {
-                printk(KERN_ERR "failed to get ip's sysmmu info\n");
-                return 1;
+        if (is_sysmmu_active(ips)) {
+                sysmmu_block(ips);
+                __sysmmu_set_ptbase(ips, pgd);
+                sysmmu_unblock(ips);
+        } else {
+                dev_dbg(dev, "%s is disabled. "
+                        "Skipping initializing page table base.\n",
+                                                sysmmu_ips_name[ips]);
         }
+}
 
-        reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CFG);
-
-        /* replacement policy : LRU */
-        reg |= 0x1;
-        __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CFG);
-
-        reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL);
+void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd)
+{
+        if (!is_sysmmu_active(ips)) {
+                sysmmu_clk_enable(ips);
 
-        /* Disable MMU */
-        reg &= ~0x1;
-        __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CTRL);
+                __sysmmu_set_ptbase(ips, pgd);
 
-        sysmmuconp->enable = false;
+                __raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
 
-        return 0;
+                set_sysmmu_active(ips);
+                dev_dbg(dev, "%s is enabled.\n", sysmmu_ips_name[ips]);
+        } else {
+                dev_dbg(dev, "%s is already enabled.\n", sysmmu_ips_name[ips]);
+        }
 }
 
-int s5p_sysmmu_tlb_invalidate(sysmmu_ips ips)
+void s5p_sysmmu_disable(sysmmu_ips ips)
 {
-        unsigned int reg;
-        struct sysmmu_controller *sysmmuconp = NULL;
-
-        sysmmuconp = &s5p_sysmmu_cntlrs[ips];
-
-        if (sysmmuconp == NULL) {
-                printk(KERN_ERR "failed to get ip's sysmmu info\n");
-                return 1;
+        if (is_sysmmu_active(ips)) {
+                __raw_writel(CTRL_DISABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
+                set_sysmmu_inactive(ips);
+                sysmmu_clk_disable(ips);
+                dev_dbg(dev, "%s is disabled.\n", sysmmu_ips_name[ips]);
+        } else {
+                dev_dbg(dev, "%s is already disabled.\n", sysmmu_ips_name[ips]);
         }
+}
 
-        /* set Block MMU for flush TLB */
-        reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL);
-        reg |= 0x1 << 1;
-        __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CTRL);
-
-        /* flush all TLB entry */
-        __raw_writel(0x1, sysmmuconp->regs + S5P_MMU_FLUSH);
-
-        /* set Un-block MMU after flush TLB */
-        reg = __raw_readl(sysmmuconp->regs + S5P_MMU_CTRL);
-        reg &= ~(0x1 << 1);
-        __raw_writel(reg, sysmmuconp->regs + S5P_MMU_CTRL);
-
-        return 0;
+void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips)
+{
+        if (is_sysmmu_active(ips)) {
+                sysmmu_block(ips);
+                __sysmmu_tlb_invalidate(ips);
+                sysmmu_unblock(ips);
+        } else {
+                dev_dbg(dev, "%s is disabled. "
+                        "Skipping invalidating TLB.\n", sysmmu_ips_name[ips]);
+        }
 }
 
 static int s5p_sysmmu_probe(struct platform_device *pdev)
 {
-        int i;
-        int ret;
-        struct resource *res;
-        struct sysmmu_controller *sysmmuconp;
-        sysmmu_ips ips;
+        int i, ret;
+        struct resource *res, *mem;
+
+        dev = &pdev->dev;
 
         for (i = 0; i < S5P_SYSMMU_TOTAL_IPNUM; i++) {
-                sysmmuconp = &s5p_sysmmu_cntlrs[i];
-                if (sysmmuconp == NULL) {
-                        printk(KERN_ERR "failed to get ip's sysmmu info\n");
-                        ret = -ENOENT;
-                        goto err_res;
-                }
+                int irq;
 
-                sysmmuconp->name = sysmmu_ips_name[i];
+                sysmmu_clk_init(dev, i);
+                sysmmu_clk_disable(i);
 
                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
                 if (!res) {
-                        printk(KERN_ERR "failed to get sysmmu resource\n");
+                        dev_err(dev, "Failed to get the resource of %s.\n",
+                                                        sysmmu_ips_name[i]);
                         ret = -ENODEV;
                         goto err_res;
                 }
 
-                sysmmuconp->mem = request_mem_region(res->start,
+                mem = request_mem_region(res->start,
                                 ((res->end) - (res->start)) + 1, pdev->name);
-                if (!sysmmuconp->mem) {
-                        pr_err("failed to request sysmmu memory region\n");
+                if (!mem) {
+                        dev_err(dev, "Failed to request the memory region of %s.\n",
+                                                        sysmmu_ips_name[i]);
                         ret = -EBUSY;
                         goto err_res;
                 }
 
-                sysmmuconp->regs = ioremap(res->start, res->end - res->start + 1);
-                if (!sysmmuconp->regs) {
-                        pr_err("failed to sysmmu ioremap\n");
+                sysmmusfrs[i] = ioremap(res->start, res->end - res->start + 1);
+                if (!sysmmusfrs[i]) {
+                        dev_err(dev, "Failed to ioremap() for %s.\n",
+                                                        sysmmu_ips_name[i]);
                         ret = -ENXIO;
                         goto err_reg;
                 }
 
-                sysmmuconp->irq = platform_get_irq(pdev, i);
-                if (sysmmuconp->irq <= 0) {
-                        pr_err("failed to get sysmmu irq resource\n");
+                irq = platform_get_irq(pdev, i);
+                if (irq <= 0) {
+                        dev_err(dev, "Failed to get the IRQ resource of %s.\n",
+                                                        sysmmu_ips_name[i]);
                         ret = -ENOENT;
                         goto err_map;
                 }
 
-                ret = request_irq(sysmmuconp->irq, s5p_sysmmu_irq, IRQF_DISABLED, pdev->name, sysmmuconp);
-                if (ret) {
-                        pr_err("failed to request irq\n");
+                if (request_irq(irq, s5p_sysmmu_irq, IRQF_DISABLED,
+                                                pdev->name, (void *)i)) {
+                        dev_err(dev, "Failed to request IRQ for %s.\n",
+                                                        sysmmu_ips_name[i]);
                         ret = -ENOENT;
                         goto err_map;
                 }
-
-                ips = (sysmmu_ips)i;
-
-                sysmmuconp->ips = ips;
         }
 
         return 0;
 
-err_reg:
-        release_mem_region((resource_size_t)sysmmuconp->mem, (resource_size_t)((res->end) - (res->start) + 1));
 err_map:
-        iounmap(sysmmuconp->regs);
+        iounmap(sysmmusfrs[i]);
+err_reg:
+        release_mem_region(mem->start, resource_size(mem));
 err_res:
         return ret;
 }
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 32be05cf82a3..be72100b81b4 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -273,6 +273,19 @@ config SAMSUNG_DEV_KEYPAD
         help
           Compile in platform device definitions for keypad
 
+config SAMSUNG_DEV_PWM
+        bool
+        default y if ARCH_S3C2410
+        help
+          Compile in platform device definition for PWM Timer
+
+config S3C24XX_PWM
+        bool "PWM device support"
+        select HAVE_PWM
+        help
+          Support for exporting the PWM timer blocks via the pwm device
+          system
+
 # DMA
 
 config S3C_DMA
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 29932f88a8d6..e9de58a2e294 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_SAMSUNG_DEV_ADC)	+= dev-adc.o
 obj-$(CONFIG_SAMSUNG_DEV_IDE)   += dev-ide.o
 obj-$(CONFIG_SAMSUNG_DEV_TS)    += dev-ts.o
 obj-$(CONFIG_SAMSUNG_DEV_KEYPAD)        += dev-keypad.o
+obj-$(CONFIG_SAMSUNG_DEV_PWM)   += dev-pwm.o
 
 # DMA support
 
diff --git a/arch/arm/plat-samsung/dev-pwm.c b/arch/arm/plat-samsung/dev-pwm.c
new file mode 100644
index 000000000000..dab47b0e1900
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-pwm.c
@@ -0,0 +1,53 @@
+/* linux/arch/arm/plat-samsung/dev-pwm.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright (c) 2007 Ben Dooks
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
+ *
+ * S3C series device definition for the PWM timer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+
+#include <plat/devs.h>
+
+#define TIMER_RESOURCE_SIZE (1)
+
+#define TIMER_RESOURCE(_tmr, _irq)                      \
+        (struct resource [TIMER_RESOURCE_SIZE]) {       \
+                [0] = {                                 \
+                        .start  = _irq,                 \
+                        .end    = _irq,                 \
+                        .flags  = IORESOURCE_IRQ        \
+                }                                       \
+        }
+
+#define DEFINE_S3C_TIMER(_tmr_no, _irq)                 \
+        .name           = "s3c24xx-pwm",                \
+        .id             = _tmr_no,                      \
+        .num_resources  = TIMER_RESOURCE_SIZE,          \
+        .resource       = TIMER_RESOURCE(_tmr_no, _irq),        \
+
+/*
+ * since we already have an static mapping for the timer,
+ * we do not bother setting any IO resource for the base.
+ */
+
+struct platform_device s3c_device_timer[] = {
+        [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
+        [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
+        [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
+        [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
+        [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
+};
+EXPORT_SYMBOL(s3c_device_timer);
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 9addb3dfb4bc..cedfff51c82b 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -82,6 +82,7 @@ extern struct sysdev_class s3c64xx_sysclass;
 extern struct sysdev_class s5p64x0_sysclass;
 extern struct sysdev_class s5p6442_sysclass;
 extern struct sysdev_class s5pv210_sysclass;
+extern struct sysdev_class exynos4_sysclass;
 
 extern void (*s5pc1xx_idle)(void);
 
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index b4d208b42957..f0da6b70fba4 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -1,5 +1,8 @@
 /* arch/arm/plat-samsung/include/plat/devs.h
  *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
  * Copyright (c) 2004 Simtec Electronics
  * Ben Dooks <ben@simtec.co.uk>
  *
@@ -96,15 +99,16 @@ extern struct platform_device s5pv210_device_iis1;
 extern struct platform_device s5pv210_device_iis2;
 extern struct platform_device s5pv210_device_spdif;
 
-extern struct platform_device s5pv310_device_ac97;
-extern struct platform_device s5pv310_device_pcm0;
-extern struct platform_device s5pv310_device_pcm1;
-extern struct platform_device s5pv310_device_pcm2;
-extern struct platform_device s5pv310_device_i2s0;
-extern struct platform_device s5pv310_device_i2s1;
-extern struct platform_device s5pv310_device_i2s2;
-extern struct platform_device s5pv310_device_spdif;
-extern struct platform_device s5pv310_device_pd[];
+extern struct platform_device exynos4_device_ac97;
+extern struct platform_device exynos4_device_pcm0;
+extern struct platform_device exynos4_device_pcm1;
+extern struct platform_device exynos4_device_pcm2;
+extern struct platform_device exynos4_device_i2s0;
+extern struct platform_device exynos4_device_i2s1;
+extern struct platform_device exynos4_device_i2s2;
+extern struct platform_device exynos4_device_spdif;
+extern struct platform_device exynos4_device_pd[];
+extern struct platform_device exynos4_device_ahci;
 
 extern struct platform_device s5p6442_device_pcm0;
 extern struct platform_device s5p6442_device_pcm1;
@@ -133,11 +137,12 @@ extern struct platform_device samsung_device_keypad;
 extern struct platform_device s5p_device_fimc0;
 extern struct platform_device s5p_device_fimc1;
 extern struct platform_device s5p_device_fimc2;
+extern struct platform_device s5p_device_fimc3;
 
 extern struct platform_device s5p_device_mipi_csis0;
 extern struct platform_device s5p_device_mipi_csis1;
 
-extern struct platform_device s5pv310_device_sysmmu;
+extern struct platform_device exynos4_device_sysmmu;
 
 /* s3c2440 specific devices */
 
diff --git a/arch/arm/plat-samsung/include/plat/fimc-core.h b/arch/arm/plat-samsung/include/plat/fimc-core.h
index 81a3bfeeccad..945a99d59563 100644
--- a/arch/arm/plat-samsung/include/plat/fimc-core.h
+++ b/arch/arm/plat-samsung/include/plat/fimc-core.h
@@ -38,6 +38,11 @@ static inline void s3c_fimc_setname(int id, char *name)
                 s5p_device_fimc2.name = name;
                 break;
 #endif
+#ifdef CONFIG_S5P_DEV_FIMC3
+        case 3:
+                s5p_device_fimc3.name = name;
+                break;
+#endif
         }
 }
 
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index e4b5cf126fa9..5e04fa6eda74 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -225,4 +225,20 @@ extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr);
  */
 extern int s5p_register_gpio_interrupt(int pin);
 
+/** s5p_register_gpioint_bank() - add gpio bank for further gpio interrupt
+ * registration (see s5p_register_gpio_interrupt function)
+ * @chain_irq: chained irq number for the gpio int handler for this bank
+ * @start: start gpio group number of this bank
+ * @nr_groups: number of gpio groups handled by this bank
+ *
+ * This functions registers initial information about gpio banks that
+ * can be later used by the s5p_register_gpio_interrupt() function to
+ * enable support for gpio interrupt for particular gpio group.
+ */
+#ifdef CONFIG_S5P_GPIO_INT
+extern int s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups);
+#else
+#define s5p_register_gpioint_bank(chain_irq, start, nr_groups) do { } while (0)
+#endif
+
 #endif /* __PLAT_GPIO_CFG_H */
diff --git a/arch/arm/plat-samsung/include/plat/pd.h b/arch/arm/plat-samsung/include/plat/pd.h
index 5f0ad85783db..abb4bc32716a 100644
--- a/arch/arm/plat-samsung/include/plat/pd.h
+++ b/arch/arm/plat-samsung/include/plat/pd.h
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-samsung/include/plat/pd.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
  * This program is free software; you can redistribute it and/or modify
@@ -17,7 +17,7 @@ struct samsung_pd_info {
         void __iomem *base;
 };
 
-enum s5pv310_pd_block {
+enum exynos4_pd_block {
         PD_MFC,
         PD_G3D,
         PD_LCD0,
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 5a41a0b69eec..b0bdf16549d5 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -1,4 +1,7 @@
-/* linux/arch/arm/plat-s3c/include/plat/sdhci.h
+/* linux/arch/arm/plat-samsung/include/plat/sdhci.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * Copyright 2008 Openmoko, Inc.
  * Copyright 2008 Simtec Electronics
@@ -119,10 +122,10 @@ extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
-extern void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
-extern void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
-extern void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
-extern void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
+extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
 
 /* S3C2416 SDHCI setup */
 
@@ -334,57 +337,57 @@ static inline void s5pv210_default_sdhci3(void) { }
 
 #endif /* CONFIG_S5PV210_SETUP_SDHCI */
 
-/* S5PV310 SDHCI setup */
-#ifdef CONFIG_S5PV310_SETUP_SDHCI
-extern char *s5pv310_hsmmc_clksrcs[4];
+/* EXYNOS4 SDHCI setup */
+#ifdef CONFIG_EXYNOS4_SETUP_SDHCI
+extern char *exynos4_hsmmc_clksrcs[4];
 
-extern void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev,
+extern void exynos4_setup_sdhci_cfg_card(struct platform_device *dev,
                                            void __iomem *r,
                                            struct mmc_ios *ios,
                                            struct mmc_card *card);
 
-static inline void s5pv310_default_sdhci0(void)
+static inline void exynos4_default_sdhci0(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC
-        s3c_hsmmc0_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
-        s3c_hsmmc0_def_platdata.cfg_gpio = s5pv310_setup_sdhci0_cfg_gpio;
-        s3c_hsmmc0_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
+        s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs;
+        s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio;
+        s3c_hsmmc0_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
 #endif
 }
 
-static inline void s5pv310_default_sdhci1(void)
+static inline void exynos4_default_sdhci1(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC1
-        s3c_hsmmc1_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
-        s3c_hsmmc1_def_platdata.cfg_gpio = s5pv310_setup_sdhci1_cfg_gpio;
-        s3c_hsmmc1_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
+        s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs;
+        s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio;
+        s3c_hsmmc1_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
 #endif
 }
 
-static inline void s5pv310_default_sdhci2(void)
+static inline void exynos4_default_sdhci2(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC2
-        s3c_hsmmc2_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
-        s3c_hsmmc2_def_platdata.cfg_gpio = s5pv310_setup_sdhci2_cfg_gpio;
-        s3c_hsmmc2_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
+        s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs;
+        s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio;
+        s3c_hsmmc2_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
 #endif
 }
 
-static inline void s5pv310_default_sdhci3(void)
+static inline void exynos4_default_sdhci3(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC3
-        s3c_hsmmc3_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
-        s3c_hsmmc3_def_platdata.cfg_gpio = s5pv310_setup_sdhci3_cfg_gpio;
-        s3c_hsmmc3_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
+        s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs;
+        s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio;
+        s3c_hsmmc3_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
 #endif
 }
 
 #else
-static inline void s5pv310_default_sdhci0(void) { }
-static inline void s5pv310_default_sdhci1(void) { }
-static inline void s5pv310_default_sdhci2(void) { }
-static inline void s5pv310_default_sdhci3(void) { }
+static inline void exynos4_default_sdhci0(void) { }
+static inline void exynos4_default_sdhci1(void) { }
+static inline void exynos4_default_sdhci2(void) { }
+static inline void exynos4_default_sdhci3(void) { }
 
-#endif /* CONFIG_S5PV310_SETUP_SDHCI */
+#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
 
 #endif /* __PLAT_S3C_SDHCI_H */
diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c
index 2eeb49fa056d..f37457c52064 100644
--- a/arch/arm/plat-samsung/pwm.c
+++ b/arch/arm/plat-samsung/pwm.c
@@ -20,10 +20,8 @@
 #include <linux/io.h>
 #include <linux/pwm.h>
 
-#include <mach/irqs.h>
 #include <mach/map.h>
 
-#include <plat/devs.h>
 #include <plat/regs-timer.h>
 
 struct pwm_device {
@@ -47,37 +45,6 @@ struct pwm_device {
 
 static struct clk *clk_scaler[2];
 
-/* Standard setup for a timer block. */
-
-#define TIMER_RESOURCE_SIZE (1)
-
-#define TIMER_RESOURCE(_tmr, _irq)                      \
-        (struct resource [TIMER_RESOURCE_SIZE]) {       \
-                [0] = {                                 \
-                        .start  = _irq,                 \
-                        .end    = _irq,                 \
-                        .flags  = IORESOURCE_IRQ        \
-                }                                       \
-        }
-
-#define DEFINE_S3C_TIMER(_tmr_no, _irq)                 \
-        .name           = "s3c24xx-pwm",                \
-        .id             = _tmr_no,                      \
-        .num_resources  = TIMER_RESOURCE_SIZE,          \
-        .resource       = TIMER_RESOURCE(_tmr_no, _irq),        \
-
-/* since we already have an static mapping for the timer, we do not
- * bother setting any IO resource for the base.
- */
-
-struct platform_device s3c_device_timer[] = {
-        [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
-        [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
-        [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
-        [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
-        [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
-};
-
 static inline int pwm_is_tdiv(struct pwm_device *pwm)
 {
         return clk_get_parent(pwm->clk) == pwm->clk_div;
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index a6dfa37a674d..fdca643249e1 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -81,6 +81,17 @@ config MFD_DM355EVM_MSP
           boards.  MSP430 firmware manages resets and power sequencing,
           inputs from buttons and the IR remote, LEDs, an RTC, and more.
 
+config MFD_TI_SSP
+        tristate "TI Sequencer Serial Port support"
+        depends on ARCH_DAVINCI_TNETV107X
+        select MFD_CORE
+        ---help---
+          Say Y here if you want support for the Sequencer Serial Port
+          in a Texas Instruments TNETV107X SoC.
+
+          To compile this driver as a module, choose M here: the
+          module will be called ti-ssp.
+
 config HTC_EGPIO
         bool "HTC EGPIO support"
         depends on GENERIC_HARDIRQS && GPIOLIB && ARM
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 91fe384459ab..f0e25cad762e 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_HTC_I2CPLD)	+= htc-i2cpld.o
 
 obj-$(CONFIG_MFD_DAVINCI_VOICECODEC)    += davinci_voicecodec.o
 obj-$(CONFIG_MFD_DM355EVM_MSP)  += dm355evm_msp.o
+obj-$(CONFIG_MFD_TI_SSP)        += ti-ssp.o
 
 obj-$(CONFIG_MFD_STMPE)         += stmpe.o
 obj-$(CONFIG_MFD_TC3589X)       += tc3589x.o
diff --git a/drivers/mfd/ti-ssp.c b/drivers/mfd/ti-ssp.c
new file mode 100644
index 000000000000..af9ab0e5ca64
--- /dev/null
+++ b/drivers/mfd/ti-ssp.c
@@ -0,0 +1,476 @@
+/*
+ * Sequencer Serial Port (SSP) driver for Texas Instruments' SoCs
+ *
+ * Copyright (C) 2010 Texas Instruments Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/wait.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/ti_ssp.h>
+
+/* Register Offsets */
+#define REG_REV         0x00
+#define REG_IOSEL_1     0x04
+#define REG_IOSEL_2     0x08
+#define REG_PREDIV      0x0c
+#define REG_INTR_ST     0x10
+#define REG_INTR_EN     0x14
+#define REG_TEST_CTRL   0x18
+
+/* Per port registers */
+#define PORT_CFG_2      0x00
+#define PORT_ADDR       0x04
+#define PORT_DATA       0x08
+#define PORT_CFG_1      0x0c
+#define PORT_STATE      0x10
+
+#define SSP_PORT_CONFIG_MASK    (SSP_EARLY_DIN | SSP_DELAY_DOUT)
+#define SSP_PORT_CLKRATE_MASK   0x0f
+
+#define SSP_SEQRAM_WR_EN        BIT(4)
+#define SSP_SEQRAM_RD_EN        BIT(5)
+#define SSP_START               BIT(15)
+#define SSP_BUSY                BIT(10)
+#define SSP_PORT_ASL            BIT(7)
+#define SSP_PORT_CFO1           BIT(6)
+
+#define SSP_PORT_SEQRAM_SIZE    32
+
+static const int ssp_port_base[]   = {0x040, 0x080};
+static const int ssp_port_seqram[] = {0x100, 0x180};
+
+struct ti_ssp {
+        struct resource         *res;
+        struct device           *dev;
+        void __iomem            *regs;
+        spinlock_t              lock;
+        struct clk              *clk;
+        int                     irq;
+        wait_queue_head_t       wqh;
+
+        /*
+         * Some of the iosel2 register bits always read-back as 0, we need to
+         * remember these values so that we don't clobber previously set
+         * values.
+         */
+        u32                     iosel2;
+};
+
+static inline struct ti_ssp *dev_to_ssp(struct device *dev)
+{
+        return dev_get_drvdata(dev->parent);
+}
+
+static inline int dev_to_port(struct device *dev)
+{
+        return to_platform_device(dev)->id;
+}
+
+/* Register Access Helpers, rmw() functions need to run locked */
+static inline u32 ssp_read(struct ti_ssp *ssp, int reg)
+{
+        return __raw_readl(ssp->regs + reg);
+}
+
+static inline void ssp_write(struct ti_ssp *ssp, int reg, u32 val)
+{
+        __raw_writel(val, ssp->regs + reg);
+}
+
+static inline void ssp_rmw(struct ti_ssp *ssp, int reg, u32 mask, u32 bits)
+{
+        ssp_write(ssp, reg, (ssp_read(ssp, reg) & ~mask) | bits);
+}
+
+static inline u32 ssp_port_read(struct ti_ssp *ssp, int port, int reg)
+{
+        return ssp_read(ssp, ssp_port_base[port] + reg);
+}
+
+static inline void ssp_port_write(struct ti_ssp *ssp, int port, int reg,
+                                  u32 val)
+{
+        ssp_write(ssp, ssp_port_base[port] + reg, val);
+}
+
+static inline void ssp_port_rmw(struct ti_ssp *ssp, int port, int reg,
+                                u32 mask, u32 bits)
+{
+        ssp_rmw(ssp, ssp_port_base[port] + reg, mask, bits);
+}
+
+static inline void ssp_port_clr_bits(struct ti_ssp *ssp, int port, int reg,
+                                     u32 bits)
+{
+        ssp_port_rmw(ssp, port, reg, bits, 0);
+}
+
+static inline void ssp_port_set_bits(struct ti_ssp *ssp, int port, int reg,
+                                     u32 bits)
+{
+        ssp_port_rmw(ssp, port, reg, 0, bits);
+}
+
+/* Called to setup port clock mode, caller must hold ssp->lock */
+static int __set_mode(struct ti_ssp *ssp, int port, int mode)
+{
+        mode &= SSP_PORT_CONFIG_MASK;
+        ssp_port_rmw(ssp, port, PORT_CFG_1, SSP_PORT_CONFIG_MASK, mode);
+
+        return 0;
+}
+
+int ti_ssp_set_mode(struct device *dev, int mode)
+{
+        struct ti_ssp *ssp = dev_to_ssp(dev);
+        int port = dev_to_port(dev);
+        int ret;
+
+        spin_lock(&ssp->lock);
+        ret = __set_mode(ssp, port, mode);
+        spin_unlock(&ssp->lock);
+
+        return ret;
+}
+EXPORT_SYMBOL(ti_ssp_set_mode);
+
+/* Called to setup iosel2, caller must hold ssp->lock */
+static void __set_iosel2(struct ti_ssp *ssp, u32 mask, u32 val)
+{
+        ssp->iosel2 = (ssp->iosel2 & ~mask) | val;
+        ssp_write(ssp, REG_IOSEL_2, ssp->iosel2);
+}
+
+/* Called to setup port iosel, caller must hold ssp->lock */
+static void __set_iosel(struct ti_ssp *ssp, int port, u32 iosel)
+{
+        unsigned val, shift = port ? 16 : 0;
+
+        /* IOSEL1 gets the least significant 16 bits */
+        val = ssp_read(ssp, REG_IOSEL_1);
+        val &= 0xffff << (port ? 0 : 16);
+        val |= (iosel & 0xffff) << (port ? 16 : 0);
+        ssp_write(ssp, REG_IOSEL_1, val);
+
+        /* IOSEL2 gets the most significant 16 bits */
+        val = (iosel >> 16) & 0x7;
+        __set_iosel2(ssp, 0x7 << shift, val << shift);
+}
+
+int ti_ssp_set_iosel(struct device *dev, u32 iosel)
+{
+        struct ti_ssp *ssp = dev_to_ssp(dev);
+        int port = dev_to_port(dev);
+
+        spin_lock(&ssp->lock);
+        __set_iosel(ssp, port, iosel);
+        spin_unlock(&ssp->lock);
+
+        return 0;
+}
+EXPORT_SYMBOL(ti_ssp_set_iosel);
+
+int ti_ssp_load(struct device *dev, int offs, u32* prog, int len)
+{
+        struct ti_ssp *ssp = dev_to_ssp(dev);
+        int port = dev_to_port(dev);
+        int i;
+
+        if (len > SSP_PORT_SEQRAM_SIZE)
+                return -ENOSPC;
+
+        spin_lock(&ssp->lock);
+
+        /* Enable SeqRAM access */
+        ssp_port_set_bits(ssp, port, PORT_CFG_2, SSP_SEQRAM_WR_EN);
+
+        /* Copy code */
+        for (i = 0; i < len; i++) {
+                __raw_writel(prog[i], ssp->regs + offs + 4*i +
+                             ssp_port_seqram[port]);
+        }
+
+        /* Disable SeqRAM access */
+        ssp_port_clr_bits(ssp, port, PORT_CFG_2, SSP_SEQRAM_WR_EN);
+
+        spin_unlock(&ssp->lock);
+
+        return 0;
+}
+EXPORT_SYMBOL(ti_ssp_load);
+
+int ti_ssp_raw_read(struct device *dev)
+{
+        struct ti_ssp *ssp = dev_to_ssp(dev);
+        int port = dev_to_port(dev);
+        int shift = port ? 27 : 11;
+
+        return (ssp_read(ssp, REG_IOSEL_2) >> shift) & 0xf;
+}
+EXPORT_SYMBOL(ti_ssp_raw_read);
+
+int ti_ssp_raw_write(struct device *dev, u32 val)
+{
+        struct ti_ssp *ssp = dev_to_ssp(dev);
+        int port = dev_to_port(dev), shift;
+
+        spin_lock(&ssp->lock);
+
+        shift = port ? 22 : 6;
+        val &= 0xf;
+        __set_iosel2(ssp, 0xf << shift, val << shift);
+
+        spin_unlock(&ssp->lock);
+
+        return 0;
+}
+EXPORT_SYMBOL(ti_ssp_raw_write);
+
+static inline int __xfer_done(struct ti_ssp *ssp, int port)
+{
+        return !(ssp_port_read(ssp, port, PORT_CFG_1) & SSP_BUSY);
+}
+
+int ti_ssp_run(struct device *dev, u32 pc, u32 input, u32 *output)
+{
+        struct ti_ssp *ssp = dev_to_ssp(dev);
+        int port = dev_to_port(dev);
+        int ret;
+
+        if (pc & ~(0x3f))
+                return -EINVAL;
+
+        /* Grab ssp->lock to serialize rmw on ssp registers */
+        spin_lock(&ssp->lock);
+
+        ssp_port_write(ssp, port, PORT_ADDR, input >> 16);
+        ssp_port_write(ssp, port, PORT_DATA, input & 0xffff);
+        ssp_port_rmw(ssp, port, PORT_CFG_1, 0x3f, pc);
+
+        /* grab wait queue head lock to avoid race with the isr */
+        spin_lock_irq(&ssp->wqh.lock);
+
+        /* kick off sequence execution in hardware */
+        ssp_port_set_bits(ssp, port, PORT_CFG_1, SSP_START);
+
+        /* drop ssp lock; no register writes beyond this */
+        spin_unlock(&ssp->lock);
+
+        ret = wait_event_interruptible_locked_irq(ssp->wqh,
+                                                  __xfer_done(ssp, port));
+        spin_unlock_irq(&ssp->wqh.lock);
+
+        if (ret < 0)
+                return ret;
+
+        if (output) {
+                *output = (ssp_port_read(ssp, port, PORT_ADDR) << 16) |
+                          (ssp_port_read(ssp, port, PORT_DATA) &  0xffff);
+        }
+
+        ret = ssp_port_read(ssp, port, PORT_STATE) & 0x3f; /* stop address */
+
+        return ret;
+}
+EXPORT_SYMBOL(ti_ssp_run);
+
+static irqreturn_t ti_ssp_interrupt(int irq, void *dev_data)
+{
+        struct ti_ssp *ssp = dev_data;
+
+        spin_lock(&ssp->wqh.lock);
+
+        ssp_write(ssp, REG_INTR_ST, 0x3);
+        wake_up_locked(&ssp->wqh);
+
+        spin_unlock(&ssp->wqh.lock);
+
+        return IRQ_HANDLED;
+}
+
+static int __devinit ti_ssp_probe(struct platform_device *pdev)
+{
+        static struct ti_ssp *ssp;
+        const struct ti_ssp_data *pdata = pdev->dev.platform_data;
+        int error = 0, prediv = 0xff, id;
+        unsigned long sysclk;
+        struct device *dev = &pdev->dev;
+        struct mfd_cell cells[2];
+
+        ssp = kzalloc(sizeof(*ssp), GFP_KERNEL);
+        if (!ssp) {
+                dev_err(dev, "cannot allocate device info\n");
+                return -ENOMEM;
+        }
+
+        ssp->dev = dev;
+        dev_set_drvdata(dev, ssp);
+
+        ssp->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!ssp->res) {
+                error = -ENODEV;
+                dev_err(dev, "cannot determine register area\n");
+                goto error_res;
+        }
+
+        if (!request_mem_region(ssp->res->start, resource_size(ssp->res),
+                                pdev->name)) {
+                error = -ENOMEM;
+                dev_err(dev, "cannot claim register memory\n");
+                goto error_res;
+        }
+
+        ssp->regs = ioremap(ssp->res->start, resource_size(ssp->res));
+        if (!ssp->regs) {
+                error = -ENOMEM;
+                dev_err(dev, "cannot map register memory\n");
+                goto error_map;
+        }
+
+        ssp->clk = clk_get(dev, NULL);
+        if (IS_ERR(ssp->clk)) {
+                error = PTR_ERR(ssp->clk);
+                dev_err(dev, "cannot claim device clock\n");
+                goto error_clk;
+        }
+
+        ssp->irq = platform_get_irq(pdev, 0);
+        if (ssp->irq < 0) {
+                error = -ENODEV;
+                dev_err(dev, "unknown irq\n");
+                goto error_irq;
+        }
+
+        error = request_threaded_irq(ssp->irq, NULL, ti_ssp_interrupt, 0,
+                                     dev_name(dev), ssp);
+        if (error < 0) {
+                dev_err(dev, "cannot acquire irq\n");
+                goto error_irq;
+        }
+
+        spin_lock_init(&ssp->lock);
+        init_waitqueue_head(&ssp->wqh);
+
+        /* Power on and initialize SSP */
+        error = clk_enable(ssp->clk);
+        if (error) {
+                dev_err(dev, "cannot enable device clock\n");
+                goto error_enable;
+        }
+
+        /* Reset registers to a sensible known state */
+        ssp_write(ssp, REG_IOSEL_1, 0);
+        ssp_write(ssp, REG_IOSEL_2, 0);
+        ssp_write(ssp, REG_INTR_EN, 0x3);
+        ssp_write(ssp, REG_INTR_ST, 0x3);
+        ssp_write(ssp, REG_TEST_CTRL, 0);
+        ssp_port_write(ssp, 0, PORT_CFG_1, SSP_PORT_ASL);
+        ssp_port_write(ssp, 1, PORT_CFG_1, SSP_PORT_ASL);
+        ssp_port_write(ssp, 0, PORT_CFG_2, SSP_PORT_CFO1);
+        ssp_port_write(ssp, 1, PORT_CFG_2, SSP_PORT_CFO1);
+
+        sysclk = clk_get_rate(ssp->clk);
+        if (pdata && pdata->out_clock)
+                prediv = (sysclk / pdata->out_clock) - 1;
+        prediv = clamp(prediv, 0, 0xff);
+        ssp_rmw(ssp, REG_PREDIV, 0xff, prediv);
+
+        memset(cells, 0, sizeof(cells));
+        for (id = 0; id < 2; id++) {
+                const struct ti_ssp_dev_data *data = &pdata->dev_data[id];
+
+                cells[id].id            = id;
+                cells[id].name          = data->dev_name;
+                cells[id].platform_data = data->pdata;
+                cells[id].data_size     = data->pdata_size;
+        }
+
+        error = mfd_add_devices(dev, 0, cells, 2, NULL, 0);
+        if (error < 0) {
+                dev_err(dev, "cannot add mfd cells\n");
+                goto error_enable;
+        }
+
+        return 0;
+
+error_enable:
+        free_irq(ssp->irq, ssp);
+error_irq:
+        clk_put(ssp->clk);
+error_clk:
+        iounmap(ssp->regs);
+error_map:
+        release_mem_region(ssp->res->start, resource_size(ssp->res));
+error_res:
+        kfree(ssp);
+        return error;
+}
+
+static int __devexit ti_ssp_remove(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct ti_ssp *ssp = dev_get_drvdata(dev);
+
+        mfd_remove_devices(dev);
+        clk_disable(ssp->clk);
+        free_irq(ssp->irq, ssp);
+        clk_put(ssp->clk);
+        iounmap(ssp->regs);
+        release_mem_region(ssp->res->start, resource_size(ssp->res));
+        kfree(ssp);
+        dev_set_drvdata(dev, NULL);
+        return 0;
+}
+
+static struct platform_driver ti_ssp_driver = {
+        .probe          = ti_ssp_probe,
+        .remove         = __devexit_p(ti_ssp_remove),
+        .driver         = {
+                .name   = "ti-ssp",
+                .owner  = THIS_MODULE,
+        }
+};
+
+static int __init ti_ssp_init(void)
+{
+        return platform_driver_register(&ti_ssp_driver);
+}
+module_init(ti_ssp_init);
+
+static void __exit ti_ssp_exit(void)
+{
+        platform_driver_unregister(&ti_ssp_driver);
+}
+module_exit(ti_ssp_exit);
+
+MODULE_DESCRIPTION("Sequencer Serial Port (SSP) Driver");
+MODULE_AUTHOR("Cyril Chemparathy");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ti-ssp");
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index c89592239bc7..450afc5df0bd 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -476,7 +476,7 @@ config MTD_NAND_MPC5121_NFC
 
 config MTD_NAND_MXC
         tristate "MXC NAND support"
-        depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 || ARCH_MX51
+        depends on IMX_HAVE_PLATFORM_MXC_NAND
         help
           This enables the driver for the NAND flash controller on the
           MXC processors.
diff --git a/drivers/mtd/onenand/Kconfig b/drivers/mtd/onenand/Kconfig
index 4dbd0f58eebf..4f426195f8db 100644
--- a/drivers/mtd/onenand/Kconfig
+++ b/drivers/mtd/onenand/Kconfig
@@ -32,7 +32,7 @@ config MTD_ONENAND_OMAP2
 
 config MTD_ONENAND_SAMSUNG
         tristate "OneNAND on Samsung SOC controller support"
-        depends on ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310
+        depends on ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4
         help
           Support for a OneNAND flash device connected to an Samsung SOC.
           S3C64XX/S5PC100 use command mapping method.
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index bb233a9cbad2..7b90fc361b52 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -161,13 +161,13 @@ config SPI_IMX_VER_0_0
         def_bool y if SOC_IMX21 || SOC_IMX27
 
 config SPI_IMX_VER_0_4
-        def_bool y if ARCH_MX31
+        def_bool y if SOC_IMX31
 
 config SPI_IMX_VER_0_7
-        def_bool y if ARCH_MX25 || ARCH_MX35 || ARCH_MX51 || ARCH_MX53
+        def_bool y if ARCH_MX25 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53
 
 config SPI_IMX_VER_2_3
-        def_bool y if ARCH_MX51 || ARCH_MX53
+        def_bool y if SOC_IMX51 || SOC_IMX53
 
 config SPI_IMX
         tristate "Freescale i.MX SPI controllers"
@@ -350,6 +350,16 @@ config SPI_TEGRA
         help
           SPI driver for NVidia Tegra SoCs
 
+config SPI_TI_SSP
+        tristate "TI Sequencer Serial Port - SPI Support"
+        depends on MFD_TI_SSP
+        help
+          This selects an SPI master implementation using a TI sequencer
+          serial port.
+
+          To compile this driver as a module, choose M here: the
+          module will be called ti-ssp-spi.
+
 config SPI_TOPCLIFF_PCH
         tristate "Topcliff PCH SPI Controller"
         depends on PCI
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 86d1b5f9bbd9..f3f31d988358 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_SPI_S3C24XX_GPIO)		+= spi_s3c24xx_gpio.o
 obj-$(CONFIG_SPI_S3C24XX)               += spi_s3c24xx_hw.o
 obj-$(CONFIG_SPI_S3C64XX)               += spi_s3c64xx.o
 obj-$(CONFIG_SPI_TEGRA)                 += spi_tegra.o
+obj-$(CONFIG_SPI_TI_SSP)                += ti-ssp-spi.o
 obj-$(CONFIG_SPI_TOPCLIFF_PCH)          += spi_topcliff_pch.o
 obj-$(CONFIG_SPI_TXX9)                  += spi_txx9.o
 obj-$(CONFIG_SPI_XILINX)                += xilinx_spi.o
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 6beab99bf95b..166a879fd9e8 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -790,7 +790,6 @@ static int davinci_spi_probe(struct platform_device *pdev)
         struct resource *r, *mem;
         resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
         resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
-        resource_size_t dma_eventq = SPI_NO_RESOURCE;
         int i = 0, ret = 0;
         u32 spipc0;
 
@@ -878,17 +877,13 @@ static int davinci_spi_probe(struct platform_device *pdev)
         r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
         if (r)
                 dma_tx_chan = r->start;
-        r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
-        if (r)
-                dma_eventq = r->start;
 
         dspi->bitbang.txrx_bufs = davinci_spi_bufs;
         if (dma_rx_chan != SPI_NO_RESOURCE &&
-            dma_tx_chan != SPI_NO_RESOURCE &&
-            dma_eventq != SPI_NO_RESOURCE) {
+            dma_tx_chan != SPI_NO_RESOURCE) {
                 dspi->dma.rx_channel = dma_rx_chan;
                 dspi->dma.tx_channel = dma_tx_chan;
-                dspi->dma.eventq = dma_eventq;
+                dspi->dma.eventq = pdata->dma_event_q;
 
                 ret = davinci_spi_request_dma(dspi);
                 if (ret)
@@ -897,7 +892,7 @@ static int davinci_spi_probe(struct platform_device *pdev)
                 dev_info(&pdev->dev, "DMA: supported\n");
                 dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, "
                                 "event queue: %d\n", dma_rx_chan, dma_tx_chan,
-                                dma_eventq);
+                                pdata->dma_event_q);
         }
 
         dspi->get_rx = davinci_spi_rx_buf_u8;
diff --git a/drivers/spi/ti-ssp-spi.c b/drivers/spi/ti-ssp-spi.c
new file mode 100644
index 000000000000..ee22795c7973
--- /dev/null
+++ b/drivers/spi/ti-ssp-spi.c
@@ -0,0 +1,402 @@
+/*
+ * Sequencer Serial Port (SSP) based SPI master driver
+ *
+ * Copyright (C) 2010 Texas Instruments Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/ti_ssp.h>
+
+#define MODE_BITS       (SPI_CPHA | SPI_CPOL | SPI_CS_HIGH)
+
+struct ti_ssp_spi {
+        struct spi_master               *master;
+        struct device                   *dev;
+        spinlock_t                      lock;
+        struct list_head                msg_queue;
+        struct completion               complete;
+        bool                            shutdown;
+        struct workqueue_struct         *workqueue;
+        struct work_struct              work;
+        u8                              mode, bpw;
+        int                             cs_active;
+        u32                             pc_en, pc_dis, pc_wr, pc_rd;
+        void                            (*select)(int cs);
+};
+
+static u32 ti_ssp_spi_rx(struct ti_ssp_spi *hw)
+{
+        u32 ret;
+
+        ti_ssp_run(hw->dev, hw->pc_rd, 0, &ret);
+        return ret;
+}
+
+static void ti_ssp_spi_tx(struct ti_ssp_spi *hw, u32 data)
+{
+        ti_ssp_run(hw->dev, hw->pc_wr, data << (32 - hw->bpw), NULL);
+}
+
+static int ti_ssp_spi_txrx(struct ti_ssp_spi *hw, struct spi_message *msg,
+                       struct spi_transfer *t)
+{
+        int count;
+
+        if (hw->bpw <= 8) {
+                u8              *rx = t->rx_buf;
+                const u8        *tx = t->tx_buf;
+
+                for (count = 0; count < t->len; count += 1) {
+                        if (t->tx_buf)
+                                ti_ssp_spi_tx(hw, *tx++);
+                        if (t->rx_buf)
+                                *rx++ = ti_ssp_spi_rx(hw);
+                }
+        } else if (hw->bpw <= 16) {
+                u16             *rx = t->rx_buf;
+                const u16       *tx = t->tx_buf;
+
+                for (count = 0; count < t->len; count += 2) {
+                        if (t->tx_buf)
+                                ti_ssp_spi_tx(hw, *tx++);
+                        if (t->rx_buf)
+                                *rx++ = ti_ssp_spi_rx(hw);
+                }
+        } else {
+                u32             *rx = t->rx_buf;
+                const u32       *tx = t->tx_buf;
+
+                for (count = 0; count < t->len; count += 4) {
+                        if (t->tx_buf)
+                                ti_ssp_spi_tx(hw, *tx++);
+                        if (t->rx_buf)
+                                *rx++ = ti_ssp_spi_rx(hw);
+                }
+        }
+
+        msg->actual_length += count; /* bytes transferred */
+
+        dev_dbg(&msg->spi->dev, "xfer %s%s, %d bytes, %d bpw, count %d%s\n",
+                t->tx_buf ? "tx" : "", t->rx_buf ? "rx" : "", t->len,
+                hw->bpw, count, (count < t->len) ? " (under)" : "");
+
+        return (count < t->len) ? -EIO : 0; /* left over data */
+}
+
+static void ti_ssp_spi_chip_select(struct ti_ssp_spi *hw, int cs_active)
+{
+        cs_active = !!cs_active;
+        if (cs_active == hw->cs_active)
+                return;
+        ti_ssp_run(hw->dev, cs_active ? hw->pc_en : hw->pc_dis, 0, NULL);
+        hw->cs_active = cs_active;
+}
+
+#define __SHIFT_OUT(bits)       (SSP_OPCODE_SHIFT | SSP_OUT_MODE | \
+                                 cs_en | clk | SSP_COUNT((bits) * 2 - 1))
+#define __SHIFT_IN(bits)        (SSP_OPCODE_SHIFT | SSP_IN_MODE  | \
+                                 cs_en | clk | SSP_COUNT((bits) * 2 - 1))
+
+static int ti_ssp_spi_setup_transfer(struct ti_ssp_spi *hw, u8 bpw, u8 mode)
+{
+        int error, idx = 0;
+        u32 seqram[16];
+        u32 cs_en, cs_dis, clk;
+        u32 topbits, botbits;
+
+        mode &= MODE_BITS;
+        if (mode == hw->mode && bpw == hw->bpw)
+                return 0;
+
+        cs_en  = (mode & SPI_CS_HIGH) ? SSP_CS_HIGH : SSP_CS_LOW;
+        cs_dis = (mode & SPI_CS_HIGH) ? SSP_CS_LOW  : SSP_CS_HIGH;
+        clk    = (mode & SPI_CPOL)    ? SSP_CLK_HIGH : SSP_CLK_LOW;
+
+        /* Construct instructions */
+
+        /* Disable Chip Select */
+        hw->pc_dis = idx;
+        seqram[idx++] = SSP_OPCODE_DIRECT | SSP_OUT_MODE | cs_dis | clk;
+        seqram[idx++] = SSP_OPCODE_STOP   | SSP_OUT_MODE | cs_dis | clk;
+
+        /* Enable Chip Select */
+        hw->pc_en = idx;
+        seqram[idx++] = SSP_OPCODE_DIRECT | SSP_OUT_MODE | cs_en | clk;
+        seqram[idx++] = SSP_OPCODE_STOP   | SSP_OUT_MODE | cs_en | clk;
+
+        /* Reads and writes need to be split for bpw > 16 */
+        topbits = (bpw > 16) ? 16 : bpw;
+        botbits = bpw - topbits;
+
+        /* Write */
+        hw->pc_wr = idx;
+        seqram[idx++] = __SHIFT_OUT(topbits) | SSP_ADDR_REG;
+        if (botbits)
+                seqram[idx++] = __SHIFT_OUT(botbits)  | SSP_DATA_REG;
+        seqram[idx++] = SSP_OPCODE_STOP | SSP_OUT_MODE | cs_en | clk;
+
+        /* Read */
+        hw->pc_rd = idx;
+        if (botbits)
+                seqram[idx++] = __SHIFT_IN(botbits) | SSP_ADDR_REG;
+        seqram[idx++] = __SHIFT_IN(topbits) | SSP_DATA_REG;
+        seqram[idx++] = SSP_OPCODE_STOP | SSP_OUT_MODE | cs_en | clk;
+
+        error = ti_ssp_load(hw->dev, 0, seqram, idx);
+        if (error < 0)
+                return error;
+
+        error = ti_ssp_set_mode(hw->dev, ((mode & SPI_CPHA) ?
+                                          0 : SSP_EARLY_DIN));
+        if (error < 0)
+                return error;
+
+        hw->bpw = bpw;
+        hw->mode = mode;
+
+        return error;
+}
+
+static void ti_ssp_spi_work(struct work_struct *work)
+{
+        struct ti_ssp_spi *hw = container_of(work, struct ti_ssp_spi, work);
+
+        spin_lock(&hw->lock);
+
+         while (!list_empty(&hw->msg_queue)) {
+                struct spi_message      *m;
+                struct spi_device       *spi;
+                struct spi_transfer     *t = NULL;
+                int                     status = 0;
+
+                m = container_of(hw->msg_queue.next, struct spi_message,
+                                 queue);
+
+                list_del_init(&m->queue);
+
+                spin_unlock(&hw->lock);
+
+                spi = m->spi;
+
+                if (hw->select)
+                        hw->select(spi->chip_select);
+
+                list_for_each_entry(t, &m->transfers, transfer_list) {
+                        int bpw = spi->bits_per_word;
+                        int xfer_status;
+
+                        if (t->bits_per_word)
+                                bpw = t->bits_per_word;
+
+                        if (ti_ssp_spi_setup_transfer(hw, bpw, spi->mode) < 0)
+                                break;
+
+                        ti_ssp_spi_chip_select(hw, 1);
+
+                        xfer_status = ti_ssp_spi_txrx(hw, m, t);
+                        if (xfer_status < 0)
+                                status = xfer_status;
+
+                        if (t->delay_usecs)
+                                udelay(t->delay_usecs);
+
+                        if (t->cs_change)
+                                ti_ssp_spi_chip_select(hw, 0);
+                }
+
+                ti_ssp_spi_chip_select(hw, 0);
+                m->status = status;
+                m->complete(m->context);
+
+                spin_lock(&hw->lock);
+        }
+
+        if (hw->shutdown)
+                complete(&hw->complete);
+
+        spin_unlock(&hw->lock);
+}
+
+static int ti_ssp_spi_setup(struct spi_device *spi)
+{
+        if (spi->bits_per_word > 32)
+                return -EINVAL;
+
+        return 0;
+}
+
+static int ti_ssp_spi_transfer(struct spi_device *spi, struct spi_message *m)
+{
+        struct ti_ssp_spi       *hw;
+        struct spi_transfer     *t;
+        int                     error = 0;
+
+        m->actual_length = 0;
+        m->status = -EINPROGRESS;
+
+        hw = spi_master_get_devdata(spi->master);
+
+        if (list_empty(&m->transfers) || !m->complete)
+                return -EINVAL;
+
+        list_for_each_entry(t, &m->transfers, transfer_list) {
+                if (t->len && !(t->rx_buf || t->tx_buf)) {
+                        dev_err(&spi->dev, "invalid xfer, no buffer\n");
+                        return -EINVAL;
+                }
+
+                if (t->len && t->rx_buf && t->tx_buf) {
+                        dev_err(&spi->dev, "invalid xfer, full duplex\n");
+                        return -EINVAL;
+                }
+
+                if (t->bits_per_word > 32) {
+                        dev_err(&spi->dev, "invalid xfer width %d\n",
+                                t->bits_per_word);
+                        return -EINVAL;
+                }
+        }
+
+        spin_lock(&hw->lock);
+        if (hw->shutdown) {
+                error = -ESHUTDOWN;
+                goto error_unlock;
+        }
+        list_add_tail(&m->queue, &hw->msg_queue);
+        queue_work(hw->workqueue, &hw->work);
+error_unlock:
+        spin_unlock(&hw->lock);
+        return error;
+}
+
+static int __devinit ti_ssp_spi_probe(struct platform_device *pdev)
+{
+        const struct ti_ssp_spi_data *pdata;
+        struct ti_ssp_spi *hw;
+        struct spi_master *master;
+        struct device *dev = &pdev->dev;
+        int error = 0;
+
+        pdata = dev->platform_data;
+        if (!pdata) {
+                dev_err(dev, "platform data not found\n");
+                return -EINVAL;
+        }
+
+        master = spi_alloc_master(dev, sizeof(struct ti_ssp_spi));
+        if (!master) {
+                dev_err(dev, "cannot allocate SPI master\n");
+                return -ENOMEM;
+        }
+
+        hw = spi_master_get_devdata(master);
+        platform_set_drvdata(pdev, hw);
+
+        hw->master = master;
+        hw->dev = dev;
+        hw->select = pdata->select;
+
+        spin_lock_init(&hw->lock);
+        init_completion(&hw->complete);
+        INIT_LIST_HEAD(&hw->msg_queue);
+        INIT_WORK(&hw->work, ti_ssp_spi_work);
+
+        hw->workqueue = create_singlethread_workqueue(dev_name(dev));
+        if (!hw->workqueue) {
+                error = -ENOMEM;
+                dev_err(dev, "work queue creation failed\n");
+                goto error_wq;
+        }
+
+        error = ti_ssp_set_iosel(hw->dev, pdata->iosel);
+        if (error < 0) {
+                dev_err(dev, "io setup failed\n");
+                goto error_iosel;
+        }
+
+        master->bus_num         = pdev->id;
+        master->num_chipselect  = pdata->num_cs;
+        master->mode_bits       = MODE_BITS;
+        master->flags           = SPI_MASTER_HALF_DUPLEX;
+        master->setup           = ti_ssp_spi_setup;
+        master->transfer        = ti_ssp_spi_transfer;
+
+        error = spi_register_master(master);
+        if (error) {
+                dev_err(dev, "master registration failed\n");
+                goto error_reg;
+        }
+
+        return 0;
+
+error_reg:
+error_iosel:
+        destroy_workqueue(hw->workqueue);
+error_wq:
+        spi_master_put(master);
+        return error;
+}
+
+static int __devexit ti_ssp_spi_remove(struct platform_device *pdev)
+{
+        struct ti_ssp_spi *hw = platform_get_drvdata(pdev);
+        int error;
+
+        hw->shutdown = 1;
+        while (!list_empty(&hw->msg_queue)) {
+                error = wait_for_completion_interruptible(&hw->complete);
+                if (error < 0) {
+                        hw->shutdown = 0;
+                        return error;
+                }
+        }
+        destroy_workqueue(hw->workqueue);
+        spi_unregister_master(hw->master);
+
+        return 0;
+}
+
+static struct platform_driver ti_ssp_spi_driver = {
+        .probe          = ti_ssp_spi_probe,
+        .remove         = __devexit_p(ti_ssp_spi_remove),
+        .driver         = {
+                .name   = "ti-ssp-spi",
+                .owner  = THIS_MODULE,
+        },
+};
+
+static int __init ti_ssp_spi_init(void)
+{
+        return platform_driver_register(&ti_ssp_spi_driver);
+}
+module_init(ti_ssp_spi_init);
+
+static void __exit ti_ssp_spi_exit(void)
+{
+        platform_driver_unregister(&ti_ssp_spi_driver);
+}
+module_exit(ti_ssp_spi_exit);
+
+MODULE_DESCRIPTION("SSP SPI Master");
+MODULE_AUTHOR("Cyril Chemparathy");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ti-ssp-spi");
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index e461be164f67..e1aee37270f5 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -537,8 +537,8 @@ config SERIAL_S3C6400
 
 config SERIAL_S5PV210
         tristate "Samsung S5PV210 Serial port support"
-        depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442 || CPU_S5PV310)
-        select SERIAL_SAMSUNG_UARTS_4 if (CPU_S5PV210 || CPU_S5PV310)
+        depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442 || CPU_EXYNOS4210)
+        select SERIAL_SAMSUNG_UARTS_4 if (CPU_S5PV210 || CPU_EXYNOS4210)
         default y
         help
           Serial port support for Samsung's S5P Family of SoC's
@@ -1598,4 +1598,18 @@ config SERIAL_MSM_SMD
           Enables userspace clients to read and write to some streaming SMD
           ports via tty device interface for MSM chipset.
 
+config SERIAL_MXS_AUART
+        depends on ARCH_MXS
+        tristate "MXS AUART support"
+        select SERIAL_CORE
+        help
+          This driver supports the MXS Application UART (AUART) port.
+
+config SERIAL_MXS_AUART_CONSOLE
+        bool "MXS AUART console support"
+        depends on SERIAL_MXS_AUART=y
+        select SERIAL_CORE_CONSOLE
+        help
+          Enable a MXS AUART port to be the system console.
+
 endmenu
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 31e868cb49b2..fee0690ef8e3 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -93,3 +93,4 @@ obj-$(CONFIG_SERIAL_MFD_HSU)	+= mfd.o
 obj-$(CONFIG_SERIAL_IFX6X60)    += ifx6x60.o
 obj-$(CONFIG_SERIAL_PCH_UART)   += pch_uart.o
 obj-$(CONFIG_SERIAL_MSM_SMD)    += msm_smd_tty.o
+obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
new file mode 100644
index 000000000000..7e02c9c344fe
--- /dev/null
+++ b/drivers/tty/serial/mxs-auart.c
@@ -0,0 +1,798 @@
+/*
+ * Freescale STMP37XX/STMP378X Application UART driver
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/wait.h>
+#include <linux/tty.h>
+#include <linux/tty_driver.h>
+#include <linux/tty_flip.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+
+#define MXS_AUART_PORTS 5
+
+#define AUART_CTRL0                     0x00000000
+#define AUART_CTRL0_SET                 0x00000004
+#define AUART_CTRL0_CLR                 0x00000008
+#define AUART_CTRL0_TOG                 0x0000000c
+#define AUART_CTRL1                     0x00000010
+#define AUART_CTRL1_SET                 0x00000014
+#define AUART_CTRL1_CLR                 0x00000018
+#define AUART_CTRL1_TOG                 0x0000001c
+#define AUART_CTRL2                     0x00000020
+#define AUART_CTRL2_SET                 0x00000024
+#define AUART_CTRL2_CLR                 0x00000028
+#define AUART_CTRL2_TOG                 0x0000002c
+#define AUART_LINECTRL                  0x00000030
+#define AUART_LINECTRL_SET              0x00000034
+#define AUART_LINECTRL_CLR              0x00000038
+#define AUART_LINECTRL_TOG              0x0000003c
+#define AUART_LINECTRL2                 0x00000040
+#define AUART_LINECTRL2_SET             0x00000044
+#define AUART_LINECTRL2_CLR             0x00000048
+#define AUART_LINECTRL2_TOG             0x0000004c
+#define AUART_INTR                      0x00000050
+#define AUART_INTR_SET                  0x00000054
+#define AUART_INTR_CLR                  0x00000058
+#define AUART_INTR_TOG                  0x0000005c
+#define AUART_DATA                      0x00000060
+#define AUART_STAT                      0x00000070
+#define AUART_DEBUG                     0x00000080
+#define AUART_VERSION                   0x00000090
+#define AUART_AUTOBAUD                  0x000000a0
+
+#define AUART_CTRL0_SFTRST                      (1 << 31)
+#define AUART_CTRL0_CLKGATE                     (1 << 30)
+
+#define AUART_CTRL2_CTSEN                       (1 << 15)
+#define AUART_CTRL2_RTS                         (1 << 11)
+#define AUART_CTRL2_RXE                         (1 << 9)
+#define AUART_CTRL2_TXE                         (1 << 8)
+#define AUART_CTRL2_UARTEN                      (1 << 0)
+
+#define AUART_LINECTRL_BAUD_DIVINT_SHIFT        16
+#define AUART_LINECTRL_BAUD_DIVINT_MASK         0xffff0000
+#define AUART_LINECTRL_BAUD_DIVINT(v)           (((v) & 0xffff) << 16)
+#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT       8
+#define AUART_LINECTRL_BAUD_DIVFRAC_MASK        0x00003f00
+#define AUART_LINECTRL_BAUD_DIVFRAC(v)          (((v) & 0x3f) << 8)
+#define AUART_LINECTRL_WLEN_MASK                0x00000060
+#define AUART_LINECTRL_WLEN(v)                  (((v) & 0x3) << 5)
+#define AUART_LINECTRL_FEN                      (1 << 4)
+#define AUART_LINECTRL_STP2                     (1 << 3)
+#define AUART_LINECTRL_EPS                      (1 << 2)
+#define AUART_LINECTRL_PEN                      (1 << 1)
+#define AUART_LINECTRL_BRK                      (1 << 0)
+
+#define AUART_INTR_RTIEN                        (1 << 22)
+#define AUART_INTR_TXIEN                        (1 << 21)
+#define AUART_INTR_RXIEN                        (1 << 20)
+#define AUART_INTR_CTSMIEN                      (1 << 17)
+#define AUART_INTR_RTIS                         (1 << 6)
+#define AUART_INTR_TXIS                         (1 << 5)
+#define AUART_INTR_RXIS                         (1 << 4)
+#define AUART_INTR_CTSMIS                       (1 << 1)
+
+#define AUART_STAT_BUSY                         (1 << 29)
+#define AUART_STAT_CTS                          (1 << 28)
+#define AUART_STAT_TXFE                         (1 << 27)
+#define AUART_STAT_TXFF                         (1 << 25)
+#define AUART_STAT_RXFE                         (1 << 24)
+#define AUART_STAT_OERR                         (1 << 19)
+#define AUART_STAT_BERR                         (1 << 18)
+#define AUART_STAT_PERR                         (1 << 17)
+#define AUART_STAT_FERR                         (1 << 16)
+
+static struct uart_driver auart_driver;
+
+struct mxs_auart_port {
+        struct uart_port port;
+
+        unsigned int flags;
+        unsigned int ctrl;
+
+        unsigned int irq;
+
+        struct clk *clk;
+        struct device *dev;
+};
+
+static void mxs_auart_stop_tx(struct uart_port *u);
+
+#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
+
+static inline void mxs_auart_tx_chars(struct mxs_auart_port *s)
+{
+        struct circ_buf *xmit = &s->port.state->xmit;
+
+        while (!(readl(s->port.membase + AUART_STAT) &
+                 AUART_STAT_TXFF)) {
+                if (s->port.x_char) {
+                        s->port.icount.tx++;
+                        writel(s->port.x_char,
+                                     s->port.membase + AUART_DATA);
+                        s->port.x_char = 0;
+                        continue;
+                }
+                if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
+                        s->port.icount.tx++;
+                        writel(xmit->buf[xmit->tail],
+                                     s->port.membase + AUART_DATA);
+                        xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+                        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+                                uart_write_wakeup(&s->port);
+                } else
+                        break;
+        }
+        if (uart_circ_empty(&(s->port.state->xmit)))
+                writel(AUART_INTR_TXIEN,
+                             s->port.membase + AUART_INTR_CLR);
+        else
+                writel(AUART_INTR_TXIEN,
+                             s->port.membase + AUART_INTR_SET);
+
+        if (uart_tx_stopped(&s->port))
+                mxs_auart_stop_tx(&s->port);
+}
+
+static void mxs_auart_rx_char(struct mxs_auart_port *s)
+{
+        int flag;
+        u32 stat;
+        u8 c;
+
+        c = readl(s->port.membase + AUART_DATA);
+        stat = readl(s->port.membase + AUART_STAT);
+
+        flag = TTY_NORMAL;
+        s->port.icount.rx++;
+
+        if (stat & AUART_STAT_BERR) {
+                s->port.icount.brk++;
+                if (uart_handle_break(&s->port))
+                        goto out;
+        } else if (stat & AUART_STAT_PERR) {
+                s->port.icount.parity++;
+        } else if (stat & AUART_STAT_FERR) {
+                s->port.icount.frame++;
+        }
+
+        /*
+         * Mask off conditions which should be ingored.
+         */
+        stat &= s->port.read_status_mask;
+
+        if (stat & AUART_STAT_BERR) {
+                flag = TTY_BREAK;
+        } else if (stat & AUART_STAT_PERR)
+                flag = TTY_PARITY;
+        else if (stat & AUART_STAT_FERR)
+                flag = TTY_FRAME;
+
+        if (stat & AUART_STAT_OERR)
+                s->port.icount.overrun++;
+
+        if (uart_handle_sysrq_char(&s->port, c))
+                goto out;
+
+        uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
+out:
+        writel(stat, s->port.membase + AUART_STAT);
+}
+
+static void mxs_auart_rx_chars(struct mxs_auart_port *s)
+{
+        struct tty_struct *tty = s->port.state->port.tty;
+        u32 stat = 0;
+
+        for (;;) {
+                stat = readl(s->port.membase + AUART_STAT);
+                if (stat & AUART_STAT_RXFE)
+                        break;
+                mxs_auart_rx_char(s);
+        }
+
+        writel(stat, s->port.membase + AUART_STAT);
+        tty_flip_buffer_push(tty);
+}
+
+static int mxs_auart_request_port(struct uart_port *u)
+{
+        return 0;
+}
+
+static int mxs_auart_verify_port(struct uart_port *u,
+                                    struct serial_struct *ser)
+{
+        if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
+                return -EINVAL;
+        return 0;
+}
+
+static void mxs_auart_config_port(struct uart_port *u, int flags)
+{
+}
+
+static const char *mxs_auart_type(struct uart_port *u)
+{
+        struct mxs_auart_port *s = to_auart_port(u);
+
+        return dev_name(s->dev);
+}
+
+static void mxs_auart_release_port(struct uart_port *u)
+{
+}
+
+static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
+{
+        struct mxs_auart_port *s = to_auart_port(u);
+
+        u32 ctrl = readl(u->membase + AUART_CTRL2);
+
+        ctrl &= ~AUART_CTRL2_RTS;
+        if (mctrl & TIOCM_RTS)
+                ctrl |= AUART_CTRL2_RTS;
+        s->ctrl = mctrl;
+        writel(ctrl, u->membase + AUART_CTRL2);
+}
+
+static u32 mxs_auart_get_mctrl(struct uart_port *u)
+{
+        struct mxs_auart_port *s = to_auart_port(u);
+        u32 stat = readl(u->membase + AUART_STAT);
+        int ctrl2 = readl(u->membase + AUART_CTRL2);
+        u32 mctrl = s->ctrl;
+
+        mctrl &= ~TIOCM_CTS;
+        if (stat & AUART_STAT_CTS)
+                mctrl |= TIOCM_CTS;
+
+        if (ctrl2 & AUART_CTRL2_RTS)
+                mctrl |= TIOCM_RTS;
+
+        return mctrl;
+}
+
+static void mxs_auart_settermios(struct uart_port *u,
+                                 struct ktermios *termios,
+                                 struct ktermios *old)
+{
+        u32 bm, ctrl, ctrl2, div;
+        unsigned int cflag, baud;
+
+        cflag = termios->c_cflag;
+
+        ctrl = AUART_LINECTRL_FEN;
+        ctrl2 = readl(u->membase + AUART_CTRL2);
+
+        /* byte size */
+        switch (cflag & CSIZE) {
+        case CS5:
+                bm = 0;
+                break;
+        case CS6:
+                bm = 1;
+                break;
+        case CS7:
+                bm = 2;
+                break;
+        case CS8:
+                bm = 3;
+                break;
+        default:
+                return;
+        }
+
+        ctrl |= AUART_LINECTRL_WLEN(bm);
+
+        /* parity */
+        if (cflag & PARENB) {
+                ctrl |= AUART_LINECTRL_PEN;
+                if ((cflag & PARODD) == 0)
+                        ctrl |= AUART_LINECTRL_EPS;
+        }
+
+        u->read_status_mask = 0;
+
+        if (termios->c_iflag & INPCK)
+                u->read_status_mask |= AUART_STAT_PERR;
+        if (termios->c_iflag & (BRKINT | PARMRK))
+                u->read_status_mask |= AUART_STAT_BERR;
+
+        /*
+         * Characters to ignore
+         */
+        u->ignore_status_mask = 0;
+        if (termios->c_iflag & IGNPAR)
+                u->ignore_status_mask |= AUART_STAT_PERR;
+        if (termios->c_iflag & IGNBRK) {
+                u->ignore_status_mask |= AUART_STAT_BERR;
+                /*
+                 * If we're ignoring parity and break indicators,
+                 * ignore overruns too (for real raw support).
+                 */
+                if (termios->c_iflag & IGNPAR)
+                        u->ignore_status_mask |= AUART_STAT_OERR;
+        }
+
+        /*
+         * ignore all characters if CREAD is not set
+         */
+        if (cflag & CREAD)
+                ctrl2 |= AUART_CTRL2_RXE;
+        else
+                ctrl2 &= ~AUART_CTRL2_RXE;
+
+        /* figure out the stop bits requested */
+        if (cflag & CSTOPB)
+                ctrl |= AUART_LINECTRL_STP2;
+
+        /* figure out the hardware flow control settings */
+        if (cflag & CRTSCTS)
+                ctrl2 |= AUART_CTRL2_CTSEN;
+        else
+                ctrl2 &= ~AUART_CTRL2_CTSEN;
+
+        /* set baud rate */
+        baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
+        div = u->uartclk * 32 / baud;
+        ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
+        ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
+
+        writel(ctrl, u->membase + AUART_LINECTRL);
+        writel(ctrl2, u->membase + AUART_CTRL2);
+}
+
+static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
+{
+        u32 istatus, istat;
+        struct mxs_auart_port *s = context;
+        u32 stat = readl(s->port.membase + AUART_STAT);
+
+        istatus = istat = readl(s->port.membase + AUART_INTR);
+
+        if (istat & AUART_INTR_CTSMIS) {
+                uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
+                writel(AUART_INTR_CTSMIS,
+                                s->port.membase + AUART_INTR_CLR);
+                istat &= ~AUART_INTR_CTSMIS;
+        }
+
+        if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
+                mxs_auart_rx_chars(s);
+                istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
+        }
+
+        if (istat & AUART_INTR_TXIS) {
+                mxs_auart_tx_chars(s);
+                istat &= ~AUART_INTR_TXIS;
+        }
+
+        writel(istatus & (AUART_INTR_RTIS
+                | AUART_INTR_TXIS
+                | AUART_INTR_RXIS
+                | AUART_INTR_CTSMIS),
+                        s->port.membase + AUART_INTR_CLR);
+
+        return IRQ_HANDLED;
+}
+
+static void mxs_auart_reset(struct uart_port *u)
+{
+        int i;
+        unsigned int reg;
+
+        writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
+
+        for (i = 0; i < 10000; i++) {
+                reg = readl(u->membase + AUART_CTRL0);
+                if (!(reg & AUART_CTRL0_SFTRST))
+                        break;
+                udelay(3);
+        }
+        writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
+}
+
+static int mxs_auart_startup(struct uart_port *u)
+{
+        struct mxs_auart_port *s = to_auart_port(u);
+
+        clk_enable(s->clk);
+
+        writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
+
+        writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
+
+        writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
+                        u->membase + AUART_INTR);
+
+        /*
+         * Enable fifo so all four bytes of a DMA word are written to
+         * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
+         */
+        writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
+
+        return 0;
+}
+
+static void mxs_auart_shutdown(struct uart_port *u)
+{
+        struct mxs_auart_port *s = to_auart_port(u);
+
+        writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
+
+        writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
+
+        writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
+                        u->membase + AUART_INTR_CLR);
+
+        clk_disable(s->clk);
+}
+
+static unsigned int mxs_auart_tx_empty(struct uart_port *u)
+{
+        if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
+                return TIOCSER_TEMT;
+        else
+                return 0;
+}
+
+static void mxs_auart_start_tx(struct uart_port *u)
+{
+        struct mxs_auart_port *s = to_auart_port(u);
+
+        /* enable transmitter */
+        writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
+
+        mxs_auart_tx_chars(s);
+}
+
+static void mxs_auart_stop_tx(struct uart_port *u)
+{
+        writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
+}
+
+static void mxs_auart_stop_rx(struct uart_port *u)
+{
+        writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
+}
+
+static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
+{
+        if (ctl)
+                writel(AUART_LINECTRL_BRK,
+                             u->membase + AUART_LINECTRL_SET);
+        else
+                writel(AUART_LINECTRL_BRK,
+                             u->membase + AUART_LINECTRL_CLR);
+}
+
+static void mxs_auart_enable_ms(struct uart_port *port)
+{
+        /* just empty */
+}
+
+static struct uart_ops mxs_auart_ops = {
+        .tx_empty       = mxs_auart_tx_empty,
+        .start_tx       = mxs_auart_start_tx,
+        .stop_tx        = mxs_auart_stop_tx,
+        .stop_rx        = mxs_auart_stop_rx,
+        .enable_ms      = mxs_auart_enable_ms,
+        .break_ctl      = mxs_auart_break_ctl,
+        .set_mctrl      = mxs_auart_set_mctrl,
+        .get_mctrl      = mxs_auart_get_mctrl,
+        .startup        = mxs_auart_startup,
+        .shutdown       = mxs_auart_shutdown,
+        .set_termios    = mxs_auart_settermios,
+        .type           = mxs_auart_type,
+        .release_port   = mxs_auart_release_port,
+        .request_port   = mxs_auart_request_port,
+        .config_port    = mxs_auart_config_port,
+        .verify_port    = mxs_auart_verify_port,
+};
+
+static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
+
+#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
+static void mxs_auart_console_putchar(struct uart_port *port, int ch)
+{
+        unsigned int to = 1000;
+
+        while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
+                if (!to--)
+                        break;
+                udelay(1);
+        }
+
+        writel(ch, port->membase + AUART_DATA);
+}
+
+static void
+auart_console_write(struct console *co, const char *str, unsigned int count)
+{
+        struct mxs_auart_port *s;
+        struct uart_port *port;
+        unsigned int old_ctrl0, old_ctrl2;
+        unsigned int to = 1000;
+
+        if (co->index > MXS_AUART_PORTS || co->index < 0)
+                return;
+
+        s = auart_port[co->index];
+        port = &s->port;
+
+        clk_enable(s->clk);
+
+        /* First save the CR then disable the interrupts */
+        old_ctrl2 = readl(port->membase + AUART_CTRL2);
+        old_ctrl0 = readl(port->membase + AUART_CTRL0);
+
+        writel(AUART_CTRL0_CLKGATE,
+                     port->membase + AUART_CTRL0_CLR);
+        writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
+                     port->membase + AUART_CTRL2_SET);
+
+        uart_console_write(port, str, count, mxs_auart_console_putchar);
+
+        /*
+         * Finally, wait for transmitter to become empty
+         * and restore the TCR
+         */
+        while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
+                if (!to--)
+                        break;
+                udelay(1);
+        }
+
+        writel(old_ctrl0, port->membase + AUART_CTRL0);
+        writel(old_ctrl2, port->membase + AUART_CTRL2);
+
+        clk_disable(s->clk);
+}
+
+static void __init
+auart_console_get_options(struct uart_port *port, int *baud,
+                          int *parity, int *bits)
+{
+        unsigned int lcr_h, quot;
+
+        if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
+                return;
+
+        lcr_h = readl(port->membase + AUART_LINECTRL);
+
+        *parity = 'n';
+        if (lcr_h & AUART_LINECTRL_PEN) {
+                if (lcr_h & AUART_LINECTRL_EPS)
+                        *parity = 'e';
+                else
+                        *parity = 'o';
+        }
+
+        if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
+                *bits = 7;
+        else
+                *bits = 8;
+
+        quot = ((readl(port->membase + AUART_LINECTRL)
+                        & AUART_LINECTRL_BAUD_DIVINT_MASK))
+                            >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
+        quot |= ((readl(port->membase + AUART_LINECTRL)
+                        & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
+                                >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
+        if (quot == 0)
+                quot = 1;
+
+        *baud = (port->uartclk << 2) / quot;
+}
+
+static int __init
+auart_console_setup(struct console *co, char *options)
+{
+        struct mxs_auart_port *s;
+        int baud = 9600;
+        int bits = 8;
+        int parity = 'n';
+        int flow = 'n';
+        int ret;
+
+        /*
+         * Check whether an invalid uart number has been specified, and
+         * if so, search for the first available port that does have
+         * console support.
+         */
+        if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
+                co->index = 0;
+        s = auart_port[co->index];
+        if (!s)
+                return -ENODEV;
+
+        clk_enable(s->clk);
+
+        if (options)
+                uart_parse_options(options, &baud, &parity, &bits, &flow);
+        else
+                auart_console_get_options(&s->port, &baud, &parity, &bits);
+
+        ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
+
+        clk_disable(s->clk);
+
+        return ret;
+}
+
+static struct console auart_console = {
+        .name           = "ttyAPP",
+        .write          = auart_console_write,
+        .device         = uart_console_device,
+        .setup          = auart_console_setup,
+        .flags          = CON_PRINTBUFFER,
+        .index          = -1,
+        .data           = &auart_driver,
+};
+#endif
+
+static struct uart_driver auart_driver = {
+        .owner          = THIS_MODULE,
+        .driver_name    = "ttyAPP",
+        .dev_name       = "ttyAPP",
+        .major          = 0,
+        .minor          = 0,
+        .nr             = MXS_AUART_PORTS,
+#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
+        .cons =         &auart_console,
+#endif
+};
+
+static int __devinit mxs_auart_probe(struct platform_device *pdev)
+{
+        struct mxs_auart_port *s;
+        u32 version;
+        int ret = 0;
+        struct resource *r;
+
+        s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
+        if (!s) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        s->clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(s->clk)) {
+                ret = PTR_ERR(s->clk);
+                goto out_free;
+        }
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!r) {
+                ret = -ENXIO;
+                goto out_free_clk;
+        }
+
+        s->port.mapbase = r->start;
+        s->port.membase = ioremap(r->start, resource_size(r));
+        s->port.ops = &mxs_auart_ops;
+        s->port.iotype = UPIO_MEM;
+        s->port.line = pdev->id < 0 ? 0 : pdev->id;
+        s->port.fifosize = 16;
+        s->port.uartclk = clk_get_rate(s->clk);
+        s->port.type = PORT_IMX;
+        s->port.dev = s->dev = get_device(&pdev->dev);
+
+        s->flags = 0;
+        s->ctrl = 0;
+
+        s->irq = platform_get_irq(pdev, 0);
+        s->port.irq = s->irq;
+        ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
+        if (ret)
+                goto out_free_clk;
+
+        platform_set_drvdata(pdev, s);
+
+        auart_port[pdev->id] = s;
+
+        mxs_auart_reset(&s->port);
+
+        ret = uart_add_one_port(&auart_driver, &s->port);
+        if (ret)
+                goto out_free_irq;
+
+        version = readl(s->port.membase + AUART_VERSION);
+        dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
+               (version >> 24) & 0xff,
+               (version >> 16) & 0xff, version & 0xffff);
+
+        return 0;
+
+out_free_irq:
+        auart_port[pdev->id] = NULL;
+        free_irq(s->irq, s);
+out_free_clk:
+        clk_put(s->clk);
+out_free:
+        kfree(s);
+out:
+        return ret;
+}
+
+static int __devexit mxs_auart_remove(struct platform_device *pdev)
+{
+        struct mxs_auart_port *s = platform_get_drvdata(pdev);
+
+        uart_remove_one_port(&auart_driver, &s->port);
+
+        auart_port[pdev->id] = NULL;
+
+        clk_put(s->clk);
+        free_irq(s->irq, s);
+        kfree(s);
+
+        return 0;
+}
+
+static struct platform_driver mxs_auart_driver = {
+        .probe = mxs_auart_probe,
+        .remove = __devexit_p(mxs_auart_remove),
+        .driver = {
+                .name = "mxs-auart",
+                .owner = THIS_MODULE,
+        },
+};
+
+static int __init mxs_auart_init(void)
+{
+        int r;
+
+        r = uart_register_driver(&auart_driver);
+        if (r)
+                goto out;
+
+        r = platform_driver_register(&mxs_auart_driver);
+        if (r)
+                goto out_err;
+
+        return 0;
+out_err:
+        uart_unregister_driver(&auart_driver);
+out:
+        return r;
+}
+
+static void __exit mxs_auart_exit(void)
+{
+        platform_driver_unregister(&mxs_auart_driver);
+        uart_unregister_driver(&auart_driver);
+}
+
+module_init(mxs_auart_init);
+module_exit(mxs_auart_exit);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Freescale MXS application uart driver");
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index c8e360d7d975..25c8c10bb689 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -203,11 +203,6 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
                 mdelay(10);
         }
 
-        /* setup specific usb hw */
-        ret = mxc_initialize_usb_hw(pdev->id, pdata->flags);
-        if (ret < 0)
-                goto err_init;
-
         ehci = hcd_to_ehci(hcd);
 
         /* EHCI registers start at offset 0x100 */
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index bfc62d1ee2f7..e6a8d8c0101d 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -2321,6 +2321,15 @@ config FB_JZ4740
         help
           Framebuffer support for the JZ4740 SoC.
 
+config FB_MXS
+        tristate "MXS LCD framebuffer support"
+        depends on FB && ARCH_MXS
+        select FB_CFB_FILLRECT
+        select FB_CFB_COPYAREA
+        select FB_CFB_IMAGEBLIT
+        help
+          Framebuffer support for the MXS SoC.
+
 config FB_PUV3_UNIGFX
         tristate "PKUnity v3 Unigfx framebuffer support"
         depends on FB && UNICORE32 && ARCH_PUV3
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index b0eb3da24670..2ea44b6625fe 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -154,6 +154,7 @@ obj-$(CONFIG_FB_BFIN_T350MCQB)	  += bfin-t350mcqb-fb.o
 obj-$(CONFIG_FB_BFIN_7393)        += bfin_adv7393fb.o
 obj-$(CONFIG_FB_MX3)              += mx3fb.o
 obj-$(CONFIG_FB_DA8XX)            += da8xx-fb.o
+obj-$(CONFIG_FB_MXS)              += mxsfb.o
 
 # the test framebuffer is last
 obj-$(CONFIG_FB_VIRTUAL)          += vfb.o
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
new file mode 100644
index 000000000000..7d0284882984
--- /dev/null
+++ b/drivers/video/mxsfb.c
@@ -0,0 +1,919 @@
+/*
+ * Copyright (C) 2010 Juergen Beisert, Pengutronix
+ *
+ * This code is based on:
+ * Author: Vitaly Wool <vital@embeddedalley.com>
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DRIVER_NAME "mxsfb"
+
+/**
+ * @file
+ * @brief LCDIF driver for i.MX23 and i.MX28
+ *
+ * The LCDIF support four modes of operation
+ * - MPU interface (to drive smart displays) -> not supported yet
+ * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet
+ * - Dotclock interface (to drive LC displays with RGB data and sync signals)
+ * - DVI (to drive ITU-R BT656)  -> not supported yet
+ *
+ * This driver depends on a correct setup of the pins used for this purpose
+ * (platform specific).
+ *
+ * For the developer: Don't forget to set the data bus width to the display
+ * in the imx_fb_videomode structure. You will else end up with ugly colours.
+ * If you fight against jitter you can vary the clock delay. This is a feature
+ * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give
+ * the required value in the imx_fb_videomode structure.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <mach/mxsfb.h>
+
+#define REG_SET 4
+#define REG_CLR 8
+
+#define LCDC_CTRL                       0x00
+#define LCDC_CTRL1                      0x10
+#define LCDC_V4_CTRL2                   0x20
+#define LCDC_V3_TRANSFER_COUNT          0x20
+#define LCDC_V4_TRANSFER_COUNT          0x30
+#define LCDC_V4_CUR_BUF                 0x40
+#define LCDC_V4_NEXT_BUF                0x50
+#define LCDC_V3_CUR_BUF                 0x30
+#define LCDC_V3_NEXT_BUF                0x40
+#define LCDC_TIMING                     0x60
+#define LCDC_VDCTRL0                    0x70
+#define LCDC_VDCTRL1                    0x80
+#define LCDC_VDCTRL2                    0x90
+#define LCDC_VDCTRL3                    0xa0
+#define LCDC_VDCTRL4                    0xb0
+#define LCDC_DVICTRL0                   0xc0
+#define LCDC_DVICTRL1                   0xd0
+#define LCDC_DVICTRL2                   0xe0
+#define LCDC_DVICTRL3                   0xf0
+#define LCDC_DVICTRL4                   0x100
+#define LCDC_V4_DATA                    0x180
+#define LCDC_V3_DATA                    0x1b0
+#define LCDC_V4_DEBUG0                  0x1d0
+#define LCDC_V3_DEBUG0                  0x1f0
+
+#define CTRL_SFTRST                     (1 << 31)
+#define CTRL_CLKGATE                    (1 << 30)
+#define CTRL_BYPASS_COUNT               (1 << 19)
+#define CTRL_VSYNC_MODE                 (1 << 18)
+#define CTRL_DOTCLK_MODE                (1 << 17)
+#define CTRL_DATA_SELECT                (1 << 16)
+#define CTRL_SET_BUS_WIDTH(x)           (((x) & 0x3) << 10)
+#define CTRL_GET_BUS_WIDTH(x)           (((x) >> 10) & 0x3)
+#define CTRL_SET_WORD_LENGTH(x)         (((x) & 0x3) << 8)
+#define CTRL_GET_WORD_LENGTH(x)         (((x) >> 8) & 0x3)
+#define CTRL_MASTER                     (1 << 5)
+#define CTRL_DF16                       (1 << 3)
+#define CTRL_DF18                       (1 << 2)
+#define CTRL_DF24                       (1 << 1)
+#define CTRL_RUN                        (1 << 0)
+
+#define CTRL1_FIFO_CLEAR                (1 << 21)
+#define CTRL1_SET_BYTE_PACKAGING(x)     (((x) & 0xf) << 16)
+#define CTRL1_GET_BYTE_PACKAGING(x)     (((x) >> 16) & 0xf)
+
+#define TRANSFER_COUNT_SET_VCOUNT(x)    (((x) & 0xffff) << 16)
+#define TRANSFER_COUNT_GET_VCOUNT(x)    (((x) >> 16) & 0xffff)
+#define TRANSFER_COUNT_SET_HCOUNT(x)    ((x) & 0xffff)
+#define TRANSFER_COUNT_GET_HCOUNT(x)    ((x) & 0xffff)
+
+
+#define VDCTRL0_ENABLE_PRESENT          (1 << 28)
+#define VDCTRL0_VSYNC_ACT_HIGH          (1 << 27)
+#define VDCTRL0_HSYNC_ACT_HIGH          (1 << 26)
+#define VDCTRL0_DOTCLK_ACT_FAILING      (1 << 25)
+#define VDCTRL0_ENABLE_ACT_HIGH         (1 << 24)
+#define VDCTRL0_VSYNC_PERIOD_UNIT       (1 << 21)
+#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT  (1 << 20)
+#define VDCTRL0_HALF_LINE               (1 << 19)
+#define VDCTRL0_HALF_LINE_MODE          (1 << 18)
+#define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
+#define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
+
+#define VDCTRL2_SET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
+#define VDCTRL2_GET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
+
+#define VDCTRL3_MUX_SYNC_SIGNALS        (1 << 29)
+#define VDCTRL3_VSYNC_ONLY              (1 << 28)
+#define SET_HOR_WAIT_CNT(x)             (((x) & 0xfff) << 16)
+#define GET_HOR_WAIT_CNT(x)             (((x) >> 16) & 0xfff)
+#define SET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
+#define GET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
+
+#define VDCTRL4_SET_DOTCLK_DLY(x)       (((x) & 0x7) << 29) /* v4 only */
+#define VDCTRL4_GET_DOTCLK_DLY(x)       (((x) >> 29) & 0x7) /* v4 only */
+#define VDCTRL4_SYNC_SIGNALS_ON         (1 << 18)
+#define SET_DOTCLK_H_VALID_DATA_CNT(x)  ((x) & 0x3ffff)
+
+#define DEBUG0_HSYNC                    (1 < 26)
+#define DEBUG0_VSYNC                    (1 < 25)
+
+#define MIN_XRES                        120
+#define MIN_YRES                        120
+
+#define RED 0
+#define GREEN 1
+#define BLUE 2
+#define TRANSP 3
+
+enum mxsfb_devtype {
+        MXSFB_V3,
+        MXSFB_V4,
+};
+
+/* CPU dependent register offsets */
+struct mxsfb_devdata {
+        unsigned transfer_count;
+        unsigned cur_buf;
+        unsigned next_buf;
+        unsigned debug0;
+        unsigned hs_wdth_mask;
+        unsigned hs_wdth_shift;
+        unsigned ipversion;
+};
+
+struct mxsfb_info {
+        struct fb_info fb_info;
+        struct platform_device *pdev;
+        struct clk *clk;
+        void __iomem *base;     /* registers */
+        unsigned allocated_size;
+        int enabled;
+        unsigned ld_intf_width;
+        unsigned dotclk_delay;
+        const struct mxsfb_devdata *devdata;
+        int mapped;
+};
+
+#define mxsfb_is_v3(host) (host->devdata->ipversion == 3)
+#define mxsfb_is_v4(host) (host->devdata->ipversion == 4)
+
+static const struct mxsfb_devdata mxsfb_devdata[] = {
+        [MXSFB_V3] = {
+                .transfer_count = LCDC_V3_TRANSFER_COUNT,
+                .cur_buf = LCDC_V3_CUR_BUF,
+                .next_buf = LCDC_V3_NEXT_BUF,
+                .debug0 = LCDC_V3_DEBUG0,
+                .hs_wdth_mask = 0xff,
+                .hs_wdth_shift = 24,
+                .ipversion = 3,
+        },
+        [MXSFB_V4] = {
+                .transfer_count = LCDC_V4_TRANSFER_COUNT,
+                .cur_buf = LCDC_V4_CUR_BUF,
+                .next_buf = LCDC_V4_NEXT_BUF,
+                .debug0 = LCDC_V4_DEBUG0,
+                .hs_wdth_mask = 0x3fff,
+                .hs_wdth_shift = 18,
+                .ipversion = 4,
+        },
+};
+
+#define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info))
+
+/* mask and shift depends on architecture */
+static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
+{
+        return (val & host->devdata->hs_wdth_mask) <<
+                host->devdata->hs_wdth_shift;
+}
+
+static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
+{
+        return (val >> host->devdata->hs_wdth_shift) &
+                host->devdata->hs_wdth_mask;
+}
+
+static const struct fb_bitfield def_rgb565[] = {
+        [RED] = {
+                .offset = 11,
+                .length = 5,
+        },
+        [GREEN] = {
+                .offset = 5,
+                .length = 6,
+        },
+        [BLUE] = {
+                .offset = 0,
+                .length = 5,
+        },
+        [TRANSP] = {    /* no support for transparency */
+                .length = 0,
+        }
+};
+
+static const struct fb_bitfield def_rgb666[] = {
+        [RED] = {
+                .offset = 16,
+                .length = 6,
+        },
+        [GREEN] = {
+                .offset = 8,
+                .length = 6,
+        },
+        [BLUE] = {
+                .offset = 0,
+                .length = 6,
+        },
+        [TRANSP] = {    /* no support for transparency */
+                .length = 0,
+        }
+};
+
+static const struct fb_bitfield def_rgb888[] = {
+        [RED] = {
+                .offset = 16,
+                .length = 8,
+        },
+        [GREEN] = {
+                .offset = 8,
+                .length = 8,
+        },
+        [BLUE] = {
+                .offset = 0,
+                .length = 8,
+        },
+        [TRANSP] = {    /* no support for transparency */
+                .length = 0,
+        }
+};
+
+static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf)
+{
+        chan &= 0xffff;
+        chan >>= 16 - bf->length;
+        return chan << bf->offset;
+}
+
+static int mxsfb_check_var(struct fb_var_screeninfo *var,
+                struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        const struct fb_bitfield *rgb = NULL;
+
+        if (var->xres < MIN_XRES)
+                var->xres = MIN_XRES;
+        if (var->yres < MIN_YRES)
+                var->yres = MIN_YRES;
+
+        var->xres_virtual = var->xres;
+
+        var->yres_virtual = var->yres;
+
+        switch (var->bits_per_pixel) {
+        case 16:
+                /* always expect RGB 565 */
+                rgb = def_rgb565;
+                break;
+        case 32:
+                switch (host->ld_intf_width) {
+                case STMLCDIF_8BIT:
+                        pr_debug("Unsupported LCD bus width mapping\n");
+                        break;
+                case STMLCDIF_16BIT:
+                case STMLCDIF_18BIT:
+                        /* 24 bit to 18 bit mapping */
+                        rgb = def_rgb666;
+                        break;
+                case STMLCDIF_24BIT:
+                        /* real 24 bit */
+                        rgb = def_rgb888;
+                        break;
+                }
+                break;
+        default:
+                pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel);
+                return -EINVAL;
+        }
+
+        /*
+         * Copy the RGB parameters for this display
+         * from the machine specific parameters.
+         */
+        var->red    = rgb[RED];
+        var->green  = rgb[GREEN];
+        var->blue   = rgb[BLUE];
+        var->transp = rgb[TRANSP];
+
+        return 0;
+}
+
+static void mxsfb_enable_controller(struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        u32 reg;
+
+        dev_dbg(&host->pdev->dev, "%s\n", __func__);
+
+        clk_enable(host->clk);
+        clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
+
+        /* if it was disabled, re-enable the mode again */
+        writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
+
+        /* enable the SYNC signals first, then the DMA engine */
+        reg = readl(host->base + LCDC_VDCTRL4);
+        reg |= VDCTRL4_SYNC_SIGNALS_ON;
+        writel(reg, host->base + LCDC_VDCTRL4);
+
+        writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET);
+
+        host->enabled = 1;
+}
+
+static void mxsfb_disable_controller(struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        unsigned loop;
+        u32 reg;
+
+        dev_dbg(&host->pdev->dev, "%s\n", __func__);
+
+        /*
+         * Even if we disable the controller here, it will still continue
+         * until its FIFOs are running out of data
+         */
+        writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR);
+
+        loop = 1000;
+        while (loop) {
+                reg = readl(host->base + LCDC_CTRL);
+                if (!(reg & CTRL_RUN))
+                        break;
+                loop--;
+        }
+
+        writel(VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4 + REG_CLR);
+
+        clk_disable(host->clk);
+
+        host->enabled = 0;
+}
+
+static int mxsfb_set_par(struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        u32 ctrl, vdctrl0, vdctrl4;
+        int line_size, fb_size;
+        int reenable = 0;
+
+        line_size =  fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
+        fb_size = fb_info->var.yres_virtual * line_size;
+
+        if (fb_size > fb_info->fix.smem_len)
+                return -ENOMEM;
+
+        fb_info->fix.line_length = line_size;
+
+        /*
+         * It seems, you can't re-program the controller if it is still running.
+         * This may lead into shifted pictures (FIFO issue?).
+         * So, first stop the controller and drain its FIFOs
+         */
+        if (host->enabled) {
+                reenable = 1;
+                mxsfb_disable_controller(fb_info);
+        }
+
+        /* clear the FIFOs */
+        writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
+
+        ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER |
+                CTRL_SET_BUS_WIDTH(host->ld_intf_width);;
+
+        switch (fb_info->var.bits_per_pixel) {
+        case 16:
+                dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n");
+                ctrl |= CTRL_SET_WORD_LENGTH(0);
+                writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1);
+                break;
+        case 32:
+                dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
+                ctrl |= CTRL_SET_WORD_LENGTH(3);
+                switch (host->ld_intf_width) {
+                case STMLCDIF_8BIT:
+                        dev_dbg(&host->pdev->dev,
+                                        "Unsupported LCD bus width mapping\n");
+                        return -EINVAL;
+                case STMLCDIF_16BIT:
+                case STMLCDIF_18BIT:
+                        /* 24 bit to 18 bit mapping */
+                        ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
+                                            *  each colour component
+                                            */
+                        break;
+                case STMLCDIF_24BIT:
+                        /* real 24 bit */
+                        break;
+                }
+                /* do not use packed pixels = one pixel per word instead */
+                writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1);
+                break;
+        default:
+                dev_dbg(&host->pdev->dev, "Unhandled color depth of %u\n",
+                                fb_info->var.bits_per_pixel);
+                return -EINVAL;
+        }
+
+        writel(ctrl, host->base + LCDC_CTRL);
+
+        writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) |
+                        TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres),
+                        host->base + host->devdata->transfer_count);
+
+        vdctrl0 = VDCTRL0_ENABLE_PRESENT |      /* always in DOTCLOCK mode */
+                VDCTRL0_VSYNC_PERIOD_UNIT |
+                VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
+                VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len);
+        if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT)
+                vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
+        if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT)
+                vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
+        if (fb_info->var.sync & FB_SYNC_DATA_ENABLE_HIGH_ACT)
+                vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
+        if (fb_info->var.sync & FB_SYNC_DOTCLK_FAILING_ACT)
+                vdctrl0 |= VDCTRL0_DOTCLK_ACT_FAILING;
+
+        writel(vdctrl0, host->base + LCDC_VDCTRL0);
+
+        /* frame length in lines */
+        writel(fb_info->var.upper_margin + fb_info->var.vsync_len +
+                fb_info->var.lower_margin + fb_info->var.yres,
+                host->base + LCDC_VDCTRL1);
+
+        /* line length in units of clocks or pixels */
+        writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) |
+                VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin +
+                fb_info->var.hsync_len + fb_info->var.right_margin +
+                fb_info->var.xres),
+                host->base + LCDC_VDCTRL2);
+
+        writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin +
+                fb_info->var.hsync_len) |
+                SET_VERT_WAIT_CNT(fb_info->var.upper_margin +
+                        fb_info->var.vsync_len),
+                host->base + LCDC_VDCTRL3);
+
+        vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres);
+        if (mxsfb_is_v4(host))
+                vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay);
+        writel(vdctrl4, host->base + LCDC_VDCTRL4);
+
+        writel(fb_info->fix.smem_start +
+                        fb_info->fix.line_length * fb_info->var.yoffset,
+                        host->base + host->devdata->next_buf);
+
+        if (reenable)
+                mxsfb_enable_controller(fb_info);
+
+        return 0;
+}
+
+static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+                u_int transp, struct fb_info *fb_info)
+{
+        unsigned int val;
+        int ret = -EINVAL;
+
+        /*
+         * If greyscale is true, then we convert the RGB value
+         * to greyscale no matter what visual we are using.
+         */
+        if (fb_info->var.grayscale)
+                red = green = blue = (19595 * red + 38470 * green +
+                                        7471 * blue) >> 16;
+
+        switch (fb_info->fix.visual) {
+        case FB_VISUAL_TRUECOLOR:
+                /*
+                 * 12 or 16-bit True Colour.  We encode the RGB value
+                 * according to the RGB bitfield information.
+                 */
+                if (regno < 16) {
+                        u32 *pal = fb_info->pseudo_palette;
+
+                        val  = chan_to_field(red, &fb_info->var.red);
+                        val |= chan_to_field(green, &fb_info->var.green);
+                        val |= chan_to_field(blue, &fb_info->var.blue);
+
+                        pal[regno] = val;
+                        ret = 0;
+                }
+                break;
+
+        case FB_VISUAL_STATIC_PSEUDOCOLOR:
+        case FB_VISUAL_PSEUDOCOLOR:
+                break;
+        }
+
+        return ret;
+}
+
+static int mxsfb_blank(int blank, struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+
+        switch (blank) {
+        case FB_BLANK_POWERDOWN:
+        case FB_BLANK_VSYNC_SUSPEND:
+        case FB_BLANK_HSYNC_SUSPEND:
+        case FB_BLANK_NORMAL:
+                if (host->enabled)
+                        mxsfb_disable_controller(fb_info);
+                break;
+
+        case FB_BLANK_UNBLANK:
+                if (!host->enabled)
+                        mxsfb_enable_controller(fb_info);
+                break;
+        }
+        return 0;
+}
+
+static int mxsfb_pan_display(struct fb_var_screeninfo *var,
+                struct fb_info *fb_info)
+{
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        unsigned offset;
+
+        if (var->xoffset != 0)
+                return -EINVAL;
+
+        offset = fb_info->fix.line_length * var->yoffset;
+
+        /* update on next VSYNC */
+        writel(fb_info->fix.smem_start + offset,
+                        host->base + host->devdata->next_buf);
+
+        return 0;
+}
+
+static struct fb_ops mxsfb_ops = {
+        .owner = THIS_MODULE,
+        .fb_check_var = mxsfb_check_var,
+        .fb_set_par = mxsfb_set_par,
+        .fb_setcolreg = mxsfb_setcolreg,
+        .fb_blank = mxsfb_blank,
+        .fb_pan_display = mxsfb_pan_display,
+        .fb_fillrect = cfb_fillrect,
+        .fb_copyarea = cfb_copyarea,
+        .fb_imageblit = cfb_imageblit,
+};
+
+static int __devinit mxsfb_restore_mode(struct mxsfb_info *host)
+{
+        struct fb_info *fb_info = &host->fb_info;
+        unsigned line_count;
+        unsigned period;
+        unsigned long pa, fbsize;
+        int bits_per_pixel, ofs;
+        u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
+        struct fb_videomode vmode;
+
+        /* Only restore the mode when the controller is running */
+        ctrl = readl(host->base + LCDC_CTRL);
+        if (!(ctrl & CTRL_RUN))
+                return -EINVAL;
+
+        vdctrl0 = readl(host->base + LCDC_VDCTRL0);
+        vdctrl2 = readl(host->base + LCDC_VDCTRL2);
+        vdctrl3 = readl(host->base + LCDC_VDCTRL3);
+        vdctrl4 = readl(host->base + LCDC_VDCTRL4);
+
+        transfer_count = readl(host->base + host->devdata->transfer_count);
+
+        vmode.xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count);
+        vmode.yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count);
+
+        switch (CTRL_GET_WORD_LENGTH(ctrl)) {
+        case 0:
+                bits_per_pixel = 16;
+                break;
+        case 3:
+                bits_per_pixel = 32;
+        case 1:
+        default:
+                return -EINVAL;
+        }
+
+        fb_info->var.bits_per_pixel = bits_per_pixel;
+
+        vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U);
+        vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2);
+        vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len;
+        vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len -
+                vmode.left_margin - vmode.xres;
+        vmode.vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0);
+        period = readl(host->base + LCDC_VDCTRL1);
+        vmode.upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode.vsync_len;
+        vmode.lower_margin = period - vmode.vsync_len - vmode.upper_margin - vmode.yres;
+
+        vmode.vmode = FB_VMODE_NONINTERLACED;
+
+        vmode.sync = 0;
+        if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH)
+                vmode.sync |= FB_SYNC_HOR_HIGH_ACT;
+        if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH)
+                vmode.sync |= FB_SYNC_VERT_HIGH_ACT;
+
+        pr_debug("Reconstructed video mode:\n");
+        pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n",
+                        vmode.xres, vmode.yres,
+                        vmode.hsync_len, vmode.left_margin, vmode.right_margin,
+                        vmode.vsync_len, vmode.upper_margin, vmode.lower_margin);
+        pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode.pixclock));
+
+        fb_add_videomode(&vmode, &fb_info->modelist);
+
+        host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl);
+        host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4);
+
+        fb_info->fix.line_length = vmode.xres * (bits_per_pixel >> 3);
+
+        pa = readl(host->base + host->devdata->cur_buf);
+        fbsize = fb_info->fix.line_length * vmode.yres;
+        if (pa < fb_info->fix.smem_start)
+                return -EINVAL;
+        if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len)
+                return -EINVAL;
+        ofs = pa - fb_info->fix.smem_start;
+        if (ofs) {
+                memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize);
+                writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf);
+        }
+
+        line_count = fb_info->fix.smem_len / fb_info->fix.line_length;
+        fb_info->fix.ypanstep = 1;
+
+        clk_enable(host->clk);
+        host->enabled = 1;
+
+        return 0;
+}
+
+static int __devinit mxsfb_init_fbinfo(struct mxsfb_info *host)
+{
+        struct fb_info *fb_info = &host->fb_info;
+        struct fb_var_screeninfo *var = &fb_info->var;
+        struct mxsfb_platform_data *pdata = host->pdev->dev.platform_data;
+        dma_addr_t fb_phys;
+        void *fb_virt;
+        unsigned fb_size = pdata->fb_size;
+
+        fb_info->fbops = &mxsfb_ops;
+        fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
+        strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id));
+        fb_info->fix.type = FB_TYPE_PACKED_PIXELS;
+        fb_info->fix.ypanstep = 1;
+        fb_info->fix.visual = FB_VISUAL_TRUECOLOR,
+        fb_info->fix.accel = FB_ACCEL_NONE;
+
+        var->bits_per_pixel = pdata->default_bpp ? pdata->default_bpp : 16;
+        var->nonstd = 0;
+        var->activate = FB_ACTIVATE_NOW;
+        var->accel_flags = 0;
+        var->vmode = FB_VMODE_NONINTERLACED;
+
+        host->dotclk_delay = pdata->dotclk_delay;
+        host->ld_intf_width = pdata->ld_intf_width;
+
+        /* Memory allocation for framebuffer */
+        if (pdata->fb_phys) {
+                if (!fb_size)
+                        return -EINVAL;
+
+                fb_phys = pdata->fb_phys;
+
+                if (!request_mem_region(fb_phys, fb_size, host->pdev->name))
+                        return -ENOMEM;
+
+                fb_virt = ioremap(fb_phys, fb_size);
+                if (!fb_virt) {
+                        release_mem_region(fb_phys, fb_size);
+                        return -ENOMEM;
+                }
+                host->mapped = 1;
+        } else {
+                if (!fb_size)
+                        fb_size = SZ_2M; /* default */
+                fb_virt = alloc_pages_exact(fb_size, GFP_DMA);
+                if (!fb_virt)
+                        return -ENOMEM;
+
+                fb_phys = virt_to_phys(fb_virt);
+        }
+
+        fb_info->fix.smem_start = fb_phys;
+        fb_info->screen_base = fb_virt;
+        fb_info->screen_size = fb_info->fix.smem_len = fb_size;
+
+        if (mxsfb_restore_mode(host))
+                memset(fb_virt, 0, fb_size);
+
+        return 0;
+}
+
+static void __devexit mxsfb_free_videomem(struct mxsfb_info *host)
+{
+        struct fb_info *fb_info = &host->fb_info;
+
+        if (host->mapped) {
+                iounmap(fb_info->screen_base);
+                release_mem_region(fb_info->fix.smem_start,
+                                fb_info->screen_size);
+        } else {
+                free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len);
+        }
+}
+
+static int __devinit mxsfb_probe(struct platform_device *pdev)
+{
+        struct mxsfb_platform_data *pdata = pdev->dev.platform_data;
+        struct resource *res;
+        struct mxsfb_info *host;
+        struct fb_info *fb_info;
+        struct fb_modelist *modelist;
+        int i, ret;
+
+        if (!pdata) {
+                dev_err(&pdev->dev, "No platformdata. Giving up\n");
+                return -ENODEV;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "Cannot get memory IO resource\n");
+                return -ENODEV;
+        }
+
+        if (!request_mem_region(res->start, resource_size(res), pdev->name))
+                return -EBUSY;
+
+        fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev);
+        if (!fb_info) {
+                dev_err(&pdev->dev, "Failed to allocate fbdev\n");
+                ret = -ENOMEM;
+                goto error_alloc_info;
+        }
+
+        host = to_imxfb_host(fb_info);
+
+        host->base = ioremap(res->start, resource_size(res));
+        if (!host->base) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto error_ioremap;
+        }
+
+        host->pdev = pdev;
+        platform_set_drvdata(pdev, host);
+
+        host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data];
+
+        host->clk = clk_get(&host->pdev->dev, NULL);
+        if (IS_ERR(host->clk)) {
+                ret = PTR_ERR(host->clk);
+                goto error_getclock;
+        }
+
+        fb_info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
+        if (!fb_info->pseudo_palette) {
+                ret = -ENOMEM;
+                goto error_pseudo_pallette;
+        }
+
+        INIT_LIST_HEAD(&fb_info->modelist);
+
+        ret = mxsfb_init_fbinfo(host);
+        if (ret != 0)
+                goto error_init_fb;
+
+        for (i = 0; i < pdata->mode_count; i++)
+                fb_add_videomode(&pdata->mode_list[i], &fb_info->modelist);
+
+        modelist = list_first_entry(&fb_info->modelist,
+                        struct fb_modelist, list);
+        fb_videomode_to_var(&fb_info->var, &modelist->mode);
+
+        /* init the color fields */
+        mxsfb_check_var(&fb_info->var, fb_info);
+
+        platform_set_drvdata(pdev, fb_info);
+
+        ret = register_framebuffer(fb_info);
+        if (ret != 0) {
+                dev_err(&pdev->dev,"Failed to register framebuffer\n");
+                goto error_register;
+        }
+
+        if (!host->enabled) {
+                writel(0, host->base + LCDC_CTRL);
+                mxsfb_set_par(fb_info);
+                mxsfb_enable_controller(fb_info);
+        }
+
+        dev_info(&pdev->dev, "initialized\n");
+
+        return 0;
+
+error_register:
+        if (host->enabled)
+                clk_disable(host->clk);
+        fb_destroy_modelist(&fb_info->modelist);
+error_init_fb:
+        kfree(fb_info->pseudo_palette);
+error_pseudo_pallette:
+        clk_put(host->clk);
+error_getclock:
+        iounmap(host->base);
+error_ioremap:
+        framebuffer_release(fb_info);
+error_alloc_info:
+        release_mem_region(res->start, resource_size(res));
+
+        return ret;
+}
+
+static int __devexit mxsfb_remove(struct platform_device *pdev)
+{
+        struct fb_info *fb_info = platform_get_drvdata(pdev);
+        struct mxsfb_info *host = to_imxfb_host(fb_info);
+        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+        if (host->enabled)
+                mxsfb_disable_controller(fb_info);
+
+        unregister_framebuffer(fb_info);
+        kfree(fb_info->pseudo_palette);
+        mxsfb_free_videomem(host);
+        iounmap(host->base);
+        clk_put(host->clk);
+
+        framebuffer_release(fb_info);
+        release_mem_region(res->start, resource_size(res));
+
+        platform_set_drvdata(pdev, NULL);
+
+        return 0;
+}
+
+static struct platform_device_id mxsfb_devtype[] = {
+        {
+                .name = "imx23-fb",
+                .driver_data = MXSFB_V3,
+        }, {
+                .name = "imx28-fb",
+                .driver_data = MXSFB_V4,
+        }, {
+                /* sentinel */
+        }
+};
+MODULE_DEVICE_TABLE(platform, mxsfb_devtype);
+
+static struct platform_driver mxsfb_driver = {
+        .probe = mxsfb_probe,
+        .remove = __devexit_p(mxsfb_remove),
+        .id_table = mxsfb_devtype,
+        .driver = {
+                   .name = DRIVER_NAME,
+        },
+};
+
+static int __init mxsfb_init(void)
+{
+        return platform_driver_register(&mxsfb_driver);
+}
+
+static void __exit mxsfb_exit(void)
+{
+        platform_driver_unregister(&mxsfb_driver);
+}
+
+module_init(mxsfb_init);
+module_exit(mxsfb_exit);
+
+MODULE_DESCRIPTION("Freescale mxs framebuffer driver");
+MODULE_AUTHOR("Sascha Hauer, Pengutronix");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/mfd/ti_ssp.h b/include/linux/mfd/ti_ssp.h
new file mode 100644
index 000000000000..dbb4b43bd20e
--- /dev/null
+++ b/include/linux/mfd/ti_ssp.h
@@ -0,0 +1,93 @@
+/*
+ * Sequencer Serial Port (SSP) driver for Texas Instruments' SoCs
+ *
+ * Copyright (C) 2010 Texas Instruments Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __TI_SSP_H__
+#define __TI_SSP_H__
+
+struct ti_ssp_dev_data {
+        const char      *dev_name;
+        void            *pdata;
+        size_t          pdata_size;
+};
+
+struct ti_ssp_data {
+        unsigned long           out_clock;
+        struct ti_ssp_dev_data  dev_data[2];
+};
+
+struct ti_ssp_spi_data {
+        unsigned long   iosel;
+        int             num_cs;
+        void            (*select)(int cs);
+};
+
+/*
+ * Sequencer port IO pin configuration bits.  These do not correlate 1-1 with
+ * the hardware.  The iosel field in the port data combines iosel1 and iosel2,
+ * and is therefore not a direct map to register space.  It is best to use the
+ * macros below to construct iosel values.
+ *
+ * least significant 16 bits --> iosel1
+ * most significant 16 bits  --> iosel2
+ */
+
+#define SSP_IN                  0x0000
+#define SSP_DATA                0x0001
+#define SSP_CLOCK               0x0002
+#define SSP_CHIPSEL             0x0003
+#define SSP_OUT                 0x0004
+#define SSP_PIN_SEL(pin, v)     ((v) << ((pin) * 3))
+#define SSP_PIN_MASK(pin)       SSP_PIN_SEL(pin, 0x7)
+#define SSP_INPUT_SEL(pin)      ((pin) << 16)
+
+/* Sequencer port config bits */
+#define SSP_EARLY_DIN           BIT(8)
+#define SSP_DELAY_DOUT          BIT(9)
+
+/* Sequence map definitions */
+#define SSP_CLK_HIGH            BIT(0)
+#define SSP_CLK_LOW             0
+#define SSP_DATA_HIGH           BIT(1)
+#define SSP_DATA_LOW            0
+#define SSP_CS_HIGH             BIT(2)
+#define SSP_CS_LOW              0
+#define SSP_OUT_MODE            BIT(3)
+#define SSP_IN_MODE             0
+#define SSP_DATA_REG            BIT(4)
+#define SSP_ADDR_REG            0
+
+#define SSP_OPCODE_DIRECT       ((0x0) << 5)
+#define SSP_OPCODE_TOGGLE       ((0x1) << 5)
+#define SSP_OPCODE_SHIFT        ((0x2) << 5)
+#define SSP_OPCODE_BRANCH0      ((0x4) << 5)
+#define SSP_OPCODE_BRANCH1      ((0x5) << 5)
+#define SSP_OPCODE_BRANCH       ((0x6) << 5)
+#define SSP_OPCODE_STOP         ((0x7) << 5)
+#define SSP_BRANCH(addr)        ((addr) << 8)
+#define SSP_COUNT(cycles)       ((cycles) << 8)
+
+int ti_ssp_raw_read(struct device *dev);
+int ti_ssp_raw_write(struct device *dev, u32 val);
+int ti_ssp_load(struct device *dev, int offs, u32* prog, int len);
+int ti_ssp_run(struct device *dev, u32 pc, u32 input, u32 *output);
+int ti_ssp_set_mode(struct device *dev, int mode);
+int ti_ssp_set_iosel(struct device *dev, u32 iosel);
+
+#endif /* __TI_SSP_H__ */
diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
index 642270a635ea..9eeb8f0d67e9 100644
--- a/sound/soc/imx/Kconfig
+++ b/sound/soc/imx/Kconfig
@@ -44,7 +44,8 @@ config SND_SOC_EUKREA_TLV320
         tristate "Eukrea TLV320"
         depends on MACH_EUKREA_MBIMX27_BASEBOARD \
                 || MACH_EUKREA_MBIMXSD25_BASEBOARD \
-                || MACH_EUKREA_MBIMXSD35_BASEBOARD
+                || MACH_EUKREA_MBIMXSD35_BASEBOARD \
+                || MACH_EUKREA_MBIMXSD51_BASEBOARD
         select SND_SOC_TLV320AIC23
         select SND_MXC_SOC_SSI
         select SND_MXC_SOC_FIQ
diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/imx/eukrea-tlv320.c
index 1e9bccae4e80..75fb4b83548b 100644
--- a/sound/soc/imx/eukrea-tlv320.c
+++ b/sound/soc/imx/eukrea-tlv320.c
@@ -98,7 +98,8 @@ static int __init eukrea_tlv320_init(void)
         int ret;
 
         if (!machine_is_eukrea_cpuimx27() && !machine_is_eukrea_cpuimx25sd()
-                && !machine_is_eukrea_cpuimx35sd())
+                && !machine_is_eukrea_cpuimx35sd()
+                && !machine_is_eukrea_cpuimx51sd())
                 /* return happy. We might run on a totally different machine */
                 return 0;
 
diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index a6a6b5fa2f2f..d6713d5a90e7 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -1,6 +1,6 @@
 config SND_SOC_SAMSUNG
         tristate "ASoC support for Samsung"
-        depends on ARCH_S3C2410 || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PV310
+        depends on ARCH_S3C2410 || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_EXYNOS4
         select S3C64XX_DMA if ARCH_S3C64XX
         select S3C2410_DMA if ARCH_S3C2410
         help