diff options
-rw-r--r-- | drivers/media/common/tuners/mxl5005s.c | 5527 | ||||
-rw-r--r-- | drivers/media/common/tuners/mxl5005s.h | 165 |
2 files changed, 2677 insertions, 3015 deletions
diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 2af14de737e9..d8885484cfbd 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c | |||
@@ -24,164 +24,61 @@ | |||
24 | 24 | ||
25 | #include "mxl5005s.h" | 25 | #include "mxl5005s.h" |
26 | 26 | ||
27 | 27 | /* MXL5005 Tuner Control Struct */ | |
28 | void BuildMxl5005sModule( | 28 | typedef struct _TunerControl_struct { |
29 | TUNER_MODULE **ppTuner, | 29 | u16 Ctrl_Num; /* Control Number */ |
30 | TUNER_MODULE *pTunerModuleMemory, | 30 | u16 size; /* Number of bits to represent Value */ |
31 | MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory, | 31 | u16 addr[25]; /* Array of Tuner Register Address for each bit position */ |
32 | BASE_INTERFACE_MODULE *pBaseInterfaceModuleMemory, | 32 | u16 bit[25]; /* Array of bit position in Register Address for each bit position */ |
33 | I2C_BRIDGE_MODULE *pI2cBridgeModuleMemory, | 33 | u16 val[25]; /* Binary representation of Value */ |
34 | unsigned char DeviceAddr, | 34 | } TunerControl_struct; |
35 | int StandardMode | 35 | |
36 | ) | 36 | /* MXL5005 Tuner Struct */ |
37 | { | 37 | struct mxl5005s_state |
38 | MXL5005S_EXTRA_MODULE *pExtra; | ||
39 | |||
40 | int MxlModMode; | ||
41 | int MxlIfMode; | ||
42 | unsigned long MxlBandwitdh; | ||
43 | unsigned long MxlIfFreqHz; | ||
44 | unsigned long MxlCrystalFreqHz; | ||
45 | int MxlAgcMode; | ||
46 | unsigned short MxlTop; | ||
47 | unsigned short MxlIfOutputLoad; | ||
48 | int MxlClockOut; | ||
49 | int MxlDivOut; | ||
50 | int MxlCapSel; | ||
51 | int MxlRssiOnOff; | ||
52 | unsigned char MxlStandard; | ||
53 | unsigned char MxlTfType; | ||
54 | |||
55 | |||
56 | |||
57 | // Set tuner module pointer, tuner extra module pointer, and I2C bridge module pointer. | ||
58 | *ppTuner = pTunerModuleMemory; | ||
59 | (*ppTuner)->pExtra = pMxl5005sExtraModuleMemory; | ||
60 | (*ppTuner)->pBaseInterface = pBaseInterfaceModuleMemory; | ||
61 | (*ppTuner)->pI2cBridge = pI2cBridgeModuleMemory; | ||
62 | |||
63 | // Get tuner extra module pointer. | ||
64 | pExtra = (MXL5005S_EXTRA_MODULE *)(*ppTuner)->pExtra; | ||
65 | |||
66 | |||
67 | // Set I2C bridge tuner arguments. | ||
68 | mxl5005s_SetI2cBridgeModuleTunerArg(*ppTuner); | ||
69 | |||
70 | |||
71 | // Set tuner module manipulating function pointers. | ||
72 | (*ppTuner)->SetDeviceAddr = mxl5005s_SetDeviceAddr; | ||
73 | |||
74 | (*ppTuner)->GetTunerType = mxl5005s_GetTunerType; | ||
75 | (*ppTuner)->GetDeviceAddr = mxl5005s_GetDeviceAddr; | ||
76 | |||
77 | (*ppTuner)->Initialize = mxl5005s_Initialize; | ||
78 | (*ppTuner)->SetRfFreqHz = mxl5005s_SetRfFreqHz; | ||
79 | (*ppTuner)->GetRfFreqHz = mxl5005s_GetRfFreqHz; | ||
80 | |||
81 | |||
82 | // Set tuner extra module manipulating function pointers. | ||
83 | pExtra->SetRegsWithTable = mxl5005s_SetRegsWithTable; | ||
84 | pExtra->SetRegMaskBits = mxl5005s_SetRegMaskBits; | ||
85 | pExtra->SetSpectrumMode = mxl5005s_SetSpectrumMode; | ||
86 | pExtra->SetBandwidthHz = mxl5005s_SetBandwidthHz; | ||
87 | |||
88 | |||
89 | // Initialize tuner parameter setting status. | ||
90 | (*ppTuner)->IsDeviceAddrSet = NO; | ||
91 | (*ppTuner)->IsRfFreqHzSet = NO; | ||
92 | |||
93 | |||
94 | // Set MxL5005S parameters. | ||
95 | MxlModMode = MXL_DIGITAL_MODE; | ||
96 | MxlIfMode = MXL_ZERO_IF; | ||
97 | MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; | ||
98 | MxlIfFreqHz = IF_FREQ_4570000HZ; | ||
99 | MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; | ||
100 | MxlAgcMode = MXL_SINGLE_AGC; | ||
101 | MxlTop = MXL5005S_TOP_25P2; | ||
102 | MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; | ||
103 | MxlClockOut = MXL_CLOCK_OUT_DISABLE; | ||
104 | MxlDivOut = MXL_DIV_OUT_4; | ||
105 | MxlCapSel = MXL_CAP_SEL_ENABLE; | ||
106 | MxlRssiOnOff = MXL_RSSI_ENABLE; | ||
107 | MxlTfType = MXL_TF_C_H; | ||
108 | |||
109 | |||
110 | // Set MxL5005S parameters according to standard mode | ||
111 | switch(StandardMode) | ||
112 | { | ||
113 | default: | ||
114 | case MXL5005S_STANDARD_DVBT: MxlStandard = MXL_DVBT; break; | ||
115 | case MXL5005S_STANDARD_ATSC: MxlStandard = MXL_ATSC; break; | ||
116 | } | ||
117 | |||
118 | |||
119 | // Set MxL5005S extra module. | ||
120 | pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; | ||
121 | |||
122 | MXL5005_TunerConfig(&pExtra->MxlDefinedTunerStructure, (unsigned char)MxlModMode, (unsigned char)MxlIfMode, | ||
123 | MxlBandwitdh, MxlIfFreqHz, MxlCrystalFreqHz, (unsigned char)MxlAgcMode, MxlTop, MxlIfOutputLoad, | ||
124 | (unsigned char)MxlClockOut, (unsigned char)MxlDivOut, (unsigned char)MxlCapSel, (unsigned char)MxlRssiOnOff, | ||
125 | MxlStandard, MxlTfType); | ||
126 | |||
127 | |||
128 | |||
129 | // Note: Need to set all module arguments before using module functions. | ||
130 | |||
131 | |||
132 | // Set tuner type. | ||
133 | (*ppTuner)->TunerType = TUNER_TYPE_MXL5005S; | ||
134 | |||
135 | // Set tuner I2C device address. | ||
136 | (*ppTuner)->SetDeviceAddr(*ppTuner, DeviceAddr); | ||
137 | |||
138 | |||
139 | return; | ||
140 | } | ||
141 | |||
142 | void mxl5005s_SetDeviceAddr( | ||
143 | TUNER_MODULE *pTuner, | ||
144 | unsigned char DeviceAddr | ||
145 | ) | ||
146 | { | ||
147 | // Set tuner I2C device address. | ||
148 | pTuner->DeviceAddr = DeviceAddr; | ||
149 | pTuner->IsDeviceAddrSet = YES; | ||
150 | |||
151 | |||
152 | return; | ||
153 | } | ||
154 | |||
155 | void mxl5005s_GetTunerType( | ||
156 | TUNER_MODULE *pTuner, | ||
157 | int *pTunerType | ||
158 | ) | ||
159 | { | ||
160 | // Get tuner type from tuner module. | ||
161 | *pTunerType = pTuner->TunerType; | ||
162 | |||
163 | |||
164 | return; | ||
165 | } | ||
166 | |||
167 | int mxl5005s_GetDeviceAddr( | ||
168 | TUNER_MODULE *pTuner, | ||
169 | unsigned char *pDeviceAddr | ||
170 | ) | ||
171 | { | 38 | { |
172 | // Get tuner I2C device address from tuner module. | 39 | u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ |
173 | if(pTuner->IsDeviceAddrSet != YES) | 40 | u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */ |
174 | goto error_status_get_tuner_i2c_device_addr; | 41 | u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */ |
175 | 42 | u32 IF_OUT; /* Desired IF Out Frequency */ | |
176 | *pDeviceAddr = pTuner->DeviceAddr; | 43 | u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */ |
177 | 44 | u32 RF_IN; /* RF Input Frequency */ | |
178 | 45 | u32 Fxtal; /* XTAL Frequency */ | |
179 | return FUNCTION_SUCCESS; | 46 | u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */ |
47 | u16 TOP; /* Value: take over point */ | ||
48 | u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */ | ||
49 | u8 DIV_OUT; /* 4MHz or 16MHz */ | ||
50 | u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */ | ||
51 | u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */ | ||
52 | u8 Mod_Type; /* Modulation Type; */ | ||
53 | /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ | ||
54 | u8 TF_Type; /* Tracking Filter Type */ | ||
55 | /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ | ||
56 | |||
57 | /* Calculated Settings */ | ||
58 | u32 RF_LO; /* Synth RF LO Frequency */ | ||
59 | u32 IF_LO; /* Synth IF LO Frequency */ | ||
60 | u32 TG_LO; /* Synth TG_LO Frequency */ | ||
61 | |||
62 | /* Pointers to ControlName Arrays */ | ||
63 | u16 Init_Ctrl_Num; /* Number of INIT Control Names */ | ||
64 | TunerControl_struct | ||
65 | Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ | ||
66 | |||
67 | u16 CH_Ctrl_Num; /* Number of CH Control Names */ | ||
68 | TunerControl_struct | ||
69 | CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ | ||
70 | |||
71 | u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ | ||
72 | TunerControl_struct | ||
73 | MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ | ||
74 | |||
75 | /* Pointer to Tuner Register Array */ | ||
76 | u16 TunerRegs_Num; /* Number of Tuner Registers */ | ||
77 | TunerReg_struct | ||
78 | TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ | ||
180 | 79 | ||
80 | }; | ||
181 | 81 | ||
182 | error_status_get_tuner_i2c_device_addr: | ||
183 | return FUNCTION_ERROR; | ||
184 | } | ||
185 | 82 | ||
186 | int mxl5005s_Initialize( | 83 | int mxl5005s_Initialize( |
187 | struct dvb_usb_device* dib, | 84 | struct dvb_usb_device* dib, |
@@ -310,24 +207,19 @@ error_status_set_tuner_registers: | |||
310 | return FUNCTION_ERROR; | 207 | return FUNCTION_ERROR; |
311 | } | 208 | } |
312 | 209 | ||
313 | int mxl5005s_GetRfFreqHz( | 210 | // DONE |
314 | struct dvb_usb_device* dib, | 211 | int mxl5005s_GetRfFreqHz(struct dvb_frontend *fe, unsigned long *pRfFreqHz) |
315 | TUNER_MODULE *pTuner, | ||
316 | unsigned long *pRfFreqHz | ||
317 | ) | ||
318 | { | 212 | { |
319 | // Get tuner RF frequency in Hz from tuner module. | 213 | struct mxl5005s_state *state = fe->demodulator_priv; |
320 | if(pTuner->IsRfFreqHzSet != YES) | 214 | int ret = -1; |
321 | goto error_status_get_tuner_rf_frequency; | ||
322 | |||
323 | *pRfFreqHz = pTuner->RfFreqHz; | ||
324 | |||
325 | |||
326 | return FUNCTION_SUCCESS; | ||
327 | 215 | ||
216 | /* Get tuner RF frequency in Hz from tuner module. */ | ||
217 | if(state->IsRfFreqHzSet == YES) { | ||
218 | *pRfFreqHz = state->RfFreqHz; | ||
219 | ret = 0; | ||
220 | } | ||
328 | 221 | ||
329 | error_status_get_tuner_rf_frequency: | 222 | return -1; |
330 | return FUNCTION_ERROR; | ||
331 | } | 223 | } |
332 | 224 | ||
333 | int mxl5005s_SetRegsWithTable( | 225 | int mxl5005s_SetRegsWithTable( |
@@ -394,14 +286,13 @@ error_status_set_tuner_registers: | |||
394 | return FUNCTION_ERROR; | 286 | return FUNCTION_ERROR; |
395 | } | 287 | } |
396 | 288 | ||
397 | int mxl5005s_SetRegsWithTable( | 289 | int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, |
398 | struct dvb_usb_device* dib, | ||
399 | TUNER_MODULE *pTuner, | ||
400 | unsigned char *pAddrTable, | 290 | unsigned char *pAddrTable, |
401 | unsigned char *pByteTable, | 291 | unsigned char *pByteTable, |
402 | int TableLen | 292 | int TableLen |
403 | ) | 293 | ) |
404 | { | 294 | { |
295 | struct mxl5005s_state *state = fe->demodulator_priv; | ||
405 | int i; | 296 | int i; |
406 | u8 end_two_bytes_buf[]={ 0 , 0 }; | 297 | u8 end_two_bytes_buf[]={ 0 , 0 }; |
407 | u8 tuner_addr=0x00; | 298 | u8 tuner_addr=0x00; |
@@ -423,31 +314,21 @@ int mxl5005s_SetRegsWithTable( | |||
423 | return FUNCTION_SUCCESS; | 314 | return FUNCTION_SUCCESS; |
424 | } | 315 | } |
425 | 316 | ||
426 | int mxl5005s_SetRegMaskBits( | 317 | int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, |
427 | struct dvb_usb_device* dib, | ||
428 | TUNER_MODULE *pTuner, | ||
429 | unsigned char RegAddr, | 318 | unsigned char RegAddr, |
430 | unsigned char Msb, | 319 | unsigned char Msb, |
431 | unsigned char Lsb, | 320 | unsigned char Lsb, |
432 | const unsigned char WritingValue | 321 | const unsigned char WritingValue |
433 | ) | 322 | ) |
434 | { | 323 | { |
435 | MXL5005S_EXTRA_MODULE *pExtra; | 324 | struct mxl5005s_state *state = fe->demodulator_priv; |
436 | |||
437 | int i; | 325 | int i; |
438 | 326 | ||
439 | unsigned char Mask; | 327 | unsigned char Mask; |
440 | unsigned char Shift; | 328 | unsigned char Shift; |
441 | |||
442 | unsigned char RegByte; | 329 | unsigned char RegByte; |
443 | 330 | ||
444 | 331 | /* Generate mask and shift according to MSB and LSB. */ | |
445 | |||
446 | // Get tuner extra module. | ||
447 | pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; | ||
448 | |||
449 | |||
450 | // Generate mask and shift according to MSB and LSB. | ||
451 | Mask = 0; | 332 | Mask = 0; |
452 | for(i = Lsb; i < (unsigned char)(Msb + 1); i++) | 333 | for(i = Lsb; i < (unsigned char)(Msb + 1); i++) |
453 | Mask |= 0x1 << i; | 334 | Mask |= 0x1 << i; |
@@ -455,20 +336,17 @@ int mxl5005s_SetRegMaskBits( | |||
455 | Shift = Lsb; | 336 | Shift = Lsb; |
456 | 337 | ||
457 | 338 | ||
458 | // Get tuner register byte according to register adddress. | 339 | /* Get tuner register byte according to register adddress. */ |
459 | MXL_RegRead(&pExtra->MxlDefinedTunerStructure, RegAddr, &RegByte); | 340 | MXL_RegRead(&pExtra->MxlDefinedTunerStructure, RegAddr, &RegByte); |
460 | 341 | ||
461 | 342 | /* Reserve register byte unmask bit with mask and inlay writing value into it. */ | |
462 | // Reserve register byte unmask bit with mask and inlay writing value into it. | ||
463 | RegByte &= ~Mask; | 343 | RegByte &= ~Mask; |
464 | RegByte |= (WritingValue << Shift) & Mask; | 344 | RegByte |= (WritingValue << Shift) & Mask; |
465 | 345 | ||
466 | 346 | /* Update tuner register byte table. */ | |
467 | // Update tuner register byte table. | ||
468 | MXL_RegWrite(&pExtra->MxlDefinedTunerStructure, RegAddr, RegByte); | 347 | MXL_RegWrite(&pExtra->MxlDefinedTunerStructure, RegAddr, RegByte); |
469 | 348 | ||
470 | 349 | /* Write tuner register byte with writing byte. */ | |
471 | // Write tuner register byte with writing byte. | ||
472 | if(pExtra->SetRegsWithTable( dib, pTuner, &RegAddr, &RegByte, LEN_1_BYTE) != FUNCTION_SUCCESS) | 350 | if(pExtra->SetRegsWithTable( dib, pTuner, &RegAddr, &RegByte, LEN_1_BYTE) != FUNCTION_SUCCESS) |
473 | goto error_status_set_tuner_registers; | 351 | goto error_status_set_tuner_registers; |
474 | 352 | ||
@@ -480,1350 +358,1321 @@ error_status_set_tuner_registers: | |||
480 | return FUNCTION_ERROR; | 358 | return FUNCTION_ERROR; |
481 | } | 359 | } |
482 | 360 | ||
483 | int mxl5005s_SetSpectrumMode( | 361 | // DONE |
484 | struct dvb_usb_device* dib, | 362 | int mxl5005s_SetSpectrumMode(struct dvb_frontend *fe, int SpectrumMode) |
485 | TUNER_MODULE *pTuner, | ||
486 | int SpectrumMode | ||
487 | ) | ||
488 | { | 363 | { |
364 | struct mxl5005s_state *state = fe->demodulator_priv; | ||
489 | static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] = | 365 | static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] = |
490 | { | 366 | { |
491 | // BB_IQSWAP | 367 | /* BB_IQSWAP */ |
492 | 0, // Normal spectrum | 368 | 0, /* Normal spectrum */ |
493 | 1, // Inverse spectrum | 369 | 1, /* Inverse spectrum */ |
494 | }; | 370 | }; |
495 | 371 | ||
496 | 372 | /* Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. */ | |
497 | MXL5005S_EXTRA_MODULE *pExtra; | 373 | mxl5005s_SetRegMaskBits(fe, |
498 | 374 | MXL5005S_BB_IQSWAP_ADDR, | |
499 | 375 | MXL5005S_BB_IQSWAP_MSB, | |
500 | 376 | MXL5005S_BB_IQSWAP_LSB, | |
501 | // Get tuner extra module. | 377 | BbIqswapTable[SpectrumMode]); |
502 | pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; | ||
503 | |||
504 | |||
505 | // Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. | ||
506 | if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_IQSWAP_ADDR, MXL5005S_BB_IQSWAP_MSB, | ||
507 | MXL5005S_BB_IQSWAP_LSB, BbIqswapTable[SpectrumMode]) != FUNCTION_SUCCESS) | ||
508 | goto error_status_set_tuner_registers; | ||
509 | |||
510 | 378 | ||
511 | return FUNCTION_SUCCESS; | 379 | return FUNCTION_SUCCESS; |
512 | |||
513 | |||
514 | error_status_set_tuner_registers: | ||
515 | return FUNCTION_ERROR; | ||
516 | } | 380 | } |
517 | 381 | ||
518 | int mxl5005s_SetBandwidthHz( | 382 | // DONE |
519 | struct dvb_usb_device* dib, | 383 | int mxl5005s_SetBandwidthHz(struct dvb_frontend *fe, unsigned long BandwidthHz) |
520 | TUNER_MODULE *pTuner, | ||
521 | unsigned long BandwidthHz | ||
522 | ) | ||
523 | { | 384 | { |
524 | MXL5005S_EXTRA_MODULE *pExtra; | 385 | struct mxl5005s_state *state = fe->demodulator_priv; |
525 | 386 | ||
526 | unsigned char BbDlpfBandsel; | 387 | unsigned char BbDlpfBandsel; |
527 | 388 | ||
528 | 389 | /* Set BB_DLPF_BANDSEL according to bandwidth. */ | |
529 | |||
530 | // Get tuner extra module. | ||
531 | pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; | ||
532 | |||
533 | |||
534 | // Set BB_DLPF_BANDSEL according to bandwidth. | ||
535 | switch(BandwidthHz) | 390 | switch(BandwidthHz) |
536 | { | 391 | { |
537 | default: | 392 | default: |
538 | case MXL5005S_BANDWIDTH_6MHZ: BbDlpfBandsel = 3; break; | 393 | case MXL5005S_BANDWIDTH_6MHZ: |
539 | case MXL5005S_BANDWIDTH_7MHZ: BbDlpfBandsel = 2; break; | 394 | BbDlpfBandsel = 3; |
540 | case MXL5005S_BANDWIDTH_8MHZ: BbDlpfBandsel = 0; break; | 395 | break; |
396 | case MXL5005S_BANDWIDTH_7MHZ: | ||
397 | BbDlpfBandsel = 2; | ||
398 | break; | ||
399 | case MXL5005S_BANDWIDTH_8MHZ: | ||
400 | BbDlpfBandsel = 0; | ||
401 | break; | ||
541 | } | 402 | } |
542 | 403 | ||
543 | if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_DLPF_BANDSEL_ADDR, MXL5005S_BB_DLPF_BANDSEL_MSB, | 404 | if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_DLPF_BANDSEL_ADDR, MXL5005S_BB_DLPF_BANDSEL_MSB, |
544 | MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != FUNCTION_SUCCESS) | 405 | MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != 0) |
545 | goto error_status_set_tuner_registers; | 406 | goto error_status_set_tuner_registers; |
546 | 407 | ||
547 | 408 | ||
548 | return FUNCTION_SUCCESS; | 409 | return 0; |
549 | 410 | ||
550 | 411 | ||
551 | error_status_set_tuner_registers: | 412 | error_status_set_tuner_registers: |
552 | return FUNCTION_ERROR; | 413 | return -1; |
553 | } | ||
554 | |||
555 | void mxl5005s_SetI2cBridgeModuleTunerArg(TUNER_MODULE *pTuner) | ||
556 | { | ||
557 | I2C_BRIDGE_MODULE *pI2cBridge; | ||
558 | |||
559 | |||
560 | |||
561 | // Get I2C bridge module. | ||
562 | pI2cBridge = pTuner->pI2cBridge; | ||
563 | |||
564 | // Set I2C bridge module tuner arguments. | ||
565 | pI2cBridge->pTunerDeviceAddr = &pTuner->DeviceAddr; | ||
566 | |||
567 | |||
568 | return; | ||
569 | } | 414 | } |
570 | 415 | ||
571 | // The following context is source code provided by MaxLinear. | 416 | // The following context is source code provided by MaxLinear. |
572 | // MaxLinear source code - MXL5005_Initialize.cpp | 417 | // MaxLinear source code - MXL5005_Initialize.cpp |
573 | u16 MXL5005_RegisterInit(Tuner_struct *Tuner) | 418 | // DONE |
419 | u16 MXL5005_RegisterInit(struct dvb_frontend *fe) | ||
574 | { | 420 | { |
575 | Tuner->TunerRegs_Num = TUNER_REGS_NUM ; | 421 | struct mxl5005s_state *state = fe->demodulator_priv; |
576 | // Tuner->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; | 422 | state->TunerRegs_Num = TUNER_REGS_NUM ; |
423 | // state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; | ||
577 | 424 | ||
578 | Tuner->TunerRegs[0].Reg_Num = 9 ; | 425 | state->TunerRegs[0].Reg_Num = 9 ; |
579 | Tuner->TunerRegs[0].Reg_Val = 0x40 ; | 426 | state->TunerRegs[0].Reg_Val = 0x40 ; |
580 | 427 | ||
581 | Tuner->TunerRegs[1].Reg_Num = 11 ; | 428 | state->TunerRegs[1].Reg_Num = 11 ; |
582 | Tuner->TunerRegs[1].Reg_Val = 0x19 ; | 429 | state->TunerRegs[1].Reg_Val = 0x19 ; |
583 | 430 | ||
584 | Tuner->TunerRegs[2].Reg_Num = 12 ; | 431 | state->TunerRegs[2].Reg_Num = 12 ; |
585 | Tuner->TunerRegs[2].Reg_Val = 0x60 ; | 432 | state->TunerRegs[2].Reg_Val = 0x60 ; |
586 | 433 | ||
587 | Tuner->TunerRegs[3].Reg_Num = 13 ; | 434 | state->TunerRegs[3].Reg_Num = 13 ; |
588 | Tuner->TunerRegs[3].Reg_Val = 0x00 ; | 435 | state->TunerRegs[3].Reg_Val = 0x00 ; |
589 | 436 | ||
590 | Tuner->TunerRegs[4].Reg_Num = 14 ; | 437 | state->TunerRegs[4].Reg_Num = 14 ; |
591 | Tuner->TunerRegs[4].Reg_Val = 0x00 ; | 438 | state->TunerRegs[4].Reg_Val = 0x00 ; |
592 | 439 | ||
593 | Tuner->TunerRegs[5].Reg_Num = 15 ; | 440 | state->TunerRegs[5].Reg_Num = 15 ; |
594 | Tuner->TunerRegs[5].Reg_Val = 0xC0 ; | 441 | state->TunerRegs[5].Reg_Val = 0xC0 ; |
595 | 442 | ||
596 | Tuner->TunerRegs[6].Reg_Num = 16 ; | 443 | state->TunerRegs[6].Reg_Num = 16 ; |
597 | Tuner->TunerRegs[6].Reg_Val = 0x00 ; | 444 | state->TunerRegs[6].Reg_Val = 0x00 ; |
598 | 445 | ||
599 | Tuner->TunerRegs[7].Reg_Num = 17 ; | 446 | state->TunerRegs[7].Reg_Num = 17 ; |
600 | Tuner->TunerRegs[7].Reg_Val = 0x00 ; | 447 | state->TunerRegs[7].Reg_Val = 0x00 ; |
601 | 448 | ||
602 | Tuner->TunerRegs[8].Reg_Num = 18 ; | 449 | state->TunerRegs[8].Reg_Num = 18 ; |
603 | Tuner->TunerRegs[8].Reg_Val = 0x00 ; | 450 | state->TunerRegs[8].Reg_Val = 0x00 ; |
604 | 451 | ||
605 | Tuner->TunerRegs[9].Reg_Num = 19 ; | 452 | state->TunerRegs[9].Reg_Num = 19 ; |
606 | Tuner->TunerRegs[9].Reg_Val = 0x34 ; | 453 | state->TunerRegs[9].Reg_Val = 0x34 ; |
607 | 454 | ||
608 | Tuner->TunerRegs[10].Reg_Num = 21 ; | 455 | state->TunerRegs[10].Reg_Num = 21 ; |
609 | Tuner->TunerRegs[10].Reg_Val = 0x00 ; | 456 | state->TunerRegs[10].Reg_Val = 0x00 ; |
610 | 457 | ||
611 | Tuner->TunerRegs[11].Reg_Num = 22 ; | 458 | state->TunerRegs[11].Reg_Num = 22 ; |
612 | Tuner->TunerRegs[11].Reg_Val = 0x6B ; | 459 | state->TunerRegs[11].Reg_Val = 0x6B ; |
613 | 460 | ||
614 | Tuner->TunerRegs[12].Reg_Num = 23 ; | 461 | state->TunerRegs[12].Reg_Num = 23 ; |
615 | Tuner->TunerRegs[12].Reg_Val = 0x35 ; | 462 | state->TunerRegs[12].Reg_Val = 0x35 ; |
616 | 463 | ||
617 | Tuner->TunerRegs[13].Reg_Num = 24 ; | 464 | state->TunerRegs[13].Reg_Num = 24 ; |
618 | Tuner->TunerRegs[13].Reg_Val = 0x70 ; | 465 | state->TunerRegs[13].Reg_Val = 0x70 ; |
619 | 466 | ||
620 | Tuner->TunerRegs[14].Reg_Num = 25 ; | 467 | state->TunerRegs[14].Reg_Num = 25 ; |
621 | Tuner->TunerRegs[14].Reg_Val = 0x3E ; | 468 | state->TunerRegs[14].Reg_Val = 0x3E ; |
622 | 469 | ||
623 | Tuner->TunerRegs[15].Reg_Num = 26 ; | 470 | state->TunerRegs[15].Reg_Num = 26 ; |
624 | Tuner->TunerRegs[15].Reg_Val = 0x82 ; | 471 | state->TunerRegs[15].Reg_Val = 0x82 ; |
625 | 472 | ||
626 | Tuner->TunerRegs[16].Reg_Num = 31 ; | 473 | state->TunerRegs[16].Reg_Num = 31 ; |
627 | Tuner->TunerRegs[16].Reg_Val = 0x00 ; | 474 | state->TunerRegs[16].Reg_Val = 0x00 ; |
628 | 475 | ||
629 | Tuner->TunerRegs[17].Reg_Num = 32 ; | 476 | state->TunerRegs[17].Reg_Num = 32 ; |
630 | Tuner->TunerRegs[17].Reg_Val = 0x40 ; | 477 | state->TunerRegs[17].Reg_Val = 0x40 ; |
631 | 478 | ||
632 | Tuner->TunerRegs[18].Reg_Num = 33 ; | 479 | state->TunerRegs[18].Reg_Num = 33 ; |
633 | Tuner->TunerRegs[18].Reg_Val = 0x53 ; | 480 | state->TunerRegs[18].Reg_Val = 0x53 ; |
634 | 481 | ||
635 | Tuner->TunerRegs[19].Reg_Num = 34 ; | 482 | state->TunerRegs[19].Reg_Num = 34 ; |
636 | Tuner->TunerRegs[19].Reg_Val = 0x81 ; | 483 | state->TunerRegs[19].Reg_Val = 0x81 ; |
637 | 484 | ||
638 | Tuner->TunerRegs[20].Reg_Num = 35 ; | 485 | state->TunerRegs[20].Reg_Num = 35 ; |
639 | Tuner->TunerRegs[20].Reg_Val = 0xC9 ; | 486 | state->TunerRegs[20].Reg_Val = 0xC9 ; |
640 | 487 | ||
641 | Tuner->TunerRegs[21].Reg_Num = 36 ; | 488 | state->TunerRegs[21].Reg_Num = 36 ; |
642 | Tuner->TunerRegs[21].Reg_Val = 0x01 ; | 489 | state->TunerRegs[21].Reg_Val = 0x01 ; |
643 | 490 | ||
644 | Tuner->TunerRegs[22].Reg_Num = 37 ; | 491 | state->TunerRegs[22].Reg_Num = 37 ; |
645 | Tuner->TunerRegs[22].Reg_Val = 0x00 ; | 492 | state->TunerRegs[22].Reg_Val = 0x00 ; |
646 | 493 | ||
647 | Tuner->TunerRegs[23].Reg_Num = 41 ; | 494 | state->TunerRegs[23].Reg_Num = 41 ; |
648 | Tuner->TunerRegs[23].Reg_Val = 0x00 ; | 495 | state->TunerRegs[23].Reg_Val = 0x00 ; |
649 | 496 | ||
650 | Tuner->TunerRegs[24].Reg_Num = 42 ; | 497 | state->TunerRegs[24].Reg_Num = 42 ; |
651 | Tuner->TunerRegs[24].Reg_Val = 0xF8 ; | 498 | state->TunerRegs[24].Reg_Val = 0xF8 ; |
652 | 499 | ||
653 | Tuner->TunerRegs[25].Reg_Num = 43 ; | 500 | state->TunerRegs[25].Reg_Num = 43 ; |
654 | Tuner->TunerRegs[25].Reg_Val = 0x43 ; | 501 | state->TunerRegs[25].Reg_Val = 0x43 ; |
655 | 502 | ||
656 | Tuner->TunerRegs[26].Reg_Num = 44 ; | 503 | state->TunerRegs[26].Reg_Num = 44 ; |
657 | Tuner->TunerRegs[26].Reg_Val = 0x20 ; | 504 | state->TunerRegs[26].Reg_Val = 0x20 ; |
658 | 505 | ||
659 | Tuner->TunerRegs[27].Reg_Num = 45 ; | 506 | state->TunerRegs[27].Reg_Num = 45 ; |
660 | Tuner->TunerRegs[27].Reg_Val = 0x80 ; | 507 | state->TunerRegs[27].Reg_Val = 0x80 ; |
661 | 508 | ||
662 | Tuner->TunerRegs[28].Reg_Num = 46 ; | 509 | state->TunerRegs[28].Reg_Num = 46 ; |
663 | Tuner->TunerRegs[28].Reg_Val = 0x88 ; | 510 | state->TunerRegs[28].Reg_Val = 0x88 ; |
664 | 511 | ||
665 | Tuner->TunerRegs[29].Reg_Num = 47 ; | 512 | state->TunerRegs[29].Reg_Num = 47 ; |
666 | Tuner->TunerRegs[29].Reg_Val = 0x86 ; | 513 | state->TunerRegs[29].Reg_Val = 0x86 ; |
667 | 514 | ||
668 | Tuner->TunerRegs[30].Reg_Num = 48 ; | 515 | state->TunerRegs[30].Reg_Num = 48 ; |
669 | Tuner->TunerRegs[30].Reg_Val = 0x00 ; | 516 | state->TunerRegs[30].Reg_Val = 0x00 ; |
670 | 517 | ||
671 | Tuner->TunerRegs[31].Reg_Num = 49 ; | 518 | state->TunerRegs[31].Reg_Num = 49 ; |
672 | Tuner->TunerRegs[31].Reg_Val = 0x00 ; | 519 | state->TunerRegs[31].Reg_Val = 0x00 ; |
673 | 520 | ||
674 | Tuner->TunerRegs[32].Reg_Num = 53 ; | 521 | state->TunerRegs[32].Reg_Num = 53 ; |
675 | Tuner->TunerRegs[32].Reg_Val = 0x94 ; | 522 | state->TunerRegs[32].Reg_Val = 0x94 ; |
676 | 523 | ||
677 | Tuner->TunerRegs[33].Reg_Num = 54 ; | 524 | state->TunerRegs[33].Reg_Num = 54 ; |
678 | Tuner->TunerRegs[33].Reg_Val = 0xFA ; | 525 | state->TunerRegs[33].Reg_Val = 0xFA ; |
679 | 526 | ||
680 | Tuner->TunerRegs[34].Reg_Num = 55 ; | 527 | state->TunerRegs[34].Reg_Num = 55 ; |
681 | Tuner->TunerRegs[34].Reg_Val = 0x92 ; | 528 | state->TunerRegs[34].Reg_Val = 0x92 ; |
682 | 529 | ||
683 | Tuner->TunerRegs[35].Reg_Num = 56 ; | 530 | state->TunerRegs[35].Reg_Num = 56 ; |
684 | Tuner->TunerRegs[35].Reg_Val = 0x80 ; | 531 | state->TunerRegs[35].Reg_Val = 0x80 ; |
685 | 532 | ||
686 | Tuner->TunerRegs[36].Reg_Num = 57 ; | 533 | state->TunerRegs[36].Reg_Num = 57 ; |
687 | Tuner->TunerRegs[36].Reg_Val = 0x41 ; | 534 | state->TunerRegs[36].Reg_Val = 0x41 ; |
688 | 535 | ||
689 | Tuner->TunerRegs[37].Reg_Num = 58 ; | 536 | state->TunerRegs[37].Reg_Num = 58 ; |
690 | Tuner->TunerRegs[37].Reg_Val = 0xDB ; | 537 | state->TunerRegs[37].Reg_Val = 0xDB ; |
691 | 538 | ||
692 | Tuner->TunerRegs[38].Reg_Num = 59 ; | 539 | state->TunerRegs[38].Reg_Num = 59 ; |
693 | Tuner->TunerRegs[38].Reg_Val = 0x00 ; | 540 | state->TunerRegs[38].Reg_Val = 0x00 ; |
694 | 541 | ||
695 | Tuner->TunerRegs[39].Reg_Num = 60 ; | 542 | state->TunerRegs[39].Reg_Num = 60 ; |
696 | Tuner->TunerRegs[39].Reg_Val = 0x00 ; | 543 | state->TunerRegs[39].Reg_Val = 0x00 ; |
697 | 544 | ||
698 | Tuner->TunerRegs[40].Reg_Num = 61 ; | 545 | state->TunerRegs[40].Reg_Num = 61 ; |
699 | Tuner->TunerRegs[40].Reg_Val = 0x00 ; | 546 | state->TunerRegs[40].Reg_Val = 0x00 ; |
700 | 547 | ||
701 | Tuner->TunerRegs[41].Reg_Num = 62 ; | 548 | state->TunerRegs[41].Reg_Num = 62 ; |
702 | Tuner->TunerRegs[41].Reg_Val = 0x00 ; | 549 | state->TunerRegs[41].Reg_Val = 0x00 ; |
703 | 550 | ||
704 | Tuner->TunerRegs[42].Reg_Num = 65 ; | 551 | state->TunerRegs[42].Reg_Num = 65 ; |
705 | Tuner->TunerRegs[42].Reg_Val = 0xF8 ; | 552 | state->TunerRegs[42].Reg_Val = 0xF8 ; |
706 | 553 | ||
707 | Tuner->TunerRegs[43].Reg_Num = 66 ; | 554 | state->TunerRegs[43].Reg_Num = 66 ; |
708 | Tuner->TunerRegs[43].Reg_Val = 0xE4 ; | 555 | state->TunerRegs[43].Reg_Val = 0xE4 ; |
709 | 556 | ||
710 | Tuner->TunerRegs[44].Reg_Num = 67 ; | 557 | state->TunerRegs[44].Reg_Num = 67 ; |
711 | Tuner->TunerRegs[44].Reg_Val = 0x90 ; | 558 | state->TunerRegs[44].Reg_Val = 0x90 ; |
712 | 559 | ||
713 | Tuner->TunerRegs[45].Reg_Num = 68 ; | 560 | state->TunerRegs[45].Reg_Num = 68 ; |
714 | Tuner->TunerRegs[45].Reg_Val = 0xC0 ; | 561 | state->TunerRegs[45].Reg_Val = 0xC0 ; |
715 | 562 | ||
716 | Tuner->TunerRegs[46].Reg_Num = 69 ; | 563 | state->TunerRegs[46].Reg_Num = 69 ; |
717 | Tuner->TunerRegs[46].Reg_Val = 0x01 ; | 564 | state->TunerRegs[46].Reg_Val = 0x01 ; |
718 | 565 | ||
719 | Tuner->TunerRegs[47].Reg_Num = 70 ; | 566 | state->TunerRegs[47].Reg_Num = 70 ; |
720 | Tuner->TunerRegs[47].Reg_Val = 0x50 ; | 567 | state->TunerRegs[47].Reg_Val = 0x50 ; |
721 | 568 | ||
722 | Tuner->TunerRegs[48].Reg_Num = 71 ; | 569 | state->TunerRegs[48].Reg_Num = 71 ; |
723 | Tuner->TunerRegs[48].Reg_Val = 0x06 ; | 570 | state->TunerRegs[48].Reg_Val = 0x06 ; |
724 | 571 | ||
725 | Tuner->TunerRegs[49].Reg_Num = 72 ; | 572 | state->TunerRegs[49].Reg_Num = 72 ; |
726 | Tuner->TunerRegs[49].Reg_Val = 0x00 ; | 573 | state->TunerRegs[49].Reg_Val = 0x00 ; |
727 | 574 | ||
728 | Tuner->TunerRegs[50].Reg_Num = 73 ; | 575 | state->TunerRegs[50].Reg_Num = 73 ; |
729 | Tuner->TunerRegs[50].Reg_Val = 0x20 ; | 576 | state->TunerRegs[50].Reg_Val = 0x20 ; |
730 | 577 | ||
731 | Tuner->TunerRegs[51].Reg_Num = 76 ; | 578 | state->TunerRegs[51].Reg_Num = 76 ; |
732 | Tuner->TunerRegs[51].Reg_Val = 0xBB ; | 579 | state->TunerRegs[51].Reg_Val = 0xBB ; |
733 | 580 | ||
734 | Tuner->TunerRegs[52].Reg_Num = 77 ; | 581 | state->TunerRegs[52].Reg_Num = 77 ; |
735 | Tuner->TunerRegs[52].Reg_Val = 0x13 ; | 582 | state->TunerRegs[52].Reg_Val = 0x13 ; |
736 | 583 | ||
737 | Tuner->TunerRegs[53].Reg_Num = 81 ; | 584 | state->TunerRegs[53].Reg_Num = 81 ; |
738 | Tuner->TunerRegs[53].Reg_Val = 0x04 ; | 585 | state->TunerRegs[53].Reg_Val = 0x04 ; |
739 | 586 | ||
740 | Tuner->TunerRegs[54].Reg_Num = 82 ; | 587 | state->TunerRegs[54].Reg_Num = 82 ; |
741 | Tuner->TunerRegs[54].Reg_Val = 0x75 ; | 588 | state->TunerRegs[54].Reg_Val = 0x75 ; |
742 | 589 | ||
743 | Tuner->TunerRegs[55].Reg_Num = 83 ; | 590 | state->TunerRegs[55].Reg_Num = 83 ; |
744 | Tuner->TunerRegs[55].Reg_Val = 0x00 ; | 591 | state->TunerRegs[55].Reg_Val = 0x00 ; |
745 | 592 | ||
746 | Tuner->TunerRegs[56].Reg_Num = 84 ; | 593 | state->TunerRegs[56].Reg_Num = 84 ; |
747 | Tuner->TunerRegs[56].Reg_Val = 0x00 ; | 594 | state->TunerRegs[56].Reg_Val = 0x00 ; |
748 | 595 | ||
749 | Tuner->TunerRegs[57].Reg_Num = 85 ; | 596 | state->TunerRegs[57].Reg_Num = 85 ; |
750 | Tuner->TunerRegs[57].Reg_Val = 0x00 ; | 597 | state->TunerRegs[57].Reg_Val = 0x00 ; |
751 | 598 | ||
752 | Tuner->TunerRegs[58].Reg_Num = 91 ; | 599 | state->TunerRegs[58].Reg_Num = 91 ; |
753 | Tuner->TunerRegs[58].Reg_Val = 0x70 ; | 600 | state->TunerRegs[58].Reg_Val = 0x70 ; |
754 | 601 | ||
755 | Tuner->TunerRegs[59].Reg_Num = 92 ; | 602 | state->TunerRegs[59].Reg_Num = 92 ; |
756 | Tuner->TunerRegs[59].Reg_Val = 0x00 ; | 603 | state->TunerRegs[59].Reg_Val = 0x00 ; |
757 | 604 | ||
758 | Tuner->TunerRegs[60].Reg_Num = 93 ; | 605 | state->TunerRegs[60].Reg_Num = 93 ; |
759 | Tuner->TunerRegs[60].Reg_Val = 0x00 ; | 606 | state->TunerRegs[60].Reg_Val = 0x00 ; |
760 | 607 | ||
761 | Tuner->TunerRegs[61].Reg_Num = 94 ; | 608 | state->TunerRegs[61].Reg_Num = 94 ; |
762 | Tuner->TunerRegs[61].Reg_Val = 0x00 ; | 609 | state->TunerRegs[61].Reg_Val = 0x00 ; |
763 | 610 | ||
764 | Tuner->TunerRegs[62].Reg_Num = 95 ; | 611 | state->TunerRegs[62].Reg_Num = 95 ; |
765 | Tuner->TunerRegs[62].Reg_Val = 0x0C ; | 612 | state->TunerRegs[62].Reg_Val = 0x0C ; |
766 | 613 | ||
767 | Tuner->TunerRegs[63].Reg_Num = 96 ; | 614 | state->TunerRegs[63].Reg_Num = 96 ; |
768 | Tuner->TunerRegs[63].Reg_Val = 0x00 ; | 615 | state->TunerRegs[63].Reg_Val = 0x00 ; |
769 | 616 | ||
770 | Tuner->TunerRegs[64].Reg_Num = 97 ; | 617 | state->TunerRegs[64].Reg_Num = 97 ; |
771 | Tuner->TunerRegs[64].Reg_Val = 0x00 ; | 618 | state->TunerRegs[64].Reg_Val = 0x00 ; |
772 | 619 | ||
773 | Tuner->TunerRegs[65].Reg_Num = 98 ; | 620 | state->TunerRegs[65].Reg_Num = 98 ; |
774 | Tuner->TunerRegs[65].Reg_Val = 0xE2 ; | 621 | state->TunerRegs[65].Reg_Val = 0xE2 ; |
775 | 622 | ||
776 | Tuner->TunerRegs[66].Reg_Num = 99 ; | 623 | state->TunerRegs[66].Reg_Num = 99 ; |
777 | Tuner->TunerRegs[66].Reg_Val = 0x00 ; | 624 | state->TunerRegs[66].Reg_Val = 0x00 ; |
778 | 625 | ||
779 | Tuner->TunerRegs[67].Reg_Num = 100 ; | 626 | state->TunerRegs[67].Reg_Num = 100 ; |
780 | Tuner->TunerRegs[67].Reg_Val = 0x00 ; | 627 | state->TunerRegs[67].Reg_Val = 0x00 ; |
781 | 628 | ||
782 | Tuner->TunerRegs[68].Reg_Num = 101 ; | 629 | state->TunerRegs[68].Reg_Num = 101 ; |
783 | Tuner->TunerRegs[68].Reg_Val = 0x12 ; | 630 | state->TunerRegs[68].Reg_Val = 0x12 ; |
784 | 631 | ||
785 | Tuner->TunerRegs[69].Reg_Num = 102 ; | 632 | state->TunerRegs[69].Reg_Num = 102 ; |
786 | Tuner->TunerRegs[69].Reg_Val = 0x80 ; | 633 | state->TunerRegs[69].Reg_Val = 0x80 ; |
787 | 634 | ||
788 | Tuner->TunerRegs[70].Reg_Num = 103 ; | 635 | state->TunerRegs[70].Reg_Num = 103 ; |
789 | Tuner->TunerRegs[70].Reg_Val = 0x32 ; | 636 | state->TunerRegs[70].Reg_Val = 0x32 ; |
790 | 637 | ||
791 | Tuner->TunerRegs[71].Reg_Num = 104 ; | 638 | state->TunerRegs[71].Reg_Num = 104 ; |
792 | Tuner->TunerRegs[71].Reg_Val = 0xB4 ; | 639 | state->TunerRegs[71].Reg_Val = 0xB4 ; |
793 | 640 | ||
794 | Tuner->TunerRegs[72].Reg_Num = 105 ; | 641 | state->TunerRegs[72].Reg_Num = 105 ; |
795 | Tuner->TunerRegs[72].Reg_Val = 0x60 ; | 642 | state->TunerRegs[72].Reg_Val = 0x60 ; |
796 | 643 | ||
797 | Tuner->TunerRegs[73].Reg_Num = 106 ; | 644 | state->TunerRegs[73].Reg_Num = 106 ; |
798 | Tuner->TunerRegs[73].Reg_Val = 0x83 ; | 645 | state->TunerRegs[73].Reg_Val = 0x83 ; |
799 | 646 | ||
800 | Tuner->TunerRegs[74].Reg_Num = 107 ; | 647 | state->TunerRegs[74].Reg_Num = 107 ; |
801 | Tuner->TunerRegs[74].Reg_Val = 0x84 ; | 648 | state->TunerRegs[74].Reg_Val = 0x84 ; |
802 | 649 | ||
803 | Tuner->TunerRegs[75].Reg_Num = 108 ; | 650 | state->TunerRegs[75].Reg_Num = 108 ; |
804 | Tuner->TunerRegs[75].Reg_Val = 0x9C ; | 651 | state->TunerRegs[75].Reg_Val = 0x9C ; |
805 | 652 | ||
806 | Tuner->TunerRegs[76].Reg_Num = 109 ; | 653 | state->TunerRegs[76].Reg_Num = 109 ; |
807 | Tuner->TunerRegs[76].Reg_Val = 0x02 ; | 654 | state->TunerRegs[76].Reg_Val = 0x02 ; |
808 | 655 | ||
809 | Tuner->TunerRegs[77].Reg_Num = 110 ; | 656 | state->TunerRegs[77].Reg_Num = 110 ; |
810 | Tuner->TunerRegs[77].Reg_Val = 0x81 ; | 657 | state->TunerRegs[77].Reg_Val = 0x81 ; |
811 | 658 | ||
812 | Tuner->TunerRegs[78].Reg_Num = 111 ; | 659 | state->TunerRegs[78].Reg_Num = 111 ; |
813 | Tuner->TunerRegs[78].Reg_Val = 0xC0 ; | 660 | state->TunerRegs[78].Reg_Val = 0xC0 ; |
814 | 661 | ||
815 | Tuner->TunerRegs[79].Reg_Num = 112 ; | 662 | state->TunerRegs[79].Reg_Num = 112 ; |
816 | Tuner->TunerRegs[79].Reg_Val = 0x10 ; | 663 | state->TunerRegs[79].Reg_Val = 0x10 ; |
817 | 664 | ||
818 | Tuner->TunerRegs[80].Reg_Num = 131 ; | 665 | state->TunerRegs[80].Reg_Num = 131 ; |
819 | Tuner->TunerRegs[80].Reg_Val = 0x8A ; | 666 | state->TunerRegs[80].Reg_Val = 0x8A ; |
820 | 667 | ||
821 | Tuner->TunerRegs[81].Reg_Num = 132 ; | 668 | state->TunerRegs[81].Reg_Num = 132 ; |
822 | Tuner->TunerRegs[81].Reg_Val = 0x10 ; | 669 | state->TunerRegs[81].Reg_Val = 0x10 ; |
823 | 670 | ||
824 | Tuner->TunerRegs[82].Reg_Num = 133 ; | 671 | state->TunerRegs[82].Reg_Num = 133 ; |
825 | Tuner->TunerRegs[82].Reg_Val = 0x24 ; | 672 | state->TunerRegs[82].Reg_Val = 0x24 ; |
826 | 673 | ||
827 | Tuner->TunerRegs[83].Reg_Num = 134 ; | 674 | state->TunerRegs[83].Reg_Num = 134 ; |
828 | Tuner->TunerRegs[83].Reg_Val = 0x00 ; | 675 | state->TunerRegs[83].Reg_Val = 0x00 ; |
829 | 676 | ||
830 | Tuner->TunerRegs[84].Reg_Num = 135 ; | 677 | state->TunerRegs[84].Reg_Num = 135 ; |
831 | Tuner->TunerRegs[84].Reg_Val = 0x00 ; | 678 | state->TunerRegs[84].Reg_Val = 0x00 ; |
832 | 679 | ||
833 | Tuner->TunerRegs[85].Reg_Num = 136 ; | 680 | state->TunerRegs[85].Reg_Num = 136 ; |
834 | Tuner->TunerRegs[85].Reg_Val = 0x7E ; | 681 | state->TunerRegs[85].Reg_Val = 0x7E ; |
835 | 682 | ||
836 | Tuner->TunerRegs[86].Reg_Num = 137 ; | 683 | state->TunerRegs[86].Reg_Num = 137 ; |
837 | Tuner->TunerRegs[86].Reg_Val = 0x40 ; | 684 | state->TunerRegs[86].Reg_Val = 0x40 ; |
838 | 685 | ||
839 | Tuner->TunerRegs[87].Reg_Num = 138 ; | 686 | state->TunerRegs[87].Reg_Num = 138 ; |
840 | Tuner->TunerRegs[87].Reg_Val = 0x38 ; | 687 | state->TunerRegs[87].Reg_Val = 0x38 ; |
841 | 688 | ||
842 | Tuner->TunerRegs[88].Reg_Num = 146 ; | 689 | state->TunerRegs[88].Reg_Num = 146 ; |
843 | Tuner->TunerRegs[88].Reg_Val = 0xF6 ; | 690 | state->TunerRegs[88].Reg_Val = 0xF6 ; |
844 | 691 | ||
845 | Tuner->TunerRegs[89].Reg_Num = 147 ; | 692 | state->TunerRegs[89].Reg_Num = 147 ; |
846 | Tuner->TunerRegs[89].Reg_Val = 0x1A ; | 693 | state->TunerRegs[89].Reg_Val = 0x1A ; |
847 | 694 | ||
848 | Tuner->TunerRegs[90].Reg_Num = 148 ; | 695 | state->TunerRegs[90].Reg_Num = 148 ; |
849 | Tuner->TunerRegs[90].Reg_Val = 0x62 ; | 696 | state->TunerRegs[90].Reg_Val = 0x62 ; |
850 | 697 | ||
851 | Tuner->TunerRegs[91].Reg_Num = 149 ; | 698 | state->TunerRegs[91].Reg_Num = 149 ; |
852 | Tuner->TunerRegs[91].Reg_Val = 0x33 ; | 699 | state->TunerRegs[91].Reg_Val = 0x33 ; |
853 | 700 | ||
854 | Tuner->TunerRegs[92].Reg_Num = 150 ; | 701 | state->TunerRegs[92].Reg_Num = 150 ; |
855 | Tuner->TunerRegs[92].Reg_Val = 0x80 ; | 702 | state->TunerRegs[92].Reg_Val = 0x80 ; |
856 | 703 | ||
857 | Tuner->TunerRegs[93].Reg_Num = 156 ; | 704 | state->TunerRegs[93].Reg_Num = 156 ; |
858 | Tuner->TunerRegs[93].Reg_Val = 0x56 ; | 705 | state->TunerRegs[93].Reg_Val = 0x56 ; |
859 | 706 | ||
860 | Tuner->TunerRegs[94].Reg_Num = 157 ; | 707 | state->TunerRegs[94].Reg_Num = 157 ; |
861 | Tuner->TunerRegs[94].Reg_Val = 0x17 ; | 708 | state->TunerRegs[94].Reg_Val = 0x17 ; |
862 | 709 | ||
863 | Tuner->TunerRegs[95].Reg_Num = 158 ; | 710 | state->TunerRegs[95].Reg_Num = 158 ; |
864 | Tuner->TunerRegs[95].Reg_Val = 0xA9 ; | 711 | state->TunerRegs[95].Reg_Val = 0xA9 ; |
865 | 712 | ||
866 | Tuner->TunerRegs[96].Reg_Num = 159 ; | 713 | state->TunerRegs[96].Reg_Num = 159 ; |
867 | Tuner->TunerRegs[96].Reg_Val = 0x00 ; | 714 | state->TunerRegs[96].Reg_Val = 0x00 ; |
868 | 715 | ||
869 | Tuner->TunerRegs[97].Reg_Num = 160 ; | 716 | state->TunerRegs[97].Reg_Num = 160 ; |
870 | Tuner->TunerRegs[97].Reg_Val = 0x00 ; | 717 | state->TunerRegs[97].Reg_Val = 0x00 ; |
871 | 718 | ||
872 | Tuner->TunerRegs[98].Reg_Num = 161 ; | 719 | state->TunerRegs[98].Reg_Num = 161 ; |
873 | Tuner->TunerRegs[98].Reg_Val = 0x00 ; | 720 | state->TunerRegs[98].Reg_Val = 0x00 ; |
874 | 721 | ||
875 | Tuner->TunerRegs[99].Reg_Num = 162 ; | 722 | state->TunerRegs[99].Reg_Num = 162 ; |
876 | Tuner->TunerRegs[99].Reg_Val = 0x40 ; | 723 | state->TunerRegs[99].Reg_Val = 0x40 ; |
877 | 724 | ||
878 | Tuner->TunerRegs[100].Reg_Num = 166 ; | 725 | state->TunerRegs[100].Reg_Num = 166 ; |
879 | Tuner->TunerRegs[100].Reg_Val = 0xAE ; | 726 | state->TunerRegs[100].Reg_Val = 0xAE ; |
880 | 727 | ||
881 | Tuner->TunerRegs[101].Reg_Num = 167 ; | 728 | state->TunerRegs[101].Reg_Num = 167 ; |
882 | Tuner->TunerRegs[101].Reg_Val = 0x1B ; | 729 | state->TunerRegs[101].Reg_Val = 0x1B ; |
883 | 730 | ||
884 | Tuner->TunerRegs[102].Reg_Num = 168 ; | 731 | state->TunerRegs[102].Reg_Num = 168 ; |
885 | Tuner->TunerRegs[102].Reg_Val = 0xF2 ; | 732 | state->TunerRegs[102].Reg_Val = 0xF2 ; |
886 | 733 | ||
887 | Tuner->TunerRegs[103].Reg_Num = 195 ; | 734 | state->TunerRegs[103].Reg_Num = 195 ; |
888 | Tuner->TunerRegs[103].Reg_Val = 0x00 ; | 735 | state->TunerRegs[103].Reg_Val = 0x00 ; |
889 | 736 | ||
890 | return 0 ; | 737 | return 0 ; |
891 | } | 738 | } |
892 | 739 | ||
893 | u16 MXL5005_ControlInit(Tuner_struct *Tuner) | 740 | // DONE |
741 | u16 MXL5005_ControlInit(struct dvb_frontend *fe) | ||
894 | { | 742 | { |
895 | Tuner->Init_Ctrl_Num = INITCTRL_NUM ; | 743 | struct mxl5005s_state *state = fe->demodulator_priv; |
896 | 744 | state->Init_Ctrl_Num = INITCTRL_NUM; | |
897 | Tuner->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; | 745 | |
898 | Tuner->Init_Ctrl[0].size = 1 ; | 746 | state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; |
899 | Tuner->Init_Ctrl[0].addr[0] = 73; | 747 | state->Init_Ctrl[0].size = 1 ; |
900 | Tuner->Init_Ctrl[0].bit[0] = 7; | 748 | state->Init_Ctrl[0].addr[0] = 73; |
901 | Tuner->Init_Ctrl[0].val[0] = 0; | 749 | state->Init_Ctrl[0].bit[0] = 7; |
902 | 750 | state->Init_Ctrl[0].val[0] = 0; | |
903 | Tuner->Init_Ctrl[1].Ctrl_Num = BB_MODE ; | 751 | |
904 | Tuner->Init_Ctrl[1].size = 1 ; | 752 | state->Init_Ctrl[1].Ctrl_Num = BB_MODE ; |
905 | Tuner->Init_Ctrl[1].addr[0] = 53; | 753 | state->Init_Ctrl[1].size = 1 ; |
906 | Tuner->Init_Ctrl[1].bit[0] = 2; | 754 | state->Init_Ctrl[1].addr[0] = 53; |
907 | Tuner->Init_Ctrl[1].val[0] = 1; | 755 | state->Init_Ctrl[1].bit[0] = 2; |
908 | 756 | state->Init_Ctrl[1].val[0] = 1; | |
909 | Tuner->Init_Ctrl[2].Ctrl_Num = BB_BUF ; | 757 | |
910 | Tuner->Init_Ctrl[2].size = 2 ; | 758 | state->Init_Ctrl[2].Ctrl_Num = BB_BUF ; |
911 | Tuner->Init_Ctrl[2].addr[0] = 53; | 759 | state->Init_Ctrl[2].size = 2 ; |
912 | Tuner->Init_Ctrl[2].bit[0] = 1; | 760 | state->Init_Ctrl[2].addr[0] = 53; |
913 | Tuner->Init_Ctrl[2].val[0] = 0; | 761 | state->Init_Ctrl[2].bit[0] = 1; |
914 | Tuner->Init_Ctrl[2].addr[1] = 57; | 762 | state->Init_Ctrl[2].val[0] = 0; |
915 | Tuner->Init_Ctrl[2].bit[1] = 0; | 763 | state->Init_Ctrl[2].addr[1] = 57; |
916 | Tuner->Init_Ctrl[2].val[1] = 1; | 764 | state->Init_Ctrl[2].bit[1] = 0; |
917 | 765 | state->Init_Ctrl[2].val[1] = 1; | |
918 | Tuner->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ; | 766 | |
919 | Tuner->Init_Ctrl[3].size = 1 ; | 767 | state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ; |
920 | Tuner->Init_Ctrl[3].addr[0] = 53; | 768 | state->Init_Ctrl[3].size = 1 ; |
921 | Tuner->Init_Ctrl[3].bit[0] = 0; | 769 | state->Init_Ctrl[3].addr[0] = 53; |
922 | Tuner->Init_Ctrl[3].val[0] = 0; | 770 | state->Init_Ctrl[3].bit[0] = 0; |
923 | 771 | state->Init_Ctrl[3].val[0] = 0; | |
924 | Tuner->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ; | 772 | |
925 | Tuner->Init_Ctrl[4].size = 3 ; | 773 | state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ; |
926 | Tuner->Init_Ctrl[4].addr[0] = 53; | 774 | state->Init_Ctrl[4].size = 3 ; |
927 | Tuner->Init_Ctrl[4].bit[0] = 5; | 775 | state->Init_Ctrl[4].addr[0] = 53; |
928 | Tuner->Init_Ctrl[4].val[0] = 0; | 776 | state->Init_Ctrl[4].bit[0] = 5; |
929 | Tuner->Init_Ctrl[4].addr[1] = 53; | 777 | state->Init_Ctrl[4].val[0] = 0; |
930 | Tuner->Init_Ctrl[4].bit[1] = 6; | 778 | state->Init_Ctrl[4].addr[1] = 53; |
931 | Tuner->Init_Ctrl[4].val[1] = 0; | 779 | state->Init_Ctrl[4].bit[1] = 6; |
932 | Tuner->Init_Ctrl[4].addr[2] = 53; | 780 | state->Init_Ctrl[4].val[1] = 0; |
933 | Tuner->Init_Ctrl[4].bit[2] = 7; | 781 | state->Init_Ctrl[4].addr[2] = 53; |
934 | Tuner->Init_Ctrl[4].val[2] = 1; | 782 | state->Init_Ctrl[4].bit[2] = 7; |
935 | 783 | state->Init_Ctrl[4].val[2] = 1; | |
936 | Tuner->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ; | 784 | |
937 | Tuner->Init_Ctrl[5].size = 1 ; | 785 | state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ; |
938 | Tuner->Init_Ctrl[5].addr[0] = 59; | 786 | state->Init_Ctrl[5].size = 1 ; |
939 | Tuner->Init_Ctrl[5].bit[0] = 0; | 787 | state->Init_Ctrl[5].addr[0] = 59; |
940 | Tuner->Init_Ctrl[5].val[0] = 0; | 788 | state->Init_Ctrl[5].bit[0] = 0; |
941 | 789 | state->Init_Ctrl[5].val[0] = 0; | |
942 | Tuner->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ; | 790 | |
943 | Tuner->Init_Ctrl[6].size = 2 ; | 791 | state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ; |
944 | Tuner->Init_Ctrl[6].addr[0] = 53; | 792 | state->Init_Ctrl[6].size = 2 ; |
945 | Tuner->Init_Ctrl[6].bit[0] = 3; | 793 | state->Init_Ctrl[6].addr[0] = 53; |
946 | Tuner->Init_Ctrl[6].val[0] = 0; | 794 | state->Init_Ctrl[6].bit[0] = 3; |
947 | Tuner->Init_Ctrl[6].addr[1] = 53; | 795 | state->Init_Ctrl[6].val[0] = 0; |
948 | Tuner->Init_Ctrl[6].bit[1] = 4; | 796 | state->Init_Ctrl[6].addr[1] = 53; |
949 | Tuner->Init_Ctrl[6].val[1] = 1; | 797 | state->Init_Ctrl[6].bit[1] = 4; |
950 | 798 | state->Init_Ctrl[6].val[1] = 1; | |
951 | Tuner->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ; | 799 | |
952 | Tuner->Init_Ctrl[7].size = 4 ; | 800 | state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ; |
953 | Tuner->Init_Ctrl[7].addr[0] = 22; | 801 | state->Init_Ctrl[7].size = 4 ; |
954 | Tuner->Init_Ctrl[7].bit[0] = 4; | 802 | state->Init_Ctrl[7].addr[0] = 22; |
955 | Tuner->Init_Ctrl[7].val[0] = 0; | 803 | state->Init_Ctrl[7].bit[0] = 4; |
956 | Tuner->Init_Ctrl[7].addr[1] = 22; | 804 | state->Init_Ctrl[7].val[0] = 0; |
957 | Tuner->Init_Ctrl[7].bit[1] = 5; | 805 | state->Init_Ctrl[7].addr[1] = 22; |
958 | Tuner->Init_Ctrl[7].val[1] = 1; | 806 | state->Init_Ctrl[7].bit[1] = 5; |
959 | Tuner->Init_Ctrl[7].addr[2] = 22; | 807 | state->Init_Ctrl[7].val[1] = 1; |
960 | Tuner->Init_Ctrl[7].bit[2] = 6; | 808 | state->Init_Ctrl[7].addr[2] = 22; |
961 | Tuner->Init_Ctrl[7].val[2] = 1; | 809 | state->Init_Ctrl[7].bit[2] = 6; |
962 | Tuner->Init_Ctrl[7].addr[3] = 22; | 810 | state->Init_Ctrl[7].val[2] = 1; |
963 | Tuner->Init_Ctrl[7].bit[3] = 7; | 811 | state->Init_Ctrl[7].addr[3] = 22; |
964 | Tuner->Init_Ctrl[7].val[3] = 0; | 812 | state->Init_Ctrl[7].bit[3] = 7; |
965 | 813 | state->Init_Ctrl[7].val[3] = 0; | |
966 | Tuner->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ; | 814 | |
967 | Tuner->Init_Ctrl[8].size = 1 ; | 815 | state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ; |
968 | Tuner->Init_Ctrl[8].addr[0] = 22; | 816 | state->Init_Ctrl[8].size = 1 ; |
969 | Tuner->Init_Ctrl[8].bit[0] = 2; | 817 | state->Init_Ctrl[8].addr[0] = 22; |
970 | Tuner->Init_Ctrl[8].val[0] = 0; | 818 | state->Init_Ctrl[8].bit[0] = 2; |
971 | 819 | state->Init_Ctrl[8].val[0] = 0; | |
972 | Tuner->Init_Ctrl[9].Ctrl_Num = AGC_IF ; | 820 | |
973 | Tuner->Init_Ctrl[9].size = 4 ; | 821 | state->Init_Ctrl[9].Ctrl_Num = AGC_IF ; |
974 | Tuner->Init_Ctrl[9].addr[0] = 76; | 822 | state->Init_Ctrl[9].size = 4 ; |
975 | Tuner->Init_Ctrl[9].bit[0] = 0; | 823 | state->Init_Ctrl[9].addr[0] = 76; |
976 | Tuner->Init_Ctrl[9].val[0] = 1; | 824 | state->Init_Ctrl[9].bit[0] = 0; |
977 | Tuner->Init_Ctrl[9].addr[1] = 76; | 825 | state->Init_Ctrl[9].val[0] = 1; |
978 | Tuner->Init_Ctrl[9].bit[1] = 1; | 826 | state->Init_Ctrl[9].addr[1] = 76; |
979 | Tuner->Init_Ctrl[9].val[1] = 1; | 827 | state->Init_Ctrl[9].bit[1] = 1; |
980 | Tuner->Init_Ctrl[9].addr[2] = 76; | 828 | state->Init_Ctrl[9].val[1] = 1; |
981 | Tuner->Init_Ctrl[9].bit[2] = 2; | 829 | state->Init_Ctrl[9].addr[2] = 76; |
982 | Tuner->Init_Ctrl[9].val[2] = 0; | 830 | state->Init_Ctrl[9].bit[2] = 2; |
983 | Tuner->Init_Ctrl[9].addr[3] = 76; | 831 | state->Init_Ctrl[9].val[2] = 0; |
984 | Tuner->Init_Ctrl[9].bit[3] = 3; | 832 | state->Init_Ctrl[9].addr[3] = 76; |
985 | Tuner->Init_Ctrl[9].val[3] = 1; | 833 | state->Init_Ctrl[9].bit[3] = 3; |
986 | 834 | state->Init_Ctrl[9].val[3] = 1; | |
987 | Tuner->Init_Ctrl[10].Ctrl_Num = AGC_RF ; | 835 | |
988 | Tuner->Init_Ctrl[10].size = 4 ; | 836 | state->Init_Ctrl[10].Ctrl_Num = AGC_RF ; |
989 | Tuner->Init_Ctrl[10].addr[0] = 76; | 837 | state->Init_Ctrl[10].size = 4 ; |
990 | Tuner->Init_Ctrl[10].bit[0] = 4; | 838 | state->Init_Ctrl[10].addr[0] = 76; |
991 | Tuner->Init_Ctrl[10].val[0] = 1; | 839 | state->Init_Ctrl[10].bit[0] = 4; |
992 | Tuner->Init_Ctrl[10].addr[1] = 76; | 840 | state->Init_Ctrl[10].val[0] = 1; |
993 | Tuner->Init_Ctrl[10].bit[1] = 5; | 841 | state->Init_Ctrl[10].addr[1] = 76; |
994 | Tuner->Init_Ctrl[10].val[1] = 1; | 842 | state->Init_Ctrl[10].bit[1] = 5; |
995 | Tuner->Init_Ctrl[10].addr[2] = 76; | 843 | state->Init_Ctrl[10].val[1] = 1; |
996 | Tuner->Init_Ctrl[10].bit[2] = 6; | 844 | state->Init_Ctrl[10].addr[2] = 76; |
997 | Tuner->Init_Ctrl[10].val[2] = 0; | 845 | state->Init_Ctrl[10].bit[2] = 6; |
998 | Tuner->Init_Ctrl[10].addr[3] = 76; | 846 | state->Init_Ctrl[10].val[2] = 0; |
999 | Tuner->Init_Ctrl[10].bit[3] = 7; | 847 | state->Init_Ctrl[10].addr[3] = 76; |
1000 | Tuner->Init_Ctrl[10].val[3] = 1; | 848 | state->Init_Ctrl[10].bit[3] = 7; |
1001 | 849 | state->Init_Ctrl[10].val[3] = 1; | |
1002 | Tuner->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ; | 850 | |
1003 | Tuner->Init_Ctrl[11].size = 5 ; | 851 | state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ; |
1004 | Tuner->Init_Ctrl[11].addr[0] = 43; | 852 | state->Init_Ctrl[11].size = 5 ; |
1005 | Tuner->Init_Ctrl[11].bit[0] = 3; | 853 | state->Init_Ctrl[11].addr[0] = 43; |
1006 | Tuner->Init_Ctrl[11].val[0] = 0; | 854 | state->Init_Ctrl[11].bit[0] = 3; |
1007 | Tuner->Init_Ctrl[11].addr[1] = 43; | 855 | state->Init_Ctrl[11].val[0] = 0; |
1008 | Tuner->Init_Ctrl[11].bit[1] = 4; | 856 | state->Init_Ctrl[11].addr[1] = 43; |
1009 | Tuner->Init_Ctrl[11].val[1] = 0; | 857 | state->Init_Ctrl[11].bit[1] = 4; |
1010 | Tuner->Init_Ctrl[11].addr[2] = 43; | 858 | state->Init_Ctrl[11].val[1] = 0; |
1011 | Tuner->Init_Ctrl[11].bit[2] = 5; | 859 | state->Init_Ctrl[11].addr[2] = 43; |
1012 | Tuner->Init_Ctrl[11].val[2] = 0; | 860 | state->Init_Ctrl[11].bit[2] = 5; |
1013 | Tuner->Init_Ctrl[11].addr[3] = 43; | 861 | state->Init_Ctrl[11].val[2] = 0; |
1014 | Tuner->Init_Ctrl[11].bit[3] = 6; | 862 | state->Init_Ctrl[11].addr[3] = 43; |
1015 | Tuner->Init_Ctrl[11].val[3] = 1; | 863 | state->Init_Ctrl[11].bit[3] = 6; |
1016 | Tuner->Init_Ctrl[11].addr[4] = 43; | 864 | state->Init_Ctrl[11].val[3] = 1; |
1017 | Tuner->Init_Ctrl[11].bit[4] = 7; | 865 | state->Init_Ctrl[11].addr[4] = 43; |
1018 | Tuner->Init_Ctrl[11].val[4] = 0; | 866 | state->Init_Ctrl[11].bit[4] = 7; |
1019 | 867 | state->Init_Ctrl[11].val[4] = 0; | |
1020 | Tuner->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ; | 868 | |
1021 | Tuner->Init_Ctrl[12].size = 6 ; | 869 | state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ; |
1022 | Tuner->Init_Ctrl[12].addr[0] = 44; | 870 | state->Init_Ctrl[12].size = 6 ; |
1023 | Tuner->Init_Ctrl[12].bit[0] = 2; | 871 | state->Init_Ctrl[12].addr[0] = 44; |
1024 | Tuner->Init_Ctrl[12].val[0] = 0; | 872 | state->Init_Ctrl[12].bit[0] = 2; |
1025 | Tuner->Init_Ctrl[12].addr[1] = 44; | 873 | state->Init_Ctrl[12].val[0] = 0; |
1026 | Tuner->Init_Ctrl[12].bit[1] = 3; | 874 | state->Init_Ctrl[12].addr[1] = 44; |
1027 | Tuner->Init_Ctrl[12].val[1] = 0; | 875 | state->Init_Ctrl[12].bit[1] = 3; |
1028 | Tuner->Init_Ctrl[12].addr[2] = 44; | 876 | state->Init_Ctrl[12].val[1] = 0; |
1029 | Tuner->Init_Ctrl[12].bit[2] = 4; | 877 | state->Init_Ctrl[12].addr[2] = 44; |
1030 | Tuner->Init_Ctrl[12].val[2] = 0; | 878 | state->Init_Ctrl[12].bit[2] = 4; |
1031 | Tuner->Init_Ctrl[12].addr[3] = 44; | 879 | state->Init_Ctrl[12].val[2] = 0; |
1032 | Tuner->Init_Ctrl[12].bit[3] = 5; | 880 | state->Init_Ctrl[12].addr[3] = 44; |
1033 | Tuner->Init_Ctrl[12].val[3] = 1; | 881 | state->Init_Ctrl[12].bit[3] = 5; |
1034 | Tuner->Init_Ctrl[12].addr[4] = 44; | 882 | state->Init_Ctrl[12].val[3] = 1; |
1035 | Tuner->Init_Ctrl[12].bit[4] = 6; | 883 | state->Init_Ctrl[12].addr[4] = 44; |
1036 | Tuner->Init_Ctrl[12].val[4] = 0; | 884 | state->Init_Ctrl[12].bit[4] = 6; |
1037 | Tuner->Init_Ctrl[12].addr[5] = 44; | 885 | state->Init_Ctrl[12].val[4] = 0; |
1038 | Tuner->Init_Ctrl[12].bit[5] = 7; | 886 | state->Init_Ctrl[12].addr[5] = 44; |
1039 | Tuner->Init_Ctrl[12].val[5] = 0; | 887 | state->Init_Ctrl[12].bit[5] = 7; |
1040 | 888 | state->Init_Ctrl[12].val[5] = 0; | |
1041 | Tuner->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ; | 889 | |
1042 | Tuner->Init_Ctrl[13].size = 7 ; | 890 | state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ; |
1043 | Tuner->Init_Ctrl[13].addr[0] = 11; | 891 | state->Init_Ctrl[13].size = 7 ; |
1044 | Tuner->Init_Ctrl[13].bit[0] = 0; | 892 | state->Init_Ctrl[13].addr[0] = 11; |
1045 | Tuner->Init_Ctrl[13].val[0] = 1; | 893 | state->Init_Ctrl[13].bit[0] = 0; |
1046 | Tuner->Init_Ctrl[13].addr[1] = 11; | 894 | state->Init_Ctrl[13].val[0] = 1; |
1047 | Tuner->Init_Ctrl[13].bit[1] = 1; | 895 | state->Init_Ctrl[13].addr[1] = 11; |
1048 | Tuner->Init_Ctrl[13].val[1] = 0; | 896 | state->Init_Ctrl[13].bit[1] = 1; |
1049 | Tuner->Init_Ctrl[13].addr[2] = 11; | 897 | state->Init_Ctrl[13].val[1] = 0; |
1050 | Tuner->Init_Ctrl[13].bit[2] = 2; | 898 | state->Init_Ctrl[13].addr[2] = 11; |
1051 | Tuner->Init_Ctrl[13].val[2] = 0; | 899 | state->Init_Ctrl[13].bit[2] = 2; |
1052 | Tuner->Init_Ctrl[13].addr[3] = 11; | 900 | state->Init_Ctrl[13].val[2] = 0; |
1053 | Tuner->Init_Ctrl[13].bit[3] = 3; | 901 | state->Init_Ctrl[13].addr[3] = 11; |
1054 | Tuner->Init_Ctrl[13].val[3] = 1; | 902 | state->Init_Ctrl[13].bit[3] = 3; |
1055 | Tuner->Init_Ctrl[13].addr[4] = 11; | 903 | state->Init_Ctrl[13].val[3] = 1; |
1056 | Tuner->Init_Ctrl[13].bit[4] = 4; | 904 | state->Init_Ctrl[13].addr[4] = 11; |
1057 | Tuner->Init_Ctrl[13].val[4] = 1; | 905 | state->Init_Ctrl[13].bit[4] = 4; |
1058 | Tuner->Init_Ctrl[13].addr[5] = 11; | 906 | state->Init_Ctrl[13].val[4] = 1; |
1059 | Tuner->Init_Ctrl[13].bit[5] = 5; | 907 | state->Init_Ctrl[13].addr[5] = 11; |
1060 | Tuner->Init_Ctrl[13].val[5] = 0; | 908 | state->Init_Ctrl[13].bit[5] = 5; |
1061 | Tuner->Init_Ctrl[13].addr[6] = 11; | 909 | state->Init_Ctrl[13].val[5] = 0; |
1062 | Tuner->Init_Ctrl[13].bit[6] = 6; | 910 | state->Init_Ctrl[13].addr[6] = 11; |
1063 | Tuner->Init_Ctrl[13].val[6] = 0; | 911 | state->Init_Ctrl[13].bit[6] = 6; |
1064 | 912 | state->Init_Ctrl[13].val[6] = 0; | |
1065 | Tuner->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ; | 913 | |
1066 | Tuner->Init_Ctrl[14].size = 16 ; | 914 | state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ; |
1067 | Tuner->Init_Ctrl[14].addr[0] = 13; | 915 | state->Init_Ctrl[14].size = 16 ; |
1068 | Tuner->Init_Ctrl[14].bit[0] = 0; | 916 | state->Init_Ctrl[14].addr[0] = 13; |
1069 | Tuner->Init_Ctrl[14].val[0] = 0; | 917 | state->Init_Ctrl[14].bit[0] = 0; |
1070 | Tuner->Init_Ctrl[14].addr[1] = 13; | 918 | state->Init_Ctrl[14].val[0] = 0; |
1071 | Tuner->Init_Ctrl[14].bit[1] = 1; | 919 | state->Init_Ctrl[14].addr[1] = 13; |
1072 | Tuner->Init_Ctrl[14].val[1] = 0; | 920 | state->Init_Ctrl[14].bit[1] = 1; |
1073 | Tuner->Init_Ctrl[14].addr[2] = 13; | 921 | state->Init_Ctrl[14].val[1] = 0; |
1074 | Tuner->Init_Ctrl[14].bit[2] = 2; | 922 | state->Init_Ctrl[14].addr[2] = 13; |
1075 | Tuner->Init_Ctrl[14].val[2] = 0; | 923 | state->Init_Ctrl[14].bit[2] = 2; |
1076 | Tuner->Init_Ctrl[14].addr[3] = 13; | 924 | state->Init_Ctrl[14].val[2] = 0; |
1077 | Tuner->Init_Ctrl[14].bit[3] = 3; | 925 | state->Init_Ctrl[14].addr[3] = 13; |
1078 | Tuner->Init_Ctrl[14].val[3] = 0; | 926 | state->Init_Ctrl[14].bit[3] = 3; |
1079 | Tuner->Init_Ctrl[14].addr[4] = 13; | 927 | state->Init_Ctrl[14].val[3] = 0; |
1080 | Tuner->Init_Ctrl[14].bit[4] = 4; | 928 | state->Init_Ctrl[14].addr[4] = 13; |
1081 | Tuner->Init_Ctrl[14].val[4] = 0; | 929 | state->Init_Ctrl[14].bit[4] = 4; |
1082 | Tuner->Init_Ctrl[14].addr[5] = 13; | 930 | state->Init_Ctrl[14].val[4] = 0; |
1083 | Tuner->Init_Ctrl[14].bit[5] = 5; | 931 | state->Init_Ctrl[14].addr[5] = 13; |
1084 | Tuner->Init_Ctrl[14].val[5] = 0; | 932 | state->Init_Ctrl[14].bit[5] = 5; |
1085 | Tuner->Init_Ctrl[14].addr[6] = 13; | 933 | state->Init_Ctrl[14].val[5] = 0; |
1086 | Tuner->Init_Ctrl[14].bit[6] = 6; | 934 | state->Init_Ctrl[14].addr[6] = 13; |
1087 | Tuner->Init_Ctrl[14].val[6] = 0; | 935 | state->Init_Ctrl[14].bit[6] = 6; |
1088 | Tuner->Init_Ctrl[14].addr[7] = 13; | 936 | state->Init_Ctrl[14].val[6] = 0; |
1089 | Tuner->Init_Ctrl[14].bit[7] = 7; | 937 | state->Init_Ctrl[14].addr[7] = 13; |
1090 | Tuner->Init_Ctrl[14].val[7] = 0; | 938 | state->Init_Ctrl[14].bit[7] = 7; |
1091 | Tuner->Init_Ctrl[14].addr[8] = 12; | 939 | state->Init_Ctrl[14].val[7] = 0; |
1092 | Tuner->Init_Ctrl[14].bit[8] = 0; | 940 | state->Init_Ctrl[14].addr[8] = 12; |
1093 | Tuner->Init_Ctrl[14].val[8] = 0; | 941 | state->Init_Ctrl[14].bit[8] = 0; |
1094 | Tuner->Init_Ctrl[14].addr[9] = 12; | 942 | state->Init_Ctrl[14].val[8] = 0; |
1095 | Tuner->Init_Ctrl[14].bit[9] = 1; | 943 | state->Init_Ctrl[14].addr[9] = 12; |
1096 | Tuner->Init_Ctrl[14].val[9] = 0; | 944 | state->Init_Ctrl[14].bit[9] = 1; |
1097 | Tuner->Init_Ctrl[14].addr[10] = 12; | 945 | state->Init_Ctrl[14].val[9] = 0; |
1098 | Tuner->Init_Ctrl[14].bit[10] = 2; | 946 | state->Init_Ctrl[14].addr[10] = 12; |
1099 | Tuner->Init_Ctrl[14].val[10] = 0; | 947 | state->Init_Ctrl[14].bit[10] = 2; |
1100 | Tuner->Init_Ctrl[14].addr[11] = 12; | 948 | state->Init_Ctrl[14].val[10] = 0; |
1101 | Tuner->Init_Ctrl[14].bit[11] = 3; | 949 | state->Init_Ctrl[14].addr[11] = 12; |
1102 | Tuner->Init_Ctrl[14].val[11] = 0; | 950 | state->Init_Ctrl[14].bit[11] = 3; |
1103 | Tuner->Init_Ctrl[14].addr[12] = 12; | 951 | state->Init_Ctrl[14].val[11] = 0; |
1104 | Tuner->Init_Ctrl[14].bit[12] = 4; | 952 | state->Init_Ctrl[14].addr[12] = 12; |
1105 | Tuner->Init_Ctrl[14].val[12] = 0; | 953 | state->Init_Ctrl[14].bit[12] = 4; |
1106 | Tuner->Init_Ctrl[14].addr[13] = 12; | 954 | state->Init_Ctrl[14].val[12] = 0; |
1107 | Tuner->Init_Ctrl[14].bit[13] = 5; | 955 | state->Init_Ctrl[14].addr[13] = 12; |
1108 | Tuner->Init_Ctrl[14].val[13] = 1; | 956 | state->Init_Ctrl[14].bit[13] = 5; |
1109 | Tuner->Init_Ctrl[14].addr[14] = 12; | 957 | state->Init_Ctrl[14].val[13] = 1; |
1110 | Tuner->Init_Ctrl[14].bit[14] = 6; | 958 | state->Init_Ctrl[14].addr[14] = 12; |
1111 | Tuner->Init_Ctrl[14].val[14] = 1; | 959 | state->Init_Ctrl[14].bit[14] = 6; |
1112 | Tuner->Init_Ctrl[14].addr[15] = 12; | 960 | state->Init_Ctrl[14].val[14] = 1; |
1113 | Tuner->Init_Ctrl[14].bit[15] = 7; | 961 | state->Init_Ctrl[14].addr[15] = 12; |
1114 | Tuner->Init_Ctrl[14].val[15] = 0; | 962 | state->Init_Ctrl[14].bit[15] = 7; |
1115 | 963 | state->Init_Ctrl[14].val[15] = 0; | |
1116 | Tuner->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ; | 964 | |
1117 | Tuner->Init_Ctrl[15].size = 3 ; | 965 | state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ; |
1118 | Tuner->Init_Ctrl[15].addr[0] = 147; | 966 | state->Init_Ctrl[15].size = 3 ; |
1119 | Tuner->Init_Ctrl[15].bit[0] = 2; | 967 | state->Init_Ctrl[15].addr[0] = 147; |
1120 | Tuner->Init_Ctrl[15].val[0] = 0; | 968 | state->Init_Ctrl[15].bit[0] = 2; |
1121 | Tuner->Init_Ctrl[15].addr[1] = 147; | 969 | state->Init_Ctrl[15].val[0] = 0; |
1122 | Tuner->Init_Ctrl[15].bit[1] = 3; | 970 | state->Init_Ctrl[15].addr[1] = 147; |
1123 | Tuner->Init_Ctrl[15].val[1] = 1; | 971 | state->Init_Ctrl[15].bit[1] = 3; |
1124 | Tuner->Init_Ctrl[15].addr[2] = 147; | 972 | state->Init_Ctrl[15].val[1] = 1; |
1125 | Tuner->Init_Ctrl[15].bit[2] = 4; | 973 | state->Init_Ctrl[15].addr[2] = 147; |
1126 | Tuner->Init_Ctrl[15].val[2] = 1; | 974 | state->Init_Ctrl[15].bit[2] = 4; |
1127 | 975 | state->Init_Ctrl[15].val[2] = 1; | |
1128 | Tuner->Init_Ctrl[16].Ctrl_Num = I_DRIVER ; | 976 | |
1129 | Tuner->Init_Ctrl[16].size = 2 ; | 977 | state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ; |
1130 | Tuner->Init_Ctrl[16].addr[0] = 147; | 978 | state->Init_Ctrl[16].size = 2 ; |
1131 | Tuner->Init_Ctrl[16].bit[0] = 0; | 979 | state->Init_Ctrl[16].addr[0] = 147; |
1132 | Tuner->Init_Ctrl[16].val[0] = 0; | 980 | state->Init_Ctrl[16].bit[0] = 0; |
1133 | Tuner->Init_Ctrl[16].addr[1] = 147; | 981 | state->Init_Ctrl[16].val[0] = 0; |
1134 | Tuner->Init_Ctrl[16].bit[1] = 1; | 982 | state->Init_Ctrl[16].addr[1] = 147; |
1135 | Tuner->Init_Ctrl[16].val[1] = 1; | 983 | state->Init_Ctrl[16].bit[1] = 1; |
1136 | 984 | state->Init_Ctrl[16].val[1] = 1; | |
1137 | Tuner->Init_Ctrl[17].Ctrl_Num = EN_AAF ; | 985 | |
1138 | Tuner->Init_Ctrl[17].size = 1 ; | 986 | state->Init_Ctrl[17].Ctrl_Num = EN_AAF ; |
1139 | Tuner->Init_Ctrl[17].addr[0] = 147; | 987 | state->Init_Ctrl[17].size = 1 ; |
1140 | Tuner->Init_Ctrl[17].bit[0] = 7; | 988 | state->Init_Ctrl[17].addr[0] = 147; |
1141 | Tuner->Init_Ctrl[17].val[0] = 0; | 989 | state->Init_Ctrl[17].bit[0] = 7; |
1142 | 990 | state->Init_Ctrl[17].val[0] = 0; | |
1143 | Tuner->Init_Ctrl[18].Ctrl_Num = EN_3P ; | 991 | |
1144 | Tuner->Init_Ctrl[18].size = 1 ; | 992 | state->Init_Ctrl[18].Ctrl_Num = EN_3P ; |
1145 | Tuner->Init_Ctrl[18].addr[0] = 147; | 993 | state->Init_Ctrl[18].size = 1 ; |
1146 | Tuner->Init_Ctrl[18].bit[0] = 6; | 994 | state->Init_Ctrl[18].addr[0] = 147; |
1147 | Tuner->Init_Ctrl[18].val[0] = 0; | 995 | state->Init_Ctrl[18].bit[0] = 6; |
1148 | 996 | state->Init_Ctrl[18].val[0] = 0; | |
1149 | Tuner->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ; | 997 | |
1150 | Tuner->Init_Ctrl[19].size = 1 ; | 998 | state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ; |
1151 | Tuner->Init_Ctrl[19].addr[0] = 156; | 999 | state->Init_Ctrl[19].size = 1 ; |
1152 | Tuner->Init_Ctrl[19].bit[0] = 0; | 1000 | state->Init_Ctrl[19].addr[0] = 156; |
1153 | Tuner->Init_Ctrl[19].val[0] = 0; | 1001 | state->Init_Ctrl[19].bit[0] = 0; |
1154 | 1002 | state->Init_Ctrl[19].val[0] = 0; | |
1155 | Tuner->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ; | 1003 | |
1156 | Tuner->Init_Ctrl[20].size = 1 ; | 1004 | state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ; |
1157 | Tuner->Init_Ctrl[20].addr[0] = 147; | 1005 | state->Init_Ctrl[20].size = 1 ; |
1158 | Tuner->Init_Ctrl[20].bit[0] = 5; | 1006 | state->Init_Ctrl[20].addr[0] = 147; |
1159 | Tuner->Init_Ctrl[20].val[0] = 0; | 1007 | state->Init_Ctrl[20].bit[0] = 5; |
1160 | 1008 | state->Init_Ctrl[20].val[0] = 0; | |
1161 | Tuner->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ; | 1009 | |
1162 | Tuner->Init_Ctrl[21].size = 1 ; | 1010 | state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ; |
1163 | Tuner->Init_Ctrl[21].addr[0] = 137; | 1011 | state->Init_Ctrl[21].size = 1 ; |
1164 | Tuner->Init_Ctrl[21].bit[0] = 4; | 1012 | state->Init_Ctrl[21].addr[0] = 137; |
1165 | Tuner->Init_Ctrl[21].val[0] = 0; | 1013 | state->Init_Ctrl[21].bit[0] = 4; |
1166 | 1014 | state->Init_Ctrl[21].val[0] = 0; | |
1167 | Tuner->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ; | 1015 | |
1168 | Tuner->Init_Ctrl[22].size = 1 ; | 1016 | state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ; |
1169 | Tuner->Init_Ctrl[22].addr[0] = 137; | 1017 | state->Init_Ctrl[22].size = 1 ; |
1170 | Tuner->Init_Ctrl[22].bit[0] = 7; | 1018 | state->Init_Ctrl[22].addr[0] = 137; |
1171 | Tuner->Init_Ctrl[22].val[0] = 0; | 1019 | state->Init_Ctrl[22].bit[0] = 7; |
1172 | 1020 | state->Init_Ctrl[22].val[0] = 0; | |
1173 | Tuner->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ; | 1021 | |
1174 | Tuner->Init_Ctrl[23].size = 1 ; | 1022 | state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ; |
1175 | Tuner->Init_Ctrl[23].addr[0] = 91; | 1023 | state->Init_Ctrl[23].size = 1 ; |
1176 | Tuner->Init_Ctrl[23].bit[0] = 5; | 1024 | state->Init_Ctrl[23].addr[0] = 91; |
1177 | Tuner->Init_Ctrl[23].val[0] = 1; | 1025 | state->Init_Ctrl[23].bit[0] = 5; |
1178 | 1026 | state->Init_Ctrl[23].val[0] = 1; | |
1179 | Tuner->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ; | 1027 | |
1180 | Tuner->Init_Ctrl[24].size = 1 ; | 1028 | state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ; |
1181 | Tuner->Init_Ctrl[24].addr[0] = 43; | 1029 | state->Init_Ctrl[24].size = 1 ; |
1182 | Tuner->Init_Ctrl[24].bit[0] = 0; | 1030 | state->Init_Ctrl[24].addr[0] = 43; |
1183 | Tuner->Init_Ctrl[24].val[0] = 1; | 1031 | state->Init_Ctrl[24].bit[0] = 0; |
1184 | 1032 | state->Init_Ctrl[24].val[0] = 1; | |
1185 | Tuner->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ; | 1033 | |
1186 | Tuner->Init_Ctrl[25].size = 2 ; | 1034 | state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ; |
1187 | Tuner->Init_Ctrl[25].addr[0] = 22; | 1035 | state->Init_Ctrl[25].size = 2 ; |
1188 | Tuner->Init_Ctrl[25].bit[0] = 0; | 1036 | state->Init_Ctrl[25].addr[0] = 22; |
1189 | Tuner->Init_Ctrl[25].val[0] = 1; | 1037 | state->Init_Ctrl[25].bit[0] = 0; |
1190 | Tuner->Init_Ctrl[25].addr[1] = 22; | 1038 | state->Init_Ctrl[25].val[0] = 1; |
1191 | Tuner->Init_Ctrl[25].bit[1] = 1; | 1039 | state->Init_Ctrl[25].addr[1] = 22; |
1192 | Tuner->Init_Ctrl[25].val[1] = 1; | 1040 | state->Init_Ctrl[25].bit[1] = 1; |
1193 | 1041 | state->Init_Ctrl[25].val[1] = 1; | |
1194 | Tuner->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ; | 1042 | |
1195 | Tuner->Init_Ctrl[26].size = 1 ; | 1043 | state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ; |
1196 | Tuner->Init_Ctrl[26].addr[0] = 134; | 1044 | state->Init_Ctrl[26].size = 1 ; |
1197 | Tuner->Init_Ctrl[26].bit[0] = 2; | 1045 | state->Init_Ctrl[26].addr[0] = 134; |
1198 | Tuner->Init_Ctrl[26].val[0] = 0; | 1046 | state->Init_Ctrl[26].bit[0] = 2; |
1199 | 1047 | state->Init_Ctrl[26].val[0] = 0; | |
1200 | Tuner->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ; | 1048 | |
1201 | Tuner->Init_Ctrl[27].size = 1 ; | 1049 | state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ; |
1202 | Tuner->Init_Ctrl[27].addr[0] = 137; | 1050 | state->Init_Ctrl[27].size = 1 ; |
1203 | Tuner->Init_Ctrl[27].bit[0] = 3; | 1051 | state->Init_Ctrl[27].addr[0] = 137; |
1204 | Tuner->Init_Ctrl[27].val[0] = 0; | 1052 | state->Init_Ctrl[27].bit[0] = 3; |
1205 | 1053 | state->Init_Ctrl[27].val[0] = 0; | |
1206 | Tuner->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ; | 1054 | |
1207 | Tuner->Init_Ctrl[28].size = 1 ; | 1055 | state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ; |
1208 | Tuner->Init_Ctrl[28].addr[0] = 77; | 1056 | state->Init_Ctrl[28].size = 1 ; |
1209 | Tuner->Init_Ctrl[28].bit[0] = 7; | 1057 | state->Init_Ctrl[28].addr[0] = 77; |
1210 | Tuner->Init_Ctrl[28].val[0] = 0; | 1058 | state->Init_Ctrl[28].bit[0] = 7; |
1211 | 1059 | state->Init_Ctrl[28].val[0] = 0; | |
1212 | Tuner->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ; | 1060 | |
1213 | Tuner->Init_Ctrl[29].size = 1 ; | 1061 | state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ; |
1214 | Tuner->Init_Ctrl[29].addr[0] = 166; | 1062 | state->Init_Ctrl[29].size = 1 ; |
1215 | Tuner->Init_Ctrl[29].bit[0] = 7; | 1063 | state->Init_Ctrl[29].addr[0] = 166; |
1216 | Tuner->Init_Ctrl[29].val[0] = 1; | 1064 | state->Init_Ctrl[29].bit[0] = 7; |
1217 | 1065 | state->Init_Ctrl[29].val[0] = 1; | |
1218 | Tuner->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ; | 1066 | |
1219 | Tuner->Init_Ctrl[30].size = 3 ; | 1067 | state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ; |
1220 | Tuner->Init_Ctrl[30].addr[0] = 166; | 1068 | state->Init_Ctrl[30].size = 3 ; |
1221 | Tuner->Init_Ctrl[30].bit[0] = 0; | 1069 | state->Init_Ctrl[30].addr[0] = 166; |
1222 | Tuner->Init_Ctrl[30].val[0] = 0; | 1070 | state->Init_Ctrl[30].bit[0] = 0; |
1223 | Tuner->Init_Ctrl[30].addr[1] = 166; | 1071 | state->Init_Ctrl[30].val[0] = 0; |
1224 | Tuner->Init_Ctrl[30].bit[1] = 1; | 1072 | state->Init_Ctrl[30].addr[1] = 166; |
1225 | Tuner->Init_Ctrl[30].val[1] = 1; | 1073 | state->Init_Ctrl[30].bit[1] = 1; |
1226 | Tuner->Init_Ctrl[30].addr[2] = 166; | 1074 | state->Init_Ctrl[30].val[1] = 1; |
1227 | Tuner->Init_Ctrl[30].bit[2] = 2; | 1075 | state->Init_Ctrl[30].addr[2] = 166; |
1228 | Tuner->Init_Ctrl[30].val[2] = 1; | 1076 | state->Init_Ctrl[30].bit[2] = 2; |
1229 | 1077 | state->Init_Ctrl[30].val[2] = 1; | |
1230 | Tuner->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ; | 1078 | |
1231 | Tuner->Init_Ctrl[31].size = 3 ; | 1079 | state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ; |
1232 | Tuner->Init_Ctrl[31].addr[0] = 166; | 1080 | state->Init_Ctrl[31].size = 3 ; |
1233 | Tuner->Init_Ctrl[31].bit[0] = 3; | 1081 | state->Init_Ctrl[31].addr[0] = 166; |
1234 | Tuner->Init_Ctrl[31].val[0] = 1; | 1082 | state->Init_Ctrl[31].bit[0] = 3; |
1235 | Tuner->Init_Ctrl[31].addr[1] = 166; | 1083 | state->Init_Ctrl[31].val[0] = 1; |
1236 | Tuner->Init_Ctrl[31].bit[1] = 4; | 1084 | state->Init_Ctrl[31].addr[1] = 166; |
1237 | Tuner->Init_Ctrl[31].val[1] = 0; | 1085 | state->Init_Ctrl[31].bit[1] = 4; |
1238 | Tuner->Init_Ctrl[31].addr[2] = 166; | 1086 | state->Init_Ctrl[31].val[1] = 0; |
1239 | Tuner->Init_Ctrl[31].bit[2] = 5; | 1087 | state->Init_Ctrl[31].addr[2] = 166; |
1240 | Tuner->Init_Ctrl[31].val[2] = 1; | 1088 | state->Init_Ctrl[31].bit[2] = 5; |
1241 | 1089 | state->Init_Ctrl[31].val[2] = 1; | |
1242 | Tuner->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ; | 1090 | |
1243 | Tuner->Init_Ctrl[32].size = 3 ; | 1091 | state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ; |
1244 | Tuner->Init_Ctrl[32].addr[0] = 167; | 1092 | state->Init_Ctrl[32].size = 3 ; |
1245 | Tuner->Init_Ctrl[32].bit[0] = 0; | 1093 | state->Init_Ctrl[32].addr[0] = 167; |
1246 | Tuner->Init_Ctrl[32].val[0] = 1; | 1094 | state->Init_Ctrl[32].bit[0] = 0; |
1247 | Tuner->Init_Ctrl[32].addr[1] = 167; | 1095 | state->Init_Ctrl[32].val[0] = 1; |
1248 | Tuner->Init_Ctrl[32].bit[1] = 1; | 1096 | state->Init_Ctrl[32].addr[1] = 167; |
1249 | Tuner->Init_Ctrl[32].val[1] = 1; | 1097 | state->Init_Ctrl[32].bit[1] = 1; |
1250 | Tuner->Init_Ctrl[32].addr[2] = 167; | 1098 | state->Init_Ctrl[32].val[1] = 1; |
1251 | Tuner->Init_Ctrl[32].bit[2] = 2; | 1099 | state->Init_Ctrl[32].addr[2] = 167; |
1252 | Tuner->Init_Ctrl[32].val[2] = 0; | 1100 | state->Init_Ctrl[32].bit[2] = 2; |
1253 | 1101 | state->Init_Ctrl[32].val[2] = 0; | |
1254 | Tuner->Init_Ctrl[33].Ctrl_Num = RFA_FLR ; | 1102 | |
1255 | Tuner->Init_Ctrl[33].size = 4 ; | 1103 | state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ; |
1256 | Tuner->Init_Ctrl[33].addr[0] = 168; | 1104 | state->Init_Ctrl[33].size = 4 ; |
1257 | Tuner->Init_Ctrl[33].bit[0] = 0; | 1105 | state->Init_Ctrl[33].addr[0] = 168; |
1258 | Tuner->Init_Ctrl[33].val[0] = 0; | 1106 | state->Init_Ctrl[33].bit[0] = 0; |
1259 | Tuner->Init_Ctrl[33].addr[1] = 168; | 1107 | state->Init_Ctrl[33].val[0] = 0; |
1260 | Tuner->Init_Ctrl[33].bit[1] = 1; | 1108 | state->Init_Ctrl[33].addr[1] = 168; |
1261 | Tuner->Init_Ctrl[33].val[1] = 1; | 1109 | state->Init_Ctrl[33].bit[1] = 1; |
1262 | Tuner->Init_Ctrl[33].addr[2] = 168; | 1110 | state->Init_Ctrl[33].val[1] = 1; |
1263 | Tuner->Init_Ctrl[33].bit[2] = 2; | 1111 | state->Init_Ctrl[33].addr[2] = 168; |
1264 | Tuner->Init_Ctrl[33].val[2] = 0; | 1112 | state->Init_Ctrl[33].bit[2] = 2; |
1265 | Tuner->Init_Ctrl[33].addr[3] = 168; | 1113 | state->Init_Ctrl[33].val[2] = 0; |
1266 | Tuner->Init_Ctrl[33].bit[3] = 3; | 1114 | state->Init_Ctrl[33].addr[3] = 168; |
1267 | Tuner->Init_Ctrl[33].val[3] = 0; | 1115 | state->Init_Ctrl[33].bit[3] = 3; |
1268 | 1116 | state->Init_Ctrl[33].val[3] = 0; | |
1269 | Tuner->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ; | 1117 | |
1270 | Tuner->Init_Ctrl[34].size = 4 ; | 1118 | state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ; |
1271 | Tuner->Init_Ctrl[34].addr[0] = 168; | 1119 | state->Init_Ctrl[34].size = 4 ; |
1272 | Tuner->Init_Ctrl[34].bit[0] = 4; | 1120 | state->Init_Ctrl[34].addr[0] = 168; |
1273 | Tuner->Init_Ctrl[34].val[0] = 1; | 1121 | state->Init_Ctrl[34].bit[0] = 4; |
1274 | Tuner->Init_Ctrl[34].addr[1] = 168; | 1122 | state->Init_Ctrl[34].val[0] = 1; |
1275 | Tuner->Init_Ctrl[34].bit[1] = 5; | 1123 | state->Init_Ctrl[34].addr[1] = 168; |
1276 | Tuner->Init_Ctrl[34].val[1] = 1; | 1124 | state->Init_Ctrl[34].bit[1] = 5; |
1277 | Tuner->Init_Ctrl[34].addr[2] = 168; | 1125 | state->Init_Ctrl[34].val[1] = 1; |
1278 | Tuner->Init_Ctrl[34].bit[2] = 6; | 1126 | state->Init_Ctrl[34].addr[2] = 168; |
1279 | Tuner->Init_Ctrl[34].val[2] = 1; | 1127 | state->Init_Ctrl[34].bit[2] = 6; |
1280 | Tuner->Init_Ctrl[34].addr[3] = 168; | 1128 | state->Init_Ctrl[34].val[2] = 1; |
1281 | Tuner->Init_Ctrl[34].bit[3] = 7; | 1129 | state->Init_Ctrl[34].addr[3] = 168; |
1282 | Tuner->Init_Ctrl[34].val[3] = 1; | 1130 | state->Init_Ctrl[34].bit[3] = 7; |
1283 | 1131 | state->Init_Ctrl[34].val[3] = 1; | |
1284 | Tuner->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ; | 1132 | |
1285 | Tuner->Init_Ctrl[35].size = 1 ; | 1133 | state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ; |
1286 | Tuner->Init_Ctrl[35].addr[0] = 135; | 1134 | state->Init_Ctrl[35].size = 1 ; |
1287 | Tuner->Init_Ctrl[35].bit[0] = 0; | 1135 | state->Init_Ctrl[35].addr[0] = 135; |
1288 | Tuner->Init_Ctrl[35].val[0] = 0; | 1136 | state->Init_Ctrl[35].bit[0] = 0; |
1289 | 1137 | state->Init_Ctrl[35].val[0] = 0; | |
1290 | Tuner->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ; | 1138 | |
1291 | Tuner->Init_Ctrl[36].size = 1 ; | 1139 | state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ; |
1292 | Tuner->Init_Ctrl[36].addr[0] = 56; | 1140 | state->Init_Ctrl[36].size = 1 ; |
1293 | Tuner->Init_Ctrl[36].bit[0] = 3; | 1141 | state->Init_Ctrl[36].addr[0] = 56; |
1294 | Tuner->Init_Ctrl[36].val[0] = 0; | 1142 | state->Init_Ctrl[36].bit[0] = 3; |
1295 | 1143 | state->Init_Ctrl[36].val[0] = 0; | |
1296 | Tuner->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ; | 1144 | |
1297 | Tuner->Init_Ctrl[37].size = 7 ; | 1145 | state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ; |
1298 | Tuner->Init_Ctrl[37].addr[0] = 59; | 1146 | state->Init_Ctrl[37].size = 7 ; |
1299 | Tuner->Init_Ctrl[37].bit[0] = 1; | 1147 | state->Init_Ctrl[37].addr[0] = 59; |
1300 | Tuner->Init_Ctrl[37].val[0] = 0; | 1148 | state->Init_Ctrl[37].bit[0] = 1; |
1301 | Tuner->Init_Ctrl[37].addr[1] = 59; | 1149 | state->Init_Ctrl[37].val[0] = 0; |
1302 | Tuner->Init_Ctrl[37].bit[1] = 2; | 1150 | state->Init_Ctrl[37].addr[1] = 59; |
1303 | Tuner->Init_Ctrl[37].val[1] = 0; | 1151 | state->Init_Ctrl[37].bit[1] = 2; |
1304 | Tuner->Init_Ctrl[37].addr[2] = 59; | 1152 | state->Init_Ctrl[37].val[1] = 0; |
1305 | Tuner->Init_Ctrl[37].bit[2] = 3; | 1153 | state->Init_Ctrl[37].addr[2] = 59; |
1306 | Tuner->Init_Ctrl[37].val[2] = 0; | 1154 | state->Init_Ctrl[37].bit[2] = 3; |
1307 | Tuner->Init_Ctrl[37].addr[3] = 59; | 1155 | state->Init_Ctrl[37].val[2] = 0; |
1308 | Tuner->Init_Ctrl[37].bit[3] = 4; | 1156 | state->Init_Ctrl[37].addr[3] = 59; |
1309 | Tuner->Init_Ctrl[37].val[3] = 0; | 1157 | state->Init_Ctrl[37].bit[3] = 4; |
1310 | Tuner->Init_Ctrl[37].addr[4] = 59; | 1158 | state->Init_Ctrl[37].val[3] = 0; |
1311 | Tuner->Init_Ctrl[37].bit[4] = 5; | 1159 | state->Init_Ctrl[37].addr[4] = 59; |
1312 | Tuner->Init_Ctrl[37].val[4] = 0; | 1160 | state->Init_Ctrl[37].bit[4] = 5; |
1313 | Tuner->Init_Ctrl[37].addr[5] = 59; | 1161 | state->Init_Ctrl[37].val[4] = 0; |
1314 | Tuner->Init_Ctrl[37].bit[5] = 6; | 1162 | state->Init_Ctrl[37].addr[5] = 59; |
1315 | Tuner->Init_Ctrl[37].val[5] = 0; | 1163 | state->Init_Ctrl[37].bit[5] = 6; |
1316 | Tuner->Init_Ctrl[37].addr[6] = 59; | 1164 | state->Init_Ctrl[37].val[5] = 0; |
1317 | Tuner->Init_Ctrl[37].bit[6] = 7; | 1165 | state->Init_Ctrl[37].addr[6] = 59; |
1318 | Tuner->Init_Ctrl[37].val[6] = 0; | 1166 | state->Init_Ctrl[37].bit[6] = 7; |
1319 | 1167 | state->Init_Ctrl[37].val[6] = 0; | |
1320 | Tuner->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ; | 1168 | |
1321 | Tuner->Init_Ctrl[38].size = 6 ; | 1169 | state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ; |
1322 | Tuner->Init_Ctrl[38].addr[0] = 32; | 1170 | state->Init_Ctrl[38].size = 6 ; |
1323 | Tuner->Init_Ctrl[38].bit[0] = 2; | 1171 | state->Init_Ctrl[38].addr[0] = 32; |
1324 | Tuner->Init_Ctrl[38].val[0] = 0; | 1172 | state->Init_Ctrl[38].bit[0] = 2; |
1325 | Tuner->Init_Ctrl[38].addr[1] = 32; | 1173 | state->Init_Ctrl[38].val[0] = 0; |
1326 | Tuner->Init_Ctrl[38].bit[1] = 3; | 1174 | state->Init_Ctrl[38].addr[1] = 32; |
1327 | Tuner->Init_Ctrl[38].val[1] = 0; | 1175 | state->Init_Ctrl[38].bit[1] = 3; |
1328 | Tuner->Init_Ctrl[38].addr[2] = 32; | 1176 | state->Init_Ctrl[38].val[1] = 0; |
1329 | Tuner->Init_Ctrl[38].bit[2] = 4; | 1177 | state->Init_Ctrl[38].addr[2] = 32; |
1330 | Tuner->Init_Ctrl[38].val[2] = 0; | 1178 | state->Init_Ctrl[38].bit[2] = 4; |
1331 | Tuner->Init_Ctrl[38].addr[3] = 32; | 1179 | state->Init_Ctrl[38].val[2] = 0; |
1332 | Tuner->Init_Ctrl[38].bit[3] = 5; | 1180 | state->Init_Ctrl[38].addr[3] = 32; |
1333 | Tuner->Init_Ctrl[38].val[3] = 0; | 1181 | state->Init_Ctrl[38].bit[3] = 5; |
1334 | Tuner->Init_Ctrl[38].addr[4] = 32; | 1182 | state->Init_Ctrl[38].val[3] = 0; |
1335 | Tuner->Init_Ctrl[38].bit[4] = 6; | 1183 | state->Init_Ctrl[38].addr[4] = 32; |
1336 | Tuner->Init_Ctrl[38].val[4] = 1; | 1184 | state->Init_Ctrl[38].bit[4] = 6; |
1337 | Tuner->Init_Ctrl[38].addr[5] = 32; | 1185 | state->Init_Ctrl[38].val[4] = 1; |
1338 | Tuner->Init_Ctrl[38].bit[5] = 7; | 1186 | state->Init_Ctrl[38].addr[5] = 32; |
1339 | Tuner->Init_Ctrl[38].val[5] = 0; | 1187 | state->Init_Ctrl[38].bit[5] = 7; |
1340 | 1188 | state->Init_Ctrl[38].val[5] = 0; | |
1341 | Tuner->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ; | 1189 | |
1342 | Tuner->Init_Ctrl[39].size = 1 ; | 1190 | state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ; |
1343 | Tuner->Init_Ctrl[39].addr[0] = 25; | 1191 | state->Init_Ctrl[39].size = 1 ; |
1344 | Tuner->Init_Ctrl[39].bit[0] = 3; | 1192 | state->Init_Ctrl[39].addr[0] = 25; |
1345 | Tuner->Init_Ctrl[39].val[0] = 1; | 1193 | state->Init_Ctrl[39].bit[0] = 3; |
1346 | 1194 | state->Init_Ctrl[39].val[0] = 1; | |
1347 | 1195 | ||
1348 | Tuner->CH_Ctrl_Num = CHCTRL_NUM ; | 1196 | |
1349 | 1197 | state->CH_Ctrl_Num = CHCTRL_NUM ; | |
1350 | Tuner->CH_Ctrl[0].Ctrl_Num = DN_POLY ; | 1198 | |
1351 | Tuner->CH_Ctrl[0].size = 2 ; | 1199 | state->CH_Ctrl[0].Ctrl_Num = DN_POLY ; |
1352 | Tuner->CH_Ctrl[0].addr[0] = 68; | 1200 | state->CH_Ctrl[0].size = 2 ; |
1353 | Tuner->CH_Ctrl[0].bit[0] = 6; | 1201 | state->CH_Ctrl[0].addr[0] = 68; |
1354 | Tuner->CH_Ctrl[0].val[0] = 1; | 1202 | state->CH_Ctrl[0].bit[0] = 6; |
1355 | Tuner->CH_Ctrl[0].addr[1] = 68; | 1203 | state->CH_Ctrl[0].val[0] = 1; |
1356 | Tuner->CH_Ctrl[0].bit[1] = 7; | 1204 | state->CH_Ctrl[0].addr[1] = 68; |
1357 | Tuner->CH_Ctrl[0].val[1] = 1; | 1205 | state->CH_Ctrl[0].bit[1] = 7; |
1358 | 1206 | state->CH_Ctrl[0].val[1] = 1; | |
1359 | Tuner->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ; | 1207 | |
1360 | Tuner->CH_Ctrl[1].size = 2 ; | 1208 | state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ; |
1361 | Tuner->CH_Ctrl[1].addr[0] = 70; | 1209 | state->CH_Ctrl[1].size = 2 ; |
1362 | Tuner->CH_Ctrl[1].bit[0] = 6; | 1210 | state->CH_Ctrl[1].addr[0] = 70; |
1363 | Tuner->CH_Ctrl[1].val[0] = 1; | 1211 | state->CH_Ctrl[1].bit[0] = 6; |
1364 | Tuner->CH_Ctrl[1].addr[1] = 70; | 1212 | state->CH_Ctrl[1].val[0] = 1; |
1365 | Tuner->CH_Ctrl[1].bit[1] = 7; | 1213 | state->CH_Ctrl[1].addr[1] = 70; |
1366 | Tuner->CH_Ctrl[1].val[1] = 0; | 1214 | state->CH_Ctrl[1].bit[1] = 7; |
1367 | 1215 | state->CH_Ctrl[1].val[1] = 0; | |
1368 | Tuner->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ; | 1216 | |
1369 | Tuner->CH_Ctrl[2].size = 9 ; | 1217 | state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ; |
1370 | Tuner->CH_Ctrl[2].addr[0] = 69; | 1218 | state->CH_Ctrl[2].size = 9 ; |
1371 | Tuner->CH_Ctrl[2].bit[0] = 5; | 1219 | state->CH_Ctrl[2].addr[0] = 69; |
1372 | Tuner->CH_Ctrl[2].val[0] = 0; | 1220 | state->CH_Ctrl[2].bit[0] = 5; |
1373 | Tuner->CH_Ctrl[2].addr[1] = 69; | 1221 | state->CH_Ctrl[2].val[0] = 0; |
1374 | Tuner->CH_Ctrl[2].bit[1] = 6; | 1222 | state->CH_Ctrl[2].addr[1] = 69; |
1375 | Tuner->CH_Ctrl[2].val[1] = 0; | 1223 | state->CH_Ctrl[2].bit[1] = 6; |
1376 | Tuner->CH_Ctrl[2].addr[2] = 69; | 1224 | state->CH_Ctrl[2].val[1] = 0; |
1377 | Tuner->CH_Ctrl[2].bit[2] = 7; | 1225 | state->CH_Ctrl[2].addr[2] = 69; |
1378 | Tuner->CH_Ctrl[2].val[2] = 0; | 1226 | state->CH_Ctrl[2].bit[2] = 7; |
1379 | Tuner->CH_Ctrl[2].addr[3] = 68; | 1227 | state->CH_Ctrl[2].val[2] = 0; |
1380 | Tuner->CH_Ctrl[2].bit[3] = 0; | 1228 | state->CH_Ctrl[2].addr[3] = 68; |
1381 | Tuner->CH_Ctrl[2].val[3] = 0; | 1229 | state->CH_Ctrl[2].bit[3] = 0; |
1382 | Tuner->CH_Ctrl[2].addr[4] = 68; | 1230 | state->CH_Ctrl[2].val[3] = 0; |
1383 | Tuner->CH_Ctrl[2].bit[4] = 1; | 1231 | state->CH_Ctrl[2].addr[4] = 68; |
1384 | Tuner->CH_Ctrl[2].val[4] = 0; | 1232 | state->CH_Ctrl[2].bit[4] = 1; |
1385 | Tuner->CH_Ctrl[2].addr[5] = 68; | 1233 | state->CH_Ctrl[2].val[4] = 0; |
1386 | Tuner->CH_Ctrl[2].bit[5] = 2; | 1234 | state->CH_Ctrl[2].addr[5] = 68; |
1387 | Tuner->CH_Ctrl[2].val[5] = 0; | 1235 | state->CH_Ctrl[2].bit[5] = 2; |
1388 | Tuner->CH_Ctrl[2].addr[6] = 68; | 1236 | state->CH_Ctrl[2].val[5] = 0; |
1389 | Tuner->CH_Ctrl[2].bit[6] = 3; | 1237 | state->CH_Ctrl[2].addr[6] = 68; |
1390 | Tuner->CH_Ctrl[2].val[6] = 0; | 1238 | state->CH_Ctrl[2].bit[6] = 3; |
1391 | Tuner->CH_Ctrl[2].addr[7] = 68; | 1239 | state->CH_Ctrl[2].val[6] = 0; |
1392 | Tuner->CH_Ctrl[2].bit[7] = 4; | 1240 | state->CH_Ctrl[2].addr[7] = 68; |
1393 | Tuner->CH_Ctrl[2].val[7] = 0; | 1241 | state->CH_Ctrl[2].bit[7] = 4; |
1394 | Tuner->CH_Ctrl[2].addr[8] = 68; | 1242 | state->CH_Ctrl[2].val[7] = 0; |
1395 | Tuner->CH_Ctrl[2].bit[8] = 5; | 1243 | state->CH_Ctrl[2].addr[8] = 68; |
1396 | Tuner->CH_Ctrl[2].val[8] = 0; | 1244 | state->CH_Ctrl[2].bit[8] = 5; |
1397 | 1245 | state->CH_Ctrl[2].val[8] = 0; | |
1398 | Tuner->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ; | 1246 | |
1399 | Tuner->CH_Ctrl[3].size = 1 ; | 1247 | state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ; |
1400 | Tuner->CH_Ctrl[3].addr[0] = 70; | 1248 | state->CH_Ctrl[3].size = 1 ; |
1401 | Tuner->CH_Ctrl[3].bit[0] = 5; | 1249 | state->CH_Ctrl[3].addr[0] = 70; |
1402 | Tuner->CH_Ctrl[3].val[0] = 0; | 1250 | state->CH_Ctrl[3].bit[0] = 5; |
1403 | 1251 | state->CH_Ctrl[3].val[0] = 0; | |
1404 | Tuner->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ; | 1252 | |
1405 | Tuner->CH_Ctrl[4].size = 3 ; | 1253 | state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ; |
1406 | Tuner->CH_Ctrl[4].addr[0] = 73; | 1254 | state->CH_Ctrl[4].size = 3 ; |
1407 | Tuner->CH_Ctrl[4].bit[0] = 4; | 1255 | state->CH_Ctrl[4].addr[0] = 73; |
1408 | Tuner->CH_Ctrl[4].val[0] = 0; | 1256 | state->CH_Ctrl[4].bit[0] = 4; |
1409 | Tuner->CH_Ctrl[4].addr[1] = 73; | 1257 | state->CH_Ctrl[4].val[0] = 0; |
1410 | Tuner->CH_Ctrl[4].bit[1] = 5; | 1258 | state->CH_Ctrl[4].addr[1] = 73; |
1411 | Tuner->CH_Ctrl[4].val[1] = 1; | 1259 | state->CH_Ctrl[4].bit[1] = 5; |
1412 | Tuner->CH_Ctrl[4].addr[2] = 73; | 1260 | state->CH_Ctrl[4].val[1] = 1; |
1413 | Tuner->CH_Ctrl[4].bit[2] = 6; | 1261 | state->CH_Ctrl[4].addr[2] = 73; |
1414 | Tuner->CH_Ctrl[4].val[2] = 0; | 1262 | state->CH_Ctrl[4].bit[2] = 6; |
1415 | 1263 | state->CH_Ctrl[4].val[2] = 0; | |
1416 | Tuner->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ; | 1264 | |
1417 | Tuner->CH_Ctrl[5].size = 4 ; | 1265 | state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ; |
1418 | Tuner->CH_Ctrl[5].addr[0] = 70; | 1266 | state->CH_Ctrl[5].size = 4 ; |
1419 | Tuner->CH_Ctrl[5].bit[0] = 0; | 1267 | state->CH_Ctrl[5].addr[0] = 70; |
1420 | Tuner->CH_Ctrl[5].val[0] = 0; | 1268 | state->CH_Ctrl[5].bit[0] = 0; |
1421 | Tuner->CH_Ctrl[5].addr[1] = 70; | 1269 | state->CH_Ctrl[5].val[0] = 0; |
1422 | Tuner->CH_Ctrl[5].bit[1] = 1; | 1270 | state->CH_Ctrl[5].addr[1] = 70; |
1423 | Tuner->CH_Ctrl[5].val[1] = 0; | 1271 | state->CH_Ctrl[5].bit[1] = 1; |
1424 | Tuner->CH_Ctrl[5].addr[2] = 70; | 1272 | state->CH_Ctrl[5].val[1] = 0; |
1425 | Tuner->CH_Ctrl[5].bit[2] = 2; | 1273 | state->CH_Ctrl[5].addr[2] = 70; |
1426 | Tuner->CH_Ctrl[5].val[2] = 0; | 1274 | state->CH_Ctrl[5].bit[2] = 2; |
1427 | Tuner->CH_Ctrl[5].addr[3] = 70; | 1275 | state->CH_Ctrl[5].val[2] = 0; |
1428 | Tuner->CH_Ctrl[5].bit[3] = 3; | 1276 | state->CH_Ctrl[5].addr[3] = 70; |
1429 | Tuner->CH_Ctrl[5].val[3] = 0; | 1277 | state->CH_Ctrl[5].bit[3] = 3; |
1430 | 1278 | state->CH_Ctrl[5].val[3] = 0; | |
1431 | Tuner->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ; | 1279 | |
1432 | Tuner->CH_Ctrl[6].size = 1 ; | 1280 | state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ; |
1433 | Tuner->CH_Ctrl[6].addr[0] = 70; | 1281 | state->CH_Ctrl[6].size = 1 ; |
1434 | Tuner->CH_Ctrl[6].bit[0] = 4; | 1282 | state->CH_Ctrl[6].addr[0] = 70; |
1435 | Tuner->CH_Ctrl[6].val[0] = 1; | 1283 | state->CH_Ctrl[6].bit[0] = 4; |
1436 | 1284 | state->CH_Ctrl[6].val[0] = 1; | |
1437 | Tuner->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ; | 1285 | |
1438 | Tuner->CH_Ctrl[7].size = 1 ; | 1286 | state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ; |
1439 | Tuner->CH_Ctrl[7].addr[0] = 111; | 1287 | state->CH_Ctrl[7].size = 1 ; |
1440 | Tuner->CH_Ctrl[7].bit[0] = 4; | 1288 | state->CH_Ctrl[7].addr[0] = 111; |
1441 | Tuner->CH_Ctrl[7].val[0] = 0; | 1289 | state->CH_Ctrl[7].bit[0] = 4; |
1442 | 1290 | state->CH_Ctrl[7].val[0] = 0; | |
1443 | Tuner->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ; | 1291 | |
1444 | Tuner->CH_Ctrl[8].size = 1 ; | 1292 | state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ; |
1445 | Tuner->CH_Ctrl[8].addr[0] = 111; | 1293 | state->CH_Ctrl[8].size = 1 ; |
1446 | Tuner->CH_Ctrl[8].bit[0] = 7; | 1294 | state->CH_Ctrl[8].addr[0] = 111; |
1447 | Tuner->CH_Ctrl[8].val[0] = 1; | 1295 | state->CH_Ctrl[8].bit[0] = 7; |
1448 | 1296 | state->CH_Ctrl[8].val[0] = 1; | |
1449 | Tuner->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ; | 1297 | |
1450 | Tuner->CH_Ctrl[9].size = 1 ; | 1298 | state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ; |
1451 | Tuner->CH_Ctrl[9].addr[0] = 111; | 1299 | state->CH_Ctrl[9].size = 1 ; |
1452 | Tuner->CH_Ctrl[9].bit[0] = 6; | 1300 | state->CH_Ctrl[9].addr[0] = 111; |
1453 | Tuner->CH_Ctrl[9].val[0] = 1; | 1301 | state->CH_Ctrl[9].bit[0] = 6; |
1454 | 1302 | state->CH_Ctrl[9].val[0] = 1; | |
1455 | Tuner->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ; | 1303 | |
1456 | Tuner->CH_Ctrl[10].size = 1 ; | 1304 | state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ; |
1457 | Tuner->CH_Ctrl[10].addr[0] = 111; | 1305 | state->CH_Ctrl[10].size = 1 ; |
1458 | Tuner->CH_Ctrl[10].bit[0] = 5; | 1306 | state->CH_Ctrl[10].addr[0] = 111; |
1459 | Tuner->CH_Ctrl[10].val[0] = 0; | 1307 | state->CH_Ctrl[10].bit[0] = 5; |
1460 | 1308 | state->CH_Ctrl[10].val[0] = 0; | |
1461 | Tuner->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ; | 1309 | |
1462 | Tuner->CH_Ctrl[11].size = 2 ; | 1310 | state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ; |
1463 | Tuner->CH_Ctrl[11].addr[0] = 110; | 1311 | state->CH_Ctrl[11].size = 2 ; |
1464 | Tuner->CH_Ctrl[11].bit[0] = 0; | 1312 | state->CH_Ctrl[11].addr[0] = 110; |
1465 | Tuner->CH_Ctrl[11].val[0] = 1; | 1313 | state->CH_Ctrl[11].bit[0] = 0; |
1466 | Tuner->CH_Ctrl[11].addr[1] = 110; | 1314 | state->CH_Ctrl[11].val[0] = 1; |
1467 | Tuner->CH_Ctrl[11].bit[1] = 1; | 1315 | state->CH_Ctrl[11].addr[1] = 110; |
1468 | Tuner->CH_Ctrl[11].val[1] = 0; | 1316 | state->CH_Ctrl[11].bit[1] = 1; |
1469 | 1317 | state->CH_Ctrl[11].val[1] = 0; | |
1470 | Tuner->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ; | 1318 | |
1471 | Tuner->CH_Ctrl[12].size = 3 ; | 1319 | state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ; |
1472 | Tuner->CH_Ctrl[12].addr[0] = 69; | 1320 | state->CH_Ctrl[12].size = 3 ; |
1473 | Tuner->CH_Ctrl[12].bit[0] = 2; | 1321 | state->CH_Ctrl[12].addr[0] = 69; |
1474 | Tuner->CH_Ctrl[12].val[0] = 0; | 1322 | state->CH_Ctrl[12].bit[0] = 2; |
1475 | Tuner->CH_Ctrl[12].addr[1] = 69; | 1323 | state->CH_Ctrl[12].val[0] = 0; |
1476 | Tuner->CH_Ctrl[12].bit[1] = 3; | 1324 | state->CH_Ctrl[12].addr[1] = 69; |
1477 | Tuner->CH_Ctrl[12].val[1] = 0; | 1325 | state->CH_Ctrl[12].bit[1] = 3; |
1478 | Tuner->CH_Ctrl[12].addr[2] = 69; | 1326 | state->CH_Ctrl[12].val[1] = 0; |
1479 | Tuner->CH_Ctrl[12].bit[2] = 4; | 1327 | state->CH_Ctrl[12].addr[2] = 69; |
1480 | Tuner->CH_Ctrl[12].val[2] = 0; | 1328 | state->CH_Ctrl[12].bit[2] = 4; |
1481 | 1329 | state->CH_Ctrl[12].val[2] = 0; | |
1482 | Tuner->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ; | 1330 | |
1483 | Tuner->CH_Ctrl[13].size = 6 ; | 1331 | state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ; |
1484 | Tuner->CH_Ctrl[13].addr[0] = 110; | 1332 | state->CH_Ctrl[13].size = 6 ; |
1485 | Tuner->CH_Ctrl[13].bit[0] = 2; | 1333 | state->CH_Ctrl[13].addr[0] = 110; |
1486 | Tuner->CH_Ctrl[13].val[0] = 0; | 1334 | state->CH_Ctrl[13].bit[0] = 2; |
1487 | Tuner->CH_Ctrl[13].addr[1] = 110; | 1335 | state->CH_Ctrl[13].val[0] = 0; |
1488 | Tuner->CH_Ctrl[13].bit[1] = 3; | 1336 | state->CH_Ctrl[13].addr[1] = 110; |
1489 | Tuner->CH_Ctrl[13].val[1] = 0; | 1337 | state->CH_Ctrl[13].bit[1] = 3; |
1490 | Tuner->CH_Ctrl[13].addr[2] = 110; | 1338 | state->CH_Ctrl[13].val[1] = 0; |
1491 | Tuner->CH_Ctrl[13].bit[2] = 4; | 1339 | state->CH_Ctrl[13].addr[2] = 110; |
1492 | Tuner->CH_Ctrl[13].val[2] = 0; | 1340 | state->CH_Ctrl[13].bit[2] = 4; |
1493 | Tuner->CH_Ctrl[13].addr[3] = 110; | 1341 | state->CH_Ctrl[13].val[2] = 0; |
1494 | Tuner->CH_Ctrl[13].bit[3] = 5; | 1342 | state->CH_Ctrl[13].addr[3] = 110; |
1495 | Tuner->CH_Ctrl[13].val[3] = 0; | 1343 | state->CH_Ctrl[13].bit[3] = 5; |
1496 | Tuner->CH_Ctrl[13].addr[4] = 110; | 1344 | state->CH_Ctrl[13].val[3] = 0; |
1497 | Tuner->CH_Ctrl[13].bit[4] = 6; | 1345 | state->CH_Ctrl[13].addr[4] = 110; |
1498 | Tuner->CH_Ctrl[13].val[4] = 0; | 1346 | state->CH_Ctrl[13].bit[4] = 6; |
1499 | Tuner->CH_Ctrl[13].addr[5] = 110; | 1347 | state->CH_Ctrl[13].val[4] = 0; |
1500 | Tuner->CH_Ctrl[13].bit[5] = 7; | 1348 | state->CH_Ctrl[13].addr[5] = 110; |
1501 | Tuner->CH_Ctrl[13].val[5] = 1; | 1349 | state->CH_Ctrl[13].bit[5] = 7; |
1502 | 1350 | state->CH_Ctrl[13].val[5] = 1; | |
1503 | Tuner->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ; | 1351 | |
1504 | Tuner->CH_Ctrl[14].size = 7 ; | 1352 | state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ; |
1505 | Tuner->CH_Ctrl[14].addr[0] = 14; | 1353 | state->CH_Ctrl[14].size = 7 ; |
1506 | Tuner->CH_Ctrl[14].bit[0] = 0; | 1354 | state->CH_Ctrl[14].addr[0] = 14; |
1507 | Tuner->CH_Ctrl[14].val[0] = 0; | 1355 | state->CH_Ctrl[14].bit[0] = 0; |
1508 | Tuner->CH_Ctrl[14].addr[1] = 14; | 1356 | state->CH_Ctrl[14].val[0] = 0; |
1509 | Tuner->CH_Ctrl[14].bit[1] = 1; | 1357 | state->CH_Ctrl[14].addr[1] = 14; |
1510 | Tuner->CH_Ctrl[14].val[1] = 0; | 1358 | state->CH_Ctrl[14].bit[1] = 1; |
1511 | Tuner->CH_Ctrl[14].addr[2] = 14; | 1359 | state->CH_Ctrl[14].val[1] = 0; |
1512 | Tuner->CH_Ctrl[14].bit[2] = 2; | 1360 | state->CH_Ctrl[14].addr[2] = 14; |
1513 | Tuner->CH_Ctrl[14].val[2] = 0; | 1361 | state->CH_Ctrl[14].bit[2] = 2; |
1514 | Tuner->CH_Ctrl[14].addr[3] = 14; | 1362 | state->CH_Ctrl[14].val[2] = 0; |
1515 | Tuner->CH_Ctrl[14].bit[3] = 3; | 1363 | state->CH_Ctrl[14].addr[3] = 14; |
1516 | Tuner->CH_Ctrl[14].val[3] = 0; | 1364 | state->CH_Ctrl[14].bit[3] = 3; |
1517 | Tuner->CH_Ctrl[14].addr[4] = 14; | 1365 | state->CH_Ctrl[14].val[3] = 0; |
1518 | Tuner->CH_Ctrl[14].bit[4] = 4; | 1366 | state->CH_Ctrl[14].addr[4] = 14; |
1519 | Tuner->CH_Ctrl[14].val[4] = 0; | 1367 | state->CH_Ctrl[14].bit[4] = 4; |
1520 | Tuner->CH_Ctrl[14].addr[5] = 14; | 1368 | state->CH_Ctrl[14].val[4] = 0; |
1521 | Tuner->CH_Ctrl[14].bit[5] = 5; | 1369 | state->CH_Ctrl[14].addr[5] = 14; |
1522 | Tuner->CH_Ctrl[14].val[5] = 0; | 1370 | state->CH_Ctrl[14].bit[5] = 5; |
1523 | Tuner->CH_Ctrl[14].addr[6] = 14; | 1371 | state->CH_Ctrl[14].val[5] = 0; |
1524 | Tuner->CH_Ctrl[14].bit[6] = 6; | 1372 | state->CH_Ctrl[14].addr[6] = 14; |
1525 | Tuner->CH_Ctrl[14].val[6] = 0; | 1373 | state->CH_Ctrl[14].bit[6] = 6; |
1526 | 1374 | state->CH_Ctrl[14].val[6] = 0; | |
1527 | Tuner->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ; | 1375 | |
1528 | Tuner->CH_Ctrl[15].size = 18 ; | 1376 | state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ; |
1529 | Tuner->CH_Ctrl[15].addr[0] = 17; | 1377 | state->CH_Ctrl[15].size = 18 ; |
1530 | Tuner->CH_Ctrl[15].bit[0] = 6; | 1378 | state->CH_Ctrl[15].addr[0] = 17; |
1531 | Tuner->CH_Ctrl[15].val[0] = 0; | 1379 | state->CH_Ctrl[15].bit[0] = 6; |
1532 | Tuner->CH_Ctrl[15].addr[1] = 17; | 1380 | state->CH_Ctrl[15].val[0] = 0; |
1533 | Tuner->CH_Ctrl[15].bit[1] = 7; | 1381 | state->CH_Ctrl[15].addr[1] = 17; |
1534 | Tuner->CH_Ctrl[15].val[1] = 0; | 1382 | state->CH_Ctrl[15].bit[1] = 7; |
1535 | Tuner->CH_Ctrl[15].addr[2] = 16; | 1383 | state->CH_Ctrl[15].val[1] = 0; |
1536 | Tuner->CH_Ctrl[15].bit[2] = 0; | 1384 | state->CH_Ctrl[15].addr[2] = 16; |
1537 | Tuner->CH_Ctrl[15].val[2] = 0; | 1385 | state->CH_Ctrl[15].bit[2] = 0; |
1538 | Tuner->CH_Ctrl[15].addr[3] = 16; | 1386 | state->CH_Ctrl[15].val[2] = 0; |
1539 | Tuner->CH_Ctrl[15].bit[3] = 1; | 1387 | state->CH_Ctrl[15].addr[3] = 16; |
1540 | Tuner->CH_Ctrl[15].val[3] = 0; | 1388 | state->CH_Ctrl[15].bit[3] = 1; |
1541 | Tuner->CH_Ctrl[15].addr[4] = 16; | 1389 | state->CH_Ctrl[15].val[3] = 0; |
1542 | Tuner->CH_Ctrl[15].bit[4] = 2; | 1390 | state->CH_Ctrl[15].addr[4] = 16; |
1543 | Tuner->CH_Ctrl[15].val[4] = 0; | 1391 | state->CH_Ctrl[15].bit[4] = 2; |
1544 | Tuner->CH_Ctrl[15].addr[5] = 16; | 1392 | state->CH_Ctrl[15].val[4] = 0; |
1545 | Tuner->CH_Ctrl[15].bit[5] = 3; | 1393 | state->CH_Ctrl[15].addr[5] = 16; |
1546 | Tuner->CH_Ctrl[15].val[5] = 0; | 1394 | state->CH_Ctrl[15].bit[5] = 3; |
1547 | Tuner->CH_Ctrl[15].addr[6] = 16; | 1395 | state->CH_Ctrl[15].val[5] = 0; |
1548 | Tuner->CH_Ctrl[15].bit[6] = 4; | 1396 | state->CH_Ctrl[15].addr[6] = 16; |
1549 | Tuner->CH_Ctrl[15].val[6] = 0; | 1397 | state->CH_Ctrl[15].bit[6] = 4; |
1550 | Tuner->CH_Ctrl[15].addr[7] = 16; | 1398 | state->CH_Ctrl[15].val[6] = 0; |
1551 | Tuner->CH_Ctrl[15].bit[7] = 5; | 1399 | state->CH_Ctrl[15].addr[7] = 16; |
1552 | Tuner->CH_Ctrl[15].val[7] = 0; | 1400 | state->CH_Ctrl[15].bit[7] = 5; |
1553 | Tuner->CH_Ctrl[15].addr[8] = 16; | 1401 | state->CH_Ctrl[15].val[7] = 0; |
1554 | Tuner->CH_Ctrl[15].bit[8] = 6; | 1402 | state->CH_Ctrl[15].addr[8] = 16; |
1555 | Tuner->CH_Ctrl[15].val[8] = 0; | 1403 | state->CH_Ctrl[15].bit[8] = 6; |
1556 | Tuner->CH_Ctrl[15].addr[9] = 16; | 1404 | state->CH_Ctrl[15].val[8] = 0; |
1557 | Tuner->CH_Ctrl[15].bit[9] = 7; | 1405 | state->CH_Ctrl[15].addr[9] = 16; |
1558 | Tuner->CH_Ctrl[15].val[9] = 0; | 1406 | state->CH_Ctrl[15].bit[9] = 7; |
1559 | Tuner->CH_Ctrl[15].addr[10] = 15; | 1407 | state->CH_Ctrl[15].val[9] = 0; |
1560 | Tuner->CH_Ctrl[15].bit[10] = 0; | 1408 | state->CH_Ctrl[15].addr[10] = 15; |
1561 | Tuner->CH_Ctrl[15].val[10] = 0; | 1409 | state->CH_Ctrl[15].bit[10] = 0; |
1562 | Tuner->CH_Ctrl[15].addr[11] = 15; | 1410 | state->CH_Ctrl[15].val[10] = 0; |
1563 | Tuner->CH_Ctrl[15].bit[11] = 1; | 1411 | state->CH_Ctrl[15].addr[11] = 15; |
1564 | Tuner->CH_Ctrl[15].val[11] = 0; | 1412 | state->CH_Ctrl[15].bit[11] = 1; |
1565 | Tuner->CH_Ctrl[15].addr[12] = 15; | 1413 | state->CH_Ctrl[15].val[11] = 0; |
1566 | Tuner->CH_Ctrl[15].bit[12] = 2; | 1414 | state->CH_Ctrl[15].addr[12] = 15; |
1567 | Tuner->CH_Ctrl[15].val[12] = 0; | 1415 | state->CH_Ctrl[15].bit[12] = 2; |
1568 | Tuner->CH_Ctrl[15].addr[13] = 15; | 1416 | state->CH_Ctrl[15].val[12] = 0; |
1569 | Tuner->CH_Ctrl[15].bit[13] = 3; | 1417 | state->CH_Ctrl[15].addr[13] = 15; |
1570 | Tuner->CH_Ctrl[15].val[13] = 0; | 1418 | state->CH_Ctrl[15].bit[13] = 3; |
1571 | Tuner->CH_Ctrl[15].addr[14] = 15; | 1419 | state->CH_Ctrl[15].val[13] = 0; |
1572 | Tuner->CH_Ctrl[15].bit[14] = 4; | 1420 | state->CH_Ctrl[15].addr[14] = 15; |
1573 | Tuner->CH_Ctrl[15].val[14] = 0; | 1421 | state->CH_Ctrl[15].bit[14] = 4; |
1574 | Tuner->CH_Ctrl[15].addr[15] = 15; | 1422 | state->CH_Ctrl[15].val[14] = 0; |
1575 | Tuner->CH_Ctrl[15].bit[15] = 5; | 1423 | state->CH_Ctrl[15].addr[15] = 15; |
1576 | Tuner->CH_Ctrl[15].val[15] = 0; | 1424 | state->CH_Ctrl[15].bit[15] = 5; |
1577 | Tuner->CH_Ctrl[15].addr[16] = 15; | 1425 | state->CH_Ctrl[15].val[15] = 0; |
1578 | Tuner->CH_Ctrl[15].bit[16] = 6; | 1426 | state->CH_Ctrl[15].addr[16] = 15; |
1579 | Tuner->CH_Ctrl[15].val[16] = 1; | 1427 | state->CH_Ctrl[15].bit[16] = 6; |
1580 | Tuner->CH_Ctrl[15].addr[17] = 15; | 1428 | state->CH_Ctrl[15].val[16] = 1; |
1581 | Tuner->CH_Ctrl[15].bit[17] = 7; | 1429 | state->CH_Ctrl[15].addr[17] = 15; |
1582 | Tuner->CH_Ctrl[15].val[17] = 1; | 1430 | state->CH_Ctrl[15].bit[17] = 7; |
1583 | 1431 | state->CH_Ctrl[15].val[17] = 1; | |
1584 | Tuner->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ; | 1432 | |
1585 | Tuner->CH_Ctrl[16].size = 5 ; | 1433 | state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ; |
1586 | Tuner->CH_Ctrl[16].addr[0] = 112; | 1434 | state->CH_Ctrl[16].size = 5 ; |
1587 | Tuner->CH_Ctrl[16].bit[0] = 0; | 1435 | state->CH_Ctrl[16].addr[0] = 112; |
1588 | Tuner->CH_Ctrl[16].val[0] = 0; | 1436 | state->CH_Ctrl[16].bit[0] = 0; |
1589 | Tuner->CH_Ctrl[16].addr[1] = 112; | 1437 | state->CH_Ctrl[16].val[0] = 0; |
1590 | Tuner->CH_Ctrl[16].bit[1] = 1; | 1438 | state->CH_Ctrl[16].addr[1] = 112; |
1591 | Tuner->CH_Ctrl[16].val[1] = 0; | 1439 | state->CH_Ctrl[16].bit[1] = 1; |
1592 | Tuner->CH_Ctrl[16].addr[2] = 112; | 1440 | state->CH_Ctrl[16].val[1] = 0; |
1593 | Tuner->CH_Ctrl[16].bit[2] = 2; | 1441 | state->CH_Ctrl[16].addr[2] = 112; |
1594 | Tuner->CH_Ctrl[16].val[2] = 0; | 1442 | state->CH_Ctrl[16].bit[2] = 2; |
1595 | Tuner->CH_Ctrl[16].addr[3] = 112; | 1443 | state->CH_Ctrl[16].val[2] = 0; |
1596 | Tuner->CH_Ctrl[16].bit[3] = 3; | 1444 | state->CH_Ctrl[16].addr[3] = 112; |
1597 | Tuner->CH_Ctrl[16].val[3] = 0; | 1445 | state->CH_Ctrl[16].bit[3] = 3; |
1598 | Tuner->CH_Ctrl[16].addr[4] = 112; | 1446 | state->CH_Ctrl[16].val[3] = 0; |
1599 | Tuner->CH_Ctrl[16].bit[4] = 4; | 1447 | state->CH_Ctrl[16].addr[4] = 112; |
1600 | Tuner->CH_Ctrl[16].val[4] = 1; | 1448 | state->CH_Ctrl[16].bit[4] = 4; |
1601 | 1449 | state->CH_Ctrl[16].val[4] = 1; | |
1602 | Tuner->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ; | 1450 | |
1603 | Tuner->CH_Ctrl[17].size = 1 ; | 1451 | state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ; |
1604 | Tuner->CH_Ctrl[17].addr[0] = 14; | 1452 | state->CH_Ctrl[17].size = 1 ; |
1605 | Tuner->CH_Ctrl[17].bit[0] = 7; | 1453 | state->CH_Ctrl[17].addr[0] = 14; |
1606 | Tuner->CH_Ctrl[17].val[0] = 0; | 1454 | state->CH_Ctrl[17].bit[0] = 7; |
1607 | 1455 | state->CH_Ctrl[17].val[0] = 0; | |
1608 | Tuner->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ; | 1456 | |
1609 | Tuner->CH_Ctrl[18].size = 4 ; | 1457 | state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ; |
1610 | Tuner->CH_Ctrl[18].addr[0] = 107; | 1458 | state->CH_Ctrl[18].size = 4 ; |
1611 | Tuner->CH_Ctrl[18].bit[0] = 3; | 1459 | state->CH_Ctrl[18].addr[0] = 107; |
1612 | Tuner->CH_Ctrl[18].val[0] = 0; | 1460 | state->CH_Ctrl[18].bit[0] = 3; |
1613 | Tuner->CH_Ctrl[18].addr[1] = 107; | 1461 | state->CH_Ctrl[18].val[0] = 0; |
1614 | Tuner->CH_Ctrl[18].bit[1] = 4; | 1462 | state->CH_Ctrl[18].addr[1] = 107; |
1615 | Tuner->CH_Ctrl[18].val[1] = 0; | 1463 | state->CH_Ctrl[18].bit[1] = 4; |
1616 | Tuner->CH_Ctrl[18].addr[2] = 107; | 1464 | state->CH_Ctrl[18].val[1] = 0; |
1617 | Tuner->CH_Ctrl[18].bit[2] = 5; | 1465 | state->CH_Ctrl[18].addr[2] = 107; |
1618 | Tuner->CH_Ctrl[18].val[2] = 0; | 1466 | state->CH_Ctrl[18].bit[2] = 5; |
1619 | Tuner->CH_Ctrl[18].addr[3] = 107; | 1467 | state->CH_Ctrl[18].val[2] = 0; |
1620 | Tuner->CH_Ctrl[18].bit[3] = 6; | 1468 | state->CH_Ctrl[18].addr[3] = 107; |
1621 | Tuner->CH_Ctrl[18].val[3] = 0; | 1469 | state->CH_Ctrl[18].bit[3] = 6; |
1622 | 1470 | state->CH_Ctrl[18].val[3] = 0; | |
1623 | Tuner->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ; | 1471 | |
1624 | Tuner->CH_Ctrl[19].size = 3 ; | 1472 | state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ; |
1625 | Tuner->CH_Ctrl[19].addr[0] = 107; | 1473 | state->CH_Ctrl[19].size = 3 ; |
1626 | Tuner->CH_Ctrl[19].bit[0] = 7; | 1474 | state->CH_Ctrl[19].addr[0] = 107; |
1627 | Tuner->CH_Ctrl[19].val[0] = 1; | 1475 | state->CH_Ctrl[19].bit[0] = 7; |
1628 | Tuner->CH_Ctrl[19].addr[1] = 106; | 1476 | state->CH_Ctrl[19].val[0] = 1; |
1629 | Tuner->CH_Ctrl[19].bit[1] = 0; | 1477 | state->CH_Ctrl[19].addr[1] = 106; |
1630 | Tuner->CH_Ctrl[19].val[1] = 1; | 1478 | state->CH_Ctrl[19].bit[1] = 0; |
1631 | Tuner->CH_Ctrl[19].addr[2] = 106; | 1479 | state->CH_Ctrl[19].val[1] = 1; |
1632 | Tuner->CH_Ctrl[19].bit[2] = 1; | 1480 | state->CH_Ctrl[19].addr[2] = 106; |
1633 | Tuner->CH_Ctrl[19].val[2] = 1; | 1481 | state->CH_Ctrl[19].bit[2] = 1; |
1634 | 1482 | state->CH_Ctrl[19].val[2] = 1; | |
1635 | Tuner->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ; | 1483 | |
1636 | Tuner->CH_Ctrl[20].size = 11 ; | 1484 | state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ; |
1637 | Tuner->CH_Ctrl[20].addr[0] = 109; | 1485 | state->CH_Ctrl[20].size = 11 ; |
1638 | Tuner->CH_Ctrl[20].bit[0] = 2; | 1486 | state->CH_Ctrl[20].addr[0] = 109; |
1639 | Tuner->CH_Ctrl[20].val[0] = 0; | 1487 | state->CH_Ctrl[20].bit[0] = 2; |
1640 | Tuner->CH_Ctrl[20].addr[1] = 109; | 1488 | state->CH_Ctrl[20].val[0] = 0; |
1641 | Tuner->CH_Ctrl[20].bit[1] = 3; | 1489 | state->CH_Ctrl[20].addr[1] = 109; |
1642 | Tuner->CH_Ctrl[20].val[1] = 0; | 1490 | state->CH_Ctrl[20].bit[1] = 3; |
1643 | Tuner->CH_Ctrl[20].addr[2] = 109; | 1491 | state->CH_Ctrl[20].val[1] = 0; |
1644 | Tuner->CH_Ctrl[20].bit[2] = 4; | 1492 | state->CH_Ctrl[20].addr[2] = 109; |
1645 | Tuner->CH_Ctrl[20].val[2] = 0; | 1493 | state->CH_Ctrl[20].bit[2] = 4; |
1646 | Tuner->CH_Ctrl[20].addr[3] = 109; | 1494 | state->CH_Ctrl[20].val[2] = 0; |
1647 | Tuner->CH_Ctrl[20].bit[3] = 5; | 1495 | state->CH_Ctrl[20].addr[3] = 109; |
1648 | Tuner->CH_Ctrl[20].val[3] = 0; | 1496 | state->CH_Ctrl[20].bit[3] = 5; |
1649 | Tuner->CH_Ctrl[20].addr[4] = 109; | 1497 | state->CH_Ctrl[20].val[3] = 0; |
1650 | Tuner->CH_Ctrl[20].bit[4] = 6; | 1498 | state->CH_Ctrl[20].addr[4] = 109; |
1651 | Tuner->CH_Ctrl[20].val[4] = 0; | 1499 | state->CH_Ctrl[20].bit[4] = 6; |
1652 | Tuner->CH_Ctrl[20].addr[5] = 109; | 1500 | state->CH_Ctrl[20].val[4] = 0; |
1653 | Tuner->CH_Ctrl[20].bit[5] = 7; | 1501 | state->CH_Ctrl[20].addr[5] = 109; |
1654 | Tuner->CH_Ctrl[20].val[5] = 0; | 1502 | state->CH_Ctrl[20].bit[5] = 7; |
1655 | Tuner->CH_Ctrl[20].addr[6] = 108; | 1503 | state->CH_Ctrl[20].val[5] = 0; |
1656 | Tuner->CH_Ctrl[20].bit[6] = 0; | 1504 | state->CH_Ctrl[20].addr[6] = 108; |
1657 | Tuner->CH_Ctrl[20].val[6] = 0; | 1505 | state->CH_Ctrl[20].bit[6] = 0; |
1658 | Tuner->CH_Ctrl[20].addr[7] = 108; | 1506 | state->CH_Ctrl[20].val[6] = 0; |
1659 | Tuner->CH_Ctrl[20].bit[7] = 1; | 1507 | state->CH_Ctrl[20].addr[7] = 108; |
1660 | Tuner->CH_Ctrl[20].val[7] = 0; | 1508 | state->CH_Ctrl[20].bit[7] = 1; |
1661 | Tuner->CH_Ctrl[20].addr[8] = 108; | 1509 | state->CH_Ctrl[20].val[7] = 0; |
1662 | Tuner->CH_Ctrl[20].bit[8] = 2; | 1510 | state->CH_Ctrl[20].addr[8] = 108; |
1663 | Tuner->CH_Ctrl[20].val[8] = 1; | 1511 | state->CH_Ctrl[20].bit[8] = 2; |
1664 | Tuner->CH_Ctrl[20].addr[9] = 108; | 1512 | state->CH_Ctrl[20].val[8] = 1; |
1665 | Tuner->CH_Ctrl[20].bit[9] = 3; | 1513 | state->CH_Ctrl[20].addr[9] = 108; |
1666 | Tuner->CH_Ctrl[20].val[9] = 1; | 1514 | state->CH_Ctrl[20].bit[9] = 3; |
1667 | Tuner->CH_Ctrl[20].addr[10] = 108; | 1515 | state->CH_Ctrl[20].val[9] = 1; |
1668 | Tuner->CH_Ctrl[20].bit[10] = 4; | 1516 | state->CH_Ctrl[20].addr[10] = 108; |
1669 | Tuner->CH_Ctrl[20].val[10] = 1; | 1517 | state->CH_Ctrl[20].bit[10] = 4; |
1670 | 1518 | state->CH_Ctrl[20].val[10] = 1; | |
1671 | Tuner->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ; | 1519 | |
1672 | Tuner->CH_Ctrl[21].size = 6 ; | 1520 | state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ; |
1673 | Tuner->CH_Ctrl[21].addr[0] = 106; | 1521 | state->CH_Ctrl[21].size = 6 ; |
1674 | Tuner->CH_Ctrl[21].bit[0] = 2; | 1522 | state->CH_Ctrl[21].addr[0] = 106; |
1675 | Tuner->CH_Ctrl[21].val[0] = 0; | 1523 | state->CH_Ctrl[21].bit[0] = 2; |
1676 | Tuner->CH_Ctrl[21].addr[1] = 106; | 1524 | state->CH_Ctrl[21].val[0] = 0; |
1677 | Tuner->CH_Ctrl[21].bit[1] = 3; | 1525 | state->CH_Ctrl[21].addr[1] = 106; |
1678 | Tuner->CH_Ctrl[21].val[1] = 0; | 1526 | state->CH_Ctrl[21].bit[1] = 3; |
1679 | Tuner->CH_Ctrl[21].addr[2] = 106; | 1527 | state->CH_Ctrl[21].val[1] = 0; |
1680 | Tuner->CH_Ctrl[21].bit[2] = 4; | 1528 | state->CH_Ctrl[21].addr[2] = 106; |
1681 | Tuner->CH_Ctrl[21].val[2] = 0; | 1529 | state->CH_Ctrl[21].bit[2] = 4; |
1682 | Tuner->CH_Ctrl[21].addr[3] = 106; | 1530 | state->CH_Ctrl[21].val[2] = 0; |
1683 | Tuner->CH_Ctrl[21].bit[3] = 5; | 1531 | state->CH_Ctrl[21].addr[3] = 106; |
1684 | Tuner->CH_Ctrl[21].val[3] = 0; | 1532 | state->CH_Ctrl[21].bit[3] = 5; |
1685 | Tuner->CH_Ctrl[21].addr[4] = 106; | 1533 | state->CH_Ctrl[21].val[3] = 0; |
1686 | Tuner->CH_Ctrl[21].bit[4] = 6; | 1534 | state->CH_Ctrl[21].addr[4] = 106; |
1687 | Tuner->CH_Ctrl[21].val[4] = 0; | 1535 | state->CH_Ctrl[21].bit[4] = 6; |
1688 | Tuner->CH_Ctrl[21].addr[5] = 106; | 1536 | state->CH_Ctrl[21].val[4] = 0; |
1689 | Tuner->CH_Ctrl[21].bit[5] = 7; | 1537 | state->CH_Ctrl[21].addr[5] = 106; |
1690 | Tuner->CH_Ctrl[21].val[5] = 1; | 1538 | state->CH_Ctrl[21].bit[5] = 7; |
1691 | 1539 | state->CH_Ctrl[21].val[5] = 1; | |
1692 | Tuner->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ; | 1540 | |
1693 | Tuner->CH_Ctrl[22].size = 1 ; | 1541 | state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ; |
1694 | Tuner->CH_Ctrl[22].addr[0] = 138; | 1542 | state->CH_Ctrl[22].size = 1 ; |
1695 | Tuner->CH_Ctrl[22].bit[0] = 4; | 1543 | state->CH_Ctrl[22].addr[0] = 138; |
1696 | Tuner->CH_Ctrl[22].val[0] = 1; | 1544 | state->CH_Ctrl[22].bit[0] = 4; |
1697 | 1545 | state->CH_Ctrl[22].val[0] = 1; | |
1698 | Tuner->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ; | 1546 | |
1699 | Tuner->CH_Ctrl[23].size = 1 ; | 1547 | state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ; |
1700 | Tuner->CH_Ctrl[23].addr[0] = 17; | 1548 | state->CH_Ctrl[23].size = 1 ; |
1701 | Tuner->CH_Ctrl[23].bit[0] = 5; | 1549 | state->CH_Ctrl[23].addr[0] = 17; |
1702 | Tuner->CH_Ctrl[23].val[0] = 0; | 1550 | state->CH_Ctrl[23].bit[0] = 5; |
1703 | 1551 | state->CH_Ctrl[23].val[0] = 0; | |
1704 | Tuner->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ; | 1552 | |
1705 | Tuner->CH_Ctrl[24].size = 1 ; | 1553 | state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ; |
1706 | Tuner->CH_Ctrl[24].addr[0] = 111; | 1554 | state->CH_Ctrl[24].size = 1 ; |
1707 | Tuner->CH_Ctrl[24].bit[0] = 3; | 1555 | state->CH_Ctrl[24].addr[0] = 111; |
1708 | Tuner->CH_Ctrl[24].val[0] = 0; | 1556 | state->CH_Ctrl[24].bit[0] = 3; |
1709 | 1557 | state->CH_Ctrl[24].val[0] = 0; | |
1710 | Tuner->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ; | 1558 | |
1711 | Tuner->CH_Ctrl[25].size = 1 ; | 1559 | state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ; |
1712 | Tuner->CH_Ctrl[25].addr[0] = 112; | 1560 | state->CH_Ctrl[25].size = 1 ; |
1713 | Tuner->CH_Ctrl[25].bit[0] = 7; | 1561 | state->CH_Ctrl[25].addr[0] = 112; |
1714 | Tuner->CH_Ctrl[25].val[0] = 0; | 1562 | state->CH_Ctrl[25].bit[0] = 7; |
1715 | 1563 | state->CH_Ctrl[25].val[0] = 0; | |
1716 | Tuner->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ; | 1564 | |
1717 | Tuner->CH_Ctrl[26].size = 1 ; | 1565 | state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ; |
1718 | Tuner->CH_Ctrl[26].addr[0] = 136; | 1566 | state->CH_Ctrl[26].size = 1 ; |
1719 | Tuner->CH_Ctrl[26].bit[0] = 7; | 1567 | state->CH_Ctrl[26].addr[0] = 136; |
1720 | Tuner->CH_Ctrl[26].val[0] = 0; | 1568 | state->CH_Ctrl[26].bit[0] = 7; |
1721 | 1569 | state->CH_Ctrl[26].val[0] = 0; | |
1722 | Tuner->CH_Ctrl[27].Ctrl_Num = GPIO_4B ; | 1570 | |
1723 | Tuner->CH_Ctrl[27].size = 1 ; | 1571 | state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ; |
1724 | Tuner->CH_Ctrl[27].addr[0] = 149; | 1572 | state->CH_Ctrl[27].size = 1 ; |
1725 | Tuner->CH_Ctrl[27].bit[0] = 7; | 1573 | state->CH_Ctrl[27].addr[0] = 149; |
1726 | Tuner->CH_Ctrl[27].val[0] = 0; | 1574 | state->CH_Ctrl[27].bit[0] = 7; |
1727 | 1575 | state->CH_Ctrl[27].val[0] = 0; | |
1728 | Tuner->CH_Ctrl[28].Ctrl_Num = GPIO_3B ; | 1576 | |
1729 | Tuner->CH_Ctrl[28].size = 1 ; | 1577 | state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ; |
1730 | Tuner->CH_Ctrl[28].addr[0] = 149; | 1578 | state->CH_Ctrl[28].size = 1 ; |
1731 | Tuner->CH_Ctrl[28].bit[0] = 6; | 1579 | state->CH_Ctrl[28].addr[0] = 149; |
1732 | Tuner->CH_Ctrl[28].val[0] = 0; | 1580 | state->CH_Ctrl[28].bit[0] = 6; |
1733 | 1581 | state->CH_Ctrl[28].val[0] = 0; | |
1734 | Tuner->CH_Ctrl[29].Ctrl_Num = GPIO_4 ; | 1582 | |
1735 | Tuner->CH_Ctrl[29].size = 1 ; | 1583 | state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ; |
1736 | Tuner->CH_Ctrl[29].addr[0] = 149; | 1584 | state->CH_Ctrl[29].size = 1 ; |
1737 | Tuner->CH_Ctrl[29].bit[0] = 5; | 1585 | state->CH_Ctrl[29].addr[0] = 149; |
1738 | Tuner->CH_Ctrl[29].val[0] = 1; | 1586 | state->CH_Ctrl[29].bit[0] = 5; |
1739 | 1587 | state->CH_Ctrl[29].val[0] = 1; | |
1740 | Tuner->CH_Ctrl[30].Ctrl_Num = GPIO_3 ; | 1588 | |
1741 | Tuner->CH_Ctrl[30].size = 1 ; | 1589 | state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ; |
1742 | Tuner->CH_Ctrl[30].addr[0] = 149; | 1590 | state->CH_Ctrl[30].size = 1 ; |
1743 | Tuner->CH_Ctrl[30].bit[0] = 4; | 1591 | state->CH_Ctrl[30].addr[0] = 149; |
1744 | Tuner->CH_Ctrl[30].val[0] = 1; | 1592 | state->CH_Ctrl[30].bit[0] = 4; |
1745 | 1593 | state->CH_Ctrl[30].val[0] = 1; | |
1746 | Tuner->CH_Ctrl[31].Ctrl_Num = GPIO_1B ; | 1594 | |
1747 | Tuner->CH_Ctrl[31].size = 1 ; | 1595 | state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ; |
1748 | Tuner->CH_Ctrl[31].addr[0] = 149; | 1596 | state->CH_Ctrl[31].size = 1 ; |
1749 | Tuner->CH_Ctrl[31].bit[0] = 3; | 1597 | state->CH_Ctrl[31].addr[0] = 149; |
1750 | Tuner->CH_Ctrl[31].val[0] = 0; | 1598 | state->CH_Ctrl[31].bit[0] = 3; |
1751 | 1599 | state->CH_Ctrl[31].val[0] = 0; | |
1752 | Tuner->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ; | 1600 | |
1753 | Tuner->CH_Ctrl[32].size = 1 ; | 1601 | state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ; |
1754 | Tuner->CH_Ctrl[32].addr[0] = 93; | 1602 | state->CH_Ctrl[32].size = 1 ; |
1755 | Tuner->CH_Ctrl[32].bit[0] = 1; | 1603 | state->CH_Ctrl[32].addr[0] = 93; |
1756 | Tuner->CH_Ctrl[32].val[0] = 0; | 1604 | state->CH_Ctrl[32].bit[0] = 1; |
1757 | 1605 | state->CH_Ctrl[32].val[0] = 0; | |
1758 | Tuner->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ; | 1606 | |
1759 | Tuner->CH_Ctrl[33].size = 1 ; | 1607 | state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ; |
1760 | Tuner->CH_Ctrl[33].addr[0] = 93; | 1608 | state->CH_Ctrl[33].size = 1 ; |
1761 | Tuner->CH_Ctrl[33].bit[0] = 0; | 1609 | state->CH_Ctrl[33].addr[0] = 93; |
1762 | Tuner->CH_Ctrl[33].val[0] = 0; | 1610 | state->CH_Ctrl[33].bit[0] = 0; |
1763 | 1611 | state->CH_Ctrl[33].val[0] = 0; | |
1764 | Tuner->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ; | 1612 | |
1765 | Tuner->CH_Ctrl[34].size = 6 ; | 1613 | state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ; |
1766 | Tuner->CH_Ctrl[34].addr[0] = 92; | 1614 | state->CH_Ctrl[34].size = 6 ; |
1767 | Tuner->CH_Ctrl[34].bit[0] = 2; | 1615 | state->CH_Ctrl[34].addr[0] = 92; |
1768 | Tuner->CH_Ctrl[34].val[0] = 0; | 1616 | state->CH_Ctrl[34].bit[0] = 2; |
1769 | Tuner->CH_Ctrl[34].addr[1] = 92; | 1617 | state->CH_Ctrl[34].val[0] = 0; |
1770 | Tuner->CH_Ctrl[34].bit[1] = 3; | 1618 | state->CH_Ctrl[34].addr[1] = 92; |
1771 | Tuner->CH_Ctrl[34].val[1] = 0; | 1619 | state->CH_Ctrl[34].bit[1] = 3; |
1772 | Tuner->CH_Ctrl[34].addr[2] = 92; | 1620 | state->CH_Ctrl[34].val[1] = 0; |
1773 | Tuner->CH_Ctrl[34].bit[2] = 4; | 1621 | state->CH_Ctrl[34].addr[2] = 92; |
1774 | Tuner->CH_Ctrl[34].val[2] = 0; | 1622 | state->CH_Ctrl[34].bit[2] = 4; |
1775 | Tuner->CH_Ctrl[34].addr[3] = 92; | 1623 | state->CH_Ctrl[34].val[2] = 0; |
1776 | Tuner->CH_Ctrl[34].bit[3] = 5; | 1624 | state->CH_Ctrl[34].addr[3] = 92; |
1777 | Tuner->CH_Ctrl[34].val[3] = 0; | 1625 | state->CH_Ctrl[34].bit[3] = 5; |
1778 | Tuner->CH_Ctrl[34].addr[4] = 92; | 1626 | state->CH_Ctrl[34].val[3] = 0; |
1779 | Tuner->CH_Ctrl[34].bit[4] = 6; | 1627 | state->CH_Ctrl[34].addr[4] = 92; |
1780 | Tuner->CH_Ctrl[34].val[4] = 0; | 1628 | state->CH_Ctrl[34].bit[4] = 6; |
1781 | Tuner->CH_Ctrl[34].addr[5] = 92; | 1629 | state->CH_Ctrl[34].val[4] = 0; |
1782 | Tuner->CH_Ctrl[34].bit[5] = 7; | 1630 | state->CH_Ctrl[34].addr[5] = 92; |
1783 | Tuner->CH_Ctrl[34].val[5] = 0; | 1631 | state->CH_Ctrl[34].bit[5] = 7; |
1784 | 1632 | state->CH_Ctrl[34].val[5] = 0; | |
1785 | Tuner->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ; | 1633 | |
1786 | Tuner->CH_Ctrl[35].size = 6 ; | 1634 | state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ; |
1787 | Tuner->CH_Ctrl[35].addr[0] = 93; | 1635 | state->CH_Ctrl[35].size = 6 ; |
1788 | Tuner->CH_Ctrl[35].bit[0] = 2; | 1636 | state->CH_Ctrl[35].addr[0] = 93; |
1789 | Tuner->CH_Ctrl[35].val[0] = 0; | 1637 | state->CH_Ctrl[35].bit[0] = 2; |
1790 | Tuner->CH_Ctrl[35].addr[1] = 93; | 1638 | state->CH_Ctrl[35].val[0] = 0; |
1791 | Tuner->CH_Ctrl[35].bit[1] = 3; | 1639 | state->CH_Ctrl[35].addr[1] = 93; |
1792 | Tuner->CH_Ctrl[35].val[1] = 0; | 1640 | state->CH_Ctrl[35].bit[1] = 3; |
1793 | Tuner->CH_Ctrl[35].addr[2] = 93; | 1641 | state->CH_Ctrl[35].val[1] = 0; |
1794 | Tuner->CH_Ctrl[35].bit[2] = 4; | 1642 | state->CH_Ctrl[35].addr[2] = 93; |
1795 | Tuner->CH_Ctrl[35].val[2] = 0; | 1643 | state->CH_Ctrl[35].bit[2] = 4; |
1796 | Tuner->CH_Ctrl[35].addr[3] = 93; | 1644 | state->CH_Ctrl[35].val[2] = 0; |
1797 | Tuner->CH_Ctrl[35].bit[3] = 5; | 1645 | state->CH_Ctrl[35].addr[3] = 93; |
1798 | Tuner->CH_Ctrl[35].val[3] = 0; | 1646 | state->CH_Ctrl[35].bit[3] = 5; |
1799 | Tuner->CH_Ctrl[35].addr[4] = 93; | 1647 | state->CH_Ctrl[35].val[3] = 0; |
1800 | Tuner->CH_Ctrl[35].bit[4] = 6; | 1648 | state->CH_Ctrl[35].addr[4] = 93; |
1801 | Tuner->CH_Ctrl[35].val[4] = 0; | 1649 | state->CH_Ctrl[35].bit[4] = 6; |
1802 | Tuner->CH_Ctrl[35].addr[5] = 93; | 1650 | state->CH_Ctrl[35].val[4] = 0; |
1803 | Tuner->CH_Ctrl[35].bit[5] = 7; | 1651 | state->CH_Ctrl[35].addr[5] = 93; |
1804 | Tuner->CH_Ctrl[35].val[5] = 0; | 1652 | state->CH_Ctrl[35].bit[5] = 7; |
1653 | state->CH_Ctrl[35].val[5] = 0; | ||
1805 | 1654 | ||
1806 | #ifdef _MXL_PRODUCTION | 1655 | #ifdef _MXL_PRODUCTION |
1807 | Tuner->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ; | 1656 | state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ; |
1808 | Tuner->CH_Ctrl[36].size = 1 ; | 1657 | state->CH_Ctrl[36].size = 1 ; |
1809 | Tuner->CH_Ctrl[36].addr[0] = 109; | 1658 | state->CH_Ctrl[36].addr[0] = 109; |
1810 | Tuner->CH_Ctrl[36].bit[0] = 1; | 1659 | state->CH_Ctrl[36].bit[0] = 1; |
1811 | Tuner->CH_Ctrl[36].val[0] = 1; | 1660 | state->CH_Ctrl[36].val[0] = 1; |
1812 | 1661 | ||
1813 | Tuner->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ; | 1662 | state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ; |
1814 | Tuner->CH_Ctrl[37].size = 2 ; | 1663 | state->CH_Ctrl[37].size = 2 ; |
1815 | Tuner->CH_Ctrl[37].addr[0] = 112; | 1664 | state->CH_Ctrl[37].addr[0] = 112; |
1816 | Tuner->CH_Ctrl[37].bit[0] = 5; | 1665 | state->CH_Ctrl[37].bit[0] = 5; |
1817 | Tuner->CH_Ctrl[37].val[0] = 0; | 1666 | state->CH_Ctrl[37].val[0] = 0; |
1818 | Tuner->CH_Ctrl[37].addr[1] = 112; | 1667 | state->CH_Ctrl[37].addr[1] = 112; |
1819 | Tuner->CH_Ctrl[37].bit[1] = 6; | 1668 | state->CH_Ctrl[37].bit[1] = 6; |
1820 | Tuner->CH_Ctrl[37].val[1] = 0; | 1669 | state->CH_Ctrl[37].val[1] = 0; |
1821 | 1670 | ||
1822 | Tuner->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ; | 1671 | state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ; |
1823 | Tuner->CH_Ctrl[38].size = 1 ; | 1672 | state->CH_Ctrl[38].size = 1 ; |
1824 | Tuner->CH_Ctrl[38].addr[0] = 65; | 1673 | state->CH_Ctrl[38].addr[0] = 65; |
1825 | Tuner->CH_Ctrl[38].bit[0] = 1; | 1674 | state->CH_Ctrl[38].bit[0] = 1; |
1826 | Tuner->CH_Ctrl[38].val[0] = 0; | 1675 | state->CH_Ctrl[38].val[0] = 0; |
1827 | #endif | 1676 | #endif |
1828 | 1677 | ||
1829 | return 0 ; | 1678 | return 0 ; |
@@ -1832,13 +1681,14 @@ u16 MXL5005_ControlInit(Tuner_struct *Tuner) | |||
1832 | // MaxLinear source code - MXL5005_c.cpp | 1681 | // MaxLinear source code - MXL5005_c.cpp |
1833 | // MXL5005.cpp : Defines the initialization routines for the DLL. | 1682 | // MXL5005.cpp : Defines the initialization routines for the DLL. |
1834 | // 2.6.12 | 1683 | // 2.6.12 |
1835 | 1684 | // DONE | |
1836 | void InitTunerControls(Tuner_struct *Tuner) | 1685 | void InitTunerControls(struct dvb_frontend *fe) |
1837 | { | 1686 | { |
1838 | MXL5005_RegisterInit(Tuner) ; | 1687 | struct mxl5005s_state *state = fe->demodulator_priv; |
1839 | MXL5005_ControlInit(Tuner) ; | 1688 | MXL5005_RegisterInit(fe); |
1689 | MXL5005_ControlInit(fe); | ||
1840 | #ifdef _MXL_INTERNAL | 1690 | #ifdef _MXL_INTERNAL |
1841 | MXL5005_MXLControlInit(Tuner) ; | 1691 | MXL5005_MXLControlInit(fe); |
1842 | #endif | 1692 | #endif |
1843 | } | 1693 | } |
1844 | 1694 | ||
@@ -1857,15 +1707,15 @@ void InitTunerControls(Tuner_struct *Tuner) | |||
1857 | // Tuner_struct: structure defined at higher level // | 1707 | // Tuner_struct: structure defined at higher level // |
1858 | // Mode: Tuner Mode (Analog/Digital) // | 1708 | // Mode: Tuner Mode (Analog/Digital) // |
1859 | // IF_Mode: IF Mode ( Zero/Low ) // | 1709 | // IF_Mode: IF Mode ( Zero/Low ) // |
1860 | // Bandwidth: Filter Channel Bandwidth (in Hz) // | 1710 | // Bandwidth: Filter Channel Bandwidth (in Hz) // |
1861 | // IF_out: Desired IF out Frequency (in Hz) // | 1711 | // IF_out: Desired IF out Frequency (in Hz) // |
1862 | // Fxtal: Crystal Frerquency (in Hz) // | 1712 | // Fxtal: Crystal Frerquency (in Hz) // |
1863 | // TOP: 0: Dual AGC; Value: take over point // | 1713 | // TOP: 0: Dual AGC; Value: take over point // |
1864 | // IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // | 1714 | // IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // |
1865 | // CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // | 1715 | // CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // |
1866 | // DIV_OUT: 0: Div-1; 1: Div-4 // | 1716 | // DIV_OUT: 0: Div-1; 1: Div-4 // |
1867 | // CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // | 1717 | // CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // |
1868 | // EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // | 1718 | // EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // |
1869 | // // | 1719 | // // |
1870 | // Outputs: // | 1720 | // Outputs: // |
1871 | // Tuner // | 1721 | // Tuner // |
@@ -1875,49 +1725,51 @@ void InitTunerControls(Tuner_struct *Tuner) | |||
1875 | // > 0 : Failed // | 1725 | // > 0 : Failed // |
1876 | // // | 1726 | // // |
1877 | /////////////////////////////////////////////////////////////////////////////// | 1727 | /////////////////////////////////////////////////////////////////////////////// |
1878 | u16 MXL5005_TunerConfig(Tuner_struct *Tuner, | 1728 | // DONE |
1879 | u8 Mode, // 0: Analog Mode ; 1: Digital Mode | 1729 | u16 MXL5005_TunerConfig(struct dvb_frontend *fe, |
1880 | u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF | 1730 | u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ |
1881 | u32 Bandwidth, // filter channel bandwidth (6, 7, 8) | 1731 | u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ |
1882 | u32 IF_out, // Desired IF Out Frequency | 1732 | u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ |
1883 | u32 Fxtal, // XTAL Frequency | 1733 | u32 IF_out, /* Desired IF Out Frequency */ |
1884 | u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 | 1734 | u32 Fxtal, /* XTAL Frequency */ |
1885 | u16 TOP, // 0: Dual AGC; Value: take over point | 1735 | u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ |
1886 | u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms) | 1736 | u16 TOP, /* 0: Dual AGC; Value: take over point */ |
1887 | u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out | 1737 | u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ |
1888 | u8 DIV_OUT, // 0: Div-1; 1: Div-4 | 1738 | u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */ |
1889 | u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable | 1739 | u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */ |
1890 | u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI | 1740 | u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ |
1891 | u8 Mod_Type, // Modulation Type; | 1741 | u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ |
1892 | // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable | 1742 | u8 Mod_Type, /* Modulation Type; */ |
1893 | u8 TF_Type // Tracking Filter | 1743 | /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ |
1894 | // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H | 1744 | u8 TF_Type /* Tracking Filter */ |
1745 | /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ | ||
1895 | ) | 1746 | ) |
1896 | { | 1747 | { |
1897 | u16 status = 0 ; | 1748 | struct mxl5005s_state *state = fe->demodulator_priv; |
1749 | u16 status = 0; | ||
1898 | 1750 | ||
1899 | Tuner->Mode = Mode ; | 1751 | state->Mode = Mode; |
1900 | Tuner->IF_Mode = IF_mode ; | 1752 | state->IF_Mode = IF_mode; |
1901 | Tuner->Chan_Bandwidth = Bandwidth ; | 1753 | state->Chan_Bandwidth = Bandwidth; |
1902 | Tuner->IF_OUT = IF_out ; | 1754 | state->IF_OUT = IF_out; |
1903 | Tuner->Fxtal = Fxtal ; | 1755 | state->Fxtal = Fxtal; |
1904 | Tuner->AGC_Mode = AGC_Mode ; | 1756 | state->AGC_Mode = AGC_Mode; |
1905 | Tuner->TOP = TOP ; | 1757 | state->TOP = TOP; |
1906 | Tuner->IF_OUT_LOAD = IF_OUT_LOAD ; | 1758 | state->IF_OUT_LOAD = IF_OUT_LOAD; |
1907 | Tuner->CLOCK_OUT = CLOCK_OUT ; | 1759 | state->CLOCK_OUT = CLOCK_OUT; |
1908 | Tuner->DIV_OUT = DIV_OUT ; | 1760 | state->DIV_OUT = DIV_OUT; |
1909 | Tuner->CAPSELECT = CAPSELECT ; | 1761 | state->CAPSELECT = CAPSELECT; |
1910 | Tuner->EN_RSSI = EN_RSSI ; | 1762 | state->EN_RSSI = EN_RSSI; |
1911 | Tuner->Mod_Type = Mod_Type ; | 1763 | state->Mod_Type = Mod_Type; |
1912 | Tuner->TF_Type = TF_Type ; | 1764 | state->TF_Type = TF_Type; |
1913 | 1765 | ||
1914 | /* Initialize all the controls and registers */ | 1766 | /* Initialize all the controls and registers */ |
1915 | InitTunerControls (Tuner) ; | 1767 | InitTunerControls(fe); |
1916 | 1768 | ||
1917 | /* Synthesizer LO frequency calculation */ | 1769 | /* Synthesizer LO frequency calculation */ |
1918 | MXL_SynthIFLO_Calc( Tuner ) ; | 1770 | MXL_SynthIFLO_Calc(fe); |
1919 | 1771 | ||
1920 | return status ; | 1772 | return status; |
1921 | } | 1773 | } |
1922 | 1774 | ||
1923 | /////////////////////////////////////////////////////////////////////////////// | 1775 | /////////////////////////////////////////////////////////////////////////////// |
@@ -1943,22 +1795,18 @@ u16 MXL5005_TunerConfig(Tuner_struct *Tuner, | |||
1943 | // > 0 : Failed // | 1795 | // > 0 : Failed // |
1944 | // // | 1796 | // // |
1945 | /////////////////////////////////////////////////////////////////////////////// | 1797 | /////////////////////////////////////////////////////////////////////////////// |
1946 | void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) | 1798 | // DONE |
1799 | void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) | ||
1947 | { | 1800 | { |
1948 | if (Tuner->Mode == 1) // Digital Mode | 1801 | struct mxl5005s_state *state = fe->demodulator_priv; |
1949 | { | 1802 | if (Tuner->Mode == 1) /* Digital Mode */ |
1950 | Tuner->IF_LO = Tuner->IF_OUT ; | 1803 | state->IF_LO = state->IF_OUT; |
1951 | } | 1804 | else /* Analog Mode */ |
1952 | else // Analog Mode | ||
1953 | { | 1805 | { |
1954 | if(Tuner->IF_Mode == 0) // Analog Zero IF mode | 1806 | if(state->IF_Mode == 0) /* Analog Zero IF mode */ |
1955 | { | 1807 | state->IF_LO = state->IF_OUT + 400000; |
1956 | Tuner->IF_LO = Tuner->IF_OUT + 400000 ; | 1808 | else /* Analog Low IF mode */ |
1957 | } | 1809 | state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2; |
1958 | else // Analog Low IF mode | ||
1959 | { | ||
1960 | Tuner->IF_LO = Tuner->IF_OUT + Tuner->Chan_Bandwidth/2 ; | ||
1961 | } | ||
1962 | } | 1810 | } |
1963 | } | 1811 | } |
1964 | 1812 | ||
@@ -1986,25 +1834,22 @@ void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) | |||
1986 | // > 0 : Failed // | 1834 | // > 0 : Failed // |
1987 | // // | 1835 | // // |
1988 | /////////////////////////////////////////////////////////////////////////////// | 1836 | /////////////////////////////////////////////////////////////////////////////// |
1989 | void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) | 1837 | // DONE |
1838 | void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) | ||
1990 | { | 1839 | { |
1991 | if (Tuner->Mode == 1) // Digital Mode | 1840 | struct mxl5005s_state *state = fe->demodulator_priv; |
1992 | { | 1841 | |
1842 | if (state->Mode == 1) /* Digital Mode */ { | ||
1993 | //remove 20.48MHz setting for 2.6.10 | 1843 | //remove 20.48MHz setting for 2.6.10 |
1994 | Tuner->RF_LO = Tuner->RF_IN ; | 1844 | state->RF_LO = state->RF_IN; |
1995 | Tuner->TG_LO = Tuner->RF_IN - 750000 ; //change for 2.6.6 | 1845 | state->TG_LO = state->RF_IN - 750000; //change for 2.6.6 |
1996 | } | 1846 | } else /* Analog Mode */ { |
1997 | else // Analog Mode | 1847 | if(state->IF_Mode == 0) /* Analog Zero IF mode */ { |
1998 | { | 1848 | state->RF_LO = state->RF_IN - 400000; |
1999 | if(Tuner->IF_Mode == 0) // Analog Zero IF mode | 1849 | state->TG_LO = state->RF_IN - 1750000; |
2000 | { | 1850 | } else /* Analog Low IF mode */ { |
2001 | Tuner->RF_LO = Tuner->RF_IN - 400000 ; | 1851 | state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2; |
2002 | Tuner->TG_LO = Tuner->RF_IN - 1750000 ; | 1852 | state->TG_LO = state->RF_IN - state->Chan_Bandwidth + 500000; |
2003 | } | ||
2004 | else // Analog Low IF mode | ||
2005 | { | ||
2006 | Tuner->RF_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth/2 ; | ||
2007 | Tuner->TG_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth + 500000 ; | ||
2008 | } | 1853 | } |
2009 | } | 1854 | } |
2010 | } | 1855 | } |
@@ -2028,16 +1873,18 @@ void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) | |||
2028 | // > 0 : Failed // | 1873 | // > 0 : Failed // |
2029 | // // | 1874 | // // |
2030 | /////////////////////////////////////////////////////////////////////////////// | 1875 | /////////////////////////////////////////////////////////////////////////////// |
2031 | u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) | 1876 | // DONE |
1877 | u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) | ||
2032 | { | 1878 | { |
2033 | u16 status = 0 ; | 1879 | struct mxl5005s_state *state = fe->demodulator_priv; |
1880 | u16 status = 0; | ||
2034 | 1881 | ||
2035 | status += MXL_ControlWrite(Tuner, OVERRIDE_1, 1) ; | 1882 | status += MXL_ControlWrite(fe, OVERRIDE_1, 1); |
2036 | status += MXL_ControlWrite(Tuner, OVERRIDE_2, 1) ; | 1883 | status += MXL_ControlWrite(fe, OVERRIDE_2, 1); |
2037 | status += MXL_ControlWrite(Tuner, OVERRIDE_3, 1) ; | 1884 | status += MXL_ControlWrite(fe, OVERRIDE_3, 1); |
2038 | status += MXL_ControlWrite(Tuner, OVERRIDE_4, 1) ; | 1885 | status += MXL_ControlWrite(fe, OVERRIDE_4, 1); |
2039 | 1886 | ||
2040 | return status ; | 1887 | return status; |
2041 | } | 1888 | } |
2042 | 1889 | ||
2043 | /////////////////////////////////////////////////////////////////////////////// | 1890 | /////////////////////////////////////////////////////////////////////////////// |
@@ -2065,363 +1912,338 @@ u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) | |||
2065 | // > 0 : Failed // | 1912 | // > 0 : Failed // |
2066 | // // | 1913 | // // |
2067 | /////////////////////////////////////////////////////////////////////////////// | 1914 | /////////////////////////////////////////////////////////////////////////////// |
2068 | u16 MXL_BlockInit( Tuner_struct *Tuner ) | 1915 | // DONE |
1916 | u16 MXL_BlockInit(struct dvb_frontend *fe) | ||
2069 | { | 1917 | { |
2070 | u16 status = 0 ; | 1918 | struct mxl5005s_state *state = fe->demodulator_priv; |
1919 | u16 status = 0; | ||
2071 | 1920 | ||
2072 | status += MXL_OverwriteICDefault(Tuner) ; | 1921 | status += MXL_OverwriteICDefault(fe); |
2073 | 1922 | ||
2074 | // | 1923 | /* Downconverter Control Dig Ana */ |
2075 | // Downconverter Control | 1924 | status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0); |
2076 | // Dig Ana | ||
2077 | status += MXL_ControlWrite(Tuner, DN_IQTN_AMP_CUT, Tuner->Mode ? 1 : 0) ; | ||
2078 | 1925 | ||
2079 | // | 1926 | /* Filter Control Dig Ana */ |
2080 | // Filter Control | 1927 | status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1); |
2081 | // Dig Ana | 1928 | status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2); |
2082 | status += MXL_ControlWrite(Tuner, BB_MODE, Tuner->Mode ? 0 : 1) ; | 1929 | status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0); |
2083 | status += MXL_ControlWrite(Tuner, BB_BUF, Tuner->Mode ? 3 : 2) ; | 1930 | status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1); |
2084 | status += MXL_ControlWrite(Tuner, BB_BUF_OA, Tuner->Mode ? 1 : 0) ; | 1931 | status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 0); |
2085 | 1932 | ||
2086 | status += MXL_ControlWrite(Tuner, BB_IQSWAP, Tuner->Mode ? 0 : 1) ; | 1933 | /* Initialize Low-Pass Filter */ |
2087 | status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 0) ; | 1934 | if (state->Mode) { /* Digital Mode */ |
2088 | 1935 | switch (state->Chan_Bandwidth) { | |
2089 | // Initialize Low-Pass Filter | ||
2090 | if (Tuner->Mode) { // Digital Mode | ||
2091 | switch (Tuner->Chan_Bandwidth) { | ||
2092 | case 8000000: | 1936 | case 8000000: |
2093 | status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 0) ; | 1937 | status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0); |
2094 | break ; | 1938 | break; |
2095 | case 7000000: | 1939 | case 7000000: |
2096 | status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 2) ; | 1940 | status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); |
2097 | break ; | 1941 | break; |
2098 | case 6000000: | 1942 | case 6000000: |
2099 | status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 3) ; | 1943 | status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); |
2100 | break ; | 1944 | break; |
2101 | } | 1945 | } |
2102 | } else { // Analog Mode | 1946 | } else { /* Analog Mode */ |
2103 | switch (Tuner->Chan_Bandwidth) { | 1947 | switch (state->Chan_Bandwidth) { |
2104 | case 8000000: // Low Zero | 1948 | case 8000000: /* Low Zero */ |
2105 | status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 0 : 3)) ; | 1949 | status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 0 : 3)); |
2106 | break ; | 1950 | break; |
2107 | case 7000000: | 1951 | case 7000000: |
2108 | status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 1 : 4)) ; | 1952 | status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 1 : 4)); |
2109 | break ; | 1953 | break; |
2110 | case 6000000: | 1954 | case 6000000: |
2111 | status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 2 : 5)) ; | 1955 | status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 2 : 5)); |
2112 | break ; | 1956 | break; |
2113 | } | 1957 | } |
2114 | } | 1958 | } |
2115 | 1959 | ||
2116 | // | 1960 | /* Charge Pump Control Dig Ana */ |
2117 | // Charge Pump Control | 1961 | status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8); |
2118 | // Dig Ana | 1962 | status += MXL_ControlWrite(fe, RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1); |
2119 | status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, Tuner->Mode ? 5 : 8) ; | 1963 | status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0); |
2120 | status += MXL_ControlWrite(Tuner, RFSYN_EN_CHP_HIGAIN, Tuner->Mode ? 1 : 1) ; | ||
2121 | status += MXL_ControlWrite(Tuner, EN_CHP_LIN_B, Tuner->Mode ? 0 : 0) ; | ||
2122 | 1964 | ||
2123 | // | 1965 | /* AGC TOP Control */ |
2124 | // AGC TOP Control | 1966 | if (state->AGC_Mode == 0) /* Dual AGC */ { |
2125 | // | 1967 | status += MXL_ControlWrite(fe, AGC_IF, 15); |
2126 | if (Tuner->AGC_Mode == 0) // Dual AGC | 1968 | status += MXL_ControlWrite(fe, AGC_RF, 15); |
2127 | { | ||
2128 | status += MXL_ControlWrite(Tuner, AGC_IF, 15) ; | ||
2129 | status += MXL_ControlWrite(Tuner, AGC_RF, 15) ; | ||
2130 | } | 1969 | } |
2131 | else // Single AGC Mode Dig Ana | 1970 | else /* Single AGC Mode Dig Ana */ |
2132 | status += MXL_ControlWrite(Tuner, AGC_RF, Tuner->Mode? 15 : 12) ; | 1971 | status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); |
2133 | 1972 | ||
2134 | 1973 | ||
2135 | if (Tuner->TOP == 55) // TOP == 5.5 | 1974 | if (state->TOP == 55) /* TOP == 5.5 */ |
2136 | status += MXL_ControlWrite(Tuner, AGC_IF, 0x0) ; | 1975 | status += MXL_ControlWrite(fe, AGC_IF, 0x0); |
2137 | 1976 | ||
2138 | if (Tuner->TOP == 72) // TOP == 7.2 | 1977 | if (state->TOP == 72) /* TOP == 7.2 */ |
2139 | status += MXL_ControlWrite(Tuner, AGC_IF, 0x1) ; | 1978 | status += MXL_ControlWrite(fe, AGC_IF, 0x1); |
2140 | 1979 | ||
2141 | if (Tuner->TOP == 92) // TOP == 9.2 | 1980 | if (state->TOP == 92) /* TOP == 9.2 */ |
2142 | status += MXL_ControlWrite(Tuner, AGC_IF, 0x2) ; | 1981 | status += MXL_ControlWrite(fe, AGC_IF, 0x2); |
2143 | 1982 | ||
2144 | if (Tuner->TOP == 110) // TOP == 11.0 | 1983 | if (state->TOP == 110) /* TOP == 11.0 */ |
2145 | status += MXL_ControlWrite(Tuner, AGC_IF, 0x3) ; | 1984 | status += MXL_ControlWrite(fe, AGC_IF, 0x3); |
2146 | 1985 | ||
2147 | if (Tuner->TOP == 129) // TOP == 12.9 | 1986 | if (state->TOP == 129) /* TOP == 12.9 */ |
2148 | status += MXL_ControlWrite(Tuner, AGC_IF, 0x4) ; | 1987 | status += MXL_ControlWrite(fe, AGC_IF, 0x4); |
2149 | 1988 | ||
2150 | if (Tuner->TOP == 147) // TOP == 14.7 | 1989 | if (state->TOP == 147) /* TOP == 14.7 */ |
2151 | status += MXL_ControlWrite(Tuner, AGC_IF, 0x5) ; | 1990 | status += MXL_ControlWrite(fe, AGC_IF, 0x5); |
2152 | 1991 | ||
2153 | if (Tuner->TOP == 168) // TOP == 16.8 | 1992 | if (state->TOP == 168) /* TOP == 16.8 */ |
2154 | status += MXL_ControlWrite(Tuner, AGC_IF, 0x6) ; | 1993 | status += MXL_ControlWrite(fe, AGC_IF, 0x6); |
2155 | 1994 | ||
2156 | if (Tuner->TOP == 194) // TOP == 19.4 | 1995 | if (state->TOP == 194) /* TOP == 19.4 */ |
2157 | status += MXL_ControlWrite(Tuner, AGC_IF, 0x7) ; | 1996 | status += MXL_ControlWrite(fe, AGC_IF, 0x7); |
2158 | 1997 | ||
2159 | if (Tuner->TOP == 212) // TOP == 21.2 | 1998 | if (state->TOP == 212) /* TOP == 21.2 */ |
2160 | status += MXL_ControlWrite(Tuner, AGC_IF, 0x9) ; | 1999 | status += MXL_ControlWrite(fe, AGC_IF, 0x9); |
2161 | 2000 | ||
2162 | if (Tuner->TOP == 232) // TOP == 23.2 | 2001 | if (state->TOP == 232) /* TOP == 23.2 */ |
2163 | status += MXL_ControlWrite(Tuner, AGC_IF, 0xA) ; | 2002 | status += MXL_ControlWrite(fe, AGC_IF, 0xA); |
2164 | 2003 | ||
2165 | if (Tuner->TOP == 252) // TOP == 25.2 | 2004 | if (state->TOP == 252) /* TOP == 25.2 */ |
2166 | status += MXL_ControlWrite(Tuner, AGC_IF, 0xB) ; | 2005 | status += MXL_ControlWrite(fe, AGC_IF, 0xB); |
2167 | 2006 | ||
2168 | if (Tuner->TOP == 271) // TOP == 27.1 | 2007 | if (state->TOP == 271) /* TOP == 27.1 */ |
2169 | status += MXL_ControlWrite(Tuner, AGC_IF, 0xC) ; | 2008 | status += MXL_ControlWrite(fe, AGC_IF, 0xC); |
2170 | 2009 | ||
2171 | if (Tuner->TOP == 292) // TOP == 29.2 | 2010 | if (state->TOP == 292) /* TOP == 29.2 */ |
2172 | status += MXL_ControlWrite(Tuner, AGC_IF, 0xD) ; | 2011 | status += MXL_ControlWrite(fe, AGC_IF, 0xD); |
2173 | 2012 | ||
2174 | if (Tuner->TOP == 317) // TOP == 31.7 | 2013 | if (state->TOP == 317) /* TOP == 31.7 */ |
2175 | status += MXL_ControlWrite(Tuner, AGC_IF, 0xE) ; | 2014 | status += MXL_ControlWrite(fe, AGC_IF, 0xE); |
2176 | 2015 | ||
2177 | if (Tuner->TOP == 349) // TOP == 34.9 | 2016 | if (state->TOP == 349) /* TOP == 34.9 */ |
2178 | status += MXL_ControlWrite(Tuner, AGC_IF, 0xF) ; | 2017 | status += MXL_ControlWrite(fe, AGC_IF, 0xF); |
2179 | 2018 | ||
2180 | // | 2019 | /* IF Synthesizer Control */ |
2181 | // IF Synthesizer Control | 2020 | status += MXL_IFSynthInit(fe); |
2182 | // | ||
2183 | status += MXL_IFSynthInit( Tuner ) ; | ||
2184 | 2021 | ||
2185 | // | 2022 | /* IF UpConverter Control */ |
2186 | // IF UpConverter Control | 2023 | if (state->IF_OUT_LOAD == 200) { |
2187 | if (Tuner->IF_OUT_LOAD == 200) | 2024 | status += MXL_ControlWrite(fe, DRV_RES_SEL, 6); |
2188 | { | 2025 | status += MXL_ControlWrite(fe, I_DRIVER, 2); |
2189 | status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 6) ; | ||
2190 | status += MXL_ControlWrite(Tuner, I_DRIVER, 2) ; | ||
2191 | } | 2026 | } |
2192 | if (Tuner->IF_OUT_LOAD == 300) | 2027 | if (state->IF_OUT_LOAD == 300) { |
2193 | { | 2028 | status += MXL_ControlWrite(fe, DRV_RES_SEL, 4); |
2194 | status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 4) ; | 2029 | status += MXL_ControlWrite(fe, I_DRIVER, 1); |
2195 | status += MXL_ControlWrite(Tuner, I_DRIVER, 1) ; | ||
2196 | } | 2030 | } |
2197 | 2031 | ||
2198 | // | 2032 | /* Anti-Alias Filtering Control |
2199 | // Anti-Alias Filtering Control | 2033 | * initialise Anti-Aliasing Filter |
2200 | // | 2034 | */ |
2201 | // initialise Anti-Aliasing Filter | 2035 | if (state->Mode) { /* Digital Mode */ |
2202 | if (Tuner->Mode) {// Digital Mode | 2036 | if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) { |
2203 | if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 6280000UL) { | 2037 | status += MXL_ControlWrite(fe, EN_AAF, 1); |
2204 | status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; | 2038 | status += MXL_ControlWrite(fe, EN_3P, 1); |
2205 | status += MXL_ControlWrite(Tuner, EN_3P, 1) ; | 2039 | status += MXL_ControlWrite(fe, EN_AUX_3P, 1); |
2206 | status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; | 2040 | status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); |
2207 | status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; | 2041 | } |
2208 | } | 2042 | if ((state->IF_OUT == 36125000UL) || (state->IF_OUT == 36150000UL)) { |
2209 | if ((Tuner->IF_OUT == 36125000UL) || (Tuner->IF_OUT == 36150000UL)) { | 2043 | status += MXL_ControlWrite(fe, EN_AAF, 1); |
2210 | status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; | 2044 | status += MXL_ControlWrite(fe, EN_3P, 1); |
2211 | status += MXL_ControlWrite(Tuner, EN_3P, 1) ; | 2045 | status += MXL_ControlWrite(fe, EN_AUX_3P, 1); |
2212 | status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; | 2046 | status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1); |
2213 | status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ; | 2047 | } |
2214 | } | 2048 | if (state->IF_OUT > 36150000UL) { |
2215 | if (Tuner->IF_OUT > 36150000UL) { | 2049 | status += MXL_ControlWrite(fe, EN_AAF, 0); |
2216 | status += MXL_ControlWrite(Tuner, EN_AAF, 0) ; | 2050 | status += MXL_ControlWrite(fe, EN_3P, 1); |
2217 | status += MXL_ControlWrite(Tuner, EN_3P, 1) ; | 2051 | status += MXL_ControlWrite(fe, EN_AUX_3P, 1); |
2218 | status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; | 2052 | status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1); |
2219 | status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ; | 2053 | } |
2220 | } | 2054 | } else { /* Analog Mode */ |
2221 | } else { // Analog Mode | 2055 | if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) |
2222 | if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 5000000UL) | ||
2223 | { | 2056 | { |
2224 | status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; | 2057 | status += MXL_ControlWrite(fe, EN_AAF, 1); |
2225 | status += MXL_ControlWrite(Tuner, EN_3P, 1) ; | 2058 | status += MXL_ControlWrite(fe, EN_3P, 1); |
2226 | status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; | 2059 | status += MXL_ControlWrite(fe, EN_AUX_3P, 1); |
2227 | status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; | 2060 | status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); |
2228 | } | 2061 | } |
2229 | if (Tuner->IF_OUT > 5000000UL) | 2062 | if (state->IF_OUT > 5000000UL) |
2230 | { | 2063 | { |
2231 | status += MXL_ControlWrite(Tuner, EN_AAF, 0) ; | 2064 | status += MXL_ControlWrite(fe, EN_AAF, 0); |
2232 | status += MXL_ControlWrite(Tuner, EN_3P, 0) ; | 2065 | status += MXL_ControlWrite(fe, EN_3P, 0); |
2233 | status += MXL_ControlWrite(Tuner, EN_AUX_3P, 0) ; | 2066 | status += MXL_ControlWrite(fe, EN_AUX_3P, 0); |
2234 | status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; | 2067 | status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); |
2235 | } | 2068 | } |
2236 | } | 2069 | } |
2237 | 2070 | ||
2238 | // | 2071 | /* Demod Clock Out */ |
2239 | // Demod Clock Out | 2072 | if (state->CLOCK_OUT) |
2240 | // | 2073 | status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 1); |
2241 | if (Tuner->CLOCK_OUT) | ||
2242 | status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 1) ; | ||
2243 | else | 2074 | else |
2244 | status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 0) ; | 2075 | status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 0); |
2245 | 2076 | ||
2246 | if (Tuner->DIV_OUT == 1) | 2077 | if (state->DIV_OUT == 1) |
2247 | status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 1) ; | 2078 | status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 1); |
2248 | if (Tuner->DIV_OUT == 0) | 2079 | if (state->DIV_OUT == 0) |
2249 | status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 0) ; | 2080 | status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 0); |
2250 | 2081 | ||
2251 | // | 2082 | /* Crystal Control */ |
2252 | // Crystal Control | 2083 | if (state->CAPSELECT) |
2253 | // | 2084 | status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 1); |
2254 | if (Tuner->CAPSELECT) | ||
2255 | status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 1) ; | ||
2256 | else | 2085 | else |
2257 | status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 0) ; | 2086 | status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 0); |
2258 | 2087 | ||
2259 | if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) | 2088 | if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL) |
2260 | status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 1) ; | 2089 | status += MXL_ControlWrite(fe, IF_SEL_DBL, 1); |
2261 | if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL) | 2090 | if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) |
2262 | status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 0) ; | 2091 | status += MXL_ControlWrite(fe, IF_SEL_DBL, 0); |
2263 | 2092 | ||
2264 | if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL) | 2093 | if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL) |
2265 | status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 3) ; | 2094 | status += MXL_ControlWrite(fe, RFSYN_R_DIV, 3); |
2266 | if (Tuner->Fxtal > 22000000UL && Tuner->Fxtal <= 32000000UL) | 2095 | if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL) |
2267 | status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 0) ; | 2096 | status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0); |
2268 | 2097 | ||
2269 | // | 2098 | /* Misc Controls */ |
2270 | // Misc Controls | 2099 | if (state->Mode == 0 && Tuner->IF_Mode == 1) /* Analog LowIF mode */ |
2271 | // | 2100 | status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0); |
2272 | if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog LowIF mode | ||
2273 | status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 0); | ||
2274 | else | 2101 | else |
2275 | status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 1); | 2102 | status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1); |
2276 | 2103 | ||
2277 | // status += MXL_ControlRead(Tuner, IF_DIVVAL, &IF_DIVVAL_Val) ; | 2104 | /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */ |
2278 | 2105 | ||
2279 | // Set TG_R_DIV | 2106 | /* Set TG_R_DIV */ |
2280 | status += MXL_ControlWrite(Tuner, TG_R_DIV, MXL_Ceiling(Tuner->Fxtal, 1000000)) ; | 2107 | status += MXL_ControlWrite(fe, TG_R_DIV, MXL_Ceiling(state->Fxtal, 1000000)); |
2281 | 2108 | ||
2282 | // | 2109 | /* Apply Default value to BB_INITSTATE_DLPF_TUNE */ |
2283 | // Apply Default value to BB_INITSTATE_DLPF_TUNE | ||
2284 | // | ||
2285 | 2110 | ||
2286 | // | 2111 | /* RSSI Control */ |
2287 | // RSSI Control | 2112 | if (state->EN_RSSI) |
2288 | // | ||
2289 | if(Tuner->EN_RSSI) | ||
2290 | { | 2113 | { |
2291 | status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; | 2114 | status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); |
2292 | status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; | 2115 | status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); |
2293 | status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; | 2116 | status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); |
2294 | status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; | 2117 | status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); |
2295 | // RSSI reference point | 2118 | |
2296 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ; | 2119 | /* RSSI reference point */ |
2297 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 3) ; | 2120 | status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2); |
2298 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; | 2121 | status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 3); |
2299 | // TOP point | 2122 | status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1); |
2300 | status += MXL_ControlWrite(Tuner, RFA_FLR, 0) ; | 2123 | |
2301 | status += MXL_ControlWrite(Tuner, RFA_CEIL, 12) ; | 2124 | /* TOP point */ |
2125 | status += MXL_ControlWrite(fe, RFA_FLR, 0); | ||
2126 | status += MXL_ControlWrite(fe, RFA_CEIL, 12); | ||
2302 | } | 2127 | } |
2303 | 2128 | ||
2304 | // | 2129 | /* Modulation type bit settings |
2305 | // Modulation type bit settings | 2130 | * Override the control values preset |
2306 | // Override the control values preset | 2131 | */ |
2307 | // | 2132 | if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ |
2308 | if (Tuner->Mod_Type == MXL_DVBT) // DVB-T Mode | ||
2309 | { | 2133 | { |
2310 | Tuner->AGC_Mode = 1 ; // Single AGC Mode | 2134 | state->AGC_Mode = 1; /* Single AGC Mode */ |
2311 | 2135 | ||
2312 | // Enable RSSI | 2136 | /* Enable RSSI */ |
2313 | status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; | 2137 | status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); |
2314 | status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; | 2138 | status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); |
2315 | status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; | 2139 | status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); |
2316 | status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; | 2140 | status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); |
2317 | // RSSI reference point | 2141 | |
2318 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; | 2142 | /* RSSI reference point */ |
2319 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; | 2143 | status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); |
2320 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; | 2144 | status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); |
2321 | // TOP point | 2145 | status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1); |
2322 | status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ; | 2146 | |
2323 | status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ; | 2147 | /* TOP point */ |
2324 | if (Tuner->IF_OUT <= 6280000UL) // Low IF | 2148 | status += MXL_ControlWrite(fe, RFA_FLR, 2); |
2325 | status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; | 2149 | status += MXL_ControlWrite(fe, RFA_CEIL, 13); |
2326 | else // High IF | 2150 | if (state->IF_OUT <= 6280000UL) /* Low IF */ |
2327 | status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; | 2151 | status += MXL_ControlWrite(fe, BB_IQSWAP, 0); |
2152 | else /* High IF */ | ||
2153 | status += MXL_ControlWrite(fe, BB_IQSWAP, 1); | ||
2328 | 2154 | ||
2329 | } | 2155 | } |
2330 | if (Tuner->Mod_Type == MXL_ATSC) // ATSC Mode | 2156 | if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ |
2331 | { | 2157 | { |
2332 | Tuner->AGC_Mode = 1 ; // Single AGC Mode | 2158 | Tuner->AGC_Mode = 1; /* Single AGC Mode */ |
2333 | 2159 | ||
2334 | // Enable RSSI | 2160 | /* Enable RSSI */ |
2335 | status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; | 2161 | status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); |
2336 | status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; | 2162 | status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); |
2337 | status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; | 2163 | status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); |
2338 | status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; | 2164 | status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); |
2339 | // RSSI reference point | 2165 | |
2340 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ; | 2166 | /* RSSI reference point */ |
2341 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 4) ; | 2167 | status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2); |
2342 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; | 2168 | status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 4); |
2343 | // TOP point | 2169 | status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1); |
2344 | status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ; | 2170 | |
2345 | status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ; | 2171 | /* TOP point */ |
2346 | 2172 | status += MXL_ControlWrite(fe, RFA_FLR, 2); | |
2347 | status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 1) ; | 2173 | status += MXL_ControlWrite(fe, RFA_CEIL, 13); |
2348 | status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ; // Low Zero | 2174 | status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1); |
2349 | if (Tuner->IF_OUT <= 6280000UL) // Low IF | 2175 | status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); /* Low Zero */ |
2350 | status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; | 2176 | if (state->IF_OUT <= 6280000UL) /* Low IF */ |
2351 | else // High IF | 2177 | status += MXL_ControlWrite(fe, BB_IQSWAP, 0); |
2352 | status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; | 2178 | else /* High IF */ |
2179 | status += MXL_ControlWrite(fe, BB_IQSWAP, 1); | ||
2353 | } | 2180 | } |
2354 | if (Tuner->Mod_Type == MXL_QAM) // QAM Mode | 2181 | if (state->Mod_Type == MXL_QAM) /* QAM Mode */ |
2355 | { | 2182 | { |
2356 | Tuner->Mode = MXL_DIGITAL_MODE; | 2183 | state->Mode = MXL_DIGITAL_MODE; |
2357 | 2184 | ||
2358 | //Tuner->AGC_Mode = 1 ; // Single AGC Mode | 2185 | /* state->AGC_Mode = 1; */ /* Single AGC Mode */ |
2359 | 2186 | ||
2360 | // Disable RSSI //change here for v2.6.5 | 2187 | /* Disable RSSI */ /* change here for v2.6.5 */ |
2361 | status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; | 2188 | status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); |
2362 | status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; | 2189 | status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); |
2363 | status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; | 2190 | status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); |
2364 | status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; | 2191 | status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); |
2365 | 2192 | ||
2366 | // RSSI reference point | 2193 | /* RSSI reference point */ |
2367 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; | 2194 | status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); |
2368 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; | 2195 | status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); |
2369 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; | 2196 | status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); |
2370 | 2197 | status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); /* change here for v2.6.5 */ | |
2371 | status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; //change here for v2.6.5 | 2198 | |
2372 | 2199 | if (state->IF_OUT <= 6280000UL) /* Low IF */ | |
2373 | if (Tuner->IF_OUT <= 6280000UL) // Low IF | 2200 | status += MXL_ControlWrite(fe, BB_IQSWAP, 0); |
2374 | status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; | 2201 | else /* High IF */ |
2375 | else // High IF | 2202 | status += MXL_ControlWrite(fe, BB_IQSWAP, 1); |
2376 | status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; | ||
2377 | } | 2203 | } |
2378 | if (Tuner->Mod_Type == MXL_ANALOG_CABLE) // Analog Cable Mode | 2204 | if (state->Mod_Type == MXL_ANALOG_CABLE) { |
2379 | { | 2205 | /* Analog Cable Mode */ |
2380 | //Tuner->Mode = MXL_DIGITAL_MODE ; | 2206 | /* Tuner->Mode = MXL_DIGITAL_MODE; */ |
2381 | Tuner->AGC_Mode = 1 ; // Single AGC Mode | 2207 | |
2382 | 2208 | state->AGC_Mode = 1; /* Single AGC Mode */ | |
2383 | // Disable RSSI | 2209 | |
2384 | status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; | 2210 | /* Disable RSSI */ |
2385 | status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; | 2211 | status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); |
2386 | status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; | 2212 | status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); |
2387 | status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; | 2213 | status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); |
2388 | 2214 | status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); | |
2389 | status += MXL_ControlWrite(Tuner, AGC_IF, 1) ; //change for 2.6.3 | 2215 | status += MXL_ControlWrite(fe, AGC_IF, 1); /* change for 2.6.3 */ |
2390 | status += MXL_ControlWrite(Tuner, AGC_RF, 15) ; | 2216 | status += MXL_ControlWrite(fe, AGC_RF, 15); |
2391 | 2217 | status += MXL_ControlWrite(fe, BB_IQSWAP, 1); | |
2392 | status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; | ||
2393 | } | 2218 | } |
2394 | 2219 | ||
2395 | if (Tuner->Mod_Type == MXL_ANALOG_OTA) //Analog OTA Terrestrial mode add for 2.6.7 | 2220 | if (state->Mod_Type == MXL_ANALOG_OTA) { |
2396 | { | 2221 | /* Analog OTA Terrestrial mode add for 2.6.7 */ |
2397 | //Tuner->Mode = MXL_ANALOG_MODE; | 2222 | /* state->Mode = MXL_ANALOG_MODE; */ |
2398 | 2223 | ||
2399 | // Enable RSSI | 2224 | /* Enable RSSI */ |
2400 | status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; | 2225 | status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); |
2401 | status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; | 2226 | status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); |
2402 | status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; | 2227 | status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); |
2403 | status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; | 2228 | status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); |
2404 | 2229 | ||
2405 | // RSSI reference point | 2230 | /* RSSI reference point */ |
2406 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; | 2231 | status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); |
2407 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; | 2232 | status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); |
2408 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; | 2233 | status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); |
2409 | 2234 | status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); | |
2410 | status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; | 2235 | status += MXL_ControlWrite(fe, BB_IQSWAP, 1); |
2411 | |||
2412 | status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; | ||
2413 | } | 2236 | } |
2414 | 2237 | ||
2415 | // RSSI disable | 2238 | /* RSSI disable */ |
2416 | if(Tuner->EN_RSSI==0) | 2239 | if(state->EN_RSSI==0) { |
2417 | { | 2240 | status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); |
2418 | status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; | 2241 | status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); |
2419 | status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; | 2242 | status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); |
2420 | status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; | 2243 | status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); |
2421 | status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; | ||
2422 | } | 2244 | } |
2423 | 2245 | ||
2424 | return status ; | 2246 | return status; |
2425 | } | 2247 | } |
2426 | 2248 | ||
2427 | /////////////////////////////////////////////////////////////////////////////// | 2249 | /////////////////////////////////////////////////////////////////////////////// |
@@ -2456,9 +2278,9 @@ u16 MXL_IFSynthInit(Tuner_struct * Tuner) | |||
2456 | u32 fracModVal ; | 2278 | u32 fracModVal ; |
2457 | Kdbl = 2 ; | 2279 | Kdbl = 2 ; |
2458 | 2280 | ||
2459 | if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) | 2281 | if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL) |
2460 | Kdbl = 2 ; | 2282 | Kdbl = 2 ; |
2461 | if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL) | 2283 | if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) |
2462 | Kdbl = 1 ; | 2284 | Kdbl = 1 ; |
2463 | 2285 | ||
2464 | // | 2286 | // |
@@ -2467,43 +2289,43 @@ u16 MXL_IFSynthInit(Tuner_struct * Tuner) | |||
2467 | if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF mode | 2289 | if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF mode |
2468 | { | 2290 | { |
2469 | if (Tuner->IF_LO == 41000000UL) { | 2291 | if (Tuner->IF_LO == 41000000UL) { |
2470 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; | 2292 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; |
2471 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; | 2293 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; |
2472 | Fref = 328000000UL ; | 2294 | Fref = 328000000UL ; |
2473 | } | 2295 | } |
2474 | if (Tuner->IF_LO == 47000000UL) { | 2296 | if (Tuner->IF_LO == 47000000UL) { |
2475 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; | 2297 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; |
2476 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2298 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2477 | Fref = 376000000UL ; | 2299 | Fref = 376000000UL ; |
2478 | } | 2300 | } |
2479 | if (Tuner->IF_LO == 54000000UL) { | 2301 | if (Tuner->IF_LO == 54000000UL) { |
2480 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; | 2302 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; |
2481 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; | 2303 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; |
2482 | Fref = 324000000UL ; | 2304 | Fref = 324000000UL ; |
2483 | } | 2305 | } |
2484 | if (Tuner->IF_LO == 60000000UL) { | 2306 | if (Tuner->IF_LO == 60000000UL) { |
2485 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; | 2307 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; |
2486 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2308 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2487 | Fref = 360000000UL ; | 2309 | Fref = 360000000UL ; |
2488 | } | 2310 | } |
2489 | if (Tuner->IF_LO == 39250000UL) { | 2311 | if (Tuner->IF_LO == 39250000UL) { |
2490 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; | 2312 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; |
2491 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; | 2313 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; |
2492 | Fref = 314000000UL ; | 2314 | Fref = 314000000UL ; |
2493 | } | 2315 | } |
2494 | if (Tuner->IF_LO == 39650000UL) { | 2316 | if (Tuner->IF_LO == 39650000UL) { |
2495 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; | 2317 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; |
2496 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; | 2318 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; |
2497 | Fref = 317200000UL ; | 2319 | Fref = 317200000UL ; |
2498 | } | 2320 | } |
2499 | if (Tuner->IF_LO == 40150000UL) { | 2321 | if (Tuner->IF_LO == 40150000UL) { |
2500 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; | 2322 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; |
2501 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; | 2323 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; |
2502 | Fref = 321200000UL ; | 2324 | Fref = 321200000UL ; |
2503 | } | 2325 | } |
2504 | if (Tuner->IF_LO == 40650000UL) { | 2326 | if (Tuner->IF_LO == 40650000UL) { |
2505 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; | 2327 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; |
2506 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; | 2328 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; |
2507 | Fref = 325200000UL ; | 2329 | Fref = 325200000UL ; |
2508 | } | 2330 | } |
2509 | } | 2331 | } |
@@ -2511,153 +2333,153 @@ u16 MXL_IFSynthInit(Tuner_struct * Tuner) | |||
2511 | if (Tuner->Mode || (Tuner->Mode == 0 && Tuner->IF_Mode == 0)) | 2333 | if (Tuner->Mode || (Tuner->Mode == 0 && Tuner->IF_Mode == 0)) |
2512 | { | 2334 | { |
2513 | if (Tuner->IF_LO == 57000000UL) { | 2335 | if (Tuner->IF_LO == 57000000UL) { |
2514 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; | 2336 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; |
2515 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2337 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2516 | Fref = 342000000UL ; | 2338 | Fref = 342000000UL ; |
2517 | } | 2339 | } |
2518 | if (Tuner->IF_LO == 44000000UL) { | 2340 | if (Tuner->IF_LO == 44000000UL) { |
2519 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; | 2341 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; |
2520 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2342 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2521 | Fref = 352000000UL ; | 2343 | Fref = 352000000UL ; |
2522 | } | 2344 | } |
2523 | if (Tuner->IF_LO == 43750000UL) { | 2345 | if (Tuner->IF_LO == 43750000UL) { |
2524 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; | 2346 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; |
2525 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2347 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2526 | Fref = 350000000UL ; | 2348 | Fref = 350000000UL ; |
2527 | } | 2349 | } |
2528 | if (Tuner->IF_LO == 36650000UL) { | 2350 | if (Tuner->IF_LO == 36650000UL) { |
2529 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; | 2351 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; |
2530 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2352 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2531 | Fref = 366500000UL ; | 2353 | Fref = 366500000UL ; |
2532 | } | 2354 | } |
2533 | if (Tuner->IF_LO == 36150000UL) { | 2355 | if (Tuner->IF_LO == 36150000UL) { |
2534 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; | 2356 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; |
2535 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2357 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2536 | Fref = 361500000UL ; | 2358 | Fref = 361500000UL ; |
2537 | } | 2359 | } |
2538 | if (Tuner->IF_LO == 36000000UL) { | 2360 | if (Tuner->IF_LO == 36000000UL) { |
2539 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; | 2361 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; |
2540 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2362 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2541 | Fref = 360000000UL ; | 2363 | Fref = 360000000UL ; |
2542 | } | 2364 | } |
2543 | if (Tuner->IF_LO == 35250000UL) { | 2365 | if (Tuner->IF_LO == 35250000UL) { |
2544 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; | 2366 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; |
2545 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2367 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2546 | Fref = 352500000UL ; | 2368 | Fref = 352500000UL ; |
2547 | } | 2369 | } |
2548 | if (Tuner->IF_LO == 34750000UL) { | 2370 | if (Tuner->IF_LO == 34750000UL) { |
2549 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; | 2371 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; |
2550 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2372 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2551 | Fref = 347500000UL ; | 2373 | Fref = 347500000UL ; |
2552 | } | 2374 | } |
2553 | if (Tuner->IF_LO == 6280000UL) { | 2375 | if (Tuner->IF_LO == 6280000UL) { |
2554 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; | 2376 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; |
2555 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2377 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2556 | Fref = 376800000UL ; | 2378 | Fref = 376800000UL ; |
2557 | } | 2379 | } |
2558 | if (Tuner->IF_LO == 5000000UL) { | 2380 | if (Tuner->IF_LO == 5000000UL) { |
2559 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; | 2381 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; |
2560 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2382 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2561 | Fref = 360000000UL ; | 2383 | Fref = 360000000UL ; |
2562 | } | 2384 | } |
2563 | if (Tuner->IF_LO == 4500000UL) { | 2385 | if (Tuner->IF_LO == 4500000UL) { |
2564 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; | 2386 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; |
2565 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2387 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2566 | Fref = 360000000UL ; | 2388 | Fref = 360000000UL ; |
2567 | } | 2389 | } |
2568 | if (Tuner->IF_LO == 4570000UL) { | 2390 | if (Tuner->IF_LO == 4570000UL) { |
2569 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; | 2391 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; |
2570 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2392 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2571 | Fref = 365600000UL ; | 2393 | Fref = 365600000UL ; |
2572 | } | 2394 | } |
2573 | if (Tuner->IF_LO == 4000000UL) { | 2395 | if (Tuner->IF_LO == 4000000UL) { |
2574 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ; | 2396 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; |
2575 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2397 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2576 | Fref = 360000000UL ; | 2398 | Fref = 360000000UL ; |
2577 | } | 2399 | } |
2578 | if (Tuner->IF_LO == 57400000UL) | 2400 | if (Tuner->IF_LO == 57400000UL) |
2579 | { | 2401 | { |
2580 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; | 2402 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; |
2581 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2403 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2582 | Fref = 344400000UL ; | 2404 | Fref = 344400000UL ; |
2583 | } | 2405 | } |
2584 | if (Tuner->IF_LO == 44400000UL) | 2406 | if (Tuner->IF_LO == 44400000UL) |
2585 | { | 2407 | { |
2586 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; | 2408 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; |
2587 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2409 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2588 | Fref = 355200000UL ; | 2410 | Fref = 355200000UL ; |
2589 | } | 2411 | } |
2590 | if (Tuner->IF_LO == 44150000UL) | 2412 | if (Tuner->IF_LO == 44150000UL) |
2591 | { | 2413 | { |
2592 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; | 2414 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; |
2593 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2415 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2594 | Fref = 353200000UL ; | 2416 | Fref = 353200000UL ; |
2595 | } | 2417 | } |
2596 | if (Tuner->IF_LO == 37050000UL) | 2418 | if (Tuner->IF_LO == 37050000UL) |
2597 | { | 2419 | { |
2598 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; | 2420 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; |
2599 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2421 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2600 | Fref = 370500000UL ; | 2422 | Fref = 370500000UL ; |
2601 | } | 2423 | } |
2602 | if (Tuner->IF_LO == 36550000UL) | 2424 | if (Tuner->IF_LO == 36550000UL) |
2603 | { | 2425 | { |
2604 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; | 2426 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; |
2605 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2427 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2606 | Fref = 365500000UL ; | 2428 | Fref = 365500000UL ; |
2607 | } | 2429 | } |
2608 | if (Tuner->IF_LO == 36125000UL) { | 2430 | if (Tuner->IF_LO == 36125000UL) { |
2609 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; | 2431 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; |
2610 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2432 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2611 | Fref = 361250000UL ; | 2433 | Fref = 361250000UL ; |
2612 | } | 2434 | } |
2613 | if (Tuner->IF_LO == 6000000UL) { | 2435 | if (Tuner->IF_LO == 6000000UL) { |
2614 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; | 2436 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; |
2615 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2437 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2616 | Fref = 360000000UL ; | 2438 | Fref = 360000000UL ; |
2617 | } | 2439 | } |
2618 | if (Tuner->IF_LO == 5400000UL) | 2440 | if (Tuner->IF_LO == 5400000UL) |
2619 | { | 2441 | { |
2620 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; | 2442 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; |
2621 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; | 2443 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; |
2622 | Fref = 324000000UL ; | 2444 | Fref = 324000000UL ; |
2623 | } | 2445 | } |
2624 | if (Tuner->IF_LO == 5380000UL) { | 2446 | if (Tuner->IF_LO == 5380000UL) { |
2625 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; | 2447 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; |
2626 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; | 2448 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; |
2627 | Fref = 322800000UL ; | 2449 | Fref = 322800000UL ; |
2628 | } | 2450 | } |
2629 | if (Tuner->IF_LO == 5200000UL) { | 2451 | if (Tuner->IF_LO == 5200000UL) { |
2630 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; | 2452 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; |
2631 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2453 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2632 | Fref = 374400000UL ; | 2454 | Fref = 374400000UL ; |
2633 | } | 2455 | } |
2634 | if (Tuner->IF_LO == 4900000UL) | 2456 | if (Tuner->IF_LO == 4900000UL) |
2635 | { | 2457 | { |
2636 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; | 2458 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; |
2637 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2459 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2638 | Fref = 352800000UL ; | 2460 | Fref = 352800000UL ; |
2639 | } | 2461 | } |
2640 | if (Tuner->IF_LO == 4400000UL) | 2462 | if (Tuner->IF_LO == 4400000UL) |
2641 | { | 2463 | { |
2642 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; | 2464 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; |
2643 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2465 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2644 | Fref = 352000000UL ; | 2466 | Fref = 352000000UL ; |
2645 | } | 2467 | } |
2646 | if (Tuner->IF_LO == 4063000UL) //add for 2.6.8 | 2468 | if (Tuner->IF_LO == 4063000UL) //add for 2.6.8 |
2647 | { | 2469 | { |
2648 | status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ; | 2470 | status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; |
2649 | status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; | 2471 | status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; |
2650 | Fref = 365670000UL ; | 2472 | Fref = 365670000UL ; |
2651 | } | 2473 | } |
2652 | } | 2474 | } |
2653 | // CHCAL_INT_MOD_IF | 2475 | // CHCAL_INT_MOD_IF |
2654 | // CHCAL_FRAC_MOD_IF | 2476 | // CHCAL_FRAC_MOD_IF |
2655 | intModVal = Fref / (Tuner->Fxtal * Kdbl/2) ; | 2477 | intModVal = Fref / (state->Fxtal * Kdbl/2) ; |
2656 | status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_IF, intModVal ) ; | 2478 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal ) ; |
2657 | 2479 | ||
2658 | fracModVal = (2<<15)*(Fref/1000 - (Tuner->Fxtal/1000 * Kdbl/2) * intModVal); | 2480 | fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * intModVal); |
2659 | fracModVal = fracModVal / ((Tuner->Fxtal * Kdbl/2)/1000) ; | 2481 | fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000) ; |
2660 | status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_IF, fracModVal) ; | 2482 | status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal) ; |
2661 | 2483 | ||
2662 | return status ; | 2484 | return status ; |
2663 | } | 2485 | } |
@@ -2706,7 +2528,7 @@ u32 MXL_GetXtalInt(u32 Xtal_Freq) | |||
2706 | // Functions used: // | 2528 | // Functions used: // |
2707 | // MXL_SynthRFTGLO_Calc // | 2529 | // MXL_SynthRFTGLO_Calc // |
2708 | // MXL5005_ControlWrite // | 2530 | // MXL5005_ControlWrite // |
2709 | // MXL_GetXtalInt // | 2531 | // MXL_GetXtalInt // |
2710 | // // | 2532 | // // |
2711 | // Inputs: // | 2533 | // Inputs: // |
2712 | // Tuner : Tuner structure defined at higher level // | 2534 | // Tuner : Tuner structure defined at higher level // |
@@ -2718,32 +2540,33 @@ u32 MXL_GetXtalInt(u32 Xtal_Freq) | |||
2718 | // 0 : Successful // | 2540 | // 0 : Successful // |
2719 | // 1 : Unsuccessful // | 2541 | // 1 : Unsuccessful // |
2720 | /////////////////////////////////////////////////////////////////////////////// | 2542 | /////////////////////////////////////////////////////////////////////////////// |
2721 | u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) | 2543 | u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) |
2722 | { | 2544 | { |
2545 | struct mxl5005s_state *state = fe->demodulator_priv; | ||
2723 | // Declare Local Variables | 2546 | // Declare Local Variables |
2724 | u16 status = 0 ; | 2547 | u16 status = 0; |
2725 | u32 divider_val, E3, E4, E5, E5A ; | 2548 | u32 divider_val, E3, E4, E5, E5A; |
2726 | u32 Fmax, Fmin, FmaxBin, FminBin ; | 2549 | u32 Fmax, Fmin, FmaxBin, FminBin; |
2727 | u32 Kdbl_RF = 2; | 2550 | u32 Kdbl_RF = 2; |
2728 | u32 tg_divval ; | 2551 | u32 tg_divval; |
2729 | u32 tg_lo ; | 2552 | u32 tg_lo; |
2730 | u32 Xtal_Int ; | 2553 | u32 Xtal_Int; |
2731 | 2554 | ||
2732 | u32 Fref_TG; | 2555 | u32 Fref_TG; |
2733 | u32 Fvco; | 2556 | u32 Fvco; |
2734 | // u32 temp; | 2557 | // u32 temp; |
2735 | 2558 | ||
2736 | 2559 | ||
2737 | Xtal_Int = MXL_GetXtalInt(Tuner->Fxtal ) ; | 2560 | Xtal_Int = MXL_GetXtalInt(state->Fxtal); |
2738 | 2561 | ||
2739 | Tuner->RF_IN = RF_Freq ; | 2562 | state->RF_IN = RF_Freq; |
2740 | 2563 | ||
2741 | MXL_SynthRFTGLO_Calc( Tuner ) ; | 2564 | MXL_SynthRFTGLO_Calc(fe); |
2742 | 2565 | ||
2743 | if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL) | 2566 | if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL) |
2744 | Kdbl_RF = 2 ; | 2567 | Kdbl_RF = 2; |
2745 | if (Tuner->Fxtal > 22000000 && Tuner->Fxtal <= 32000000) | 2568 | if (state->Fxtal > 22000000 && state->Fxtal <= 32000000) |
2746 | Kdbl_RF = 1 ; | 2569 | Kdbl_RF = 1; |
2747 | 2570 | ||
2748 | // | 2571 | // |
2749 | // Downconverter Controls | 2572 | // Downconverter Controls |
@@ -2755,133 +2578,133 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) | |||
2755 | // DN_EN_VHFUHFBAR | 2578 | // DN_EN_VHFUHFBAR |
2756 | // DN_GAIN_ADJUST | 2579 | // DN_GAIN_ADJUST |
2757 | // Change the boundary reference from RF_IN to RF_LO | 2580 | // Change the boundary reference from RF_IN to RF_LO |
2758 | if (Tuner->RF_LO < 40000000UL) { | 2581 | if (state->RF_LO < 40000000UL) { |
2759 | return -1; | 2582 | return -1; |
2760 | } | 2583 | } |
2761 | if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) { | 2584 | if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { |
2762 | // Look-Up Table implementation | 2585 | // Look-Up Table implementation |
2763 | status += MXL_ControlWrite(Tuner, DN_POLY, 2) ; | 2586 | status += MXL_ControlWrite(fe, DN_POLY, 2); |
2764 | status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; | 2587 | status += MXL_ControlWrite(fe, DN_RFGAIN, 3); |
2765 | status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 423) ; | 2588 | status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423); |
2766 | status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; | 2589 | status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); |
2767 | status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ; | 2590 | status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); |
2768 | } | 2591 | } |
2769 | if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) { | 2592 | if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { |
2770 | // Look-Up Table implementation | 2593 | // Look-Up Table implementation |
2771 | status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; | 2594 | status += MXL_ControlWrite(fe, DN_POLY, 3); |
2772 | status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; | 2595 | status += MXL_ControlWrite(fe, DN_RFGAIN, 3); |
2773 | status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 222) ; | 2596 | status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222); |
2774 | status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; | 2597 | status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); |
2775 | status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ; | 2598 | status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); |
2776 | } | 2599 | } |
2777 | if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) { | 2600 | if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { |
2778 | // Look-Up Table implementation | 2601 | // Look-Up Table implementation |
2779 | status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; | 2602 | status += MXL_ControlWrite(fe, DN_POLY, 3); |
2780 | status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; | 2603 | status += MXL_ControlWrite(fe, DN_RFGAIN, 3); |
2781 | status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 147) ; | 2604 | status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147); |
2782 | status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; | 2605 | status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); |
2783 | status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ; | 2606 | status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); |
2784 | } | 2607 | } |
2785 | if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) { | 2608 | if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { |
2786 | // Look-Up Table implementation | 2609 | // Look-Up Table implementation |
2787 | status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; | 2610 | status += MXL_ControlWrite(fe, DN_POLY, 3); |
2788 | status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; | 2611 | status += MXL_ControlWrite(fe, DN_RFGAIN, 3); |
2789 | status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 9) ; | 2612 | status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9); |
2790 | status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; | 2613 | status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); |
2791 | status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ; | 2614 | status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); |
2792 | } | 2615 | } |
2793 | if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) { | 2616 | if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { |
2794 | // Look-Up Table implementation | 2617 | // Look-Up Table implementation |
2795 | status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; | 2618 | status += MXL_ControlWrite(fe, DN_POLY, 3) ; |
2796 | status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; | 2619 | status += MXL_ControlWrite(fe, DN_RFGAIN, 3) ; |
2797 | status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; | 2620 | status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; |
2798 | status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; | 2621 | status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1) ; |
2799 | status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; | 2622 | status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; |
2800 | } | 2623 | } |
2801 | if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 650000000UL) { | 2624 | if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) { |
2802 | // Look-Up Table implementation | 2625 | // Look-Up Table implementation |
2803 | status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; | 2626 | status += MXL_ControlWrite(fe, DN_POLY, 3) ; |
2804 | status += MXL_ControlWrite(Tuner, DN_RFGAIN, 1) ; | 2627 | status += MXL_ControlWrite(fe, DN_RFGAIN, 1) ; |
2805 | status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; | 2628 | status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; |
2806 | status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ; | 2629 | status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ; |
2807 | status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; | 2630 | status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; |
2808 | } | 2631 | } |
2809 | if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 900000000UL) { | 2632 | if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) { |
2810 | // Look-Up Table implementation | 2633 | // Look-Up Table implementation |
2811 | status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; | 2634 | status += MXL_ControlWrite(fe, DN_POLY, 3) ; |
2812 | status += MXL_ControlWrite(Tuner, DN_RFGAIN, 2) ; | 2635 | status += MXL_ControlWrite(fe, DN_RFGAIN, 2) ; |
2813 | status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; | 2636 | status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; |
2814 | status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ; | 2637 | status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ; |
2815 | status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; | 2638 | status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; |
2816 | } | 2639 | } |
2817 | if (Tuner->RF_LO > 900000000UL) { | 2640 | if (state->RF_LO > 900000000UL) { |
2818 | return -1; | 2641 | return -1; |
2819 | } | 2642 | } |
2820 | // DN_IQTNBUF_AMP | 2643 | // DN_IQTNBUF_AMP |
2821 | // DN_IQTNGNBFBIAS_BST | 2644 | // DN_IQTNGNBFBIAS_BST |
2822 | if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) { | 2645 | if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { |
2823 | status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; | 2646 | status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); |
2824 | status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; | 2647 | status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); |
2825 | } | 2648 | } |
2826 | if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) { | 2649 | if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { |
2827 | status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; | 2650 | status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); |
2828 | status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; | 2651 | status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); |
2829 | } | 2652 | } |
2830 | if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) { | 2653 | if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { |
2831 | status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; | 2654 | status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); |
2832 | status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; | 2655 | status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); |
2833 | } | 2656 | } |
2834 | if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) { | 2657 | if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { |
2835 | status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; | 2658 | status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); |
2836 | status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; | 2659 | status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); |
2837 | } | 2660 | } |
2838 | if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) { | 2661 | if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { |
2839 | status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; | 2662 | status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); |
2840 | status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; | 2663 | status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); |
2841 | } | 2664 | } |
2842 | if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 400000000UL) { | 2665 | if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) { |
2843 | status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; | 2666 | status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); |
2844 | status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; | 2667 | status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); |
2845 | } | 2668 | } |
2846 | if (Tuner->RF_LO > 400000000UL && Tuner->RF_LO <= 450000000UL) { | 2669 | if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) { |
2847 | status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; | 2670 | status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); |
2848 | status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; | 2671 | status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); |
2849 | } | 2672 | } |
2850 | if (Tuner->RF_LO > 450000000UL && Tuner->RF_LO <= 500000000UL) { | 2673 | if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) { |
2851 | status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; | 2674 | status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); |
2852 | status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; | 2675 | status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); |
2853 | } | 2676 | } |
2854 | if (Tuner->RF_LO > 500000000UL && Tuner->RF_LO <= 550000000UL) { | 2677 | if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) { |
2855 | status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; | 2678 | status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); |
2856 | status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; | 2679 | status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); |
2857 | } | 2680 | } |
2858 | if (Tuner->RF_LO > 550000000UL && Tuner->RF_LO <= 600000000UL) { | 2681 | if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) { |
2859 | status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; | 2682 | status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); |
2860 | status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; | 2683 | status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); |
2861 | } | 2684 | } |
2862 | if (Tuner->RF_LO > 600000000UL && Tuner->RF_LO <= 650000000UL) { | 2685 | if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) { |
2863 | status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; | 2686 | status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); |
2864 | status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; | 2687 | status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); |
2865 | } | 2688 | } |
2866 | if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 700000000UL) { | 2689 | if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) { |
2867 | status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; | 2690 | status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); |
2868 | status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; | 2691 | status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); |
2869 | } | 2692 | } |
2870 | if (Tuner->RF_LO > 700000000UL && Tuner->RF_LO <= 750000000UL) { | 2693 | if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) { |
2871 | status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; | 2694 | status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); |
2872 | status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; | 2695 | status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); |
2873 | } | 2696 | } |
2874 | if (Tuner->RF_LO > 750000000UL && Tuner->RF_LO <= 800000000UL) { | 2697 | if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) { |
2875 | status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; | 2698 | status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); |
2876 | status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; | 2699 | status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); |
2877 | } | 2700 | } |
2878 | if (Tuner->RF_LO > 800000000UL && Tuner->RF_LO <= 850000000UL) { | 2701 | if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) { |
2879 | status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ; | 2702 | status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10); |
2880 | status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ; | 2703 | status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1); |
2881 | } | 2704 | } |
2882 | if (Tuner->RF_LO > 850000000UL && Tuner->RF_LO <= 900000000UL) { | 2705 | if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) { |
2883 | status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ; | 2706 | status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10); |
2884 | status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ; | 2707 | status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1); |
2885 | } | 2708 | } |
2886 | 2709 | ||
2887 | // | 2710 | // |
@@ -2898,143 +2721,143 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) | |||
2898 | // Set divider_val, Fmax, Fmix to use in Equations | 2721 | // Set divider_val, Fmax, Fmix to use in Equations |
2899 | FminBin = 28000000UL ; | 2722 | FminBin = 28000000UL ; |
2900 | FmaxBin = 42500000UL ; | 2723 | FmaxBin = 42500000UL ; |
2901 | if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= FmaxBin) { | 2724 | if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) { |
2902 | status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; | 2725 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); |
2903 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; | 2726 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); |
2904 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; | 2727 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
2905 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; | 2728 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); |
2906 | status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; | 2729 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); |
2907 | status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; | 2730 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); |
2908 | divider_val = 64 ; | 2731 | divider_val = 64 ; |
2909 | Fmax = FmaxBin ; | 2732 | Fmax = FmaxBin ; |
2910 | Fmin = FminBin ; | 2733 | Fmin = FminBin ; |
2911 | } | 2734 | } |
2912 | FminBin = 42500000UL ; | 2735 | FminBin = 42500000UL ; |
2913 | FmaxBin = 56000000UL ; | 2736 | FmaxBin = 56000000UL ; |
2914 | if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { | 2737 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2915 | status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; | 2738 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); |
2916 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; | 2739 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); |
2917 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; | 2740 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); |
2918 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; | 2741 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); |
2919 | status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; | 2742 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); |
2920 | status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; | 2743 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); |
2921 | divider_val = 64 ; | 2744 | divider_val = 64 ; |
2922 | Fmax = FmaxBin ; | 2745 | Fmax = FmaxBin ; |
2923 | Fmin = FminBin ; | 2746 | Fmin = FminBin ; |
2924 | } | 2747 | } |
2925 | FminBin = 56000000UL ; | 2748 | FminBin = 56000000UL ; |
2926 | FmaxBin = 85000000UL ; | 2749 | FmaxBin = 85000000UL ; |
2927 | if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { | 2750 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2928 | status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; | 2751 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; |
2929 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; | 2752 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; |
2930 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; | 2753 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; |
2931 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; | 2754 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; |
2932 | status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; | 2755 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; |
2933 | status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; | 2756 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ; |
2934 | divider_val = 32 ; | 2757 | divider_val = 32 ; |
2935 | Fmax = FmaxBin ; | 2758 | Fmax = FmaxBin ; |
2936 | Fmin = FminBin ; | 2759 | Fmin = FminBin ; |
2937 | } | 2760 | } |
2938 | FminBin = 85000000UL ; | 2761 | FminBin = 85000000UL ; |
2939 | FmaxBin = 112000000UL ; | 2762 | FmaxBin = 112000000UL ; |
2940 | if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { | 2763 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2941 | status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; | 2764 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; |
2942 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; | 2765 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; |
2943 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; | 2766 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; |
2944 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; | 2767 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; |
2945 | status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; | 2768 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; |
2946 | status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; | 2769 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ; |
2947 | divider_val = 32 ; | 2770 | divider_val = 32 ; |
2948 | Fmax = FmaxBin ; | 2771 | Fmax = FmaxBin ; |
2949 | Fmin = FminBin ; | 2772 | Fmin = FminBin ; |
2950 | } | 2773 | } |
2951 | FminBin = 112000000UL ; | 2774 | FminBin = 112000000UL ; |
2952 | FmaxBin = 170000000UL ; | 2775 | FmaxBin = 170000000UL ; |
2953 | if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { | 2776 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2954 | status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; | 2777 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; |
2955 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; | 2778 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; |
2956 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; | 2779 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; |
2957 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; | 2780 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; |
2958 | status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; | 2781 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; |
2959 | status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ; | 2782 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ; |
2960 | divider_val = 16 ; | 2783 | divider_val = 16 ; |
2961 | Fmax = FmaxBin ; | 2784 | Fmax = FmaxBin ; |
2962 | Fmin = FminBin ; | 2785 | Fmin = FminBin ; |
2963 | } | 2786 | } |
2964 | FminBin = 170000000UL ; | 2787 | FminBin = 170000000UL ; |
2965 | FmaxBin = 225000000UL ; | 2788 | FmaxBin = 225000000UL ; |
2966 | if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { | 2789 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2967 | status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; | 2790 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; |
2968 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; | 2791 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; |
2969 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; | 2792 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; |
2970 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; | 2793 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; |
2971 | status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; | 2794 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; |
2972 | status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ; | 2795 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ; |
2973 | divider_val = 16 ; | 2796 | divider_val = 16 ; |
2974 | Fmax = FmaxBin ; | 2797 | Fmax = FmaxBin ; |
2975 | Fmin = FminBin ; | 2798 | Fmin = FminBin ; |
2976 | } | 2799 | } |
2977 | FminBin = 225000000UL ; | 2800 | FminBin = 225000000UL ; |
2978 | FmaxBin = 300000000UL ; | 2801 | FmaxBin = 300000000UL ; |
2979 | if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { | 2802 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2980 | status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; | 2803 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; |
2981 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; | 2804 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; |
2982 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; | 2805 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; |
2983 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; | 2806 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; |
2984 | status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; | 2807 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; |
2985 | status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 4) ; | 2808 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4) ; |
2986 | divider_val = 8 ; | 2809 | divider_val = 8 ; |
2987 | Fmax = 340000000UL ; | 2810 | Fmax = 340000000UL ; |
2988 | Fmin = FminBin ; | 2811 | Fmin = FminBin ; |
2989 | } | 2812 | } |
2990 | FminBin = 300000000UL ; | 2813 | FminBin = 300000000UL ; |
2991 | FmaxBin = 340000000UL ; | 2814 | FmaxBin = 340000000UL ; |
2992 | if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { | 2815 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
2993 | status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; | 2816 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ; |
2994 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; | 2817 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ; |
2995 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; | 2818 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; |
2996 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; | 2819 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; |
2997 | status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; | 2820 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; |
2998 | status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; | 2821 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; |
2999 | divider_val = 8 ; | 2822 | divider_val = 8 ; |
3000 | Fmax = FmaxBin ; | 2823 | Fmax = FmaxBin ; |
3001 | Fmin = 225000000UL ; | 2824 | Fmin = 225000000UL ; |
3002 | } | 2825 | } |
3003 | FminBin = 340000000UL ; | 2826 | FminBin = 340000000UL ; |
3004 | FmaxBin = 450000000UL ; | 2827 | FmaxBin = 450000000UL ; |
3005 | if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { | 2828 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
3006 | status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; | 2829 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ; |
3007 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; | 2830 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ; |
3008 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; | 2831 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; |
3009 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; | 2832 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; |
3010 | status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 2) ; | 2833 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2) ; |
3011 | status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; | 2834 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; |
3012 | divider_val = 8 ; | 2835 | divider_val = 8 ; |
3013 | Fmax = FmaxBin ; | 2836 | Fmax = FmaxBin ; |
3014 | Fmin = FminBin ; | 2837 | Fmin = FminBin ; |
3015 | } | 2838 | } |
3016 | FminBin = 450000000UL ; | 2839 | FminBin = 450000000UL ; |
3017 | FmaxBin = 680000000UL ; | 2840 | FmaxBin = 680000000UL ; |
3018 | if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { | 2841 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
3019 | status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; | 2842 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; |
3020 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; | 2843 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; |
3021 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; | 2844 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; |
3022 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ; | 2845 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ; |
3023 | status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; | 2846 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; |
3024 | status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; | 2847 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; |
3025 | divider_val = 4 ; | 2848 | divider_val = 4 ; |
3026 | Fmax = FmaxBin ; | 2849 | Fmax = FmaxBin ; |
3027 | Fmin = FminBin ; | 2850 | Fmin = FminBin ; |
3028 | } | 2851 | } |
3029 | FminBin = 680000000UL ; | 2852 | FminBin = 680000000UL ; |
3030 | FmaxBin = 900000000UL ; | 2853 | FmaxBin = 900000000UL ; |
3031 | if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { | 2854 | if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { |
3032 | status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; | 2855 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; |
3033 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; | 2856 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; |
3034 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; | 2857 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; |
3035 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ; | 2858 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ; |
3036 | status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; | 2859 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; |
3037 | status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; | 2860 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; |
3038 | divider_val = 4 ; | 2861 | divider_val = 4 ; |
3039 | Fmax = FmaxBin ; | 2862 | Fmax = FmaxBin ; |
3040 | Fmin = FminBin ; | 2863 | Fmin = FminBin ; |
@@ -3047,32 +2870,32 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) | |||
3047 | 2870 | ||
3048 | // Equation E3 | 2871 | // Equation E3 |
3049 | // RFSYN_VCO_BIAS | 2872 | // RFSYN_VCO_BIAS |
3050 | E3 = (((Fmax-Tuner->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; | 2873 | E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; |
3051 | status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, E3) ; | 2874 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3) ; |
3052 | 2875 | ||
3053 | // Equation E4 | 2876 | // Equation E4 |
3054 | // CHCAL_INT_MOD_RF | 2877 | // CHCAL_INT_MOD_RF |
3055 | E4 = (Tuner->RF_LO*divider_val/1000)/(2*Tuner->Fxtal*Kdbl_RF/1000) ; | 2878 | E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000) ; |
3056 | MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, E4) ; | 2879 | MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4) ; |
3057 | 2880 | ||
3058 | // Equation E5 | 2881 | // Equation E5 |
3059 | // CHCAL_FRAC_MOD_RF | 2882 | // CHCAL_FRAC_MOD_RF |
3060 | // CHCAL_EN_INT_RF | 2883 | // CHCAL_EN_INT_RF |
3061 | E5 = ((2<<17)*(Tuner->RF_LO/10000*divider_val - (E4*(2*Tuner->Fxtal*Kdbl_RF)/10000)))/(2*Tuner->Fxtal*Kdbl_RF/10000) ; | 2884 | E5 = ((2<<17)*(state->RF_LO/10000*divider_val - (E4*(2*state->Fxtal*Kdbl_RF)/10000)))/(2*state->Fxtal*Kdbl_RF/10000) ; |
3062 | status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ; | 2885 | status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ; |
3063 | 2886 | ||
3064 | // Equation E5A | 2887 | // Equation E5A |
3065 | // RFSYN_LPF_R | 2888 | // RFSYN_LPF_R |
3066 | E5A = (((Fmax - Tuner->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; | 2889 | E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; |
3067 | status += MXL_ControlWrite(Tuner, RFSYN_LPF_R, E5A) ; | 2890 | status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A) ; |
3068 | 2891 | ||
3069 | // Euqation E5B | 2892 | // Euqation E5B |
3070 | // CHCAL_EN_INIT_RF | 2893 | // CHCAL_EN_INIT_RF |
3071 | status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0)); | 2894 | status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0)); |
3072 | //if (E5 == 0) | 2895 | //if (E5 == 0) |
3073 | // status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, 1); | 2896 | // status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1); |
3074 | //else | 2897 | //else |
3075 | // status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ; | 2898 | // status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ; |
3076 | 2899 | ||
3077 | // | 2900 | // |
3078 | // Set TG Synth | 2901 | // Set TG Synth |
@@ -3082,98 +2905,98 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) | |||
3082 | // TG_LO_SELVAL | 2905 | // TG_LO_SELVAL |
3083 | // | 2906 | // |
3084 | // Set divider_val, Fmax, Fmix to use in Equations | 2907 | // Set divider_val, Fmax, Fmix to use in Equations |
3085 | if (Tuner->TG_LO < 33000000UL) { | 2908 | if (state->TG_LO < 33000000UL) { |
3086 | return -1; | 2909 | return -1; |
3087 | } | 2910 | } |
3088 | FminBin = 33000000UL ; | 2911 | FminBin = 33000000UL ; |
3089 | FmaxBin = 50000000UL ; | 2912 | FmaxBin = 50000000UL ; |
3090 | if (Tuner->TG_LO >= FminBin && Tuner->TG_LO <= FmaxBin) { | 2913 | if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) { |
3091 | status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x6) ; | 2914 | status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6) ; |
3092 | status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ; | 2915 | status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ; |
3093 | divider_val = 36 ; | 2916 | divider_val = 36 ; |
3094 | Fmax = FmaxBin ; | 2917 | Fmax = FmaxBin ; |
3095 | Fmin = FminBin ; | 2918 | Fmin = FminBin ; |
3096 | } | 2919 | } |
3097 | FminBin = 50000000UL ; | 2920 | FminBin = 50000000UL ; |
3098 | FmaxBin = 67000000UL ; | 2921 | FmaxBin = 67000000UL ; |
3099 | if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { | 2922 | if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { |
3100 | status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x1) ; | 2923 | status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1) ; |
3101 | status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ; | 2924 | status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ; |
3102 | divider_val = 24 ; | 2925 | divider_val = 24 ; |
3103 | Fmax = FmaxBin ; | 2926 | Fmax = FmaxBin ; |
3104 | Fmin = FminBin ; | 2927 | Fmin = FminBin ; |
3105 | } | 2928 | } |
3106 | FminBin = 67000000UL ; | 2929 | FminBin = 67000000UL ; |
3107 | FmaxBin = 100000000UL ; | 2930 | FmaxBin = 100000000UL ; |
3108 | if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { | 2931 | if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { |
3109 | status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0xC) ; | 2932 | status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC) ; |
3110 | status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; | 2933 | status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; |
3111 | divider_val = 18 ; | 2934 | divider_val = 18 ; |
3112 | Fmax = FmaxBin ; | 2935 | Fmax = FmaxBin ; |
3113 | Fmin = FminBin ; | 2936 | Fmin = FminBin ; |
3114 | } | 2937 | } |
3115 | FminBin = 100000000UL ; | 2938 | FminBin = 100000000UL ; |
3116 | FmaxBin = 150000000UL ; | 2939 | FmaxBin = 150000000UL ; |
3117 | if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { | 2940 | if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { |
3118 | status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; | 2941 | status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; |
3119 | status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; | 2942 | status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; |
3120 | divider_val = 12 ; | 2943 | divider_val = 12 ; |
3121 | Fmax = FmaxBin ; | 2944 | Fmax = FmaxBin ; |
3122 | Fmin = FminBin ; | 2945 | Fmin = FminBin ; |
3123 | } | 2946 | } |
3124 | FminBin = 150000000UL ; | 2947 | FminBin = 150000000UL ; |
3125 | FmaxBin = 200000000UL ; | 2948 | FmaxBin = 200000000UL ; |
3126 | if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { | 2949 | if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { |
3127 | status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; | 2950 | status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; |
3128 | status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; | 2951 | status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; |
3129 | divider_val = 8 ; | 2952 | divider_val = 8 ; |
3130 | Fmax = FmaxBin ; | 2953 | Fmax = FmaxBin ; |
3131 | Fmin = FminBin ; | 2954 | Fmin = FminBin ; |
3132 | } | 2955 | } |
3133 | FminBin = 200000000UL ; | 2956 | FminBin = 200000000UL ; |
3134 | FmaxBin = 300000000UL ; | 2957 | FmaxBin = 300000000UL ; |
3135 | if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { | 2958 | if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { |
3136 | status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; | 2959 | status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; |
3137 | status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ; | 2960 | status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ; |
3138 | divider_val = 6 ; | 2961 | divider_val = 6 ; |
3139 | Fmax = FmaxBin ; | 2962 | Fmax = FmaxBin ; |
3140 | Fmin = FminBin ; | 2963 | Fmin = FminBin ; |
3141 | } | 2964 | } |
3142 | FminBin = 300000000UL ; | 2965 | FminBin = 300000000UL ; |
3143 | FmaxBin = 400000000UL ; | 2966 | FmaxBin = 400000000UL ; |
3144 | if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { | 2967 | if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { |
3145 | status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; | 2968 | status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; |
3146 | status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ; | 2969 | status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ; |
3147 | divider_val = 4 ; | 2970 | divider_val = 4 ; |
3148 | Fmax = FmaxBin ; | 2971 | Fmax = FmaxBin ; |
3149 | Fmin = FminBin ; | 2972 | Fmin = FminBin ; |
3150 | } | 2973 | } |
3151 | FminBin = 400000000UL ; | 2974 | FminBin = 400000000UL ; |
3152 | FmaxBin = 600000000UL ; | 2975 | FmaxBin = 600000000UL ; |
3153 | if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { | 2976 | if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { |
3154 | status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; | 2977 | status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; |
3155 | status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ; | 2978 | status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ; |
3156 | divider_val = 3 ; | 2979 | divider_val = 3 ; |
3157 | Fmax = FmaxBin ; | 2980 | Fmax = FmaxBin ; |
3158 | Fmin = FminBin ; | 2981 | Fmin = FminBin ; |
3159 | } | 2982 | } |
3160 | FminBin = 600000000UL ; | 2983 | FminBin = 600000000UL ; |
3161 | FmaxBin = 900000000UL ; | 2984 | FmaxBin = 900000000UL ; |
3162 | if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { | 2985 | if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { |
3163 | status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; | 2986 | status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; |
3164 | status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ; | 2987 | status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ; |
3165 | divider_val = 2 ; | 2988 | divider_val = 2 ; |
3166 | Fmax = FmaxBin ; | 2989 | Fmax = FmaxBin ; |
3167 | Fmin = FminBin ; | 2990 | Fmin = FminBin ; |
3168 | } | 2991 | } |
3169 | 2992 | ||
3170 | // TG_DIV_VAL | 2993 | // TG_DIV_VAL |
3171 | tg_divval = (Tuner->TG_LO*divider_val/100000) | 2994 | tg_divval = (state->TG_LO*divider_val/100000) |
3172 | *(MXL_Ceiling(Tuner->Fxtal,1000000) * 100) / (Tuner->Fxtal/1000) ; | 2995 | *(MXL_Ceiling(state->Fxtal,1000000) * 100) / (state->Fxtal/1000) ; |
3173 | status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval) ; | 2996 | status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval) ; |
3174 | 2997 | ||
3175 | if (Tuner->TG_LO > 600000000UL) | 2998 | if (state->TG_LO > 600000000UL) |
3176 | status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval + 1 ) ; | 2999 | status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1 ) ; |
3177 | 3000 | ||
3178 | Fmax = 1800000000UL ; | 3001 | Fmax = 1800000000UL ; |
3179 | Fmin = 1200000000UL ; | 3002 | Fmin = 1200000000UL ; |
@@ -3181,28 +3004,28 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) | |||
3181 | 3004 | ||
3182 | 3005 | ||
3183 | // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4 | 3006 | // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4 |
3184 | Fref_TG = (Tuner->Fxtal/1000)/ MXL_Ceiling(Tuner->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000 | 3007 | Fref_TG = (state->Fxtal/1000)/ MXL_Ceiling(state->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000 |
3185 | 3008 | ||
3186 | Fvco = (Tuner->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10 | 3009 | Fvco = (state->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10 |
3187 | 3010 | ||
3188 | tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8; | 3011 | tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8; |
3189 | 3012 | ||
3190 | //below equation is same as above but much harder to debug. | 3013 | //below equation is same as above but much harder to debug. |
3191 | //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((Tuner->TG_LO/10000)*divider_val*(Tuner->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ; | 3014 | //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((state->TG_LO/10000)*divider_val*(state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ; |
3192 | 3015 | ||
3193 | 3016 | ||
3194 | status += MXL_ControlWrite(Tuner, TG_VCO_BIAS , tg_lo) ; | 3017 | status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo) ; |
3195 | 3018 | ||
3196 | 3019 | ||
3197 | 3020 | ||
3198 | //add for 2.6.5 | 3021 | //add for 2.6.5 |
3199 | //Special setting for QAM | 3022 | //Special setting for QAM |
3200 | if(Tuner ->Mod_Type == MXL_QAM) | 3023 | if(state->Mod_Type == MXL_QAM) |
3201 | { | 3024 | { |
3202 | if(Tuner->RF_IN < 680000000) | 3025 | if(state->RF_IN < 680000000) |
3203 | status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; | 3026 | status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ; |
3204 | else | 3027 | else |
3205 | status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 2) ; | 3028 | status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2) ; |
3206 | } | 3029 | } |
3207 | 3030 | ||
3208 | 3031 | ||
@@ -3213,673 +3036,675 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) | |||
3213 | // | 3036 | // |
3214 | if (Tuner->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks | 3037 | if (Tuner->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks |
3215 | { | 3038 | { |
3216 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; | 3039 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; |
3217 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; | 3040 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; |
3218 | 3041 | ||
3219 | status += MXL_SetGPIO(Tuner, 3, 1) ; // turn off Bank 1 | 3042 | status += MXL_SetGPIO(fe, 3, 1) ; // turn off Bank 1 |
3220 | status += MXL_SetGPIO(Tuner, 1, 1) ; // turn off Bank 2 | 3043 | status += MXL_SetGPIO(fe, 1, 1) ; // turn off Bank 2 |
3221 | status += MXL_SetGPIO(Tuner, 4, 1) ; // turn off Bank 3 | 3044 | status += MXL_SetGPIO(fe, 4, 1) ; // turn off Bank 3 |
3222 | } | 3045 | } |
3223 | 3046 | ||
3224 | if (Tuner->TF_Type == MXL_TF_C) // Tracking Filter type C | 3047 | if (Tuner->TF_Type == MXL_TF_C) // Tracking Filter type C |
3225 | { | 3048 | { |
3226 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; | 3049 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; |
3227 | status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; | 3050 | status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; |
3228 | 3051 | ||
3229 | if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000) | 3052 | if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) |
3230 | { | 3053 | { |
3231 | 3054 | ||
3232 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off | 3055 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off |
3233 | status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; | 3056 | status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; |
3234 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank1 On | 3057 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank1 On |
3235 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3058 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3236 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off | 3059 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off |
3237 | } | 3060 | } |
3238 | if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000) | 3061 | if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) |
3239 | { | 3062 | { |
3240 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off | 3063 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off |
3241 | status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; | 3064 | status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; |
3242 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off | 3065 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off |
3243 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3066 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3244 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off | 3067 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off |
3245 | } | 3068 | } |
3246 | if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000) | 3069 | if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) |
3247 | { | 3070 | { |
3248 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off | 3071 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off |
3249 | status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; | 3072 | status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; |
3250 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off | 3073 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off |
3251 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3074 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3252 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On | 3075 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On |
3253 | } | 3076 | } |
3254 | if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000) | 3077 | if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) |
3255 | { | 3078 | { |
3256 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off | 3079 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off |
3257 | status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; | 3080 | status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; |
3258 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off | 3081 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off |
3259 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3082 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3260 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On | 3083 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On |
3261 | } | 3084 | } |
3262 | if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000) | 3085 | if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) |
3263 | { | 3086 | { |
3264 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On | 3087 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On |
3265 | status += MXL_ControlWrite(Tuner, DAC_DIN_B, 29) ; | 3088 | status += MXL_ControlWrite(fe, DAC_DIN_B, 29) ; |
3266 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off | 3089 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off |
3267 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3090 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3268 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On | 3091 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On |
3269 | } | 3092 | } |
3270 | if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000) | 3093 | if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) |
3271 | { | 3094 | { |
3272 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On | 3095 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On |
3273 | status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; | 3096 | status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; |
3274 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off | 3097 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off |
3275 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3098 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3276 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On | 3099 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On |
3277 | } | 3100 | } |
3278 | if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000) | 3101 | if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) |
3279 | { | 3102 | { |
3280 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On | 3103 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On |
3281 | status += MXL_ControlWrite(Tuner, DAC_DIN_B, 16) ; | 3104 | status += MXL_ControlWrite(fe, DAC_DIN_B, 16) ; |
3282 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off | 3105 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off |
3283 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3106 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3284 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off | 3107 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off |
3285 | } | 3108 | } |
3286 | if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000) | 3109 | if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) |
3287 | { | 3110 | { |
3288 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On | 3111 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On |
3289 | status += MXL_ControlWrite(Tuner, DAC_DIN_B, 7) ; | 3112 | status += MXL_ControlWrite(fe, DAC_DIN_B, 7) ; |
3290 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off | 3113 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off |
3291 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3114 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3292 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off | 3115 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off |
3293 | } | 3116 | } |
3294 | if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) | 3117 | if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) |
3295 | { | 3118 | { |
3296 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On | 3119 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On |
3297 | status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; | 3120 | status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; |
3298 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off | 3121 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off |
3299 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3122 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3300 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off | 3123 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off |
3301 | } | 3124 | } |
3302 | } | 3125 | } |
3303 | 3126 | ||
3304 | if (Tuner->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only | 3127 | if (Tuner->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only |
3305 | { | 3128 | { |
3306 | status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; | 3129 | status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; |
3307 | 3130 | ||
3308 | if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000) | 3131 | if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) |
3309 | { | 3132 | { |
3310 | 3133 | ||
3311 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off | 3134 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off |
3312 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On | 3135 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On |
3313 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off | 3136 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off |
3314 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off | 3137 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off |
3315 | } | 3138 | } |
3316 | if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000) | 3139 | if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) |
3317 | { | 3140 | { |
3318 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off | 3141 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off |
3319 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3142 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3320 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On | 3143 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On |
3321 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off | 3144 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off |
3322 | } | 3145 | } |
3323 | if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000) | 3146 | if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) |
3324 | { | 3147 | { |
3325 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off | 3148 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off |
3326 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3149 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3327 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On | 3150 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On |
3328 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On | 3151 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On |
3329 | } | 3152 | } |
3330 | if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000) | 3153 | if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) |
3331 | { | 3154 | { |
3332 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off | 3155 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off |
3333 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3156 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3334 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off | 3157 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off |
3335 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On | 3158 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On |
3336 | } | 3159 | } |
3337 | if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000) | 3160 | if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) |
3338 | { | 3161 | { |
3339 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On | 3162 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On |
3340 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3163 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3341 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off | 3164 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off |
3342 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On | 3165 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On |
3343 | } | 3166 | } |
3344 | if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000) | 3167 | if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) |
3345 | { | 3168 | { |
3346 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On | 3169 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On |
3347 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3170 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3348 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off | 3171 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off |
3349 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On | 3172 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On |
3350 | } | 3173 | } |
3351 | if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000) | 3174 | if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) |
3352 | { | 3175 | { |
3353 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On | 3176 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On |
3354 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3177 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3355 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off | 3178 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off |
3356 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off | 3179 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off |
3357 | } | 3180 | } |
3358 | if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000) | 3181 | if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) |
3359 | { | 3182 | { |
3360 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On | 3183 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On |
3361 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3184 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3362 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off | 3185 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off |
3363 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off | 3186 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off |
3364 | } | 3187 | } |
3365 | if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) | 3188 | if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) |
3366 | { | 3189 | { |
3367 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On | 3190 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On |
3368 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3191 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3369 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off | 3192 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off |
3370 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off | 3193 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off |
3371 | } | 3194 | } |
3372 | } | 3195 | } |
3373 | 3196 | ||
3374 | if (Tuner->TF_Type == MXL_TF_D) // Tracking Filter type D | 3197 | if (Tuner->TF_Type == MXL_TF_D) // Tracking Filter type D |
3375 | { | 3198 | { |
3376 | status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; | 3199 | status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; |
3377 | 3200 | ||
3378 | if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) | 3201 | if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) |
3379 | { | 3202 | { |
3380 | 3203 | ||
3381 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3204 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3382 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On | 3205 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On |
3383 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3206 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3384 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3207 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3385 | } | 3208 | } |
3386 | if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) | 3209 | if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) |
3387 | { | 3210 | { |
3388 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3211 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3389 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On | 3212 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On |
3390 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3213 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3391 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3214 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3392 | } | 3215 | } |
3393 | if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000) | 3216 | if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) |
3394 | { | 3217 | { |
3395 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3218 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3396 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3219 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3397 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3220 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3398 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3221 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3399 | } | 3222 | } |
3400 | if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000) | 3223 | if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) |
3401 | { | 3224 | { |
3402 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3225 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3403 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3226 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3404 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3227 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3405 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3228 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3406 | } | 3229 | } |
3407 | if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000) | 3230 | if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) |
3408 | { | 3231 | { |
3409 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3232 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3410 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3233 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3411 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3234 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3412 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3235 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3413 | } | 3236 | } |
3414 | if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) | 3237 | if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) |
3415 | { | 3238 | { |
3416 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On | 3239 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On |
3417 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3240 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3418 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3241 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3419 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3242 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3420 | } | 3243 | } |
3421 | if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000) | 3244 | if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) |
3422 | { | 3245 | { |
3423 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On | 3246 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On |
3424 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3247 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3425 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3248 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3426 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3249 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3427 | } | 3250 | } |
3428 | } | 3251 | } |
3429 | 3252 | ||
3430 | 3253 | ||
3431 | if (Tuner->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 | 3254 | if (Tuner->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 |
3432 | { | 3255 | { |
3433 | status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; | 3256 | status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; |
3434 | 3257 | ||
3435 | // if UHF and terrestrial => Turn off Tracking Filter | 3258 | // if UHF and terrestrial => Turn off Tracking Filter |
3436 | if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) | 3259 | if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0) |
3437 | { | 3260 | { |
3438 | // Turn off all the banks | 3261 | // Turn off all the banks |
3439 | status += MXL_SetGPIO(Tuner, 3, 1) ; | 3262 | status += MXL_SetGPIO(fe, 3, 1) ; |
3440 | status += MXL_SetGPIO(Tuner, 1, 1) ; | 3263 | status += MXL_SetGPIO(fe, 1, 1) ; |
3441 | status += MXL_SetGPIO(Tuner, 4, 1) ; | 3264 | status += MXL_SetGPIO(fe, 4, 1) ; |
3442 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; | 3265 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; |
3443 | 3266 | ||
3444 | status += MXL_ControlWrite(Tuner, AGC_IF, 10) ; | 3267 | status += MXL_ControlWrite(fe, AGC_IF, 10) ; |
3445 | } | 3268 | } |
3446 | 3269 | ||
3447 | else // if VHF or cable => Turn on Tracking Filter | 3270 | else // if VHF or cable => Turn on Tracking Filter |
3448 | { | 3271 | { |
3449 | if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 140000000) | 3272 | if (state->RF_IN >= 43000000 && state->RF_IN < 140000000) |
3450 | { | 3273 | { |
3451 | 3274 | ||
3452 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off | 3275 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off |
3453 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On | 3276 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On |
3454 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3277 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3455 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off | 3278 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off |
3456 | } | 3279 | } |
3457 | if (Tuner->RF_IN >= 140000000 && Tuner->RF_IN < 240000000) | 3280 | if (state->RF_IN >= 140000000 && state->RF_IN < 240000000) |
3458 | { | 3281 | { |
3459 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off | 3282 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off |
3460 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On | 3283 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On |
3461 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3284 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3462 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off | 3285 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off |
3463 | } | 3286 | } |
3464 | if (Tuner->RF_IN >= 240000000 && Tuner->RF_IN < 340000000) | 3287 | if (state->RF_IN >= 240000000 && state->RF_IN < 340000000) |
3465 | { | 3288 | { |
3466 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off | 3289 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off |
3467 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off | 3290 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off |
3468 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 On | 3291 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 On |
3469 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off | 3292 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off |
3470 | } | 3293 | } |
3471 | if (Tuner->RF_IN >= 340000000 && Tuner->RF_IN < 430000000) | 3294 | if (state->RF_IN >= 340000000 && state->RF_IN < 430000000) |
3472 | { | 3295 | { |
3473 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off | 3296 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off |
3474 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off | 3297 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off |
3475 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3298 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3476 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On | 3299 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On |
3477 | } | 3300 | } |
3478 | if (Tuner->RF_IN >= 430000000 && Tuner->RF_IN < 470000000) | 3301 | if (state->RF_IN >= 430000000 && state->RF_IN < 470000000) |
3479 | { | 3302 | { |
3480 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 Off | 3303 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 Off |
3481 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3304 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3482 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off | 3305 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off |
3483 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On | 3306 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On |
3484 | } | 3307 | } |
3485 | if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 570000000) | 3308 | if (state->RF_IN >= 470000000 && state->RF_IN < 570000000) |
3486 | { | 3309 | { |
3487 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On | 3310 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On |
3488 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off | 3311 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off |
3489 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off | 3312 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off |
3490 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On | 3313 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On |
3491 | } | 3314 | } |
3492 | if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 620000000) | 3315 | if (state->RF_IN >= 570000000 && state->RF_IN < 620000000) |
3493 | { | 3316 | { |
3494 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 On | 3317 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 On |
3495 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off | 3318 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off |
3496 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3319 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3497 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Offq | 3320 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Offq |
3498 | } | 3321 | } |
3499 | if (Tuner->RF_IN >= 620000000 && Tuner->RF_IN < 760000000) | 3322 | if (state->RF_IN >= 620000000 && state->RF_IN < 760000000) |
3500 | { | 3323 | { |
3501 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On | 3324 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On |
3502 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off | 3325 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off |
3503 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3326 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3504 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3327 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3505 | } | 3328 | } |
3506 | if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) | 3329 | if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) |
3507 | { | 3330 | { |
3508 | status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On | 3331 | status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On |
3509 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3332 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3510 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3333 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3511 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3334 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3512 | } | 3335 | } |
3513 | } | 3336 | } |
3514 | } | 3337 | } |
3515 | 3338 | ||
3516 | if (Tuner->TF_Type == MXL_TF_E) // Tracking Filter type E | 3339 | if (Tuner->TF_Type == MXL_TF_E) // Tracking Filter type E |
3517 | { | 3340 | { |
3518 | status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; | 3341 | status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; |
3519 | 3342 | ||
3520 | if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) | 3343 | if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) |
3521 | { | 3344 | { |
3522 | 3345 | ||
3523 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3346 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3524 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On | 3347 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On |
3525 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3348 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3526 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3349 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3527 | } | 3350 | } |
3528 | if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) | 3351 | if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) |
3529 | { | 3352 | { |
3530 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3353 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3531 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On | 3354 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On |
3532 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3355 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3533 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3356 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3534 | } | 3357 | } |
3535 | if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000) | 3358 | if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) |
3536 | { | 3359 | { |
3537 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3360 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3538 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3361 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3539 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3362 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3540 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3363 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3541 | } | 3364 | } |
3542 | if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000) | 3365 | if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) |
3543 | { | 3366 | { |
3544 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3367 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3545 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3368 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3546 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3369 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3547 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3370 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3548 | } | 3371 | } |
3549 | if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000) | 3372 | if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) |
3550 | { | 3373 | { |
3551 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3374 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3552 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3375 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3553 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3376 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3554 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3377 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3555 | } | 3378 | } |
3556 | if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) | 3379 | if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) |
3557 | { | 3380 | { |
3558 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On | 3381 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On |
3559 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3382 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3560 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3383 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3561 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3384 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3562 | } | 3385 | } |
3563 | if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000) | 3386 | if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) |
3564 | { | 3387 | { |
3565 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On | 3388 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On |
3566 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3389 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3567 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3390 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3568 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3391 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3569 | } | 3392 | } |
3570 | } | 3393 | } |
3571 | 3394 | ||
3572 | if (Tuner->TF_Type == MXL_TF_F) // Tracking Filter type F | 3395 | if (Tuner->TF_Type == MXL_TF_F) // Tracking Filter type F |
3573 | { | 3396 | { |
3574 | status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; | 3397 | status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; |
3575 | 3398 | ||
3576 | if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 160000000) | 3399 | if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) |
3577 | { | 3400 | { |
3578 | 3401 | ||
3579 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3402 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3580 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On | 3403 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On |
3581 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3404 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3582 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3405 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3583 | } | 3406 | } |
3584 | if (Tuner->RF_IN >= 160000000 && Tuner->RF_IN < 210000000) | 3407 | if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) |
3585 | { | 3408 | { |
3586 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3409 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3587 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On | 3410 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On |
3588 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3411 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3589 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3412 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3590 | } | 3413 | } |
3591 | if (Tuner->RF_IN >= 210000000 && Tuner->RF_IN < 300000000) | 3414 | if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) |
3592 | { | 3415 | { |
3593 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3416 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3594 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3417 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3595 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3418 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3596 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3419 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3597 | } | 3420 | } |
3598 | if (Tuner->RF_IN >= 300000000 && Tuner->RF_IN < 390000000) | 3421 | if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) |
3599 | { | 3422 | { |
3600 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3423 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3601 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3424 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3602 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3425 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3603 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3426 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3604 | } | 3427 | } |
3605 | if (Tuner->RF_IN >= 390000000 && Tuner->RF_IN < 515000000) | 3428 | if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) |
3606 | { | 3429 | { |
3607 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3430 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3608 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3431 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3609 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3432 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3610 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3433 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3611 | } | 3434 | } |
3612 | if (Tuner->RF_IN >= 515000000 && Tuner->RF_IN < 650000000) | 3435 | if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) |
3613 | { | 3436 | { |
3614 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On | 3437 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On |
3615 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3438 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3616 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3439 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3617 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3440 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3618 | } | 3441 | } |
3619 | if (Tuner->RF_IN >= 650000000 && Tuner->RF_IN <= 900000000) | 3442 | if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) |
3620 | { | 3443 | { |
3621 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On | 3444 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On |
3622 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3445 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3623 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3446 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3624 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3447 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3625 | } | 3448 | } |
3626 | } | 3449 | } |
3627 | 3450 | ||
3628 | if (Tuner->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 | 3451 | if (Tuner->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 |
3629 | { | 3452 | { |
3630 | status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; | 3453 | status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; |
3631 | 3454 | ||
3632 | if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) | 3455 | if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) |
3633 | { | 3456 | { |
3634 | 3457 | ||
3635 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3458 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3636 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On | 3459 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On |
3637 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3460 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3638 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3461 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3639 | } | 3462 | } |
3640 | if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) | 3463 | if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) |
3641 | { | 3464 | { |
3642 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3465 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3643 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On | 3466 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On |
3644 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3467 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3645 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3468 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3646 | } | 3469 | } |
3647 | if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000) | 3470 | if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) |
3648 | { | 3471 | { |
3649 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3472 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3650 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3473 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3651 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3474 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3652 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3475 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3653 | } | 3476 | } |
3654 | if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) | 3477 | if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) |
3655 | { | 3478 | { |
3656 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3479 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3657 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3480 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3658 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3481 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3659 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3482 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3660 | } | 3483 | } |
3661 | if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000) | 3484 | if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) |
3662 | { | 3485 | { |
3663 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3486 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3664 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3487 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3665 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3488 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3666 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3489 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3667 | } | 3490 | } |
3668 | if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000) | 3491 | if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) |
3669 | { | 3492 | { |
3670 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On | 3493 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On |
3671 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3494 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3672 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3495 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3673 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3496 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3674 | } | 3497 | } |
3675 | if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000) | 3498 | if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) |
3676 | { | 3499 | { |
3677 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On | 3500 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On |
3678 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3501 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3679 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3502 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3680 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3503 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3681 | } | 3504 | } |
3682 | } | 3505 | } |
3683 | 3506 | ||
3684 | if (Tuner->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 | 3507 | if (Tuner->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 |
3685 | { | 3508 | { |
3686 | status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; | 3509 | status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; |
3687 | 3510 | ||
3688 | if (Tuner->RF_IN >= 50000000 && Tuner->RF_IN < 190000000) | 3511 | if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) |
3689 | { | 3512 | { |
3690 | 3513 | ||
3691 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3514 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3692 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On | 3515 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On |
3693 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3516 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3694 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3517 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3695 | } | 3518 | } |
3696 | if (Tuner->RF_IN >= 190000000 && Tuner->RF_IN < 280000000) | 3519 | if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) |
3697 | { | 3520 | { |
3698 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3521 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3699 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On | 3522 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On |
3700 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3523 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3701 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3524 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3702 | } | 3525 | } |
3703 | if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 350000000) | 3526 | if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) |
3704 | { | 3527 | { |
3705 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3528 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3706 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3529 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3707 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3530 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3708 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3531 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3709 | } | 3532 | } |
3710 | if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) | 3533 | if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) |
3711 | { | 3534 | { |
3712 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3535 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3713 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3536 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3714 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3537 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3715 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3538 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3716 | } | 3539 | } |
3717 | if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 470000000) //modified for 2.6.11 | 3540 | if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) //modified for 2.6.11 |
3718 | { | 3541 | { |
3719 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On | 3542 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On |
3720 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On | 3543 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On |
3721 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off | 3544 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off |
3722 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3545 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3723 | } | 3546 | } |
3724 | if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) | 3547 | if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) |
3725 | { | 3548 | { |
3726 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3549 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3727 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3550 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3728 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3551 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3729 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3552 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3730 | } | 3553 | } |
3731 | if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN < 820000000) | 3554 | if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) |
3732 | { | 3555 | { |
3733 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On | 3556 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On |
3734 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3557 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3735 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3558 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3736 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3559 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3737 | } | 3560 | } |
3738 | if (Tuner->RF_IN >= 820000000 && Tuner->RF_IN <= 900000000) | 3561 | if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) |
3739 | { | 3562 | { |
3740 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On | 3563 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On |
3741 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3564 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3742 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3565 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3743 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3566 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3744 | } | 3567 | } |
3745 | } | 3568 | } |
3746 | 3569 | ||
3747 | if (Tuner->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 | 3570 | if (Tuner->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 |
3748 | { | 3571 | { |
3749 | status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; | 3572 | status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; |
3750 | 3573 | ||
3751 | // if UHF and terrestrial=> Turn off Tracking Filter | 3574 | // if UHF and terrestrial=> Turn off Tracking Filter |
3752 | if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) | 3575 | if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0) |
3753 | { | 3576 | { |
3754 | // Turn off all the banks | 3577 | // Turn off all the banks |
3755 | status += MXL_SetGPIO(Tuner, 3, 1) ; | 3578 | status += MXL_SetGPIO(fe, 3, 1) ; |
3756 | status += MXL_SetGPIO(Tuner, 1, 1) ; | 3579 | status += MXL_SetGPIO(fe, 1, 1) ; |
3757 | status += MXL_SetGPIO(Tuner, 4, 1) ; | 3580 | status += MXL_SetGPIO(fe, 4, 1) ; |
3758 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; | 3581 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; |
3759 | 3582 | ||
3760 | //2.6.12 | 3583 | //2.6.12 |
3761 | //Turn on RSSI | 3584 | //Turn on RSSI |
3762 | status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; | 3585 | status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1) ; |
3763 | status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; | 3586 | status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1) ; |
3764 | status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; | 3587 | status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1) ; |
3765 | status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; | 3588 | status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1) ; |
3766 | 3589 | ||
3767 | // RSSI reference point | 3590 | // RSSI reference point |
3768 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; | 3591 | status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5) ; |
3769 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; | 3592 | status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3) ; |
3770 | status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; | 3593 | status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2) ; |
3771 | 3594 | ||
3772 | 3595 | ||
3773 | //status += MXL_ControlWrite(Tuner, AGC_IF, 10) ; //doesn't matter since RSSI is turn on | 3596 | //status += MXL_ControlWrite(fe, AGC_IF, 10) ; //doesn't matter since RSSI is turn on |
3774 | 3597 | ||
3775 | //following parameter is from analog OTA mode, can be change to seek better performance | 3598 | //following parameter is from analog OTA mode, can be change to seek better performance |
3776 | status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; | 3599 | status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ; |
3777 | } | 3600 | } |
3778 | 3601 | ||
3779 | else //if VHF or Cable => Turn on Tracking Filter | 3602 | else //if VHF or Cable => Turn on Tracking Filter |
3780 | { | 3603 | { |
3781 | //2.6.12 | 3604 | //2.6.12 |
3782 | //Turn off RSSI | 3605 | //Turn off RSSI |
3783 | status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; | 3606 | status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0) ; |
3784 | 3607 | ||
3785 | //change back from above condition | 3608 | //change back from above condition |
3786 | status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ; | 3609 | status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5) ; |
3787 | 3610 | ||
3788 | 3611 | ||
3789 | if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) | 3612 | if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) |
3790 | { | 3613 | { |
3791 | 3614 | ||
3792 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3615 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3793 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On | 3616 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On |
3794 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3617 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3795 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3618 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3796 | } | 3619 | } |
3797 | if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) | 3620 | if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) |
3798 | { | 3621 | { |
3799 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3622 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3800 | status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On | 3623 | status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On |
3801 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3624 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3802 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3625 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3803 | } | 3626 | } |
3804 | if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000) | 3627 | if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) |
3805 | { | 3628 | { |
3806 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3629 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3807 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3630 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3808 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3631 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3809 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3632 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3810 | } | 3633 | } |
3811 | if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) | 3634 | if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) |
3812 | { | 3635 | { |
3813 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3636 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3814 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3637 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3815 | status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On | 3638 | status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On |
3816 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3639 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3817 | } | 3640 | } |
3818 | if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000) | 3641 | if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) |
3819 | { | 3642 | { |
3820 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off | 3643 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off |
3821 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3644 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3822 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3645 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3823 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3646 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3824 | } | 3647 | } |
3825 | if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000) | 3648 | if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) |
3826 | { | 3649 | { |
3827 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On | 3650 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On |
3828 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3651 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3829 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3652 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3830 | status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On | 3653 | status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On |
3831 | } | 3654 | } |
3832 | if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000) | 3655 | if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) |
3833 | { | 3656 | { |
3834 | status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On | 3657 | status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On |
3835 | status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off | 3658 | status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off |
3836 | status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off | 3659 | status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off |
3837 | status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off | 3660 | status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off |
3838 | } | 3661 | } |
3839 | } | 3662 | } |
3840 | } | 3663 | } |
3841 | return status ; | 3664 | return status ; |
3842 | } | 3665 | } |
3843 | 3666 | ||
3844 | u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val) | 3667 | // DONE |
3668 | u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) | ||
3845 | { | 3669 | { |
3846 | u16 status = 0 ; | 3670 | struct mxl5005s_state *state = fe->demodulator_priv; |
3671 | u16 status = 0; | ||
3847 | 3672 | ||
3848 | if (GPIO_Num == 1) | 3673 | if (GPIO_Num == 1) |
3849 | status += MXL_ControlWrite(Tuner, GPIO_1B, GPIO_Val ? 0 : 1) ; | 3674 | status += MXL_ControlWrite(fe, GPIO_1B, GPIO_Val ? 0 : 1); |
3850 | // GPIO2 is not available | 3675 | |
3851 | if (GPIO_Num == 3) | 3676 | /* GPIO2 is not available */ |
3852 | { | 3677 | |
3678 | if (GPIO_Num == 3) { | ||
3853 | if (GPIO_Val == 1) { | 3679 | if (GPIO_Val == 1) { |
3854 | status += MXL_ControlWrite(Tuner, GPIO_3, 0) ; | 3680 | status += MXL_ControlWrite(fe, GPIO_3, 0); |
3855 | status += MXL_ControlWrite(Tuner, GPIO_3B, 0) ; | 3681 | status += MXL_ControlWrite(fe, GPIO_3B, 0); |
3856 | } | 3682 | } |
3857 | if (GPIO_Val == 0) { | 3683 | if (GPIO_Val == 0) { |
3858 | status += MXL_ControlWrite(Tuner, GPIO_3, 1) ; | 3684 | status += MXL_ControlWrite(fe, GPIO_3, 1); |
3859 | status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ; | 3685 | status += MXL_ControlWrite(fe, GPIO_3B, 1); |
3860 | } | 3686 | } |
3861 | if (GPIO_Val == 3) { // tri-state | 3687 | if (GPIO_Val == 3) { /* tri-state */ |
3862 | status += MXL_ControlWrite(Tuner, GPIO_3, 0) ; | 3688 | status += MXL_ControlWrite(fe, GPIO_3, 0); |
3863 | status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ; | 3689 | status += MXL_ControlWrite(fe, GPIO_3B, 1); |
3864 | } | 3690 | } |
3865 | } | 3691 | } |
3866 | if (GPIO_Num == 4) | 3692 | if (GPIO_Num == 4) { |
3867 | { | ||
3868 | if (GPIO_Val == 1) { | 3693 | if (GPIO_Val == 1) { |
3869 | status += MXL_ControlWrite(Tuner, GPIO_4, 0) ; | 3694 | status += MXL_ControlWrite(fe, GPIO_4, 0); |
3870 | status += MXL_ControlWrite(Tuner, GPIO_4B, 0) ; | 3695 | status += MXL_ControlWrite(fe, GPIO_4B, 0); |
3871 | } | 3696 | } |
3872 | if (GPIO_Val == 0) { | 3697 | if (GPIO_Val == 0) { |
3873 | status += MXL_ControlWrite(Tuner, GPIO_4, 1) ; | 3698 | status += MXL_ControlWrite(fe, GPIO_4, 1); |
3874 | status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ; | 3699 | status += MXL_ControlWrite(fe, GPIO_4B, 1); |
3875 | } | 3700 | } |
3876 | if (GPIO_Val == 3) { // tri-state | 3701 | if (GPIO_Val == 3) { /* tri-state */ |
3877 | status += MXL_ControlWrite(Tuner, GPIO_4, 0) ; | 3702 | status += MXL_ControlWrite(fe, GPIO_4, 0); |
3878 | status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ; | 3703 | status += MXL_ControlWrite(fe, GPIO_4B, 1); |
3879 | } | 3704 | } |
3880 | } | 3705 | } |
3881 | 3706 | ||
3882 | return status ; | 3707 | return status; |
3883 | } | 3708 | } |
3884 | 3709 | ||
3885 | /////////////////////////////////////////////////////////////////////////////// | 3710 | /////////////////////////////////////////////////////////////////////////////// |
@@ -3907,17 +3732,19 @@ u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val) | |||
3907 | // >0 : Value exceed maximum allowed for control number // | 3732 | // >0 : Value exceed maximum allowed for control number // |
3908 | // // | 3733 | // // |
3909 | /////////////////////////////////////////////////////////////////////////////// | 3734 | /////////////////////////////////////////////////////////////////////////////// |
3910 | u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value) | 3735 | // DONE |
3736 | u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) | ||
3911 | { | 3737 | { |
3912 | u16 status = 0 ; | 3738 | struct mxl5005s_state *state = fe->demodulator_priv; |
3913 | // Will write ALL Matching Control Name | 3739 | u16 status = 0; |
3914 | status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 1 ) ; // Write Matching INIT Control | 3740 | |
3915 | status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 2 ) ; // Write Matching CH Control | 3741 | /* Will write ALL Matching Control Name */ |
3742 | status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control * | ||
3743 | status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control * | ||
3916 | #ifdef _MXL_INTERNAL | 3744 | #ifdef _MXL_INTERNAL |
3917 | status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 3 ) ; // Write Matching MXL Control | 3745 | status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control * |
3918 | #endif | 3746 | #endif |
3919 | 3747 | return status; | |
3920 | return status ; | ||
3921 | } | 3748 | } |
3922 | 3749 | ||
3923 | /////////////////////////////////////////////////////////////////////////////// | 3750 | /////////////////////////////////////////////////////////////////////////////// |
@@ -3947,105 +3774,86 @@ u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value) | |||
3947 | // 2 : Control name not found // | 3774 | // 2 : Control name not found // |
3948 | // // | 3775 | // // |
3949 | /////////////////////////////////////////////////////////////////////////////// | 3776 | /////////////////////////////////////////////////////////////////////////////// |
3950 | u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 controlNum, u32 value, u16 controlGroup) | 3777 | // DONE |
3778 | u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) | ||
3951 | { | 3779 | { |
3952 | u16 i, j, k ; | 3780 | struct mxl5005s_state *state = fe->demodulator_priv; |
3953 | u32 highLimit ; | 3781 | u16 i, j, k; |
3954 | u32 ctrlVal ; | 3782 | u32 highLimit; |
3783 | u32 ctrlVal; | ||
3955 | 3784 | ||
3956 | if( controlGroup == 1) // Initial Control | 3785 | if (controlGroup == 1) /* Initial Control */ { |
3957 | { | 3786 | |
3958 | for (i=0; i<Tuner->Init_Ctrl_Num ; i++) | 3787 | for (i = 0; i < state->Init_Ctrl_Num; i++) { |
3959 | { | 3788 | |
3960 | if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) | 3789 | if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { |
3961 | { // find the control Name | 3790 | |
3962 | highLimit = 1 << Tuner->Init_Ctrl[i].size ; | 3791 | highLimit = 1 << state->Init_Ctrl[i].size; |
3963 | if ( value < highLimit) | 3792 | if (value < highLimit) { |
3964 | { | 3793 | for (j = 0; j < state->Init_Ctrl[i].size; j++) { |
3965 | for( j=0; j<Tuner->Init_Ctrl[i].size; j++) | 3794 | state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); |
3966 | { | 3795 | MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]), |
3967 | Tuner->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; | 3796 | (u8)(state->Init_Ctrl[i].bit[j]), |
3968 | // change the register map accordingly | 3797 | (u8)((value>>j) & 0x01) ); |
3969 | MXL_RegWriteBit( Tuner, (u8)(Tuner->Init_Ctrl[i].addr[j]), | ||
3970 | (u8)(Tuner->Init_Ctrl[i].bit[j]), | ||
3971 | (u8)((value>>j) & 0x01) ) ; | ||
3972 | } | ||
3973 | ctrlVal = 0 ; | ||
3974 | for(k=0; k<Tuner->Init_Ctrl[i].size; k++) | ||
3975 | { | ||
3976 | ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ; | ||
3977 | } | 3798 | } |
3799 | ctrlVal = 0; | ||
3800 | for (k = 0; k < state->Init_Ctrl[i].size; k++) | ||
3801 | ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); | ||
3978 | } | 3802 | } |
3979 | else | 3803 | else |
3980 | { | 3804 | return -1; |
3981 | return -1 ; | ||
3982 | } | ||
3983 | } | 3805 | } |
3984 | } | 3806 | } |
3985 | } | 3807 | } |
3986 | if ( controlGroup == 2) // Chan change Control | 3808 | if (controlGroup == 2) /* Chan change Control */ { |
3987 | { | 3809 | |
3988 | for (i=0; i<Tuner->CH_Ctrl_Num; i++) | 3810 | for (i = 0; i < state->CH_Ctrl_Num; i++) { |
3989 | { | 3811 | |
3990 | if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) | 3812 | if (controlNum == state->CH_Ctrl[i].Ctrl_Num ) { |
3991 | { // find the control Name | 3813 | |
3992 | highLimit = 1 << Tuner->CH_Ctrl[i].size ; | 3814 | highLimit = 1 << state->CH_Ctrl[i].size; |
3993 | if ( value < highLimit) | 3815 | if (value < highLimit) { |
3994 | { | 3816 | for (j = 0; j < state->CH_Ctrl[i].size; j++) { |
3995 | for( j=0; j<Tuner->CH_Ctrl[i].size; j++) | 3817 | state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); |
3996 | { | 3818 | MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]), |
3997 | Tuner->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; | 3819 | (u8)(state->CH_Ctrl[i].bit[j]), |
3998 | // change the register map accordingly | 3820 | (u8)((value>>j) & 0x01) ); |
3999 | MXL_RegWriteBit( Tuner, (u8)(Tuner->CH_Ctrl[i].addr[j]), | ||
4000 | (u8)(Tuner->CH_Ctrl[i].bit[j]), | ||
4001 | (u8)((value>>j) & 0x01) ) ; | ||
4002 | } | ||
4003 | ctrlVal = 0 ; | ||
4004 | for(k=0; k<Tuner->CH_Ctrl[i].size; k++) | ||
4005 | { | ||
4006 | ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ; | ||
4007 | } | 3821 | } |
3822 | ctrlVal = 0; | ||
3823 | for (k = 0; k < state->CH_Ctrl[i].size; k++) | ||
3824 | ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); | ||
4008 | } | 3825 | } |
4009 | else | 3826 | else |
4010 | { | 3827 | return -1; |
4011 | return -1 ; | ||
4012 | } | ||
4013 | } | 3828 | } |
4014 | } | 3829 | } |
4015 | } | 3830 | } |
4016 | #ifdef _MXL_INTERNAL | 3831 | #ifdef _MXL_INTERNAL |
4017 | if ( controlGroup == 3) // Maxlinear Control | 3832 | if (controlGroup == 3) /* Maxlinear Control */ { |
4018 | { | 3833 | |
4019 | for (i=0; i<Tuner->MXL_Ctrl_Num; i++) | 3834 | for (i = 0; i < state->MXL_Ctrl_Num; i++) { |
4020 | { | 3835 | |
4021 | if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) | 3836 | if (controlNum == state->MXL_Ctrl[i].Ctrl_Num ) { |
4022 | { // find the control Name | 3837 | |
4023 | highLimit = (1 << Tuner->MXL_Ctrl[i].size) ; | 3838 | highLimit = (1 << state->MXL_Ctrl[i].size) ; |
4024 | if ( value < highLimit) | 3839 | if (value < highLimit) { |
4025 | { | 3840 | for (j = 0; j < state->MXL_Ctrl[i].size; j++) { |
4026 | for( j=0; j<Tuner->MXL_Ctrl[i].size; j++) | 3841 | state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); |
4027 | { | 3842 | MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]), |
4028 | Tuner->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; | 3843 | (u8)(state->MXL_Ctrl[i].bit[j]), |
4029 | // change the register map accordingly | 3844 | (u8)((value>>j) & 0x01) ); |
4030 | MXL_RegWriteBit( Tuner, (u8)(Tuner->MXL_Ctrl[i].addr[j]), | ||
4031 | (u8)(Tuner->MXL_Ctrl[i].bit[j]), | ||
4032 | (u8)((value>>j) & 0x01) ) ; | ||
4033 | } | ||
4034 | ctrlVal = 0 ; | ||
4035 | for(k=0; k<Tuner->MXL_Ctrl[i].size; k++) | ||
4036 | { | ||
4037 | ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1 << k) ; | ||
4038 | } | 3845 | } |
3846 | ctrlVal = 0; | ||
3847 | for(k = 0; k < state->MXL_Ctrl[i].size; k++) | ||
3848 | ctrlVal += state->MXL_Ctrl[i].val[k] * (1 << k); | ||
4039 | } | 3849 | } |
4040 | else | 3850 | else |
4041 | { | 3851 | return -1; |
4042 | return -1 ; | ||
4043 | } | ||
4044 | } | 3852 | } |
4045 | } | 3853 | } |
4046 | } | 3854 | } |
4047 | #endif | 3855 | #endif |
4048 | return 0 ; // successful return | 3856 | return 0 ; /* successful return */ |
4049 | } | 3857 | } |
4050 | 3858 | ||
4051 | /////////////////////////////////////////////////////////////////////////////// | 3859 | /////////////////////////////////////////////////////////////////////////////// |
@@ -4073,20 +3881,20 @@ u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 controlNum, u32 value, u16 c | |||
4073 | // -1 : Invalid Register Address // | 3881 | // -1 : Invalid Register Address // |
4074 | // // | 3882 | // // |
4075 | /////////////////////////////////////////////////////////////////////////////// | 3883 | /////////////////////////////////////////////////////////////////////////////// |
4076 | u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal) | 3884 | // DONE |
3885 | u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) | ||
4077 | { | 3886 | { |
3887 | struct mxl5005s_state *state = fe->demodulator_priv; | ||
4078 | int i ; | 3888 | int i ; |
4079 | 3889 | ||
4080 | for (i=0; i<104; i++) | 3890 | for (i = 0; i < 104; i++) { |
4081 | { | 3891 | if (RegNum == state->TunerRegs[i].Reg_Num) { |
4082 | if (RegNum == Tuner->TunerRegs[i].Reg_Num ) | 3892 | state->TunerRegs[i].Reg_Val = RegVal; |
4083 | { | 3893 | return 0; |
4084 | Tuner->TunerRegs[i].Reg_Val = RegVal ; | ||
4085 | return 0 ; | ||
4086 | } | 3894 | } |
4087 | } | 3895 | } |
4088 | 3896 | ||
4089 | return 1 ; | 3897 | return 1; |
4090 | } | 3898 | } |
4091 | 3899 | ||
4092 | /////////////////////////////////////////////////////////////////////////////// | 3900 | /////////////////////////////////////////////////////////////////////////////// |
@@ -4113,20 +3921,20 @@ u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal) | |||
4113 | // -1 : Invalid Register Address // | 3921 | // -1 : Invalid Register Address // |
4114 | // // | 3922 | // // |
4115 | /////////////////////////////////////////////////////////////////////////////// | 3923 | /////////////////////////////////////////////////////////////////////////////// |
4116 | u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal) | 3924 | // DONE |
3925 | u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) | ||
4117 | { | 3926 | { |
3927 | struct mxl5005s_state *state = fe->demodulator_priv; | ||
4118 | int i ; | 3928 | int i ; |
4119 | 3929 | ||
4120 | for (i=0; i<104; i++) | 3930 | for (i = 0; i < 104; i++) { |
4121 | { | 3931 | if (RegNum == state->TunerRegs[i].Reg_Num ) { |
4122 | if (RegNum == Tuner->TunerRegs[i].Reg_Num ) | 3932 | *RegVal = (u8)(state->TunerRegs[i].Reg_Val); |
4123 | { | 3933 | return 0; |
4124 | *RegVal = (u8)(Tuner->TunerRegs[i].Reg_Val) ; | ||
4125 | return 0 ; | ||
4126 | } | 3934 | } |
4127 | } | 3935 | } |
4128 | 3936 | ||
4129 | return 1 ; | 3937 | return 1; |
4130 | } | 3938 | } |
4131 | 3939 | ||
4132 | /////////////////////////////////////////////////////////////////////////////// | 3940 | /////////////////////////////////////////////////////////////////////////////// |
@@ -4150,48 +3958,53 @@ u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal) | |||
4150 | // -1 : Invalid control name // | 3958 | // -1 : Invalid control name // |
4151 | // // | 3959 | // // |
4152 | /////////////////////////////////////////////////////////////////////////////// | 3960 | /////////////////////////////////////////////////////////////////////////////// |
4153 | u16 MXL_ControlRead(Tuner_struct *Tuner, u16 controlNum, u32 * value) | 3961 | // DONE |
3962 | u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 * value) | ||
4154 | { | 3963 | { |
3964 | struct mxl5005s_state *state = fe->demodulator_priv; | ||
4155 | u32 ctrlVal ; | 3965 | u32 ctrlVal ; |
4156 | u16 i, k ; | 3966 | u16 i, k ; |
4157 | 3967 | ||
4158 | for (i=0; i<Tuner->Init_Ctrl_Num ; i++) | 3968 | for (i = 0; i < state->Init_Ctrl_Num ; i++) { |
4159 | { | 3969 | |
4160 | if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) | 3970 | if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { |
4161 | { | 3971 | |
4162 | ctrlVal = 0 ; | 3972 | ctrlVal = 0; |
4163 | for(k=0; k<Tuner->Init_Ctrl[i].size; k++) | 3973 | for (k = 0; k < state->Init_Ctrl[i].size; k++) |
4164 | ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ; | 3974 | ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); |
4165 | *value = ctrlVal ; | 3975 | *value = ctrlVal; |
4166 | return 0 ; | 3976 | return 0; |
4167 | } | 3977 | } |
4168 | } | 3978 | } |
4169 | for (i=0; i<Tuner->CH_Ctrl_Num ; i++) | 3979 | |
4170 | { | 3980 | for (i = 0; i < state->CH_Ctrl_Num ; i++) { |
4171 | if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) | 3981 | |
4172 | { | 3982 | if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { |
4173 | ctrlVal = 0 ; | 3983 | |
4174 | for(k=0; k<Tuner->CH_Ctrl[i].size; k++) | 3984 | ctrlVal = 0; |
4175 | ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ; | 3985 | for (k = 0; k < state->CH_Ctrl[i].size; k++) |
4176 | *value = ctrlVal ; | 3986 | ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); |
4177 | return 0 ; | 3987 | *value = ctrlVal; |
3988 | return 0; | ||
3989 | |||
4178 | } | 3990 | } |
4179 | } | 3991 | } |
4180 | 3992 | ||
4181 | #ifdef _MXL_INTERNAL | 3993 | #ifdef _MXL_INTERNAL |
4182 | for (i=0; i<Tuner->MXL_Ctrl_Num ; i++) | 3994 | for (i = 0; i < state->MXL_Ctrl_Num ; i++) { |
4183 | { | 3995 | |
4184 | if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) | 3996 | if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { |
4185 | { | 3997 | |
4186 | ctrlVal = 0 ; | 3998 | ctrlVal = 0; |
4187 | for(k=0; k<Tuner->MXL_Ctrl[i].size; k++) | 3999 | for (k = 0; k < state->MXL_Ctrl[i].size; k++) |
4188 | ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1<<k) ; | 4000 | ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k); |
4189 | *value = ctrlVal ; | 4001 | *value = ctrlVal; |
4190 | return 0 ; | 4002 | return 0; |
4003 | |||
4191 | } | 4004 | } |
4192 | } | 4005 | } |
4193 | #endif | 4006 | #endif |
4194 | return 1 ; | 4007 | return 1; |
4195 | } | 4008 | } |
4196 | 4009 | ||
4197 | /////////////////////////////////////////////////////////////////////////////// | 4010 | /////////////////////////////////////////////////////////////////////////////// |
@@ -4217,82 +4030,87 @@ u16 MXL_ControlRead(Tuner_struct *Tuner, u16 controlNum, u32 * value) | |||
4217 | // -1 : Invalid control name // | 4030 | // -1 : Invalid control name // |
4218 | // // | 4031 | // // |
4219 | /////////////////////////////////////////////////////////////////////////////// | 4032 | /////////////////////////////////////////////////////////////////////////////// |
4220 | u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 controlNum, u8 *RegNum, int * count) | 4033 | // DONE |
4034 | u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count) | ||
4221 | { | 4035 | { |
4036 | struct mxl5005s_state *state = fe->demodulator_priv; | ||
4222 | u16 i, j, k ; | 4037 | u16 i, j, k ; |
4223 | u16 Count ; | 4038 | u16 Count ; |
4224 | 4039 | ||
4225 | for (i=0; i<Tuner->Init_Ctrl_Num ; i++) | 4040 | for (i = 0; i < state->Init_Ctrl_Num ; i++) { |
4226 | { | 4041 | |
4227 | if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) | 4042 | if ( controlNum == state->Init_Ctrl[i].Ctrl_Num ) { |
4228 | { | 4043 | |
4229 | Count = 1 ; | 4044 | Count = 1; |
4230 | RegNum[0] = (u8)(Tuner->Init_Ctrl[i].addr[0]) ; | 4045 | RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]); |
4046 | |||
4047 | for (k = 1; k < state->Init_Ctrl[i].size; k++) { | ||
4048 | |||
4049 | for (j = 0; j < Count; j++) { | ||
4050 | |||
4051 | if (state->Init_Ctrl[i].addr[k] != RegNum[j]) { | ||
4052 | |||
4053 | Count ++; | ||
4054 | RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]); | ||
4231 | 4055 | ||
4232 | for(k=1; k<Tuner->Init_Ctrl[i].size; k++) | ||
4233 | { | ||
4234 | for (j= 0; j<Count; j++) | ||
4235 | { | ||
4236 | if (Tuner->Init_Ctrl[i].addr[k] != RegNum[j]) | ||
4237 | { | ||
4238 | Count ++ ; | ||
4239 | RegNum[Count-1] = (u8)(Tuner->Init_Ctrl[i].addr[k]) ; | ||
4240 | } | 4056 | } |
4241 | } | 4057 | } |
4242 | 4058 | ||
4243 | } | 4059 | } |
4244 | *count = Count ; | 4060 | *count = Count; |
4245 | return 0 ; | 4061 | return 0; |
4246 | } | 4062 | } |
4247 | } | 4063 | } |
4248 | for (i=0; i<Tuner->CH_Ctrl_Num ; i++) | 4064 | for (i = 0; i < state->CH_Ctrl_Num ; i++) { |
4249 | { | 4065 | |
4250 | if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) | 4066 | if ( controlNum == state->CH_Ctrl[i].Ctrl_Num ) { |
4251 | { | 4067 | |
4252 | Count = 1 ; | 4068 | Count = 1; |
4253 | RegNum[0] = (u8)(Tuner->CH_Ctrl[i].addr[0]) ; | 4069 | RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]); |
4070 | |||
4071 | for (k = 1; k < state->CH_Ctrl[i].size; k++) { | ||
4072 | |||
4073 | for (j= 0; j<Count; j++) { | ||
4074 | |||
4075 | if (state->CH_Ctrl[i].addr[k] != RegNum[j]) { | ||
4076 | |||
4077 | Count ++; | ||
4078 | RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]); | ||
4254 | 4079 | ||
4255 | for(k=1; k<Tuner->CH_Ctrl[i].size; k++) | ||
4256 | { | ||
4257 | for (j= 0; j<Count; j++) | ||
4258 | { | ||
4259 | if (Tuner->CH_Ctrl[i].addr[k] != RegNum[j]) | ||
4260 | { | ||
4261 | Count ++ ; | ||
4262 | RegNum[Count-1] = (u8)(Tuner->CH_Ctrl[i].addr[k]) ; | ||
4263 | } | 4080 | } |
4264 | } | 4081 | } |
4265 | } | 4082 | } |
4266 | *count = Count ; | 4083 | *count = Count; |
4267 | return 0 ; | 4084 | return 0; |
4268 | } | 4085 | } |
4269 | } | 4086 | } |
4270 | #ifdef _MXL_INTERNAL | 4087 | #ifdef _MXL_INTERNAL |
4271 | for (i=0; i<Tuner->MXL_Ctrl_Num ; i++) | 4088 | for (i = 0; i < state->MXL_Ctrl_Num ; i++) { |
4272 | { | 4089 | |
4273 | if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) | 4090 | if ( controlNum == state->MXL_Ctrl[i].Ctrl_Num ) { |
4274 | { | 4091 | |
4275 | Count = 1 ; | 4092 | Count = 1; |
4276 | RegNum[0] = (u8)(Tuner->MXL_Ctrl[i].addr[0]) ; | 4093 | RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]); |
4094 | |||
4095 | for (k = 1; k < state->MXL_Ctrl[i].size; k++) { | ||
4096 | |||
4097 | for (j = 0; j<Count; j++) { | ||
4098 | |||
4099 | if (state->MXL_Ctrl[i].addr[k] != RegNum[j]) { | ||
4100 | |||
4101 | Count ++; | ||
4102 | RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k]; | ||
4277 | 4103 | ||
4278 | for(k=1; k<Tuner->MXL_Ctrl[i].size; k++) | ||
4279 | { | ||
4280 | for (j= 0; j<Count; j++) | ||
4281 | { | ||
4282 | if (Tuner->MXL_Ctrl[i].addr[k] != RegNum[j]) | ||
4283 | { | ||
4284 | Count ++ ; | ||
4285 | RegNum[Count-1] = (u8)Tuner->MXL_Ctrl[i].addr[k] ; | ||
4286 | } | 4104 | } |
4287 | } | 4105 | } |
4288 | } | 4106 | } |
4289 | *count = Count ; | 4107 | *count = Count; |
4290 | return 0 ; | 4108 | return 0; |
4291 | } | 4109 | } |
4292 | } | 4110 | } |
4293 | #endif | 4111 | #endif |
4294 | *count = 0 ; | 4112 | *count = 0; |
4295 | return 1 ; | 4113 | return 1; |
4296 | } | 4114 | } |
4297 | 4115 | ||
4298 | /////////////////////////////////////////////////////////////////////////////// | 4116 | /////////////////////////////////////////////////////////////////////////////// |
@@ -4308,7 +4126,7 @@ u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 controlNum, u8 *RegNum, int * co | |||
4308 | // Inputs: // | 4126 | // Inputs: // |
4309 | // Tuner_struct : structure defined at higher level // | 4127 | // Tuner_struct : structure defined at higher level // |
4310 | // address : register address // | 4128 | // address : register address // |
4311 | // bit : register bit number // | 4129 | // bit : register bit number // |
4312 | // bitVal : register bit value // | 4130 | // bitVal : register bit value // |
4313 | // // | 4131 | // // |
4314 | // Outputs: // | 4132 | // Outputs: // |
@@ -4318,12 +4136,12 @@ u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 controlNum, u8 *RegNum, int * co | |||
4318 | // NONE // | 4136 | // NONE // |
4319 | // // | 4137 | // // |
4320 | /////////////////////////////////////////////////////////////////////////////// | 4138 | /////////////////////////////////////////////////////////////////////////////// |
4321 | 4139 | // DONE | |
4322 | void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal) | 4140 | void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) |
4323 | { | 4141 | { |
4142 | struct mxl5005s_state *state = fe->demodulator_priv; | ||
4324 | int i ; | 4143 | int i ; |
4325 | 4144 | ||
4326 | // Declare Local Constants | ||
4327 | const u8 AND_MAP[8] = { | 4145 | const u8 AND_MAP[8] = { |
4328 | 0xFE, 0xFD, 0xFB, 0xF7, | 4146 | 0xFE, 0xFD, 0xFB, 0xF7, |
4329 | 0xEF, 0xDF, 0xBF, 0x7F } ; | 4147 | 0xEF, 0xDF, 0xBF, 0x7F } ; |
@@ -4332,17 +4150,16 @@ void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal) | |||
4332 | 0x01, 0x02, 0x04, 0x08, | 4150 | 0x01, 0x02, 0x04, 0x08, |
4333 | 0x10, 0x20, 0x40, 0x80 } ; | 4151 | 0x10, 0x20, 0x40, 0x80 } ; |
4334 | 4152 | ||
4335 | for(i=0; i<Tuner->TunerRegs_Num; i++) { | 4153 | for (i = 0; i < state->TunerRegs_Num; i++) { |
4336 | if ( Tuner->TunerRegs[i].Reg_Num == address ) { | 4154 | if (state->TunerRegs[i].Reg_Num == address) { |
4337 | if (bitVal) | 4155 | if (bitVal) |
4338 | Tuner->TunerRegs[i].Reg_Val |= OR_MAP[bit] ; | 4156 | state->TunerRegs[i].Reg_Val |= OR_MAP[bit]; |
4339 | else | 4157 | else |
4340 | Tuner->TunerRegs[i].Reg_Val &= AND_MAP[bit] ; | 4158 | state->TunerRegs[i].Reg_Val &= AND_MAP[bit]; |
4341 | break ; | 4159 | break ; |
4342 | } | 4160 | } |
4343 | } | 4161 | } |
4344 | } ; | 4162 | } |
4345 | |||
4346 | 4163 | ||
4347 | /////////////////////////////////////////////////////////////////////////////// | 4164 | /////////////////////////////////////////////////////////////////////////////// |
4348 | // // | 4165 | // // |
@@ -4367,37 +4184,43 @@ void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal) | |||
4367 | // Computed value // | 4184 | // Computed value // |
4368 | // // | 4185 | // // |
4369 | /////////////////////////////////////////////////////////////////////////////// | 4186 | /////////////////////////////////////////////////////////////////////////////// |
4370 | u32 MXL_Ceiling( u32 value, u32 resolution ) | 4187 | // DONE |
4188 | u32 MXL_Ceiling(u32 value, u32 resolution) | ||
4371 | { | 4189 | { |
4372 | return (value/resolution + (value%resolution > 0 ? 1 : 0)) ; | 4190 | return (value/resolution + (value % resolution > 0 ? 1 : 0)); |
4373 | }; | 4191 | } |
4374 | 4192 | ||
4375 | // | 4193 | // |
4376 | // Retrieve the Initialzation Registers | 4194 | // Retrieve the Initialzation Registers |
4377 | // | 4195 | // |
4378 | u16 MXL_GetInitRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) | 4196 | // DONE |
4197 | u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) | ||
4379 | { | 4198 | { |
4199 | struct mxl5005s_state *state = fe->demodulator_priv; | ||
4380 | u16 status = 0; | 4200 | u16 status = 0; |
4381 | int i ; | 4201 | int i ; |
4382 | 4202 | ||
4383 | u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, | 4203 | u8 RegAddr[] = { |
4384 | 76, 77, 91, 134, 135, 137, 147, | 4204 | 11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, |
4385 | 156, 166, 167, 168, 25 } ; | 4205 | 76, 77, 91, 134, 135, 137, 147, |
4386 | *count = sizeof(RegAddr) / sizeof(u8) ; | 4206 | 156, 166, 167, 168, 25 }; |
4387 | 4207 | ||
4388 | status += MXL_BlockInit(Tuner) ; | 4208 | *count = sizeof(RegAddr) / sizeof(u8); |
4389 | 4209 | ||
4390 | for (i=0 ; i< *count; i++) | 4210 | status += MXL_BlockInit(fe); |
4391 | { | 4211 | |
4392 | RegNum[i] = RegAddr[i] ; | 4212 | for (i = 0 ; i < *count; i++) { |
4393 | status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; | 4213 | RegNum[i] = RegAddr[i]; |
4214 | status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); | ||
4394 | } | 4215 | } |
4395 | 4216 | ||
4396 | return status ; | 4217 | return status; |
4397 | } | 4218 | } |
4398 | 4219 | ||
4399 | u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) | 4220 | // DONE |
4221 | u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) | ||
4400 | { | 4222 | { |
4223 | struct mxl5005s_state *state = fe->demodulator_priv; | ||
4401 | u16 status = 0; | 4224 | u16 status = 0; |
4402 | int i ; | 4225 | int i ; |
4403 | 4226 | ||
@@ -4413,203 +4236,207 @@ u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) | |||
4413 | // RegAddr[i] = i; | 4236 | // RegAddr[i] = i; |
4414 | #endif | 4237 | #endif |
4415 | 4238 | ||
4416 | *count = sizeof(RegAddr) / sizeof(u8) ; | 4239 | *count = sizeof(RegAddr) / sizeof(u8); |
4417 | 4240 | ||
4418 | for (i=0 ; i< *count; i++) | 4241 | for (i = 0 ; i < *count; i++) { |
4419 | { | 4242 | RegNum[i] = RegAddr[i]; |
4420 | RegNum[i] = RegAddr[i] ; | 4243 | status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); |
4421 | status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; | ||
4422 | } | 4244 | } |
4423 | 4245 | ||
4424 | return status ; | 4246 | return status; |
4425 | |||
4426 | } | 4247 | } |
4427 | 4248 | ||
4428 | u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) | 4249 | // DONE |
4250 | u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) | ||
4429 | { | 4251 | { |
4430 | u16 status = 0 ; | 4252 | struct mxl5005s_state *state = fe->demodulator_priv; |
4431 | int i ; | 4253 | u16 status = 0; |
4254 | int i; | ||
4432 | 4255 | ||
4433 | u8 RegAddr[] = {43, 136} ; | 4256 | u8 RegAddr[] = {43, 136}; |
4434 | 4257 | ||
4435 | *count = sizeof(RegAddr) / sizeof(u8) ; | 4258 | *count = sizeof(RegAddr) / sizeof(u8); |
4436 | 4259 | ||
4437 | for (i=0; i<*count; i++) | 4260 | for (i = 0; i < *count; i++) { |
4438 | { | 4261 | RegNum[i] = RegAddr[i]; |
4439 | RegNum[i] = RegAddr[i] ; | 4262 | status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); |
4440 | status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; | ||
4441 | } | 4263 | } |
4442 | return status ; | ||
4443 | 4264 | ||
4265 | return status; | ||
4444 | } | 4266 | } |
4445 | 4267 | ||
4446 | u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) | 4268 | // DONE |
4269 | u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) | ||
4447 | { | 4270 | { |
4448 | u16 status = 0 ; | 4271 | struct mxl5005s_state *state = fe->demodulator_priv; |
4449 | int i ; | 4272 | u16 status = 0; |
4273 | int i; | ||
4450 | 4274 | ||
4451 | u8 RegAddr[] = {138} ; | 4275 | u8 RegAddr[] = { 138 }; |
4452 | 4276 | ||
4453 | *count = sizeof(RegAddr) / sizeof(u8) ; | 4277 | *count = sizeof(RegAddr) / sizeof(u8); |
4454 | 4278 | ||
4455 | for (i=0; i<*count; i++) | 4279 | for (i = 0; i < *count; i++) { |
4456 | { | 4280 | RegNum[i] = RegAddr[i]; |
4457 | RegNum[i] = RegAddr[i] ; | 4281 | status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); |
4458 | status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; | ||
4459 | } | 4282 | } |
4460 | return status ; | ||
4461 | 4283 | ||
4284 | return status; | ||
4462 | } | 4285 | } |
4463 | 4286 | ||
4287 | // DONE | ||
4464 | u16 MXL_GetMasterControl(u8 *MasterReg, int state) | 4288 | u16 MXL_GetMasterControl(u8 *MasterReg, int state) |
4465 | { | 4289 | { |
4466 | if (state == 1) // Load_Start | 4290 | if (state == 1) /* Load_Start */ |
4467 | *MasterReg = 0xF3 ; | 4291 | *MasterReg = 0xF3; |
4468 | if (state == 2) // Power_Down | 4292 | if (state == 2) /* Power_Down */ |
4469 | *MasterReg = 0x41 ; | 4293 | *MasterReg = 0x41; |
4470 | if (state == 3) // Synth_Reset | 4294 | if (state == 3) /* Synth_Reset */ |
4471 | *MasterReg = 0xB1 ; | 4295 | *MasterReg = 0xB1; |
4472 | if (state == 4) // Seq_Off | 4296 | if (state == 4) /* Seq_Off */ |
4473 | *MasterReg = 0xF1 ; | 4297 | *MasterReg = 0xF1; |
4474 | 4298 | ||
4475 | return 0 ; | 4299 | return 0; |
4476 | } | 4300 | } |
4477 | 4301 | ||
4478 | #ifdef _MXL_PRODUCTION | 4302 | #ifdef _MXL_PRODUCTION |
4479 | u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) | 4303 | u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) |
4480 | { | 4304 | { |
4305 | struct mxl5005s_state *state = fe->demodulator_priv; | ||
4481 | u16 status = 0 ; | 4306 | u16 status = 0 ; |
4482 | 4307 | ||
4483 | if (VCO_Range == 1) { | 4308 | if (VCO_Range == 1) { |
4484 | status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); | 4309 | status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); |
4485 | status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); | 4310 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); |
4486 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); | 4311 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); |
4487 | status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); | 4312 | status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); |
4488 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); | 4313 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); |
4489 | status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); | 4314 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); |
4490 | status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); | 4315 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); |
4491 | if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { | 4316 | if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { |
4492 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); | 4317 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); |
4493 | status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); | 4318 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); |
4494 | status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56); | 4319 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); |
4495 | status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224); | 4320 | status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 180224); |
4496 | } | 4321 | } |
4497 | if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { | 4322 | if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { |
4498 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; | 4323 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); |
4499 | status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; | 4324 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); |
4500 | status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; | 4325 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); |
4501 | status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ; | 4326 | status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 222822); |
4502 | } | 4327 | } |
4503 | if (Tuner->Mode == 1) // Digital Mode { | 4328 | if (state->Mode == 1) /* Digital Mode */ { |
4504 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; | 4329 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); |
4505 | status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; | 4330 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); |
4506 | status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; | 4331 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); |
4507 | status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ; | 4332 | status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 229376); |
4508 | } | 4333 | } |
4509 | } | 4334 | } |
4510 | 4335 | ||
4511 | if (VCO_Range == 2) { | 4336 | if (VCO_Range == 2) { |
4512 | status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); | 4337 | status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); |
4513 | status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); | 4338 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); |
4514 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); | 4339 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); |
4515 | status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); | 4340 | status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); |
4516 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); | 4341 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); |
4517 | status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); | 4342 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); |
4518 | status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); | 4343 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); |
4519 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); | 4344 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); |
4520 | status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); | 4345 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); |
4521 | status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41); | 4346 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); |
4522 | if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { | 4347 | if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { |
4523 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); | 4348 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); |
4524 | status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); | 4349 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); |
4525 | status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); | 4350 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); |
4526 | status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); | 4351 | status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); |
4527 | } | 4352 | } |
4528 | if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { | 4353 | if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { |
4529 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); | 4354 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); |
4530 | status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); | 4355 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); |
4531 | status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); | 4356 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); |
4532 | status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); | 4357 | status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); |
4533 | } | 4358 | } |
4534 | if (Tuner->Mode == 1) // Digital Mode { | 4359 | if (state->Mode == 1) /* Digital Mode */ { |
4535 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); | 4360 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); |
4536 | status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); | 4361 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); |
4537 | status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41); | 4362 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); |
4538 | status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384); | 4363 | status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 16384); |
4539 | } | 4364 | } |
4540 | } | 4365 | } |
4541 | 4366 | ||
4542 | if (VCO_Range == 3) { | 4367 | if (VCO_Range == 3) { |
4543 | status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); | 4368 | status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); |
4544 | status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); | 4369 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); |
4545 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); | 4370 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); |
4546 | status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); | 4371 | status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); |
4547 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); | 4372 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); |
4548 | status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); | 4373 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); |
4549 | status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); | 4374 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); |
4550 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); | 4375 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
4551 | status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); | 4376 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); |
4552 | status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); | 4377 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); |
4553 | if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { | 4378 | if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { |
4554 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); | 4379 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
4555 | status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); | 4380 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); |
4556 | status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44); | 4381 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); |
4557 | status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670); | 4382 | status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); |
4558 | } | 4383 | } |
4559 | if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { | 4384 | if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { |
4560 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); | 4385 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
4561 | status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); | 4386 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); |
4562 | status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44); | 4387 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); |
4563 | status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670); | 4388 | status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); |
4564 | } | 4389 | } |
4565 | if (Tuner->Mode == 1) // Digital Mode { | 4390 | if (state->Mode == 1) /* Digital Mode */ { |
4566 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); | 4391 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
4567 | status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); | 4392 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); |
4568 | status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); | 4393 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); |
4569 | status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760); | 4394 | status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 245760); |
4570 | } | 4395 | } |
4571 | } | 4396 | } |
4572 | 4397 | ||
4573 | if (VCO_Range == 4) { | 4398 | if (VCO_Range == 4) { |
4574 | status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); | 4399 | status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); |
4575 | status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); | 4400 | status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); |
4576 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); | 4401 | status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); |
4577 | status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); | 4402 | status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); |
4578 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); | 4403 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); |
4579 | status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); | 4404 | status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); |
4580 | status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); | 4405 | status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); |
4581 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); | 4406 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
4582 | status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); | 4407 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); |
4583 | status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); | 4408 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); |
4584 | if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { | 4409 | if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { |
4585 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); | 4410 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
4586 | status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); | 4411 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); |
4587 | status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); | 4412 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); |
4588 | status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); | 4413 | status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); |
4589 | } | 4414 | } |
4590 | if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { | 4415 | if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { |
4591 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); | 4416 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
4592 | status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); | 4417 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); |
4593 | status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); | 4418 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); |
4594 | status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); | 4419 | status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); |
4595 | } | 4420 | } |
4596 | if (Tuner->Mode == 1) // Digital Mode { | 4421 | if (state->Mode == 1) /* Digital Mode */ { |
4597 | status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); | 4422 | status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); |
4598 | status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); | 4423 | status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); |
4599 | status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); | 4424 | status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); |
4600 | status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992); | 4425 | status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 212992); |
4601 | } | 4426 | } |
4602 | } | 4427 | } |
4603 | 4428 | ||
4604 | return status; | 4429 | return status; |
4605 | } | 4430 | } |
4606 | 4431 | ||
4607 | u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) | 4432 | // DONE |
4433 | u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) | ||
4608 | { | 4434 | { |
4435 | struct mxl5005s_state *state = fe->demodulator_priv; | ||
4609 | u16 status = 0; | 4436 | u16 status = 0; |
4610 | 4437 | ||
4611 | if (Hystersis == 1) | 4438 | if (Hystersis == 1) |
4612 | status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1); | 4439 | status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1); |
4613 | 4440 | ||
4614 | return status; | 4441 | return status; |
4615 | } | 4442 | } |
diff --git a/drivers/media/common/tuners/mxl5005s.h b/drivers/media/common/tuners/mxl5005s.h index 1944d9e94427..df49826816bb 100644 --- a/drivers/media/common/tuners/mxl5005s.h +++ b/drivers/media/common/tuners/mxl5005s.h | |||
@@ -140,61 +140,6 @@ typedef struct _TunerReg_struct | |||
140 | u16 Reg_Val; /* Current sofware programmed value waiting to be writen */ | 140 | u16 Reg_Val; /* Current sofware programmed value waiting to be writen */ |
141 | } TunerReg_struct; | 141 | } TunerReg_struct; |
142 | 142 | ||
143 | /* MXL5005 Tuner Control Struct */ | ||
144 | typedef struct _TunerControl_struct { | ||
145 | u16 Ctrl_Num; /* Control Number */ | ||
146 | u16 size; /* Number of bits to represent Value */ | ||
147 | u16 addr[25]; /* Array of Tuner Register Address for each bit position */ | ||
148 | u16 bit[25]; /* Array of bit position in Register Address for each bit position */ | ||
149 | u16 val[25]; /* Binary representation of Value */ | ||
150 | } TunerControl_struct; | ||
151 | |||
152 | /* MXL5005 Tuner Struct */ | ||
153 | typedef struct _Tuner_struct | ||
154 | { | ||
155 | u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ | ||
156 | u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */ | ||
157 | u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */ | ||
158 | u32 IF_OUT; /* Desired IF Out Frequency */ | ||
159 | u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */ | ||
160 | u32 RF_IN; /* RF Input Frequency */ | ||
161 | u32 Fxtal; /* XTAL Frequency */ | ||
162 | u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */ | ||
163 | u16 TOP; /* Value: take over point */ | ||
164 | u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */ | ||
165 | u8 DIV_OUT; /* 4MHz or 16MHz */ | ||
166 | u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */ | ||
167 | u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */ | ||
168 | u8 Mod_Type; /* Modulation Type; */ | ||
169 | /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ | ||
170 | u8 TF_Type; /* Tracking Filter Type */ | ||
171 | /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ | ||
172 | |||
173 | /* Calculated Settings */ | ||
174 | u32 RF_LO; /* Synth RF LO Frequency */ | ||
175 | u32 IF_LO; /* Synth IF LO Frequency */ | ||
176 | u32 TG_LO; /* Synth TG_LO Frequency */ | ||
177 | |||
178 | /* Pointers to ControlName Arrays */ | ||
179 | u16 Init_Ctrl_Num; /* Number of INIT Control Names */ | ||
180 | TunerControl_struct | ||
181 | Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ | ||
182 | |||
183 | u16 CH_Ctrl_Num; /* Number of CH Control Names */ | ||
184 | TunerControl_struct | ||
185 | CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ | ||
186 | |||
187 | u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ | ||
188 | TunerControl_struct | ||
189 | MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ | ||
190 | |||
191 | /* Pointer to Tuner Register Array */ | ||
192 | u16 TunerRegs_Num; /* Number of Tuner Registers */ | ||
193 | TunerReg_struct | ||
194 | TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ | ||
195 | |||
196 | } Tuner_struct; | ||
197 | |||
198 | typedef enum | 143 | typedef enum |
199 | { | 144 | { |
200 | /* Initialization Control Names */ | 145 | /* Initialization Control Names */ |
@@ -290,60 +235,6 @@ typedef enum | |||
290 | * MaxLinear source code - Common_MXL.h (?) | 235 | * MaxLinear source code - Common_MXL.h (?) |
291 | */ | 236 | */ |
292 | 237 | ||
293 | void InitTunerControls(Tuner_struct *Tuner); | ||
294 | u16 MXL_BlockInit(Tuner_struct *Tuner); | ||
295 | u16 MXL5005_RegisterInit(Tuner_struct *Tuner); | ||
296 | u16 MXL5005_ControlInit(Tuner_struct *Tuner); | ||
297 | #ifdef _MXL_INTERNAL | ||
298 | u16 MXL5005_MXLControlInit(Tuner_struct *Tuner); | ||
299 | #endif | ||
300 | |||
301 | u16 MXL5005_TunerConfig(Tuner_struct *Tuner, | ||
302 | u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ | ||
303 | u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ | ||
304 | u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ | ||
305 | u32 IF_out, /* Desired IF Out Frequency */ | ||
306 | u32 Fxtal, /* XTAL Frequency */ | ||
307 | u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ | ||
308 | u16 TOP, /* 0: Dual AGC; Value: take over point */ | ||
309 | u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ | ||
310 | u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */ | ||
311 | u8 DIV_OUT, /* 4MHz or 16MHz */ | ||
312 | u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ | ||
313 | u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ | ||
314 | u8 Mod_Type, /* Modulation Type; */ | ||
315 | /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ | ||
316 | u8 TF_Type /* Tracking Filter Type */ | ||
317 | /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ | ||
318 | ); | ||
319 | |||
320 | void MXL_SynthIFLO_Calc(Tuner_struct *Tuner); | ||
321 | void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner); | ||
322 | u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal); | ||
323 | u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal); | ||
324 | u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value); | ||
325 | u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 ControlNum, u32 value, u16 controlGroup); | ||
326 | u16 MXL_ControlRead(Tuner_struct *Tuner, u16 ControlNum, u32 * value); | ||
327 | u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 ControlNum, u8 *RegNum, int *count); | ||
328 | void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal); | ||
329 | u16 MXL_IFSynthInit(Tuner_struct * Tuner ); | ||
330 | u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq); | ||
331 | u16 MXL_OverwriteICDefault(Tuner_struct *Tuner); | ||
332 | u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val); | ||
333 | u32 MXL_Ceiling(u32 value, u32 resolution); | ||
334 | u32 MXL_GetXtalInt(u32 Xtal_Freq); | ||
335 | |||
336 | u16 MXL_GetInitRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); | ||
337 | u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); | ||
338 | u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); | ||
339 | u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); | ||
340 | u16 MXL_GetMasterControl(u8 *MasterReg, int state); | ||
341 | |||
342 | #ifdef _MXL_PRODUCTION | ||
343 | u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range); | ||
344 | u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis); | ||
345 | #endif | ||
346 | |||
347 | /* Constants */ | 238 | /* Constants */ |
348 | #define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 | 239 | #define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 |
349 | #define MXL5005S_LATCH_BYTE 0xfe | 240 | #define MXL5005S_LATCH_BYTE 0xfe |
@@ -401,62 +292,6 @@ enum | |||
401 | MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, | 292 | MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, |
402 | }; | 293 | }; |
403 | 294 | ||
404 | /* MxL5005S extra module alias */ | ||
405 | typedef struct MXL5005S_EXTRA_MODULE_TAG MXL5005S_EXTRA_MODULE; | ||
406 | |||
407 | /* MxL5005S register setting function pointer */ | ||
408 | typedef int | ||
409 | (*MXL5005S_FP_SET_REGS_WITH_TABLE)( | ||
410 | struct dvb_usb_device* dib, | ||
411 | TUNER_MODULE *pTuner, | ||
412 | unsigned char *pAddrTable, | ||
413 | unsigned char *pByteTable, | ||
414 | int TableLen | ||
415 | ); | ||
416 | |||
417 | |||
418 | /* MxL5005S register mask bits setting function pointer */ | ||
419 | typedef int | ||
420 | (*MXL5005S_FP_SET_REG_MASK_BITS)( | ||
421 | struct dvb_usb_device* dib, | ||
422 | TUNER_MODULE *pTuner, | ||
423 | unsigned char RegAddr, | ||
424 | unsigned char Msb, | ||
425 | unsigned char Lsb, | ||
426 | const unsigned char WritingValue | ||
427 | ); | ||
428 | |||
429 | /* MxL5005S spectrum mode setting function pointer */ | ||
430 | typedef int | ||
431 | (*MXL5005S_FP_SET_SPECTRUM_MODE)( | ||
432 | struct dvb_usb_device* dib, | ||
433 | TUNER_MODULE *pTuner, | ||
434 | int SpectrumMode | ||
435 | ); | ||
436 | |||
437 | /* MxL5005S bandwidth setting function pointer */ | ||
438 | typedef int | ||
439 | (*MXL5005S_FP_SET_BANDWIDTH_HZ)( | ||
440 | struct dvb_usb_device* dib, | ||
441 | TUNER_MODULE *pTuner, | ||
442 | unsigned long BandwidthHz | ||
443 | ); | ||
444 | |||
445 | /* MxL5005S extra module */ | ||
446 | struct MXL5005S_EXTRA_MODULE_TAG | ||
447 | { | ||
448 | /* MxL5005S function pointers */ | ||
449 | MXL5005S_FP_SET_REGS_WITH_TABLE SetRegsWithTable; | ||
450 | MXL5005S_FP_SET_REG_MASK_BITS SetRegMaskBits; | ||
451 | MXL5005S_FP_SET_SPECTRUM_MODE SetSpectrumMode; | ||
452 | MXL5005S_FP_SET_BANDWIDTH_HZ SetBandwidthHz; | ||
453 | |||
454 | /* MxL5005S extra data */ | ||
455 | unsigned char AgcMasterByte; /* Variable name in MaxLinear source code: AGC_MASTER_BYTE */ | ||
456 | |||
457 | /* MaxLinear defined struct */ | ||
458 | Tuner_struct MxlDefinedTunerStructure; | ||
459 | }; | ||
460 | /* End of common_mxl.h (?) */ | 295 | /* End of common_mxl.h (?) */ |
461 | 296 | ||
462 | #endif /* __MXL5005S_H */ | 297 | #endif /* __MXL5005S_H */ |