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-rw-r--r--drivers/mmc/host/sdhci.h138
-rw-r--r--include/linux/mmc/sdhci.h144
2 files changed, 151 insertions, 131 deletions
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 112543ae36c9..410ee8aa04d4 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -1,6 +1,8 @@
1/* 1/*
2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
3 * 3 *
4 * Header file for Host Controller registers and I/O accessors.
5 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 6 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 * 7 *
6 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
@@ -8,14 +10,16 @@
8 * the Free Software Foundation; either version 2 of the License, or (at 10 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version. 11 * your option) any later version.
10 */ 12 */
11#ifndef __SDHCI_H 13#ifndef __SDHCI_HW_H
12#define __SDHCI_H 14#define __SDHCI_HW_H
13 15
14#include <linux/scatterlist.h> 16#include <linux/scatterlist.h>
15#include <linux/compiler.h> 17#include <linux/compiler.h>
16#include <linux/types.h> 18#include <linux/types.h>
17#include <linux/io.h> 19#include <linux/io.h>
18 20
21#include <linux/mmc/sdhci.h>
22
19/* 23/*
20 * Controller registers 24 * Controller registers
21 */ 25 */
@@ -192,134 +196,6 @@
192#define SDHCI_MAX_DIV_SPEC_200 256 196#define SDHCI_MAX_DIV_SPEC_200 256
193#define SDHCI_MAX_DIV_SPEC_300 2046 197#define SDHCI_MAX_DIV_SPEC_300 2046
194 198
195struct sdhci_ops;
196
197struct sdhci_host {
198 /* Data set by hardware interface driver */
199 const char *hw_name; /* Hardware bus name */
200
201 unsigned int quirks; /* Deviations from spec. */
202
203/* Controller doesn't honor resets unless we touch the clock register */
204#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
205/* Controller has bad caps bits, but really supports DMA */
206#define SDHCI_QUIRK_FORCE_DMA (1<<1)
207/* Controller doesn't like to be reset when there is no card inserted. */
208#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
209/* Controller doesn't like clearing the power reg before a change */
210#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
211/* Controller has flaky internal state so reset it on each ios change */
212#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
213/* Controller has an unusable DMA engine */
214#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
215/* Controller has an unusable ADMA engine */
216#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
217/* Controller can only DMA from 32-bit aligned addresses */
218#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
219/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
220#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
221/* Controller can only ADMA chunks that are a multiple of 32 bits */
222#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
223/* Controller needs to be reset after each request to stay stable */
224#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
225/* Controller needs voltage and power writes to happen separately */
226#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
227/* Controller provides an incorrect timeout value for transfers */
228#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
229/* Controller has an issue with buffer bits for small transfers */
230#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
231/* Controller does not provide transfer-complete interrupt when not busy */
232#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
233/* Controller has unreliable card detection */
234#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
235/* Controller reports inverted write-protect state */
236#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
237/* Controller has nonstandard clock management */
238#define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17)
239/* Controller does not like fast PIO transfers */
240#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
241/* Controller losing signal/interrupt enable states after reset */
242#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19)
243/* Controller has to be forced to use block size of 2048 bytes */
244#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
245/* Controller cannot do multi-block transfers */
246#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
247/* Controller can only handle 1-bit data transfers */
248#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
249/* Controller needs 10ms delay between applying power and clock */
250#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
251/* Controller uses SDCLK instead of TMCLK for data timeouts */
252#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
253/* Controller reports wrong base clock capability */
254#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
255/* Controller cannot support End Attribute in NOP ADMA descriptor */
256#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
257/* Controller is missing device caps. Use caps provided by host */
258#define SDHCI_QUIRK_MISSING_CAPS (1<<27)
259/* Controller uses Auto CMD12 command to stop the transfer */
260#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
261/* Controller doesn't have HISPD bit field in HI-SPEED SD card */
262#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
263
264 int irq; /* Device IRQ */
265 void __iomem * ioaddr; /* Mapped address */
266
267 const struct sdhci_ops *ops; /* Low level hw interface */
268
269 struct regulator *vmmc; /* Power regulator */
270
271 /* Internal data */
272 struct mmc_host *mmc; /* MMC structure */
273 u64 dma_mask; /* custom DMA mask */
274
275#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
276 struct led_classdev led; /* LED control */
277 char led_name[32];
278#endif
279
280 spinlock_t lock; /* Mutex */
281
282 int flags; /* Host attributes */
283#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
284#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
285#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
286#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
287
288 unsigned int version; /* SDHCI spec. version */
289
290 unsigned int max_clk; /* Max possible freq (MHz) */
291 unsigned int timeout_clk; /* Timeout freq (KHz) */
292
293 unsigned int clock; /* Current clock (MHz) */
294 u8 pwr; /* Current voltage */
295
296 struct mmc_request *mrq; /* Current request */
297 struct mmc_command *cmd; /* Current command */
298 struct mmc_data *data; /* Current data request */
299 unsigned int data_early:1; /* Data finished before cmd */
300
301 struct sg_mapping_iter sg_miter; /* SG state for PIO */
302 unsigned int blocks; /* remaining PIO blocks */
303
304 int sg_count; /* Mapped sg entries */
305
306 u8 *adma_desc; /* ADMA descriptor table */
307 u8 *align_buffer; /* Bounce buffer */
308
309 dma_addr_t adma_addr; /* Mapped ADMA descr. table */
310 dma_addr_t align_addr; /* Mapped bounce buffer */
311
312 struct tasklet_struct card_tasklet; /* Tasklet structures */
313 struct tasklet_struct finish_tasklet;
314
315 struct timer_list timer; /* Timer for timeouts */
316
317 unsigned int caps; /* Alternative capabilities */
318
319 unsigned long private[0] ____cacheline_aligned;
320};
321
322
323struct sdhci_ops { 199struct sdhci_ops {
324#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 200#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
325 u32 (*read_l)(struct sdhci_host *host, int reg); 201 u32 (*read_l)(struct sdhci_host *host, int reg);
@@ -440,4 +316,4 @@ extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
440extern int sdhci_resume_host(struct sdhci_host *host); 316extern int sdhci_resume_host(struct sdhci_host *host);
441#endif 317#endif
442 318
443#endif /* __SDHCI_H */ 319#endif /* __SDHCI_HW_H */
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
new file mode 100644
index 000000000000..1fdc673f2396
--- /dev/null
+++ b/include/linux/mmc/sdhci.h
@@ -0,0 +1,144 @@
1/*
2 * linux/include/linux/mmc/sdhci.h - Secure Digital Host Controller Interface
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 */
11#ifndef __SDHCI_H
12#define __SDHCI_H
13
14#include <linux/scatterlist.h>
15#include <linux/compiler.h>
16#include <linux/types.h>
17#include <linux/io.h>
18#include <linux/mmc/host.h>
19
20struct sdhci_host {
21 /* Data set by hardware interface driver */
22 const char *hw_name; /* Hardware bus name */
23
24 unsigned int quirks; /* Deviations from spec. */
25
26/* Controller doesn't honor resets unless we touch the clock register */
27#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
28/* Controller has bad caps bits, but really supports DMA */
29#define SDHCI_QUIRK_FORCE_DMA (1<<1)
30/* Controller doesn't like to be reset when there is no card inserted. */
31#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
32/* Controller doesn't like clearing the power reg before a change */
33#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
34/* Controller has flaky internal state so reset it on each ios change */
35#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
36/* Controller has an unusable DMA engine */
37#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
38/* Controller has an unusable ADMA engine */
39#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
40/* Controller can only DMA from 32-bit aligned addresses */
41#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
42/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
43#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
44/* Controller can only ADMA chunks that are a multiple of 32 bits */
45#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
46/* Controller needs to be reset after each request to stay stable */
47#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
48/* Controller needs voltage and power writes to happen separately */
49#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
50/* Controller provides an incorrect timeout value for transfers */
51#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
52/* Controller has an issue with buffer bits for small transfers */
53#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
54/* Controller does not provide transfer-complete interrupt when not busy */
55#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
56/* Controller has unreliable card detection */
57#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
58/* Controller reports inverted write-protect state */
59#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
60/* Controller has nonstandard clock management */
61#define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17)
62/* Controller does not like fast PIO transfers */
63#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
64/* Controller losing signal/interrupt enable states after reset */
65#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19)
66/* Controller has to be forced to use block size of 2048 bytes */
67#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
68/* Controller cannot do multi-block transfers */
69#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
70/* Controller can only handle 1-bit data transfers */
71#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
72/* Controller needs 10ms delay between applying power and clock */
73#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
74/* Controller uses SDCLK instead of TMCLK for data timeouts */
75#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
76/* Controller reports wrong base clock capability */
77#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
78/* Controller cannot support End Attribute in NOP ADMA descriptor */
79#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
80/* Controller is missing device caps. Use caps provided by host */
81#define SDHCI_QUIRK_MISSING_CAPS (1<<27)
82/* Controller uses Auto CMD12 command to stop the transfer */
83#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
84/* Controller doesn't have HISPD bit field in HI-SPEED SD card */
85#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
86
87 int irq; /* Device IRQ */
88 void __iomem *ioaddr; /* Mapped address */
89
90 const struct sdhci_ops *ops; /* Low level hw interface */
91
92 struct regulator *vmmc; /* Power regulator */
93
94 /* Internal data */
95 struct mmc_host *mmc; /* MMC structure */
96 u64 dma_mask; /* custom DMA mask */
97
98#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
99 struct led_classdev led; /* LED control */
100 char led_name[32];
101#endif
102
103 spinlock_t lock; /* Mutex */
104
105 int flags; /* Host attributes */
106#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
107#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
108#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
109#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
110
111 unsigned int version; /* SDHCI spec. version */
112
113 unsigned int max_clk; /* Max possible freq (MHz) */
114 unsigned int timeout_clk; /* Timeout freq (KHz) */
115
116 unsigned int clock; /* Current clock (MHz) */
117 u8 pwr; /* Current voltage */
118
119 struct mmc_request *mrq; /* Current request */
120 struct mmc_command *cmd; /* Current command */
121 struct mmc_data *data; /* Current data request */
122 unsigned int data_early:1; /* Data finished before cmd */
123
124 struct sg_mapping_iter sg_miter; /* SG state for PIO */
125 unsigned int blocks; /* remaining PIO blocks */
126
127 int sg_count; /* Mapped sg entries */
128
129 u8 *adma_desc; /* ADMA descriptor table */
130 u8 *align_buffer; /* Bounce buffer */
131
132 dma_addr_t adma_addr; /* Mapped ADMA descr. table */
133 dma_addr_t align_addr; /* Mapped bounce buffer */
134
135 struct tasklet_struct card_tasklet; /* Tasklet structures */
136 struct tasklet_struct finish_tasklet;
137
138 struct timer_list timer; /* Timer for timeouts */
139
140 unsigned int caps; /* Alternative capabilities */
141
142 unsigned long private[0] ____cacheline_aligned;
143};
144#endif /* __SDHCI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 20:41:28 -0500