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-rw-r--r--drivers/gpu/drm/radeon/evergreen.c150
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h46
-rw-r--r--drivers/gpu/drm/radeon/ni.c3
3 files changed, 198 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index d0aef76121d5..c6bbf6216498 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -136,6 +136,7 @@ static u32 sumo_rlc_save_restore_register_list_size = ARRAY_SIZE(sumo_rlc_save_r
136static void evergreen_gpu_init(struct radeon_device *rdev); 136static void evergreen_gpu_init(struct radeon_device *rdev);
137void evergreen_fini(struct radeon_device *rdev); 137void evergreen_fini(struct radeon_device *rdev);
138void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 138void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
139void evergreen_program_aspm(struct radeon_device *rdev);
139extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 140extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
140 int ring, u32 cp_int_cntl); 141 int ring, u32 cp_int_cntl);
141 142
@@ -5071,6 +5072,8 @@ static int evergreen_startup(struct radeon_device *rdev)
5071 5072
5072 /* enable pcie gen2 link */ 5073 /* enable pcie gen2 link */
5073 evergreen_pcie_gen2_enable(rdev); 5074 evergreen_pcie_gen2_enable(rdev);
5075 /* enable aspm */
5076 evergreen_program_aspm(rdev);
5074 5077
5075 if (ASIC_IS_DCE5(rdev)) { 5078 if (ASIC_IS_DCE5(rdev)) {
5076 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { 5079 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
@@ -5468,3 +5471,150 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
5468 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 5471 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
5469 } 5472 }
5470} 5473}
5474
5475void evergreen_program_aspm(struct radeon_device *rdev)
5476{
5477 u32 data, orig;
5478 u32 pcie_lc_cntl, pcie_lc_cntl_old;
5479 bool disable_l0s, disable_l1 = false, disable_plloff_in_l1 = false;
5480 /* fusion_platform = true
5481 * if the system is a fusion system
5482 * (APU or DGPU in a fusion system).
5483 * todo: check if the system is a fusion platform.
5484 */
5485 bool fusion_platform = false;
5486
5487 if (!(rdev->flags & RADEON_IS_PCIE))
5488 return;
5489
5490 switch (rdev->family) {
5491 case CHIP_CYPRESS:
5492 case CHIP_HEMLOCK:
5493 case CHIP_JUNIPER:
5494 case CHIP_REDWOOD:
5495 case CHIP_CEDAR:
5496 case CHIP_SUMO:
5497 case CHIP_SUMO2:
5498 case CHIP_PALM:
5499 case CHIP_ARUBA:
5500 disable_l0s = true;
5501 break;
5502 default:
5503 disable_l0s = false;
5504 break;
5505 }
5506
5507 if (rdev->flags & RADEON_IS_IGP)
5508 fusion_platform = true; /* XXX also dGPUs in a fusion system */
5509
5510 data = orig = RREG32_PIF_PHY0(PB0_PIF_PAIRING);
5511 if (fusion_platform)
5512 data &= ~MULTI_PIF;
5513 else
5514 data |= MULTI_PIF;
5515 if (data != orig)
5516 WREG32_PIF_PHY0(PB0_PIF_PAIRING, data);
5517
5518 data = orig = RREG32_PIF_PHY1(PB1_PIF_PAIRING);
5519 if (fusion_platform)
5520 data &= ~MULTI_PIF;
5521 else
5522 data |= MULTI_PIF;
5523 if (data != orig)
5524 WREG32_PIF_PHY1(PB1_PIF_PAIRING, data);
5525
5526 pcie_lc_cntl = pcie_lc_cntl_old = RREG32_PCIE_PORT(PCIE_LC_CNTL);
5527 pcie_lc_cntl &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
5528 if (!disable_l0s) {
5529 if (rdev->family >= CHIP_BARTS)
5530 pcie_lc_cntl |= LC_L0S_INACTIVITY(7);
5531 else
5532 pcie_lc_cntl |= LC_L0S_INACTIVITY(3);
5533 }
5534
5535 if (!disable_l1) {
5536 if (rdev->family >= CHIP_BARTS)
5537 pcie_lc_cntl |= LC_L1_INACTIVITY(7);
5538 else
5539 pcie_lc_cntl |= LC_L1_INACTIVITY(8);
5540
5541 if (!disable_plloff_in_l1) {
5542 data = orig = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);
5543 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
5544 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
5545 if (data != orig)
5546 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);
5547
5548 data = orig = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);
5549 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
5550 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
5551 if (data != orig)
5552 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);
5553
5554 data = orig = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);
5555 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
5556 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
5557 if (data != orig)
5558 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);
5559
5560 data = orig = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);
5561 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
5562 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
5563 if (data != orig)
5564 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);
5565
5566 if (rdev->family >= CHIP_BARTS) {
5567 data = orig = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);
5568 data &= ~PLL_RAMP_UP_TIME_0_MASK;
5569 data |= PLL_RAMP_UP_TIME_0(4);
5570 if (data != orig)
5571 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);
5572
5573 data = orig = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);
5574 data &= ~PLL_RAMP_UP_TIME_1_MASK;
5575 data |= PLL_RAMP_UP_TIME_1(4);
5576 if (data != orig)
5577 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);
5578
5579 data = orig = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);
5580 data &= ~PLL_RAMP_UP_TIME_0_MASK;
5581 data |= PLL_RAMP_UP_TIME_0(4);
5582 if (data != orig)
5583 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);
5584
5585 data = orig = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);
5586 data &= ~PLL_RAMP_UP_TIME_1_MASK;
5587 data |= PLL_RAMP_UP_TIME_1(4);
5588 if (data != orig)
5589 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);
5590 }
5591
5592 data = orig = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
5593 data &= ~LC_DYN_LANES_PWR_STATE_MASK;
5594 data |= LC_DYN_LANES_PWR_STATE(3);
5595 if (data != orig)
5596 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
5597
5598 if (rdev->family >= CHIP_BARTS) {
5599 data = orig = RREG32_PIF_PHY0(PB0_PIF_CNTL);
5600 data &= ~LS2_EXIT_TIME_MASK;
5601 data |= LS2_EXIT_TIME(1);
5602 if (data != orig)
5603 WREG32_PIF_PHY0(PB0_PIF_CNTL, data);
5604
5605 data = orig = RREG32_PIF_PHY1(PB1_PIF_CNTL);
5606 data &= ~LS2_EXIT_TIME_MASK;
5607 data |= LS2_EXIT_TIME(1);
5608 if (data != orig)
5609 WREG32_PIF_PHY1(PB1_PIF_CNTL, data);
5610 }
5611 }
5612 }
5613
5614 /* evergreen parts only */
5615 if (rdev->family < CHIP_BARTS)
5616 pcie_lc_cntl |= LC_PMI_TO_L1_DIS;
5617
5618 if (pcie_lc_cntl != pcie_lc_cntl_old)
5619 WREG32_PCIE_PORT(PCIE_LC_CNTL, pcie_lc_cntl);
5620}
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 35e61539b5f8..c0df1cac9485 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -1323,7 +1323,48 @@
1323#define DMA_PACKET_CONSTANT_FILL 0xd 1323#define DMA_PACKET_CONSTANT_FILL 0xd
1324#define DMA_PACKET_NOP 0xf 1324#define DMA_PACKET_NOP 0xf
1325 1325
1326/* PCIE link stuff */ 1326/* PIF PHY0 indirect regs */
1327#define PB0_PIF_CNTL 0x10
1328# define LS2_EXIT_TIME(x) ((x) << 17)
1329# define LS2_EXIT_TIME_MASK (0x7 << 17)
1330# define LS2_EXIT_TIME_SHIFT 17
1331#define PB0_PIF_PAIRING 0x11
1332# define MULTI_PIF (1 << 25)
1333#define PB0_PIF_PWRDOWN_0 0x12
1334# define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
1335# define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
1336# define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
1337# define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
1338# define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
1339# define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
1340# define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
1341# define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
1342# define PLL_RAMP_UP_TIME_0_SHIFT 24
1343#define PB0_PIF_PWRDOWN_1 0x13
1344# define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
1345# define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
1346# define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
1347# define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
1348# define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
1349# define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
1350# define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
1351# define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
1352# define PLL_RAMP_UP_TIME_1_SHIFT 24
1353/* PIF PHY1 indirect regs */
1354#define PB1_PIF_CNTL 0x10
1355#define PB1_PIF_PAIRING 0x11
1356#define PB1_PIF_PWRDOWN_0 0x12
1357#define PB1_PIF_PWRDOWN_1 0x13
1358/* PCIE PORT indirect regs */
1359#define PCIE_LC_CNTL 0xa0
1360# define LC_L0S_INACTIVITY(x) ((x) << 8)
1361# define LC_L0S_INACTIVITY_MASK (0xf << 8)
1362# define LC_L0S_INACTIVITY_SHIFT 8
1363# define LC_L1_INACTIVITY(x) ((x) << 12)
1364# define LC_L1_INACTIVITY_MASK (0xf << 12)
1365# define LC_L1_INACTIVITY_SHIFT 12
1366# define LC_PMI_TO_L1_DIS (1 << 16)
1367# define LC_ASPM_TO_L1_DIS (1 << 24)
1327#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 1368#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
1328#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 1369#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
1329# define LC_LINK_WIDTH_SHIFT 0 1370# define LC_LINK_WIDTH_SHIFT 0
@@ -1343,6 +1384,9 @@
1343# define LC_SHORT_RECONFIG_EN (1 << 11) 1384# define LC_SHORT_RECONFIG_EN (1 << 11)
1344# define LC_UPCONFIGURE_SUPPORT (1 << 12) 1385# define LC_UPCONFIGURE_SUPPORT (1 << 12)
1345# define LC_UPCONFIGURE_DIS (1 << 13) 1386# define LC_UPCONFIGURE_DIS (1 << 13)
1387# define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
1388# define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
1389# define LC_DYN_LANES_PWR_STATE_SHIFT 21
1346#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 1390#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
1347# define LC_GEN2_EN_STRAP (1 << 0) 1391# define LC_GEN2_EN_STRAP (1 << 0)
1348# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 1392# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index ad65143232c0..cafc3bd78a38 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -173,6 +173,7 @@ extern void evergreen_irq_suspend(struct radeon_device *rdev);
173extern int evergreen_mc_init(struct radeon_device *rdev); 173extern int evergreen_mc_init(struct radeon_device *rdev);
174extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 174extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
175extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 175extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
176extern void evergreen_program_aspm(struct radeon_device *rdev);
176extern void sumo_rlc_fini(struct radeon_device *rdev); 177extern void sumo_rlc_fini(struct radeon_device *rdev);
177extern int sumo_rlc_init(struct radeon_device *rdev); 178extern int sumo_rlc_init(struct radeon_device *rdev);
178 179
@@ -2076,6 +2077,8 @@ static int cayman_startup(struct radeon_device *rdev)
2076 2077
2077 /* enable pcie gen2 link */ 2078 /* enable pcie gen2 link */
2078 evergreen_pcie_gen2_enable(rdev); 2079 evergreen_pcie_gen2_enable(rdev);
2080 /* enable aspm */
2081 evergreen_program_aspm(rdev);
2079 2082
2080 if (rdev->flags & RADEON_IS_IGP) { 2083 if (rdev->flags & RADEON_IS_IGP) {
2081 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 2084 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 06:19:58 -0500