diff options
-rw-r--r-- | arch/arm/mach-at91/at91cap9.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-at91/at91sam9260.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-at91/at91sam9261.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-at91/at91sam9263.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-at91/at91sam9_alt_reset.S | 7 | ||||
-rw-r--r-- | arch/arm/mach-at91/at91sam9g45.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-at91/at91sam9rl.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-at91/generic.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_rstc.h | 18 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91cap9.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9260.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9261.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9263.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9g45.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9rl.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-at91/pm.c | 9 | ||||
-rw-r--r-- | arch/arm/mach-at91/setup.c | 9 |
17 files changed, 42 insertions, 20 deletions
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c index edb879ac04c8..7a2309e0d984 100644 --- a/arch/arm/mach-at91/at91cap9.c +++ b/arch/arm/mach-at91/at91cap9.c | |||
@@ -331,6 +331,7 @@ static void __init at91cap9_map_io(void) | |||
331 | static void __init at91cap9_ioremap_registers(void) | 331 | static void __init at91cap9_ioremap_registers(void) |
332 | { | 332 | { |
333 | at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC); | 333 | at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC); |
334 | at91_ioremap_rstc(AT91CAP9_BASE_RSTC); | ||
334 | at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT); | 335 | at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT); |
335 | at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC); | 336 | at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC); |
336 | } | 337 | } |
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 5e46e4a96430..d4036ba43612 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c | |||
@@ -323,6 +323,7 @@ static void __init at91sam9260_map_io(void) | |||
323 | static void __init at91sam9260_ioremap_registers(void) | 323 | static void __init at91sam9260_ioremap_registers(void) |
324 | { | 324 | { |
325 | at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC); | 325 | at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC); |
326 | at91_ioremap_rstc(AT91SAM9260_BASE_RSTC); | ||
326 | at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); | 327 | at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); |
327 | at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); | 328 | at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); |
328 | } | 329 | } |
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index b85b9ea60170..023c2ff138df 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c | |||
@@ -281,6 +281,7 @@ static void __init at91sam9261_map_io(void) | |||
281 | static void __init at91sam9261_ioremap_registers(void) | 281 | static void __init at91sam9261_ioremap_registers(void) |
282 | { | 282 | { |
283 | at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC); | 283 | at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC); |
284 | at91_ioremap_rstc(AT91SAM9261_BASE_RSTC); | ||
284 | at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); | 285 | at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); |
285 | at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); | 286 | at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); |
286 | } | 287 | } |
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 79e3669b1117..75e876c258af 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c | |||
@@ -301,6 +301,7 @@ static void __init at91sam9263_map_io(void) | |||
301 | static void __init at91sam9263_ioremap_registers(void) | 301 | static void __init at91sam9263_ioremap_registers(void) |
302 | { | 302 | { |
303 | at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC); | 303 | at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC); |
304 | at91_ioremap_rstc(AT91SAM9263_BASE_RSTC); | ||
304 | at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT); | 305 | at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT); |
305 | at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0); | 306 | at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0); |
306 | at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1); | 307 | at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1); |
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S index d3f931c5942e..518e42377171 100644 --- a/arch/arm/mach-at91/at91sam9_alt_reset.S +++ b/arch/arm/mach-at91/at91sam9_alt_reset.S | |||
@@ -23,7 +23,8 @@ | |||
23 | .globl at91sam9_alt_restart | 23 | .globl at91sam9_alt_restart |
24 | 24 | ||
25 | at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants | 25 | at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants |
26 | ldr r1, .at91_va_base_rstc_cr | 26 | ldr r1, =at91_rstc_base |
27 | ldr r1, [r1] | ||
27 | 28 | ||
28 | mov r2, #1 | 29 | mov r2, #1 |
29 | mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN | 30 | mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN |
@@ -33,11 +34,9 @@ at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants | |||
33 | 34 | ||
34 | str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access | 35 | str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access |
35 | str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM | 36 | str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM |
36 | str r4, [r1] @ reset processor | 37 | str r4, [r1, #AT91_RSTC_CR] @ reset processor |
37 | 38 | ||
38 | b . | 39 | b . |
39 | 40 | ||
40 | .at91_va_base_sdramc: | 41 | .at91_va_base_sdramc: |
41 | .word AT91_VA_BASE_SYS + AT91_SDRAMC0 | 42 | .word AT91_VA_BASE_SYS + AT91_SDRAMC0 |
42 | .at91_va_base_rstc_cr: | ||
43 | .word AT91_VA_BASE_SYS + AT91_RSTC_CR | ||
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 7032dd32cdf0..ec6a2db9ea69 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c | |||
@@ -336,6 +336,7 @@ static void __init at91sam9g45_map_io(void) | |||
336 | static void __init at91sam9g45_ioremap_registers(void) | 336 | static void __init at91sam9g45_ioremap_registers(void) |
337 | { | 337 | { |
338 | at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC); | 338 | at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC); |
339 | at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC); | ||
339 | at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); | 340 | at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); |
340 | at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); | 341 | at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); |
341 | } | 342 | } |
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index d6bcb1da11df..d2c91a841cb8 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c | |||
@@ -286,6 +286,7 @@ static void __init at91sam9rl_map_io(void) | |||
286 | static void __init at91sam9rl_ioremap_registers(void) | 286 | static void __init at91sam9rl_ioremap_registers(void) |
287 | { | 287 | { |
288 | at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC); | 288 | at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC); |
289 | at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC); | ||
289 | at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); | 290 | at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); |
290 | at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); | 291 | at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); |
291 | } | 292 | } |
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 4866b8180d66..62e508b71ec2 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h | |||
@@ -58,6 +58,7 @@ extern void at91_irq_suspend(void); | |||
58 | extern void at91_irq_resume(void); | 58 | extern void at91_irq_resume(void); |
59 | 59 | ||
60 | /* reset */ | 60 | /* reset */ |
61 | extern void at91_ioremap_rstc(u32 base_addr); | ||
61 | extern void at91sam9_alt_restart(char, const char *); | 62 | extern void at91sam9_alt_restart(char, const char *); |
62 | 63 | ||
63 | /* shutdown */ | 64 | /* shutdown */ |
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h index cbd2bf052c1f..875fa336800b 100644 --- a/arch/arm/mach-at91/include/mach/at91_rstc.h +++ b/arch/arm/mach-at91/include/mach/at91_rstc.h | |||
@@ -16,13 +16,25 @@ | |||
16 | #ifndef AT91_RSTC_H | 16 | #ifndef AT91_RSTC_H |
17 | #define AT91_RSTC_H | 17 | #define AT91_RSTC_H |
18 | 18 | ||
19 | #define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ | 19 | #ifndef __ASSEMBLY__ |
20 | extern void __iomem *at91_rstc_base; | ||
21 | |||
22 | #define at91_rstc_read(field) \ | ||
23 | __raw_readl(at91_rstc_base + field) | ||
24 | |||
25 | #define at91_rstc_write(field, value) \ | ||
26 | __raw_writel(value, at91_rstc_base + field); | ||
27 | #else | ||
28 | .extern at91_rstc_base | ||
29 | #endif | ||
30 | |||
31 | #define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */ | ||
20 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ | 32 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ |
21 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ | 33 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ |
22 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ | 34 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ |
23 | #define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ | 35 | #define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ |
24 | 36 | ||
25 | #define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ | 37 | #define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */ |
26 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ | 38 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ |
27 | #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ | 39 | #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ |
28 | #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) | 40 | #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) |
@@ -33,7 +45,7 @@ | |||
33 | #define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ | 45 | #define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ |
34 | #define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ | 46 | #define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ |
35 | 47 | ||
36 | #define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ | 48 | #define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */ |
37 | #define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ | 49 | #define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ |
38 | #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ | 50 | #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ |
39 | #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ | 51 | #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ |
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h index 4c0e2f6011d7..61d952902f2b 100644 --- a/arch/arm/mach-at91/include/mach/at91cap9.h +++ b/arch/arm/mach-at91/include/mach/at91cap9.h | |||
@@ -83,7 +83,6 @@ | |||
83 | #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) | 83 | #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) |
84 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) | 84 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) |
85 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 85 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
86 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
87 | #define AT91_GPBR (cpu_is_at91cap9_revB() ? \ | 86 | #define AT91_GPBR (cpu_is_at91cap9_revB() ? \ |
88 | (0xfffffd50 - AT91_BASE_SYS) : \ | 87 | (0xfffffd50 - AT91_BASE_SYS) : \ |
89 | (0xfffffd60 - AT91_BASE_SYS)) | 88 | (0xfffffd60 - AT91_BASE_SYS)) |
@@ -96,6 +95,7 @@ | |||
96 | #define AT91CAP9_BASE_PIOB 0xfffff400 | 95 | #define AT91CAP9_BASE_PIOB 0xfffff400 |
97 | #define AT91CAP9_BASE_PIOC 0xfffff600 | 96 | #define AT91CAP9_BASE_PIOC 0xfffff600 |
98 | #define AT91CAP9_BASE_PIOD 0xfffff800 | 97 | #define AT91CAP9_BASE_PIOD 0xfffff800 |
98 | #define AT91CAP9_BASE_RSTC 0xfffffd00 | ||
99 | #define AT91CAP9_BASE_SHDWC 0xfffffd10 | 99 | #define AT91CAP9_BASE_SHDWC 0xfffffd10 |
100 | #define AT91CAP9_BASE_RTT 0xfffffd20 | 100 | #define AT91CAP9_BASE_RTT 0xfffffd20 |
101 | #define AT91CAP9_BASE_PIT 0xfffffd30 | 101 | #define AT91CAP9_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index f937c476bb67..fa5ca278adeb 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h | |||
@@ -83,7 +83,6 @@ | |||
83 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) | 83 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) |
84 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | 84 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) |
85 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 85 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
86 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
87 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | 86 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) |
88 | 87 | ||
89 | #define AT91SAM9260_BASE_ECC 0xffffe800 | 88 | #define AT91SAM9260_BASE_ECC 0xffffe800 |
@@ -92,6 +91,7 @@ | |||
92 | #define AT91SAM9260_BASE_PIOA 0xfffff400 | 91 | #define AT91SAM9260_BASE_PIOA 0xfffff400 |
93 | #define AT91SAM9260_BASE_PIOB 0xfffff600 | 92 | #define AT91SAM9260_BASE_PIOB 0xfffff600 |
94 | #define AT91SAM9260_BASE_PIOC 0xfffff800 | 93 | #define AT91SAM9260_BASE_PIOC 0xfffff800 |
94 | #define AT91SAM9260_BASE_RSTC 0xfffffd00 | ||
95 | #define AT91SAM9260_BASE_SHDWC 0xfffffd10 | 95 | #define AT91SAM9260_BASE_SHDWC 0xfffffd10 |
96 | #define AT91SAM9260_BASE_RTT 0xfffffd20 | 96 | #define AT91SAM9260_BASE_RTT 0xfffffd20 |
97 | #define AT91SAM9260_BASE_PIT 0xfffffd30 | 97 | #define AT91SAM9260_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index 175604e261be..7cde2d36570e 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h | |||
@@ -68,7 +68,6 @@ | |||
68 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) | 68 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) |
69 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | 69 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) |
70 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 70 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
71 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
72 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | 71 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) |
73 | 72 | ||
74 | #define AT91SAM9261_BASE_SMC 0xffffec00 | 73 | #define AT91SAM9261_BASE_SMC 0xffffec00 |
@@ -76,6 +75,7 @@ | |||
76 | #define AT91SAM9261_BASE_PIOA 0xfffff400 | 75 | #define AT91SAM9261_BASE_PIOA 0xfffff400 |
77 | #define AT91SAM9261_BASE_PIOB 0xfffff600 | 76 | #define AT91SAM9261_BASE_PIOB 0xfffff600 |
78 | #define AT91SAM9261_BASE_PIOC 0xfffff800 | 77 | #define AT91SAM9261_BASE_PIOC 0xfffff800 |
78 | #define AT91SAM9261_BASE_RSTC 0xfffffd00 | ||
79 | #define AT91SAM9261_BASE_SHDWC 0xfffffd10 | 79 | #define AT91SAM9261_BASE_SHDWC 0xfffffd10 |
80 | #define AT91SAM9261_BASE_RTT 0xfffffd20 | 80 | #define AT91SAM9261_BASE_RTT 0xfffffd20 |
81 | #define AT91SAM9261_BASE_PIT 0xfffffd30 | 81 | #define AT91SAM9261_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h index 80c915002d83..5949abda962b 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h | |||
@@ -78,7 +78,6 @@ | |||
78 | #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) | 78 | #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) |
79 | #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) | 79 | #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) |
80 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 80 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
81 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
82 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | 81 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
83 | 82 | ||
84 | #define AT91SAM9263_BASE_ECC0 0xffffe000 | 83 | #define AT91SAM9263_BASE_ECC0 0xffffe000 |
@@ -91,6 +90,7 @@ | |||
91 | #define AT91SAM9263_BASE_PIOC 0xfffff600 | 90 | #define AT91SAM9263_BASE_PIOC 0xfffff600 |
92 | #define AT91SAM9263_BASE_PIOD 0xfffff800 | 91 | #define AT91SAM9263_BASE_PIOD 0xfffff800 |
93 | #define AT91SAM9263_BASE_PIOE 0xfffffa00 | 92 | #define AT91SAM9263_BASE_PIOE 0xfffffa00 |
93 | #define AT91SAM9263_BASE_RSTC 0xfffffd00 | ||
94 | #define AT91SAM9263_BASE_SHDWC 0xfffffd10 | 94 | #define AT91SAM9263_BASE_SHDWC 0xfffffd10 |
95 | #define AT91SAM9263_BASE_RTT0 0xfffffd20 | 95 | #define AT91SAM9263_BASE_RTT0 0xfffffd20 |
96 | #define AT91SAM9263_BASE_PIT 0xfffffd30 | 96 | #define AT91SAM9263_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index f0c23c960dec..dd9c95ea0862 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h | |||
@@ -90,7 +90,6 @@ | |||
90 | #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) | 90 | #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) |
91 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) | 91 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) |
92 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 92 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
93 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
94 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | 93 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
95 | 94 | ||
96 | #define AT91SAM9G45_BASE_ECC 0xffffe200 | 95 | #define AT91SAM9G45_BASE_ECC 0xffffe200 |
@@ -102,6 +101,7 @@ | |||
102 | #define AT91SAM9G45_BASE_PIOC 0xfffff600 | 101 | #define AT91SAM9G45_BASE_PIOC 0xfffff600 |
103 | #define AT91SAM9G45_BASE_PIOD 0xfffff800 | 102 | #define AT91SAM9G45_BASE_PIOD 0xfffff800 |
104 | #define AT91SAM9G45_BASE_PIOE 0xfffffa00 | 103 | #define AT91SAM9G45_BASE_PIOE 0xfffffa00 |
104 | #define AT91SAM9G45_BASE_RSTC 0xfffffd00 | ||
105 | #define AT91SAM9G45_BASE_SHDWC 0xfffffd10 | 105 | #define AT91SAM9G45_BASE_SHDWC 0xfffffd10 |
106 | #define AT91SAM9G45_BASE_RTT 0xfffffd20 | 106 | #define AT91SAM9G45_BASE_RTT 0xfffffd20 |
107 | #define AT91SAM9G45_BASE_PIT 0xfffffd30 | 107 | #define AT91SAM9G45_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index 2bb359e60b97..d7bead7118da 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h | |||
@@ -72,7 +72,6 @@ | |||
72 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) | 72 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) |
73 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | 73 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) |
74 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | 74 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
75 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
76 | #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) | 75 | #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) |
77 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | 76 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) |
78 | 77 | ||
@@ -84,6 +83,7 @@ | |||
84 | #define AT91SAM9RL_BASE_PIOB 0xfffff600 | 83 | #define AT91SAM9RL_BASE_PIOB 0xfffff600 |
85 | #define AT91SAM9RL_BASE_PIOC 0xfffff800 | 84 | #define AT91SAM9RL_BASE_PIOC 0xfffff800 |
86 | #define AT91SAM9RL_BASE_PIOD 0xfffffa00 | 85 | #define AT91SAM9RL_BASE_PIOD 0xfffffa00 |
86 | #define AT91SAM9RL_BASE_RSTC 0xfffffd00 | ||
87 | #define AT91SAM9RL_BASE_SHDWC 0xfffffd10 | 87 | #define AT91SAM9RL_BASE_SHDWC 0xfffffd10 |
88 | #define AT91SAM9RL_BASE_RTT 0xfffffd20 | 88 | #define AT91SAM9RL_BASE_RTT 0xfffffd20 |
89 | #define AT91SAM9RL_BASE_PIT 0xfffffd30 | 89 | #define AT91SAM9RL_BASE_PIT 0xfffffd30 |
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 62ad95556c36..1606379ac284 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c | |||
@@ -34,7 +34,6 @@ | |||
34 | /* | 34 | /* |
35 | * Show the reason for the previous system reset. | 35 | * Show the reason for the previous system reset. |
36 | */ | 36 | */ |
37 | #if defined(AT91_RSTC) | ||
38 | 37 | ||
39 | #include <mach/at91_rstc.h> | 38 | #include <mach/at91_rstc.h> |
40 | #include <mach/at91_shdwc.h> | 39 | #include <mach/at91_shdwc.h> |
@@ -58,10 +57,10 @@ static void __init show_reset_status(void) | |||
58 | char *reason, *r2 = reset; | 57 | char *reason, *r2 = reset; |
59 | u32 reset_type, wake_type; | 58 | u32 reset_type, wake_type; |
60 | 59 | ||
61 | if (!at91_shdwc_base) | 60 | if (!at91_shdwc_base || !at91_rstc_base) |
62 | return; | 61 | return; |
63 | 62 | ||
64 | reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP; | 63 | reset_type = at91_rstc_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP; |
65 | wake_type = at91_shdwc_read(AT91_SHDW_SR); | 64 | wake_type = at91_shdwc_read(AT91_SHDW_SR); |
66 | 65 | ||
67 | switch (reset_type) { | 66 | switch (reset_type) { |
@@ -102,10 +101,6 @@ static void __init show_reset_status(void) | |||
102 | } | 101 | } |
103 | pr_info("AT91: Starting after %s %s\n", reason, r2); | 102 | pr_info("AT91: Starting after %s %s\n", reason, r2); |
104 | } | 103 | } |
105 | #else | ||
106 | static void __init show_reset_status(void) {} | ||
107 | #endif | ||
108 | |||
109 | 104 | ||
110 | static int at91_pm_valid_state(suspend_state_t state) | 105 | static int at91_pm_valid_state(suspend_state_t state) |
111 | { | 106 | { |
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index f524718d14fe..69d3fc4c46f3 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c | |||
@@ -284,6 +284,15 @@ void __init at91_ioremap_shdwc(u32 base_addr) | |||
284 | pm_power_off = at91sam9_poweroff; | 284 | pm_power_off = at91sam9_poweroff; |
285 | } | 285 | } |
286 | 286 | ||
287 | void __iomem *at91_rstc_base; | ||
288 | |||
289 | void __init at91_ioremap_rstc(u32 base_addr) | ||
290 | { | ||
291 | at91_rstc_base = ioremap(base_addr, 16); | ||
292 | if (!at91_rstc_base) | ||
293 | panic("Impossible to ioremap at91_rstc_base\n"); | ||
294 | } | ||
295 | |||
287 | void __init at91_initialize(unsigned long main_clock) | 296 | void __init at91_initialize(unsigned long main_clock) |
288 | { | 297 | { |
289 | at91_boot_soc.ioremap_registers(); | 298 | at91_boot_soc.ioremap_registers(); |