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-rw-r--r--arch/arm/kernel/entry-armv.S14
-rw-r--r--arch/arm/mm/abort-ev4.S11
-rw-r--r--arch/arm/mm/abort-ev4t.S11
-rw-r--r--arch/arm/mm/abort-ev5t.S11
-rw-r--r--arch/arm/mm/abort-ev5tj.S13
-rw-r--r--arch/arm/mm/abort-ev6.S13
-rw-r--r--arch/arm/mm/abort-ev7.S15
-rw-r--r--arch/arm/mm/abort-lv4t.S43
-rw-r--r--arch/arm/mm/abort-macro.S4
-rw-r--r--arch/arm/mm/abort-nommu.S8
-rw-r--r--arch/arm/mm/proc-arm6_7.S29
11 files changed, 73 insertions, 99 deletions
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 85298c093256..bbdd443b8055 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -60,6 +60,7 @@
60 @ 60 @
61 @ Call the processor-specific abort handler: 61 @ Call the processor-specific abort handler:
62 @ 62 @
63 @ r2 - pt_regs
63 @ r4 - aborted context pc 64 @ r4 - aborted context pc
64 @ r5 - aborted context psr 65 @ r5 - aborted context psr
65 @ 66 @
@@ -186,13 +187,8 @@ ENDPROC(__und_invalid)
186 .align 5 187 .align 5
187__dabt_svc: 188__dabt_svc:
188 svc_entry 189 svc_entry
189 dabt_helper
190
191 @
192 @ call main handler
193 @
194 mov r2, sp 190 mov r2, sp
195 bl do_DataAbort 191 dabt_helper
196 192
197 @ 193 @
198 @ IRQs off again before pulling preserved data off the stack 194 @ IRQs off again before pulling preserved data off the stack
@@ -407,11 +403,9 @@ ENDPROC(__pabt_svc)
407__dabt_usr: 403__dabt_usr:
408 usr_entry 404 usr_entry
409 kuser_cmpxchg_check 405 kuser_cmpxchg_check
410 dabt_helper
411
412 mov r2, sp 406 mov r2, sp
413 adr lr, BSYM(ret_from_exception) 407 dabt_helper
414 b do_DataAbort 408 b ret_from_exception
415 UNWIND(.fnend ) 409 UNWIND(.fnend )
416ENDPROC(__dabt_usr) 410ENDPROC(__dabt_usr)
417 411
diff --git a/arch/arm/mm/abort-ev4.S b/arch/arm/mm/abort-ev4.S
index beb112bdc049..54473cd4aba9 100644
--- a/arch/arm/mm/abort-ev4.S
+++ b/arch/arm/mm/abort-ev4.S
@@ -3,14 +3,11 @@
3/* 3/*
4 * Function: v4_early_abort 4 * Function: v4_early_abort
5 * 5 *
6 * Params : r4 = aborted context pc 6 * Params : r2 = pt_regs
7 * : r4 = aborted context pc
7 * : r5 = aborted context psr 8 * : r5 = aborted context psr
8 * 9 *
9 * Returns : r0 = address of abort 10 * Returns : r4 - r11, r13 preserved
10 * : r1 = FSR, bit 11 = write
11 * : r2-r8 = corrupted
12 * : r9 = preserved
13 * : sp = pointer to registers
14 * 11 *
15 * Purpose : obtain information about current aborted instruction. 12 * Purpose : obtain information about current aborted instruction.
16 * Note: we read user space. This means we might cause a data 13 * Note: we read user space. This means we might cause a data
@@ -25,4 +22,4 @@ ENTRY(v4_early_abort)
25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR 22 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
26 tst r3, #1 << 20 @ L = 1 -> write? 23 tst r3, #1 << 20 @ L = 1 -> write?
27 orreq r1, r1, #1 << 11 @ yes. 24 orreq r1, r1, #1 << 11 @ yes.
28 mov pc, lr 25 b do_DataAbort
diff --git a/arch/arm/mm/abort-ev4t.S b/arch/arm/mm/abort-ev4t.S
index eaa4ac023959..9da704e7b86e 100644
--- a/arch/arm/mm/abort-ev4t.S
+++ b/arch/arm/mm/abort-ev4t.S
@@ -4,14 +4,11 @@
4/* 4/*
5 * Function: v4t_early_abort 5 * Function: v4t_early_abort
6 * 6 *
7 * Params : r4 = aborted context pc 7 * Params : r2 = pt_regs
8 * : r4 = aborted context pc
8 * : r5 = aborted context psr 9 * : r5 = aborted context psr
9 * 10 *
10 * Returns : r0 = address of abort 11 * Returns : r4 - r11, r13 preserved
11 * : r1 = FSR, bit 11 = write
12 * : r2-r8 = corrupted
13 * : r9 = preserved
14 * : sp = pointer to registers
15 * 12 *
16 * Purpose : obtain information about current aborted instruction. 13 * Purpose : obtain information about current aborted instruction.
17 * Note: we read user space. This means we might cause a data 14 * Note: we read user space. This means we might cause a data
@@ -27,4 +24,4 @@ ENTRY(v4t_early_abort)
27 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR 24 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
28 tst r3, #1 << 20 @ check write 25 tst r3, #1 << 20 @ check write
29 orreq r1, r1, #1 << 11 26 orreq r1, r1, #1 << 11
30 mov pc, lr 27 b do_DataAbort
diff --git a/arch/arm/mm/abort-ev5t.S b/arch/arm/mm/abort-ev5t.S
index 751391a5de59..a0908d4653a3 100644
--- a/arch/arm/mm/abort-ev5t.S
+++ b/arch/arm/mm/abort-ev5t.S
@@ -4,14 +4,11 @@
4/* 4/*
5 * Function: v5t_early_abort 5 * Function: v5t_early_abort
6 * 6 *
7 * Params : r4 = aborted context pc 7 * Params : r2 = pt_regs
8 * : r4 = aborted context pc
8 * : r5 = aborted context psr 9 * : r5 = aborted context psr
9 * 10 *
10 * Returns : r0 = address of abort 11 * Returns : r4 - r11, r13 preserved
11 * : r1 = FSR, bit 11 = write
12 * : r2-r8 = corrupted
13 * : r9 = preserved
14 * : sp = pointer to registers
15 * 12 *
16 * Purpose : obtain information about current aborted instruction. 13 * Purpose : obtain information about current aborted instruction.
17 * Note: we read user space. This means we might cause a data 14 * Note: we read user space. This means we might cause a data
@@ -28,4 +25,4 @@ ENTRY(v5t_early_abort)
28 do_ldrd_abort tmp=ip, insn=r3 25 do_ldrd_abort tmp=ip, insn=r3
29 tst r3, #1 << 20 @ check write 26 tst r3, #1 << 20 @ check write
30 orreq r1, r1, #1 << 11 27 orreq r1, r1, #1 << 11
31 mov pc, lr 28 b do_DataAbort
diff --git a/arch/arm/mm/abort-ev5tj.S b/arch/arm/mm/abort-ev5tj.S
index ccfbc937054d..4006b7a61264 100644
--- a/arch/arm/mm/abort-ev5tj.S
+++ b/arch/arm/mm/abort-ev5tj.S
@@ -4,14 +4,11 @@
4/* 4/*
5 * Function: v5tj_early_abort 5 * Function: v5tj_early_abort
6 * 6 *
7 * Params : r4 = aborted context pc 7 * Params : r2 = pt_regs
8 * : r4 = aborted context pc
8 * : r5 = aborted context psr 9 * : r5 = aborted context psr
9 * 10 *
10 * Returns : r0 = address of abort 11 * Returns : r4 - r11, r13 preserved
11 * : r1 = FSR, bit 11 = write
12 * : r2-r8 = corrupted
13 * : r9 = preserved
14 * : sp = pointer to registers
15 * 12 *
16 * Purpose : obtain information about current aborted instruction. 13 * Purpose : obtain information about current aborted instruction.
17 * Note: we read user space. This means we might cause a data 14 * Note: we read user space. This means we might cause a data
@@ -24,10 +21,10 @@ ENTRY(v5tj_early_abort)
24 mrc p15, 0, r0, c6, c0, 0 @ get FAR 21 mrc p15, 0, r0, c6, c0, 0 @ get FAR
25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR 22 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
26 tst r5, #PSR_J_BIT @ Java? 23 tst r5, #PSR_J_BIT @ Java?
27 movne pc, lr 24 bne do_DataAbort
28 do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3 25 do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
29 ldreq r3, [r4] @ read aborted ARM instruction 26 ldreq r3, [r4] @ read aborted ARM instruction
30 do_ldrd_abort tmp=ip, insn=r3 27 do_ldrd_abort tmp=ip, insn=r3
31 tst r3, #1 << 20 @ L = 0 -> write 28 tst r3, #1 << 20 @ L = 0 -> write
32 orreq r1, r1, #1 << 11 @ yes. 29 orreq r1, r1, #1 << 11 @ yes.
33 mov pc, lr 30 b do_DataAbort
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index b64d886c0be7..ff1f7cc11f87 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -4,14 +4,11 @@
4/* 4/*
5 * Function: v6_early_abort 5 * Function: v6_early_abort
6 * 6 *
7 * Params : r4 = aborted context pc 7 * Params : r2 = pt_regs
8 * : r4 = aborted context pc
8 * : r5 = aborted context psr 9 * : r5 = aborted context psr
9 * 10 *
10 * Returns : r0 = address of abort 11 * Returns : r4 - r11, r13 preserved
11 * : r1 = FSR, bit 11 = write
12 * : r2-r8 = corrupted
13 * : r9 = preserved
14 * : sp = pointer to registers
15 * 12 *
16 * Purpose : obtain information about current aborted instruction. 13 * Purpose : obtain information about current aborted instruction.
17 * Note: we read user space. This means we might cause a data 14 * Note: we read user space. This means we might cause a data
@@ -34,7 +31,7 @@ ENTRY(v6_early_abort)
34 */ 31 */
35 bic r1, r1, #1 << 11 @ clear bit 11 of FSR 32 bic r1, r1, #1 << 11 @ clear bit 11 of FSR
36 tst r5, #PSR_J_BIT @ Java? 33 tst r5, #PSR_J_BIT @ Java?
37 movne pc, lr 34 bne do_DataAbort
38 do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3 35 do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
39 ldreq r3, [r4] @ read aborted ARM instruction 36 ldreq r3, [r4] @ read aborted ARM instruction
40#ifdef CONFIG_CPU_ENDIAN_BE8 37#ifdef CONFIG_CPU_ENDIAN_BE8
@@ -43,4 +40,4 @@ ENTRY(v6_early_abort)
43 do_ldrd_abort tmp=ip, insn=r3 40 do_ldrd_abort tmp=ip, insn=r3
44 tst r3, #1 << 20 @ L = 0 -> write 41 tst r3, #1 << 20 @ L = 0 -> write
45 orreq r1, r1, #1 << 11 @ yes. 42 orreq r1, r1, #1 << 11 @ yes.
46 mov pc, lr 43 b do_DataAbort
diff --git a/arch/arm/mm/abort-ev7.S b/arch/arm/mm/abort-ev7.S
index 6f98b3a17ac7..703375277ba6 100644
--- a/arch/arm/mm/abort-ev7.S
+++ b/arch/arm/mm/abort-ev7.S
@@ -3,14 +3,11 @@
3/* 3/*
4 * Function: v7_early_abort 4 * Function: v7_early_abort
5 * 5 *
6 * Params : r4 = aborted context pc 6 * Params : r2 = pt_regs
7 * : r4 = aborted context pc
7 * : r5 = aborted context psr 8 * : r5 = aborted context psr
8 * 9 *
9 * Returns : r0 = address of abort 10 * Returns : r4 - r11, r13 preserved
10 * : r1 = FSR, bit 11 = write
11 * : r2-r8 = corrupted
12 * : r9 = preserved
13 * : sp = pointer to registers
14 * 11 *
15 * Purpose : obtain information about current aborted instruction. 12 * Purpose : obtain information about current aborted instruction.
16 */ 13 */
@@ -37,18 +34,18 @@ ENTRY(v7_early_abort)
37 ldr r3, =0x40d @ On permission fault 34 ldr r3, =0x40d @ On permission fault
38 and r3, r1, r3 35 and r3, r1, r3
39 cmp r3, #0x0d 36 cmp r3, #0x0d
40 movne pc, lr 37 bne do_DataAbort
41 38
42 mcr p15, 0, r0, c7, c8, 0 @ Retranslate FAR 39 mcr p15, 0, r0, c7, c8, 0 @ Retranslate FAR
43 isb 40 isb
44 mrc p15, 0, ip, c7, c4, 0 @ Read the PAR 41 mrc p15, 0, ip, c7, c4, 0 @ Read the PAR
45 and r3, ip, #0x7b @ On translation fault 42 and r3, ip, #0x7b @ On translation fault
46 cmp r3, #0x0b 43 cmp r3, #0x0b
47 movne pc, lr 44 bne do_DataAbort
48 bic r1, r1, #0xf @ Fix up FSR FS[5:0] 45 bic r1, r1, #0xf @ Fix up FSR FS[5:0]
49 and ip, ip, #0x7e 46 and ip, ip, #0x7e
50 orr r1, r1, ip, LSR #1 47 orr r1, r1, ip, LSR #1
51#endif 48#endif
52 49
53 mov pc, lr 50 b do_DataAbort
54ENDPROC(v7_early_abort) 51ENDPROC(v7_early_abort)
diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
index d032b1f2067b..d432f31cdab5 100644
--- a/arch/arm/mm/abort-lv4t.S
+++ b/arch/arm/mm/abort-lv4t.S
@@ -3,7 +3,8 @@
3/* 3/*
4 * Function: v4t_late_abort 4 * Function: v4t_late_abort
5 * 5 *
6 * Params : r4 = aborted context pc 6 * Params : r2 = pt_regs
7 * : r4 = aborted context pc
7 * : r5 = aborted context psr 8 * : r5 = aborted context psr
8 * 9 *
9 * Returns : r0 = address of abort 10 * Returns : r0 = address of abort
@@ -47,20 +48,18 @@ ENTRY(v4t_late_abort)
47/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist> 48/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
48/* a */ b .data_unknown 49/* a */ b .data_unknown
49/* b */ b .data_unknown 50/* b */ b .data_unknown
50/* c */ mov pc, lr @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m 51/* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
51/* d */ mov pc, lr @ ldc rd, [rn, #m] 52/* d */ b do_DataAbort @ ldc rd, [rn, #m]
52/* e */ b .data_unknown 53/* e */ b .data_unknown
53/* f */ 54/* f */
54.data_unknown: @ Part of jumptable 55.data_unknown: @ Part of jumptable
55 mov r0, r4 56 mov r0, r4
56 mov r1, r8 57 mov r1, r8
57 mov r2, sp 58 b baddataabort
58 bl baddataabort
59 b ret_from_exception
60 59
61.data_arm_ldmstm: 60.data_arm_ldmstm:
62 tst r8, #1 << 21 @ check writeback bit 61 tst r8, #1 << 21 @ check writeback bit
63 moveq pc, lr @ no writeback -> no fixup 62 beq do_DataAbort @ no writeback -> no fixup
64 mov r7, #0x11 63 mov r7, #0x11
65 orr r7, r7, #0x1100 64 orr r7, r7, #0x1100
66 and r6, r8, r7 65 and r6, r8, r7
@@ -79,11 +78,11 @@ ENTRY(v4t_late_abort)
79 subne r7, r7, r6, lsl #2 @ Undo increment 78 subne r7, r7, r6, lsl #2 @ Undo increment
80 addeq r7, r7, r6, lsl #2 @ Undo decrement 79 addeq r7, r7, r6, lsl #2 @ Undo decrement
81 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 80 str r7, [sp, r5, lsr #14] @ Put register 'Rn'
82 mov pc, lr 81 b do_DataAbort
83 82
84.data_arm_lateldrhpre: 83.data_arm_lateldrhpre:
85 tst r8, #1 << 21 @ Check writeback bit 84 tst r8, #1 << 21 @ Check writeback bit
86 moveq pc, lr @ No writeback -> no fixup 85 beq do_DataAbort @ No writeback -> no fixup
87.data_arm_lateldrhpost: 86.data_arm_lateldrhpost:
88 and r5, r8, #0x00f @ get Rm / low nibble of immediate value 87 and r5, r8, #0x00f @ get Rm / low nibble of immediate value
89 tst r8, #1 << 22 @ if (immediate offset) 88 tst r8, #1 << 22 @ if (immediate offset)
@@ -97,25 +96,25 @@ ENTRY(v4t_late_abort)
97 subne r7, r7, r6 @ Undo incrmenet 96 subne r7, r7, r6 @ Undo incrmenet
98 addeq r7, r7, r6 @ Undo decrement 97 addeq r7, r7, r6 @ Undo decrement
99 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 98 str r7, [sp, r5, lsr #14] @ Put register 'Rn'
100 mov pc, lr 99 b do_DataAbort
101 100
102.data_arm_lateldrpreconst: 101.data_arm_lateldrpreconst:
103 tst r8, #1 << 21 @ check writeback bit 102 tst r8, #1 << 21 @ check writeback bit
104 moveq pc, lr @ no writeback -> no fixup 103 beq do_DataAbort @ no writeback -> no fixup
105.data_arm_lateldrpostconst: 104.data_arm_lateldrpostconst:
106 movs r9, r8, lsl #20 @ Get offset 105 movs r9, r8, lsl #20 @ Get offset
107 moveq pc, lr @ zero -> no fixup 106 beq do_DataAbort @ zero -> no fixup
108 and r5, r8, #15 << 16 @ Extract 'n' from instruction 107 and r5, r8, #15 << 16 @ Extract 'n' from instruction
109 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn' 108 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
110 tst r8, #1 << 23 @ Check U bit 109 tst r8, #1 << 23 @ Check U bit
111 subne r7, r7, r9, lsr #20 @ Undo increment 110 subne r7, r7, r9, lsr #20 @ Undo increment
112 addeq r7, r7, r9, lsr #20 @ Undo decrement 111 addeq r7, r7, r9, lsr #20 @ Undo decrement
113 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 112 str r7, [sp, r5, lsr #14] @ Put register 'Rn'
114 mov pc, lr 113 b do_DataAbort
115 114
116.data_arm_lateldrprereg: 115.data_arm_lateldrprereg:
117 tst r8, #1 << 21 @ check writeback bit 116 tst r8, #1 << 21 @ check writeback bit
118 moveq pc, lr @ no writeback -> no fixup 117 beq do_DataAbort @ no writeback -> no fixup
119.data_arm_lateldrpostreg: 118.data_arm_lateldrpostreg:
120 and r7, r8, #15 @ Extract 'm' from instruction 119 and r7, r8, #15 @ Extract 'm' from instruction
121 ldr r6, [sp, r7, lsl #2] @ Get register 'Rm' 120 ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'
@@ -172,10 +171,10 @@ ENTRY(v4t_late_abort)
172/* 3 */ b .data_unknown 171/* 3 */ b .data_unknown
173/* 4 */ b .data_unknown 172/* 4 */ b .data_unknown
174/* 5 */ b .data_thumb_reg 173/* 5 */ b .data_thumb_reg
175/* 6 */ mov pc, lr 174/* 6 */ b do_DataAbort
176/* 7 */ mov pc, lr 175/* 7 */ b do_DataAbort
177/* 8 */ mov pc, lr 176/* 8 */ b do_DataAbort
178/* 9 */ mov pc, lr 177/* 9 */ b do_DataAbort
179/* A */ b .data_unknown 178/* A */ b .data_unknown
180/* B */ b .data_thumb_pushpop 179/* B */ b .data_thumb_pushpop
181/* C */ b .data_thumb_ldmstm 180/* C */ b .data_thumb_ldmstm
@@ -185,10 +184,10 @@ ENTRY(v4t_late_abort)
185 184
186.data_thumb_reg: 185.data_thumb_reg:
187 tst r8, #1 << 9 186 tst r8, #1 << 9
188 moveq pc, lr 187 beq do_DataAbort
189 tst r8, #1 << 10 @ If 'S' (signed) bit is set 188 tst r8, #1 << 10 @ If 'S' (signed) bit is set
190 movne r1, #0 @ it must be a load instr 189 movne r1, #0 @ it must be a load instr
191 mov pc, lr 190 b do_DataAbort
192 191
193.data_thumb_pushpop: 192.data_thumb_pushpop:
194 tst r8, #1 << 10 193 tst r8, #1 << 10
@@ -207,7 +206,7 @@ ENTRY(v4t_late_abort)
207 addeq r7, r7, r6, lsl #2 @ increment SP if PUSH 206 addeq r7, r7, r6, lsl #2 @ increment SP if PUSH
208 subne r7, r7, r6, lsl #2 @ decrement SP if POP 207 subne r7, r7, r6, lsl #2 @ decrement SP if POP
209 str r7, [sp, #13 << 2] 208 str r7, [sp, #13 << 2]
210 mov pc, lr 209 b do_DataAbort
211 210
212.data_thumb_ldmstm: 211.data_thumb_ldmstm:
213 and r6, r8, #0x55 @ hweight8(r8) 212 and r6, r8, #0x55 @ hweight8(r8)
@@ -222,4 +221,4 @@ ENTRY(v4t_late_abort)
222 and r6, r6, #15 @ number of regs to transfer 221 and r6, r6, #15 @ number of regs to transfer
223 sub r7, r7, r6, lsl #2 @ always decrement 222 sub r7, r7, r6, lsl #2 @ always decrement
224 str r7, [sp, r5, lsr #6] 223 str r7, [sp, r5, lsr #6]
225 mov pc, lr 224 b do_DataAbort
diff --git a/arch/arm/mm/abort-macro.S b/arch/arm/mm/abort-macro.S
index af97a10bc5ed..52162d59407a 100644
--- a/arch/arm/mm/abort-macro.S
+++ b/arch/arm/mm/abort-macro.S
@@ -18,7 +18,7 @@
18 orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes 18 orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
19 tst \tmp, #1 << 11 @ L = 0 -> write 19 tst \tmp, #1 << 11 @ L = 0 -> write
20 orreq \psr, \psr, #1 << 11 @ yes. 20 orreq \psr, \psr, #1 << 11 @ yes.
21 mov pc, lr 21 b do_DataAbort
22not_thumb: 22not_thumb:
23 .endm 23 .endm
24 24
@@ -34,7 +34,7 @@ not_thumb:
34 bne not_ldrd 34 bne not_ldrd
35 and \tmp, \insn, #0x000000f0 @ [7:4] == 1101 35 and \tmp, \insn, #0x000000f0 @ [7:4] == 1101
36 cmp \tmp, #0x000000d0 36 cmp \tmp, #0x000000d0
37 moveq pc, lr 37 beq do_DataAbort
38not_ldrd: 38not_ldrd:
39 .endm 39 .endm
40 40
diff --git a/arch/arm/mm/abort-nommu.S b/arch/arm/mm/abort-nommu.S
index 9eaef6f846c3..119cb479c2ab 100644
--- a/arch/arm/mm/abort-nommu.S
+++ b/arch/arm/mm/abort-nommu.S
@@ -3,11 +3,11 @@
3/* 3/*
4 * Function: nommu_early_abort 4 * Function: nommu_early_abort
5 * 5 *
6 * Params : r4 = aborted context pc 6 * Params : r2 = pt_regs
7 * : r4 = aborted context pc
7 * : r5 = aborted context psr 8 * : r5 = aborted context psr
8 * 9 *
9 * Returns : r0 = 0 (abort address) 10 * Returns : r4 - r11, r13 preserved
10 * : r1 = 0 (FSR)
11 * 11 *
12 * Note: There is no FSR/FAR on !CPU_CP15_MMU cores. 12 * Note: There is no FSR/FAR on !CPU_CP15_MMU cores.
13 * Just fill zero into the registers. 13 * Just fill zero into the registers.
@@ -16,5 +16,5 @@
16ENTRY(nommu_early_abort) 16ENTRY(nommu_early_abort)
17 mov r0, #0 @ clear r0, r1 (no FSR/FAR) 17 mov r0, #0 @ clear r0, r1 (no FSR/FAR)
18 mov r1, #0 18 mov r1, #0
19 mov pc, lr 19 b do_DataAbort
20ENDPROC(nommu_early_abort) 20ENDPROC(nommu_early_abort)
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index d4c328ecf3ba..d755d5b83898 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -29,7 +29,8 @@ ENTRY(cpu_arm7_dcache_clean_area)
29/* 29/*
30 * Function: arm6_7_data_abort () 30 * Function: arm6_7_data_abort ()
31 * 31 *
32 * Params : r4 = aborted context pc 32 * Params : r2 = pt_regs
33 * : r4 = aborted context pc
33 * : r5 = aborted context psr 34 * : r5 = aborted context psr
34 * 35 *
35 * Purpose : obtain information about current aborted instruction 36 * Purpose : obtain information about current aborted instruction
@@ -49,7 +50,7 @@ ENTRY(cpu_arm7_data_abort)
49 nop 50 nop
50 51
51/* 0 */ b .data_unknown 52/* 0 */ b .data_unknown
52/* 1 */ mov pc, lr @ swp 53/* 1 */ b do_DataAbort @ swp
53/* 2 */ b .data_unknown 54/* 2 */ b .data_unknown
54/* 3 */ b .data_unknown 55/* 3 */ b .data_unknown
55/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m 56/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
@@ -60,16 +61,14 @@ ENTRY(cpu_arm7_data_abort)
60/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist> 61/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
61/* a */ b .data_unknown 62/* a */ b .data_unknown
62/* b */ b .data_unknown 63/* b */ b .data_unknown
63/* c */ mov pc, lr @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m 64/* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
64/* d */ mov pc, lr @ ldc rd, [rn, #m] 65/* d */ b do_DataAbort @ ldc rd, [rn, #m]
65/* e */ b .data_unknown 66/* e */ b .data_unknown
66/* f */ 67/* f */
67.data_unknown: @ Part of jumptable 68.data_unknown: @ Part of jumptable
68 mov r0, r4 69 mov r0, r4
69 mov r1, r8 70 mov r1, r8
70 mov r2, sp 71 b baddataabort
71 bl baddataabort
72 b ret_from_exception
73 72
74ENTRY(cpu_arm6_data_abort) 73ENTRY(cpu_arm6_data_abort)
75 mrc p15, 0, r1, c5, c0, 0 @ get FSR 74 mrc p15, 0, r1, c5, c0, 0 @ get FSR
@@ -79,11 +78,11 @@ ENTRY(cpu_arm6_data_abort)
79 orreq r1, r1, #1 << 11 @ yes. 78 orreq r1, r1, #1 << 11 @ yes.
80 and r7, r8, #14 << 24 79 and r7, r8, #14 << 24
81 teq r7, #8 << 24 @ was it ldm/stm 80 teq r7, #8 << 24 @ was it ldm/stm
82 movne pc, lr 81 bne do_DataAbort
83 82
84.data_arm_ldmstm: 83.data_arm_ldmstm:
85 tst r8, #1 << 21 @ check writeback bit 84 tst r8, #1 << 21 @ check writeback bit
86 moveq pc, lr @ no writeback -> no fixup 85 beq do_DataAbort @ no writeback -> no fixup
87 mov r7, #0x11 86 mov r7, #0x11
88 orr r7, r7, #0x1100 87 orr r7, r7, #0x1100
89 and r6, r8, r7 88 and r6, r8, r7
@@ -102,7 +101,7 @@ ENTRY(cpu_arm6_data_abort)
102 subne r7, r7, r6, lsl #2 @ Undo increment 101 subne r7, r7, r6, lsl #2 @ Undo increment
103 addeq r7, r7, r6, lsl #2 @ Undo decrement 102 addeq r7, r7, r6, lsl #2 @ Undo decrement
104 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 103 str r7, [sp, r5, lsr #14] @ Put register 'Rn'
105 mov pc, lr 104 b do_DataAbort
106 105
107.data_arm_apply_r6_and_rn: 106.data_arm_apply_r6_and_rn:
108 and r5, r8, #15 << 16 @ Extract 'n' from instruction 107 and r5, r8, #15 << 16 @ Extract 'n' from instruction
@@ -111,25 +110,25 @@ ENTRY(cpu_arm6_data_abort)
111 subne r7, r7, r6 @ Undo incrmenet 110 subne r7, r7, r6 @ Undo incrmenet
112 addeq r7, r7, r6 @ Undo decrement 111 addeq r7, r7, r6 @ Undo decrement
113 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 112 str r7, [sp, r5, lsr #14] @ Put register 'Rn'
114 mov pc, lr 113 b do_DataAbort
115 114
116.data_arm_lateldrpreconst: 115.data_arm_lateldrpreconst:
117 tst r8, #1 << 21 @ check writeback bit 116 tst r8, #1 << 21 @ check writeback bit
118 moveq pc, lr @ no writeback -> no fixup 117 beq do_DataAbort @ no writeback -> no fixup
119.data_arm_lateldrpostconst: 118.data_arm_lateldrpostconst:
120 movs r9, r8, lsl #20 @ Get offset 119 movs r9, r8, lsl #20 @ Get offset
121 moveq pc, lr @ zero -> no fixup 120 beq do_DataAbort @ zero -> no fixup
122 and r5, r8, #15 << 16 @ Extract 'n' from instruction 121 and r5, r8, #15 << 16 @ Extract 'n' from instruction
123 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn' 122 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
124 tst r8, #1 << 23 @ Check U bit 123 tst r8, #1 << 23 @ Check U bit
125 subne r7, r7, r9, lsr #20 @ Undo increment 124 subne r7, r7, r9, lsr #20 @ Undo increment
126 addeq r7, r7, r9, lsr #20 @ Undo decrement 125 addeq r7, r7, r9, lsr #20 @ Undo decrement
127 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 126 str r7, [sp, r5, lsr #14] @ Put register 'Rn'
128 mov pc, lr 127 b do_DataAbort
129 128
130.data_arm_lateldrprereg: 129.data_arm_lateldrprereg:
131 tst r8, #1 << 21 @ check writeback bit 130 tst r8, #1 << 21 @ check writeback bit
132 moveq pc, lr @ no writeback -> no fixup 131 beq do_DataAbort @ no writeback -> no fixup
133.data_arm_lateldrpostreg: 132.data_arm_lateldrpostreg:
134 and r7, r8, #15 @ Extract 'm' from instruction 133 and r7, r8, #15 @ Extract 'm' from instruction
135 ldr r6, [sp, r7, lsl #2] @ Get register 'Rm' 134 ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 22:11:35 -0500