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-rw-r--r--drivers/gpu/drm/omapdrm/omap_connector.c6
-rw-r--r--drivers/video/omap2/displays-new/connector-analog-tv.c2
-rw-r--r--drivers/video/omap2/displays-new/connector-dvi.c2
-rw-r--r--drivers/video/omap2/displays-new/connector-hdmi.c2
-rw-r--r--drivers/video/omap2/displays-new/panel-dsi-cm.c2
-rw-r--r--drivers/video/omap2/displays-new/panel-lgphilips-lb035q02.c2
-rw-r--r--drivers/video/omap2/displays-new/panel-nec-nl8048hl11.c4
-rw-r--r--drivers/video/omap2/displays-new/panel-sharp-ls037v7dw01.c2
-rw-r--r--drivers/video/omap2/displays-new/panel-sony-acx565akm.c2
-rw-r--r--drivers/video/omap2/displays-new/panel-tpo-td028ttec1.c2
-rw-r--r--drivers/video/omap2/displays-new/panel-tpo-td043mtea1.c2
-rw-r--r--drivers/video/omap2/dss/dispc.c8
-rw-r--r--drivers/video/omap2/dss/display-sysfs.c4
-rw-r--r--drivers/video/omap2/dss/display.c4
-rw-r--r--drivers/video/omap2/dss/dpi.c25
-rw-r--r--drivers/video/omap2/dss/dsi.c16
-rw-r--r--drivers/video/omap2/dss/hdmi4.c9
-rw-r--r--drivers/video/omap2/dss/hdmi_common.c74
-rw-r--r--drivers/video/omap2/dss/sdi.c15
-rw-r--r--drivers/video/omap2/dss/venc.c4
-rw-r--r--drivers/video/omap2/dss/venc_panel.c2
-rw-r--r--drivers/video/omap2/omapfb/omapfb-main.c8
-rw-r--r--include/video/omapdss.h4
23 files changed, 100 insertions, 101 deletions
diff --git a/drivers/gpu/drm/omapdrm/omap_connector.c b/drivers/gpu/drm/omapdrm/omap_connector.c
index 912759daf562..86f4ead0441d 100644
--- a/drivers/gpu/drm/omapdrm/omap_connector.c
+++ b/drivers/gpu/drm/omapdrm/omap_connector.c
@@ -37,7 +37,7 @@ struct omap_connector {
37void copy_timings_omap_to_drm(struct drm_display_mode *mode, 37void copy_timings_omap_to_drm(struct drm_display_mode *mode,
38 struct omap_video_timings *timings) 38 struct omap_video_timings *timings)
39{ 39{
40 mode->clock = timings->pixel_clock; 40 mode->clock = timings->pixelclock / 1000;
41 41
42 mode->hdisplay = timings->x_res; 42 mode->hdisplay = timings->x_res;
43 mode->hsync_start = mode->hdisplay + timings->hfp; 43 mode->hsync_start = mode->hdisplay + timings->hfp;
@@ -68,7 +68,7 @@ void copy_timings_omap_to_drm(struct drm_display_mode *mode,
68void copy_timings_drm_to_omap(struct omap_video_timings *timings, 68void copy_timings_drm_to_omap(struct omap_video_timings *timings,
69 struct drm_display_mode *mode) 69 struct drm_display_mode *mode)
70{ 70{
71 timings->pixel_clock = mode->clock; 71 timings->pixelclock = mode->clock * 1000;
72 72
73 timings->x_res = mode->hdisplay; 73 timings->x_res = mode->hdisplay;
74 timings->hfp = mode->hsync_start - mode->hdisplay; 74 timings->hfp = mode->hsync_start - mode->hdisplay;
@@ -220,7 +220,7 @@ static int omap_connector_mode_valid(struct drm_connector *connector,
220 if (!r) { 220 if (!r) {
221 /* check if vrefresh is still valid */ 221 /* check if vrefresh is still valid */
222 new_mode = drm_mode_duplicate(dev, mode); 222 new_mode = drm_mode_duplicate(dev, mode);
223 new_mode->clock = timings.pixel_clock; 223 new_mode->clock = timings.pixelclock / 1000;
224 new_mode->vrefresh = 0; 224 new_mode->vrefresh = 0;
225 if (mode->vrefresh == drm_mode_vrefresh(new_mode)) 225 if (mode->vrefresh == drm_mode_vrefresh(new_mode))
226 ret = MODE_OK; 226 ret = MODE_OK;
diff --git a/drivers/video/omap2/displays-new/connector-analog-tv.c b/drivers/video/omap2/displays-new/connector-analog-tv.c
index ccd9073f706f..27f33ef8fca1 100644
--- a/drivers/video/omap2/displays-new/connector-analog-tv.c
+++ b/drivers/video/omap2/displays-new/connector-analog-tv.c
@@ -31,7 +31,7 @@ struct panel_drv_data {
31static const struct omap_video_timings tvc_pal_timings = { 31static const struct omap_video_timings tvc_pal_timings = {
32 .x_res = 720, 32 .x_res = 720,
33 .y_res = 574, 33 .y_res = 574,
34 .pixel_clock = 13500, 34 .pixelclock = 13500000,
35 .hsw = 64, 35 .hsw = 64,
36 .hfp = 12, 36 .hfp = 12,
37 .hbp = 68, 37 .hbp = 68,
diff --git a/drivers/video/omap2/displays-new/connector-dvi.c b/drivers/video/omap2/displays-new/connector-dvi.c
index b6c50904038e..d18e4b8c0731 100644
--- a/drivers/video/omap2/displays-new/connector-dvi.c
+++ b/drivers/video/omap2/displays-new/connector-dvi.c
@@ -23,7 +23,7 @@ static const struct omap_video_timings dvic_default_timings = {
23 .x_res = 640, 23 .x_res = 640,
24 .y_res = 480, 24 .y_res = 480,
25 25
26 .pixel_clock = 23500, 26 .pixelclock = 23500000,
27 27
28 .hfp = 48, 28 .hfp = 48,
29 .hsw = 32, 29 .hsw = 32,
diff --git a/drivers/video/omap2/displays-new/connector-hdmi.c b/drivers/video/omap2/displays-new/connector-hdmi.c
index 9abe2c039ae9..9393e2d6473d 100644
--- a/drivers/video/omap2/displays-new/connector-hdmi.c
+++ b/drivers/video/omap2/displays-new/connector-hdmi.c
@@ -21,7 +21,7 @@
21static const struct omap_video_timings hdmic_default_timings = { 21static const struct omap_video_timings hdmic_default_timings = {
22 .x_res = 640, 22 .x_res = 640,
23 .y_res = 480, 23 .y_res = 480,
24 .pixel_clock = 25175, 24 .pixelclock = 25175000,
25 .hsw = 96, 25 .hsw = 96,
26 .hfp = 16, 26 .hfp = 16,
27 .hbp = 48, 27 .hbp = 48,
diff --git a/drivers/video/omap2/displays-new/panel-dsi-cm.c b/drivers/video/omap2/displays-new/panel-dsi-cm.c
index b7baafe83aa3..f317c878a259 100644
--- a/drivers/video/omap2/displays-new/panel-dsi-cm.c
+++ b/drivers/video/omap2/displays-new/panel-dsi-cm.c
@@ -1184,7 +1184,7 @@ static int dsicm_probe(struct platform_device *pdev)
1184 1184
1185 ddata->timings.x_res = 864; 1185 ddata->timings.x_res = 864;
1186 ddata->timings.y_res = 480; 1186 ddata->timings.y_res = 480;
1187 ddata->timings.pixel_clock = DIV_ROUND_UP(864 * 480 * 60, 1000); 1187 ddata->timings.pixelclock = 864 * 480 * 60;
1188 1188
1189 dssdev = &ddata->dssdev; 1189 dssdev = &ddata->dssdev;
1190 dssdev->dev = dev; 1190 dssdev->dev = dev;
diff --git a/drivers/video/omap2/displays-new/panel-lgphilips-lb035q02.c b/drivers/video/omap2/displays-new/panel-lgphilips-lb035q02.c
index 6e8977b18950..2e6b513222d9 100644
--- a/drivers/video/omap2/displays-new/panel-lgphilips-lb035q02.c
+++ b/drivers/video/omap2/displays-new/panel-lgphilips-lb035q02.c
@@ -23,7 +23,7 @@ static struct omap_video_timings lb035q02_timings = {
23 .x_res = 320, 23 .x_res = 320,
24 .y_res = 240, 24 .y_res = 240,
25 25
26 .pixel_clock = 6500, 26 .pixelclock = 6500000,
27 27
28 .hsw = 2, 28 .hsw = 2,
29 .hfp = 20, 29 .hfp = 20,
diff --git a/drivers/video/omap2/displays-new/panel-nec-nl8048hl11.c b/drivers/video/omap2/displays-new/panel-nec-nl8048hl11.c
index bb217da65c5f..996fa004b48c 100644
--- a/drivers/video/omap2/displays-new/panel-nec-nl8048hl11.c
+++ b/drivers/video/omap2/displays-new/panel-nec-nl8048hl11.c
@@ -40,7 +40,7 @@ struct panel_drv_data {
40 * NEC PIX Clock Ratings 40 * NEC PIX Clock Ratings
41 * MIN:21.8MHz TYP:23.8MHz MAX:25.7MHz 41 * MIN:21.8MHz TYP:23.8MHz MAX:25.7MHz
42 */ 42 */
43#define LCD_PIXEL_CLOCK 23800 43#define LCD_PIXEL_CLOCK 23800000
44 44
45static const struct { 45static const struct {
46 unsigned char addr; 46 unsigned char addr;
@@ -69,7 +69,7 @@ static const struct {
69static const struct omap_video_timings nec_8048_panel_timings = { 69static const struct omap_video_timings nec_8048_panel_timings = {
70 .x_res = LCD_XRES, 70 .x_res = LCD_XRES,
71 .y_res = LCD_YRES, 71 .y_res = LCD_YRES,
72 .pixel_clock = LCD_PIXEL_CLOCK, 72 .pixelclock = LCD_PIXEL_CLOCK,
73 .hfp = 6, 73 .hfp = 6,
74 .hsw = 1, 74 .hsw = 1,
75 .hbp = 4, 75 .hbp = 4,
diff --git a/drivers/video/omap2/displays-new/panel-sharp-ls037v7dw01.c b/drivers/video/omap2/displays-new/panel-sharp-ls037v7dw01.c
index 72a4fb5aa6b1..b2f710be565d 100644
--- a/drivers/video/omap2/displays-new/panel-sharp-ls037v7dw01.c
+++ b/drivers/video/omap2/displays-new/panel-sharp-ls037v7dw01.c
@@ -37,7 +37,7 @@ static const struct omap_video_timings sharp_ls_timings = {
37 .x_res = 480, 37 .x_res = 480,
38 .y_res = 640, 38 .y_res = 640,
39 39
40 .pixel_clock = 19200, 40 .pixelclock = 19200000,
41 41
42 .hsw = 2, 42 .hsw = 2,
43 .hfp = 1, 43 .hfp = 1,
diff --git a/drivers/video/omap2/displays-new/panel-sony-acx565akm.c b/drivers/video/omap2/displays-new/panel-sony-acx565akm.c
index 8e97d06921ff..27f60ad6b2ab 100644
--- a/drivers/video/omap2/displays-new/panel-sony-acx565akm.c
+++ b/drivers/video/omap2/displays-new/panel-sony-acx565akm.c
@@ -93,7 +93,7 @@ struct panel_drv_data {
93static const struct omap_video_timings acx565akm_panel_timings = { 93static const struct omap_video_timings acx565akm_panel_timings = {
94 .x_res = 800, 94 .x_res = 800,
95 .y_res = 480, 95 .y_res = 480,
96 .pixel_clock = 24000, 96 .pixelclock = 24000000,
97 .hfp = 28, 97 .hfp = 28,
98 .hsw = 4, 98 .hsw = 4,
99 .hbp = 24, 99 .hbp = 24,
diff --git a/drivers/video/omap2/displays-new/panel-tpo-td028ttec1.c b/drivers/video/omap2/displays-new/panel-tpo-td028ttec1.c
index 9a08908fe998..fae6adc005a7 100644
--- a/drivers/video/omap2/displays-new/panel-tpo-td028ttec1.c
+++ b/drivers/video/omap2/displays-new/panel-tpo-td028ttec1.c
@@ -45,7 +45,7 @@ struct panel_drv_data {
45static struct omap_video_timings td028ttec1_panel_timings = { 45static struct omap_video_timings td028ttec1_panel_timings = {
46 .x_res = 480, 46 .x_res = 480,
47 .y_res = 640, 47 .y_res = 640,
48 .pixel_clock = 22153, 48 .pixelclock = 22153000,
49 .hfp = 24, 49 .hfp = 24,
50 .hsw = 8, 50 .hsw = 8,
51 .hbp = 8, 51 .hbp = 8,
diff --git a/drivers/video/omap2/displays-new/panel-tpo-td043mtea1.c b/drivers/video/omap2/displays-new/panel-tpo-td043mtea1.c
index eadc6529fa3d..875b40263b33 100644
--- a/drivers/video/omap2/displays-new/panel-tpo-td043mtea1.c
+++ b/drivers/video/omap2/displays-new/panel-tpo-td043mtea1.c
@@ -76,7 +76,7 @@ static const struct omap_video_timings tpo_td043_timings = {
76 .x_res = 800, 76 .x_res = 800,
77 .y_res = 480, 77 .y_res = 480,
78 78
79 .pixel_clock = 36000, 79 .pixelclock = 36000000,
80 80
81 .hsw = 1, 81 .hsw = 1,
82 .hfp = 68, 82 .hfp = 68,
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 1659aa912d2b..b801be4660e9 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -2873,7 +2873,7 @@ bool dispc_mgr_timings_ok(enum omap_channel channel,
2873 2873
2874 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res); 2874 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2875 2875
2876 timings_ok &= _dispc_mgr_pclk_ok(channel, timings->pixel_clock * 1000); 2876 timings_ok &= _dispc_mgr_pclk_ok(channel, timings->pixelclock);
2877 2877
2878 if (dss_mgr_is_lcd(channel)) { 2878 if (dss_mgr_is_lcd(channel)) {
2879 timings_ok &= _dispc_lcd_timings_ok(timings->hsw, timings->hfp, 2879 timings_ok &= _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
@@ -2968,10 +2968,10 @@ void dispc_mgr_set_timings(enum omap_channel channel,
2968 xtot = t.x_res + t.hfp + t.hsw + t.hbp; 2968 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2969 ytot = t.y_res + t.vfp + t.vsw + t.vbp; 2969 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
2970 2970
2971 ht = (timings->pixel_clock * 1000) / xtot; 2971 ht = timings->pixelclock / xtot;
2972 vt = (timings->pixel_clock * 1000) / xtot / ytot; 2972 vt = timings->pixelclock / xtot / ytot;
2973 2973
2974 DSSDBG("pck %u\n", timings->pixel_clock); 2974 DSSDBG("pck %u\n", timings->pixelclock);
2975 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", 2975 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2976 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp); 2976 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
2977 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", 2977 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
diff --git a/drivers/video/omap2/dss/display-sysfs.c b/drivers/video/omap2/dss/display-sysfs.c
index f7b5f9561041..5a2095a98ed8 100644
--- a/drivers/video/omap2/dss/display-sysfs.c
+++ b/drivers/video/omap2/dss/display-sysfs.c
@@ -132,7 +132,7 @@ static ssize_t display_timings_show(struct device *dev,
132 dssdev->driver->get_timings(dssdev, &t); 132 dssdev->driver->get_timings(dssdev, &t);
133 133
134 return snprintf(buf, PAGE_SIZE, "%u,%u/%u/%u/%u,%u/%u/%u/%u\n", 134 return snprintf(buf, PAGE_SIZE, "%u,%u/%u/%u/%u,%u/%u/%u/%u\n",
135 t.pixel_clock, 135 t.pixelclock,
136 t.x_res, t.hfp, t.hbp, t.hsw, 136 t.x_res, t.hfp, t.hbp, t.hsw,
137 t.y_res, t.vfp, t.vbp, t.vsw); 137 t.y_res, t.vfp, t.vbp, t.vsw);
138} 138}
@@ -158,7 +158,7 @@ static ssize_t display_timings_store(struct device *dev,
158 } 158 }
159#endif 159#endif
160 if (!found && sscanf(buf, "%u,%hu/%hu/%hu/%hu,%hu/%hu/%hu/%hu", 160 if (!found && sscanf(buf, "%u,%hu/%hu/%hu/%hu,%hu/%hu/%hu/%hu",
161 &t.pixel_clock, 161 &t.pixelclock,
162 &t.x_res, &t.hfp, &t.hbp, &t.hsw, 162 &t.x_res, &t.hfp, &t.hbp, &t.hsw,
163 &t.y_res, &t.vfp, &t.vbp, &t.vsw) != 9) 163 &t.y_res, &t.vfp, &t.vbp, &t.vsw) != 9)
164 return -EINVAL; 164 return -EINVAL;
diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c
index 669a81fdf58e..9f19ae22944c 100644
--- a/drivers/video/omap2/dss/display.c
+++ b/drivers/video/omap2/dss/display.c
@@ -248,7 +248,7 @@ void videomode_to_omap_video_timings(const struct videomode *vm,
248{ 248{
249 memset(ovt, 0, sizeof(*ovt)); 249 memset(ovt, 0, sizeof(*ovt));
250 250
251 ovt->pixel_clock = vm->pixelclock / 1000; 251 ovt->pixelclock = vm->pixelclock;
252 ovt->x_res = vm->hactive; 252 ovt->x_res = vm->hactive;
253 ovt->hbp = vm->hback_porch; 253 ovt->hbp = vm->hback_porch;
254 ovt->hfp = vm->hfront_porch; 254 ovt->hfp = vm->hfront_porch;
@@ -280,7 +280,7 @@ void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
280{ 280{
281 memset(vm, 0, sizeof(*vm)); 281 memset(vm, 0, sizeof(*vm));
282 282
283 vm->pixelclock = ovt->pixel_clock * 1000; 283 vm->pixelclock = ovt->pixelclock;
284 284
285 vm->hactive = ovt->x_res; 285 vm->hactive = ovt->x_res;
286 vm->hback_porch = ovt->hbp; 286 vm->hback_porch = ovt->hbp;
diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
index 7411f2674e16..d806fd50aa94 100644
--- a/drivers/video/omap2/dss/dpi.c
+++ b/drivers/video/omap2/dss/dpi.c
@@ -307,22 +307,21 @@ static int dpi_set_mode(struct omap_overlay_manager *mgr)
307 int r = 0; 307 int r = 0;
308 308
309 if (dpi.dsidev) 309 if (dpi.dsidev)
310 r = dpi_set_dsi_clk(mgr->id, t->pixel_clock * 1000, &fck, 310 r = dpi_set_dsi_clk(mgr->id, t->pixelclock, &fck,
311 &lck_div, &pck_div); 311 &lck_div, &pck_div);
312 else 312 else
313 r = dpi_set_dispc_clk(t->pixel_clock * 1000, &fck, 313 r = dpi_set_dispc_clk(t->pixelclock, &fck,
314 &lck_div, &pck_div); 314 &lck_div, &pck_div);
315 if (r) 315 if (r)
316 return r; 316 return r;
317 317
318 pck = fck / lck_div / pck_div / 1000; 318 pck = fck / lck_div / pck_div;
319 319
320 if (pck != t->pixel_clock) { 320 if (pck != t->pixelclock) {
321 DSSWARN("Could not find exact pixel clock. " 321 DSSWARN("Could not find exact pixel clock. Requested %d Hz, got %lu Hz\n",
322 "Requested %d kHz, got %lu kHz\n", 322 t->pixelclock, pck);
323 t->pixel_clock, pck);
324 323
325 t->pixel_clock = pck; 324 t->pixelclock = pck;
326 } 325 }
327 326
328 dss_mgr_set_timings(mgr, t); 327 dss_mgr_set_timings(mgr, t);
@@ -480,17 +479,17 @@ static int dpi_check_timings(struct omap_dss_device *dssdev,
480 if (mgr && !dispc_mgr_timings_ok(mgr->id, timings)) 479 if (mgr && !dispc_mgr_timings_ok(mgr->id, timings))
481 return -EINVAL; 480 return -EINVAL;
482 481
483 if (timings->pixel_clock == 0) 482 if (timings->pixelclock == 0)
484 return -EINVAL; 483 return -EINVAL;
485 484
486 if (dpi.dsidev) { 485 if (dpi.dsidev) {
487 ok = dpi_dsi_clk_calc(timings->pixel_clock * 1000, &ctx); 486 ok = dpi_dsi_clk_calc(timings->pixelclock, &ctx);
488 if (!ok) 487 if (!ok)
489 return -EINVAL; 488 return -EINVAL;
490 489
491 fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk; 490 fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
492 } else { 491 } else {
493 ok = dpi_dss_clk_calc(timings->pixel_clock * 1000, &ctx); 492 ok = dpi_dss_clk_calc(timings->pixelclock, &ctx);
494 if (!ok) 493 if (!ok)
495 return -EINVAL; 494 return -EINVAL;
496 495
@@ -500,9 +499,9 @@ static int dpi_check_timings(struct omap_dss_device *dssdev,
500 lck_div = ctx.dispc_cinfo.lck_div; 499 lck_div = ctx.dispc_cinfo.lck_div;
501 pck_div = ctx.dispc_cinfo.pck_div; 500 pck_div = ctx.dispc_cinfo.pck_div;
502 501
503 pck = fck / lck_div / pck_div / 1000; 502 pck = fck / lck_div / pck_div;
504 503
505 timings->pixel_clock = pck; 504 timings->pixelclock = pck;
506 505
507 return 0; 506 return 0;
508} 507}
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index a820c37e323e..0d82f731d2f0 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -4616,7 +4616,7 @@ static void print_dsi_vm(const char *str,
4616 4616
4617static void print_dispc_vm(const char *str, const struct omap_video_timings *t) 4617static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
4618{ 4618{
4619 unsigned long pck = t->pixel_clock * 1000; 4619 unsigned long pck = t->pixelclock;
4620 int hact, bl, tot; 4620 int hact, bl, tot;
4621 4621
4622 hact = t->x_res; 4622 hact = t->x_res;
@@ -4656,7 +4656,7 @@ static void print_dsi_dispc_vm(const char *str,
4656 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl); 4656 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4657 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp; 4657 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4658 4658
4659 vm.pixel_clock = pck / 1000; 4659 vm.pixelclock = pck;
4660 vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk); 4660 vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4661 vm.hbp = div64_u64((u64)t->hbp * pck, byteclk); 4661 vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
4662 vm.hfp = div64_u64((u64)t->hfp * pck, byteclk); 4662 vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
@@ -4678,7 +4678,7 @@ static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4678 ctx->dispc_cinfo.pck = pck; 4678 ctx->dispc_cinfo.pck = pck;
4679 4679
4680 *t = *ctx->config->timings; 4680 *t = *ctx->config->timings;
4681 t->pixel_clock = pck / 1000; 4681 t->pixelclock = pck;
4682 t->x_res = ctx->config->timings->x_res; 4682 t->x_res = ctx->config->timings->x_res;
4683 t->y_res = ctx->config->timings->y_res; 4683 t->y_res = ctx->config->timings->y_res;
4684 t->hsw = t->hfp = t->hbp = t->vsw = 1; 4684 t->hsw = t->hfp = t->hbp = t->vsw = 1;
@@ -4732,7 +4732,7 @@ static bool dsi_cm_calc(struct dsi_data *dsi,
4732 * especially as we go to LP between each pixel packet due to HW 4732 * especially as we go to LP between each pixel packet due to HW
4733 * "feature". So let's just estimate very roughly and multiply by 1.5. 4733 * "feature". So let's just estimate very roughly and multiply by 1.5.
4734 */ 4734 */
4735 pck = cfg->timings->pixel_clock * 1000; 4735 pck = cfg->timings->pixelclock;
4736 pck = pck * 3 / 2; 4736 pck = pck * 3 / 2;
4737 txbyteclk = pck * bitspp / 8 / ndl; 4737 txbyteclk = pck * bitspp / 8 / ndl;
4738 4738
@@ -4909,7 +4909,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4909 4909
4910 dispc_vm = &ctx->dispc_vm; 4910 dispc_vm = &ctx->dispc_vm;
4911 *dispc_vm = *req_vm; 4911 *dispc_vm = *req_vm;
4912 dispc_vm->pixel_clock = dispc_pck / 1000; 4912 dispc_vm->pixelclock = dispc_pck;
4913 4913
4914 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4914 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4915 hsa = div64_u64((u64)req_vm->hsw * dispc_pck, 4915 hsa = div64_u64((u64)req_vm->hsw * dispc_pck,
@@ -5031,9 +5031,9 @@ static bool dsi_vm_calc(struct dsi_data *dsi,
5031 ctx->dsi_cinfo.clkin = clkin; 5031 ctx->dsi_cinfo.clkin = clkin;
5032 5032
5033 /* these limits should come from the panel driver */ 5033 /* these limits should come from the panel driver */
5034 ctx->req_pck_min = t->pixel_clock * 1000 - 1000; 5034 ctx->req_pck_min = t->pixelclock - 1000;
5035 ctx->req_pck_nom = t->pixel_clock * 1000; 5035 ctx->req_pck_nom = t->pixelclock;
5036 ctx->req_pck_max = t->pixel_clock * 1000 + 1000; 5036 ctx->req_pck_max = t->pixelclock + 1000;
5037 5037
5038 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); 5038 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
5039 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); 5039 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
diff --git a/drivers/video/omap2/dss/hdmi4.c b/drivers/video/omap2/dss/hdmi4.c
index 4a74538f9ea5..895c252ae0a8 100644
--- a/drivers/video/omap2/dss/hdmi4.c
+++ b/drivers/video/omap2/dss/hdmi4.c
@@ -153,7 +153,8 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
153 153
154 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); 154 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
155 155
156 phy = p->pixel_clock; 156 /* the functions below use kHz pixel clock. TODO: change to Hz */
157 phy = p->pixelclock / 1000;
157 158
158 hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy); 159 hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy);
159 160
@@ -238,13 +239,13 @@ static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
238 if (t != NULL) { 239 if (t != NULL) {
239 hdmi.cfg = *t; 240 hdmi.cfg = *t;
240 241
241 dispc_set_tv_pclk(t->timings.pixel_clock * 1000); 242 dispc_set_tv_pclk(t->timings.pixelclock);
242 } else { 243 } else {
243 hdmi.cfg.timings = *timings; 244 hdmi.cfg.timings = *timings;
244 hdmi.cfg.cm.code = 0; 245 hdmi.cfg.cm.code = 0;
245 hdmi.cfg.cm.mode = HDMI_DVI; 246 hdmi.cfg.cm.mode = HDMI_DVI;
246 247
247 dispc_set_tv_pclk(timings->pixel_clock * 1000); 248 dispc_set_tv_pclk(timings->pixelclock);
248 } 249 }
249 250
250 DSSDBG("using mode: %s, code %d\n", hdmi.cfg.cm.mode == HDMI_DVI ? 251 DSSDBG("using mode: %s, code %d\n", hdmi.cfg.cm.mode == HDMI_DVI ?
@@ -509,7 +510,7 @@ static int hdmi_audio_config(struct omap_dss_device *dssdev,
509 struct omap_dss_audio *audio) 510 struct omap_dss_audio *audio)
510{ 511{
511 int r; 512 int r;
512 u32 pclk = hdmi.cfg.timings.pixel_clock; 513 u32 pclk = hdmi.cfg.timings.pixelclock;
513 514
514 mutex_lock(&hdmi.lock); 515 mutex_lock(&hdmi.lock);
515 516
diff --git a/drivers/video/omap2/dss/hdmi_common.c b/drivers/video/omap2/dss/hdmi_common.c
index 0614922902dd..b11afac8e068 100644
--- a/drivers/video/omap2/dss/hdmi_common.c
+++ b/drivers/video/omap2/dss/hdmi_common.c
@@ -23,91 +23,91 @@
23 23
24static const struct hdmi_config cea_timings[] = { 24static const struct hdmi_config cea_timings[] = {
25 { 25 {
26 { 640, 480, 25200, 96, 16, 48, 2, 10, 33, 26 { 640, 480, 25200000, 96, 16, 48, 2, 10, 33,
27 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, 27 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
28 false, }, 28 false, },
29 { 1, HDMI_HDMI }, 29 { 1, HDMI_HDMI },
30 }, 30 },
31 { 31 {
32 { 720, 480, 27027, 62, 16, 60, 6, 9, 30, 32 { 720, 480, 27027000, 62, 16, 60, 6, 9, 30,
33 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, 33 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
34 false, }, 34 false, },
35 { 2, HDMI_HDMI }, 35 { 2, HDMI_HDMI },
36 }, 36 },
37 { 37 {
38 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20, 38 { 1280, 720, 74250000, 40, 110, 220, 5, 5, 20,
39 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, 39 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
40 false, }, 40 false, },
41 { 4, HDMI_HDMI }, 41 { 4, HDMI_HDMI },
42 }, 42 },
43 { 43 {
44 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15, 44 { 1920, 540, 74250000, 44, 88, 148, 5, 2, 15,
45 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, 45 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
46 true, }, 46 true, },
47 { 5, HDMI_HDMI }, 47 { 5, HDMI_HDMI },
48 }, 48 },
49 { 49 {
50 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15, 50 { 1440, 240, 27027000, 124, 38, 114, 3, 4, 15,
51 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, 51 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
52 true, }, 52 true, },
53 { 6, HDMI_HDMI }, 53 { 6, HDMI_HDMI },
54 }, 54 },
55 { 55 {
56 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36, 56 { 1920, 1080, 148500000, 44, 88, 148, 5, 4, 36,
57 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, 57 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
58 false, }, 58 false, },
59 { 16, HDMI_HDMI }, 59 { 16, HDMI_HDMI },
60 }, 60 },
61 { 61 {
62 { 720, 576, 27000, 64, 12, 68, 5, 5, 39, 62 { 720, 576, 27000000, 64, 12, 68, 5, 5, 39,
63 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, 63 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
64 false, }, 64 false, },
65 { 17, HDMI_HDMI }, 65 { 17, HDMI_HDMI },
66 }, 66 },
67 { 67 {
68 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20, 68 { 1280, 720, 74250000, 40, 440, 220, 5, 5, 20,
69 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, 69 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
70 false, }, 70 false, },
71 { 19, HDMI_HDMI }, 71 { 19, HDMI_HDMI },
72 }, 72 },
73 { 73 {
74 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15, 74 { 1920, 540, 74250000, 44, 528, 148, 5, 2, 15,
75 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, 75 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
76 true, }, 76 true, },
77 { 20, HDMI_HDMI }, 77 { 20, HDMI_HDMI },
78 }, 78 },
79 { 79 {
80 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19, 80 { 1440, 288, 27000000, 126, 24, 138, 3, 2, 19,
81 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, 81 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
82 true, }, 82 true, },
83 { 21, HDMI_HDMI }, 83 { 21, HDMI_HDMI },
84 }, 84 },
85 { 85 {
86 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39, 86 { 1440, 576, 54000000, 128, 24, 136, 5, 5, 39,
87 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, 87 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
88 false, }, 88 false, },
89 { 29, HDMI_HDMI }, 89 { 29, HDMI_HDMI },
90 }, 90 },
91 { 91 {
92 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36, 92 { 1920, 1080, 148500000, 44, 528, 148, 5, 4, 36,
93 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, 93 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
94 false, }, 94 false, },
95 { 31, HDMI_HDMI }, 95 { 31, HDMI_HDMI },
96 }, 96 },
97 { 97 {
98 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36, 98 { 1920, 1080, 74250000, 44, 638, 148, 5, 4, 36,
99 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, 99 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
100 false, }, 100 false, },
101 { 32, HDMI_HDMI }, 101 { 32, HDMI_HDMI },
102 }, 102 },
103 { 103 {
104 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30, 104 { 2880, 480, 108108000, 248, 64, 240, 6, 9, 30,
105 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, 105 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
106 false, }, 106 false, },
107 { 35, HDMI_HDMI }, 107 { 35, HDMI_HDMI },
108 }, 108 },
109 { 109 {
110 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39, 110 { 2880, 576, 108000000, 256, 48, 272, 5, 5, 39,
111 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, 111 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
112 false, }, 112 false, },
113 { 37, HDMI_HDMI }, 113 { 37, HDMI_HDMI },
@@ -117,121 +117,121 @@ static const struct hdmi_config cea_timings[] = {
117static const struct hdmi_config vesa_timings[] = { 117static const struct hdmi_config vesa_timings[] = {
118/* VESA From Here */ 118/* VESA From Here */
119 { 119 {
120 { 640, 480, 25175, 96, 16, 48, 2, 11, 31, 120 { 640, 480, 25175000, 96, 16, 48, 2, 11, 31,
121 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, 121 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
122 false, }, 122 false, },
123 { 4, HDMI_DVI }, 123 { 4, HDMI_DVI },
124 }, 124 },
125 { 125 {
126 { 800, 600, 40000, 128, 40, 88, 4, 1, 23, 126 { 800, 600, 40000000, 128, 40, 88, 4, 1, 23,
127 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, 127 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
128 false, }, 128 false, },
129 { 9, HDMI_DVI }, 129 { 9, HDMI_DVI },
130 }, 130 },
131 { 131 {
132 { 848, 480, 33750, 112, 16, 112, 8, 6, 23, 132 { 848, 480, 33750000, 112, 16, 112, 8, 6, 23,
133 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, 133 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
134 false, }, 134 false, },
135 { 0xE, HDMI_DVI }, 135 { 0xE, HDMI_DVI },
136 }, 136 },
137 { 137 {
138 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20, 138 { 1280, 768, 79500000, 128, 64, 192, 7, 3, 20,
139 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, 139 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
140 false, }, 140 false, },
141 { 0x17, HDMI_DVI }, 141 { 0x17, HDMI_DVI },
142 }, 142 },
143 { 143 {
144 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22, 144 { 1280, 800, 83500000, 128, 72, 200, 6, 3, 22,
145 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, 145 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
146 false, }, 146 false, },
147 { 0x1C, HDMI_DVI }, 147 { 0x1C, HDMI_DVI },
148 }, 148 },
149 { 149 {
150 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18, 150 { 1360, 768, 85500000, 112, 64, 256, 6, 3, 18,
151 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, 151 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
152 false, }, 152 false, },
153 { 0x27, HDMI_DVI }, 153 { 0x27, HDMI_DVI },
154 }, 154 },
155 { 155 {
156 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36, 156 { 1280, 960, 108000000, 112, 96, 312, 3, 1, 36,
157 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, 157 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
158 false, }, 158 false, },
159 { 0x20, HDMI_DVI }, 159 { 0x20, HDMI_DVI },
160 }, 160 },
161 { 161 {
162 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38, 162 { 1280, 1024, 108000000, 112, 48, 248, 3, 1, 38,
163 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, 163 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
164 false, }, 164 false, },
165 { 0x23, HDMI_DVI }, 165 { 0x23, HDMI_DVI },
166 }, 166 },
167 { 167 {
168 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29, 168 { 1024, 768, 65000000, 136, 24, 160, 6, 3, 29,
169 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, 169 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
170 false, }, 170 false, },
171 { 0x10, HDMI_DVI }, 171 { 0x10, HDMI_DVI },
172 }, 172 },
173 { 173 {
174 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32, 174 { 1400, 1050, 121750000, 144, 88, 232, 4, 3, 32,
175 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, 175 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
176 false, }, 176 false, },
177 { 0x2A, HDMI_DVI }, 177 { 0x2A, HDMI_DVI },
178 }, 178 },
179 { 179 {
180 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25, 180 { 1440, 900, 106500000, 152, 80, 232, 6, 3, 25,
181 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, 181 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
182 false, }, 182 false, },
183 { 0x2F, HDMI_DVI }, 183 { 0x2F, HDMI_DVI },
184 }, 184 },
185 { 185 {
186 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, 186 { 1680, 1050, 146250000, 176 , 104, 280, 6, 3, 30,
187 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, 187 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
188 false, }, 188 false, },
189 { 0x3A, HDMI_DVI }, 189 { 0x3A, HDMI_DVI },
190 }, 190 },
191 { 191 {
192 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24, 192 { 1366, 768, 85500000, 143, 70, 213, 3, 3, 24,
193 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, 193 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
194 false, }, 194 false, },
195 { 0x51, HDMI_DVI }, 195 { 0x51, HDMI_DVI },
196 }, 196 },
197 { 197 {
198 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36, 198 { 1920, 1080, 148500000, 44, 148, 80, 5, 4, 36,
199 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, 199 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
200 false, }, 200 false, },
201 { 0x52, HDMI_DVI }, 201 { 0x52, HDMI_DVI },
202 }, 202 },
203 { 203 {
204 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12, 204 { 1280, 768, 68250000, 32, 48, 80, 7, 3, 12,
205 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, 205 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
206 false, }, 206 false, },
207 { 0x16, HDMI_DVI }, 207 { 0x16, HDMI_DVI },
208 }, 208 },
209 { 209 {
210 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23, 210 { 1400, 1050, 101000000, 32, 48, 80, 4, 3, 23,
211 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, 211 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
212 false, }, 212 false, },
213 { 0x29, HDMI_DVI }, 213 { 0x29, HDMI_DVI },
214 }, 214 },
215 { 215 {
216 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21, 216 { 1680, 1050, 119000000, 32, 48, 80, 6, 3, 21,
217 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, 217 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
218 false, }, 218 false, },
219 { 0x39, HDMI_DVI }, 219 { 0x39, HDMI_DVI },
220 }, 220 },
221 { 221 {
222 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14, 222 { 1280, 800, 79500000, 32, 48, 80, 6, 3, 14,
223 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, 223 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
224 false, }, 224 false, },
225 { 0x1B, HDMI_DVI }, 225 { 0x1B, HDMI_DVI },
226 }, 226 },
227 { 227 {
228 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20, 228 { 1280, 720, 74250000, 40, 110, 220, 5, 5, 20,
229 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, 229 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
230 false, }, 230 false, },
231 { 0x55, HDMI_DVI }, 231 { 0x55, HDMI_DVI },
232 }, 232 },
233 { 233 {
234 { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26, 234 { 1920, 1200, 154000000, 32, 48, 80, 6, 3, 26,
235 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, 235 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
236 false, }, 236 false, },
237 { 0x44, HDMI_DVI }, 237 { 0x44, HDMI_DVI },
@@ -277,8 +277,8 @@ static bool hdmi_timings_compare(struct omap_video_timings *timing1,
277{ 277{
278 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync; 278 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
279 279
280 if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) == 280 if ((DIV_ROUND_CLOSEST(timing2->pixelclock, 1000000) ==
281 DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) && 281 DIV_ROUND_CLOSEST(timing1->pixelclock, 1000000)) &&
282 (timing2->x_res == timing1->x_res) && 282 (timing2->x_res == timing1->x_res) &&
283 (timing2->y_res == timing1->y_res)) { 283 (timing2->y_res == timing1->y_res)) {
284 284
diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
index efb9ee9e3c96..800b2bb4ed93 100644
--- a/drivers/video/omap2/dss/sdi.c
+++ b/drivers/video/omap2/dss/sdi.c
@@ -149,20 +149,19 @@ static int sdi_display_enable(struct omap_dss_device *dssdev)
149 t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; 149 t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
150 t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; 150 t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
151 151
152 r = sdi_calc_clock_div(t->pixel_clock * 1000, &fck, &dispc_cinfo); 152 r = sdi_calc_clock_div(t->pixelclock, &fck, &dispc_cinfo);
153 if (r) 153 if (r)
154 goto err_calc_clock_div; 154 goto err_calc_clock_div;
155 155
156 sdi.mgr_config.clock_info = dispc_cinfo; 156 sdi.mgr_config.clock_info = dispc_cinfo;
157 157
158 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div / 1000; 158 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
159 159
160 if (pck != t->pixel_clock) { 160 if (pck != t->pixelclock) {
161 DSSWARN("Could not find exact pixel clock. Requested %d kHz, " 161 DSSWARN("Could not find exact pixel clock. Requested %d Hz, got %lu Hz\n",
162 "got %lu kHz\n", 162 t->pixelclock, pck);
163 t->pixel_clock, pck);
164 163
165 t->pixel_clock = pck; 164 t->pixelclock = pck;
166 } 165 }
167 166
168 167
@@ -244,7 +243,7 @@ static int sdi_check_timings(struct omap_dss_device *dssdev,
244 if (mgr && !dispc_mgr_timings_ok(mgr->id, timings)) 243 if (mgr && !dispc_mgr_timings_ok(mgr->id, timings))
245 return -EINVAL; 244 return -EINVAL;
246 245
247 if (timings->pixel_clock == 0) 246 if (timings->pixelclock == 0)
248 return -EINVAL; 247 return -EINVAL;
249 248
250 return 0; 249 return 0;
diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
index 2cd7f7e42105..59ade34bd536 100644
--- a/drivers/video/omap2/dss/venc.c
+++ b/drivers/video/omap2/dss/venc.c
@@ -264,7 +264,7 @@ static const struct venc_config venc_config_pal_bdghi = {
264const struct omap_video_timings omap_dss_pal_timings = { 264const struct omap_video_timings omap_dss_pal_timings = {
265 .x_res = 720, 265 .x_res = 720,
266 .y_res = 574, 266 .y_res = 574,
267 .pixel_clock = 13500, 267 .pixelclock = 13500000,
268 .hsw = 64, 268 .hsw = 64,
269 .hfp = 12, 269 .hfp = 12,
270 .hbp = 68, 270 .hbp = 68,
@@ -279,7 +279,7 @@ EXPORT_SYMBOL(omap_dss_pal_timings);
279const struct omap_video_timings omap_dss_ntsc_timings = { 279const struct omap_video_timings omap_dss_ntsc_timings = {
280 .x_res = 720, 280 .x_res = 720,
281 .y_res = 482, 281 .y_res = 482,
282 .pixel_clock = 13500, 282 .pixelclock = 13500000,
283 .hsw = 64, 283 .hsw = 64,
284 .hfp = 16, 284 .hfp = 16,
285 .hbp = 58, 285 .hbp = 58,
diff --git a/drivers/video/omap2/dss/venc_panel.c b/drivers/video/omap2/dss/venc_panel.c
index f7d92c57bd73..af68cd444d7e 100644
--- a/drivers/video/omap2/dss/venc_panel.c
+++ b/drivers/video/omap2/dss/venc_panel.c
@@ -89,7 +89,7 @@ static int venc_panel_probe(struct omap_dss_device *dssdev)
89 const struct omap_video_timings default_timings = { 89 const struct omap_video_timings default_timings = {
90 .x_res = 720, 90 .x_res = 720,
91 .y_res = 574, 91 .y_res = 574,
92 .pixel_clock = 13500, 92 .pixelclock = 13500000,
93 .hsw = 64, 93 .hsw = 64,
94 .hfp = 12, 94 .hfp = 12,
95 .hbp = 68, 95 .hbp = 68,
diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
index fcb9e932d00c..8d02f164c8c6 100644
--- a/drivers/video/omap2/omapfb/omapfb-main.c
+++ b/drivers/video/omap2/omapfb/omapfb-main.c
@@ -723,8 +723,8 @@ int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
723 display->driver->get_timings(display, &timings); 723 display->driver->get_timings(display, &timings);
724 724
725 /* pixclock in ps, the rest in pixclock */ 725 /* pixclock in ps, the rest in pixclock */
726 var->pixclock = timings.pixel_clock != 0 ? 726 var->pixclock = timings.pixelclock != 0 ?
727 KHZ2PICOS(timings.pixel_clock) : 727 KHZ2PICOS(timings.pixelclock / 1000) :
728 0; 728 0;
729 var->left_margin = timings.hbp; 729 var->left_margin = timings.hbp;
730 var->right_margin = timings.hfp; 730 var->right_margin = timings.hfp;
@@ -2077,7 +2077,7 @@ static int omapfb_mode_to_timings(const char *mode_str,
2077 timings->sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES; 2077 timings->sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
2078 } 2078 }
2079 2079
2080 timings->pixel_clock = PICOS2KHZ(var->pixclock); 2080 timings->pixelclock = PICOS2KHZ(var->pixclock) * 1000;
2081 timings->hbp = var->left_margin; 2081 timings->hbp = var->left_margin;
2082 timings->hfp = var->right_margin; 2082 timings->hfp = var->right_margin;
2083 timings->vbp = var->upper_margin; 2083 timings->vbp = var->upper_margin;
@@ -2229,7 +2229,7 @@ static void fb_videomode_to_omap_timings(struct fb_videomode *m,
2229 2229
2230 t->x_res = m->xres; 2230 t->x_res = m->xres;
2231 t->y_res = m->yres; 2231 t->y_res = m->yres;
2232 t->pixel_clock = PICOS2KHZ(m->pixclock); 2232 t->pixelclock = PICOS2KHZ(m->pixclock) * 1000;
2233 t->hsw = m->hsync_len; 2233 t->hsw = m->hsync_len;
2234 t->hfp = m->right_margin; 2234 t->hfp = m->right_margin;
2235 t->hbp = m->left_margin; 2235 t->hbp = m->left_margin;
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index 1eb9aa605eee..24f3a57022b8 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -343,8 +343,8 @@ struct omap_video_timings {
343 u16 x_res; 343 u16 x_res;
344 /* Unit: pixels */ 344 /* Unit: pixels */
345 u16 y_res; 345 u16 y_res;
346 /* Unit: KHz */ 346 /* Unit: Hz */
347 u32 pixel_clock; 347 u32 pixelclock;
348 /* Unit: pixel clocks */ 348 /* Unit: pixel clocks */
349 u16 hsw; /* Horizontal synchronization pulse width */ 349 u16 hsw; /* Horizontal synchronization pulse width */
350 /* Unit: pixel clocks */ 350 /* Unit: pixel clocks */