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-rw-r--r--arch/arm/Kconfig3
-rw-r--r--arch/arm/mach-vexpress/ct-ca9x4.c55
-rw-r--r--arch/arm/mach-vexpress/include/mach/clkdev.h15
-rw-r--r--arch/arm/mach-vexpress/include/mach/motherboard.h19
-rw-r--r--arch/arm/mach-vexpress/v2m.c252
5 files changed, 139 insertions, 205 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 17beb66c6fa1..6374a08a6cab 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -310,14 +310,13 @@ config ARCH_VEXPRESS
310 select ARM_AMBA 310 select ARM_AMBA
311 select ARM_TIMER_SP804 311 select ARM_TIMER_SP804
312 select CLKDEV_LOOKUP 312 select CLKDEV_LOOKUP
313 select HAVE_MACH_CLKDEV 313 select COMMON_CLK
314 select GENERIC_CLOCKEVENTS 314 select GENERIC_CLOCKEVENTS
315 select HAVE_CLK 315 select HAVE_CLK
316 select HAVE_PATA_PLATFORM 316 select HAVE_PATA_PLATFORM
317 select ICST 317 select ICST
318 select NO_IOPORT 318 select NO_IOPORT
319 select PLAT_VERSATILE 319 select PLAT_VERSATILE
320 select PLAT_VERSATILE_CLOCK
321 select PLAT_VERSATILE_CLCD 320 select PLAT_VERSATILE_CLCD
322 help 321 help
323 This enables support for the ARM Ltd Versatile Express boards. 322 This enables support for the ARM Ltd Versatile Express boards.
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index ab15a5515312..61c492403b05 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -112,45 +112,11 @@ static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
112}; 112};
113 113
114 114
115static long ct_round(struct clk *clk, unsigned long rate) 115static struct v2m_osc ct_osc1 = {
116{ 116 .osc = 1,
117 return rate; 117 .rate_min = 10000000,
118} 118 .rate_max = 80000000,
119 119 .rate_default = 23750000,
120static int ct_set(struct clk *clk, unsigned long rate)
121{
122 u32 site = v2m_get_master_site();
123
124 return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(site) | 1, rate);
125}
126
127static const struct clk_ops osc1_clk_ops = {
128 .round = ct_round,
129 .set = ct_set,
130};
131
132static struct clk osc1_clk = {
133 .ops = &osc1_clk_ops,
134 .rate = 24000000,
135};
136
137static struct clk ct_sp804_clk = {
138 .rate = 1000000,
139};
140
141static struct clk_lookup lookups[] = {
142 { /* CLCD */
143 .dev_id = "ct:clcd",
144 .clk = &osc1_clk,
145 }, { /* SP804 timers */
146 .dev_id = "sp804",
147 .con_id = "ct-timer0",
148 .clk = &ct_sp804_clk,
149 }, { /* SP804 timers */
150 .dev_id = "sp804",
151 .con_id = "ct-timer1",
152 .clk = &ct_sp804_clk,
153 },
154}; 120};
155 121
156static struct resource pmu_resources[] = { 122static struct resource pmu_resources[] = {
@@ -183,14 +149,10 @@ static struct platform_device pmu_device = {
183 .resource = pmu_resources, 149 .resource = pmu_resources,
184}; 150};
185 151
186static void __init ct_ca9x4_init_early(void)
187{
188 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
189}
190
191static void __init ct_ca9x4_init(void) 152static void __init ct_ca9x4_init(void)
192{ 153{
193 int i; 154 int i;
155 struct clk *clk;
194 156
195#ifdef CONFIG_CACHE_L2X0 157#ifdef CONFIG_CACHE_L2X0
196 void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K); 158 void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
@@ -202,6 +164,10 @@ static void __init ct_ca9x4_init(void)
202 l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff); 164 l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
203#endif 165#endif
204 166
167 ct_osc1.site = v2m_get_master_site();
168 clk = v2m_osc_register("ct:osc1", &ct_osc1);
169 clk_register_clkdev(clk, NULL, "ct:clcd");
170
205 for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++) 171 for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
206 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource); 172 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
207 173
@@ -243,7 +209,6 @@ struct ct_desc ct_ca9x4_desc __initdata = {
243 .id = V2M_CT_ID_CA9, 209 .id = V2M_CT_ID_CA9,
244 .name = "CA9x4", 210 .name = "CA9x4",
245 .map_io = ct_ca9x4_map_io, 211 .map_io = ct_ca9x4_map_io,
246 .init_early = ct_ca9x4_init_early,
247 .init_irq = ct_ca9x4_init_irq, 212 .init_irq = ct_ca9x4_init_irq,
248 .init_tile = ct_ca9x4_init, 213 .init_tile = ct_ca9x4_init,
249#ifdef CONFIG_SMP 214#ifdef CONFIG_SMP
diff --git a/arch/arm/mach-vexpress/include/mach/clkdev.h b/arch/arm/mach-vexpress/include/mach/clkdev.h
deleted file mode 100644
index 3f8307d73cad..000000000000
--- a/arch/arm/mach-vexpress/include/mach/clkdev.h
+++ /dev/null
@@ -1,15 +0,0 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4#include <plat/clock.h>
5
6struct clk {
7 const struct clk_ops *ops;
8 unsigned long rate;
9 const struct icst_params *params;
10};
11
12#define __clk_get(clk) ({ 1; })
13#define __clk_put(clk) do { } while (0)
14
15#endif
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index f004ec982d29..1e388c7bf4d7 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -1,6 +1,8 @@
1#ifndef __MACH_MOTHERBOARD_H 1#ifndef __MACH_MOTHERBOARD_H
2#define __MACH_MOTHERBOARD_H 2#define __MACH_MOTHERBOARD_H
3 3
4#include <linux/clk-provider.h>
5
4/* 6/*
5 * Physical addresses, offset from V2M_PA_CS0-3 7 * Physical addresses, offset from V2M_PA_CS0-3
6 */ 8 */
@@ -147,4 +149,21 @@ struct ct_desc {
147 149
148extern struct ct_desc *ct_desc; 150extern struct ct_desc *ct_desc;
149 151
152/*
153 * OSC clock provider
154 */
155struct v2m_osc {
156 struct clk_hw hw;
157 u8 site; /* 0 = motherboard, 1 = site 1, 2 = site 2 */
158 u8 stack; /* board stack position */
159 u16 osc;
160 unsigned long rate_min;
161 unsigned long rate_max;
162 unsigned long rate_default;
163};
164
165#define to_v2m_osc(osc) container_of(osc, struct v2m_osc, hw)
166
167struct clk *v2m_osc_register(const char *name, struct v2m_osc *osc);
168
150#endif 169#endif
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index bb185921fce1..a3652a4ddc40 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -16,6 +16,7 @@
16#include <linux/spinlock.h> 16#include <linux/spinlock.h>
17#include <linux/usb/isp1760.h> 17#include <linux/usb/isp1760.h>
18#include <linux/clkdev.h> 18#include <linux/clkdev.h>
19#include <linux/clk-provider.h>
19#include <linux/mtd/physmap.h> 20#include <linux/mtd/physmap.h>
20 21
21#include <asm/arch_timer.h> 22#include <asm/arch_timer.h>
@@ -81,16 +82,6 @@ static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
81 sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0"); 82 sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
82} 83}
83 84
84static void __init v2m_timer_init(void)
85{
86 v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
87 v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
88}
89
90static struct sys_timer v2m_timer = {
91 .init = v2m_timer_init,
92};
93
94 85
95static DEFINE_SPINLOCK(v2m_cfg_lock); 86static DEFINE_SPINLOCK(v2m_cfg_lock);
96 87
@@ -326,87 +317,133 @@ static struct amba_device *v2m_amba_devs[] __initdata = {
326}; 317};
327 318
328 319
329static long v2m_osc_round(struct clk *clk, unsigned long rate) 320static unsigned long v2m_osc_recalc_rate(struct clk_hw *hw,
321 unsigned long parent_rate)
322{
323 struct v2m_osc *osc = to_v2m_osc(hw);
324
325 return !parent_rate ? osc->rate_default : parent_rate;
326}
327
328static long v2m_osc_round_rate(struct clk_hw *hw, unsigned long rate,
329 unsigned long *parent_rate)
330{ 330{
331 struct v2m_osc *osc = to_v2m_osc(hw);
332
333 if (WARN_ON(rate < osc->rate_min))
334 rate = osc->rate_min;
335
336 if (WARN_ON(rate > osc->rate_max))
337 rate = osc->rate_max;
338
331 return rate; 339 return rate;
332} 340}
333 341
334static int v2m_osc1_set(struct clk *clk, unsigned long rate) 342static int v2m_osc_set_rate(struct clk_hw *hw, unsigned long rate,
343 unsigned long parent_rate)
335{ 344{
336 return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(SYS_CFG_SITE_MB) | 1, 345 struct v2m_osc *osc = to_v2m_osc(hw);
337 rate); 346
347 v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(osc->site) |
348 SYS_CFG_STACK(osc->stack) | osc->osc, rate);
349
350 return 0;
338} 351}
339 352
340static const struct clk_ops osc1_clk_ops = { 353static struct clk_ops v2m_osc_ops = {
341 .round = v2m_osc_round, 354 .recalc_rate = v2m_osc_recalc_rate,
342 .set = v2m_osc1_set, 355 .round_rate = v2m_osc_round_rate,
356 .set_rate = v2m_osc_set_rate,
343}; 357};
344 358
345static struct clk osc1_clk = { 359struct clk * __init v2m_osc_register(const char *name, struct v2m_osc *osc)
346 .ops = &osc1_clk_ops, 360{
347 .rate = 24000000, 361 struct clk_init_data init;
362
363 WARN_ON(osc->site > 2);
364 WARN_ON(osc->stack > 15);
365 WARN_ON(osc->osc > 4095);
366
367 init.name = name;
368 init.ops = &v2m_osc_ops;
369 init.flags = CLK_IS_ROOT;
370 init.num_parents = 0;
371
372 osc->hw.init = &init;
373
374 return clk_register(NULL, &osc->hw);
375}
376
377static struct v2m_osc v2m_mb_osc1 = {
378 .site = SYS_CFG_SITE_MB,
379 .osc = 1,
380 .rate_min = 23750000,
381 .rate_max = 63500000,
382 .rate_default = 23750000,
348}; 383};
349 384
350static struct clk osc2_clk = { 385static const char *v2m_ref_clk_periphs[] __initconst = {
351 .rate = 24000000, 386 "mb:wdt", "1000f000.wdt", "1c0f0000.wdt", /* SP805 WDT */
352}; 387};
353 388
354static struct clk v2m_sp804_clk = { 389static const char *v2m_osc1_periphs[] __initconst = {
355 .rate = 1000000, 390 "mb:clcd", "1001f000.clcd", "1c1f0000.clcd", /* PL111 CLCD */
356}; 391};
357 392
358static struct clk v2m_ref_clk = { 393static const char *v2m_osc2_periphs[] __initconst = {
359 .rate = 32768, 394 "mb:mmci", "10005000.mmci", "1c050000.mmci", /* PL180 MMCI */
395 "mb:kmi0", "10006000.kmi", "1c060000.kmi", /* PL050 KMI0 */
396 "mb:kmi1", "10007000.kmi", "1c070000.kmi", /* PL050 KMI1 */
397 "mb:uart0", "10009000.uart", "1c090000.uart", /* PL011 UART0 */
398 "mb:uart1", "1000a000.uart", "1c0a0000.uart", /* PL011 UART1 */
399 "mb:uart2", "1000b000.uart", "1c0b0000.uart", /* PL011 UART2 */
400 "mb:uart3", "1000c000.uart", "1c0c0000.uart", /* PL011 UART3 */
360}; 401};
361 402
362static struct clk dummy_apb_pclk; 403static void __init v2m_clk_init(void)
363 404{
364static struct clk_lookup v2m_lookups[] = { 405 struct clk *clk;
365 { /* AMBA bus clock */ 406 int i;
366 .con_id = "apb_pclk", 407
367 .clk = &dummy_apb_pclk, 408 clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL,
368 }, { /* UART0 */ 409 CLK_IS_ROOT, 0);
369 .dev_id = "mb:uart0", 410 WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL));
370 .clk = &osc2_clk, 411
371 }, { /* UART1 */ 412 clk = clk_register_fixed_rate(NULL, "mb:ref_clk", NULL,
372 .dev_id = "mb:uart1", 413 CLK_IS_ROOT, 32768);
373 .clk = &osc2_clk, 414 for (i = 0; i < ARRAY_SIZE(v2m_ref_clk_periphs); i++)
374 }, { /* UART2 */ 415 WARN_ON(clk_register_clkdev(clk, NULL, v2m_ref_clk_periphs[i]));
375 .dev_id = "mb:uart2", 416
376 .clk = &osc2_clk, 417 clk = clk_register_fixed_rate(NULL, "mb:sp804_clk", NULL,
377 }, { /* UART3 */ 418 CLK_IS_ROOT, 1000000);
378 .dev_id = "mb:uart3", 419 WARN_ON(clk_register_clkdev(clk, "v2m-timer0", "sp804"));
379 .clk = &osc2_clk, 420 WARN_ON(clk_register_clkdev(clk, "v2m-timer1", "sp804"));
380 }, { /* KMI0 */ 421
381 .dev_id = "mb:kmi0", 422 clk = v2m_osc_register("mb:osc1", &v2m_mb_osc1);
382 .clk = &osc2_clk, 423 for (i = 0; i < ARRAY_SIZE(v2m_osc1_periphs); i++)
383 }, { /* KMI1 */ 424 WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc1_periphs[i]));
384 .dev_id = "mb:kmi1", 425
385 .clk = &osc2_clk, 426 clk = clk_register_fixed_rate(NULL, "mb:osc2", NULL,
386 }, { /* MMC0 */ 427 CLK_IS_ROOT, 24000000);
387 .dev_id = "mb:mmci", 428 for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++)
388 .clk = &osc2_clk, 429 WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i]));
389 }, { /* CLCD */ 430}
390 .dev_id = "mb:clcd", 431
391 .clk = &osc1_clk, 432static void __init v2m_timer_init(void)
392 }, { /* SP805 WDT */ 433{
393 .dev_id = "mb:wdt", 434 v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
394 .clk = &v2m_ref_clk, 435 v2m_clk_init();
395 }, { /* SP804 timers */ 436 v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
396 .dev_id = "sp804", 437}
397 .con_id = "v2m-timer0", 438
398 .clk = &v2m_sp804_clk, 439static struct sys_timer v2m_timer = {
399 }, { /* SP804 timers */ 440 .init = v2m_timer_init,
400 .dev_id = "sp804",
401 .con_id = "v2m-timer1",
402 .clk = &v2m_sp804_clk,
403 },
404}; 441};
405 442
406static void __init v2m_init_early(void) 443static void __init v2m_init_early(void)
407{ 444{
408 ct_desc->init_early(); 445 if (ct_desc->init_early)
409 clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups)); 446 ct_desc->init_early();
410 versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000); 447 versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
411} 448}
412 449
@@ -530,77 +567,6 @@ void __init v2m_dt_map_io(void)
530#endif 567#endif
531} 568}
532 569
533static struct clk_lookup v2m_dt_lookups[] = {
534 { /* AMBA bus clock */
535 .con_id = "apb_pclk",
536 .clk = &dummy_apb_pclk,
537 }, { /* SP804 timers */
538 .dev_id = "sp804",
539 .con_id = "v2m-timer0",
540 .clk = &v2m_sp804_clk,
541 }, { /* SP804 timers */
542 .dev_id = "sp804",
543 .con_id = "v2m-timer1",
544 .clk = &v2m_sp804_clk,
545 }, { /* PL180 MMCI */
546 .dev_id = "mb:mmci", /* 10005000.mmci */
547 .clk = &osc2_clk,
548 }, { /* PL050 KMI0 */
549 .dev_id = "10006000.kmi",
550 .clk = &osc2_clk,
551 }, { /* PL050 KMI1 */
552 .dev_id = "10007000.kmi",
553 .clk = &osc2_clk,
554 }, { /* PL011 UART0 */
555 .dev_id = "10009000.uart",
556 .clk = &osc2_clk,
557 }, { /* PL011 UART1 */
558 .dev_id = "1000a000.uart",
559 .clk = &osc2_clk,
560 }, { /* PL011 UART2 */
561 .dev_id = "1000b000.uart",
562 .clk = &osc2_clk,
563 }, { /* PL011 UART3 */
564 .dev_id = "1000c000.uart",
565 .clk = &osc2_clk,
566 }, { /* SP805 WDT */
567 .dev_id = "1000f000.wdt",
568 .clk = &v2m_ref_clk,
569 }, { /* PL111 CLCD */
570 .dev_id = "1001f000.clcd",
571 .clk = &osc1_clk,
572 },
573 /* RS1 memory map */
574 { /* PL180 MMCI */
575 .dev_id = "mb:mmci", /* 1c050000.mmci */
576 .clk = &osc2_clk,
577 }, { /* PL050 KMI0 */
578 .dev_id = "1c060000.kmi",
579 .clk = &osc2_clk,
580 }, { /* PL050 KMI1 */
581 .dev_id = "1c070000.kmi",
582 .clk = &osc2_clk,
583 }, { /* PL011 UART0 */
584 .dev_id = "1c090000.uart",
585 .clk = &osc2_clk,
586 }, { /* PL011 UART1 */
587 .dev_id = "1c0a0000.uart",
588 .clk = &osc2_clk,
589 }, { /* PL011 UART2 */
590 .dev_id = "1c0b0000.uart",
591 .clk = &osc2_clk,
592 }, { /* PL011 UART3 */
593 .dev_id = "1c0c0000.uart",
594 .clk = &osc2_clk,
595 }, { /* SP805 WDT */
596 .dev_id = "1c0f0000.wdt",
597 .clk = &v2m_ref_clk,
598 }, { /* PL111 CLCD */
599 .dev_id = "1c1f0000.clcd",
600 .clk = &osc1_clk,
601 },
602};
603
604void __init v2m_dt_init_early(void) 570void __init v2m_dt_init_early(void)
605{ 571{
606 struct device_node *node; 572 struct device_node *node;
@@ -622,8 +588,6 @@ void __init v2m_dt_init_early(void)
622 pr_warning("vexpress: DT HBI (%x) is not matching " 588 pr_warning("vexpress: DT HBI (%x) is not matching "
623 "hardware (%x)!\n", dt_hbi, hbi); 589 "hardware (%x)!\n", dt_hbi, hbi);
624 } 590 }
625
626 clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
627} 591}
628 592
629static struct of_device_id vexpress_irq_match[] __initdata = { 593static struct of_device_id vexpress_irq_match[] __initdata = {
@@ -645,6 +609,8 @@ static void __init v2m_dt_timer_init(void)
645 node = of_find_compatible_node(NULL, NULL, "arm,sp810"); 609 node = of_find_compatible_node(NULL, NULL, "arm,sp810");
646 v2m_sysctl_init(of_iomap(node, 0)); 610 v2m_sysctl_init(of_iomap(node, 0));
647 611
612 v2m_clk_init();
613
648 err = of_property_read_string(of_aliases, "arm,v2m_timer", &path); 614 err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
649 if (WARN_ON(err)) 615 if (WARN_ON(err))
650 return; 616 return;