diff options
-rw-r--r-- | arch/arm/mm/cache-l2x0.c | 206 |
1 files changed, 0 insertions, 206 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 57680e03da84..c5d754912f96 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c | |||
@@ -134,20 +134,6 @@ static inline void cache_sync(void) | |||
134 | cache_wait(base + L2X0_CACHE_SYNC, 1); | 134 | cache_wait(base + L2X0_CACHE_SYNC, 1); |
135 | } | 135 | } |
136 | 136 | ||
137 | static inline void l2x0_clean_line(unsigned long addr) | ||
138 | { | ||
139 | void __iomem *base = l2x0_base; | ||
140 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); | ||
141 | writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); | ||
142 | } | ||
143 | |||
144 | static inline void l2x0_inv_line(unsigned long addr) | ||
145 | { | ||
146 | void __iomem *base = l2x0_base; | ||
147 | cache_wait(base + L2X0_INV_LINE_PA, 1); | ||
148 | writel_relaxed(addr, base + L2X0_INV_LINE_PA); | ||
149 | } | ||
150 | |||
151 | #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) | 137 | #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) |
152 | static inline void debug_writel(unsigned long val) | 138 | static inline void debug_writel(unsigned long val) |
153 | { | 139 | { |
@@ -161,27 +147,6 @@ static inline void debug_writel(unsigned long val) | |||
161 | } | 147 | } |
162 | #endif | 148 | #endif |
163 | 149 | ||
164 | #ifdef CONFIG_PL310_ERRATA_588369 | ||
165 | static inline void l2x0_flush_line(unsigned long addr) | ||
166 | { | ||
167 | void __iomem *base = l2x0_base; | ||
168 | |||
169 | /* Clean by PA followed by Invalidate by PA */ | ||
170 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); | ||
171 | writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); | ||
172 | cache_wait(base + L2X0_INV_LINE_PA, 1); | ||
173 | writel_relaxed(addr, base + L2X0_INV_LINE_PA); | ||
174 | } | ||
175 | #else | ||
176 | |||
177 | static inline void l2x0_flush_line(unsigned long addr) | ||
178 | { | ||
179 | void __iomem *base = l2x0_base; | ||
180 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); | ||
181 | writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA); | ||
182 | } | ||
183 | #endif | ||
184 | |||
185 | static void l2x0_cache_sync(void) | 150 | static void l2x0_cache_sync(void) |
186 | { | 151 | { |
187 | unsigned long flags; | 152 | unsigned long flags; |
@@ -209,131 +174,6 @@ static void l2x0_flush_all(void) | |||
209 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | 174 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
210 | } | 175 | } |
211 | 176 | ||
212 | static void l2x0_clean_all(void) | ||
213 | { | ||
214 | unsigned long flags; | ||
215 | |||
216 | /* clean all ways */ | ||
217 | raw_spin_lock_irqsave(&l2x0_lock, flags); | ||
218 | __l2c_op_way(l2x0_base + L2X0_CLEAN_WAY); | ||
219 | cache_sync(); | ||
220 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | ||
221 | } | ||
222 | |||
223 | static void l2x0_inv_all(void) | ||
224 | { | ||
225 | unsigned long flags; | ||
226 | |||
227 | /* invalidate all ways */ | ||
228 | raw_spin_lock_irqsave(&l2x0_lock, flags); | ||
229 | /* Invalidating when L2 is enabled is a nono */ | ||
230 | BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN); | ||
231 | __l2c_op_way(l2x0_base + L2X0_INV_WAY); | ||
232 | cache_sync(); | ||
233 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | ||
234 | } | ||
235 | |||
236 | static void l2x0_inv_range(unsigned long start, unsigned long end) | ||
237 | { | ||
238 | void __iomem *base = l2x0_base; | ||
239 | unsigned long flags; | ||
240 | |||
241 | raw_spin_lock_irqsave(&l2x0_lock, flags); | ||
242 | if (start & (CACHE_LINE_SIZE - 1)) { | ||
243 | start &= ~(CACHE_LINE_SIZE - 1); | ||
244 | debug_writel(0x03); | ||
245 | l2x0_flush_line(start); | ||
246 | debug_writel(0x00); | ||
247 | start += CACHE_LINE_SIZE; | ||
248 | } | ||
249 | |||
250 | if (end & (CACHE_LINE_SIZE - 1)) { | ||
251 | end &= ~(CACHE_LINE_SIZE - 1); | ||
252 | debug_writel(0x03); | ||
253 | l2x0_flush_line(end); | ||
254 | debug_writel(0x00); | ||
255 | } | ||
256 | |||
257 | while (start < end) { | ||
258 | unsigned long blk_end = start + min(end - start, 4096UL); | ||
259 | |||
260 | while (start < blk_end) { | ||
261 | l2x0_inv_line(start); | ||
262 | start += CACHE_LINE_SIZE; | ||
263 | } | ||
264 | |||
265 | if (blk_end < end) { | ||
266 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | ||
267 | raw_spin_lock_irqsave(&l2x0_lock, flags); | ||
268 | } | ||
269 | } | ||
270 | cache_wait(base + L2X0_INV_LINE_PA, 1); | ||
271 | cache_sync(); | ||
272 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | ||
273 | } | ||
274 | |||
275 | static void l2x0_clean_range(unsigned long start, unsigned long end) | ||
276 | { | ||
277 | void __iomem *base = l2x0_base; | ||
278 | unsigned long flags; | ||
279 | |||
280 | if ((end - start) >= l2x0_size) { | ||
281 | l2x0_clean_all(); | ||
282 | return; | ||
283 | } | ||
284 | |||
285 | raw_spin_lock_irqsave(&l2x0_lock, flags); | ||
286 | start &= ~(CACHE_LINE_SIZE - 1); | ||
287 | while (start < end) { | ||
288 | unsigned long blk_end = start + min(end - start, 4096UL); | ||
289 | |||
290 | while (start < blk_end) { | ||
291 | l2x0_clean_line(start); | ||
292 | start += CACHE_LINE_SIZE; | ||
293 | } | ||
294 | |||
295 | if (blk_end < end) { | ||
296 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | ||
297 | raw_spin_lock_irqsave(&l2x0_lock, flags); | ||
298 | } | ||
299 | } | ||
300 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); | ||
301 | cache_sync(); | ||
302 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | ||
303 | } | ||
304 | |||
305 | static void l2x0_flush_range(unsigned long start, unsigned long end) | ||
306 | { | ||
307 | void __iomem *base = l2x0_base; | ||
308 | unsigned long flags; | ||
309 | |||
310 | if ((end - start) >= l2x0_size) { | ||
311 | l2x0_flush_all(); | ||
312 | return; | ||
313 | } | ||
314 | |||
315 | raw_spin_lock_irqsave(&l2x0_lock, flags); | ||
316 | start &= ~(CACHE_LINE_SIZE - 1); | ||
317 | while (start < end) { | ||
318 | unsigned long blk_end = start + min(end - start, 4096UL); | ||
319 | |||
320 | debug_writel(0x03); | ||
321 | while (start < blk_end) { | ||
322 | l2x0_flush_line(start); | ||
323 | start += CACHE_LINE_SIZE; | ||
324 | } | ||
325 | debug_writel(0x00); | ||
326 | |||
327 | if (blk_end < end) { | ||
328 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | ||
329 | raw_spin_lock_irqsave(&l2x0_lock, flags); | ||
330 | } | ||
331 | } | ||
332 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); | ||
333 | cache_sync(); | ||
334 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | ||
335 | } | ||
336 | |||
337 | static void l2x0_disable(void) | 177 | static void l2x0_disable(void) |
338 | { | 178 | { |
339 | unsigned long flags; | 179 | unsigned long flags; |
@@ -345,49 +185,6 @@ static void l2x0_disable(void) | |||
345 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | 185 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
346 | } | 186 | } |
347 | 187 | ||
348 | static void l2x0_enable(void __iomem *base, u32 aux, unsigned num_lock) | ||
349 | { | ||
350 | unsigned id; | ||
351 | |||
352 | id = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_PART_MASK; | ||
353 | if (id == L2X0_CACHE_ID_PART_L310) | ||
354 | num_lock = 8; | ||
355 | else | ||
356 | num_lock = 1; | ||
357 | |||
358 | /* l2x0 controller is disabled */ | ||
359 | writel_relaxed(aux, base + L2X0_AUX_CTRL); | ||
360 | |||
361 | /* Make sure that I&D is not locked down when starting */ | ||
362 | l2c_unlock(base, num_lock); | ||
363 | |||
364 | l2x0_inv_all(); | ||
365 | |||
366 | /* enable L2X0 */ | ||
367 | writel_relaxed(L2X0_CTRL_EN, base + L2X0_CTRL); | ||
368 | } | ||
369 | |||
370 | static void l2x0_resume(void) | ||
371 | { | ||
372 | void __iomem *base = l2x0_base; | ||
373 | |||
374 | if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) | ||
375 | l2x0_enable(base, l2x0_saved_regs.aux_ctrl, 0); | ||
376 | } | ||
377 | |||
378 | static const struct l2c_init_data l2x0_init_fns __initconst = { | ||
379 | .enable = l2x0_enable, | ||
380 | .outer_cache = { | ||
381 | .inv_range = l2x0_inv_range, | ||
382 | .clean_range = l2x0_clean_range, | ||
383 | .flush_range = l2x0_flush_range, | ||
384 | .flush_all = l2x0_flush_all, | ||
385 | .disable = l2x0_disable, | ||
386 | .sync = l2x0_cache_sync, | ||
387 | .resume = l2x0_resume, | ||
388 | }, | ||
389 | }; | ||
390 | |||
391 | /* | 188 | /* |
392 | * L2C-210 specific code. | 189 | * L2C-210 specific code. |
393 | * | 190 | * |
@@ -966,9 +763,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) | |||
966 | 763 | ||
967 | switch (cache_id & L2X0_CACHE_ID_PART_MASK) { | 764 | switch (cache_id & L2X0_CACHE_ID_PART_MASK) { |
968 | default: | 765 | default: |
969 | data = &l2x0_init_fns; | ||
970 | break; | ||
971 | |||
972 | case L2X0_CACHE_ID_PART_L210: | 766 | case L2X0_CACHE_ID_PART_L210: |
973 | data = &l2c210_data; | 767 | data = &l2c210_data; |
974 | break; | 768 | break; |