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-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/boot/dts/lpc32xx.dtsi34
-rw-r--r--arch/arm/boot/dts/phy3250.dts8
-rw-r--r--arch/arm/mach-lpc32xx/Kconfig32
-rw-r--r--arch/arm/mach-lpc32xx/serial.c85
5 files changed, 35 insertions, 126 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 84449dd8f031..973d5380a431 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1019,8 +1019,6 @@ source "arch/arm/mach-kirkwood/Kconfig"
1019 1019
1020source "arch/arm/mach-ks8695/Kconfig" 1020source "arch/arm/mach-ks8695/Kconfig"
1021 1021
1022source "arch/arm/mach-lpc32xx/Kconfig"
1023
1024source "arch/arm/mach-msm/Kconfig" 1022source "arch/arm/mach-msm/Kconfig"
1025 1023
1026source "arch/arm/mach-mv78xx0/Kconfig" 1024source "arch/arm/mach-mv78xx0/Kconfig"
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index a9b2a6a22024..acb68171d04d 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -126,24 +126,42 @@
126 reg = <0x2009C000 0x1000>; 126 reg = <0x2009C000 0x1000>;
127 }; 127 };
128 128
129 /* UART5 first since it is the default console, ttyS0 */
130 uart5: serial@40090000 {
131 /* actually, ns16550a w/ 64 byte fifos! */
132 compatible = "nxp,lpc3220-uart";
133 reg = <0x40090000 0x1000>;
134 interrupts = <9 0>;
135 clock-frequency = <13000000>;
136 reg-shift = <2>;
137 status = "disabled";
138 };
139
129 uart3: serial@40080000 { 140 uart3: serial@40080000 {
130 compatible = "nxp,serial"; 141 compatible = "nxp,lpc3220-uart";
131 reg = <0x40080000 0x1000>; 142 reg = <0x40080000 0x1000>;
143 interrupts = <7 0>;
144 clock-frequency = <13000000>;
145 reg-shift = <2>;
146 status = "disabled";
132 }; 147 };
133 148
134 uart4: serial@40088000 { 149 uart4: serial@40088000 {
135 compatible = "nxp,serial"; 150 compatible = "nxp,lpc3220-uart";
136 reg = <0x40088000 0x1000>; 151 reg = <0x40088000 0x1000>;
137 }; 152 interrupts = <8 0>;
138 153 clock-frequency = <13000000>;
139 uart5: serial@40090000 { 154 reg-shift = <2>;
140 compatible = "nxp,serial"; 155 status = "disabled";
141 reg = <0x40090000 0x1000>;
142 }; 156 };
143 157
144 uart6: serial@40098000 { 158 uart6: serial@40098000 {
145 compatible = "nxp,serial"; 159 compatible = "nxp,lpc3220-uart";
146 reg = <0x40098000 0x1000>; 160 reg = <0x40098000 0x1000>;
161 interrupts = <10 0>;
162 clock-frequency = <13000000>;
163 reg-shift = <2>;
164 status = "disabled";
147 }; 165 };
148 166
149 i2c1: i2c@400A0000 { 167 i2c1: i2c@400A0000 {
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
index d5432378f234..57d4961372d4 100644
--- a/arch/arm/boot/dts/phy3250.dts
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -94,6 +94,14 @@
94 }; 94 };
95 95
96 apb { 96 apb {
97 uart5: serial@40090000 {
98 status = "okay";
99 };
100
101 uart3: serial@40080000 {
102 status = "okay";
103 };
104
97 i2c1: i2c@400A0000 { 105 i2c1: i2c@400A0000 {
98 clock-frequency = <100000>; 106 clock-frequency = <100000>;
99 107
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
deleted file mode 100644
index e0b3eee83834..000000000000
--- a/arch/arm/mach-lpc32xx/Kconfig
+++ /dev/null
@@ -1,32 +0,0 @@
1if ARCH_LPC32XX
2
3menu "Individual UART enable selections"
4
5config ARCH_LPC32XX_UART3_SELECT
6 bool "Add support for standard UART3"
7 help
8 Adds support for standard UART 3 when the 8250 serial support
9 is enabled.
10
11config ARCH_LPC32XX_UART4_SELECT
12 bool "Add support for standard UART4"
13 help
14 Adds support for standard UART 4 when the 8250 serial support
15 is enabled.
16
17config ARCH_LPC32XX_UART5_SELECT
18 bool "Add support for standard UART5"
19 default y
20 help
21 Adds support for standard UART 5 when the 8250 serial support
22 is enabled.
23
24config ARCH_LPC32XX_UART6_SELECT
25 bool "Add support for standard UART6"
26 help
27 Adds support for standard UART 6 when the 8250 serial support
28 is enabled.
29
30endmenu
31
32endif
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
index f2735281616a..b5a3f3423f63 100644
--- a/arch/arm/mach-lpc32xx/serial.c
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -31,59 +31,6 @@
31 31
32#define LPC32XX_SUART_FIFO_SIZE 64 32#define LPC32XX_SUART_FIFO_SIZE 64
33 33
34/* Standard 8250/16550 compatible serial ports */
35static struct plat_serial8250_port serial_std_platform_data[] = {
36#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
37 {
38 .membase = io_p2v(LPC32XX_UART5_BASE),
39 .mapbase = LPC32XX_UART5_BASE,
40 .irq = IRQ_LPC32XX_UART_IIR5,
41 .uartclk = LPC32XX_MAIN_OSC_FREQ,
42 .regshift = 2,
43 .iotype = UPIO_MEM32,
44 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
45 UPF_SKIP_TEST,
46 },
47#endif
48#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
49 {
50 .membase = io_p2v(LPC32XX_UART3_BASE),
51 .mapbase = LPC32XX_UART3_BASE,
52 .irq = IRQ_LPC32XX_UART_IIR3,
53 .uartclk = LPC32XX_MAIN_OSC_FREQ,
54 .regshift = 2,
55 .iotype = UPIO_MEM32,
56 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
57 UPF_SKIP_TEST,
58 },
59#endif
60#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
61 {
62 .membase = io_p2v(LPC32XX_UART4_BASE),
63 .mapbase = LPC32XX_UART4_BASE,
64 .irq = IRQ_LPC32XX_UART_IIR4,
65 .uartclk = LPC32XX_MAIN_OSC_FREQ,
66 .regshift = 2,
67 .iotype = UPIO_MEM32,
68 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
69 UPF_SKIP_TEST,
70 },
71#endif
72#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
73 {
74 .membase = io_p2v(LPC32XX_UART6_BASE),
75 .mapbase = LPC32XX_UART6_BASE,
76 .irq = IRQ_LPC32XX_UART_IIR6,
77 .uartclk = LPC32XX_MAIN_OSC_FREQ,
78 .regshift = 2,
79 .iotype = UPIO_MEM32,
80 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
81 UPF_SKIP_TEST,
82 },
83#endif
84 { },
85};
86
87struct uartinit { 34struct uartinit {
88 char *uart_ck_name; 35 char *uart_ck_name;
89 u32 ck_mode_mask; 36 u32 ck_mode_mask;
@@ -92,7 +39,6 @@ struct uartinit {
92}; 39};
93 40
94static struct uartinit uartinit_data[] __initdata = { 41static struct uartinit uartinit_data[] __initdata = {
95#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
96 { 42 {
97 .uart_ck_name = "uart5_ck", 43 .uart_ck_name = "uart5_ck",
98 .ck_mode_mask = 44 .ck_mode_mask =
@@ -100,8 +46,6 @@ static struct uartinit uartinit_data[] __initdata = {
100 .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL, 46 .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
101 .mapbase = LPC32XX_UART5_BASE, 47 .mapbase = LPC32XX_UART5_BASE,
102 }, 48 },
103#endif
104#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
105 { 49 {
106 .uart_ck_name = "uart3_ck", 50 .uart_ck_name = "uart3_ck",
107 .ck_mode_mask = 51 .ck_mode_mask =
@@ -109,8 +53,6 @@ static struct uartinit uartinit_data[] __initdata = {
109 .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL, 53 .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
110 .mapbase = LPC32XX_UART3_BASE, 54 .mapbase = LPC32XX_UART3_BASE,
111 }, 55 },
112#endif
113#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
114 { 56 {
115 .uart_ck_name = "uart4_ck", 57 .uart_ck_name = "uart4_ck",
116 .ck_mode_mask = 58 .ck_mode_mask =
@@ -118,8 +60,6 @@ static struct uartinit uartinit_data[] __initdata = {
118 .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL, 60 .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
119 .mapbase = LPC32XX_UART4_BASE, 61 .mapbase = LPC32XX_UART4_BASE,
120 }, 62 },
121#endif
122#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
123 { 63 {
124 .uart_ck_name = "uart6_ck", 64 .uart_ck_name = "uart6_ck",
125 .ck_mode_mask = 65 .ck_mode_mask =
@@ -127,19 +67,6 @@ static struct uartinit uartinit_data[] __initdata = {
127 .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL, 67 .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
128 .mapbase = LPC32XX_UART6_BASE, 68 .mapbase = LPC32XX_UART6_BASE,
129 }, 69 },
130#endif
131};
132
133static struct platform_device serial_std_platform_device = {
134 .name = "serial8250",
135 .id = 0,
136 .dev = {
137 .platform_data = serial_std_platform_data,
138 },
139};
140
141static struct platform_device *lpc32xx_serial_devs[] __initdata = {
142 &serial_std_platform_device,
143}; 70};
144 71
145void __init lpc32xx_serial_init(void) 72void __init lpc32xx_serial_init(void)
@@ -156,15 +83,8 @@ void __init lpc32xx_serial_init(void)
156 clk = clk_get(NULL, uartinit_data[i].uart_ck_name); 83 clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
157 if (!IS_ERR(clk)) { 84 if (!IS_ERR(clk)) {
158 clk_enable(clk); 85 clk_enable(clk);
159 serial_std_platform_data[i].uartclk =
160 clk_get_rate(clk);
161 } 86 }
162 87
163 /* Fall back on main osc rate if clock rate return fails */
164 if (serial_std_platform_data[i].uartclk == 0)
165 serial_std_platform_data[i].uartclk =
166 LPC32XX_MAIN_OSC_FREQ;
167
168 /* Setup UART clock modes for all UARTs, disable autoclock */ 88 /* Setup UART clock modes for all UARTs, disable autoclock */
169 clkmodes |= uartinit_data[i].ck_mode_mask; 89 clkmodes |= uartinit_data[i].ck_mode_mask;
170 90
@@ -189,7 +109,7 @@ void __init lpc32xx_serial_init(void)
189 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); 109 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
190 for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) { 110 for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
191 /* Force a flush of the RX FIFOs to work around a HW bug */ 111 /* Force a flush of the RX FIFOs to work around a HW bug */
192 puart = serial_std_platform_data[i].mapbase; 112 puart = uartinit_data[i].mapbase;
193 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); 113 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
194 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); 114 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
195 j = LPC32XX_SUART_FIFO_SIZE; 115 j = LPC32XX_SUART_FIFO_SIZE;
@@ -202,7 +122,4 @@ void __init lpc32xx_serial_init(void)
202 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); 122 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
203 tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB; 123 tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
204 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); 124 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
205
206 platform_add_devices(lpc32xx_serial_devs,
207 ARRAY_SIZE(lpc32xx_serial_devs));
208} 125}
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 11:04:06 -0400