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-rw-r--r--drivers/gpu/drm/radeon/r600_blit.c52
1 files changed, 31 insertions, 21 deletions
diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c
index d988eece0187..626a9ab7075a 100644
--- a/drivers/gpu/drm/radeon/r600_blit.c
+++ b/drivers/gpu/drm/radeon/r600_blit.c
@@ -774,6 +774,7 @@ r600_blit_swap(struct drm_device *dev,
774{ 774{
775 drm_radeon_private_t *dev_priv = dev->dev_private; 775 drm_radeon_private_t *dev_priv = dev->dev_private;
776 int cb_format, tex_format; 776 int cb_format, tex_format;
777 int sx2, sy2, dx2, dy2;
777 u64 vb_addr; 778 u64 vb_addr;
778 u32 *vb; 779 u32 *vb;
779 780
@@ -790,16 +791,10 @@ r600_blit_swap(struct drm_device *dev,
790 vb = r600_nomm_get_vb_ptr(dev); 791 vb = r600_nomm_get_vb_ptr(dev);
791 } 792 }
792 793
793 if (cpp == 4) { 794 sx2 = sx + w;
794 cb_format = COLOR_8_8_8_8; 795 sy2 = sy + h;
795 tex_format = FMT_8_8_8_8; 796 dx2 = dx + w;
796 } else if (cpp == 2) { 797 dy2 = dy + h;
797 cb_format = COLOR_5_6_5;
798 tex_format = FMT_5_6_5;
799 } else {
800 cb_format = COLOR_8;
801 tex_format = FMT_8;
802 }
803 798
804 vb[0] = i2f(dx); 799 vb[0] = i2f(dx);
805 vb[1] = i2f(dy); 800 vb[1] = i2f(dy);
@@ -807,31 +802,46 @@ r600_blit_swap(struct drm_device *dev,
807 vb[3] = i2f(sy); 802 vb[3] = i2f(sy);
808 803
809 vb[4] = i2f(dx); 804 vb[4] = i2f(dx);
810 vb[5] = i2f(dy + h); 805 vb[5] = i2f(dy2);
811 vb[6] = i2f(sx); 806 vb[6] = i2f(sx);
812 vb[7] = i2f(sy + h); 807 vb[7] = i2f(sy2);
813 808
814 vb[8] = i2f(dx + w); 809 vb[8] = i2f(dx2);
815 vb[9] = i2f(dy + h); 810 vb[9] = i2f(dy2);
816 vb[10] = i2f(sx + w); 811 vb[10] = i2f(sx2);
817 vb[11] = i2f(sy + h); 812 vb[11] = i2f(sy2);
813
814 switch(cpp) {
815 case 4:
816 cb_format = COLOR_8_8_8_8;
817 tex_format = FMT_8_8_8_8;
818 break;
819 case 2:
820 cb_format = COLOR_5_6_5;
821 tex_format = FMT_5_6_5;
822 break;
823 default:
824 cb_format = COLOR_8;
825 tex_format = FMT_8;
826 break;
827 }
818 828
819 /* src */ 829 /* src */
820 set_tex_resource(dev_priv, tex_format, 830 set_tex_resource(dev_priv, tex_format,
821 src_pitch / cpp, 831 src_pitch / cpp,
822 sy + h, src_pitch / cpp, 832 sy2, src_pitch / cpp,
823 src_gpu_addr); 833 src_gpu_addr);
824 834
825 cp_set_surface_sync(dev_priv, 835 cp_set_surface_sync(dev_priv,
826 R600_TC_ACTION_ENA, (src_pitch * (sy + h)), src_gpu_addr); 836 R600_TC_ACTION_ENA, src_pitch * sy2, src_gpu_addr);
827 837
828 /* dst */ 838 /* dst */
829 set_render_target(dev_priv, cb_format, 839 set_render_target(dev_priv, cb_format,
830 dst_pitch / cpp, dy + h, 840 dst_pitch / cpp, dy2,
831 dst_gpu_addr); 841 dst_gpu_addr);
832 842
833 /* scissors */ 843 /* scissors */
834 set_scissors(dev_priv, dx, dy, dx + w, dy + h); 844 set_scissors(dev_priv, dx, dy, dx2, dy2);
835 845
836 /* Vertex buffer setup */ 846 /* Vertex buffer setup */
837 vb_addr = dev_priv->gart_buffers_offset + 847 vb_addr = dev_priv->gart_buffers_offset +
@@ -844,7 +854,7 @@ r600_blit_swap(struct drm_device *dev,
844 854
845 cp_set_surface_sync(dev_priv, 855 cp_set_surface_sync(dev_priv,
846 R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA, 856 R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
847 dst_pitch * (dy + h), dst_gpu_addr); 857 dst_pitch * dy2, dst_gpu_addr);
848 858
849 dev_priv->blit_vb->used += 12 * 4; 859 dev_priv->blit_vb->used += 12 * 4;
850} 860}