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-rw-r--r--drivers/net/tg3.c21
-rw-r--r--drivers/net/tg3.h1
2 files changed, 7 insertions, 15 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 9bd1be48d0f5..45fcbc3b141d 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1742,7 +1742,8 @@ static int tg3_phy_reset(struct tg3 *tp)
1742 tw32(TG3_CPMU_CTRL, cpmuctrl); 1742 tw32(TG3_CPMU_CTRL, cpmuctrl);
1743 } 1743 }
1744 1744
1745 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) { 1745 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1746 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1746 u32 val; 1747 u32 val;
1747 1748
1748 val = tr32(TG3_CPMU_LSPD_1000MB_CLK); 1749 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
@@ -2004,7 +2005,8 @@ static void tg3_power_down_phy(struct tg3 *tp)
2004 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))) 2005 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2005 return; 2006 return;
2006 2007
2007 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) { 2008 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2009 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2008 val = tr32(TG3_CPMU_LSPD_1000MB_CLK); 2010 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2009 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; 2011 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2010 val |= CPMU_LSPD_1000MB_MACCLK_12_5; 2012 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
@@ -3815,8 +3817,7 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3815 err = tg3_setup_copper_phy(tp, force_reset); 3817 err = tg3_setup_copper_phy(tp, force_reset);
3816 } 3818 }
3817 3819
3818 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 || 3820 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
3819 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3820 u32 val, scale; 3821 u32 val, scale;
3821 3822
3822 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; 3823 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
@@ -7044,8 +7045,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7044 7045
7045 tg3_write_sig_legacy(tp, RESET_KIND_INIT); 7046 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7046 7047
7047 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 || 7048 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7048 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
7049 val = tr32(TG3_CPMU_CTRL); 7049 val = tr32(TG3_CPMU_CTRL);
7050 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); 7050 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7051 tw32(TG3_CPMU_CTRL, val); 7051 tw32(TG3_CPMU_CTRL, val);
@@ -12283,16 +12283,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12283 12283
12284 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || 12284 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12285 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || 12285 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12286 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { 12286 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12287 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; 12287 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12288 12288
12289 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
12290 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1 ||
12291 tp->pci_chip_rev_id == CHIPREV_ID_5761_A0 ||
12292 tp->pci_chip_rev_id == CHIPREV_ID_5761_A1)
12293 tp->tg3_flags3 |= TG3_FLG3_5761_5784_AX_FIXES;
12294 }
12295
12296 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state(). 12289 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12297 * GPIO1 driven high will bring 5700's external PHY out of reset. 12290 * GPIO1 driven high will bring 5700's external PHY out of reset.
12298 * It is also used as eeprom write protect on LOMs. 12291 * It is also used as eeprom write protect on LOMs.
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 65b5ff45d201..417de07ca895 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2510,7 +2510,6 @@ struct tg3 {
2510 u32 tg3_flags3; 2510 u32 tg3_flags3;
2511#define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001 2511#define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001
2512#define TG3_FLG3_ENABLE_APE 0x00000002 2512#define TG3_FLG3_ENABLE_APE 0x00000002
2513#define TG3_FLG3_5761_5784_AX_FIXES 0x00000004
2514#define TG3_FLG3_5701_DMA_BUG 0x00000008 2513#define TG3_FLG3_5701_DMA_BUG 0x00000008
2515#define TG3_FLG3_USE_PHYLIB 0x00000010 2514#define TG3_FLG3_USE_PHYLIB 0x00000010
2516#define TG3_FLG3_MDIOBUS_INITED 0x00000020 2515#define TG3_FLG3_MDIOBUS_INITED 0x00000020