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-rw-r--r--arch/powerpc/boot/dcr.h27
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
index 8e7ee2a4298f..f6b793573b96 100644
--- a/arch/powerpc/boot/dcr.h
+++ b/arch/powerpc/boot/dcr.h
@@ -147,4 +147,31 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
147#define DCRN_405_CPC0_CR0 0xb1 147#define DCRN_405_CPC0_CR0 0xb1
148#define DCRN_405_CPC0_CR1 0xb2 148#define DCRN_405_CPC0_CR1 0xb2
149 149
150
151/* 440GX Clock control etc */
152
153
154#define DCRN_CPR0_CLKUPD 0x020
155#define DCRN_CPR0_PLLC 0x040
156#define DCRN_CPR0_PLLD 0x060
157#define DCRN_CPR0_PRIMAD 0x080
158#define DCRN_CPR0_PRIMBD 0x0a0
159#define DCRN_CPR0_OPBD 0x0c0
160#define DCRN_CPR0_PERD 0x0e0
161#define DCRN_CPR0_MALD 0x100
162
163/* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
164
165#define DCRN_CPR0_CFGADDR 0xc
166#define DCRN_CPR0_CFGDATA 0xd
167
168#define CPR0_READ(offset) ({\
169 mtdcr(DCRN_CPR0_CFGADDR, offset); \
170 mfdcr(DCRN_CPR0_CFGDATA); })
171#define CPR0_WRITE(offset, data) ({\
172 mtdcr(DCRN_CPR0_CFGADDR, offset); \
173 mtdcr(DCRN_CPR0_CFGDATA, data); })
174
175
176
150#endif /* _PPC_BOOT_DCR_H_ */ 177#endif /* _PPC_BOOT_DCR_H_ */