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-rw-r--r--arch/x86/mm/pgtable.c21
1 files changed, 14 insertions, 7 deletions
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index c96314abd144..0004ac72dbdd 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -399,13 +399,20 @@ int pmdp_test_and_clear_young(struct vm_area_struct *vma,
399int ptep_clear_flush_young(struct vm_area_struct *vma, 399int ptep_clear_flush_young(struct vm_area_struct *vma,
400 unsigned long address, pte_t *ptep) 400 unsigned long address, pte_t *ptep)
401{ 401{
402 int young; 402 /*
403 403 * On x86 CPUs, clearing the accessed bit without a TLB flush
404 young = ptep_test_and_clear_young(vma, address, ptep); 404 * doesn't cause data corruption. [ It could cause incorrect
405 if (young) 405 * page aging and the (mistaken) reclaim of hot pages, but the
406 flush_tlb_page(vma, address); 406 * chance of that should be relatively low. ]
407 407 *
408 return young; 408 * So as a performance optimization don't flush the TLB when
409 * clearing the accessed bit, it will eventually be flushed by
410 * a context switch or a VM operation anyway. [ In the rare
411 * event of it not getting flushed for a long time the delay
412 * shouldn't really matter because there's no real memory
413 * pressure for swapout to react to. ]
414 */
415 return ptep_test_and_clear_young(vma, address, ptep);
409} 416}
410 417
411#ifdef CONFIG_TRANSPARENT_HUGEPAGE 418#ifdef CONFIG_TRANSPARENT_HUGEPAGE