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-rw-r--r--arch/arm64/include/asm/insn.h77
-rw-r--r--arch/arm64/kernel/Makefile2
-rw-r--r--arch/arm64/kernel/insn.c91
3 files changed, 169 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
new file mode 100644
index 000000000000..1bdc44c27456
--- /dev/null
+++ b/arch/arm64/include/asm/insn.h
@@ -0,0 +1,77 @@
1/*
2 * Copyright (C) 2013 Huawei Ltd.
3 * Author: Jiang Liu <liuj97@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17#ifndef __ASM_INSN_H
18#define __ASM_INSN_H
19#include <linux/types.h>
20
21/*
22 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
23 * Section C3.1 "A64 instruction index by encoding":
24 * AArch64 main encoding table
25 * Bit position
26 * 28 27 26 25 Encoding Group
27 * 0 0 - - Unallocated
28 * 1 0 0 - Data processing, immediate
29 * 1 0 1 - Branch, exception generation and system instructions
30 * - 1 - 0 Loads and stores
31 * - 1 0 1 Data processing - register
32 * 0 1 1 1 Data processing - SIMD and floating point
33 * 1 1 1 1 Data processing - SIMD and floating point
34 * "-" means "don't care"
35 */
36enum aarch64_insn_encoding_class {
37 AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */
38 AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */
39 AARCH64_INSN_CLS_DP_REG, /* Data processing - register */
40 AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */
41 AARCH64_INSN_CLS_LDST, /* Loads and stores */
42 AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and
43 * system instructions */
44};
45
46enum aarch64_insn_hint_op {
47 AARCH64_INSN_HINT_NOP = 0x0 << 5,
48 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
49 AARCH64_INSN_HINT_WFE = 0x2 << 5,
50 AARCH64_INSN_HINT_WFI = 0x3 << 5,
51 AARCH64_INSN_HINT_SEV = 0x4 << 5,
52 AARCH64_INSN_HINT_SEVL = 0x5 << 5,
53};
54
55#define __AARCH64_INSN_FUNCS(abbr, mask, val) \
56static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
57{ return (code & (mask)) == (val); } \
58static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
59{ return (val); }
60
61__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
62__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
63__AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001)
64__AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002)
65__AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003)
66__AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000)
67__AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F)
68
69#undef __AARCH64_INSN_FUNCS
70
71bool aarch64_insn_is_nop(u32 insn);
72
73enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
74
75bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
76
77#endif /* __ASM_INSN_H */
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 1cd339d5037b..1ea7221f8853 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -9,7 +9,7 @@ AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET)
9arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \ 9arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \
10 entry-fpsimd.o process.o ptrace.o setup.o signal.o \ 10 entry-fpsimd.o process.o ptrace.o setup.o signal.o \
11 sys.o stacktrace.o time.o traps.o io.o vdso.o \ 11 sys.o stacktrace.o time.o traps.o io.o vdso.o \
12 hyp-stub.o psci.o cpu_ops.o 12 hyp-stub.o psci.o cpu_ops.o insn.o
13 13
14arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \ 14arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \
15 sys_compat.o 15 sys_compat.o
diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
new file mode 100644
index 000000000000..56a2498ab3e3
--- /dev/null
+++ b/arch/arm64/kernel/insn.c
@@ -0,0 +1,91 @@
1/*
2 * Copyright (C) 2013 Huawei Ltd.
3 * Author: Jiang Liu <liuj97@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17#include <linux/compiler.h>
18#include <linux/kernel.h>
19#include <asm/insn.h>
20
21static int aarch64_insn_encoding_class[] = {
22 AARCH64_INSN_CLS_UNKNOWN,
23 AARCH64_INSN_CLS_UNKNOWN,
24 AARCH64_INSN_CLS_UNKNOWN,
25 AARCH64_INSN_CLS_UNKNOWN,
26 AARCH64_INSN_CLS_LDST,
27 AARCH64_INSN_CLS_DP_REG,
28 AARCH64_INSN_CLS_LDST,
29 AARCH64_INSN_CLS_DP_FPSIMD,
30 AARCH64_INSN_CLS_DP_IMM,
31 AARCH64_INSN_CLS_DP_IMM,
32 AARCH64_INSN_CLS_BR_SYS,
33 AARCH64_INSN_CLS_BR_SYS,
34 AARCH64_INSN_CLS_LDST,
35 AARCH64_INSN_CLS_DP_REG,
36 AARCH64_INSN_CLS_LDST,
37 AARCH64_INSN_CLS_DP_FPSIMD,
38};
39
40enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
41{
42 return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
43}
44
45/* NOP is an alias of HINT */
46bool __kprobes aarch64_insn_is_nop(u32 insn)
47{
48 if (!aarch64_insn_is_hint(insn))
49 return false;
50
51 switch (insn & 0xFE0) {
52 case AARCH64_INSN_HINT_YIELD:
53 case AARCH64_INSN_HINT_WFE:
54 case AARCH64_INSN_HINT_WFI:
55 case AARCH64_INSN_HINT_SEV:
56 case AARCH64_INSN_HINT_SEVL:
57 return false;
58 default:
59 return true;
60 }
61}
62
63static bool __kprobes __aarch64_insn_hotpatch_safe(u32 insn)
64{
65 if (aarch64_get_insn_class(insn) != AARCH64_INSN_CLS_BR_SYS)
66 return false;
67
68 return aarch64_insn_is_b(insn) ||
69 aarch64_insn_is_bl(insn) ||
70 aarch64_insn_is_svc(insn) ||
71 aarch64_insn_is_hvc(insn) ||
72 aarch64_insn_is_smc(insn) ||
73 aarch64_insn_is_brk(insn) ||
74 aarch64_insn_is_nop(insn);
75}
76
77/*
78 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
79 * Section B2.6.5 "Concurrent modification and execution of instructions":
80 * Concurrent modification and execution of instructions can lead to the
81 * resulting instruction performing any behavior that can be achieved by
82 * executing any sequence of instructions that can be executed from the
83 * same Exception level, except where the instruction before modification
84 * and the instruction after modification is a B, BL, NOP, BKPT, SVC, HVC,
85 * or SMC instruction.
86 */
87bool __kprobes aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn)
88{
89 return __aarch64_insn_hotpatch_safe(old_insn) &&
90 __aarch64_insn_hotpatch_safe(new_insn);
91}
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