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-rw-r--r--arch/sh/Kconfig17
-rw-r--r--arch/sh/Kconfig.debug1
-rw-r--r--arch/sh/Makefile1
-rw-r--r--arch/sh/boards/mpc1211/Makefile8
-rw-r--r--arch/sh/boards/mpc1211/pci.c295
-rw-r--r--arch/sh/boards/mpc1211/rtc.c136
-rw-r--r--arch/sh/boards/mpc1211/setup.c347
-rw-r--r--arch/sh/boards/renesas/migor/setup.c11
-rw-r--r--arch/sh/boards/renesas/r7780rp/irq-r7780mp.c2
-rw-r--r--arch/sh/boards/renesas/r7780rp/irq-r7780rp.c2
-rw-r--r--arch/sh/boards/renesas/r7780rp/irq-r7785rp.c2
-rw-r--r--arch/sh/boards/renesas/r7780rp/setup.c24
-rw-r--r--arch/sh/boards/renesas/rts7751r2d/setup.c7
-rw-r--r--arch/sh/boards/se/7206/setup.c17
-rw-r--r--arch/sh/boards/se/7722/setup.c6
-rw-r--r--arch/sh/boot/compressed/Makefile_321
-rw-r--r--arch/sh/boot/compressed/Makefile_641
-rw-r--r--arch/sh/kernel/cpu/irq/intc-sh5.c73
-rw-r--r--arch/sh/kernel/cpu/irq/intc.c93
-rw-r--r--arch/sh/kernel/cpu/sh2a/fpu.c4
-rw-r--r--arch/sh/kernel/cpu/sh3/Makefile2
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh3.c71
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c22
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c32
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c25
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c35
-rw-r--r--arch/sh/kernel/cpu/sh5/entry.S28
-rw-r--r--arch/sh/kernel/cpu/sh5/probe.c4
-rw-r--r--arch/sh/kernel/early_printk.c30
-rw-r--r--arch/sh/kernel/setup.c46
-rw-r--r--arch/sh/kernel/sh_ksyms_32.c2
-rw-r--r--arch/sh/kernel/sh_ksyms_64.c26
-rw-r--r--arch/sh/kernel/time_64.c5
-rw-r--r--arch/sh/lib64/dbg.c2
-rw-r--r--arch/sh/mm/Makefile_647
-rw-r--r--arch/sh/mm/cache-sh5.c2
-rw-r--r--arch/sh/mm/ioremap_64.c2
-rw-r--r--arch/sh/mm/numa.c2
-rw-r--r--arch/sh/tools/mach-types1
-rw-r--r--drivers/input/serio/i8042-io.h2
-rw-r--r--drivers/mtd/maps/Kconfig9
-rw-r--r--drivers/mtd/maps/Makefile1
-rw-r--r--drivers/mtd/maps/mpc1211.c80
-rw-r--r--drivers/rtc/rtc-sh.c14
-rw-r--r--drivers/serial/sh-sci.c32
-rw-r--r--drivers/serial/sh-sci.h27
-rw-r--r--include/asm-sh/cpu-sh3/dma.h10
-rw-r--r--include/asm-sh/hw_irq.h19
-rw-r--r--include/asm-sh/io.h12
-rw-r--r--include/asm-sh/keyboard.h13
-rw-r--r--include/asm-sh/mmu_context.h4
-rw-r--r--include/asm-sh/mmzone.h2
-rw-r--r--include/asm-sh/mpc1211/dma.h303
-rw-r--r--include/asm-sh/mpc1211/io.h22
-rw-r--r--include/asm-sh/mpc1211/keyboard.h60
-rw-r--r--include/asm-sh/mpc1211/m1543c.h200
-rw-r--r--include/asm-sh/mpc1211/mc146818rtc.h6
-rw-r--r--include/asm-sh/mpc1211/mpc1211.h18
-rw-r--r--include/asm-sh/mpc1211/pci.h38
-rw-r--r--include/asm-sh/r7780rp.h4
-rw-r--r--include/asm-sh/tlb_64.h10
-rw-r--r--include/asm-sh/topology.h11
-rw-r--r--include/asm-sh/uaccess_64.h2
63 files changed, 498 insertions, 1793 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 6a679c3e15e8..8a68160079a9 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -448,14 +448,6 @@ config SH_DREAMCAST
448 Select Dreamcast if configuring for a SEGA Dreamcast. 448 Select Dreamcast if configuring for a SEGA Dreamcast.
449 More information at <http://www.linux-sh.org> 449 More information at <http://www.linux-sh.org>
450 450
451config SH_MPC1211
452 bool "Interface MPC1211"
453 depends on CPU_SUBTYPE_SH7751 && BROKEN
454 help
455 CTP/PCI-SH02 is a CPU module computer that is produced
456 by Interface Corporation.
457 More information at <http://www.interface.co.jp>
458
459config SH_SH03 451config SH_SH03
460 bool "Interface CTP/PCI-SH03" 452 bool "Interface CTP/PCI-SH03"
461 depends on CPU_SUBTYPE_SH7751 453 depends on CPU_SUBTYPE_SH7751
@@ -657,8 +649,7 @@ source "arch/sh/drivers/Kconfig"
657endmenu 649endmenu
658 650
659config ISA_DMA_API 651config ISA_DMA_API
660 def_bool y 652 bool
661 depends on SH_MPC1211
662 653
663menu "Kernel features" 654menu "Kernel features"
664 655
@@ -666,7 +657,7 @@ source kernel/Kconfig.hz
666 657
667config KEXEC 658config KEXEC
668 bool "kexec system call (EXPERIMENTAL)" 659 bool "kexec system call (EXPERIMENTAL)"
669 depends on EXPERIMENTAL 660 depends on SUPERH32 && EXPERIMENTAL
670 help 661 help
671 kexec is a system call that implements the ability to shutdown your 662 kexec is a system call that implements the ability to shutdown your
672 current kernel, and to start another kernel. It is like a reboot 663 current kernel, and to start another kernel. It is like a reboot
@@ -683,7 +674,7 @@ config KEXEC
683 674
684config CRASH_DUMP 675config CRASH_DUMP
685 bool "kernel crash dumps (EXPERIMENTAL)" 676 bool "kernel crash dumps (EXPERIMENTAL)"
686 depends on EXPERIMENTAL 677 depends on SUPERH32 && EXPERIMENTAL
687 help 678 help
688 Generate crash dump after being started by kexec. 679 Generate crash dump after being started by kexec.
689 This should be normally only set in special crash dump kernels 680 This should be normally only set in special crash dump kernels
@@ -763,7 +754,7 @@ menu "Boot options"
763 754
764config ZERO_PAGE_OFFSET 755config ZERO_PAGE_OFFSET
765 hex "Zero page offset" 756 hex "Zero page offset"
766 default "0x00004000" if SH_MPC1211 || SH_SH03 757 default "0x00004000" if SH_SH03
767 default "0x00010000" if PAGE_SIZE_64KB 758 default "0x00010000" if PAGE_SIZE_64KB
768 default "0x00002000" if PAGE_SIZE_8KB 759 default "0x00002000" if PAGE_SIZE_8KB
769 default "0x00001000" 760 default "0x00001000"
diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug
index d9d28f9dd0db..0d2ef1e9a6fd 100644
--- a/arch/sh/Kconfig.debug
+++ b/arch/sh/Kconfig.debug
@@ -7,6 +7,7 @@ source "lib/Kconfig.debug"
7 7
8config SH_STANDARD_BIOS 8config SH_STANDARD_BIOS
9 bool "Use LinuxSH standard BIOS" 9 bool "Use LinuxSH standard BIOS"
10 depends on SUPERH32
10 help 11 help
11 Say Y here if your target has the gdb-sh-stub 12 Say Y here if your target has the gdb-sh-stub
12 package from www.m17n.org (or any conforming standard LinuxSH BIOS) 13 package from www.m17n.org (or any conforming standard LinuxSH BIOS)
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index bb06f83e6239..8050b03d51fc 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -110,7 +110,6 @@ machdir-$(CONFIG_SH_7343_SOLUTION_ENGINE) += se/7343
110machdir-$(CONFIG_SH_7721_SOLUTION_ENGINE) += se/7721 110machdir-$(CONFIG_SH_7721_SOLUTION_ENGINE) += se/7721
111machdir-$(CONFIG_SH_HP6XX) += hp6xx 111machdir-$(CONFIG_SH_HP6XX) += hp6xx
112machdir-$(CONFIG_SH_DREAMCAST) += dreamcast 112machdir-$(CONFIG_SH_DREAMCAST) += dreamcast
113machdir-$(CONFIG_SH_MPC1211) += mpc1211
114machdir-$(CONFIG_SH_SH03) += sh03 113machdir-$(CONFIG_SH_SH03) += sh03
115machdir-$(CONFIG_SH_SECUREEDGE5410) += snapgear 114machdir-$(CONFIG_SH_SECUREEDGE5410) += snapgear
116machdir-$(CONFIG_SH_RTS7751R2D) += renesas/rts7751r2d 115machdir-$(CONFIG_SH_RTS7751R2D) += renesas/rts7751r2d
diff --git a/arch/sh/boards/mpc1211/Makefile b/arch/sh/boards/mpc1211/Makefile
deleted file mode 100644
index 8cd31b5d200b..000000000000
--- a/arch/sh/boards/mpc1211/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Makefile for the Interface (CTP/PCI/MPC-SH02) specific parts of the kernel
3#
4
5obj-y := setup.o rtc.o
6
7obj-$(CONFIG_PCI) += pci.o
8
diff --git a/arch/sh/boards/mpc1211/pci.c b/arch/sh/boards/mpc1211/pci.c
deleted file mode 100644
index 23849f70f133..000000000000
--- a/arch/sh/boards/mpc1211/pci.c
+++ /dev/null
@@ -1,295 +0,0 @@
1/*
2 * Low-Level PCI Support for the MPC-1211(CTP/PCI/MPC-SH02)
3 *
4 * (c) 2002-2003 Saito.K & Jeanne
5 *
6 * Dustin McIntire (dustin@sensoria.com)
7 * Derived from arch/i386/kernel/pci-*.c which bore the message:
8 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
9 *
10 * May be copied or modified under the terms of the GNU General Public
11 * License. See linux/COPYING for more information.
12 *
13 */
14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pci.h>
19#include <linux/sched.h>
20#include <linux/ioport.h>
21#include <linux/errno.h>
22#include <linux/irq.h>
23#include <linux/interrupt.h>
24
25#include <asm/machvec.h>
26#include <asm/io.h>
27#include <asm/mpc1211/pci.h>
28
29static struct resource mpcpci_io_resource = {
30 "MPCPCI IO",
31 0x00000000,
32 0xffffffff,
33 IORESOURCE_IO
34};
35
36static struct resource mpcpci_mem_resource = {
37 "MPCPCI mem",
38 0x00000000,
39 0xffffffff,
40 IORESOURCE_MEM
41};
42
43static struct pci_ops pci_direct_conf1;
44struct pci_channel board_pci_channels[] = {
45 {&pci_direct_conf1, &mpcpci_io_resource, &mpcpci_mem_resource, 0, 256},
46 {NULL, NULL, NULL, 0, 0},
47};
48
49/*
50 * Direct access to PCI hardware...
51 */
52
53
54#define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
55
56/*
57 * Functions for accessing PCI configuration space with type 1 accesses
58 */
59static int pci_conf1_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
60{
61 u32 word;
62 unsigned long flags;
63
64 /*
65 * PCIPDR may only be accessed as 32 bit words,
66 * so we must do byte alignment by hand
67 */
68 local_irq_save(flags);
69 writel(CONFIG_CMD(bus,devfn,where), PCIPAR);
70 word = readl(PCIPDR);
71 local_irq_restore(flags);
72
73 switch (size) {
74 case 1:
75 switch (where & 0x3) {
76 case 3:
77 *value = (u8)(word >> 24);
78 break;
79 case 2:
80 *value = (u8)(word >> 16);
81 break;
82 case 1:
83 *value = (u8)(word >> 8);
84 break;
85 default:
86 *value = (u8)word;
87 break;
88 }
89 break;
90 case 2:
91 switch (where & 0x3) {
92 case 3:
93 *value = (u16)(word >> 24);
94 local_irq_save(flags);
95 writel(CONFIG_CMD(bus,devfn,(where+1)), PCIPAR);
96 word = readl(PCIPDR);
97 local_irq_restore(flags);
98 *value |= ((word & 0xff) << 8);
99 break;
100 case 2:
101 *value = (u16)(word >> 16);
102 break;
103 case 1:
104 *value = (u16)(word >> 8);
105 break;
106 default:
107 *value = (u16)word;
108 break;
109 }
110 break;
111 case 4:
112 *value = word;
113 break;
114 }
115 PCIDBG(4,"pci_conf1_read@0x%08x=0x%x\n", CONFIG_CMD(bus,devfn,where),*value);
116 return PCIBIOS_SUCCESSFUL;
117}
118
119/*
120 * Since MPC-1211 only does 32bit access we'll have to do a read,mask,write operation.
121 * We'll allow an odd byte offset, though it should be illegal.
122 */
123static int pci_conf1_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
124{
125 u32 word,mask = 0;
126 unsigned long flags;
127 u32 shift = (where & 3) * 8;
128
129 if(size == 1) {
130 mask = ((1 << 8) - 1) << shift; // create the byte mask
131 } else if(size == 2){
132 if(shift == 24)
133 return PCIBIOS_BAD_REGISTER_NUMBER;
134 mask = ((1 << 16) - 1) << shift; // create the word mask
135 }
136 local_irq_save(flags);
137 writel(CONFIG_CMD(bus,devfn,where), PCIPAR);
138 if(size == 4){
139 writel(value, PCIPDR);
140 local_irq_restore(flags);
141 PCIDBG(4,"pci_conf1_write@0x%08x=0x%x\n", CONFIG_CMD(bus,devfn,where),value);
142 return PCIBIOS_SUCCESSFUL;
143 }
144 word = readl(PCIPDR);
145 word &= ~mask;
146 word |= ((value << shift) & mask);
147 writel(word, PCIPDR);
148 local_irq_restore(flags);
149 PCIDBG(4,"pci_conf1_write@0x%08x=0x%x\n", CONFIG_CMD(bus,devfn,where),word);
150 return PCIBIOS_SUCCESSFUL;
151}
152
153#undef CONFIG_CMD
154
155static struct pci_ops pci_direct_conf1 = {
156 .read = pci_conf1_read,
157 .write = pci_conf1_write,
158};
159
160static void __devinit quirk_ali_ide_ports(struct pci_dev *dev)
161{
162 dev->resource[0].start = 0x1f0;
163 dev->resource[0].end = 0x1f7;
164 dev->resource[0].flags = IORESOURCE_IO;
165 dev->resource[1].start = 0x3f6;
166 dev->resource[1].end = 0x3f6;
167 dev->resource[1].flags = IORESOURCE_IO;
168 dev->resource[2].start = 0x170;
169 dev->resource[2].end = 0x177;
170 dev->resource[2].flags = IORESOURCE_IO;
171 dev->resource[3].start = 0x376;
172 dev->resource[3].end = 0x376;
173 dev->resource[3].flags = IORESOURCE_IO;
174 dev->resource[4].start = 0xf000;
175 dev->resource[4].end = 0xf00f;
176 dev->resource[4].flags = IORESOURCE_IO;
177}
178DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, quirk_ali_ide_ports);
179
180char * __devinit pcibios_setup(char *str)
181{
182 return str;
183}
184
185/*
186 * Called after each bus is probed, but before its children
187 * are examined.
188 */
189
190void __devinit pcibios_fixup_bus(struct pci_bus *b)
191{
192 pci_read_bridge_bases(b);
193}
194
195/*
196 * IRQ functions
197 */
198static inline u8 bridge_swizzle(u8 pin, u8 slot)
199{
200 return (((pin-1) + slot) % 4) + 1;
201}
202
203static inline u8 bridge_swizzle_pci_1(u8 pin, u8 slot)
204{
205 return (((pin-1) - slot) & 3) + 1;
206}
207
208static u8 __init mpc1211_swizzle(struct pci_dev *dev, u8 *pinp)
209{
210 unsigned long flags;
211 u8 pin = *pinp;
212 u32 word;
213
214 for ( ; dev->bus->self; dev = dev->bus->self) {
215 if (!pin)
216 continue;
217
218 if (dev->bus->number == 1) {
219 local_irq_save(flags);
220 writel(0x80000000 | 0x2c, PCIPAR);
221 word = readl(PCIPDR);
222 local_irq_restore(flags);
223 word >>= 16;
224
225 if (word == 0x0001)
226 pin = bridge_swizzle_pci_1(pin, PCI_SLOT(dev->devfn));
227 else
228 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
229 } else
230 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
231 }
232
233 *pinp = pin;
234
235 return PCI_SLOT(dev->devfn);
236}
237
238static int __init map_mpc1211_irq(struct pci_dev *dev, u8 slot, u8 pin)
239{
240 int irq = -1;
241
242 /* now lookup the actual IRQ on a platform specific basis (pci-'platform'.c) */
243 if (dev->bus->number == 0) {
244 switch (slot) {
245 case 13: irq = 9; break; /* USB */
246 case 22: irq = 10; break; /* LAN */
247 default: irq = 0; break;
248 }
249 } else {
250 switch (pin) {
251 case 0: irq = 0; break;
252 case 1: irq = 7; break;
253 case 2: irq = 9; break;
254 case 3: irq = 10; break;
255 case 4: irq = 11; break;
256 }
257 }
258
259 if( irq < 0 ) {
260 PCIDBG(3, "PCI: Error mapping IRQ on device %s\n", pci_name(dev));
261 return irq;
262 }
263
264 PCIDBG(2, "Setting IRQ for slot %s to %d\n", pci_name(dev), irq);
265
266 return irq;
267}
268
269void __init pcibios_fixup_irqs(void)
270{
271 pci_fixup_irqs(mpc1211_swizzle, map_mpc1211_irq);
272}
273
274void pcibios_align_resource(void *data, struct resource *res,
275 resource_size_t size, resource_size_t align)
276{
277 resource_size_t start = res->start;
278
279 if (res->flags & IORESOURCE_IO) {
280 if (start >= 0x10000UL) {
281 if ((start & 0xffffUL) < 0x4000UL) {
282 start = (start & 0xffff0000UL) + 0x4000UL;
283 } else if ((start & 0xffffUL) >= 0xf000UL) {
284 start = (start & 0xffff0000UL) + 0x10000UL;
285 }
286 res->start = start;
287 } else {
288 if (start & 0x300) {
289 start = (start + 0x3ff) & ~0x3ff;
290 res->start = start;
291 }
292 }
293 }
294}
295
diff --git a/arch/sh/boards/mpc1211/rtc.c b/arch/sh/boards/mpc1211/rtc.c
deleted file mode 100644
index 03b123a4bba4..000000000000
--- a/arch/sh/boards/mpc1211/rtc.c
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * linux/arch/sh/kernel/rtc-mpc1211.c -- MPC-1211 on-chip RTC support
3 *
4 * Copyright (C) 2002 Saito.K & Jeanne
5 *
6 */
7
8#include <linux/init.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/time.h>
12#include <linux/bcd.h>
13#include <linux/mc146818rtc.h>
14
15unsigned long get_cmos_time(void)
16{
17 unsigned int year, mon, day, hour, min, sec;
18
19 spin_lock(&rtc_lock);
20
21 do {
22 sec = CMOS_READ(RTC_SECONDS);
23 min = CMOS_READ(RTC_MINUTES);
24 hour = CMOS_READ(RTC_HOURS);
25 day = CMOS_READ(RTC_DAY_OF_MONTH);
26 mon = CMOS_READ(RTC_MONTH);
27 year = CMOS_READ(RTC_YEAR);
28 } while (sec != CMOS_READ(RTC_SECONDS));
29
30 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
31 BCD_TO_BIN(sec);
32 BCD_TO_BIN(min);
33 BCD_TO_BIN(hour);
34 BCD_TO_BIN(day);
35 BCD_TO_BIN(mon);
36 BCD_TO_BIN(year);
37 }
38
39 spin_unlock(&rtc_lock);
40
41 year += 1900;
42 if (year < 1970)
43 year += 100;
44
45 return mktime(year, mon, day, hour, min, sec);
46}
47
48void mpc1211_rtc_gettimeofday(struct timeval *tv)
49{
50
51 tv->tv_sec = get_cmos_time();
52 tv->tv_usec = 0;
53}
54
55/* arc/i386/kernel/time.c */
56/*
57 * In order to set the CMOS clock precisely, set_rtc_mmss has to be
58 * called 500 ms after the second nowtime has started, because when
59 * nowtime is written into the registers of the CMOS clock, it will
60 * jump to the next second precisely 500 ms later. Check the Motorola
61 * MC146818A or Dallas DS12887 data sheet for details.
62 *
63 * BUG: This routine does not handle hour overflow properly; it just
64 * sets the minutes. Usually you'll only notice that after reboot!
65 */
66static int set_rtc_mmss(unsigned long nowtime)
67{
68 int retval = 0;
69 int real_seconds, real_minutes, cmos_minutes;
70 unsigned char save_control, save_freq_select;
71
72 /* gets recalled with irq locally disabled */
73 spin_lock(&rtc_lock);
74 save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
75 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
76
77 save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
78 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
79
80 cmos_minutes = CMOS_READ(RTC_MINUTES);
81 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
82 BCD_TO_BIN(cmos_minutes);
83
84 /*
85 * since we're only adjusting minutes and seconds,
86 * don't interfere with hour overflow. This avoids
87 * messing with unknown time zones but requires your
88 * RTC not to be off by more than 15 minutes
89 */
90 real_seconds = nowtime % 60;
91 real_minutes = nowtime / 60;
92 if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
93 real_minutes += 30; /* correct for half hour time zone */
94 real_minutes %= 60;
95
96 if (abs(real_minutes - cmos_minutes) < 30) {
97 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
98 BIN_TO_BCD(real_seconds);
99 BIN_TO_BCD(real_minutes);
100 }
101 CMOS_WRITE(real_seconds,RTC_SECONDS);
102 CMOS_WRITE(real_minutes,RTC_MINUTES);
103 } else {
104 printk(KERN_WARNING
105 "set_rtc_mmss: can't update from %d to %d\n",
106 cmos_minutes, real_minutes);
107 retval = -1;
108 }
109
110 /* The following flags have to be released exactly in this order,
111 * otherwise the DS12887 (popular MC146818A clone with integrated
112 * battery and quartz) will not reset the oscillator and will not
113 * update precisely 500 ms later. You won't find this mentioned in
114 * the Dallas Semiconductor data sheets, but who believes data
115 * sheets anyway ... -- Markus Kuhn
116 */
117 CMOS_WRITE(save_control, RTC_CONTROL);
118 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
119 spin_unlock(&rtc_lock);
120
121 return retval;
122}
123
124int mpc1211_rtc_settimeofday(const struct timeval *tv)
125{
126 unsigned long nowtime = tv->tv_sec;
127
128 return set_rtc_mmss(nowtime);
129}
130
131void mpc1211_time_init(void)
132{
133 rtc_sh_get_time = mpc1211_rtc_gettimeofday;
134 rtc_sh_set_time = mpc1211_rtc_settimeofday;
135}
136
diff --git a/arch/sh/boards/mpc1211/setup.c b/arch/sh/boards/mpc1211/setup.c
deleted file mode 100644
index fede36361dc7..000000000000
--- a/arch/sh/boards/mpc1211/setup.c
+++ /dev/null
@@ -1,347 +0,0 @@
1/*
2 * linux/arch/sh/boards/mpc1211/setup.c
3 *
4 * Copyright (C) 2002 Saito.K & Jeanne, Fujii.Y
5 *
6 */
7
8#include <linux/init.h>
9#include <linux/irq.h>
10#include <linux/hdreg.h>
11#include <linux/ide.h>
12#include <linux/interrupt.h>
13#include <linux/platform_device.h>
14#include <asm/io.h>
15#include <asm/machvec.h>
16#include <asm/mpc1211/mpc1211.h>
17#include <asm/mpc1211/pci.h>
18#include <asm/mpc1211/m1543c.h>
19
20/* ALI15X3 SMBus address offsets */
21#define SMBHSTSTS (0 + 0x3100)
22#define SMBHSTCNT (1 + 0x3100)
23#define SMBHSTSTART (2 + 0x3100)
24#define SMBHSTCMD (7 + 0x3100)
25#define SMBHSTADD (3 + 0x3100)
26#define SMBHSTDAT0 (4 + 0x3100)
27#define SMBHSTDAT1 (5 + 0x3100)
28#define SMBBLKDAT (6 + 0x3100)
29
30/* Other settings */
31#define MAX_TIMEOUT 500 /* times 1/100 sec */
32
33/* ALI15X3 command constants */
34#define ALI15X3_ABORT 0x04
35#define ALI15X3_T_OUT 0x08
36#define ALI15X3_QUICK 0x00
37#define ALI15X3_BYTE 0x10
38#define ALI15X3_BYTE_DATA 0x20
39#define ALI15X3_WORD_DATA 0x30
40#define ALI15X3_BLOCK_DATA 0x40
41#define ALI15X3_BLOCK_CLR 0x80
42
43/* ALI15X3 status register bits */
44#define ALI15X3_STS_IDLE 0x04
45#define ALI15X3_STS_BUSY 0x08
46#define ALI15X3_STS_DONE 0x10
47#define ALI15X3_STS_DEV 0x20 /* device error */
48#define ALI15X3_STS_COLL 0x40 /* collision or no response */
49#define ALI15X3_STS_TERM 0x80 /* terminated by abort */
50#define ALI15X3_STS_ERR 0xE0 /* all the bad error bits */
51
52static void __init pci_write_config(unsigned long busNo,
53 unsigned long devNo,
54 unsigned long fncNo,
55 unsigned long cnfAdd,
56 unsigned long cnfData)
57{
58 ctrl_outl((0x80000000
59 + ((busNo & 0xff) << 16)
60 + ((devNo & 0x1f) << 11)
61 + ((fncNo & 0x07) << 8)
62 + (cnfAdd & 0xfc)), PCIPAR);
63
64 ctrl_outl(cnfData, PCIPDR);
65}
66
67/*
68 Initialize IRQ setting
69*/
70
71static unsigned char m_irq_mask = 0xfb;
72static unsigned char s_irq_mask = 0xff;
73
74static void disable_mpc1211_irq(unsigned int irq)
75{
76 if( irq < 8) {
77 m_irq_mask |= (1 << irq);
78 outb(m_irq_mask,I8259_M_MR);
79 } else {
80 s_irq_mask |= (1 << (irq - 8));
81 outb(s_irq_mask,I8259_S_MR);
82 }
83
84}
85
86static void enable_mpc1211_irq(unsigned int irq)
87{
88 if( irq < 8) {
89 m_irq_mask &= ~(1 << irq);
90 outb(m_irq_mask,I8259_M_MR);
91 } else {
92 s_irq_mask &= ~(1 << (irq - 8));
93 outb(s_irq_mask,I8259_S_MR);
94 }
95}
96
97static inline int mpc1211_irq_real(unsigned int irq)
98{
99 int value;
100 int irqmask;
101
102 if ( irq < 8) {
103 irqmask = 1<<irq;
104 outb(0x0b,I8259_M_CR); /* ISR register */
105 value = inb(I8259_M_CR) & irqmask;
106 outb(0x0a,I8259_M_CR); /* back ro the IPR reg */
107 return value;
108 }
109 irqmask = 1<<(irq - 8);
110 outb(0x0b,I8259_S_CR); /* ISR register */
111 value = inb(I8259_S_CR) & irqmask;
112 outb(0x0a,I8259_S_CR); /* back ro the IPR reg */
113 return value;
114}
115
116static void mask_and_ack_mpc1211(unsigned int irq)
117{
118 if(irq < 8) {
119 if(m_irq_mask & (1<<irq)){
120 if(!mpc1211_irq_real(irq)){
121 atomic_inc(&irq_err_count)
122 printk("spurious 8259A interrupt: IRQ %x\n",irq);
123 }
124 } else {
125 m_irq_mask |= (1<<irq);
126 }
127 inb(I8259_M_MR); /* DUMMY */
128 outb(m_irq_mask,I8259_M_MR); /* disable */
129 outb(0x60+irq,I8259_M_CR); /* EOI */
130
131 } else {
132 if(s_irq_mask & (1<<(irq - 8))){
133 if(!mpc1211_irq_real(irq)){
134 atomic_inc(&irq_err_count);
135 printk("spurious 8259A interrupt: IRQ %x\n",irq);
136 }
137 } else {
138 s_irq_mask |= (1<<(irq - 8));
139 }
140 inb(I8259_S_MR); /* DUMMY */
141 outb(s_irq_mask,I8259_S_MR); /* disable */
142 outb(0x60+(irq-8),I8259_S_CR); /* EOI */
143 outb(0x60+2,I8259_M_CR);
144 }
145}
146
147static void end_mpc1211_irq(unsigned int irq)
148{
149 enable_mpc1211_irq(irq);
150}
151
152static unsigned int startup_mpc1211_irq(unsigned int irq)
153{
154 enable_mpc1211_irq(irq);
155 return 0;
156}
157
158static void shutdown_mpc1211_irq(unsigned int irq)
159{
160 disable_mpc1211_irq(irq);
161}
162
163static struct hw_interrupt_type mpc1211_irq_type = {
164 .typename = "MPC1211-IRQ",
165 .startup = startup_mpc1211_irq,
166 .shutdown = shutdown_mpc1211_irq,
167 .enable = enable_mpc1211_irq,
168 .disable = disable_mpc1211_irq,
169 .ack = mask_and_ack_mpc1211,
170 .end = end_mpc1211_irq
171};
172
173static void make_mpc1211_irq(unsigned int irq)
174{
175 irq_desc[irq].chip = &mpc1211_irq_type;
176 irq_desc[irq].status = IRQ_DISABLED;
177 irq_desc[irq].action = 0;
178 irq_desc[irq].depth = 1;
179 disable_mpc1211_irq(irq);
180}
181
182int mpc1211_irq_demux(int irq)
183{
184 unsigned int poll;
185
186 if( irq == 2 ) {
187 outb(0x0c,I8259_M_CR);
188 poll = inb(I8259_M_CR);
189 if(poll & 0x80) {
190 irq = (poll & 0x07);
191 }
192 if( irq == 2) {
193 outb(0x0c,I8259_S_CR);
194 poll = inb(I8259_S_CR);
195 irq = (poll & 0x07) + 8;
196 }
197 }
198 return irq;
199}
200
201static void __init init_mpc1211_IRQ(void)
202{
203 int i;
204 /*
205 * Super I/O (Just mimic PC):
206 * 1: keyboard
207 * 3: serial 1
208 * 4: serial 0
209 * 5: printer
210 * 6: floppy
211 * 8: rtc
212 * 10: lan
213 * 12: mouse
214 * 14: ide0
215 * 15: ide1
216 */
217
218 pci_write_config(0,0,0,0x54, 0xb0b0002d);
219 outb(0x11, I8259_M_CR); /* mater icw1 edge trigger */
220 outb(0x11, I8259_S_CR); /* slave icw1 edge trigger */
221 outb(0x20, I8259_M_MR); /* m icw2 base vec 0x08 */
222 outb(0x28, I8259_S_MR); /* s icw2 base vec 0x70 */
223 outb(0x04, I8259_M_MR); /* m icw3 slave irq2 */
224 outb(0x02, I8259_S_MR); /* s icw3 slave id */
225 outb(0x01, I8259_M_MR); /* m icw4 non buf normal eoi*/
226 outb(0x01, I8259_S_MR); /* s icw4 non buf normal eo1*/
227 outb(0xfb, I8259_M_MR); /* disable irq0--irq7 */
228 outb(0xff, I8259_S_MR); /* disable irq8--irq15 */
229
230 for ( i=0; i < 16; i++) {
231 if(i != 2) {
232 make_mpc1211_irq(i);
233 }
234 }
235}
236
237static void delay1000(void)
238{
239 int i;
240
241 for (i=0; i<1000; i++)
242 ctrl_delay();
243}
244
245static int put_smb_blk(unsigned char *p, int address, int command, int no)
246{
247 int temp;
248 int timeout;
249 int i;
250
251 outb(0xff, SMBHSTSTS);
252 temp = inb(SMBHSTSTS);
253 for (timeout = 0; (timeout < MAX_TIMEOUT) && !(temp & ALI15X3_STS_IDLE); timeout++) {
254 delay1000();
255 temp = inb(SMBHSTSTS);
256 }
257 if (timeout >= MAX_TIMEOUT){
258 return -1;
259 }
260
261 outb(((address & 0x7f) << 1), SMBHSTADD);
262 outb(0xc0, SMBHSTCNT);
263 outb(command & 0xff, SMBHSTCMD);
264 outb(no & 0x1f, SMBHSTDAT0);
265
266 for(i = 1; i <= no; i++) {
267 outb(*p++, SMBBLKDAT);
268 }
269 outb(0xff, SMBHSTSTART);
270
271 temp = inb(SMBHSTSTS);
272 for (timeout = 0; (timeout < MAX_TIMEOUT) && !(temp & (ALI15X3_STS_ERR | ALI15X3_STS_DONE)); timeout++) {
273 delay1000();
274 temp = inb(SMBHSTSTS);
275 }
276 if (timeout >= MAX_TIMEOUT) {
277 return -2;
278 }
279 if ( temp & ALI15X3_STS_ERR ){
280 return -3;
281 }
282 return 0;
283}
284
285static struct resource heartbeat_resources[] = {
286 [0] = {
287 .start = 0xa2000000,
288 .end = 0xa2000000,
289 .flags = IORESOURCE_MEM,
290 },
291};
292
293static struct platform_device heartbeat_device = {
294 .name = "heartbeat",
295 .id = -1,
296 .num_resources = ARRAY_SIZE(heartbeat_resources),
297 .resource = heartbeat_resources,
298};
299
300static struct platform_device *mpc1211_devices[] __initdata = {
301 &heartbeat_device,
302};
303
304static int __init mpc1211_devices_setup(void)
305{
306 return platform_add_devices(mpc1211_devices,
307 ARRAY_SIZE(mpc1211_devices));
308}
309__initcall(mpc1211_devices_setup);
310
311/* arch/sh/boards/mpc1211/rtc.c */
312void mpc1211_time_init(void);
313
314static void __init mpc1211_setup(char **cmdline_p)
315{
316 unsigned char spd_buf[128];
317
318 __set_io_port_base(PA_PCI_IO);
319
320 pci_write_config(0,0,0,0x54, 0xb0b00000);
321
322 do {
323 outb(ALI15X3_ABORT, SMBHSTCNT);
324 spd_buf[0] = 0x0c;
325 spd_buf[1] = 0x43;
326 spd_buf[2] = 0x7f;
327 spd_buf[3] = 0x03;
328 spd_buf[4] = 0x00;
329 spd_buf[5] = 0x03;
330 spd_buf[6] = 0x00;
331 } while (put_smb_blk(spd_buf, 0x69, 0, 7) < 0);
332
333 board_time_init = mpc1211_time_init;
334
335 return 0;
336}
337
338/*
339 * The Machine Vector
340 */
341static struct sh_machine_vector mv_mpc1211 __initmv = {
342 .mv_name = "Interface MPC-1211(CTP/PCI/MPC-SH02)",
343 .mv_setup = mpc1211_setup,
344 .mv_nr_irqs = 48,
345 .mv_irq_demux = mpc1211_irq_demux,
346 .mv_init_irq = init_mpc1211_IRQ,
347};
diff --git a/arch/sh/boards/renesas/migor/setup.c b/arch/sh/boards/renesas/migor/setup.c
index e7c150d49702..01af44245b57 100644
--- a/arch/sh/boards/renesas/migor/setup.c
+++ b/arch/sh/boards/renesas/migor/setup.c
@@ -14,6 +14,7 @@
14#include <linux/mtd/physmap.h> 14#include <linux/mtd/physmap.h>
15#include <linux/mtd/nand.h> 15#include <linux/mtd/nand.h>
16#include <linux/i2c.h> 16#include <linux/i2c.h>
17#include <linux/smc91x.h>
17#include <asm/machvec.h> 18#include <asm/machvec.h>
18#include <asm/io.h> 19#include <asm/io.h>
19#include <asm/sh_keysc.h> 20#include <asm/sh_keysc.h>
@@ -27,6 +28,11 @@
27 * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A) 28 * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
28 */ 29 */
29 30
31static struct smc91x_platdata smc91x_info = {
32 .flags = SMC91X_USE_16BIT,
33 .irq_flags = IRQF_TRIGGER_HIGH,
34};
35
30static struct resource smc91x_eth_resources[] = { 36static struct resource smc91x_eth_resources[] = {
31 [0] = { 37 [0] = {
32 .name = "SMC91C111" , 38 .name = "SMC91C111" ,
@@ -36,7 +42,7 @@ static struct resource smc91x_eth_resources[] = {
36 }, 42 },
37 [1] = { 43 [1] = {
38 .start = 32, /* IRQ0 */ 44 .start = 32, /* IRQ0 */
39 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH, 45 .flags = IORESOURCE_IRQ,
40 }, 46 },
41}; 47};
42 48
@@ -44,6 +50,9 @@ static struct platform_device smc91x_eth_device = {
44 .name = "smc91x", 50 .name = "smc91x",
45 .num_resources = ARRAY_SIZE(smc91x_eth_resources), 51 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
46 .resource = smc91x_eth_resources, 52 .resource = smc91x_eth_resources,
53 .dev = {
54 .platform_data = &smc91x_info,
55 },
47}; 56};
48 57
49static struct sh_keysc_info sh_keysc_info = { 58static struct sh_keysc_info sh_keysc_info = {
diff --git a/arch/sh/boards/renesas/r7780rp/irq-r7780mp.c b/arch/sh/boards/renesas/r7780rp/irq-r7780mp.c
index 68f0ad1b637d..ae1cfcb29700 100644
--- a/arch/sh/boards/renesas/r7780rp/irq-r7780mp.c
+++ b/arch/sh/boards/renesas/r7780rp/irq-r7780mp.c
@@ -62,7 +62,7 @@ static unsigned char irl2irq[HL_NR_IRL] __initdata = {
62static DECLARE_INTC_DESC(intc_desc, "r7780mp", vectors, 62static DECLARE_INTC_DESC(intc_desc, "r7780mp", vectors,
63 NULL, mask_registers, NULL, NULL); 63 NULL, mask_registers, NULL, NULL);
64 64
65unsigned char * __init highlander_init_irq_r7780mp(void) 65unsigned char * __init highlander_plat_irq_setup(void)
66{ 66{
67 if ((ctrl_inw(0xa4000700) & 0xf000) == 0x2000) { 67 if ((ctrl_inw(0xa4000700) & 0xf000) == 0x2000) {
68 printk(KERN_INFO "Using r7780mp interrupt controller.\n"); 68 printk(KERN_INFO "Using r7780mp interrupt controller.\n");
diff --git a/arch/sh/boards/renesas/r7780rp/irq-r7780rp.c b/arch/sh/boards/renesas/r7780rp/irq-r7780rp.c
index bd34048ed0e1..9d3921fe27c0 100644
--- a/arch/sh/boards/renesas/r7780rp/irq-r7780rp.c
+++ b/arch/sh/boards/renesas/r7780rp/irq-r7780rp.c
@@ -55,7 +55,7 @@ static unsigned char irl2irq[HL_NR_IRL] __initdata = {
55static DECLARE_INTC_DESC(intc_desc, "r7780rp", vectors, 55static DECLARE_INTC_DESC(intc_desc, "r7780rp", vectors,
56 NULL, mask_registers, NULL, NULL); 56 NULL, mask_registers, NULL, NULL);
57 57
58unsigned char * __init highlander_init_irq_r7780rp(void) 58unsigned char * __init highlander_plat_irq_setup(void)
59{ 59{
60 if (ctrl_inw(0xa5000600)) { 60 if (ctrl_inw(0xa5000600)) {
61 printk(KERN_INFO "Using r7780rp interrupt controller.\n"); 61 printk(KERN_INFO "Using r7780rp interrupt controller.\n");
diff --git a/arch/sh/boards/renesas/r7780rp/irq-r7785rp.c b/arch/sh/boards/renesas/r7780rp/irq-r7785rp.c
index bf7ec107fbc6..896c045aa39d 100644
--- a/arch/sh/boards/renesas/r7780rp/irq-r7785rp.c
+++ b/arch/sh/boards/renesas/r7780rp/irq-r7785rp.c
@@ -64,7 +64,7 @@ static unsigned char irl2irq[HL_NR_IRL] __initdata = {
64static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors, 64static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors,
65 NULL, mask_registers, NULL, NULL); 65 NULL, mask_registers, NULL, NULL);
66 66
67unsigned char * __init highlander_init_irq_r7785rp(void) 67unsigned char * __init highlander_plat_irq_setup(void)
68{ 68{
69 if ((ctrl_inw(0xa4000158) & 0xf000) != 0x1000) 69 if ((ctrl_inw(0xa4000158) & 0xf000) != 0x1000)
70 return NULL; 70 return NULL;
diff --git a/arch/sh/boards/renesas/r7780rp/setup.c b/arch/sh/boards/renesas/r7780rp/setup.c
index ac0a96522e45..bc79afb6fc4c 100644
--- a/arch/sh/boards/renesas/r7780rp/setup.c
+++ b/arch/sh/boards/renesas/r7780rp/setup.c
@@ -316,7 +316,7 @@ static void __init highlander_setup(char **cmdline_p)
316 316
317static unsigned char irl2irq[HL_NR_IRL]; 317static unsigned char irl2irq[HL_NR_IRL];
318 318
319int highlander_irq_demux(int irq) 319static int highlander_irq_demux(int irq)
320{ 320{
321 if (irq >= HL_NR_IRL || !irl2irq[irq]) 321 if (irq >= HL_NR_IRL || !irl2irq[irq])
322 return irq; 322 return irq;
@@ -324,27 +324,9 @@ int highlander_irq_demux(int irq)
324 return irl2irq[irq]; 324 return irl2irq[irq];
325} 325}
326 326
327void __init highlander_init_irq(void) 327static void __init highlander_init_irq(void)
328{ 328{
329 unsigned char *ucp = NULL; 329 unsigned char *ucp = highlander_plat_irq_setup();
330
331 do {
332#ifdef CONFIG_SH_R7780MP
333 ucp = highlander_init_irq_r7780mp();
334 if (ucp)
335 break;
336#endif
337#ifdef CONFIG_SH_R7785RP
338 ucp = highlander_init_irq_r7785rp();
339 if (ucp)
340 break;
341#endif
342#ifdef CONFIG_SH_R7780RP
343 ucp = highlander_init_irq_r7780rp();
344 if (ucp)
345 break;
346#endif
347 } while (0);
348 330
349 if (ucp) { 331 if (ucp) {
350 plat_irq_setup_pins(IRQ_MODE_IRL3210); 332 plat_irq_setup_pins(IRQ_MODE_IRL3210);
diff --git a/arch/sh/boards/renesas/rts7751r2d/setup.c b/arch/sh/boards/renesas/rts7751r2d/setup.c
index f21ee49ef3a5..452d0d6459a4 100644
--- a/arch/sh/boards/renesas/rts7751r2d/setup.c
+++ b/arch/sh/boards/renesas/rts7751r2d/setup.c
@@ -109,7 +109,6 @@ static struct platform_device heartbeat_device = {
109 .resource = heartbeat_resources, 109 .resource = heartbeat_resources,
110}; 110};
111 111
112#ifdef CONFIG_MFD_SM501
113static struct plat_serial8250_port uart_platform_data[] = { 112static struct plat_serial8250_port uart_platform_data[] = {
114 { 113 {
115 .membase = (void __iomem *)0xb3e30000, 114 .membase = (void __iomem *)0xb3e30000,
@@ -208,13 +207,9 @@ static struct platform_device sm501_device = {
208 .resource = sm501_resources, 207 .resource = sm501_resources,
209}; 208};
210 209
211#endif /* CONFIG_MFD_SM501 */
212
213static struct platform_device *rts7751r2d_devices[] __initdata = { 210static struct platform_device *rts7751r2d_devices[] __initdata = {
214#ifdef CONFIG_MFD_SM501
215 &uart_device, 211 &uart_device,
216 &sm501_device, 212 &sm501_device,
217#endif
218 &heartbeat_device, 213 &heartbeat_device,
219 &spi_sh_sci_device, 214 &spi_sh_sci_device,
220}; 215};
@@ -234,7 +229,9 @@ static int __init rts7751r2d_devices_setup(void)
234{ 229{
235 if (register_trapped_io(&cf_trapped_io) == 0) 230 if (register_trapped_io(&cf_trapped_io) == 0)
236 platform_device_register(&cf_ide_device); 231 platform_device_register(&cf_ide_device);
232
237 spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus)); 233 spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus));
234
238 return platform_add_devices(rts7751r2d_devices, 235 return platform_add_devices(rts7751r2d_devices,
239 ARRAY_SIZE(rts7751r2d_devices)); 236 ARRAY_SIZE(rts7751r2d_devices));
240} 237}
diff --git a/arch/sh/boards/se/7206/setup.c b/arch/sh/boards/se/7206/setup.c
index 5b3ee089d91d..4fe84cc08406 100644
--- a/arch/sh/boards/se/7206/setup.c
+++ b/arch/sh/boards/se/7206/setup.c
@@ -3,12 +3,13 @@
3 * linux/arch/sh/boards/se/7206/setup.c 3 * linux/arch/sh/boards/se/7206/setup.c
4 * 4 *
5 * Copyright (C) 2006 Yoshinori Sato 5 * Copyright (C) 2006 Yoshinori Sato
6 * Copyright (C) 2007 Paul Mundt 6 * Copyright (C) 2007 - 2008 Paul Mundt
7 * 7 *
8 * Hitachi 7206 SolutionEngine Support. 8 * Hitachi 7206 SolutionEngine Support.
9 */ 9 */
10#include <linux/init.h> 10#include <linux/init.h>
11#include <linux/platform_device.h> 11#include <linux/platform_device.h>
12#include <linux/smc91x.h>
12#include <asm/se7206.h> 13#include <asm/se7206.h>
13#include <asm/io.h> 14#include <asm/io.h>
14#include <asm/machvec.h> 15#include <asm/machvec.h>
@@ -16,8 +17,9 @@
16 17
17static struct resource smc91x_resources[] = { 18static struct resource smc91x_resources[] = {
18 [0] = { 19 [0] = {
19 .start = 0x300, 20 .name = "smc91x-regs",
20 .end = 0x300 + 0x020 - 1, 21 .start = PA_SMSC + 0x300,
22 .end = PA_SMSC + 0x300 + 0x020 - 1,
21 .flags = IORESOURCE_MEM, 23 .flags = IORESOURCE_MEM,
22 }, 24 },
23 [1] = { 25 [1] = {
@@ -27,9 +29,18 @@ static struct resource smc91x_resources[] = {
27 }, 29 },
28}; 30};
29 31
32static struct smc91x_platdata smc91x_info = {
33 .flags = SMC91X_USE_16BIT,
34};
35
30static struct platform_device smc91x_device = { 36static struct platform_device smc91x_device = {
31 .name = "smc91x", 37 .name = "smc91x",
32 .id = -1, 38 .id = -1,
39 .dev = {
40 .dma_mask = NULL,
41 .coherent_dma_mask = 0xffffffff,
42 .platform_data = &smc91x_info,
43 },
33 .num_resources = ARRAY_SIZE(smc91x_resources), 44 .num_resources = ARRAY_SIZE(smc91x_resources),
34 .resource = smc91x_resources, 45 .resource = smc91x_resources,
35}; 46};
diff --git a/arch/sh/boards/se/7722/setup.c b/arch/sh/boards/se/7722/setup.c
index 33f6ee71f848..ede3957fc14a 100644
--- a/arch/sh/boards/se/7722/setup.c
+++ b/arch/sh/boards/se/7722/setup.c
@@ -14,6 +14,7 @@
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/ata_platform.h> 15#include <linux/ata_platform.h>
16#include <linux/input.h> 16#include <linux/input.h>
17#include <linux/smc91x.h>
17#include <asm/machvec.h> 18#include <asm/machvec.h>
18#include <asm/se7722.h> 19#include <asm/se7722.h>
19#include <asm/io.h> 20#include <asm/io.h>
@@ -44,6 +45,10 @@ static struct platform_device heartbeat_device = {
44}; 45};
45 46
46/* SMC91x */ 47/* SMC91x */
48static struct smc91x_platdata smc91x_info = {
49 .flags = SMC91X_USE_16BIT,
50};
51
47static struct resource smc91x_eth_resources[] = { 52static struct resource smc91x_eth_resources[] = {
48 [0] = { 53 [0] = {
49 .name = "smc91x-regs" , 54 .name = "smc91x-regs" ,
@@ -64,6 +69,7 @@ static struct platform_device smc91x_eth_device = {
64 .dev = { 69 .dev = {
65 .dma_mask = NULL, /* don't use dma */ 70 .dma_mask = NULL, /* don't use dma */
66 .coherent_dma_mask = 0xffffffff, 71 .coherent_dma_mask = 0xffffffff,
72 .platform_data = &smc91x_info,
67 }, 73 },
68 .num_resources = ARRAY_SIZE(smc91x_eth_resources), 74 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
69 .resource = smc91x_eth_resources, 75 .resource = smc91x_eth_resources,
diff --git a/arch/sh/boot/compressed/Makefile_32 b/arch/sh/boot/compressed/Makefile_32
index 6ac8d4a4ed1d..c0d25fb1aa60 100644
--- a/arch/sh/boot/compressed/Makefile_32
+++ b/arch/sh/boot/compressed/Makefile_32
@@ -6,7 +6,6 @@
6 6
7targets := vmlinux vmlinux.bin vmlinux.bin.gz \ 7targets := vmlinux vmlinux.bin vmlinux.bin.gz \
8 head_32.o misc_32.o piggy.o 8 head_32.o misc_32.o piggy.o
9EXTRA_AFLAGS := -traditional
10 9
11OBJECTS = $(obj)/head_32.o $(obj)/misc_32.o 10OBJECTS = $(obj)/head_32.o $(obj)/misc_32.o
12 11
diff --git a/arch/sh/boot/compressed/Makefile_64 b/arch/sh/boot/compressed/Makefile_64
index 4334f2b86d8f..912f3e205a0d 100644
--- a/arch/sh/boot/compressed/Makefile_64
+++ b/arch/sh/boot/compressed/Makefile_64
@@ -13,7 +13,6 @@
13 13
14targets := vmlinux vmlinux.bin vmlinux.bin.gz \ 14targets := vmlinux vmlinux.bin vmlinux.bin.gz \
15 head_64.o misc_64.o cache.o piggy.o 15 head_64.o misc_64.o cache.o piggy.o
16EXTRA_AFLAGS := -traditional
17 16
18OBJECTS := $(obj)/vmlinux_64.lds $(obj)/head_64.o $(obj)/misc_64.o \ 17OBJECTS := $(obj)/vmlinux_64.lds $(obj)/head_64.o $(obj)/misc_64.o \
19 $(obj)/cache.o 18 $(obj)/cache.o
diff --git a/arch/sh/kernel/cpu/irq/intc-sh5.c b/arch/sh/kernel/cpu/irq/intc-sh5.c
index d6e0e2bdaad5..de45c6a3e33b 100644
--- a/arch/sh/kernel/cpu/irq/intc-sh5.c
+++ b/arch/sh/kernel/cpu/irq/intc-sh5.c
@@ -184,9 +184,8 @@ int intc_irq_describe(char* p, int irq)
184 184
185void __init plat_irq_setup(void) 185void __init plat_irq_setup(void)
186{ 186{
187 unsigned long long __dummy0, __dummy1=~0x00000000100000f0; 187 unsigned long long __dummy0, __dummy1=~0x00000000100000f0;
188 unsigned long reg; 188 unsigned long reg;
189 unsigned long data;
190 int i; 189 int i;
191 190
192 intc_virt = onchip_remap(INTC_BASE, 1024, "INTC"); 191 intc_virt = onchip_remap(INTC_BASE, 1024, "INTC");
@@ -196,11 +195,8 @@ void __init plat_irq_setup(void)
196 195
197 196
198 /* Set default: per-line enable/disable, priority driven ack/eoi */ 197 /* Set default: per-line enable/disable, priority driven ack/eoi */
199 for (i = 0; i < NR_INTC_IRQS; i++) { 198 for (i = 0; i < NR_INTC_IRQS; i++)
200 if (platform_int_priority[i] != NO_PRIORITY) { 199 irq_desc[i].chip = &intc_irq_type;
201 irq_desc[i].chip = &intc_irq_type;
202 }
203 }
204 200
205 201
206 /* Disable all interrupts and set all priorities to 0 to avoid trouble */ 202 /* Disable all interrupts and set all priorities to 0 to avoid trouble */
@@ -211,35 +207,42 @@ void __init plat_irq_setup(void)
211 ctrl_outl( NO_PRIORITY, reg); 207 ctrl_outl( NO_PRIORITY, reg);
212 208
213 209
214 /* Set IRLM */ 210#ifdef CONFIG_SH_CAYMAN
215 /* If all the priorities are set to 'no priority', then 211 {
216 * assume we are using encoded mode. 212 unsigned long data;
217 */ 213
218 irlm = platform_int_priority[IRQ_IRL0] + platform_int_priority[IRQ_IRL1] + \ 214 /* Set IRLM */
219 platform_int_priority[IRQ_IRL2] + platform_int_priority[IRQ_IRL3]; 215 /* If all the priorities are set to 'no priority', then
220 216 * assume we are using encoded mode.
221 if (irlm == NO_PRIORITY) { 217 */
222 /* IRLM = 0 */ 218 irlm = platform_int_priority[IRQ_IRL0] +
223 reg = INTC_ICR_CLEAR; 219 platform_int_priority[IRQ_IRL1] +
224 i = IRQ_INTA; 220 platform_int_priority[IRQ_IRL2] +
225 printk("Trying to use encoded IRL0-3. IRLs unsupported.\n"); 221 platform_int_priority[IRQ_IRL3];
226 } else { 222 if (irlm == NO_PRIORITY) {
227 /* IRLM = 1 */ 223 /* IRLM = 0 */
228 reg = INTC_ICR_SET; 224 reg = INTC_ICR_CLEAR;
229 i = IRQ_IRL0; 225 i = IRQ_INTA;
230 } 226 printk("Trying to use encoded IRL0-3. IRLs unsupported.\n");
231 ctrl_outl(INTC_ICR_IRLM, reg); 227 } else {
232 228 /* IRLM = 1 */
233 /* Set interrupt priorities according to platform description */ 229 reg = INTC_ICR_SET;
234 for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) { 230 i = IRQ_IRL0;
235 data |= platform_int_priority[i] << ((i % INTC_INTPRI_PPREG) * 4);
236 if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) {
237 /* Upon the 7th, set Priority Register */
238 ctrl_outl(data, reg);
239 data = 0;
240 reg += 8;
241 } 231 }
242 } 232 ctrl_outl(INTC_ICR_IRLM, reg);
233
234 /* Set interrupt priorities according to platform description */
235 for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) {
236 data |= platform_int_priority[i] <<
237 ((i % INTC_INTPRI_PPREG) * 4);
238 if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) {
239 /* Upon the 7th, set Priority Register */
240 ctrl_outl(data, reg);
241 data = 0;
242 reg += 8;
243 }
244 }
245#endif
243 246
244 /* 247 /*
245 * And now let interrupts come in. 248 * And now let interrupts come in.
diff --git a/arch/sh/kernel/cpu/irq/intc.c b/arch/sh/kernel/cpu/irq/intc.c
index 84806b2027f8..da5dae787888 100644
--- a/arch/sh/kernel/cpu/irq/intc.c
+++ b/arch/sh/kernel/cpu/irq/intc.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs. 2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 * 3 *
4 * Copyright (C) 2007 Magnus Damm 4 * Copyright (C) 2007, 2008 Magnus Damm
5 * 5 *
6 * Based on intc2.c and ipr.c 6 * Based on intc2.c and ipr.c
7 * 7 *
@@ -62,6 +62,9 @@ struct intc_desc_int {
62#endif 62#endif
63 63
64static unsigned int intc_prio_level[NR_IRQS]; /* for now */ 64static unsigned int intc_prio_level[NR_IRQS]; /* for now */
65#ifdef CONFIG_CPU_SH3
66static unsigned long ack_handle[NR_IRQS];
67#endif
65 68
66static inline struct intc_desc_int *get_intc_desc(unsigned int irq) 69static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
67{ 70{
@@ -98,17 +101,26 @@ static void write_32(unsigned long addr, unsigned long h, unsigned long data)
98 101
99static void modify_8(unsigned long addr, unsigned long h, unsigned long data) 102static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
100{ 103{
104 unsigned long flags;
105 local_irq_save(flags);
101 ctrl_outb(set_field(ctrl_inb(addr), data, h), addr); 106 ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
107 local_irq_restore(flags);
102} 108}
103 109
104static void modify_16(unsigned long addr, unsigned long h, unsigned long data) 110static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
105{ 111{
112 unsigned long flags;
113 local_irq_save(flags);
106 ctrl_outw(set_field(ctrl_inw(addr), data, h), addr); 114 ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
115 local_irq_restore(flags);
107} 116}
108 117
109static void modify_32(unsigned long addr, unsigned long h, unsigned long data) 118static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
110{ 119{
120 unsigned long flags;
121 local_irq_save(flags);
111 ctrl_outl(set_field(ctrl_inl(addr), data, h), addr); 122 ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
123 local_irq_restore(flags);
112} 124}
113 125
114enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 }; 126enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
@@ -219,6 +231,25 @@ static void intc_disable(unsigned int irq)
219 } 231 }
220} 232}
221 233
234#ifdef CONFIG_CPU_SH3
235static void intc_mask_ack(unsigned int irq)
236{
237 struct intc_desc_int *d = get_intc_desc(irq);
238 unsigned long handle = ack_handle[irq];
239 unsigned long addr;
240
241 intc_disable(irq);
242
243 /* read register and write zero only to the assocaited bit */
244
245 if (handle) {
246 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
247 ctrl_inb(addr);
248 ctrl_outb(0x3f ^ set_field(0, 1, handle), addr);
249 }
250}
251#endif
252
222static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp, 253static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
223 unsigned int nr_hp, 254 unsigned int nr_hp,
224 unsigned int irq) 255 unsigned int irq)
@@ -280,7 +311,12 @@ static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
280 [IRQ_TYPE_EDGE_FALLING] = VALID(0), 311 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
281 [IRQ_TYPE_EDGE_RISING] = VALID(1), 312 [IRQ_TYPE_EDGE_RISING] = VALID(1),
282 [IRQ_TYPE_LEVEL_LOW] = VALID(2), 313 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
314 /* SH7706, SH7707 and SH7709 do not support high level triggered */
315#if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
316 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
317 !defined(CONFIG_CPU_SUBTYPE_SH7709)
283 [IRQ_TYPE_LEVEL_HIGH] = VALID(3), 318 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
319#endif
284}; 320};
285 321
286static int intc_set_sense(unsigned int irq, unsigned int type) 322static int intc_set_sense(unsigned int irq, unsigned int type)
@@ -430,6 +466,40 @@ static unsigned int __init intc_prio_data(struct intc_desc *desc,
430 return 0; 466 return 0;
431} 467}
432 468
469#ifdef CONFIG_CPU_SH3
470static unsigned int __init intc_ack_data(struct intc_desc *desc,
471 struct intc_desc_int *d,
472 intc_enum enum_id)
473{
474 struct intc_mask_reg *mr = desc->ack_regs;
475 unsigned int i, j, fn, mode;
476 unsigned long reg_e, reg_d;
477
478 for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
479 mr = desc->ack_regs + i;
480
481 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
482 if (mr->enum_ids[j] != enum_id)
483 continue;
484
485 fn = REG_FN_MODIFY_BASE;
486 mode = MODE_ENABLE_REG;
487 reg_e = mr->set_reg;
488 reg_d = mr->set_reg;
489
490 fn += (mr->reg_width >> 3) - 1;
491 return _INTC_MK(fn, mode,
492 intc_get_reg(d, reg_e),
493 intc_get_reg(d, reg_d),
494 1,
495 (mr->reg_width - 1) - j);
496 }
497 }
498
499 return 0;
500}
501#endif
502
433static unsigned int __init intc_sense_data(struct intc_desc *desc, 503static unsigned int __init intc_sense_data(struct intc_desc *desc,
434 struct intc_desc_int *d, 504 struct intc_desc_int *d,
435 intc_enum enum_id) 505 intc_enum enum_id)
@@ -530,6 +600,11 @@ static void __init intc_register_irq(struct intc_desc *desc,
530 600
531 /* irq should be disabled by default */ 601 /* irq should be disabled by default */
532 d->chip.mask(irq); 602 d->chip.mask(irq);
603
604#ifdef CONFIG_CPU_SH3
605 if (desc->ack_regs)
606 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
607#endif
533} 608}
534 609
535static unsigned int __init save_reg(struct intc_desc_int *d, 610static unsigned int __init save_reg(struct intc_desc_int *d,
@@ -560,6 +635,9 @@ void __init register_intc_controller(struct intc_desc *desc)
560 d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0; 635 d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
561 d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0; 636 d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
562 637
638#ifdef CONFIG_CPU_SH3
639 d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
640#endif
563 d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg)); 641 d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
564#ifdef CONFIG_SMP 642#ifdef CONFIG_SMP
565 d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp)); 643 d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp));
@@ -592,14 +670,23 @@ void __init register_intc_controller(struct intc_desc *desc)
592 } 670 }
593 } 671 }
594 672
595 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
596
597 d->chip.name = desc->name; 673 d->chip.name = desc->name;
598 d->chip.mask = intc_disable; 674 d->chip.mask = intc_disable;
599 d->chip.unmask = intc_enable; 675 d->chip.unmask = intc_enable;
600 d->chip.mask_ack = intc_disable; 676 d->chip.mask_ack = intc_disable;
601 d->chip.set_type = intc_set_sense; 677 d->chip.set_type = intc_set_sense;
602 678
679#ifdef CONFIG_CPU_SH3
680 if (desc->ack_regs) {
681 for (i = 0; i < desc->nr_ack_regs; i++)
682 k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
683
684 d->chip.mask_ack = intc_mask_ack;
685 }
686#endif
687
688 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
689
603 for (i = 0; i < desc->nr_vectors; i++) { 690 for (i = 0; i < desc->nr_vectors; i++) {
604 struct intc_vect *vect = desc->vectors + i; 691 struct intc_vect *vect = desc->vectors + i;
605 692
diff --git a/arch/sh/kernel/cpu/sh2a/fpu.c b/arch/sh/kernel/cpu/sh2a/fpu.c
index 5627c0b3ffa8..6df2fb98eb30 100644
--- a/arch/sh/kernel/cpu/sh2a/fpu.c
+++ b/arch/sh/kernel/cpu/sh2a/fpu.c
@@ -300,7 +300,7 @@ static int denormal_addf(int hx, int hy)
300 iy = hy & 0x7fffffff; 300 iy = hy & 0x7fffffff;
301 if (iy < 0x00800000) { 301 if (iy < 0x00800000) {
302 ix = denormal_subf1(ix, iy); 302 ix = denormal_subf1(ix, iy);
303 if (ix < 0) { 303 if ((int) ix < 0) {
304 ix = -ix; 304 ix = -ix;
305 sign ^= 0x80000000; 305 sign ^= 0x80000000;
306 } 306 }
@@ -385,7 +385,7 @@ static long long denormal_addd(long long hx, long long hy)
385 iy = hy & 0x7fffffffffffffffLL; 385 iy = hy & 0x7fffffffffffffffLL;
386 if (iy < 0x0010000000000000LL) { 386 if (iy < 0x0010000000000000LL) {
387 ix = denormal_subd1(ix, iy); 387 ix = denormal_subd1(ix, iy);
388 if (ix < 0) { 388 if ((int) ix < 0) {
389 ix = -ix; 389 ix = -ix;
390 sign ^= 0x8000000000000000LL; 390 sign ^= 0x8000000000000000LL;
391 } 391 }
diff --git a/arch/sh/kernel/cpu/sh3/Makefile b/arch/sh/kernel/cpu/sh3/Makefile
index 3ae4d9111f19..511de55af832 100644
--- a/arch/sh/kernel/cpu/sh3/Makefile
+++ b/arch/sh/kernel/cpu/sh3/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the Linux/SuperH SH-3 backends. 2# Makefile for the Linux/SuperH SH-3 backends.
3# 3#
4 4
5obj-y := ex.o probe.o entry.o 5obj-y := ex.o probe.o entry.o setup-sh3.o
6 6
7# CPU subtype setup 7# CPU subtype setup
8obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o 8obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh3.c b/arch/sh/kernel/cpu/sh3/setup-sh3.c
new file mode 100644
index 000000000000..c98846857855
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/setup-sh3.c
@@ -0,0 +1,71 @@
1/*
2 * Shared SH3 Setup code
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/init.h>
12#include <linux/irq.h>
13#include <linux/io.h>
14
15/* All SH3 devices are equipped with IRQ0->5 (except sh7708) */
16
17enum {
18 UNUSED = 0,
19
20 /* interrupt sources */
21 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
22};
23
24static struct intc_vect vectors_irq0123[] __initdata = {
25 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
26 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
27};
28
29static struct intc_vect vectors_irq45[] __initdata = {
30 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
31};
32
33static struct intc_prio_reg prio_registers[] __initdata = {
34 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
35 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
36};
37
38static struct intc_mask_reg ack_registers[] __initdata = {
39 { 0xa4000004, 0, 8, /* IRR0 */
40 { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
41};
42
43static struct intc_sense_reg sense_registers[] __initdata = {
44 { 0xa4000010, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
45};
46
47static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh3-irq0123",
48 vectors_irq0123, NULL, NULL,
49 prio_registers, sense_registers, ack_registers);
50
51static DECLARE_INTC_DESC_ACK(intc_desc_irq45, "sh3-irq45",
52 vectors_irq45, NULL, NULL,
53 prio_registers, sense_registers, ack_registers);
54
55#define INTC_ICR1 0xa4000010UL
56#define INTC_ICR1_IRQLVL (1<<14)
57
58void __init plat_irq_setup_pins(int mode)
59{
60 if (mode == IRQ_MODE_IRQ) {
61 ctrl_outw(ctrl_inw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1);
62 register_intc_controller(&intc_desc_irq0123);
63 return;
64 }
65 BUG();
66}
67
68void __init plat_irq_setup_sh3(void)
69{
70 register_intc_controller(&intc_desc_irq45);
71}
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index f581534cb732..6468ae86b944 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -37,7 +37,7 @@ enum {
37}; 37};
38 38
39static struct intc_vect vectors[] __initdata = { 39static struct intc_vect vectors[] __initdata = {
40 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 40 /* IRQ0->5 are handled in setup-sh3.c */
41 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), 41 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
42 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), 42 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
43 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), 43 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
@@ -48,7 +48,7 @@ static struct intc_vect vectors[] __initdata = {
48 INTC_VECT(ADC_ADI, 0x980), 48 INTC_VECT(ADC_ADI, 0x980),
49 INTC_VECT(USB_USI0, 0xa20), INTC_VECT(USB_USI1, 0xa40), 49 INTC_VECT(USB_USI0, 0xa20), INTC_VECT(USB_USI1, 0xa40),
50 INTC_VECT(TPU0, 0xc00), INTC_VECT(TPU1, 0xc20), 50 INTC_VECT(TPU0, 0xc00), INTC_VECT(TPU1, 0xc20),
51 INTC_VECT(TPU3, 0xc80), INTC_VECT(TPU1, 0xca0), 51 INTC_VECT(TPU2, 0xc80), INTC_VECT(TPU3, 0xca0),
52 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 52 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
53 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 53 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
54 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 54 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
@@ -81,14 +81,6 @@ static struct intc_prio_reg prio_registers[] __initdata = {
81static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, groups, 81static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, groups,
82 NULL, prio_registers, NULL); 82 NULL, prio_registers, NULL);
83 83
84static struct intc_vect vectors_irq[] __initdata = {
85 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
86 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
87};
88
89static DECLARE_INTC_DESC(intc_desc_irq, "sh7705-irq", vectors_irq, NULL,
90 NULL, prio_registers, NULL);
91
92static struct plat_sci_port sci_platform_data[] = { 84static struct plat_sci_port sci_platform_data[] = {
93 { 85 {
94 .mapbase = 0xa4410000, 86 .mapbase = 0xa4410000,
@@ -159,16 +151,8 @@ static int __init sh7705_devices_setup(void)
159} 151}
160__initcall(sh7705_devices_setup); 152__initcall(sh7705_devices_setup);
161 153
162void __init plat_irq_setup_pins(int mode)
163{
164 if (mode == IRQ_MODE_IRQ) {
165 register_intc_controller(&intc_desc_irq);
166 return;
167 }
168 BUG();
169}
170
171void __init plat_irq_setup(void) 154void __init plat_irq_setup(void)
172{ 155{
173 register_intc_controller(&intc_desc); 156 register_intc_controller(&intc_desc);
157 plat_irq_setup_sh3();
174} 158}
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index d3733b13ea52..93c55e2ed952 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -52,7 +52,7 @@ static struct intc_vect vectors[] __initdata = {
52#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 52#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
53 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 53 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
54 defined(CONFIG_CPU_SUBTYPE_SH7709) 54 defined(CONFIG_CPU_SUBTYPE_SH7709)
55 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 55 /* IRQ0->5 are handled in setup-sh3.c */
56 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), 56 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
57 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), 57 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
58 INTC_VECT(ADC_ADI, 0x980), 58 INTC_VECT(ADC_ADI, 0x980),
@@ -104,18 +104,6 @@ static struct intc_prio_reg prio_registers[] __initdata = {
104static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, groups, 104static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, groups,
105 NULL, prio_registers, NULL); 105 NULL, prio_registers, NULL);
106 106
107#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
108 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
109 defined(CONFIG_CPU_SUBTYPE_SH7709)
110static struct intc_vect vectors_irq[] __initdata = {
111 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
112 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
113};
114
115static DECLARE_INTC_DESC(intc_desc_irq, "sh770x-irq", vectors_irq, NULL,
116 NULL, prio_registers, NULL);
117#endif
118
119static struct resource rtc_resources[] = { 107static struct resource rtc_resources[] = {
120 [0] = { 108 [0] = {
121 .start = 0xfffffec0, 109 .start = 0xfffffec0,
@@ -194,24 +182,12 @@ static int __init sh770x_devices_setup(void)
194} 182}
195__initcall(sh770x_devices_setup); 183__initcall(sh770x_devices_setup);
196 184
197#define INTC_ICR1 0xa4000010UL 185void __init plat_irq_setup(void)
198#define INTC_ICR1_IRQLVL (1<<14)
199
200void __init plat_irq_setup_pins(int mode)
201{ 186{
202 if (mode == IRQ_MODE_IRQ) { 187 register_intc_controller(&intc_desc);
203#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 188#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
204 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 189 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
205 defined(CONFIG_CPU_SUBTYPE_SH7709) 190 defined(CONFIG_CPU_SUBTYPE_SH7709)
206 ctrl_outw(ctrl_inw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1); 191 plat_irq_setup_sh3();
207 register_intc_controller(&intc_desc_irq);
208 return;
209#endif 192#endif
210 }
211 BUG();
212}
213
214void __init plat_irq_setup(void)
215{
216 register_intc_controller(&intc_desc);
217} 193}
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 7406c9ad9259..77eee481de47 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -38,7 +38,7 @@ enum {
38}; 38};
39 39
40static struct intc_vect vectors[] __initdata = { 40static struct intc_vect vectors[] __initdata = {
41 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 41 /* IRQ0->5 are handled in setup-sh3.c */
42 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), 42 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
43 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), 43 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
44 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0), 44 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
@@ -79,10 +79,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
79 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 79 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
80 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, 80 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
81 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } }, 81 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
82 { 0xa4080000, 0, 16, 4, /* IPRF */ { 0, DMAC2 } }, 82 { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC, DMAC2 } },
83#ifdef CONFIG_CPU_SUBTYPE_SH7710
84 { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC } },
85#endif
86 { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } }, 83 { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },
87 { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } }, 84 { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },
88 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } }, 85 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
@@ -91,14 +88,6 @@ static struct intc_prio_reg prio_registers[] __initdata = {
91static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups, 88static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups,
92 NULL, prio_registers, NULL); 89 NULL, prio_registers, NULL);
93 90
94static struct intc_vect vectors_irq[] __initdata = {
95 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
96 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
97};
98
99static DECLARE_INTC_DESC(intc_desc_irq, "sh7710-irq", vectors_irq, NULL,
100 NULL, prio_registers, NULL);
101
102static struct resource rtc_resources[] = { 91static struct resource rtc_resources[] = {
103 [0] = { 92 [0] = {
104 .start = 0xa413fec0, 93 .start = 0xa413fec0,
@@ -170,16 +159,8 @@ static int __init sh7710_devices_setup(void)
170} 159}
171__initcall(sh7710_devices_setup); 160__initcall(sh7710_devices_setup);
172 161
173void __init plat_irq_setup_pins(int mode)
174{
175 if (mode == IRQ_MODE_IRQ) {
176 register_intc_controller(&intc_desc_irq);
177 return;
178 }
179 BUG();
180}
181
182void __init plat_irq_setup(void) 162void __init plat_irq_setup(void)
183{ 163{
184 register_intc_controller(&intc_desc); 164 register_intc_controller(&intc_desc);
165 plat_irq_setup_sh3();
185} 166}
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 8028082527c5..f807a21b066c 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -19,10 +19,6 @@
19#include <linux/serial_sci.h> 19#include <linux/serial_sci.h>
20#include <asm/rtc.h> 20#include <asm/rtc.h>
21 21
22#define INTC_ICR1 0xA4140010UL
23#define INTC_ICR_IRLM 0x4000
24#define INTC_ICR_IRQ (~INTC_ICR_IRLM)
25
26static struct resource rtc_resources[] = { 22static struct resource rtc_resources[] = {
27 [0] = { 23 [0] = {
28 .start = 0xa413fec0, 24 .start = 0xa413fec0,
@@ -170,6 +166,7 @@ enum {
170}; 166};
171 167
172static struct intc_vect vectors[] __initdata = { 168static struct intc_vect vectors[] __initdata = {
169 /* IRQ0->5 are handled in setup-sh3.c */
173 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 170 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
174 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC_ATI, 0x480), 171 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC_ATI, 0x480),
175 INTC_VECT(RTC_PRI, 0x4a0), INTC_VECT(RTC_CUI, 0x4c0), 172 INTC_VECT(RTC_PRI, 0x4a0), INTC_VECT(RTC_CUI, 0x4c0),
@@ -214,11 +211,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
214 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, 211 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
215 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 212 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
216 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } }, 213 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
217#if defined(CONFIG_CPU_SUBTYPE_SH7720)
218 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } }, 214 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
219#else
220 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, 0 } },
221#endif
222 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } }, 215 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
223 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } }, 216 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
224 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } }, 217 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
@@ -229,32 +222,8 @@ static struct intc_prio_reg prio_registers[] __initdata = {
229static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, groups, 222static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, groups,
230 NULL, prio_registers, NULL); 223 NULL, prio_registers, NULL);
231 224
232static struct intc_sense_reg sense_registers[] __initdata = {
233 { INTC_ICR1, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
234};
235
236static struct intc_vect vectors_irq[] __initdata = {
237 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
238 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
239 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
240};
241
242static DECLARE_INTC_DESC(intc_irq_desc, "sh7720-irq", vectors_irq,
243 NULL, NULL, prio_registers, sense_registers);
244
245void __init plat_irq_setup_pins(int mode)
246{
247 switch (mode) {
248 case IRQ_MODE_IRQ:
249 ctrl_outw(ctrl_inw(INTC_ICR1) & INTC_ICR_IRQ, INTC_ICR1);
250 register_intc_controller(&intc_irq_desc);
251 break;
252 default:
253 BUG();
254 }
255}
256
257void __init plat_irq_setup(void) 225void __init plat_irq_setup(void)
258{ 226{
259 register_intc_controller(&intc_desc); 227 register_intc_controller(&intc_desc);
228 plat_irq_setup_sh3();
260} 229}
diff --git a/arch/sh/kernel/cpu/sh5/entry.S b/arch/sh/kernel/cpu/sh5/entry.S
index ba8750176d91..05372ed6c568 100644
--- a/arch/sh/kernel/cpu/sh5/entry.S
+++ b/arch/sh/kernel/cpu/sh5/entry.S
@@ -143,12 +143,22 @@ resvec_save_area:
143trap_jtable: 143trap_jtable:
144 .long do_exception_error /* 0x000 */ 144 .long do_exception_error /* 0x000 */
145 .long do_exception_error /* 0x020 */ 145 .long do_exception_error /* 0x020 */
146#ifdef CONFIG_MMU
146 .long tlb_miss_load /* 0x040 */ 147 .long tlb_miss_load /* 0x040 */
147 .long tlb_miss_store /* 0x060 */ 148 .long tlb_miss_store /* 0x060 */
149#else
150 .long do_exception_error
151 .long do_exception_error
152#endif
148 ! ARTIFICIAL pseudo-EXPEVT setting 153 ! ARTIFICIAL pseudo-EXPEVT setting
149 .long do_debug_interrupt /* 0x080 */ 154 .long do_debug_interrupt /* 0x080 */
155#ifdef CONFIG_MMU
150 .long tlb_miss_load /* 0x0A0 */ 156 .long tlb_miss_load /* 0x0A0 */
151 .long tlb_miss_store /* 0x0C0 */ 157 .long tlb_miss_store /* 0x0C0 */
158#else
159 .long do_exception_error
160 .long do_exception_error
161#endif
152 .long do_address_error_load /* 0x0E0 */ 162 .long do_address_error_load /* 0x0E0 */
153 .long do_address_error_store /* 0x100 */ 163 .long do_address_error_store /* 0x100 */
154#ifdef CONFIG_SH_FPU 164#ifdef CONFIG_SH_FPU
@@ -185,10 +195,18 @@ trap_jtable:
185 .endr 195 .endr
186 .long do_IRQ /* 0xA00 */ 196 .long do_IRQ /* 0xA00 */
187 .long do_IRQ /* 0xA20 */ 197 .long do_IRQ /* 0xA20 */
198#ifdef CONFIG_MMU
188 .long itlb_miss_or_IRQ /* 0xA40 */ 199 .long itlb_miss_or_IRQ /* 0xA40 */
200#else
201 .long do_IRQ
202#endif
189 .long do_IRQ /* 0xA60 */ 203 .long do_IRQ /* 0xA60 */
190 .long do_IRQ /* 0xA80 */ 204 .long do_IRQ /* 0xA80 */
205#ifdef CONFIG_MMU
191 .long itlb_miss_or_IRQ /* 0xAA0 */ 206 .long itlb_miss_or_IRQ /* 0xAA0 */
207#else
208 .long do_IRQ
209#endif
192 .long do_exception_error /* 0xAC0 */ 210 .long do_exception_error /* 0xAC0 */
193 .long do_address_error_exec /* 0xAE0 */ 211 .long do_address_error_exec /* 0xAE0 */
194 .rept 8 212 .rept 8
@@ -274,6 +292,7 @@ not_a_tlb_miss:
274 * Instead of '.space 1024-TEXT_SIZE' place the RESVEC 292 * Instead of '.space 1024-TEXT_SIZE' place the RESVEC
275 * block making sure the final alignment is correct. 293 * block making sure the final alignment is correct.
276 */ 294 */
295#ifdef CONFIG_MMU
277tlb_miss: 296tlb_miss:
278 synco /* TAKum03020 (but probably a good idea anyway.) */ 297 synco /* TAKum03020 (but probably a good idea anyway.) */
279 putcon SP, KCR1 298 putcon SP, KCR1
@@ -377,6 +396,9 @@ fixup_to_invoke_general_handler:
377 getcon KCR1, SP 396 getcon KCR1, SP
378 pta handle_exception, tr0 397 pta handle_exception, tr0
379 blink tr0, ZERO 398 blink tr0, ZERO
399#else /* CONFIG_MMU */
400 .balign 256
401#endif
380 402
381/* NB TAKE GREAT CARE HERE TO ENSURE THAT THE INTERRUPT CODE 403/* NB TAKE GREAT CARE HERE TO ENSURE THAT THE INTERRUPT CODE
382 DOES END UP AT VBR+0x600 */ 404 DOES END UP AT VBR+0x600 */
@@ -1103,6 +1125,7 @@ restore_all:
1103 * fpu_error_or_IRQ? is a helper to deflect to the right cause. 1125 * fpu_error_or_IRQ? is a helper to deflect to the right cause.
1104 * 1126 *
1105 */ 1127 */
1128#ifdef CONFIG_MMU
1106tlb_miss_load: 1129tlb_miss_load:
1107 or SP, ZERO, r2 1130 or SP, ZERO, r2
1108 or ZERO, ZERO, r3 /* Read */ 1131 or ZERO, ZERO, r3 /* Read */
@@ -1132,6 +1155,7 @@ call_do_page_fault:
1132 movi do_page_fault, r6 1155 movi do_page_fault, r6
1133 ptabs r6, tr0 1156 ptabs r6, tr0
1134 blink tr0, ZERO 1157 blink tr0, ZERO
1158#endif /* CONFIG_MMU */
1135 1159
1136fpu_error_or_IRQA: 1160fpu_error_or_IRQA:
1137 pta its_IRQ, tr0 1161 pta its_IRQ, tr0
@@ -1481,6 +1505,7 @@ poke_real_address_q:
1481 ptabs LINK, tr0 1505 ptabs LINK, tr0
1482 blink tr0, r63 1506 blink tr0, r63
1483 1507
1508#ifdef CONFIG_MMU
1484/* 1509/*
1485 * --- User Access Handling Section 1510 * --- User Access Handling Section
1486 */ 1511 */
@@ -1604,6 +1629,7 @@ ___clear_user_exit:
1604 ptabs LINK, tr0 1629 ptabs LINK, tr0
1605 blink tr0, ZERO 1630 blink tr0, ZERO
1606 1631
1632#endif /* CONFIG_MMU */
1607 1633
1608/* 1634/*
1609 * int __strncpy_from_user(unsigned long __dest, unsigned long __src, 1635 * int __strncpy_from_user(unsigned long __dest, unsigned long __src,
@@ -2014,9 +2040,11 @@ sa_default_restorer:
2014 .global asm_uaccess_start /* Just a marker */ 2040 .global asm_uaccess_start /* Just a marker */
2015asm_uaccess_start: 2041asm_uaccess_start:
2016 2042
2043#ifdef CONFIG_MMU
2017 .long ___copy_user1, ___copy_user_exit 2044 .long ___copy_user1, ___copy_user_exit
2018 .long ___copy_user2, ___copy_user_exit 2045 .long ___copy_user2, ___copy_user_exit
2019 .long ___clear_user1, ___clear_user_exit 2046 .long ___clear_user1, ___clear_user_exit
2047#endif
2020 .long ___strncpy_from_user1, ___strncpy_from_user_exit 2048 .long ___strncpy_from_user1, ___strncpy_from_user_exit
2021 .long ___strnlen_user1, ___strnlen_user_exit 2049 .long ___strnlen_user1, ___strnlen_user_exit
2022 .long ___get_user_asm_b1, ___get_user_asm_b_exit 2050 .long ___get_user_asm_b1, ___get_user_asm_b_exit
diff --git a/arch/sh/kernel/cpu/sh5/probe.c b/arch/sh/kernel/cpu/sh5/probe.c
index 31f8cb0f6374..92ad844b5c12 100644
--- a/arch/sh/kernel/cpu/sh5/probe.c
+++ b/arch/sh/kernel/cpu/sh5/probe.c
@@ -15,6 +15,7 @@
15#include <linux/string.h> 15#include <linux/string.h>
16#include <asm/processor.h> 16#include <asm/processor.h>
17#include <asm/cache.h> 17#include <asm/cache.h>
18#include <asm/tlb.h>
18 19
19int __init detect_cpu_and_cache_system(void) 20int __init detect_cpu_and_cache_system(void)
20{ 21{
@@ -67,5 +68,8 @@ int __init detect_cpu_and_cache_system(void)
67 set_bit(SH_CACHE_MODE_WB, &(boot_cpu_data.dcache.flags)); 68 set_bit(SH_CACHE_MODE_WB, &(boot_cpu_data.dcache.flags));
68#endif 69#endif
69 70
71 /* Setup some I/D TLB defaults */
72 sh64_tlb_init();
73
70 return 0; 74 return 0;
71} 75}
diff --git a/arch/sh/kernel/early_printk.c b/arch/sh/kernel/early_printk.c
index 957f25611543..6b7d166694e2 100644
--- a/arch/sh/kernel/early_printk.c
+++ b/arch/sh/kernel/early_printk.c
@@ -141,7 +141,9 @@ static void scif_sercon_init(char *s)
141 */ 141 */
142static void scif_sercon_init(char *s) 142static void scif_sercon_init(char *s)
143{ 143{
144 struct uart_port *port = &scif_port;
144 unsigned baud = DEFAULT_BAUD; 145 unsigned baud = DEFAULT_BAUD;
146 unsigned int status;
145 char *e; 147 char *e;
146 148
147 if (*s == ',') 149 if (*s == ',')
@@ -160,19 +162,25 @@ static void scif_sercon_init(char *s)
160 baud = DEFAULT_BAUD; 162 baud = DEFAULT_BAUD;
161 } 163 }
162 164
163 ctrl_outw(0, scif_port.mapbase + 8); 165 do {
164 ctrl_outw(0, scif_port.mapbase); 166 status = sci_in(port, SCxSR);
167 } while (!(status & SCxSR_TEND(port)));
168
169 sci_out(port, SCSCR, 0); /* TE=0, RE=0 */
170 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
171 sci_out(port, SCSMR, 0);
165 172
166 /* Set baud rate */ 173 /* Set baud rate */
167 ctrl_outb((CONFIG_SH_PCLK_FREQ + 16 * baud) / 174 sci_out(port, SCBRR, (CONFIG_SH_PCLK_FREQ + 16 * baud) /
168 (32 * baud) - 1, scif_port.mapbase + 4); 175 (32 * baud) - 1);
169 176 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
170 ctrl_outw(12, scif_port.mapbase + 24); 177
171 ctrl_outw(8, scif_port.mapbase + 24); 178 sci_out(port, SCSPTR, 0);
172 ctrl_outw(0, scif_port.mapbase + 32); 179 sci_out(port, SCxSR, 0x60);
173 ctrl_outw(0x60, scif_port.mapbase + 16); 180 sci_out(port, SCLSR, 0);
174 ctrl_outw(0, scif_port.mapbase + 36); 181
175 ctrl_outw(0x30, scif_port.mapbase + 8); 182 sci_out(port, SCFCR, 0);
183 sci_out(port, SCSCR, 0x30); /* TE=1, RE=1 */
176} 184}
177#endif /* defined(CONFIG_CPU_SUBTYPE_SH7720) */ 185#endif /* defined(CONFIG_CPU_SUBTYPE_SH7720) */
178#endif /* !defined(CONFIG_SH_STANDARD_BIOS) */ 186#endif /* !defined(CONFIG_SH_STANDARD_BIOS) */
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 284f66f1ebbe..516bde9c50fa 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -53,6 +53,7 @@ EXPORT_SYMBOL(cpu_data);
53 * sh_mv= on the command line, prior to .machvec.init teardown. 53 * sh_mv= on the command line, prior to .machvec.init teardown.
54 */ 54 */
55struct sh_machine_vector sh_mv = { .mv_name = "generic", }; 55struct sh_machine_vector sh_mv = { .mv_name = "generic", };
56EXPORT_SYMBOL(sh_mv);
56 57
57#ifdef CONFIG_VT 58#ifdef CONFIG_VT
58struct screen_info screen_info; 59struct screen_info screen_info;
@@ -76,11 +77,18 @@ static struct resource data_resource = {
76 .flags = IORESOURCE_BUSY | IORESOURCE_MEM, 77 .flags = IORESOURCE_BUSY | IORESOURCE_MEM,
77}; 78};
78 79
80static struct resource bss_resource = {
81 .name = "Kernel bss",
82 .flags = IORESOURCE_BUSY | IORESOURCE_MEM,
83};
84
79unsigned long memory_start; 85unsigned long memory_start;
80EXPORT_SYMBOL(memory_start); 86EXPORT_SYMBOL(memory_start);
81unsigned long memory_end = 0; 87unsigned long memory_end = 0;
82EXPORT_SYMBOL(memory_end); 88EXPORT_SYMBOL(memory_end);
83 89
90static struct resource mem_resources[MAX_NUMNODES];
91
84int l1i_cache_shape, l1d_cache_shape, l2_cache_shape; 92int l1i_cache_shape, l1d_cache_shape, l2_cache_shape;
85 93
86static int __init early_parse_mem(char *p) 94static int __init early_parse_mem(char *p)
@@ -169,6 +177,40 @@ static inline void __init reserve_crashkernel(void)
169{} 177{}
170#endif 178#endif
171 179
180void __init __add_active_range(unsigned int nid, unsigned long start_pfn,
181 unsigned long end_pfn)
182{
183 struct resource *res = &mem_resources[nid];
184
185 WARN_ON(res->name); /* max one active range per node for now */
186
187 res->name = "System RAM";
188 res->start = start_pfn << PAGE_SHIFT;
189 res->end = (end_pfn << PAGE_SHIFT) - 1;
190 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
191 if (request_resource(&iomem_resource, res)) {
192 pr_err("unable to request memory_resource 0x%lx 0x%lx\n",
193 start_pfn, end_pfn);
194 return;
195 }
196
197 /*
198 * We don't know which RAM region contains kernel data,
199 * so we try it repeatedly and let the resource manager
200 * test it.
201 */
202 request_resource(res, &code_resource);
203 request_resource(res, &data_resource);
204 request_resource(res, &bss_resource);
205
206#ifdef CONFIG_KEXEC
207 if (crashk_res.start != crashk_res.end)
208 request_resource(res, &crashk_res);
209#endif
210
211 add_active_range(nid, start_pfn, end_pfn);
212}
213
172void __init setup_bootmem_allocator(unsigned long free_pfn) 214void __init setup_bootmem_allocator(unsigned long free_pfn)
173{ 215{
174 unsigned long bootmap_size; 216 unsigned long bootmap_size;
@@ -181,7 +223,7 @@ void __init setup_bootmem_allocator(unsigned long free_pfn)
181 bootmap_size = init_bootmem_node(NODE_DATA(0), free_pfn, 223 bootmap_size = init_bootmem_node(NODE_DATA(0), free_pfn,
182 min_low_pfn, max_low_pfn); 224 min_low_pfn, max_low_pfn);
183 225
184 add_active_range(0, min_low_pfn, max_low_pfn); 226 __add_active_range(0, min_low_pfn, max_low_pfn);
185 register_bootmem_low_pages(); 227 register_bootmem_low_pages();
186 228
187 node_set_online(0); 229 node_set_online(0);
@@ -267,6 +309,8 @@ void __init setup_arch(char **cmdline_p)
267 code_resource.end = virt_to_phys(_etext)-1; 309 code_resource.end = virt_to_phys(_etext)-1;
268 data_resource.start = virt_to_phys(_etext); 310 data_resource.start = virt_to_phys(_etext);
269 data_resource.end = virt_to_phys(_edata)-1; 311 data_resource.end = virt_to_phys(_edata)-1;
312 bss_resource.start = virt_to_phys(__bss_start);
313 bss_resource.end = virt_to_phys(_ebss)-1;
270 314
271 memory_start = (unsigned long)__va(__MEMORY_START); 315 memory_start = (unsigned long)__va(__MEMORY_START);
272 if (!memory_end) 316 if (!memory_end)
diff --git a/arch/sh/kernel/sh_ksyms_32.c b/arch/sh/kernel/sh_ksyms_32.c
index 6d405462cee8..8f916536719c 100644
--- a/arch/sh/kernel/sh_ksyms_32.c
+++ b/arch/sh/kernel/sh_ksyms_32.c
@@ -20,8 +20,6 @@
20extern int dump_fpu(struct pt_regs *, elf_fpregset_t *); 20extern int dump_fpu(struct pt_regs *, elf_fpregset_t *);
21extern struct hw_interrupt_type no_irq_type; 21extern struct hw_interrupt_type no_irq_type;
22 22
23EXPORT_SYMBOL(sh_mv);
24
25/* platform dependent support */ 23/* platform dependent support */
26EXPORT_SYMBOL(dump_fpu); 24EXPORT_SYMBOL(dump_fpu);
27EXPORT_SYMBOL(kernel_thread); 25EXPORT_SYMBOL(kernel_thread);
diff --git a/arch/sh/kernel/sh_ksyms_64.c b/arch/sh/kernel/sh_ksyms_64.c
index a310c9707f03..9324d32adacc 100644
--- a/arch/sh/kernel/sh_ksyms_64.c
+++ b/arch/sh/kernel/sh_ksyms_64.c
@@ -16,6 +16,7 @@
16#include <linux/in6.h> 16#include <linux/in6.h>
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/screen_info.h> 18#include <linux/screen_info.h>
19#include <asm/cacheflush.h>
19#include <asm/processor.h> 20#include <asm/processor.h>
20#include <asm/uaccess.h> 21#include <asm/uaccess.h>
21#include <asm/checksum.h> 22#include <asm/checksum.h>
@@ -29,25 +30,50 @@ extern int dump_fpu(struct pt_regs *, elf_fpregset_t *);
29EXPORT_SYMBOL(dump_fpu); 30EXPORT_SYMBOL(dump_fpu);
30EXPORT_SYMBOL(kernel_thread); 31EXPORT_SYMBOL(kernel_thread);
31 32
33#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU)
34EXPORT_SYMBOL(clear_user_page);
35#endif
36
37#ifndef CONFIG_CACHE_OFF
38EXPORT_SYMBOL(flush_dcache_page);
39#endif
40
32/* Networking helper routines. */ 41/* Networking helper routines. */
42EXPORT_SYMBOL(csum_partial);
33EXPORT_SYMBOL(csum_partial_copy_nocheck); 43EXPORT_SYMBOL(csum_partial_copy_nocheck);
44#ifdef CONFIG_IPV6
45EXPORT_SYMBOL(csum_ipv6_magic);
46#endif
34 47
35#ifdef CONFIG_VT 48#ifdef CONFIG_VT
36EXPORT_SYMBOL(screen_info); 49EXPORT_SYMBOL(screen_info);
37#endif 50#endif
38 51
52EXPORT_SYMBOL(__put_user_asm_b);
53EXPORT_SYMBOL(__put_user_asm_w);
39EXPORT_SYMBOL(__put_user_asm_l); 54EXPORT_SYMBOL(__put_user_asm_l);
55EXPORT_SYMBOL(__put_user_asm_q);
56EXPORT_SYMBOL(__get_user_asm_b);
57EXPORT_SYMBOL(__get_user_asm_w);
40EXPORT_SYMBOL(__get_user_asm_l); 58EXPORT_SYMBOL(__get_user_asm_l);
59EXPORT_SYMBOL(__get_user_asm_q);
60EXPORT_SYMBOL(__strnlen_user);
61EXPORT_SYMBOL(__strncpy_from_user);
62EXPORT_SYMBOL(clear_page);
63EXPORT_SYMBOL(__clear_user);
41EXPORT_SYMBOL(copy_page); 64EXPORT_SYMBOL(copy_page);
42EXPORT_SYMBOL(__copy_user); 65EXPORT_SYMBOL(__copy_user);
43EXPORT_SYMBOL(empty_zero_page); 66EXPORT_SYMBOL(empty_zero_page);
44EXPORT_SYMBOL(memcpy); 67EXPORT_SYMBOL(memcpy);
45EXPORT_SYMBOL(__udelay); 68EXPORT_SYMBOL(__udelay);
46EXPORT_SYMBOL(__ndelay); 69EXPORT_SYMBOL(__ndelay);
70EXPORT_SYMBOL(__const_udelay);
47 71
48/* Ugh. These come in from libgcc.a at link time. */ 72/* Ugh. These come in from libgcc.a at link time. */
49#define DECLARE_EXPORT(name) extern void name(void);EXPORT_SYMBOL(name) 73#define DECLARE_EXPORT(name) extern void name(void);EXPORT_SYMBOL(name)
50 74
51DECLARE_EXPORT(__sdivsi3); 75DECLARE_EXPORT(__sdivsi3);
76DECLARE_EXPORT(__sdivsi3_2);
52DECLARE_EXPORT(__muldi3); 77DECLARE_EXPORT(__muldi3);
53DECLARE_EXPORT(__udivsi3); 78DECLARE_EXPORT(__udivsi3);
79DECLARE_EXPORT(__div_table);
diff --git a/arch/sh/kernel/time_64.c b/arch/sh/kernel/time_64.c
index 898977ee2030..022a55f1c1d4 100644
--- a/arch/sh/kernel/time_64.c
+++ b/arch/sh/kernel/time_64.c
@@ -172,6 +172,7 @@ void do_gettimeofday(struct timeval *tv)
172 tv->tv_sec = sec; 172 tv->tv_sec = sec;
173 tv->tv_usec = usec; 173 tv->tv_usec = usec;
174} 174}
175EXPORT_SYMBOL(do_gettimeofday);
175 176
176int do_settimeofday(struct timespec *tv) 177int do_settimeofday(struct timespec *tv)
177{ 178{
@@ -240,7 +241,7 @@ static inline void do_timer_interrupt(void)
240 * the irq version of write_lock because as just said we have irq 241 * the irq version of write_lock because as just said we have irq
241 * locally disabled. -arca 242 * locally disabled. -arca
242 */ 243 */
243 write_lock(&xtime_lock); 244 write_seqlock(&xtime_lock);
244 asm ("getcon cr62, %0" : "=r" (current_ctc)); 245 asm ("getcon cr62, %0" : "=r" (current_ctc));
245 ctc_last_interrupt = (unsigned long) current_ctc; 246 ctc_last_interrupt = (unsigned long) current_ctc;
246 247
@@ -266,7 +267,7 @@ static inline void do_timer_interrupt(void)
266 /* do it again in 60 s */ 267 /* do it again in 60 s */
267 last_rtc_update = xtime.tv_sec - 600; 268 last_rtc_update = xtime.tv_sec - 600;
268 } 269 }
269 write_unlock(&xtime_lock); 270 write_sequnlock(&xtime_lock);
270 271
271#ifndef CONFIG_SMP 272#ifndef CONFIG_SMP
272 update_process_times(user_mode(get_irq_regs())); 273 update_process_times(user_mode(get_irq_regs()));
diff --git a/arch/sh/lib64/dbg.c b/arch/sh/lib64/dbg.c
index 75825ef6e084..2fb8eaf6de60 100644
--- a/arch/sh/lib64/dbg.c
+++ b/arch/sh/lib64/dbg.c
@@ -186,8 +186,8 @@ void evt_debug(int evt, int ret_addr, int event, int tra, struct pt_regs *regs)
186 rr->pc = regs->pc; 186 rr->pc = regs->pc;
187 187
188 if (sp < stack_bottom + 3092) { 188 if (sp < stack_bottom + 3092) {
189 printk("evt_debug : stack underflow report\n");
190 int i, j; 189 int i, j;
190 printk("evt_debug : stack underflow report\n");
191 for (j=0, i = event_ptr; j<16; j++) { 191 for (j=0, i = event_ptr; j<16; j++) {
192 rr = event_ring + i; 192 rr = event_ring + i;
193 printk("evt=%08x event=%08x tra=%08x pid=%5d sp=%08lx pc=%08lx\n", 193 printk("evt=%08x event=%08x tra=%08x pid=%5d sp=%08lx pc=%08lx\n",
diff --git a/arch/sh/mm/Makefile_64 b/arch/sh/mm/Makefile_64
index cbd6aa33c5ac..0d92a8a3ac9a 100644
--- a/arch/sh/mm/Makefile_64
+++ b/arch/sh/mm/Makefile_64
@@ -2,10 +2,11 @@
2# Makefile for the Linux SuperH-specific parts of the memory manager. 2# Makefile for the Linux SuperH-specific parts of the memory manager.
3# 3#
4 4
5obj-y := init.o extable_64.o consistent.o 5obj-y := init.o consistent.o
6 6
7mmu-y := tlb-nommu.o pg-nommu.o 7mmu-y := tlb-nommu.o pg-nommu.o extable_32.o
8mmu-$(CONFIG_MMU) := fault_64.o ioremap_64.o tlbflush_64.o tlb-sh5.o 8mmu-$(CONFIG_MMU) := fault_64.o ioremap_64.o tlbflush_64.o tlb-sh5.o \
9 extable_64.o
9 10
10ifndef CONFIG_CACHE_OFF 11ifndef CONFIG_CACHE_OFF
11obj-y += cache-sh5.o 12obj-y += cache-sh5.o
diff --git a/arch/sh/mm/cache-sh5.c b/arch/sh/mm/cache-sh5.c
index 3877321fcede..9e277ec7d536 100644
--- a/arch/sh/mm/cache-sh5.c
+++ b/arch/sh/mm/cache-sh5.c
@@ -714,6 +714,7 @@ void flush_cache_sigtramp(unsigned long vaddr)
714 sh64_icache_inv_current_user_range(vaddr, end); 714 sh64_icache_inv_current_user_range(vaddr, end);
715} 715}
716 716
717#ifdef CONFIG_MMU
717/* 718/*
718 * These *MUST* lie in an area of virtual address space that's otherwise 719 * These *MUST* lie in an area of virtual address space that's otherwise
719 * unused. 720 * unused.
@@ -830,3 +831,4 @@ void clear_user_page(void *to, unsigned long address, struct page *page)
830 else 831 else
831 sh64_clear_user_page_coloured(to, address); 832 sh64_clear_user_page_coloured(to, address);
832} 833}
834#endif
diff --git a/arch/sh/mm/ioremap_64.c b/arch/sh/mm/ioremap_64.c
index cea224c3e49b..6e0be24d26e2 100644
--- a/arch/sh/mm/ioremap_64.c
+++ b/arch/sh/mm/ioremap_64.c
@@ -343,6 +343,7 @@ unsigned long onchip_remap(unsigned long phys, unsigned long size, const char *n
343 343
344 return shmedia_alloc_io(phys, size, name); 344 return shmedia_alloc_io(phys, size, name);
345} 345}
346EXPORT_SYMBOL(onchip_remap);
346 347
347void onchip_unmap(unsigned long vaddr) 348void onchip_unmap(unsigned long vaddr)
348{ 349{
@@ -370,6 +371,7 @@ void onchip_unmap(unsigned long vaddr)
370 kfree(res); 371 kfree(res);
371 } 372 }
372} 373}
374EXPORT_SYMBOL(onchip_unmap);
373 375
374#ifdef CONFIG_PROC_FS 376#ifdef CONFIG_PROC_FS
375static int 377static int
diff --git a/arch/sh/mm/numa.c b/arch/sh/mm/numa.c
index 2de7302724fc..1663199ce888 100644
--- a/arch/sh/mm/numa.c
+++ b/arch/sh/mm/numa.c
@@ -59,7 +59,7 @@ void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end)
59 free_pfn = start_pfn = start >> PAGE_SHIFT; 59 free_pfn = start_pfn = start >> PAGE_SHIFT;
60 end_pfn = end >> PAGE_SHIFT; 60 end_pfn = end >> PAGE_SHIFT;
61 61
62 add_active_range(nid, start_pfn, end_pfn); 62 __add_active_range(nid, start_pfn, end_pfn);
63 63
64 /* Node-local pgdat */ 64 /* Node-local pgdat */
65 NODE_DATA(nid) = pfn_to_kaddr(free_pfn); 65 NODE_DATA(nid) = pfn_to_kaddr(free_pfn);
diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types
index 987c6682bf99..1bba7d36be90 100644
--- a/arch/sh/tools/mach-types
+++ b/arch/sh/tools/mach-types
@@ -28,7 +28,6 @@ HD64465 HD64465
287751SYSTEMH SH_7751_SYSTEMH 287751SYSTEMH SH_7751_SYSTEMH
29HP6XX SH_HP6XX 29HP6XX SH_HP6XX
30DREAMCAST SH_DREAMCAST 30DREAMCAST SH_DREAMCAST
31MPC1211 SH_MPC1211
32SNAPGEAR SH_SECUREEDGE5410 31SNAPGEAR SH_SECUREEDGE5410
33EDOSK7705 SH_EDOSK7705 32EDOSK7705 SH_EDOSK7705
34SH4202_MICRODEV SH_SH4202_MICRODEV 33SH4202_MICRODEV SH_SH4202_MICRODEV
diff --git a/drivers/input/serio/i8042-io.h b/drivers/input/serio/i8042-io.h
index 3b4e13b9ce1b..f451c7351a9d 100644
--- a/drivers/input/serio/i8042-io.h
+++ b/drivers/input/serio/i8042-io.h
@@ -25,7 +25,7 @@
25#elif defined(__arm__) 25#elif defined(__arm__)
26/* defined in include/asm-arm/arch-xxx/irqs.h */ 26/* defined in include/asm-arm/arch-xxx/irqs.h */
27#include <asm/irq.h> 27#include <asm/irq.h>
28#elif defined(CONFIG_SUPERH64) 28#elif defined(CONFIG_SH_CAYMAN)
29#include <asm/irq.h> 29#include <asm/irq.h>
30#else 30#else
31# define I8042_KBD_IRQ 1 31# define I8042_KBD_IRQ 1
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index 1bd69aa9e22a..17bc87a43ff4 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -374,7 +374,7 @@ config MTD_REDWOOD
374 374
375config MTD_SOLUTIONENGINE 375config MTD_SOLUTIONENGINE
376 tristate "CFI Flash device mapped on Hitachi SolutionEngine" 376 tristate "CFI Flash device mapped on Hitachi SolutionEngine"
377 depends on SUPERH && MTD_CFI && MTD_REDBOOT_PARTS 377 depends on SUPERH && SOLUTION_ENGINE && MTD_CFI && MTD_REDBOOT_PARTS
378 help 378 help
379 This enables access to the flash chips on the Hitachi SolutionEngine and 379 This enables access to the flash chips on the Hitachi SolutionEngine and
380 similar boards. Say 'Y' if you are building a kernel for such a board. 380 similar boards. Say 'Y' if you are building a kernel for such a board.
@@ -480,13 +480,6 @@ config MTD_H720X
480 This enables access to the flash chips on the Hynix evaluation boards. 480 This enables access to the flash chips on the Hynix evaluation boards.
481 If you have such a board, say 'Y'. 481 If you have such a board, say 'Y'.
482 482
483config MTD_MPC1211
484 tristate "CFI Flash device mapped on Interface MPC-1211"
485 depends on SH_MPC1211 && MTD_CFI
486 help
487 This enables access to the flash chips on the Interface MPC-1211(CTP/PCI/MPC-SH02).
488 If you have such a board, say 'Y'.
489
490config MTD_OMAP_NOR 483config MTD_OMAP_NOR
491 tristate "TI OMAP board mappings" 484 tristate "TI OMAP board mappings"
492 depends on MTD_CFI && ARCH_OMAP 485 depends on MTD_CFI && ARCH_OMAP
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index a9cbe80f99a0..957fb5f70f5e 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -58,7 +58,6 @@ obj-$(CONFIG_MTD_WALNUT) += walnut.o
58obj-$(CONFIG_MTD_H720X) += h720x-flash.o 58obj-$(CONFIG_MTD_H720X) += h720x-flash.o
59obj-$(CONFIG_MTD_SBC8240) += sbc8240.o 59obj-$(CONFIG_MTD_SBC8240) += sbc8240.o
60obj-$(CONFIG_MTD_NOR_TOTO) += omap-toto-flash.o 60obj-$(CONFIG_MTD_NOR_TOTO) += omap-toto-flash.o
61obj-$(CONFIG_MTD_MPC1211) += mpc1211.o
62obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o 61obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o
63obj-$(CONFIG_MTD_IXP2000) += ixp2000.o 62obj-$(CONFIG_MTD_IXP2000) += ixp2000.o
64obj-$(CONFIG_MTD_WRSBC8260) += wr_sbc82xx_flash.o 63obj-$(CONFIG_MTD_WRSBC8260) += wr_sbc82xx_flash.o
diff --git a/drivers/mtd/maps/mpc1211.c b/drivers/mtd/maps/mpc1211.c
deleted file mode 100644
index 45a00fac88ac..000000000000
--- a/drivers/mtd/maps/mpc1211.c
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * Flash on MPC-1211
3 *
4 * $Id: mpc1211.c,v 1.4 2004/09/16 23:27:13 gleixner Exp $
5 *
6 * (C) 2002 Interface, Saito.K & Jeanne
7 *
8 * GPL'd
9 */
10
11#include <linux/module.h>
12#include <linux/types.h>
13#include <linux/kernel.h>
14#include <asm/io.h>
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/map.h>
17#include <linux/mtd/partitions.h>
18
19static struct mtd_info *flash_mtd;
20static struct mtd_partition *parsed_parts;
21
22struct map_info mpc1211_flash_map = {
23 .name = "MPC-1211 FLASH",
24 .size = 0x80000,
25 .bankwidth = 1,
26};
27
28static struct mtd_partition mpc1211_partitions[] = {
29 {
30 .name = "IPL & ETH-BOOT",
31 .offset = 0x00000000,
32 .size = 0x10000,
33 },
34 {
35 .name = "Flash FS",
36 .offset = 0x00010000,
37 .size = MTDPART_SIZ_FULL,
38 }
39};
40
41static int __init init_mpc1211_maps(void)
42{
43 int nr_parts;
44
45 mpc1211_flash_map.phys = 0;
46 mpc1211_flash_map.virt = (void __iomem *)P2SEGADDR(0);
47
48 simple_map_init(&mpc1211_flash_map);
49
50 printk(KERN_NOTICE "Probing for flash chips at 0x00000000:\n");
51 flash_mtd = do_map_probe("jedec_probe", &mpc1211_flash_map);
52 if (!flash_mtd) {
53 printk(KERN_NOTICE "Flash chips not detected at either possible location.\n");
54 return -ENXIO;
55 }
56 printk(KERN_NOTICE "MPC-1211: Flash at 0x%08lx\n", mpc1211_flash_map.virt & 0x1fffffff);
57 flash_mtd->module = THIS_MODULE;
58
59 parsed_parts = mpc1211_partitions;
60 nr_parts = ARRAY_SIZE(mpc1211_partitions);
61
62 add_mtd_partitions(flash_mtd, parsed_parts, nr_parts);
63 return 0;
64}
65
66static void __exit cleanup_mpc1211_maps(void)
67{
68 if (parsed_parts)
69 del_mtd_partitions(flash_mtd);
70 else
71 del_mtd_device(flash_mtd);
72 map_destroy(flash_mtd);
73}
74
75module_init(init_mpc1211_maps);
76module_exit(cleanup_mpc1211_maps);
77
78MODULE_LICENSE("GPL");
79MODULE_AUTHOR("Saito.K & Jeanne <ksaito@interface.co.jp>");
80MODULE_DESCRIPTION("MTD map driver for MPC-1211 boards. Interface");
diff --git a/drivers/rtc/rtc-sh.c b/drivers/rtc/rtc-sh.c
index 110699bb4787..1f88e9e914ec 100644
--- a/drivers/rtc/rtc-sh.c
+++ b/drivers/rtc/rtc-sh.c
@@ -616,7 +616,7 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
616 goto err_badres; 616 goto err_badres;
617 } 617 }
618 618
619 rtc->regbase = (void __iomem *)rtc->res->start; 619 rtc->regbase = ioremap_nocache(rtc->res->start, rtc->regsize);
620 if (unlikely(!rtc->regbase)) { 620 if (unlikely(!rtc->regbase)) {
621 ret = -EINVAL; 621 ret = -EINVAL;
622 goto err_badmap; 622 goto err_badmap;
@@ -626,7 +626,7 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
626 &sh_rtc_ops, THIS_MODULE); 626 &sh_rtc_ops, THIS_MODULE);
627 if (IS_ERR(rtc->rtc_dev)) { 627 if (IS_ERR(rtc->rtc_dev)) {
628 ret = PTR_ERR(rtc->rtc_dev); 628 ret = PTR_ERR(rtc->rtc_dev);
629 goto err_badmap; 629 goto err_unmap;
630 } 630 }
631 631
632 rtc->capabilities = RTC_DEF_CAPABILITIES; 632 rtc->capabilities = RTC_DEF_CAPABILITIES;
@@ -653,7 +653,7 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
653 dev_err(&pdev->dev, 653 dev_err(&pdev->dev,
654 "request period IRQ failed with %d, IRQ %d\n", ret, 654 "request period IRQ failed with %d, IRQ %d\n", ret,
655 rtc->periodic_irq); 655 rtc->periodic_irq);
656 goto err_badmap; 656 goto err_unmap;
657 } 657 }
658 658
659 ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, IRQF_DISABLED, 659 ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, IRQF_DISABLED,
@@ -663,7 +663,7 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
663 "request carry IRQ failed with %d, IRQ %d\n", ret, 663 "request carry IRQ failed with %d, IRQ %d\n", ret,
664 rtc->carry_irq); 664 rtc->carry_irq);
665 free_irq(rtc->periodic_irq, rtc); 665 free_irq(rtc->periodic_irq, rtc);
666 goto err_badmap; 666 goto err_unmap;
667 } 667 }
668 668
669 ret = request_irq(rtc->alarm_irq, sh_rtc_alarm, IRQF_DISABLED, 669 ret = request_irq(rtc->alarm_irq, sh_rtc_alarm, IRQF_DISABLED,
@@ -674,7 +674,7 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
674 rtc->alarm_irq); 674 rtc->alarm_irq);
675 free_irq(rtc->carry_irq, rtc); 675 free_irq(rtc->carry_irq, rtc);
676 free_irq(rtc->periodic_irq, rtc); 676 free_irq(rtc->periodic_irq, rtc);
677 goto err_badmap; 677 goto err_unmap;
678 } 678 }
679 679
680 tmp = readb(rtc->regbase + RCR1); 680 tmp = readb(rtc->regbase + RCR1);
@@ -684,6 +684,8 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
684 684
685 return 0; 685 return 0;
686 686
687err_unmap:
688 iounmap(rtc->regbase);
687err_badmap: 689err_badmap:
688 release_resource(rtc->res); 690 release_resource(rtc->res);
689err_badres: 691err_badres:
@@ -708,6 +710,8 @@ static int __devexit sh_rtc_remove(struct platform_device *pdev)
708 710
709 release_resource(rtc->res); 711 release_resource(rtc->res);
710 712
713 iounmap(rtc->regbase);
714
711 platform_set_drvdata(pdev, NULL); 715 platform_set_drvdata(pdev, NULL);
712 716
713 kfree(rtc); 717 kfree(rtc);
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index 969106187718..8fdafc27fce8 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -42,14 +42,12 @@
42#include <linux/console.h> 42#include <linux/console.h>
43#include <linux/platform_device.h> 43#include <linux/platform_device.h>
44#include <linux/serial_sci.h> 44#include <linux/serial_sci.h>
45
46#ifdef CONFIG_CPU_FREQ
47#include <linux/notifier.h> 45#include <linux/notifier.h>
48#include <linux/cpufreq.h> 46#include <linux/cpufreq.h>
49#endif 47#include <linux/clk.h>
50
51#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
52#include <linux/ctype.h> 48#include <linux/ctype.h>
49
50#ifdef CONFIG_SUPERH
53#include <asm/clock.h> 51#include <asm/clock.h>
54#include <asm/sh_bios.h> 52#include <asm/sh_bios.h>
55#include <asm/kgdb.h> 53#include <asm/kgdb.h>
@@ -80,7 +78,7 @@ struct sci_port {
80 struct timer_list break_timer; 78 struct timer_list break_timer;
81 int break_flag; 79 int break_flag;
82 80
83#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64) 81#ifdef CONFIG_SUPERH
84 /* Port clock */ 82 /* Port clock */
85 struct clk *clk; 83 struct clk *clk;
86#endif 84#endif
@@ -365,21 +363,19 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
365static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 363static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
366{ 364{
367 unsigned int fcr_val = 0; 365 unsigned int fcr_val = 0;
366 unsigned short data;
368 367
369 if (cflag & CRTSCTS) { 368 if (port->mapbase == 0xffe00000) {
370 fcr_val |= SCFCR_MCE; 369 data = ctrl_inw(PSCR);
371 370 data &= ~0x03cf;
372 ctrl_outw(0x0000, PORT_PSCR); 371 if (cflag & CRTSCTS)
373 } else { 372 fcr_val |= SCFCR_MCE;
374 unsigned short data; 373 else
375 374 data |= 0x0340;
376 data = ctrl_inw(PORT_PSCR);
377 data &= 0x033f;
378 data |= 0x0400;
379 ctrl_outw(data, PORT_PSCR);
380 375
381 ctrl_outw(ctrl_inw(SCSPTR0) & 0x17, SCSPTR0); 376 ctrl_outw(data, PSCR);
382 } 377 }
378 /* SCIF1 and SCIF2 should be setup by board code */
383 379
384 sci_out(port, SCFCR, fcr_val); 380 sci_out(port, SCFCR, fcr_val);
385} 381}
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index fa8700a968fc..eb84833233fd 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -76,12 +76,13 @@
76# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ 76# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
77# define SCIF_ONLY 77# define SCIF_ONLY
78#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 78#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
79# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 79# define PADR 0xA4050120
80# define SCSPTR0 SCPDR0 80# define PSDR 0xA405013e
81# define PWDR 0xA4050166
82# define PSCR 0xA405011E
81# define SCIF_ORER 0x0001 /* overrun error bit */ 83# define SCIF_ORER 0x0001 /* overrun error bit */
82# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 84# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
83# define SCIF_ONLY 85# define SCIF_ONLY
84# define PORT_PSCR 0xA405011E
85#elif defined(CONFIG_CPU_SUBTYPE_SH7366) 86#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
86# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 87# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
87# define SCSPTR0 SCPDR0 88# define SCSPTR0 SCPDR0
@@ -320,7 +321,7 @@
320 unsigned int addr = port->mapbase + (offset); \ 321 unsigned int addr = port->mapbase + (offset); \
321 if ((size) == 8) { \ 322 if ((size) == 8) { \
322 ctrl_outb(value, addr); \ 323 ctrl_outb(value, addr); \
323 } else { \ 324 } else if ((size) == 16) { \
324 ctrl_outw(value, addr); \ 325 ctrl_outw(value, addr); \
325 } 326 }
326 327
@@ -451,7 +452,11 @@ SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
451SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 452SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
452#else 453#else
453SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 454SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
455#if defined(CONFIG_CPU_SUBTYPE_SH7722)
456SCIF_FNS(SCSPTR, 0, 0, 0, 0)
457#else
454SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) 458SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
459#endif
455SCIF_FNS(SCLSR, 0, 0, 0x24, 16) 460SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
456#endif 461#endif
457#endif 462#endif
@@ -593,13 +598,25 @@ static inline int sci_rxd_in(struct uart_port *port)
593 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 598 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
594 return 1; 599 return 1;
595} 600}
596#elif defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7366) 601#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
597static inline int sci_rxd_in(struct uart_port *port) 602static inline int sci_rxd_in(struct uart_port *port)
598{ 603{
599 if (port->mapbase == 0xffe00000) 604 if (port->mapbase == 0xffe00000)
600 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ 605 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
601 return 1; 606 return 1;
602} 607}
608#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
609static inline int sci_rxd_in(struct uart_port *port)
610{
611 if (port->mapbase == 0xffe00000)
612 return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
613 if (port->mapbase == 0xffe10000)
614 return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
615 if (port->mapbase == 0xffe20000)
616 return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
617
618 return 1;
619}
603#elif defined(CONFIG_CPU_SUBTYPE_SH7723) 620#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
604static inline int sci_rxd_in(struct uart_port *port) 621static inline int sci_rxd_in(struct uart_port *port)
605{ 622{
diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h
index 092ff9d872c3..6813c3220a1d 100644
--- a/include/asm-sh/cpu-sh3/dma.h
+++ b/include/asm-sh/cpu-sh3/dma.h
@@ -3,19 +3,19 @@
3 3
4 4
5#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 5#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 6 defined(CONFIG_CPU_SUBTYPE_SH7721)
7 defined(CONFIG_CPU_SUBTYPE_SH7709)
8#define SH_DMAC_BASE 0xa4010020 7#define SH_DMAC_BASE 0xa4010020
8#else
9#define SH_DMAC_BASE 0xa4000020
10#endif
9 11
12#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
10#define DMTE0_IRQ 48 13#define DMTE0_IRQ 48
11#define DMTE1_IRQ 49 14#define DMTE1_IRQ 49
12#define DMTE2_IRQ 50 15#define DMTE2_IRQ 50
13#define DMTE3_IRQ 51 16#define DMTE3_IRQ 51
14#define DMTE4_IRQ 76 17#define DMTE4_IRQ 76
15#define DMTE5_IRQ 77 18#define DMTE5_IRQ 77
16
17#else
18#define SH_DMAC_BASE 0xa4000020
19#endif 19#endif
20 20
21/* Definitions for the SuperH DMAC */ 21/* Definitions for the SuperH DMAC */
diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index c958fdaa0095..7438d1e21bc9 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -79,6 +79,10 @@ struct intc_desc {
79 struct intc_sense_reg *sense_regs; 79 struct intc_sense_reg *sense_regs;
80 unsigned int nr_sense_regs; 80 unsigned int nr_sense_regs;
81 char *name; 81 char *name;
82#ifdef CONFIG_CPU_SH3
83 struct intc_mask_reg *ack_regs;
84 unsigned int nr_ack_regs;
85#endif
82}; 86};
83 87
84#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a) 88#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
@@ -91,10 +95,25 @@ struct intc_desc symbol __initdata = { \
91 chipname, \ 95 chipname, \
92} 96}
93 97
98#ifdef CONFIG_CPU_SH3
99#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \
100 mask_regs, prio_regs, sense_regs, ack_regs) \
101struct intc_desc symbol __initdata = { \
102 _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
103 _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
104 _INTC_ARRAY(sense_regs), \
105 chipname, \
106 _INTC_ARRAY(ack_regs), \
107}
108#endif
109
94void __init register_intc_controller(struct intc_desc *desc); 110void __init register_intc_controller(struct intc_desc *desc);
95int intc_set_priority(unsigned int irq, unsigned int prio); 111int intc_set_priority(unsigned int irq, unsigned int prio);
96 112
97void __init plat_irq_setup(void); 113void __init plat_irq_setup(void);
114#ifdef CONFIG_CPU_SH3
115void __init plat_irq_setup_sh3(void);
116#endif
98 117
99enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210, 118enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
100 IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK, 119 IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h
index 356e50d06745..a4fbf0c84fb1 100644
--- a/include/asm-sh/io.h
+++ b/include/asm-sh/io.h
@@ -268,11 +268,6 @@ unsigned long long peek_real_address_q(unsigned long long addr);
268unsigned long long poke_real_address_q(unsigned long long addr, 268unsigned long long poke_real_address_q(unsigned long long addr,
269 unsigned long long val); 269 unsigned long long val);
270 270
271/* arch/sh/mm/ioremap_64.c */
272unsigned long onchip_remap(unsigned long addr, unsigned long size,
273 const char *name);
274extern void onchip_unmap(unsigned long vaddr);
275
276#if !defined(CONFIG_MMU) 271#if !defined(CONFIG_MMU)
277#define virt_to_phys(address) ((unsigned long)(address)) 272#define virt_to_phys(address) ((unsigned long)(address))
278#define phys_to_virt(address) ((void *)(address)) 273#define phys_to_virt(address) ((void *)(address))
@@ -302,9 +297,16 @@ extern void onchip_unmap(unsigned long vaddr);
302void __iomem *__ioremap(unsigned long offset, unsigned long size, 297void __iomem *__ioremap(unsigned long offset, unsigned long size,
303 unsigned long flags); 298 unsigned long flags);
304void __iounmap(void __iomem *addr); 299void __iounmap(void __iomem *addr);
300
301/* arch/sh/mm/ioremap_64.c */
302unsigned long onchip_remap(unsigned long addr, unsigned long size,
303 const char *name);
304extern void onchip_unmap(unsigned long vaddr);
305#else 305#else
306#define __ioremap(offset, size, flags) ((void __iomem *)(offset)) 306#define __ioremap(offset, size, flags) ((void __iomem *)(offset))
307#define __iounmap(addr) do { } while (0) 307#define __iounmap(addr) do { } while (0)
308#define onchip_remap(addr, size, name) (addr)
309#define onchip_unmap(addr) do { } while (0)
308#endif /* CONFIG_MMU */ 310#endif /* CONFIG_MMU */
309 311
310static inline void __iomem * 312static inline void __iomem *
diff --git a/include/asm-sh/keyboard.h b/include/asm-sh/keyboard.h
deleted file mode 100644
index 31dcc4fa5f28..000000000000
--- a/include/asm-sh/keyboard.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __ASM_SH_KEYBOARD_H
2#define __ASM_SH_KEYBOARD_H
3/*
4 * $Id: keyboard.h,v 1.1.1.1 2001/10/15 20:45:09 mrbrown Exp $
5 */
6
7#include <linux/kd.h>
8#include <asm/machvec.h>
9
10#ifdef CONFIG_SH_MPC1211
11#include <asm/mpc1211/keyboard-mpc1211.h>
12#endif
13#endif
diff --git a/include/asm-sh/mmu_context.h b/include/asm-sh/mmu_context.h
index fe58d00b250c..87e812f68bb0 100644
--- a/include/asm-sh/mmu_context.h
+++ b/include/asm-sh/mmu_context.h
@@ -27,6 +27,7 @@
27/* ASID is 8-bit value, so it can't be 0x100 */ 27/* ASID is 8-bit value, so it can't be 0x100 */
28#define MMU_NO_ASID 0x100 28#define MMU_NO_ASID 0x100
29 29
30#ifdef CONFIG_MMU
30#define asid_cache(cpu) (cpu_data[cpu].asid_cache) 31#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
31#define cpu_context(cpu, mm) ((mm)->context.id[cpu]) 32#define cpu_context(cpu, mm) ((mm)->context.id[cpu])
32 33
@@ -38,7 +39,6 @@
38 */ 39 */
39#define MMU_VPN_MASK 0xfffff000 40#define MMU_VPN_MASK 0xfffff000
40 41
41#ifdef CONFIG_MMU
42#if defined(CONFIG_SUPERH32) 42#if defined(CONFIG_SUPERH32)
43#include "mmu_context_32.h" 43#include "mmu_context_32.h"
44#else 44#else
@@ -129,6 +129,8 @@ static inline void switch_mm(struct mm_struct *prev,
129#define destroy_context(mm) do { } while (0) 129#define destroy_context(mm) do { } while (0)
130#define set_asid(asid) do { } while (0) 130#define set_asid(asid) do { } while (0)
131#define get_asid() (0) 131#define get_asid() (0)
132#define cpu_asid(cpu, mm) ({ (void)cpu; 0; })
133#define switch_and_save_asid(asid) (0)
132#define set_TTB(pgd) do { } while (0) 134#define set_TTB(pgd) do { } while (0)
133#define get_TTB() (0) 135#define get_TTB() (0)
134#define activate_context(mm,cpu) do { } while (0) 136#define activate_context(mm,cpu) do { } while (0)
diff --git a/include/asm-sh/mmzone.h b/include/asm-sh/mmzone.h
index 7969f381dff2..2969253c4042 100644
--- a/include/asm-sh/mmzone.h
+++ b/include/asm-sh/mmzone.h
@@ -41,6 +41,8 @@ void __init plat_mem_setup(void);
41 41
42/* arch/sh/kernel/setup.c */ 42/* arch/sh/kernel/setup.c */
43void __init setup_bootmem_allocator(unsigned long start_pfn); 43void __init setup_bootmem_allocator(unsigned long start_pfn);
44void __init __add_active_range(unsigned int nid, unsigned long start_pfn,
45 unsigned long end_pfn);
44 46
45#endif /* __KERNEL__ */ 47#endif /* __KERNEL__ */
46#endif /* __ASM_SH_MMZONE_H */ 48#endif /* __ASM_SH_MMZONE_H */
diff --git a/include/asm-sh/mpc1211/dma.h b/include/asm-sh/mpc1211/dma.h
deleted file mode 100644
index e506d1aaa0d0..000000000000
--- a/include/asm-sh/mpc1211/dma.h
+++ /dev/null
@@ -1,303 +0,0 @@
1/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 */
7
8#ifndef _ASM_MPC1211_DMA_H
9#define _ASM_MPC1211_DMA_H
10
11#include <linux/spinlock.h> /* And spinlocks */
12#include <asm/io.h> /* need byte IO */
13#include <linux/delay.h>
14
15
16#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
17#define dma_outb outb_p
18#else
19#define dma_outb outb
20#endif
21
22#define dma_inb inb
23
24/*
25 * NOTES about DMA transfers:
26 *
27 * controller 1: channels 0-3, byte operations, ports 00-1F
28 * controller 2: channels 4-7, word operations, ports C0-DF
29 *
30 * - ALL registers are 8 bits only, regardless of transfer size
31 * - channel 4 is not used - cascades 1 into 2.
32 * - channels 0-3 are byte - addresses/counts are for physical bytes
33 * - channels 5-7 are word - addresses/counts are for physical words
34 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
35 * - transfer count loaded to registers is 1 less than actual count
36 * - controller 2 offsets are all even (2x offsets for controller 1)
37 * - page registers for 5-7 don't use data bit 0, represent 128K pages
38 * - page registers for 0-3 use bit 0, represent 64K pages
39 *
40 * DMA transfers are limited to the lower 16MB of _physical_ memory.
41 * Note that addresses loaded into registers must be _physical_ addresses,
42 * not logical addresses (which may differ if paging is active).
43 *
44 * Address mapping for channels 0-3:
45 *
46 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
47 * | ... | | ... | | ... |
48 * | ... | | ... | | ... |
49 * | ... | | ... | | ... |
50 * P7 ... P0 A7 ... A0 A7 ... A0
51 * | Page | Addr MSB | Addr LSB | (DMA registers)
52 *
53 * Address mapping for channels 5-7:
54 *
55 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
56 * | ... | \ \ ... \ \ \ ... \ \
57 * | ... | \ \ ... \ \ \ ... \ (not used)
58 * | ... | \ \ ... \ \ \ ... \
59 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
60 * | Page | Addr MSB | Addr LSB | (DMA registers)
61 *
62 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
63 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
64 * the hardware level, so odd-byte transfers aren't possible).
65 *
66 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
67 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
68 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
69 *
70 */
71
72#define MAX_DMA_CHANNELS 8
73
74/* The maximum address that we can perform a DMA transfer to on this platform */
75#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
76
77/* 8237 DMA controllers */
78#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
79#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
80
81/* DMA controller registers */
82#define DMA1_CMD_REG 0x08 /* command register (w) */
83#define DMA1_STAT_REG 0x08 /* status register (r) */
84#define DMA1_REQ_REG 0x09 /* request register (w) */
85#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
86#define DMA1_MODE_REG 0x0B /* mode register (w) */
87#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
88#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
89#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
90#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
91#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
92
93#define DMA2_CMD_REG 0xD0 /* command register (w) */
94#define DMA2_STAT_REG 0xD0 /* status register (r) */
95#define DMA2_REQ_REG 0xD2 /* request register (w) */
96#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
97#define DMA2_MODE_REG 0xD6 /* mode register (w) */
98#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
99#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
100#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
101#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
102#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
103
104#define DMA_ADDR_0 0x00 /* DMA address registers */
105#define DMA_ADDR_1 0x02
106#define DMA_ADDR_2 0x04
107#define DMA_ADDR_3 0x06
108#define DMA_ADDR_4 0xC0
109#define DMA_ADDR_5 0xC4
110#define DMA_ADDR_6 0xC8
111#define DMA_ADDR_7 0xCC
112
113#define DMA_CNT_0 0x01 /* DMA count registers */
114#define DMA_CNT_1 0x03
115#define DMA_CNT_2 0x05
116#define DMA_CNT_3 0x07
117#define DMA_CNT_4 0xC2
118#define DMA_CNT_5 0xC6
119#define DMA_CNT_6 0xCA
120#define DMA_CNT_7 0xCE
121
122#define DMA_PAGE_0 0x87 /* DMA page registers */
123#define DMA_PAGE_1 0x83
124#define DMA_PAGE_2 0x81
125#define DMA_PAGE_3 0x82
126#define DMA_PAGE_5 0x8B
127#define DMA_PAGE_6 0x89
128#define DMA_PAGE_7 0x8A
129
130#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
131#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
132#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
133
134#define DMA_AUTOINIT 0x10
135
136
137extern spinlock_t dma_spin_lock;
138
139static __inline__ unsigned long claim_dma_lock(void)
140{
141 unsigned long flags;
142 spin_lock_irqsave(&dma_spin_lock, flags);
143 return flags;
144}
145
146static __inline__ void release_dma_lock(unsigned long flags)
147{
148 spin_unlock_irqrestore(&dma_spin_lock, flags);
149}
150
151/* enable/disable a specific DMA channel */
152static __inline__ void enable_dma(unsigned int dmanr)
153{
154 if (dmanr<=3)
155 dma_outb(dmanr, DMA1_MASK_REG);
156 else
157 dma_outb(dmanr & 3, DMA2_MASK_REG);
158}
159
160static __inline__ void disable_dma(unsigned int dmanr)
161{
162 if (dmanr<=3)
163 dma_outb(dmanr | 4, DMA1_MASK_REG);
164 else
165 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
166}
167
168/* Clear the 'DMA Pointer Flip Flop'.
169 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
170 * Use this once to initialize the FF to a known state.
171 * After that, keep track of it. :-)
172 * --- In order to do that, the DMA routines below should ---
173 * --- only be used while holding the DMA lock ! ---
174 */
175static __inline__ void clear_dma_ff(unsigned int dmanr)
176{
177 if (dmanr<=3)
178 dma_outb(0, DMA1_CLEAR_FF_REG);
179 else
180 dma_outb(0, DMA2_CLEAR_FF_REG);
181}
182
183/* set mode (above) for a specific DMA channel */
184static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
185{
186 if (dmanr<=3)
187 dma_outb(mode | dmanr, DMA1_MODE_REG);
188 else
189 dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
190}
191
192/* Set only the page register bits of the transfer address.
193 * This is used for successive transfers when we know the contents of
194 * the lower 16 bits of the DMA current address register, but a 64k boundary
195 * may have been crossed.
196 */
197static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
198{
199 switch(dmanr) {
200 case 0:
201 dma_outb( pagenr & 0xff, DMA_PAGE_0);
202 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_0 + 0x400);
203 break;
204 case 1:
205 dma_outb( pagenr & 0xff, DMA_PAGE_1);
206 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_1 + 0x400);
207 break;
208 case 2:
209 dma_outb( pagenr & 0xff, DMA_PAGE_2);
210 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_2 + 0x400);
211 break;
212 case 3:
213 dma_outb( pagenr & 0xff, DMA_PAGE_3);
214 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_3 + 0x400);
215 break;
216 case 5:
217 dma_outb( pagenr & 0xfe, DMA_PAGE_5);
218 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_5 + 0x400);
219 break;
220 case 6:
221 dma_outb( pagenr & 0xfe, DMA_PAGE_6);
222 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_6 + 0x400);
223 break;
224 case 7:
225 dma_outb( pagenr & 0xfe, DMA_PAGE_7);
226 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_7 + 0x400);
227 break;
228 }
229}
230
231
232/* Set transfer address & page bits for specific DMA channel.
233 * Assumes dma flipflop is clear.
234 */
235static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
236{
237 set_dma_page(dmanr, a>>16);
238 if (dmanr <= 3) {
239 dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
240 dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
241 } else {
242 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
243 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
244 }
245}
246
247
248/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
249 * a specific DMA channel.
250 * You must ensure the parameters are valid.
251 * NOTE: from a manual: "the number of transfers is one more
252 * than the initial word count"! This is taken into account.
253 * Assumes dma flip-flop is clear.
254 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
255 */
256static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
257{
258 count--;
259 if (dmanr <= 3) {
260 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
261 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
262 } else {
263 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
264 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
265 }
266}
267
268
269/* Get DMA residue count. After a DMA transfer, this
270 * should return zero. Reading this while a DMA transfer is
271 * still in progress will return unpredictable results.
272 * If called before the channel has been used, it may return 1.
273 * Otherwise, it returns the number of _bytes_ left to transfer.
274 *
275 * Assumes DMA flip-flop is clear.
276 */
277static __inline__ int get_dma_residue(unsigned int dmanr)
278{
279 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
280 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
281
282 /* using short to get 16-bit wrap around */
283 unsigned short count;
284
285 count = 1 + dma_inb(io_port);
286 count += dma_inb(io_port) << 8;
287 return (dmanr<=3)? count : (count<<1);
288}
289
290
291/* These are in kernel/dma.c: */
292extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
293extern void free_dma(unsigned int dmanr); /* release it again */
294
295/* From PCI */
296
297#ifdef CONFIG_PCI
298extern int isa_dma_bridge_buggy;
299#else
300#define isa_dma_bridge_buggy (0)
301#endif
302
303#endif /* _ASM_MPC1211_DMA_H */
diff --git a/include/asm-sh/mpc1211/io.h b/include/asm-sh/mpc1211/io.h
deleted file mode 100644
index 6298370bec2d..000000000000
--- a/include/asm-sh/mpc1211/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * include/asm-sh/mpc1211/io.h
3 *
4 * Copyright 2001 Saito.K & Jeanne
5 *
6 * IO functions for an Interface MPC-1211
7 */
8
9#ifndef _ASM_SH_IO_MPC1211_H
10#define _ASM_SH_IO_MPC1211_H
11
12#include <linux/time.h>
13
14extern int mpc1211_irq_demux(int irq);
15
16extern void init_mpc1211_IRQ(void);
17extern void heartbeat_mpc1211(void);
18
19extern void mpc1211_rtc_gettimeofday(struct timeval *tv);
20extern int mpc1211_rtc_settimeofday(const struct timeval *tv);
21
22#endif /* _ASM_SH_IO_MPC1211_H */
diff --git a/include/asm-sh/mpc1211/keyboard.h b/include/asm-sh/mpc1211/keyboard.h
deleted file mode 100644
index 9020feee7b4c..000000000000
--- a/include/asm-sh/mpc1211/keyboard.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * MPC1211 specific keybord definitions
3 * Taken from the old asm-i386/keybord.h for PC/AT-style definitions
4 * created 3 Nov 1996 by Geert Uytterhoeven.
5 */
6
7#ifdef __KERNEL__
8
9#include <linux/kernel.h>
10#include <linux/ioport.h>
11#include <linux/kd.h>
12#include <linux/pm.h>
13#include <asm/io.h>
14
15#define KEYBOARD_IRQ 1
16#define DISABLE_KBD_DURING_INTERRUPTS 0
17
18extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
19extern int pckbd_getkeycode(unsigned int scancode);
20extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
21 char raw_mode);
22extern char pckbd_unexpected_up(unsigned char keycode);
23extern void pckbd_leds(unsigned char leds);
24extern void pckbd_init_hw(void);
25extern int pckbd_pm_resume(struct pm_dev *, pm_request_t, void *);
26extern pm_callback pm_kbd_request_override;
27
28#define kbd_setkeycode pckbd_setkeycode
29#define kbd_getkeycode pckbd_getkeycode
30#define kbd_translate pckbd_translate
31#define kbd_unexpected_up pckbd_unexpected_up
32#define kbd_leds pckbd_leds
33#define kbd_init_hw pckbd_init_hw
34
35/* resource allocation */
36#define kbd_request_region()
37#define kbd_request_irq(handler) request_irq(KEYBOARD_IRQ, handler, 0, \
38 "keyboard", NULL)
39
40/* How to access the keyboard macros on this platform. */
41#define kbd_read_input() inb(KBD_DATA_REG)
42#define kbd_read_status() inb(KBD_STATUS_REG)
43#define kbd_write_output(val) outb(val, KBD_DATA_REG)
44#define kbd_write_command(val) outb(val, KBD_CNTL_REG)
45
46/* Some stoneage hardware needs delays after some operations. */
47#define kbd_pause() do { } while(0)
48
49/*
50 * Machine specific bits for the PS/2 driver
51 */
52
53#define AUX_IRQ 12
54
55#define aux_request_irq(hand, dev_id) \
56 request_irq(AUX_IRQ, hand, IRQF_SHARED, "PS2 Mouse", dev_id)
57
58#define aux_free_irq(dev_id) free_irq(AUX_IRQ, dev_id)
59
60#endif /* __KERNEL__ */
diff --git a/include/asm-sh/mpc1211/m1543c.h b/include/asm-sh/mpc1211/m1543c.h
deleted file mode 100644
index c95d13236c3b..000000000000
--- a/include/asm-sh/mpc1211/m1543c.h
+++ /dev/null
@@ -1,200 +0,0 @@
1#ifndef __ASM_SH_M1543C_H
2#define __ASM_SH_M1543C_H
3
4/*
5 * linux/include/asm-sh/m1543c.h
6 * Copyright (C) 2001 Nobuhiro Sakawa
7 * M1543C:PCI-ISA Bus Bridge with Super IO Chip support
8 *
9 * from
10 *
11 * linux/include/asm-sh/smc37c93x.h
12 *
13 * Copyright (C) 2000 Kazumoto Kojima
14 *
15 * SMSC 37C93x Super IO Chip support
16 */
17
18/* Default base I/O address */
19#define FDC_PRIMARY_BASE 0x3f0
20#define IDE1_PRIMARY_BASE 0x1f0
21#define IDE1_SECONDARY_BASE 0x170
22#define PARPORT_PRIMARY_BASE 0x378
23#define COM1_PRIMARY_BASE 0x2f8
24#define COM2_PRIMARY_BASE 0x3f8
25#define COM3_PRIMARY_BASE 0x3e8
26#define RTC_PRIMARY_BASE 0x070
27#define KBC_PRIMARY_BASE 0x060
28#define AUXIO_PRIMARY_BASE 0x000 /* XXX */
29#define I8259_M_CR 0x20
30#define I8259_M_MR 0x21
31#define I8259_S_CR 0xa0
32#define I8259_S_MR 0xa1
33
34/* Logical device number */
35#define LDN_FDC 0
36#define LDN_IDE1 1
37#define LDN_IDE2 2
38#define LDN_PARPORT 3
39#define LDN_COM1 4
40#define LDN_COM2 5
41#define LDN_COM3 11
42#define LDN_RTC 6
43#define LDN_KBC 7
44
45/* Configuration port and key */
46#define CONFIG_PORT 0x3f0
47#define INDEX_PORT CONFIG_PORT
48#define DATA_PORT 0x3f1
49#define CONFIG_ENTER1 0x51
50#define CONFIG_ENTER2 0x23
51#define CONFIG_EXIT 0xbb
52
53/* Configuration index */
54#define CURRENT_LDN_INDEX 0x07
55#define POWER_CONTROL_INDEX 0x22
56#define ACTIVATE_INDEX 0x30
57#define IO_BASE_HI_INDEX 0x60
58#define IO_BASE_LO_INDEX 0x61
59#define IRQ_SELECT_INDEX 0x70
60#define PS2_IRQ_INDEX 0x72
61#define DMA_SELECT_INDEX 0x74
62
63/* UART stuff. Only for debugging. */
64/* UART Register */
65
66#define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */
67#define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */
68#define UART_IER 0x2 /* Interrupt Enable Register */
69#define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */
70#define UART_FCR 0x4 /* FIFO Control Register (Write Only) */
71#define UART_LCR 0x6 /* Line Control Register */
72#define UART_MCR 0x8 /* MODEM Control Register */
73#define UART_LSR 0xa /* Line Status Register */
74#define UART_MSR 0xc /* MODEM Status Register */
75#define UART_SCR 0xe /* Scratch Register */
76#define UART_DLL 0x0 /* Divisor Latch (LS) */
77#define UART_DLM 0x2 /* Divisor Latch (MS) */
78
79#ifndef __ASSEMBLY__
80typedef struct uart_reg {
81 volatile __u16 rbr;
82 volatile __u16 ier;
83 volatile __u16 iir;
84 volatile __u16 lcr;
85 volatile __u16 mcr;
86 volatile __u16 lsr;
87 volatile __u16 msr;
88 volatile __u16 scr;
89} uart_reg;
90#endif /* ! __ASSEMBLY__ */
91
92/* Alias for Write Only Register */
93
94#define thr rbr
95#define tcr iir
96
97/* Alias for Divisor Latch Register */
98
99#define dll rbr
100#define dlm ier
101#define fcr iir
102
103/* Interrupt Enable Register */
104
105#define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */
106#define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */
107#define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */
108#define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */
109
110/* Interrupt Ident Register */
111
112#define IIR_IP 0x0100 /* "0" if Interrupt Pending */
113#define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */
114#define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */
115#define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */
116#define IIR_FIFO 0xc000 /* FIFOs enabled */
117
118/* FIFO Control Register */
119
120#define FCR_FEN 0x0100 /* FIFO enable */
121#define FCR_RFRES 0x0200 /* Receiver FIFO reset */
122#define FCR_TFRES 0x0400 /* Transmitter FIFO reset */
123#define FCR_DMA 0x0800 /* DMA mode select */
124#define FCR_RTL 0x4000 /* Receiver triger (LSB) */
125#define FCR_RTM 0x8000 /* Receiver triger (MSB) */
126
127/* Line Control Register */
128
129#define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */
130#define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */
131#define LCR_STB 0x0400 /* Number of Stop Bits */
132#define LCR_PEN 0x0800 /* Parity Enable */
133#define LCR_EPS 0x1000 /* Even Parity Select */
134#define LCR_SP 0x2000 /* Stick Parity */
135#define LCR_SB 0x4000 /* Set Break */
136#define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
137
138/* MODEM Control Register */
139
140#define MCR_DTR 0x0100 /* Data Terminal Ready */
141#define MCR_RTS 0x0200 /* Request to Send */
142#define MCR_OUT1 0x0400 /* Out 1 */
143#define MCR_IRQEN 0x0800 /* IRQ Enable */
144#define MCR_LOOP 0x1000 /* Loop */
145
146/* Line Status Register */
147
148#define LSR_DR 0x0100 /* Data Ready */
149#define LSR_OE 0x0200 /* Overrun Error */
150#define LSR_PE 0x0400 /* Parity Error */
151#define LSR_FE 0x0800 /* Framing Error */
152#define LSR_BI 0x1000 /* Break Interrupt */
153#define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */
154#define LSR_TEMT 0x4000 /* Transmitter Empty */
155#define LSR_FIFOE 0x8000 /* Receiver FIFO error */
156
157/* MODEM Status Register */
158
159#define MSR_DCTS 0x0100 /* Delta Clear to Send */
160#define MSR_DDSR 0x0200 /* Delta Data Set Ready */
161#define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */
162#define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */
163#define MSR_CTS 0x1000 /* Clear to Send */
164#define MSR_DSR 0x2000 /* Data Set Ready */
165#define MSR_RI 0x4000 /* Ring Indicator */
166#define MSR_DCD 0x8000 /* Data Carrier Detect */
167
168/* Baud Rate Divisor */
169
170#define UART_CLK (1843200) /* 1.8432 MHz */
171#define UART_BAUD(x) (UART_CLK / (16 * (x)))
172
173/* RTC register definition */
174#define RTC_SECONDS 0
175#define RTC_SECONDS_ALARM 1
176#define RTC_MINUTES 2
177#define RTC_MINUTES_ALARM 3
178#define RTC_HOURS 4
179#define RTC_HOURS_ALARM 5
180#define RTC_DAY_OF_WEEK 6
181#define RTC_DAY_OF_MONTH 7
182#define RTC_MONTH 8
183#define RTC_YEAR 9
184#define RTC_FREQ_SELECT 10
185# define RTC_UIP 0x80
186# define RTC_DIV_CTL 0x70
187/* This RTC can work under 32.768KHz clock only. */
188# define RTC_OSC_ENABLE 0x20
189# define RTC_OSC_DISABLE 0x00
190#define RTC_CONTROL 11
191# define RTC_SET 0x80
192# define RTC_PIE 0x40
193# define RTC_AIE 0x20
194# define RTC_UIE 0x10
195# define RTC_SQWE 0x08
196# define RTC_DM_BINARY 0x04
197# define RTC_24H 0x02
198# define RTC_DST_EN 0x01
199
200#endif /* __ASM_SH_M1543C_H */
diff --git a/include/asm-sh/mpc1211/mc146818rtc.h b/include/asm-sh/mpc1211/mc146818rtc.h
deleted file mode 100644
index e245f2a3cd78..000000000000
--- a/include/asm-sh/mpc1211/mc146818rtc.h
+++ /dev/null
@@ -1,6 +0,0 @@
1/*
2 * MPC1211 uses PC/AT style RTC definitions.
3 */
4#include <asm-x86/mc146818rtc_32.h>
5
6
diff --git a/include/asm-sh/mpc1211/mpc1211.h b/include/asm-sh/mpc1211/mpc1211.h
deleted file mode 100644
index fa456c3e4e01..000000000000
--- a/include/asm-sh/mpc1211/mpc1211.h
+++ /dev/null
@@ -1,18 +0,0 @@
1#ifndef __ASM_SH_MPC1211_H
2#define __ASM_SH_MPC1211_H
3
4/*
5 * linux/include/asm-sh/mpc1211.h
6 *
7 * Copyright (C) 2001 Saito.K & Jeanne
8 *
9 * Interface MPC-1211 support
10 */
11
12#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
13#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
14
15#define PCIPAR (0xa4000cf8) /* PCI Config address */
16#define PCIPDR (0xa4000cfc) /* PCI Config data */
17
18#endif /* __ASM_SH_MPC1211_H */
diff --git a/include/asm-sh/mpc1211/pci.h b/include/asm-sh/mpc1211/pci.h
deleted file mode 100644
index d9162c5ed76a..000000000000
--- a/include/asm-sh/mpc1211/pci.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * Low-Level PCI Support for MPC-1211
3 *
4 * (c) 2002 Saito.K & Jeanne
5 *
6 */
7
8#ifndef _PCI_MPC1211_H_
9#define _PCI_MPC1211_H_
10
11#include <linux/pci.h>
12
13/* set debug level 4=verbose...1=terse */
14//#define DEBUG_PCI 3
15#undef DEBUG_PCI
16
17#ifdef DEBUG_PCI
18#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }
19#else
20#define PCIDBG(n, x...)
21#endif
22
23/* startup values */
24#define PCI_PROBE_BIOS 1
25#define PCI_PROBE_CONF1 2
26#define PCI_PROBE_CONF2 4
27#define PCI_NO_CHECKS 0x400
28#define PCI_ASSIGN_ROMS 0x1000
29#define PCI_BIOS_IRQ_SCAN 0x2000
30
31/* MPC-1211 Specific Values */
32#define PCIPAR (0xa4000cf8) /* PCI Config address */
33#define PCIPDR (0xa4000cfc) /* PCI Config data */
34
35#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
36#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
37
38#endif /* _PCI_MPC1211_H_ */
diff --git a/include/asm-sh/r7780rp.h b/include/asm-sh/r7780rp.h
index a33838f23a6d..306f7359f7d4 100644
--- a/include/asm-sh/r7780rp.h
+++ b/include/asm-sh/r7780rp.h
@@ -193,8 +193,6 @@
193#define IRQ_SCIF0 (HL_FPGA_IRQ_BASE + 15) 193#define IRQ_SCIF0 (HL_FPGA_IRQ_BASE + 15)
194#define IRQ_SCIF1 (HL_FPGA_IRQ_BASE + 16) 194#define IRQ_SCIF1 (HL_FPGA_IRQ_BASE + 16)
195 195
196unsigned char *highlander_init_irq_r7780mp(void); 196unsigned char *highlander_plat_irq_setup(void);
197unsigned char *highlander_init_irq_r7780rp(void);
198unsigned char *highlander_init_irq_r7785rp(void);
199 197
200#endif /* __ASM_SH_RENESAS_R7780RP */ 198#endif /* __ASM_SH_RENESAS_R7780RP */
diff --git a/include/asm-sh/tlb_64.h b/include/asm-sh/tlb_64.h
index 0308e05fc57b..0a96f3af69e3 100644
--- a/include/asm-sh/tlb_64.h
+++ b/include/asm-sh/tlb_64.h
@@ -56,6 +56,7 @@ static inline void __flush_tlb_slot(unsigned long long slot)
56 __asm__ __volatile__ ("putcfg %0, 0, r63\n" : : "r" (slot)); 56 __asm__ __volatile__ ("putcfg %0, 0, r63\n" : : "r" (slot));
57} 57}
58 58
59#ifdef CONFIG_MMU
59/* arch/sh64/mm/tlb.c */ 60/* arch/sh64/mm/tlb.c */
60int sh64_tlb_init(void); 61int sh64_tlb_init(void);
61unsigned long long sh64_next_free_dtlb_entry(void); 62unsigned long long sh64_next_free_dtlb_entry(void);
@@ -64,6 +65,13 @@ int sh64_put_wired_dtlb_entry(unsigned long long entry);
64void sh64_setup_tlb_slot(unsigned long long config_addr, unsigned long eaddr, 65void sh64_setup_tlb_slot(unsigned long long config_addr, unsigned long eaddr,
65 unsigned long asid, unsigned long paddr); 66 unsigned long asid, unsigned long paddr);
66void sh64_teardown_tlb_slot(unsigned long long config_addr); 67void sh64_teardown_tlb_slot(unsigned long long config_addr);
67 68#else
69#define sh64_tlb_init() do { } while (0)
70#define sh64_next_free_dtlb_entry() (0)
71#define sh64_get_wired_dtlb_entry() (0)
72#define sh64_put_wired_dtlb_entry(entry) do { } while (0)
73#define sh64_setup_tlb_slot(conf, virt, asid, phys) do { } while (0)
74#define sh64_teardown_tlb_slot(addr) do { } while (0)
75#endif /* CONFIG_MMU */
68#endif /* __ASSEMBLY__ */ 76#endif /* __ASSEMBLY__ */
69#endif /* __ASM_SH_TLB_64_H */ 77#endif /* __ASM_SH_TLB_64_H */
diff --git a/include/asm-sh/topology.h b/include/asm-sh/topology.h
index 34cdb28e8f44..95f0085e098a 100644
--- a/include/asm-sh/topology.h
+++ b/include/asm-sh/topology.h
@@ -29,6 +29,17 @@
29 .nr_balance_failed = 0, \ 29 .nr_balance_failed = 0, \
30} 30}
31 31
32#define cpu_to_node(cpu) ((void)(cpu),0)
33#define parent_node(node) ((void)(node),0)
34
35#define node_to_cpumask(node) ((void)node, cpu_online_map)
36#define node_to_first_cpu(node) ((void)(node),0)
37
38#define pcibus_to_node(bus) ((void)(bus), -1)
39#define pcibus_to_cpumask(bus) (pcibus_to_node(bus) == -1 ? \
40 CPU_MASK_ALL : \
41 node_to_cpumask(pcibus_to_node(bus)) \
42 )
32#endif 43#endif
33 44
34#include <asm-generic/topology.h> 45#include <asm-generic/topology.h>
diff --git a/include/asm-sh/uaccess_64.h b/include/asm-sh/uaccess_64.h
index f956b7b316c7..a9b68d094844 100644
--- a/include/asm-sh/uaccess_64.h
+++ b/include/asm-sh/uaccess_64.h
@@ -274,7 +274,9 @@ struct exception_table_entry
274 unsigned long insn, fixup; 274 unsigned long insn, fixup;
275}; 275};
276 276
277#ifdef CONFIG_MMU
277#define ARCH_HAS_SEARCH_EXTABLE 278#define ARCH_HAS_SEARCH_EXTABLE
279#endif
278 280
279/* Returns 0 if exception not found and fixup.unit otherwise. */ 281/* Returns 0 if exception not found and fixup.unit otherwise. */
280extern unsigned long search_exception_table(unsigned long addr); 282extern unsigned long search_exception_table(unsigned long addr);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 13:34:03 -0500