1 files changed, 13 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8a439f0c21f5..fb0538358c34 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3122,6 +3122,19 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
                         return ret;
         }
 
+        /* The display engine is not coherent with the LLC cache on gen6.  As
+         * a result, we make sure that the pinning that is about to occur is
+         * done with uncached PTEs. This is lowest common denominator for all
+         * chipsets.
+         *
+         * However for gen6+, we could do better by using the GFDT bit instead
+         * of uncaching, which would allow us to flush all the LLC-cached data
+         * with that bit in the PTE to main memory with just one PIPE_CONTROL.
+         */
+        ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
+        if (ret)
+                return ret;
+
         /* As the user may map the buffer once pinned in the display plane
          * (e.g. libkms for the bootup splash), we have to ensure that we
          * always use map_and_fenceable for all scanout buffers.