2 files changed, 49 insertions, 0 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 762ae536f909..0f1ad743ccdd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -924,6 +924,19 @@ config ARM_ERRATA_460075
           ACTLR register. Note that setting specific bits in the ACTLR register
           may not be available in non-secure mode.
 
+config PL310_ERRATA_588369
+        bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
+        depends on CACHE_L2X0 && ARCH_OMAP4
+        help
+           The PL310 L2 cache controller implements three types of Clean &
+           Invalidate maintenance operations: by Physical Address
+           (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
+           They are architecturally defined to behave as the execution of a
+           clean operation followed immediately by an invalidate operation,
+           both performing to the same memory location. This functionality
+           is not correctly implemented in PL310 as clean lines are not
+           invalidated as a result of these operations. Note that this errata
+           uses Texas Instrument's secure monitor api.
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 1a14d18e5713..07334632d3e2 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -56,12 +56,42 @@ static inline void l2x0_inv_line(unsigned long addr)
         writel(addr, base + L2X0_INV_LINE_PA);
 }
 
+#ifdef CONFIG_PL310_ERRATA_588369
+static void debug_writel(unsigned long val)
+{
+        extern void omap_smc1(u32 fn, u32 arg);
+
+        /*
+         * Texas Instrument secure monitor api to modify the
+         * PL310 Debug Control Register.
+         */
+        omap_smc1(0x100, val);
+}
+
+static inline void l2x0_flush_line(unsigned long addr)
+{
+        void __iomem *base = l2x0_base;
+
+        /* Clean by PA followed by Invalidate by PA */
+        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
+        writel(addr, base + L2X0_CLEAN_LINE_PA);
+        cache_wait(base + L2X0_INV_LINE_PA, 1);
+        writel(addr, base + L2X0_INV_LINE_PA);
+}
+#else
+
+/* Optimised out for non-errata case */
+static inline void debug_writel(unsigned long val)
+{
+}
+
 static inline void l2x0_flush_line(unsigned long addr)
 {
         void __iomem *base = l2x0_base;
         cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
         writel(addr, base + L2X0_CLEAN_INV_LINE_PA);
 }
+#endif
 
 static inline void l2x0_inv_all(void)
 {
@@ -83,13 +113,17 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
         spin_lock_irqsave(&l2x0_lock, flags);
         if (start & (CACHE_LINE_SIZE - 1)) {
                 start &= ~(CACHE_LINE_SIZE - 1);
+                debug_writel(0x03);
                 l2x0_flush_line(start);
+                debug_writel(0x00);
                 start += CACHE_LINE_SIZE;
         }
 
         if (end & (CACHE_LINE_SIZE - 1)) {
                 end &= ~(CACHE_LINE_SIZE - 1);
+                debug_writel(0x03);
                 l2x0_flush_line(end);
+                debug_writel(0x00);
         }
 
         while (start < end) {
@@ -145,10 +179,12 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
         while (start < end) {
                 unsigned long blk_end = start + min(end - start, 4096UL);
 
+                debug_writel(0x03);
                 while (start < blk_end) {
                         l2x0_flush_line(start);
                         start += CACHE_LINE_SIZE;
                 }
+                debug_writel(0x00);
 
                 if (blk_end < end) {
                         spin_unlock_irqrestore(&l2x0_lock, flags);