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-rw-r--r--Documentation/cgroups/cpuacct.txt2
-rw-r--r--Documentation/cgroups/cpusets.txt2
-rw-r--r--Documentation/sysctl/kernel.txt215
-rw-r--r--arch/ia64/kvm/Kconfig1
-rw-r--r--arch/mips/Kconfig16
-rw-r--r--arch/powerpc/kvm/Kconfig1
-rw-r--r--arch/s390/kvm/Kconfig1
-rw-r--r--arch/sh/Kconfig16
-rw-r--r--arch/tile/kvm/Kconfig1
-rw-r--r--arch/um/sys-i386/Makefile3
-rw-r--r--arch/x86/Kconfig16
-rw-r--r--arch/x86/Kconfig.cpu3
-rw-r--r--arch/x86/boot/Makefile9
-rw-r--r--arch/x86/boot/tools/build.c33
-rw-r--r--arch/x86/include/asm/apb_timer.h22
-rw-r--r--arch/x86/include/asm/cmpxchg_32.h48
-rw-r--r--arch/x86/include/asm/cmpxchg_64.h45
-rw-r--r--arch/x86/include/asm/cpufeature.h2
-rw-r--r--arch/x86/kernel/apb_timer.c409
-rw-r--r--arch/x86/kernel/apic/apic.c22
-rw-r--r--arch/x86/kernel/cpu/bugs.c4
-rw-r--r--arch/x86/kernel/cpu/hypervisor.c4
-rw-r--r--arch/x86/kernel/quirks.c5
-rw-r--r--arch/x86/kernel/relocate_kernel_32.S2
-rw-r--r--arch/x86/kernel/relocate_kernel_64.S2
-rw-r--r--arch/x86/kernel/tsc.c24
-rw-r--r--arch/x86/kvm/Kconfig1
-rw-r--r--drivers/Kconfig2
-rw-r--r--drivers/clocksource/Kconfig3
-rw-r--r--drivers/clocksource/Makefile1
-rw-r--r--drivers/clocksource/dw_apb_timer.c401
-rw-r--r--drivers/virtio/Kconfig3
-rw-r--r--include/linux/dw_apb_timer.h56
-rw-r--r--include/linux/irq.h5
-rw-r--r--init/Kconfig2
-rw-r--r--tools/perf/Makefile5
36 files changed, 806 insertions, 581 deletions
diff --git a/Documentation/cgroups/cpuacct.txt b/Documentation/cgroups/cpuacct.txt
index 9ad85df4b983..9d73cc0cadb9 100644
--- a/Documentation/cgroups/cpuacct.txt
+++ b/Documentation/cgroups/cpuacct.txt
@@ -23,7 +23,7 @@ New accounting groups can be created under the parent group /sys/fs/cgroup.
23 23
24# cd /sys/fs/cgroup 24# cd /sys/fs/cgroup
25# mkdir g1 25# mkdir g1
26# echo $$ > g1 26# echo $$ > g1/tasks
27 27
28The above steps create a new group g1 and move the current shell 28The above steps create a new group g1 and move the current shell
29process (bash) into it. CPU time consumed by this bash and its children 29process (bash) into it. CPU time consumed by this bash and its children
diff --git a/Documentation/cgroups/cpusets.txt b/Documentation/cgroups/cpusets.txt
index 5b0d78e55ccc..5c51ed406d1d 100644
--- a/Documentation/cgroups/cpusets.txt
+++ b/Documentation/cgroups/cpusets.txt
@@ -180,7 +180,7 @@ files describing that cpuset:
180 - cpuset.sched_load_balance flag: if set, load balance within CPUs on that cpuset 180 - cpuset.sched_load_balance flag: if set, load balance within CPUs on that cpuset
181 - cpuset.sched_relax_domain_level: the searching range when migrating tasks 181 - cpuset.sched_relax_domain_level: the searching range when migrating tasks
182 182
183In addition, the root cpuset only has the following file: 183In addition, only the root cpuset has the following file:
184 - cpuset.memory_pressure_enabled flag: compute memory_pressure? 184 - cpuset.memory_pressure_enabled flag: compute memory_pressure?
185 185
186New cpusets are created using the mkdir system call or shell 186New cpusets are created using the mkdir system call or shell
diff --git a/Documentation/sysctl/kernel.txt b/Documentation/sysctl/kernel.txt
index 5e7cb39ad195..1c7fb0a94e28 100644
--- a/Documentation/sysctl/kernel.txt
+++ b/Documentation/sysctl/kernel.txt
@@ -17,23 +17,21 @@ before actually making adjustments.
17 17
18Currently, these files might (depending on your configuration) 18Currently, these files might (depending on your configuration)
19show up in /proc/sys/kernel: 19show up in /proc/sys/kernel:
20- acpi_video_flags 20
21- acct 21- acct
22- acpi_video_flags
23- auto_msgmni
22- bootloader_type [ X86 only ] 24- bootloader_type [ X86 only ]
23- bootloader_version [ X86 only ] 25- bootloader_version [ X86 only ]
24- callhome [ S390 only ] 26- callhome [ S390 only ]
25- auto_msgmni
26- core_pattern 27- core_pattern
27- core_pipe_limit 28- core_pipe_limit
28- core_uses_pid 29- core_uses_pid
29- ctrl-alt-del 30- ctrl-alt-del
30- dentry-state
31- dmesg_restrict 31- dmesg_restrict
32- domainname 32- domainname
33- hostname 33- hostname
34- hotplug 34- hotplug
35- java-appletviewer [ binfmt_java, obsolete ]
36- java-interpreter [ binfmt_java, obsolete ]
37- kptr_restrict 35- kptr_restrict
38- kstack_depth_to_print [ X86 only ] 36- kstack_depth_to_print [ X86 only ]
39- l2cr [ PPC only ] 37- l2cr [ PPC only ]
@@ -48,10 +46,14 @@ show up in /proc/sys/kernel:
48- overflowgid 46- overflowgid
49- overflowuid 47- overflowuid
50- panic 48- panic
49- panic_on_oops
50- panic_on_unrecovered_nmi
51- pid_max 51- pid_max
52- powersave-nap [ PPC only ] 52- powersave-nap [ PPC only ]
53- panic_on_unrecovered_nmi
54- printk 53- printk
54- printk_delay
55- printk_ratelimit
56- printk_ratelimit_burst
55- randomize_va_space 57- randomize_va_space
56- real-root-dev ==> Documentation/initrd.txt 58- real-root-dev ==> Documentation/initrd.txt
57- reboot-cmd [ SPARC only ] 59- reboot-cmd [ SPARC only ]
@@ -62,6 +64,7 @@ show up in /proc/sys/kernel:
62- shmall 64- shmall
63- shmmax [ sysv ipc ] 65- shmmax [ sysv ipc ]
64- shmmni 66- shmmni
67- softlockup_thresh
65- stop-a [ SPARC only ] 68- stop-a [ SPARC only ]
66- sysrq ==> Documentation/sysrq.txt 69- sysrq ==> Documentation/sysrq.txt
67- tainted 70- tainted
@@ -71,15 +74,6 @@ show up in /proc/sys/kernel:
71 74
72============================================================== 75==============================================================
73 76
74acpi_video_flags:
75
76flags
77
78See Doc*/kernel/power/video.txt, it allows mode of video boot to be
79set during run time.
80
81==============================================================
82
83acct: 77acct:
84 78
85highwater lowwater frequency 79highwater lowwater frequency
@@ -97,6 +91,25 @@ valid for 30 seconds.
97 91
98============================================================== 92==============================================================
99 93
94acpi_video_flags:
95
96flags
97
98See Doc*/kernel/power/video.txt, it allows mode of video boot to be
99set during run time.
100
101==============================================================
102
103auto_msgmni:
104
105Enables/Disables automatic recomputing of msgmni upon memory add/remove
106or upon ipc namespace creation/removal (see the msgmni description
107above). Echoing "1" into this file enables msgmni automatic recomputing.
108Echoing "0" turns it off. auto_msgmni default value is 1.
109
110
111==============================================================
112
100bootloader_type: 113bootloader_type:
101 114
102x86 bootloader identification 115x86 bootloader identification
@@ -172,22 +185,24 @@ core_pattern is used to specify a core dumpfile pattern name.
172 185
173core_pipe_limit: 186core_pipe_limit:
174 187
175This sysctl is only applicable when core_pattern is configured to pipe core 188This sysctl is only applicable when core_pattern is configured to pipe
176files to a user space helper (when the first character of core_pattern is a '|', 189core files to a user space helper (when the first character of
177see above). When collecting cores via a pipe to an application, it is 190core_pattern is a '|', see above). When collecting cores via a pipe
178occasionally useful for the collecting application to gather data about the 191to an application, it is occasionally useful for the collecting
179crashing process from its /proc/pid directory. In order to do this safely, the 192application to gather data about the crashing process from its
180kernel must wait for the collecting process to exit, so as not to remove the 193/proc/pid directory. In order to do this safely, the kernel must wait
181crashing processes proc files prematurely. This in turn creates the possibility 194for the collecting process to exit, so as not to remove the crashing
182that a misbehaving userspace collecting process can block the reaping of a 195processes proc files prematurely. This in turn creates the
183crashed process simply by never exiting. This sysctl defends against that. It 196possibility that a misbehaving userspace collecting process can block
184defines how many concurrent crashing processes may be piped to user space 197the reaping of a crashed process simply by never exiting. This sysctl
185applications in parallel. If this value is exceeded, then those crashing 198defends against that. It defines how many concurrent crashing
186processes above that value are noted via the kernel log and their cores are 199processes may be piped to user space applications in parallel. If
187skipped. 0 is a special value, indicating that unlimited processes may be 200this value is exceeded, then those crashing processes above that value
188captured in parallel, but that no waiting will take place (i.e. the collecting 201are noted via the kernel log and their cores are skipped. 0 is a
189process is not guaranteed access to /proc/<crashing pid>/). This value defaults 202special value, indicating that unlimited processes may be captured in
190to 0. 203parallel, but that no waiting will take place (i.e. the collecting
204process is not guaranteed access to /proc/<crashing pid>/). This
205value defaults to 0.
191 206
192============================================================== 207==============================================================
193 208
@@ -218,14 +233,14 @@ to decide what to do with it.
218 233
219dmesg_restrict: 234dmesg_restrict:
220 235
221This toggle indicates whether unprivileged users are prevented from using 236This toggle indicates whether unprivileged users are prevented
222dmesg(8) to view messages from the kernel's log buffer. When 237from using dmesg(8) to view messages from the kernel's log buffer.
223dmesg_restrict is set to (0) there are no restrictions. When 238When dmesg_restrict is set to (0) there are no restrictions. When
224dmesg_restrict is set set to (1), users must have CAP_SYSLOG to use 239dmesg_restrict is set set to (1), users must have CAP_SYSLOG to use
225dmesg(8). 240dmesg(8).
226 241
227The kernel config option CONFIG_SECURITY_DMESG_RESTRICT sets the default 242The kernel config option CONFIG_SECURITY_DMESG_RESTRICT sets the
228value of dmesg_restrict. 243default value of dmesg_restrict.
229 244
230============================================================== 245==============================================================
231 246
@@ -256,13 +271,6 @@ Default value is "/sbin/hotplug".
256 271
257============================================================== 272==============================================================
258 273
259l2cr: (PPC only)
260
261This flag controls the L2 cache of G3 processor boards. If
2620, the cache is disabled. Enabled if nonzero.
263
264==============================================================
265
266kptr_restrict: 274kptr_restrict:
267 275
268This toggle indicates whether restrictions are placed on 276This toggle indicates whether restrictions are placed on
@@ -283,6 +291,13 @@ kernel stack.
283 291
284============================================================== 292==============================================================
285 293
294l2cr: (PPC only)
295
296This flag controls the L2 cache of G3 processor boards. If
2970, the cache is disabled. Enabled if nonzero.
298
299==============================================================
300
286modules_disabled: 301modules_disabled:
287 302
288A toggle value indicating if modules are allowed to be loaded 303A toggle value indicating if modules are allowed to be loaded
@@ -293,6 +308,21 @@ to false.
293 308
294============================================================== 309==============================================================
295 310
311nmi_watchdog:
312
313Enables/Disables the NMI watchdog on x86 systems. When the value is
314non-zero the NMI watchdog is enabled and will continuously test all
315online cpus to determine whether or not they are still functioning
316properly. Currently, passing "nmi_watchdog=" parameter at boot time is
317required for this function to work.
318
319If LAPIC NMI watchdog method is in use (nmi_watchdog=2 kernel
320parameter), the NMI watchdog shares registers with oprofile. By
321disabling the NMI watchdog, oprofile may have more registers to
322utilize.
323
324==============================================================
325
296osrelease, ostype & version: 326osrelease, ostype & version:
297 327
298# cat osrelease 328# cat osrelease
@@ -312,10 +342,10 @@ The only way to tune these values is to rebuild the kernel :-)
312 342
313overflowgid & overflowuid: 343overflowgid & overflowuid:
314 344
315if your architecture did not always support 32-bit UIDs (i.e. arm, i386, 345if your architecture did not always support 32-bit UIDs (i.e. arm,
316m68k, sh, and sparc32), a fixed UID and GID will be returned to 346i386, m68k, sh, and sparc32), a fixed UID and GID will be returned to
317applications that use the old 16-bit UID/GID system calls, if the actual 347applications that use the old 16-bit UID/GID system calls, if the
318UID or GID would exceed 65535. 348actual UID or GID would exceed 65535.
319 349
320These sysctls allow you to change the value of the fixed UID and GID. 350These sysctls allow you to change the value of the fixed UID and GID.
321The default is 65534. 351The default is 65534.
@@ -324,9 +354,22 @@ The default is 65534.
324 354
325panic: 355panic:
326 356
327The value in this file represents the number of seconds the 357The value in this file represents the number of seconds the kernel
328kernel waits before rebooting on a panic. When you use the 358waits before rebooting on a panic. When you use the software watchdog,
329software watchdog, the recommended setting is 60. 359the recommended setting is 60.
360
361==============================================================
362
363panic_on_unrecovered_nmi:
364
365The default Linux behaviour on an NMI of either memory or unknown is
366to continue operation. For many environments such as scientific
367computing it is preferable that the box is taken out and the error
368dealt with than an uncorrected parity/ECC error get propagated.
369
370A small number of systems do generate NMI's for bizarre random reasons
371such as power management so the default is off. That sysctl works like
372the existing panic controls already in that directory.
330 373
331============================================================== 374==============================================================
332 375
@@ -376,6 +419,14 @@ the different loglevels.
376 419
377============================================================== 420==============================================================
378 421
422printk_delay:
423
424Delay each printk message in printk_delay milliseconds
425
426Value from 0 - 10000 is allowed.
427
428==============================================================
429
379printk_ratelimit: 430printk_ratelimit:
380 431
381Some warning messages are rate limited. printk_ratelimit specifies 432Some warning messages are rate limited. printk_ratelimit specifies
@@ -395,15 +446,7 @@ send before ratelimiting kicks in.
395 446
396============================================================== 447==============================================================
397 448
398printk_delay: 449randomize_va_space:
399
400Delay each printk message in printk_delay milliseconds
401
402Value from 0 - 10000 is allowed.
403
404==============================================================
405
406randomize-va-space:
407 450
408This option can be used to select the type of process address 451This option can be used to select the type of process address
409space randomization that is used in the system, for architectures 452space randomization that is used in the system, for architectures
@@ -466,11 +509,11 @@ are doing anyway :)
466 509
467============================================================== 510==============================================================
468 511
469shmmax: 512shmmax:
470 513
471This value can be used to query and set the run time limit 514This value can be used to query and set the run time limit
472on the maximum shared memory segment size that can be created. 515on the maximum shared memory segment size that can be created.
473Shared memory segments up to 1Gb are now supported in the 516Shared memory segments up to 1Gb are now supported in the
474kernel. This value defaults to SHMMAX. 517kernel. This value defaults to SHMMAX.
475 518
476============================================================== 519==============================================================
@@ -484,7 +527,7 @@ tunable to zero will disable the softlockup detection altogether.
484 527
485============================================================== 528==============================================================
486 529
487tainted: 530tainted:
488 531
489Non-zero if the kernel has been tainted. Numeric values, which 532Non-zero if the kernel has been tainted. Numeric values, which
490can be ORed together: 533can be ORed together:
@@ -509,49 +552,11 @@ can be ORed together:
509 552
510============================================================== 553==============================================================
511 554
512auto_msgmni:
513
514Enables/Disables automatic recomputing of msgmni upon memory add/remove or
515upon ipc namespace creation/removal (see the msgmni description above).
516Echoing "1" into this file enables msgmni automatic recomputing.
517Echoing "0" turns it off.
518auto_msgmni default value is 1.
519
520==============================================================
521
522nmi_watchdog:
523
524Enables/Disables the NMI watchdog on x86 systems. When the value is non-zero
525the NMI watchdog is enabled and will continuously test all online cpus to
526determine whether or not they are still functioning properly. Currently,
527passing "nmi_watchdog=" parameter at boot time is required for this function
528to work.
529
530If LAPIC NMI watchdog method is in use (nmi_watchdog=2 kernel parameter), the
531NMI watchdog shares registers with oprofile. By disabling the NMI watchdog,
532oprofile may have more registers to utilize.
533
534==============================================================
535
536unknown_nmi_panic: 555unknown_nmi_panic:
537 556
538The value in this file affects behavior of handling NMI. When the value is 557The value in this file affects behavior of handling NMI. When the
539non-zero, unknown NMI is trapped and then panic occurs. At that time, kernel 558value is non-zero, unknown NMI is trapped and then panic occurs. At
540debugging information is displayed on console. 559that time, kernel debugging information is displayed on console.
541
542NMI switch that most IA32 servers have fires unknown NMI up, for example.
543If a system hangs up, try pressing the NMI switch.
544
545==============================================================
546
547panic_on_unrecovered_nmi:
548
549The default Linux behaviour on an NMI of either memory or unknown is to continue
550operation. For many environments such as scientific computing it is preferable
551that the box is taken out and the error dealt with than an uncorrected
552parity/ECC error get propogated.
553
554A small number of systems do generate NMI's for bizarre random reasons such as
555power management so the default is off. That sysctl works like the existing
556panic controls already in that directory.
557 560
561NMI switch that most IA32 servers have fires unknown NMI up, for
562example. If a system hangs up, try pressing the NMI switch.
diff --git a/arch/ia64/kvm/Kconfig b/arch/ia64/kvm/Kconfig
index fa4d1e59deb0..9806e55f91be 100644
--- a/arch/ia64/kvm/Kconfig
+++ b/arch/ia64/kvm/Kconfig
@@ -49,6 +49,5 @@ config KVM_INTEL
49 extensions. 49 extensions.
50 50
51source drivers/vhost/Kconfig 51source drivers/vhost/Kconfig
52source drivers/virtio/Kconfig
53 52
54endif # VIRTUALIZATION 53endif # VIRTUALIZATION
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 6cb60adb7b30..177cdaf83564 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2493,20 +2493,4 @@ source "security/Kconfig"
2493 2493
2494source "crypto/Kconfig" 2494source "crypto/Kconfig"
2495 2495
2496menuconfig VIRTUALIZATION
2497 bool "Virtualization"
2498 default n
2499 ---help---
2500 Say Y here to get to see options for using your Linux host to run other
2501 operating systems inside virtual machines (guests).
2502 This option alone does not add any kernel code.
2503
2504 If you say N, all options in this submenu will be skipped and disabled.
2505
2506if VIRTUALIZATION
2507
2508source drivers/virtio/Kconfig
2509
2510endif # VIRTUALIZATION
2511
2512source "lib/Kconfig" 2496source "lib/Kconfig"
diff --git a/arch/powerpc/kvm/Kconfig b/arch/powerpc/kvm/Kconfig
index b7baff78f90c..105b6918b23e 100644
--- a/arch/powerpc/kvm/Kconfig
+++ b/arch/powerpc/kvm/Kconfig
@@ -99,6 +99,5 @@ config KVM_E500
99 If unsure, say N. 99 If unsure, say N.
100 100
101source drivers/vhost/Kconfig 101source drivers/vhost/Kconfig
102source drivers/virtio/Kconfig
103 102
104endif # VIRTUALIZATION 103endif # VIRTUALIZATION
diff --git a/arch/s390/kvm/Kconfig b/arch/s390/kvm/Kconfig
index f66a1bdbb61d..a21634173a66 100644
--- a/arch/s390/kvm/Kconfig
+++ b/arch/s390/kvm/Kconfig
@@ -37,6 +37,5 @@ config KVM
37# OK, it's a little counter-intuitive to do this, but it puts it neatly under 37# OK, it's a little counter-intuitive to do this, but it puts it neatly under
38# the virtualization menu. 38# the virtualization menu.
39source drivers/vhost/Kconfig 39source drivers/vhost/Kconfig
40source drivers/virtio/Kconfig
41 40
42endif # VIRTUALIZATION 41endif # VIRTUALIZATION
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index bbdeb48bbf8e..748ff1920068 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -897,20 +897,4 @@ source "security/Kconfig"
897 897
898source "crypto/Kconfig" 898source "crypto/Kconfig"
899 899
900menuconfig VIRTUALIZATION
901 bool "Virtualization"
902 default n
903 ---help---
904 Say Y here to get to see options for using your Linux host to run other
905 operating systems inside virtual machines (guests).
906 This option alone does not add any kernel code.
907
908 If you say N, all options in this submenu will be skipped and disabled.
909
910if VIRTUALIZATION
911
912source drivers/virtio/Kconfig
913
914endif # VIRTUALIZATION
915
916source "lib/Kconfig" 900source "lib/Kconfig"
diff --git a/arch/tile/kvm/Kconfig b/arch/tile/kvm/Kconfig
index b88f9c047781..669fcdba31ea 100644
--- a/arch/tile/kvm/Kconfig
+++ b/arch/tile/kvm/Kconfig
@@ -33,6 +33,5 @@ config KVM
33 If unsure, say N. 33 If unsure, say N.
34 34
35source drivers/vhost/Kconfig 35source drivers/vhost/Kconfig
36source drivers/virtio/Kconfig
37 36
38endif # VIRTUALIZATION 37endif # VIRTUALIZATION
diff --git a/arch/um/sys-i386/Makefile b/arch/um/sys-i386/Makefile
index 15587ed9a361..87b659dadf3f 100644
--- a/arch/um/sys-i386/Makefile
+++ b/arch/um/sys-i386/Makefile
@@ -8,7 +8,8 @@ obj-y = bug.o bugs.o checksum.o delay.o fault.o ksyms.o ldt.o ptrace.o \
8 8
9obj-$(CONFIG_BINFMT_ELF) += elfcore.o 9obj-$(CONFIG_BINFMT_ELF) += elfcore.o
10 10
11subarch-obj-y = lib/rwsem.o lib/string_32.o 11subarch-obj-y = lib/string_32.o
12subarch-obj-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += lib/rwsem.o
12subarch-obj-$(CONFIG_HIGHMEM) += mm/highmem_32.o 13subarch-obj-$(CONFIG_HIGHMEM) += mm/highmem_32.o
13subarch-obj-$(CONFIG_MODULES) += kernel/module.o 14subarch-obj-$(CONFIG_MODULES) += kernel/module.o
14 15
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5f60ea190d5b..b2127544fbe7 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -390,12 +390,21 @@ config X86_INTEL_CE
390 This option compiles in support for the CE4100 SOC for settop 390 This option compiles in support for the CE4100 SOC for settop
391 boxes and media devices. 391 boxes and media devices.
392 392
393config X86_INTEL_MID
394 bool "Intel MID platform support"
395 depends on X86_32
396 depends on X86_EXTENDED_PLATFORM
397 ---help---
398 Select to build a kernel capable of supporting Intel MID platform
399 systems which do not have the PCI legacy interfaces (Moorestown,
400 Medfield). If you are building for a PC class system say N here.
401
402if X86_INTEL_MID
403
393config X86_MRST 404config X86_MRST
394 bool "Moorestown MID platform" 405 bool "Moorestown MID platform"
395 depends on PCI 406 depends on PCI
396 depends on PCI_GOANY 407 depends on PCI_GOANY
397 depends on X86_32
398 depends on X86_EXTENDED_PLATFORM
399 depends on X86_IO_APIC 408 depends on X86_IO_APIC
400 select APB_TIMER 409 select APB_TIMER
401 select I2C 410 select I2C
@@ -410,6 +419,8 @@ config X86_MRST
410 nor standard legacy replacement devices/features. e.g. Moorestown does 419 nor standard legacy replacement devices/features. e.g. Moorestown does
411 not contain i8259, i8254, HPET, legacy BIOS, most of the io ports. 420 not contain i8259, i8254, HPET, legacy BIOS, most of the io ports.
412 421
422endif
423
413config X86_RDC321X 424config X86_RDC321X
414 bool "RDC R-321x SoC" 425 bool "RDC R-321x SoC"
415 depends on X86_32 426 depends on X86_32
@@ -623,6 +634,7 @@ config HPET_EMULATE_RTC
623config APB_TIMER 634config APB_TIMER
624 def_bool y if MRST 635 def_bool y if MRST
625 prompt "Langwell APB Timer Support" if X86_MRST 636 prompt "Langwell APB Timer Support" if X86_MRST
637 select DW_APB_TIMER
626 help 638 help
627 APB timer is the replacement for 8254, HPET on X86 MID platforms. 639 APB timer is the replacement for 8254, HPET on X86 MID platforms.
628 The APBT provides a stable time base on SMP 640 The APBT provides a stable time base on SMP
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 6a7cfdf8ff69..e3ca7e0d858c 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -312,6 +312,9 @@ config X86_CMPXCHG
312config CMPXCHG_LOCAL 312config CMPXCHG_LOCAL
313 def_bool X86_64 || (X86_32 && !M386) 313 def_bool X86_64 || (X86_32 && !M386)
314 314
315config CMPXCHG_DOUBLE
316 def_bool y
317
315config X86_L1_CACHE_SHIFT 318config X86_L1_CACHE_SHIFT
316 int 319 int
317 default "7" if MPENTIUM4 || MPSC 320 default "7" if MPENTIUM4 || MPSC
diff --git a/arch/x86/boot/Makefile b/arch/x86/boot/Makefile
index f7cb086b4add..95365a82b6a0 100644
--- a/arch/x86/boot/Makefile
+++ b/arch/x86/boot/Makefile
@@ -9,12 +9,6 @@
9# Changed by many, many contributors over the years. 9# Changed by many, many contributors over the years.
10# 10#
11 11
12# ROOT_DEV specifies the default root-device when making the image.
13# This can be either FLOPPY, CURRENT, /dev/xxxx or empty, in which case
14# the default of FLOPPY is used by 'build'.
15
16ROOT_DEV := CURRENT
17
18# If you want to preset the SVGA mode, uncomment the next line and 12# If you want to preset the SVGA mode, uncomment the next line and
19# set SVGA_MODE to whatever number you want. 13# set SVGA_MODE to whatever number you want.
20# Set it to -DSVGA_MODE=NORMAL_VGA if you just want the EGA/VGA mode. 14# Set it to -DSVGA_MODE=NORMAL_VGA if you just want the EGA/VGA mode.
@@ -75,8 +69,7 @@ GCOV_PROFILE := n
75$(obj)/bzImage: asflags-y := $(SVGA_MODE) 69$(obj)/bzImage: asflags-y := $(SVGA_MODE)
76 70
77quiet_cmd_image = BUILD $@ 71quiet_cmd_image = BUILD $@
78cmd_image = $(obj)/tools/build $(obj)/setup.bin $(obj)/vmlinux.bin \ 72cmd_image = $(obj)/tools/build $(obj)/setup.bin $(obj)/vmlinux.bin > $@
79 $(ROOT_DEV) > $@
80 73
81$(obj)/bzImage: $(obj)/setup.bin $(obj)/vmlinux.bin $(obj)/tools/build FORCE 74$(obj)/bzImage: $(obj)/setup.bin $(obj)/vmlinux.bin $(obj)/tools/build FORCE
82 $(call if_changed,image) 75 $(call if_changed,image)
diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c
index ee3a4ea923ac..fdc60a0b3c20 100644
--- a/arch/x86/boot/tools/build.c
+++ b/arch/x86/boot/tools/build.c
@@ -130,7 +130,7 @@ static void die(const char * str, ...)
130 130
131static void usage(void) 131static void usage(void)
132{ 132{
133 die("Usage: build setup system [rootdev] [> image]"); 133 die("Usage: build setup system [> image]");
134} 134}
135 135
136int main(int argc, char ** argv) 136int main(int argc, char ** argv)
@@ -138,39 +138,14 @@ int main(int argc, char ** argv)
138 unsigned int i, sz, setup_sectors; 138 unsigned int i, sz, setup_sectors;
139 int c; 139 int c;
140 u32 sys_size; 140 u32 sys_size;
141 u8 major_root, minor_root;
142 struct stat sb; 141 struct stat sb;
143 FILE *file; 142 FILE *file;
144 int fd; 143 int fd;
145 void *kernel; 144 void *kernel;
146 u32 crc = 0xffffffffUL; 145 u32 crc = 0xffffffffUL;
147 146
148 if ((argc < 3) || (argc > 4)) 147 if (argc != 3)
149 usage(); 148 usage();
150 if (argc > 3) {
151 if (!strcmp(argv[3], "CURRENT")) {
152 if (stat("/", &sb)) {
153 perror("/");
154 die("Couldn't stat /");
155 }
156 major_root = major(sb.st_dev);
157 minor_root = minor(sb.st_dev);
158 } else if (strcmp(argv[3], "FLOPPY")) {
159 if (stat(argv[3], &sb)) {
160 perror(argv[3]);
161 die("Couldn't stat root device.");
162 }
163 major_root = major(sb.st_rdev);
164 minor_root = minor(sb.st_rdev);
165 } else {
166 major_root = 0;
167 minor_root = 0;
168 }
169 } else {
170 major_root = DEFAULT_MAJOR_ROOT;
171 minor_root = DEFAULT_MINOR_ROOT;
172 }
173 fprintf(stderr, "Root device is (%d, %d)\n", major_root, minor_root);
174 149
175 /* Copy the setup code */ 150 /* Copy the setup code */
176 file = fopen(argv[1], "r"); 151 file = fopen(argv[1], "r");
@@ -193,8 +168,8 @@ int main(int argc, char ** argv)
193 memset(buf+c, 0, i-c); 168 memset(buf+c, 0, i-c);
194 169
195 /* Set the default root device */ 170 /* Set the default root device */
196 buf[508] = minor_root; 171 buf[508] = DEFAULT_MINOR_ROOT;
197 buf[509] = major_root; 172 buf[509] = DEFAULT_MAJOR_ROOT;
198 173
199 fprintf(stderr, "Setup is %d bytes (padded to %d bytes).\n", c, i); 174 fprintf(stderr, "Setup is %d bytes (padded to %d bytes).\n", c, i);
200 175
diff --git a/arch/x86/include/asm/apb_timer.h b/arch/x86/include/asm/apb_timer.h
index 082cf8184935..0acbac299e49 100644
--- a/arch/x86/include/asm/apb_timer.h
+++ b/arch/x86/include/asm/apb_timer.h
@@ -18,24 +18,6 @@
18 18
19#ifdef CONFIG_APB_TIMER 19#ifdef CONFIG_APB_TIMER
20 20
21/* Langwell DW APB timer registers */
22#define APBTMR_N_LOAD_COUNT 0x00
23#define APBTMR_N_CURRENT_VALUE 0x04
24#define APBTMR_N_CONTROL 0x08
25#define APBTMR_N_EOI 0x0c
26#define APBTMR_N_INT_STATUS 0x10
27
28#define APBTMRS_INT_STATUS 0xa0
29#define APBTMRS_EOI 0xa4
30#define APBTMRS_RAW_INT_STATUS 0xa8
31#define APBTMRS_COMP_VERSION 0xac
32#define APBTMRS_REG_SIZE 0x14
33
34/* register bits */
35#define APBTMR_CONTROL_ENABLE (1<<0)
36#define APBTMR_CONTROL_MODE_PERIODIC (1<<1) /*1: periodic 0:free running */
37#define APBTMR_CONTROL_INT (1<<2)
38
39/* default memory mapped register base */ 21/* default memory mapped register base */
40#define LNW_SCU_ADDR 0xFF100000 22#define LNW_SCU_ADDR 0xFF100000
41#define LNW_EXT_TIMER_OFFSET 0x1B800 23#define LNW_EXT_TIMER_OFFSET 0x1B800
@@ -43,8 +25,8 @@
43#define LNW_EXT_TIMER_PGOFFSET 0x800 25#define LNW_EXT_TIMER_PGOFFSET 0x800
44 26
45/* APBT clock speed range from PCLK to fabric base, 25-100MHz */ 27/* APBT clock speed range from PCLK to fabric base, 25-100MHz */
46#define APBT_MAX_FREQ 50 28#define APBT_MAX_FREQ 50000000
47#define APBT_MIN_FREQ 1 29#define APBT_MIN_FREQ 1000000
48#define APBT_MMAP_SIZE 1024 30#define APBT_MMAP_SIZE 1024
49 31
50#define APBT_DEV_USED 1 32#define APBT_DEV_USED 1
diff --git a/arch/x86/include/asm/cmpxchg_32.h b/arch/x86/include/asm/cmpxchg_32.h
index 284a6e8f7ce1..3deb7250624c 100644
--- a/arch/x86/include/asm/cmpxchg_32.h
+++ b/arch/x86/include/asm/cmpxchg_32.h
@@ -280,4 +280,52 @@ static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
280 280
281#endif 281#endif
282 282
283#define cmpxchg8b(ptr, o1, o2, n1, n2) \
284({ \
285 char __ret; \
286 __typeof__(o2) __dummy; \
287 __typeof__(*(ptr)) __old1 = (o1); \
288 __typeof__(o2) __old2 = (o2); \
289 __typeof__(*(ptr)) __new1 = (n1); \
290 __typeof__(o2) __new2 = (n2); \
291 asm volatile(LOCK_PREFIX "cmpxchg8b %2; setz %1" \
292 : "=d"(__dummy), "=a" (__ret), "+m" (*ptr)\
293 : "a" (__old1), "d"(__old2), \
294 "b" (__new1), "c" (__new2) \
295 : "memory"); \
296 __ret; })
297
298
299#define cmpxchg8b_local(ptr, o1, o2, n1, n2) \
300({ \
301 char __ret; \
302 __typeof__(o2) __dummy; \
303 __typeof__(*(ptr)) __old1 = (o1); \
304 __typeof__(o2) __old2 = (o2); \
305 __typeof__(*(ptr)) __new1 = (n1); \
306 __typeof__(o2) __new2 = (n2); \
307 asm volatile("cmpxchg8b %2; setz %1" \
308 : "=d"(__dummy), "=a"(__ret), "+m" (*ptr)\
309 : "a" (__old), "d"(__old2), \
310 "b" (__new1), "c" (__new2), \
311 : "memory"); \
312 __ret; })
313
314
315#define cmpxchg_double(ptr, o1, o2, n1, n2) \
316({ \
317 BUILD_BUG_ON(sizeof(*(ptr)) != 4); \
318 VM_BUG_ON((unsigned long)(ptr) % 8); \
319 cmpxchg8b((ptr), (o1), (o2), (n1), (n2)); \
320})
321
322#define cmpxchg_double_local(ptr, o1, o2, n1, n2) \
323({ \
324 BUILD_BUG_ON(sizeof(*(ptr)) != 4); \
325 VM_BUG_ON((unsigned long)(ptr) % 8); \
326 cmpxchg16b_local((ptr), (o1), (o2), (n1), (n2)); \
327})
328
329#define system_has_cmpxchg_double() cpu_has_cx8
330
283#endif /* _ASM_X86_CMPXCHG_32_H */ 331#endif /* _ASM_X86_CMPXCHG_32_H */
diff --git a/arch/x86/include/asm/cmpxchg_64.h b/arch/x86/include/asm/cmpxchg_64.h
index 423ae58aa020..7cf5c0a24434 100644
--- a/arch/x86/include/asm/cmpxchg_64.h
+++ b/arch/x86/include/asm/cmpxchg_64.h
@@ -151,4 +151,49 @@ extern void __cmpxchg_wrong_size(void);
151 cmpxchg_local((ptr), (o), (n)); \ 151 cmpxchg_local((ptr), (o), (n)); \
152}) 152})
153 153
154#define cmpxchg16b(ptr, o1, o2, n1, n2) \
155({ \
156 char __ret; \
157 __typeof__(o2) __junk; \
158 __typeof__(*(ptr)) __old1 = (o1); \
159 __typeof__(o2) __old2 = (o2); \
160 __typeof__(*(ptr)) __new1 = (n1); \
161 __typeof__(o2) __new2 = (n2); \
162 asm volatile(LOCK_PREFIX "cmpxchg16b %2;setz %1" \
163 : "=d"(__junk), "=a"(__ret), "+m" (*ptr) \
164 : "b"(__new1), "c"(__new2), \
165 "a"(__old1), "d"(__old2)); \
166 __ret; })
167
168
169#define cmpxchg16b_local(ptr, o1, o2, n1, n2) \
170({ \
171 char __ret; \
172 __typeof__(o2) __junk; \
173 __typeof__(*(ptr)) __old1 = (o1); \
174 __typeof__(o2) __old2 = (o2); \
175 __typeof__(*(ptr)) __new1 = (n1); \
176 __typeof__(o2) __new2 = (n2); \
177 asm volatile("cmpxchg16b %2;setz %1" \
178 : "=d"(__junk), "=a"(__ret), "+m" (*ptr) \
179 : "b"(__new1), "c"(__new2), \
180 "a"(__old1), "d"(__old2)); \
181 __ret; })
182
183#define cmpxchg_double(ptr, o1, o2, n1, n2) \
184({ \
185 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
186 VM_BUG_ON((unsigned long)(ptr) % 16); \
187 cmpxchg16b((ptr), (o1), (o2), (n1), (n2)); \
188})
189
190#define cmpxchg_double_local(ptr, o1, o2, n1, n2) \
191({ \
192 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
193 VM_BUG_ON((unsigned long)(ptr) % 16); \
194 cmpxchg16b_local((ptr), (o1), (o2), (n1), (n2)); \
195})
196
197#define system_has_cmpxchg_double() cpu_has_cx16
198
154#endif /* _ASM_X86_CMPXCHG_64_H */ 199#endif /* _ASM_X86_CMPXCHG_64_H */
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 9929b35929ff..4258aac99a6e 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -288,6 +288,8 @@ extern const char * const x86_power_flags[32];
288#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) 288#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)
289#define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ) 289#define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ)
290#define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE) 290#define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
291#define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8)
292#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
291 293
292#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) 294#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
293# define cpu_has_invlpg 1 295# define cpu_has_invlpg 1
diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c
index 2b6630d75e17..afdc3f756dea 100644
--- a/arch/x86/kernel/apb_timer.c
+++ b/arch/x86/kernel/apb_timer.c
@@ -27,15 +27,12 @@
27 * timer, but by default APB timer has higher rating than local APIC timers. 27 * timer, but by default APB timer has higher rating than local APIC timers.
28 */ 28 */
29 29
30#include <linux/clocksource.h>
31#include <linux/clockchips.h>
32#include <linux/delay.h> 30#include <linux/delay.h>
31#include <linux/dw_apb_timer.h>
33#include <linux/errno.h> 32#include <linux/errno.h>
34#include <linux/init.h> 33#include <linux/init.h>
35#include <linux/sysdev.h>
36#include <linux/slab.h> 34#include <linux/slab.h>
37#include <linux/pm.h> 35#include <linux/pm.h>
38#include <linux/pci.h>
39#include <linux/sfi.h> 36#include <linux/sfi.h>
40#include <linux/interrupt.h> 37#include <linux/interrupt.h>
41#include <linux/cpu.h> 38#include <linux/cpu.h>
@@ -46,75 +43,46 @@
46#include <asm/mrst.h> 43#include <asm/mrst.h>
47#include <asm/time.h> 44#include <asm/time.h>
48 45
49#define APBT_MASK CLOCKSOURCE_MASK(32)
50#define APBT_SHIFT 22
51#define APBT_CLOCKEVENT_RATING 110 46#define APBT_CLOCKEVENT_RATING 110
52#define APBT_CLOCKSOURCE_RATING 250 47#define APBT_CLOCKSOURCE_RATING 250
53#define APBT_MIN_DELTA_USEC 200
54 48
55#define EVT_TO_APBT_DEV(evt) container_of(evt, struct apbt_dev, evt)
56#define APBT_CLOCKEVENT0_NUM (0) 49#define APBT_CLOCKEVENT0_NUM (0)
57#define APBT_CLOCKEVENT1_NUM (1)
58#define APBT_CLOCKSOURCE_NUM (2) 50#define APBT_CLOCKSOURCE_NUM (2)
59 51
60static unsigned long apbt_address; 52static phys_addr_t apbt_address;
61static int apb_timer_block_enabled; 53static int apb_timer_block_enabled;
62static void __iomem *apbt_virt_address; 54static void __iomem *apbt_virt_address;
63static int phy_cs_timer_id;
64 55
65/* 56/*
66 * Common DW APB timer info 57 * Common DW APB timer info
67 */ 58 */
68static uint64_t apbt_freq; 59static unsigned long apbt_freq;
69
70static void apbt_set_mode(enum clock_event_mode mode,
71 struct clock_event_device *evt);
72static int apbt_next_event(unsigned long delta,
73 struct clock_event_device *evt);
74static cycle_t apbt_read_clocksource(struct clocksource *cs);
75static void apbt_restart_clocksource(struct clocksource *cs);
76 60
77struct apbt_dev { 61struct apbt_dev {
78 struct clock_event_device evt; 62 struct dw_apb_clock_event_device *timer;
79 unsigned int num; 63 unsigned int num;
80 int cpu; 64 int cpu;
81 unsigned int irq; 65 unsigned int irq;
82 unsigned int tick; 66 char name[10];
83 unsigned int count;
84 unsigned int flags;
85 char name[10];
86}; 67};
87 68
88static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev); 69static struct dw_apb_clocksource *clocksource_apbt;
89 70
90#ifdef CONFIG_SMP 71static inline void __iomem *adev_virt_addr(struct apbt_dev *adev)
91static unsigned int apbt_num_timers_used;
92static struct apbt_dev *apbt_devs;
93#endif
94
95static inline unsigned long apbt_readl_reg(unsigned long a)
96{ 72{
97 return readl(apbt_virt_address + a); 73 return apbt_virt_address + adev->num * APBTMRS_REG_SIZE;
98} 74}
99 75
100static inline void apbt_writel_reg(unsigned long d, unsigned long a) 76static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
101{
102 writel(d, apbt_virt_address + a);
103}
104
105static inline unsigned long apbt_readl(int n, unsigned long a)
106{
107 return readl(apbt_virt_address + a + n * APBTMRS_REG_SIZE);
108}
109 77
110static inline void apbt_writel(int n, unsigned long d, unsigned long a) 78#ifdef CONFIG_SMP
111{ 79static unsigned int apbt_num_timers_used;
112 writel(d, apbt_virt_address + a + n * APBTMRS_REG_SIZE); 80#endif
113}
114 81
115static inline void apbt_set_mapping(void) 82static inline void apbt_set_mapping(void)
116{ 83{
117 struct sfi_timer_table_entry *mtmr; 84 struct sfi_timer_table_entry *mtmr;
85 int phy_cs_timer_id = 0;
118 86
119 if (apbt_virt_address) { 87 if (apbt_virt_address) {
120 pr_debug("APBT base already mapped\n"); 88 pr_debug("APBT base already mapped\n");
@@ -126,21 +94,18 @@ static inline void apbt_set_mapping(void)
126 APBT_CLOCKEVENT0_NUM); 94 APBT_CLOCKEVENT0_NUM);
127 return; 95 return;
128 } 96 }
129 apbt_address = (unsigned long)mtmr->phys_addr; 97 apbt_address = (phys_addr_t)mtmr->phys_addr;
130 if (!apbt_address) { 98 if (!apbt_address) {
131 printk(KERN_WARNING "No timer base from SFI, use default\n"); 99 printk(KERN_WARNING "No timer base from SFI, use default\n");
132 apbt_address = APBT_DEFAULT_BASE; 100 apbt_address = APBT_DEFAULT_BASE;
133 } 101 }
134 apbt_virt_address = ioremap_nocache(apbt_address, APBT_MMAP_SIZE); 102 apbt_virt_address = ioremap_nocache(apbt_address, APBT_MMAP_SIZE);
135 if (apbt_virt_address) { 103 if (!apbt_virt_address) {
136 pr_debug("Mapped APBT physical addr %p at virtual addr %p\n",\ 104 pr_debug("Failed mapping APBT phy address at %lu\n",\
137 (void *)apbt_address, (void *)apbt_virt_address); 105 (unsigned long)apbt_address);
138 } else {
139 pr_debug("Failed mapping APBT phy address at %p\n",\
140 (void *)apbt_address);
141 goto panic_noapbt; 106 goto panic_noapbt;
142 } 107 }
143 apbt_freq = mtmr->freq_hz / USEC_PER_SEC; 108 apbt_freq = mtmr->freq_hz;
144 sfi_free_mtmr(mtmr); 109 sfi_free_mtmr(mtmr);
145 110
146 /* Now figure out the physical timer id for clocksource device */ 111 /* Now figure out the physical timer id for clocksource device */
@@ -149,9 +114,14 @@ static inline void apbt_set_mapping(void)
149 goto panic_noapbt; 114 goto panic_noapbt;
150 115
151 /* Now figure out the physical timer id */ 116 /* Now figure out the physical timer id */
152 phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff) 117 pr_debug("Use timer %d for clocksource\n",
153 / APBTMRS_REG_SIZE; 118 (int)(mtmr->phys_addr & 0xff) / APBTMRS_REG_SIZE);
154 pr_debug("Use timer %d for clocksource\n", phy_cs_timer_id); 119 phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff) /
120 APBTMRS_REG_SIZE;
121
122 clocksource_apbt = dw_apb_clocksource_init(APBT_CLOCKSOURCE_RATING,
123 "apbt0", apbt_virt_address + phy_cs_timer_id *
124 APBTMRS_REG_SIZE, apbt_freq);
155 return; 125 return;
156 126
157panic_noapbt: 127panic_noapbt:
@@ -173,82 +143,6 @@ static inline int is_apbt_capable(void)
173 return apbt_virt_address ? 1 : 0; 143 return apbt_virt_address ? 1 : 0;
174} 144}
175 145
176static struct clocksource clocksource_apbt = {
177 .name = "apbt",
178 .rating = APBT_CLOCKSOURCE_RATING,
179 .read = apbt_read_clocksource,
180 .mask = APBT_MASK,
181 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
182 .resume = apbt_restart_clocksource,
183};
184
185/* boot APB clock event device */
186static struct clock_event_device apbt_clockevent = {
187 .name = "apbt0",
188 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
189 .set_mode = apbt_set_mode,
190 .set_next_event = apbt_next_event,
191 .shift = APBT_SHIFT,
192 .irq = 0,
193 .rating = APBT_CLOCKEVENT_RATING,
194};
195
196/*
197 * start count down from 0xffff_ffff. this is done by toggling the enable bit
198 * then load initial load count to ~0.
199 */
200static void apbt_start_counter(int n)
201{
202 unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
203
204 ctrl &= ~APBTMR_CONTROL_ENABLE;
205 apbt_writel(n, ctrl, APBTMR_N_CONTROL);
206 apbt_writel(n, ~0, APBTMR_N_LOAD_COUNT);
207 /* enable, mask interrupt */
208 ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
209 ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT);
210 apbt_writel(n, ctrl, APBTMR_N_CONTROL);
211 /* read it once to get cached counter value initialized */
212 apbt_read_clocksource(&clocksource_apbt);
213}
214
215static irqreturn_t apbt_interrupt_handler(int irq, void *data)
216{
217 struct apbt_dev *dev = (struct apbt_dev *)data;
218 struct clock_event_device *aevt = &dev->evt;
219
220 if (!aevt->event_handler) {
221 printk(KERN_INFO "Spurious APBT timer interrupt on %d\n",
222 dev->num);
223 return IRQ_NONE;
224 }
225 aevt->event_handler(aevt);
226 return IRQ_HANDLED;
227}
228
229static void apbt_restart_clocksource(struct clocksource *cs)
230{
231 apbt_start_counter(phy_cs_timer_id);
232}
233
234static void apbt_enable_int(int n)
235{
236 unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
237 /* clear pending intr */
238 apbt_readl(n, APBTMR_N_EOI);
239 ctrl &= ~APBTMR_CONTROL_INT;
240 apbt_writel(n, ctrl, APBTMR_N_CONTROL);
241}
242
243static void apbt_disable_int(int n)
244{
245 unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
246
247 ctrl |= APBTMR_CONTROL_INT;
248 apbt_writel(n, ctrl, APBTMR_N_CONTROL);
249}
250
251
252static int __init apbt_clockevent_register(void) 146static int __init apbt_clockevent_register(void)
253{ 147{
254 struct sfi_timer_table_entry *mtmr; 148 struct sfi_timer_table_entry *mtmr;
@@ -261,45 +155,21 @@ static int __init apbt_clockevent_register(void)
261 return -ENODEV; 155 return -ENODEV;
262 } 156 }
263 157
264 /*
265 * We need to calculate the scaled math multiplication factor for
266 * nanosecond to apbt tick conversion.
267 * mult = (nsec/cycle)*2^APBT_SHIFT
268 */
269 apbt_clockevent.mult = div_sc((unsigned long) mtmr->freq_hz
270 , NSEC_PER_SEC, APBT_SHIFT);
271
272 /* Calculate the min / max delta */
273 apbt_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
274 &apbt_clockevent);
275 apbt_clockevent.min_delta_ns = clockevent_delta2ns(
276 APBT_MIN_DELTA_USEC*apbt_freq,
277 &apbt_clockevent);
278 /*
279 * Start apbt with the boot cpu mask and make it
280 * global if not used for per cpu timer.
281 */
282 apbt_clockevent.cpumask = cpumask_of(smp_processor_id());
283 adev->num = smp_processor_id(); 158 adev->num = smp_processor_id();
284 memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device)); 159 adev->timer = dw_apb_clockevent_init(smp_processor_id(), "apbt0",
160 mrst_timer_options == MRST_TIMER_LAPIC_APBT ?
161 APBT_CLOCKEVENT_RATING - 100 : APBT_CLOCKEVENT_RATING,
162 adev_virt_addr(adev), 0, apbt_freq);
163 /* Firmware does EOI handling for us. */
164 adev->timer->eoi = NULL;
285 165
286 if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) { 166 if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
287 adev->evt.rating = APBT_CLOCKEVENT_RATING - 100; 167 global_clock_event = &adev->timer->ced;
288 global_clock_event = &adev->evt;
289 printk(KERN_DEBUG "%s clockevent registered as global\n", 168 printk(KERN_DEBUG "%s clockevent registered as global\n",
290 global_clock_event->name); 169 global_clock_event->name);
291 } 170 }
292 171
293 if (request_irq(apbt_clockevent.irq, apbt_interrupt_handler, 172 dw_apb_clockevent_register(adev->timer);
294 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
295 apbt_clockevent.name, adev)) {
296 printk(KERN_ERR "Failed request IRQ for APBT%d\n",
297 apbt_clockevent.irq);
298 }
299
300 clockevents_register_device(&adev->evt);
301 /* Start APBT 0 interrupts */
302 apbt_enable_int(APBT_CLOCKEVENT0_NUM);
303 173
304 sfi_free_mtmr(mtmr); 174 sfi_free_mtmr(mtmr);
305 return 0; 175 return 0;
@@ -317,52 +187,34 @@ static void apbt_setup_irq(struct apbt_dev *adev)
317 irq_set_affinity(adev->irq, cpumask_of(adev->cpu)); 187 irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
318 /* APB timer irqs are set up as mp_irqs, timer is edge type */ 188 /* APB timer irqs are set up as mp_irqs, timer is edge type */
319 __irq_set_handler(adev->irq, handle_edge_irq, 0, "edge"); 189 __irq_set_handler(adev->irq, handle_edge_irq, 0, "edge");
320
321 if (system_state == SYSTEM_BOOTING) {
322 if (request_irq(adev->irq, apbt_interrupt_handler,
323 IRQF_TIMER | IRQF_DISABLED |
324 IRQF_NOBALANCING,
325 adev->name, adev)) {
326 printk(KERN_ERR "Failed request IRQ for APBT%d\n",
327 adev->num);
328 }
329 } else
330 enable_irq(adev->irq);
331} 190}
332 191
333/* Should be called with per cpu */ 192/* Should be called with per cpu */
334void apbt_setup_secondary_clock(void) 193void apbt_setup_secondary_clock(void)
335{ 194{
336 struct apbt_dev *adev; 195 struct apbt_dev *adev;
337 struct clock_event_device *aevt;
338 int cpu; 196 int cpu;
339 197
340 /* Don't register boot CPU clockevent */ 198 /* Don't register boot CPU clockevent */
341 cpu = smp_processor_id(); 199 cpu = smp_processor_id();
342 if (!cpu) 200 if (!cpu)
343 return; 201 return;
344 /*
345 * We need to calculate the scaled math multiplication factor for
346 * nanosecond to apbt tick conversion.
347 * mult = (nsec/cycle)*2^APBT_SHIFT
348 */
349 printk(KERN_INFO "Init per CPU clockevent %d\n", cpu);
350 adev = &per_cpu(cpu_apbt_dev, cpu);
351 aevt = &adev->evt;
352 202
353 memcpy(aevt, &apbt_clockevent, sizeof(*aevt)); 203 adev = &__get_cpu_var(cpu_apbt_dev);
354 aevt->cpumask = cpumask_of(cpu); 204 if (!adev->timer) {
355 aevt->name = adev->name; 205 adev->timer = dw_apb_clockevent_init(cpu, adev->name,
356 aevt->mode = CLOCK_EVT_MODE_UNUSED; 206 APBT_CLOCKEVENT_RATING, adev_virt_addr(adev),
207 adev->irq, apbt_freq);
208 adev->timer->eoi = NULL;
209 } else {
210 dw_apb_clockevent_resume(adev->timer);
211 }
357 212
358 printk(KERN_INFO "Registering CPU %d clockevent device %s, mask %08x\n", 213 printk(KERN_INFO "Registering CPU %d clockevent device %s, cpu %08x\n",
359 cpu, aevt->name, *(u32 *)aevt->cpumask); 214 cpu, adev->name, adev->cpu);
360 215
361 apbt_setup_irq(adev); 216 apbt_setup_irq(adev);
362 217 dw_apb_clockevent_register(adev->timer);
363 clockevents_register_device(aevt);
364
365 apbt_enable_int(cpu);
366 218
367 return; 219 return;
368} 220}
@@ -385,13 +237,12 @@ static int apbt_cpuhp_notify(struct notifier_block *n,
385 237
386 switch (action & 0xf) { 238 switch (action & 0xf) {
387 case CPU_DEAD: 239 case CPU_DEAD:
388 disable_irq(adev->irq); 240 dw_apb_clockevent_pause(adev->timer);
389 apbt_disable_int(cpu);
390 if (system_state == SYSTEM_RUNNING) { 241 if (system_state == SYSTEM_RUNNING) {
391 pr_debug("skipping APBT CPU %lu offline\n", cpu); 242 pr_debug("skipping APBT CPU %lu offline\n", cpu);
392 } else if (adev) { 243 } else if (adev) {
393 pr_debug("APBT clockevent for cpu %lu offline\n", cpu); 244 pr_debug("APBT clockevent for cpu %lu offline\n", cpu);
394 free_irq(adev->irq, adev); 245 dw_apb_clockevent_stop(adev->timer);
395 } 246 }
396 break; 247 break;
397 default: 248 default:
@@ -416,116 +267,16 @@ void apbt_setup_secondary_clock(void) {}
416 267
417#endif /* CONFIG_SMP */ 268#endif /* CONFIG_SMP */
418 269
419static void apbt_set_mode(enum clock_event_mode mode,
420 struct clock_event_device *evt)
421{
422 unsigned long ctrl;
423 uint64_t delta;
424 int timer_num;
425 struct apbt_dev *adev = EVT_TO_APBT_DEV(evt);
426
427 BUG_ON(!apbt_virt_address);
428
429 timer_num = adev->num;
430 pr_debug("%s CPU %d timer %d mode=%d\n",
431 __func__, first_cpu(*evt->cpumask), timer_num, mode);
432
433 switch (mode) {
434 case CLOCK_EVT_MODE_PERIODIC:
435 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * apbt_clockevent.mult;
436 delta >>= apbt_clockevent.shift;
437 ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
438 ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
439 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
440 /*
441 * DW APB p. 46, have to disable timer before load counter,
442 * may cause sync problem.
443 */
444 ctrl &= ~APBTMR_CONTROL_ENABLE;
445 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
446 udelay(1);
447 pr_debug("Setting clock period %d for HZ %d\n", (int)delta, HZ);
448 apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT);
449 ctrl |= APBTMR_CONTROL_ENABLE;
450 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
451 break;
452 /* APB timer does not have one-shot mode, use free running mode */
453 case CLOCK_EVT_MODE_ONESHOT:
454 ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
455 /*
456 * set free running mode, this mode will let timer reload max
457 * timeout which will give time (3min on 25MHz clock) to rearm
458 * the next event, therefore emulate the one-shot mode.
459 */
460 ctrl &= ~APBTMR_CONTROL_ENABLE;
461 ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
462
463 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
464 /* write again to set free running mode */
465 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
466
467 /*
468 * DW APB p. 46, load counter with all 1s before starting free
469 * running mode.
470 */
471 apbt_writel(timer_num, ~0, APBTMR_N_LOAD_COUNT);
472 ctrl &= ~APBTMR_CONTROL_INT;
473 ctrl |= APBTMR_CONTROL_ENABLE;
474 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
475 break;
476
477 case CLOCK_EVT_MODE_UNUSED:
478 case CLOCK_EVT_MODE_SHUTDOWN:
479 apbt_disable_int(timer_num);
480 ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
481 ctrl &= ~APBTMR_CONTROL_ENABLE;
482 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
483 break;
484
485 case CLOCK_EVT_MODE_RESUME:
486 apbt_enable_int(timer_num);
487 break;
488 }
489}
490
491static int apbt_next_event(unsigned long delta,
492 struct clock_event_device *evt)
493{
494 unsigned long ctrl;
495 int timer_num;
496
497 struct apbt_dev *adev = EVT_TO_APBT_DEV(evt);
498
499 timer_num = adev->num;
500 /* Disable timer */
501 ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
502 ctrl &= ~APBTMR_CONTROL_ENABLE;
503 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
504 /* write new count */
505 apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT);
506 ctrl |= APBTMR_CONTROL_ENABLE;
507 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
508 return 0;
509}
510
511static cycle_t apbt_read_clocksource(struct clocksource *cs)
512{
513 unsigned long current_count;
514
515 current_count = apbt_readl(phy_cs_timer_id, APBTMR_N_CURRENT_VALUE);
516 return (cycle_t)~current_count;
517}
518
519static int apbt_clocksource_register(void) 270static int apbt_clocksource_register(void)
520{ 271{
521 u64 start, now; 272 u64 start, now;
522 cycle_t t1; 273 cycle_t t1;
523 274
524 /* Start the counter, use timer 2 as source, timer 0/1 for event */ 275 /* Start the counter, use timer 2 as source, timer 0/1 for event */
525 apbt_start_counter(phy_cs_timer_id); 276 dw_apb_clocksource_start(clocksource_apbt);
526 277
527 /* Verify whether apbt counter works */ 278 /* Verify whether apbt counter works */
528 t1 = apbt_read_clocksource(&clocksource_apbt); 279 t1 = dw_apb_clocksource_read(clocksource_apbt);
529 rdtscll(start); 280 rdtscll(start);
530 281
531 /* 282 /*
@@ -540,10 +291,10 @@ static int apbt_clocksource_register(void)
540 } while ((now - start) < 200000UL); 291 } while ((now - start) < 200000UL);
541 292
542 /* APBT is the only always on clocksource, it has to work! */ 293 /* APBT is the only always on clocksource, it has to work! */
543 if (t1 == apbt_read_clocksource(&clocksource_apbt)) 294 if (t1 == dw_apb_clocksource_read(clocksource_apbt))
544 panic("APBT counter not counting. APBT disabled\n"); 295 panic("APBT counter not counting. APBT disabled\n");
545 296
546 clocksource_register_khz(&clocksource_apbt, (u32)apbt_freq*1000); 297 dw_apb_clocksource_register(clocksource_apbt);
547 298
548 return 0; 299 return 0;
549} 300}
@@ -567,10 +318,7 @@ void __init apbt_time_init(void)
567 if (apb_timer_block_enabled) 318 if (apb_timer_block_enabled)
568 return; 319 return;
569 apbt_set_mapping(); 320 apbt_set_mapping();
570 if (apbt_virt_address) { 321 if (!apbt_virt_address)
571 pr_debug("Found APBT version 0x%lx\n",\
572 apbt_readl_reg(APBTMRS_COMP_VERSION));
573 } else
574 goto out_noapbt; 322 goto out_noapbt;
575 /* 323 /*
576 * Read the frequency and check for a sane value, for ESL model 324 * Read the frequency and check for a sane value, for ESL model
@@ -578,7 +326,7 @@ void __init apbt_time_init(void)
578 */ 326 */
579 327
580 if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) { 328 if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) {
581 pr_debug("APBT has invalid freq 0x%llx\n", apbt_freq); 329 pr_debug("APBT has invalid freq 0x%lx\n", apbt_freq);
582 goto out_noapbt; 330 goto out_noapbt;
583 } 331 }
584 if (apbt_clocksource_register()) { 332 if (apbt_clocksource_register()) {
@@ -604,30 +352,20 @@ void __init apbt_time_init(void)
604 } else { 352 } else {
605 percpu_timer = 0; 353 percpu_timer = 0;
606 apbt_num_timers_used = 1; 354 apbt_num_timers_used = 1;
607 adev = &per_cpu(cpu_apbt_dev, 0);
608 adev->flags &= ~APBT_DEV_USED;
609 } 355 }
610 pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used); 356 pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used);
611 357
612 /* here we set up per CPU timer data structure */ 358 /* here we set up per CPU timer data structure */
613 apbt_devs = kzalloc(sizeof(struct apbt_dev) * apbt_num_timers_used,
614 GFP_KERNEL);
615 if (!apbt_devs) {
616 printk(KERN_ERR "Failed to allocate APB timer devices\n");
617 return;
618 }
619 for (i = 0; i < apbt_num_timers_used; i++) { 359 for (i = 0; i < apbt_num_timers_used; i++) {
620 adev = &per_cpu(cpu_apbt_dev, i); 360 adev = &per_cpu(cpu_apbt_dev, i);
621 adev->num = i; 361 adev->num = i;
622 adev->cpu = i; 362 adev->cpu = i;
623 p_mtmr = sfi_get_mtmr(i); 363 p_mtmr = sfi_get_mtmr(i);
624 if (p_mtmr) { 364 if (p_mtmr)
625 adev->tick = p_mtmr->freq_hz;
626 adev->irq = p_mtmr->irq; 365 adev->irq = p_mtmr->irq;
627 } else 366 else
628 printk(KERN_ERR "Failed to get timer for cpu %d\n", i); 367 printk(KERN_ERR "Failed to get timer for cpu %d\n", i);
629 adev->count = 0; 368 snprintf(adev->name, sizeof(adev->name) - 1, "apbt%d", i);
630 sprintf(adev->name, "apbt%d", i);
631 } 369 }
632#endif 370#endif
633 371
@@ -639,17 +377,8 @@ out_noapbt:
639 panic("failed to enable APB timer\n"); 377 panic("failed to enable APB timer\n");
640} 378}
641 379
642static inline void apbt_disable(int n)
643{
644 if (is_apbt_capable()) {
645 unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
646 ctrl &= ~APBTMR_CONTROL_ENABLE;
647 apbt_writel(n, ctrl, APBTMR_N_CONTROL);
648 }
649}
650
651/* called before apb_timer_enable, use early map */ 380/* called before apb_timer_enable, use early map */
652unsigned long apbt_quick_calibrate() 381unsigned long apbt_quick_calibrate(void)
653{ 382{
654 int i, scale; 383 int i, scale;
655 u64 old, new; 384 u64 old, new;
@@ -658,31 +387,31 @@ unsigned long apbt_quick_calibrate()
658 u32 loop, shift; 387 u32 loop, shift;
659 388
660 apbt_set_mapping(); 389 apbt_set_mapping();
661 apbt_start_counter(phy_cs_timer_id); 390 dw_apb_clocksource_start(clocksource_apbt);
662 391
663 /* check if the timer can count down, otherwise return */ 392 /* check if the timer can count down, otherwise return */
664 old = apbt_read_clocksource(&clocksource_apbt); 393 old = dw_apb_clocksource_read(clocksource_apbt);
665 i = 10000; 394 i = 10000;
666 while (--i) { 395 while (--i) {
667 if (old != apbt_read_clocksource(&clocksource_apbt)) 396 if (old != dw_apb_clocksource_read(clocksource_apbt))
668 break; 397 break;
669 } 398 }
670 if (!i) 399 if (!i)
671 goto failed; 400 goto failed;
672 401
673 /* count 16 ms */ 402 /* count 16 ms */
674 loop = (apbt_freq * 1000) << 4; 403 loop = (apbt_freq / 1000) << 4;
675 404
676 /* restart the timer to ensure it won't get to 0 in the calibration */ 405 /* restart the timer to ensure it won't get to 0 in the calibration */
677 apbt_start_counter(phy_cs_timer_id); 406 dw_apb_clocksource_start(clocksource_apbt);
678 407
679 old = apbt_read_clocksource(&clocksource_apbt); 408 old = dw_apb_clocksource_read(clocksource_apbt);
680 old += loop; 409 old += loop;
681 410
682 t1 = __native_read_tsc(); 411 t1 = __native_read_tsc();
683 412
684 do { 413 do {
685 new = apbt_read_clocksource(&clocksource_apbt); 414 new = dw_apb_clocksource_read(clocksource_apbt);
686 } while (new < old); 415 } while (new < old);
687 416
688 t2 = __native_read_tsc(); 417 t2 = __native_read_tsc();
@@ -694,7 +423,7 @@ unsigned long apbt_quick_calibrate()
694 return 0; 423 return 0;
695 } 424 }
696 scale = (int)div_u64((t2 - t1), loop >> shift); 425 scale = (int)div_u64((t2 - t1), loop >> shift);
697 khz = (scale * apbt_freq * 1000) >> shift; 426 khz = (scale * (apbt_freq / 1000)) >> shift;
698 printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz); 427 printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz);
699 return khz; 428 return khz;
700failed: 429failed:
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 9498b8445186..b24be38c8cf8 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1944,10 +1944,28 @@ void disconnect_bsp_APIC(int virt_wire_setup)
1944 1944
1945void __cpuinit generic_processor_info(int apicid, int version) 1945void __cpuinit generic_processor_info(int apicid, int version)
1946{ 1946{
1947 int cpu; 1947 int cpu, max = nr_cpu_ids;
1948 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
1949 phys_cpu_present_map);
1950
1951 /*
1952 * If boot cpu has not been detected yet, then only allow upto
1953 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
1954 */
1955 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
1956 apicid != boot_cpu_physical_apicid) {
1957 int thiscpu = max + disabled_cpus - 1;
1958
1959 pr_warning(
1960 "ACPI: NR_CPUS/possible_cpus limit of %i almost"
1961 " reached. Keeping one slot for boot cpu."
1962 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1963
1964 disabled_cpus++;
1965 return;
1966 }
1948 1967
1949 if (num_processors >= nr_cpu_ids) { 1968 if (num_processors >= nr_cpu_ids) {
1950 int max = nr_cpu_ids;
1951 int thiscpu = max + disabled_cpus; 1969 int thiscpu = max + disabled_cpus;
1952 1970
1953 pr_warning( 1971 pr_warning(
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 525514cf33c3..46674fbb62ba 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -62,6 +62,8 @@ static void __init check_fpu(void)
62 return; 62 return;
63 } 63 }
64 64
65 kernel_fpu_begin();
66
65 /* 67 /*
66 * trap_init() enabled FXSR and company _before_ testing for FP 68 * trap_init() enabled FXSR and company _before_ testing for FP
67 * problems here. 69 * problems here.
@@ -80,6 +82,8 @@ static void __init check_fpu(void)
80 : "=m" (*&fdiv_bug) 82 : "=m" (*&fdiv_bug)
81 : "m" (*&x), "m" (*&y)); 83 : "m" (*&x), "m" (*&y));
82 84
85 kernel_fpu_end();
86
83 boot_cpu_data.fdiv_bug = fdiv_bug; 87 boot_cpu_data.fdiv_bug = fdiv_bug;
84 if (boot_cpu_data.fdiv_bug) 88 if (boot_cpu_data.fdiv_bug)
85 printk(KERN_WARNING "Hmm, FPU with FDIV bug.\n"); 89 printk(KERN_WARNING "Hmm, FPU with FDIV bug.\n");
diff --git a/arch/x86/kernel/cpu/hypervisor.c b/arch/x86/kernel/cpu/hypervisor.c
index 8095f8611f8a..755f64fb0743 100644
--- a/arch/x86/kernel/cpu/hypervisor.c
+++ b/arch/x86/kernel/cpu/hypervisor.c
@@ -32,11 +32,11 @@
32 */ 32 */
33static const __initconst struct hypervisor_x86 * const hypervisors[] = 33static const __initconst struct hypervisor_x86 * const hypervisors[] =
34{ 34{
35 &x86_hyper_vmware,
36 &x86_hyper_ms_hyperv,
37#ifdef CONFIG_XEN_PVHVM 35#ifdef CONFIG_XEN_PVHVM
38 &x86_hyper_xen_hvm, 36 &x86_hyper_xen_hvm,
39#endif 37#endif
38 &x86_hyper_vmware,
39 &x86_hyper_ms_hyperv,
40}; 40};
41 41
42const struct hypervisor_x86 *x86_hyper; 42const struct hypervisor_x86 *x86_hyper;
diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index 8bbe8c56916d..b78643d0f9a5 100644
--- a/arch/x86/kernel/quirks.c
+++ b/arch/x86/kernel/quirks.c
@@ -10,7 +10,7 @@
10 10
11static void __devinit quirk_intel_irqbalance(struct pci_dev *dev) 11static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
12{ 12{
13 u8 config, rev; 13 u8 config;
14 u16 word; 14 u16 word;
15 15
16 /* BIOS may enable hardware IRQ balancing for 16 /* BIOS may enable hardware IRQ balancing for
@@ -18,8 +18,7 @@ static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
18 * based platforms. 18 * based platforms.
19 * Disable SW irqbalance/affinity on those platforms. 19 * Disable SW irqbalance/affinity on those platforms.
20 */ 20 */
21 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); 21 if (dev->revision > 0x9)
22 if (rev > 0x9)
23 return; 22 return;
24 23
25 /* enable access to config space*/ 24 /* enable access to config space*/
diff --git a/arch/x86/kernel/relocate_kernel_32.S b/arch/x86/kernel/relocate_kernel_32.S
index 41235531b11c..36818f8ec2be 100644
--- a/arch/x86/kernel/relocate_kernel_32.S
+++ b/arch/x86/kernel/relocate_kernel_32.S
@@ -97,6 +97,8 @@ relocate_kernel:
97 ret 97 ret
98 98
99identity_mapped: 99identity_mapped:
100 /* set return address to 0 if not preserving context */
101 pushl $0
100 /* store the start address on the stack */ 102 /* store the start address on the stack */
101 pushl %edx 103 pushl %edx
102 104
diff --git a/arch/x86/kernel/relocate_kernel_64.S b/arch/x86/kernel/relocate_kernel_64.S
index 4de8f5b3d476..7a6f3b3be3cf 100644
--- a/arch/x86/kernel/relocate_kernel_64.S
+++ b/arch/x86/kernel/relocate_kernel_64.S
@@ -100,6 +100,8 @@ relocate_kernel:
100 ret 100 ret
101 101
102identity_mapped: 102identity_mapped:
103 /* set return address to 0 if not preserving context */
104 pushq $0
103 /* store the start address on the stack */ 105 /* store the start address on the stack */
104 pushq %rdx 106 pushq %rdx
105 107
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 56c633a5db72..db483369f10b 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -5,7 +5,6 @@
5#include <linux/timer.h> 5#include <linux/timer.h>
6#include <linux/acpi_pmtmr.h> 6#include <linux/acpi_pmtmr.h>
7#include <linux/cpufreq.h> 7#include <linux/cpufreq.h>
8#include <linux/dmi.h>
9#include <linux/delay.h> 8#include <linux/delay.h>
10#include <linux/clocksource.h> 9#include <linux/clocksource.h>
11#include <linux/percpu.h> 10#include <linux/percpu.h>
@@ -800,27 +799,6 @@ void mark_tsc_unstable(char *reason)
800 799
801EXPORT_SYMBOL_GPL(mark_tsc_unstable); 800EXPORT_SYMBOL_GPL(mark_tsc_unstable);
802 801
803static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d)
804{
805 printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
806 d->ident);
807 tsc_unstable = 1;
808 return 0;
809}
810
811/* List of systems that have known TSC problems */
812static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
813 {
814 .callback = dmi_mark_tsc_unstable,
815 .ident = "IBM Thinkpad 380XD",
816 .matches = {
817 DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
818 DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
819 },
820 },
821 {}
822};
823
824static void __init check_system_tsc_reliable(void) 802static void __init check_system_tsc_reliable(void)
825{ 803{
826#ifdef CONFIG_MGEODE_LX 804#ifdef CONFIG_MGEODE_LX
@@ -1010,8 +988,6 @@ void __init tsc_init(void)
1010 lpj_fine = lpj; 988 lpj_fine = lpj;
1011 989
1012 use_tsc_delay(); 990 use_tsc_delay();
1013 /* Check and install the TSC clocksource */
1014 dmi_check_system(bad_tsc_dmi_table);
1015 991
1016 if (unsynchronized_tsc()) 992 if (unsynchronized_tsc())
1017 mark_tsc_unstable("TSCs unsynchronized"); 993 mark_tsc_unstable("TSCs unsynchronized");
diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig
index 50f63648ce1b..65cf8233d25c 100644
--- a/arch/x86/kvm/Kconfig
+++ b/arch/x86/kvm/Kconfig
@@ -76,6 +76,5 @@ config KVM_MMU_AUDIT
76# the virtualization menu. 76# the virtualization menu.
77source drivers/vhost/Kconfig 77source drivers/vhost/Kconfig
78source drivers/lguest/Kconfig 78source drivers/lguest/Kconfig
79source drivers/virtio/Kconfig
80 79
81endif # VIRTUALIZATION 80endif # VIRTUALIZATION
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 52e306dd5010..9e7a4f5b5c2e 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -112,6 +112,8 @@ source "drivers/uio/Kconfig"
112 112
113source "drivers/vlynq/Kconfig" 113source "drivers/vlynq/Kconfig"
114 114
115source "drivers/virtio/Kconfig"
116
115source "drivers/xen/Kconfig" 117source "drivers/xen/Kconfig"
116 118
117source "drivers/staging/Kconfig" 119source "drivers/staging/Kconfig"
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index d8d3e02b912c..34e9c4f88926 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -12,3 +12,6 @@ config CLKBLD_I8253
12 12
13config CLKSRC_MMIO 13config CLKSRC_MMIO
14 bool 14 bool
15
16config DW_APB_TIMER
17 bool
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 7922a0cfc99f..85ad1646a7b7 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o
8obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o 8obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
9obj-$(CONFIG_CLKBLD_I8253) += i8253.o 9obj-$(CONFIG_CLKBLD_I8253) += i8253.o
10obj-$(CONFIG_CLKSRC_MMIO) += mmio.o 10obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
11obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o
diff --git a/drivers/clocksource/dw_apb_timer.c b/drivers/clocksource/dw_apb_timer.c
new file mode 100644
index 000000000000..580f870541a3
--- /dev/null
+++ b/drivers/clocksource/dw_apb_timer.c
@@ -0,0 +1,401 @@
1/*
2 * (C) Copyright 2009 Intel Corporation
3 * Author: Jacob Pan (jacob.jun.pan@intel.com)
4 *
5 * Shared with ARM platforms, Jamie Iles, Picochip 2011
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Support for the Synopsys DesignWare APB Timers.
12 */
13#include <linux/dw_apb_timer.h>
14#include <linux/delay.h>
15#include <linux/kernel.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/io.h>
19#include <linux/slab.h>
20
21#define APBT_MIN_PERIOD 4
22#define APBT_MIN_DELTA_USEC 200
23
24#define APBTMR_N_LOAD_COUNT 0x00
25#define APBTMR_N_CURRENT_VALUE 0x04
26#define APBTMR_N_CONTROL 0x08
27#define APBTMR_N_EOI 0x0c
28#define APBTMR_N_INT_STATUS 0x10
29
30#define APBTMRS_INT_STATUS 0xa0
31#define APBTMRS_EOI 0xa4
32#define APBTMRS_RAW_INT_STATUS 0xa8
33#define APBTMRS_COMP_VERSION 0xac
34
35#define APBTMR_CONTROL_ENABLE (1 << 0)
36/* 1: periodic, 0:free running. */
37#define APBTMR_CONTROL_MODE_PERIODIC (1 << 1)
38#define APBTMR_CONTROL_INT (1 << 2)
39
40static inline struct dw_apb_clock_event_device *
41ced_to_dw_apb_ced(struct clock_event_device *evt)
42{
43 return container_of(evt, struct dw_apb_clock_event_device, ced);
44}
45
46static inline struct dw_apb_clocksource *
47clocksource_to_dw_apb_clocksource(struct clocksource *cs)
48{
49 return container_of(cs, struct dw_apb_clocksource, cs);
50}
51
52static unsigned long apbt_readl(struct dw_apb_timer *timer, unsigned long offs)
53{
54 return readl(timer->base + offs);
55}
56
57static void apbt_writel(struct dw_apb_timer *timer, unsigned long val,
58 unsigned long offs)
59{
60 writel(val, timer->base + offs);
61}
62
63static void apbt_disable_int(struct dw_apb_timer *timer)
64{
65 unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
66
67 ctrl |= APBTMR_CONTROL_INT;
68 apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
69}
70
71/**
72 * dw_apb_clockevent_pause() - stop the clock_event_device from running
73 *
74 * @dw_ced: The APB clock to stop generating events.
75 */
76void dw_apb_clockevent_pause(struct dw_apb_clock_event_device *dw_ced)
77{
78 disable_irq(dw_ced->timer.irq);
79 apbt_disable_int(&dw_ced->timer);
80}
81
82static void apbt_eoi(struct dw_apb_timer *timer)
83{
84 apbt_readl(timer, APBTMR_N_EOI);
85}
86
87static irqreturn_t dw_apb_clockevent_irq(int irq, void *data)
88{
89 struct clock_event_device *evt = data;
90 struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
91
92 if (!evt->event_handler) {
93 pr_info("Spurious APBT timer interrupt %d", irq);
94 return IRQ_NONE;
95 }
96
97 if (dw_ced->eoi)
98 dw_ced->eoi(&dw_ced->timer);
99
100 evt->event_handler(evt);
101 return IRQ_HANDLED;
102}
103
104static void apbt_enable_int(struct dw_apb_timer *timer)
105{
106 unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
107 /* clear pending intr */
108 apbt_readl(timer, APBTMR_N_EOI);
109 ctrl &= ~APBTMR_CONTROL_INT;
110 apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
111}
112
113static void apbt_set_mode(enum clock_event_mode mode,
114 struct clock_event_device *evt)
115{
116 unsigned long ctrl;
117 unsigned long period;
118 struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
119
120 pr_debug("%s CPU %d mode=%d\n", __func__, first_cpu(*evt->cpumask),
121 mode);
122
123 switch (mode) {
124 case CLOCK_EVT_MODE_PERIODIC:
125 period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
126 ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
127 ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
128 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
129 /*
130 * DW APB p. 46, have to disable timer before load counter,
131 * may cause sync problem.
132 */
133 ctrl &= ~APBTMR_CONTROL_ENABLE;
134 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
135 udelay(1);
136 pr_debug("Setting clock period %lu for HZ %d\n", period, HZ);
137 apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT);
138 ctrl |= APBTMR_CONTROL_ENABLE;
139 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
140 break;
141
142 case CLOCK_EVT_MODE_ONESHOT:
143 ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
144 /*
145 * set free running mode, this mode will let timer reload max
146 * timeout which will give time (3min on 25MHz clock) to rearm
147 * the next event, therefore emulate the one-shot mode.
148 */
149 ctrl &= ~APBTMR_CONTROL_ENABLE;
150 ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
151
152 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
153 /* write again to set free running mode */
154 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
155
156 /*
157 * DW APB p. 46, load counter with all 1s before starting free
158 * running mode.
159 */
160 apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT);
161 ctrl &= ~APBTMR_CONTROL_INT;
162 ctrl |= APBTMR_CONTROL_ENABLE;
163 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
164 break;
165
166 case CLOCK_EVT_MODE_UNUSED:
167 case CLOCK_EVT_MODE_SHUTDOWN:
168 ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
169 ctrl &= ~APBTMR_CONTROL_ENABLE;
170 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
171 break;
172
173 case CLOCK_EVT_MODE_RESUME:
174 apbt_enable_int(&dw_ced->timer);
175 break;
176 }
177}
178
179static int apbt_next_event(unsigned long delta,
180 struct clock_event_device *evt)
181{
182 unsigned long ctrl;
183 struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
184
185 /* Disable timer */
186 ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
187 ctrl &= ~APBTMR_CONTROL_ENABLE;
188 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
189 /* write new count */
190 apbt_writel(&dw_ced->timer, delta, APBTMR_N_LOAD_COUNT);
191 ctrl |= APBTMR_CONTROL_ENABLE;
192 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
193
194 return 0;
195}
196
197/**
198 * dw_apb_clockevent_init() - use an APB timer as a clock_event_device
199 *
200 * @cpu: The CPU the events will be targeted at.
201 * @name: The name used for the timer and the IRQ for it.
202 * @rating: The rating to give the timer.
203 * @base: I/O base for the timer registers.
204 * @irq: The interrupt number to use for the timer.
205 * @freq: The frequency that the timer counts at.
206 *
207 * This creates a clock_event_device for using with the generic clock layer
208 * but does not start and register it. This should be done with
209 * dw_apb_clockevent_register() as the next step. If this is the first time
210 * it has been called for a timer then the IRQ will be requested, if not it
211 * just be enabled to allow CPU hotplug to avoid repeatedly requesting and
212 * releasing the IRQ.
213 */
214struct dw_apb_clock_event_device *
215dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
216 void __iomem *base, int irq, unsigned long freq)
217{
218 struct dw_apb_clock_event_device *dw_ced =
219 kzalloc(sizeof(*dw_ced), GFP_KERNEL);
220 int err;
221
222 if (!dw_ced)
223 return NULL;
224
225 dw_ced->timer.base = base;
226 dw_ced->timer.irq = irq;
227 dw_ced->timer.freq = freq;
228
229 clockevents_calc_mult_shift(&dw_ced->ced, freq, APBT_MIN_PERIOD);
230 dw_ced->ced.max_delta_ns = clockevent_delta2ns(0x7fffffff,
231 &dw_ced->ced);
232 dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced);
233 dw_ced->ced.cpumask = cpumask_of(cpu);
234 dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
235 dw_ced->ced.set_mode = apbt_set_mode;
236 dw_ced->ced.set_next_event = apbt_next_event;
237 dw_ced->ced.irq = dw_ced->timer.irq;
238 dw_ced->ced.rating = rating;
239 dw_ced->ced.name = name;
240
241 dw_ced->irqaction.name = dw_ced->ced.name;
242 dw_ced->irqaction.handler = dw_apb_clockevent_irq;
243 dw_ced->irqaction.dev_id = &dw_ced->ced;
244 dw_ced->irqaction.irq = irq;
245 dw_ced->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL |
246 IRQF_NOBALANCING |
247 IRQF_DISABLED;
248
249 dw_ced->eoi = apbt_eoi;
250 err = setup_irq(irq, &dw_ced->irqaction);
251 if (err) {
252 pr_err("failed to request timer irq\n");
253 kfree(dw_ced);
254 dw_ced = NULL;
255 }
256
257 return dw_ced;
258}
259
260/**
261 * dw_apb_clockevent_resume() - resume a clock that has been paused.
262 *
263 * @dw_ced: The APB clock to resume.
264 */
265void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced)
266{
267 enable_irq(dw_ced->timer.irq);
268}
269
270/**
271 * dw_apb_clockevent_stop() - stop the clock_event_device and release the IRQ.
272 *
273 * @dw_ced: The APB clock to stop generating the events.
274 */
275void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced)
276{
277 free_irq(dw_ced->timer.irq, &dw_ced->ced);
278}
279
280/**
281 * dw_apb_clockevent_register() - register the clock with the generic layer
282 *
283 * @dw_ced: The APB clock to register as a clock_event_device.
284 */
285void dw_apb_clockevent_register(struct dw_apb_clock_event_device *dw_ced)
286{
287 apbt_writel(&dw_ced->timer, 0, APBTMR_N_CONTROL);
288 clockevents_register_device(&dw_ced->ced);
289 apbt_enable_int(&dw_ced->timer);
290}
291
292/**
293 * dw_apb_clocksource_start() - start the clocksource counting.
294 *
295 * @dw_cs: The clocksource to start.
296 *
297 * This is used to start the clocksource before registration and can be used
298 * to enable calibration of timers.
299 */
300void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs)
301{
302 /*
303 * start count down from 0xffff_ffff. this is done by toggling the
304 * enable bit then load initial load count to ~0.
305 */
306 unsigned long ctrl = apbt_readl(&dw_cs->timer, APBTMR_N_CONTROL);
307
308 ctrl &= ~APBTMR_CONTROL_ENABLE;
309 apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
310 apbt_writel(&dw_cs->timer, ~0, APBTMR_N_LOAD_COUNT);
311 /* enable, mask interrupt */
312 ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
313 ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT);
314 apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
315 /* read it once to get cached counter value initialized */
316 dw_apb_clocksource_read(dw_cs);
317}
318
319static cycle_t __apbt_read_clocksource(struct clocksource *cs)
320{
321 unsigned long current_count;
322 struct dw_apb_clocksource *dw_cs =
323 clocksource_to_dw_apb_clocksource(cs);
324
325 current_count = apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);
326
327 return (cycle_t)~current_count;
328}
329
330static void apbt_restart_clocksource(struct clocksource *cs)
331{
332 struct dw_apb_clocksource *dw_cs =
333 clocksource_to_dw_apb_clocksource(cs);
334
335 dw_apb_clocksource_start(dw_cs);
336}
337
338/**
339 * dw_apb_clocksource_init() - use an APB timer as a clocksource.
340 *
341 * @rating: The rating to give the clocksource.
342 * @name: The name for the clocksource.
343 * @base: The I/O base for the timer registers.
344 * @freq: The frequency that the timer counts at.
345 *
346 * This creates a clocksource using an APB timer but does not yet register it
347 * with the clocksource system. This should be done with
348 * dw_apb_clocksource_register() as the next step.
349 */
350struct dw_apb_clocksource *
351dw_apb_clocksource_init(unsigned rating, char *name, void __iomem *base,
352 unsigned long freq)
353{
354 struct dw_apb_clocksource *dw_cs = kzalloc(sizeof(*dw_cs), GFP_KERNEL);
355
356 if (!dw_cs)
357 return NULL;
358
359 dw_cs->timer.base = base;
360 dw_cs->timer.freq = freq;
361 dw_cs->cs.name = name;
362 dw_cs->cs.rating = rating;
363 dw_cs->cs.read = __apbt_read_clocksource;
364 dw_cs->cs.mask = CLOCKSOURCE_MASK(32);
365 dw_cs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
366 dw_cs->cs.resume = apbt_restart_clocksource;
367
368 return dw_cs;
369}
370
371/**
372 * dw_apb_clocksource_register() - register the APB clocksource.
373 *
374 * @dw_cs: The clocksource to register.
375 */
376void dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs)
377{
378 clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq);
379}
380
381/**
382 * dw_apb_clocksource_read() - read the current value of a clocksource.
383 *
384 * @dw_cs: The clocksource to read.
385 */
386cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs)
387{
388 return (cycle_t)~apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);
389}
390
391/**
392 * dw_apb_clocksource_unregister() - unregister and free a clocksource.
393 *
394 * @dw_cs: The clocksource to unregister/free.
395 */
396void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs)
397{
398 clocksource_unregister(&dw_cs->cs);
399
400 kfree(dw_cs);
401}
diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig
index 3dd6294d10b6..57e493b1bd20 100644
--- a/drivers/virtio/Kconfig
+++ b/drivers/virtio/Kconfig
@@ -7,6 +7,8 @@ config VIRTIO_RING
7 tristate 7 tristate
8 depends on VIRTIO 8 depends on VIRTIO
9 9
10menu "Virtio drivers"
11
10config VIRTIO_PCI 12config VIRTIO_PCI
11 tristate "PCI driver for virtio devices (EXPERIMENTAL)" 13 tristate "PCI driver for virtio devices (EXPERIMENTAL)"
12 depends on PCI && EXPERIMENTAL 14 depends on PCI && EXPERIMENTAL
@@ -33,3 +35,4 @@ config VIRTIO_BALLOON
33 35
34 If unsure, say M. 36 If unsure, say M.
35 37
38endmenu
diff --git a/include/linux/dw_apb_timer.h b/include/linux/dw_apb_timer.h
new file mode 100644
index 000000000000..49638ea3b776
--- /dev/null
+++ b/include/linux/dw_apb_timer.h
@@ -0,0 +1,56 @@
1/*
2 * (C) Copyright 2009 Intel Corporation
3 * Author: Jacob Pan (jacob.jun.pan@intel.com)
4 *
5 * Shared with ARM platforms, Jamie Iles, Picochip 2011
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Support for the Synopsys DesignWare APB Timers.
12 */
13#ifndef __DW_APB_TIMER_H__
14#define __DW_APB_TIMER_H__
15
16#include <linux/clockchips.h>
17#include <linux/clocksource.h>
18#include <linux/interrupt.h>
19
20#define APBTMRS_REG_SIZE 0x14
21
22struct dw_apb_timer {
23 void __iomem *base;
24 unsigned long freq;
25 int irq;
26};
27
28struct dw_apb_clock_event_device {
29 struct clock_event_device ced;
30 struct dw_apb_timer timer;
31 struct irqaction irqaction;
32 void (*eoi)(struct dw_apb_timer *);
33};
34
35struct dw_apb_clocksource {
36 struct dw_apb_timer timer;
37 struct clocksource cs;
38};
39
40void dw_apb_clockevent_register(struct dw_apb_clock_event_device *dw_ced);
41void dw_apb_clockevent_pause(struct dw_apb_clock_event_device *dw_ced);
42void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced);
43void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced);
44
45struct dw_apb_clock_event_device *
46dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
47 void __iomem *base, int irq, unsigned long freq);
48struct dw_apb_clocksource *
49dw_apb_clocksource_init(unsigned rating, char *name, void __iomem *base,
50 unsigned long freq);
51void dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs);
52void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs);
53cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs);
54void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs);
55
56#endif /* __DW_APB_TIMER_H__ */
diff --git a/include/linux/irq.h b/include/linux/irq.h
index baa397eb9c33..5f695041090c 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -96,11 +96,6 @@ enum {
96 96
97#define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 97#define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
98 98
99static inline __deprecated bool CHECK_IRQ_PER_CPU(unsigned int status)
100{
101 return status & IRQ_PER_CPU;
102}
103
104/* 99/*
105 * Return value for chip->irq_set_affinity() 100 * Return value for chip->irq_set_affinity()
106 * 101 *
diff --git a/init/Kconfig b/init/Kconfig
index 27b8a7a43261..e20aa3112240 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -917,6 +917,8 @@ config ANON_INODES
917 917
918menuconfig EXPERT 918menuconfig EXPERT
919 bool "Configure standard kernel features (expert users)" 919 bool "Configure standard kernel features (expert users)"
920 # Unhide debug options, to make the on-by-default options visible
921 select DEBUG_KERNEL
920 help 922 help
921 This option allows certain base kernel options and settings 923 This option allows certain base kernel options and settings
922 to be disabled or tweaked. This is for specialized 924 to be disabled or tweaked. This is for specialized
diff --git a/tools/perf/Makefile b/tools/perf/Makefile
index d0861bbd1d94..56d62d3fb167 100644
--- a/tools/perf/Makefile
+++ b/tools/perf/Makefile
@@ -52,7 +52,10 @@ ifeq ($(ARCH),i386)
52endif 52endif
53ifeq ($(ARCH),x86_64) 53ifeq ($(ARCH),x86_64)
54 ARCH := x86 54 ARCH := x86
55 IS_X86_64 := $(shell echo __x86_64__ | ${CC} -E -xc - | tail -n 1) 55 IS_X86_64 := 0
56 ifeq (, $(findstring m32,$(EXTRA_CFLAGS)))
57 IS_X86_64 := $(shell echo __x86_64__ | ${CC} -E -xc - | tail -n 1)
58 endif
56 ifeq (${IS_X86_64}, 1) 59 ifeq (${IS_X86_64}, 1)
57 RAW_ARCH := x86_64 60 RAW_ARCH := x86_64
58 ARCH_CFLAGS := -DARCH_X86_64 61 ARCH_CFLAGS := -DARCH_X86_64
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 04:37:33 -0500