diff options
-rw-r--r-- | arch/powerpc/include/asm/processor.h | 38 | ||||
-rw-r--r-- | arch/powerpc/include/asm/reg_booke.h | 8 | ||||
-rw-r--r-- | arch/powerpc/kernel/asm-offsets.c | 2 | ||||
-rw-r--r-- | arch/powerpc/kernel/process.c | 42 | ||||
-rw-r--r-- | arch/powerpc/kernel/ptrace.c | 154 | ||||
-rw-r--r-- | arch/powerpc/kernel/ptrace32.c | 2 | ||||
-rw-r--r-- | arch/powerpc/kernel/signal_32.c | 6 | ||||
-rw-r--r-- | arch/powerpc/kernel/traps.c | 35 |
8 files changed, 147 insertions, 140 deletions
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index e378cccfca55..b43844442a6c 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h | |||
@@ -147,22 +147,7 @@ typedef struct { | |||
147 | #define TS_FPR(i) fpr[i][TS_FPROFFSET] | 147 | #define TS_FPR(i) fpr[i][TS_FPROFFSET] |
148 | #define TS_TRANS_FPR(i) transact_fpr[i][TS_FPROFFSET] | 148 | #define TS_TRANS_FPR(i) transact_fpr[i][TS_FPROFFSET] |
149 | 149 | ||
150 | struct thread_struct { | 150 | struct debug_reg { |
151 | unsigned long ksp; /* Kernel stack pointer */ | ||
152 | unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */ | ||
153 | |||
154 | #ifdef CONFIG_PPC64 | ||
155 | unsigned long ksp_vsid; | ||
156 | #endif | ||
157 | struct pt_regs *regs; /* Pointer to saved register state */ | ||
158 | mm_segment_t fs; /* for get_fs() validation */ | ||
159 | #ifdef CONFIG_BOOKE | ||
160 | /* BookE base exception scratch space; align on cacheline */ | ||
161 | unsigned long normsave[8] ____cacheline_aligned; | ||
162 | #endif | ||
163 | #ifdef CONFIG_PPC32 | ||
164 | void *pgdir; /* root of page-table tree */ | ||
165 | #endif | ||
166 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS | 151 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
167 | /* | 152 | /* |
168 | * The following help to manage the use of Debug Control Registers | 153 | * The following help to manage the use of Debug Control Registers |
@@ -199,6 +184,27 @@ struct thread_struct { | |||
199 | unsigned long dvc2; | 184 | unsigned long dvc2; |
200 | #endif | 185 | #endif |
201 | #endif | 186 | #endif |
187 | }; | ||
188 | |||
189 | struct thread_struct { | ||
190 | unsigned long ksp; /* Kernel stack pointer */ | ||
191 | unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */ | ||
192 | |||
193 | #ifdef CONFIG_PPC64 | ||
194 | unsigned long ksp_vsid; | ||
195 | #endif | ||
196 | struct pt_regs *regs; /* Pointer to saved register state */ | ||
197 | mm_segment_t fs; /* for get_fs() validation */ | ||
198 | #ifdef CONFIG_BOOKE | ||
199 | /* BookE base exception scratch space; align on cacheline */ | ||
200 | unsigned long normsave[8] ____cacheline_aligned; | ||
201 | #endif | ||
202 | #ifdef CONFIG_PPC32 | ||
203 | void *pgdir; /* root of page-table tree */ | ||
204 | #endif | ||
205 | /* Debug Registers */ | ||
206 | struct debug_reg debug; | ||
207 | |||
202 | /* FP and VSX 0-31 register set */ | 208 | /* FP and VSX 0-31 register set */ |
203 | double fpr[32][TS_FPRWIDTH] __attribute__((aligned(16))); | 209 | double fpr[32][TS_FPRWIDTH] __attribute__((aligned(16))); |
204 | struct { | 210 | struct { |
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index ed8f836da094..2e31aacd8acc 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h | |||
@@ -381,7 +381,7 @@ | |||
381 | #define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ | 381 | #define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ |
382 | #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ | 382 | #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ |
383 | 383 | ||
384 | #define dbcr_iac_range(task) ((task)->thread.dbcr0) | 384 | #define dbcr_iac_range(task) ((task)->thread.debug.dbcr0) |
385 | #define DBCR_IAC12I DBCR0_IA12 /* Range Inclusive */ | 385 | #define DBCR_IAC12I DBCR0_IA12 /* Range Inclusive */ |
386 | #define DBCR_IAC12X (DBCR0_IA12 | DBCR0_IA12X) /* Range Exclusive */ | 386 | #define DBCR_IAC12X (DBCR0_IA12 | DBCR0_IA12X) /* Range Exclusive */ |
387 | #define DBCR_IAC12MODE (DBCR0_IA12 | DBCR0_IA12X) /* IAC 1-2 Mode Bits */ | 387 | #define DBCR_IAC12MODE (DBCR0_IA12 | DBCR0_IA12X) /* IAC 1-2 Mode Bits */ |
@@ -395,7 +395,7 @@ | |||
395 | #define DBCR1_DAC1W 0x20000000 /* DAC1 Write Debug Event */ | 395 | #define DBCR1_DAC1W 0x20000000 /* DAC1 Write Debug Event */ |
396 | #define DBCR1_DAC2W 0x10000000 /* DAC2 Write Debug Event */ | 396 | #define DBCR1_DAC2W 0x10000000 /* DAC2 Write Debug Event */ |
397 | 397 | ||
398 | #define dbcr_dac(task) ((task)->thread.dbcr1) | 398 | #define dbcr_dac(task) ((task)->thread.debug.dbcr1) |
399 | #define DBCR_DAC1R DBCR1_DAC1R | 399 | #define DBCR_DAC1R DBCR1_DAC1R |
400 | #define DBCR_DAC1W DBCR1_DAC1W | 400 | #define DBCR_DAC1W DBCR1_DAC1W |
401 | #define DBCR_DAC2R DBCR1_DAC2R | 401 | #define DBCR_DAC2R DBCR1_DAC2R |
@@ -441,7 +441,7 @@ | |||
441 | #define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */ | 441 | #define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */ |
442 | #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ | 442 | #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ |
443 | 443 | ||
444 | #define dbcr_dac(task) ((task)->thread.dbcr0) | 444 | #define dbcr_dac(task) ((task)->thread.debug.dbcr0) |
445 | #define DBCR_DAC1R DBCR0_DAC1R | 445 | #define DBCR_DAC1R DBCR0_DAC1R |
446 | #define DBCR_DAC1W DBCR0_DAC1W | 446 | #define DBCR_DAC1W DBCR0_DAC1W |
447 | #define DBCR_DAC2R DBCR0_DAC2R | 447 | #define DBCR_DAC2R DBCR0_DAC2R |
@@ -475,7 +475,7 @@ | |||
475 | #define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */ | 475 | #define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */ |
476 | #define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */ | 476 | #define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */ |
477 | 477 | ||
478 | #define dbcr_iac_range(task) ((task)->thread.dbcr1) | 478 | #define dbcr_iac_range(task) ((task)->thread.debug.dbcr1) |
479 | #define DBCR_IAC12I DBCR1_IAC12M /* Range Inclusive */ | 479 | #define DBCR_IAC12I DBCR1_IAC12M /* Range Inclusive */ |
480 | #define DBCR_IAC12X DBCR1_IAC12MX /* Range Exclusive */ | 480 | #define DBCR_IAC12X DBCR1_IAC12MX /* Range Exclusive */ |
481 | #define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */ | 481 | #define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */ |
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c index fda7f4020a33..95ba8095fc4a 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c | |||
@@ -113,7 +113,7 @@ int main(void) | |||
113 | #endif /* CONFIG_SPE */ | 113 | #endif /* CONFIG_SPE */ |
114 | #endif /* CONFIG_PPC64 */ | 114 | #endif /* CONFIG_PPC64 */ |
115 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) | 115 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) |
116 | DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, dbcr0)); | 116 | DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, debug.dbcr0)); |
117 | #endif | 117 | #endif |
118 | #ifdef CONFIG_KVM_BOOK3S_32_HANDLER | 118 | #ifdef CONFIG_KVM_BOOK3S_32_HANDLER |
119 | DEFINE(THREAD_KVM_SVCPU, offsetof(struct thread_struct, kvm_shadow_vcpu)); | 119 | DEFINE(THREAD_KVM_SVCPU, offsetof(struct thread_struct, kvm_shadow_vcpu)); |
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 8eb6e39b7343..a2b9231cfd48 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c | |||
@@ -314,28 +314,28 @@ static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); | |||
314 | */ | 314 | */ |
315 | static void set_debug_reg_defaults(struct thread_struct *thread) | 315 | static void set_debug_reg_defaults(struct thread_struct *thread) |
316 | { | 316 | { |
317 | thread->iac1 = thread->iac2 = 0; | 317 | thread->debug.iac1 = thread->debug.iac2 = 0; |
318 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | 318 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
319 | thread->iac3 = thread->iac4 = 0; | 319 | thread->debug.iac3 = thread->debug.iac4 = 0; |
320 | #endif | 320 | #endif |
321 | thread->dac1 = thread->dac2 = 0; | 321 | thread->debug.dac1 = thread->debug.dac2 = 0; |
322 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | 322 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
323 | thread->dvc1 = thread->dvc2 = 0; | 323 | thread->debug.dvc1 = thread->debug.dvc2 = 0; |
324 | #endif | 324 | #endif |
325 | thread->dbcr0 = 0; | 325 | thread->debug.dbcr0 = 0; |
326 | #ifdef CONFIG_BOOKE | 326 | #ifdef CONFIG_BOOKE |
327 | /* | 327 | /* |
328 | * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) | 328 | * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) |
329 | */ | 329 | */ |
330 | thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | | 330 | thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | |
331 | DBCR1_IAC3US | DBCR1_IAC4US; | 331 | DBCR1_IAC3US | DBCR1_IAC4US; |
332 | /* | 332 | /* |
333 | * Force Data Address Compare User/Supervisor bits to be User-only | 333 | * Force Data Address Compare User/Supervisor bits to be User-only |
334 | * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. | 334 | * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. |
335 | */ | 335 | */ |
336 | thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; | 336 | thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; |
337 | #else | 337 | #else |
338 | thread->dbcr1 = 0; | 338 | thread->debug.dbcr1 = 0; |
339 | #endif | 339 | #endif |
340 | } | 340 | } |
341 | 341 | ||
@@ -348,22 +348,22 @@ static void prime_debug_regs(struct thread_struct *thread) | |||
348 | */ | 348 | */ |
349 | mtmsr(mfmsr() & ~MSR_DE); | 349 | mtmsr(mfmsr() & ~MSR_DE); |
350 | 350 | ||
351 | mtspr(SPRN_IAC1, thread->iac1); | 351 | mtspr(SPRN_IAC1, thread->debug.iac1); |
352 | mtspr(SPRN_IAC2, thread->iac2); | 352 | mtspr(SPRN_IAC2, thread->debug.iac2); |
353 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | 353 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
354 | mtspr(SPRN_IAC3, thread->iac3); | 354 | mtspr(SPRN_IAC3, thread->debug.iac3); |
355 | mtspr(SPRN_IAC4, thread->iac4); | 355 | mtspr(SPRN_IAC4, thread->debug.iac4); |
356 | #endif | 356 | #endif |
357 | mtspr(SPRN_DAC1, thread->dac1); | 357 | mtspr(SPRN_DAC1, thread->debug.dac1); |
358 | mtspr(SPRN_DAC2, thread->dac2); | 358 | mtspr(SPRN_DAC2, thread->debug.dac2); |
359 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | 359 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
360 | mtspr(SPRN_DVC1, thread->dvc1); | 360 | mtspr(SPRN_DVC1, thread->debug.dvc1); |
361 | mtspr(SPRN_DVC2, thread->dvc2); | 361 | mtspr(SPRN_DVC2, thread->debug.dvc2); |
362 | #endif | 362 | #endif |
363 | mtspr(SPRN_DBCR0, thread->dbcr0); | 363 | mtspr(SPRN_DBCR0, thread->debug.dbcr0); |
364 | mtspr(SPRN_DBCR1, thread->dbcr1); | 364 | mtspr(SPRN_DBCR1, thread->debug.dbcr1); |
365 | #ifdef CONFIG_BOOKE | 365 | #ifdef CONFIG_BOOKE |
366 | mtspr(SPRN_DBCR2, thread->dbcr2); | 366 | mtspr(SPRN_DBCR2, thread->debug.dbcr2); |
367 | #endif | 367 | #endif |
368 | } | 368 | } |
369 | /* | 369 | /* |
@@ -373,8 +373,8 @@ static void prime_debug_regs(struct thread_struct *thread) | |||
373 | */ | 373 | */ |
374 | static void switch_booke_debug_regs(struct thread_struct *new_thread) | 374 | static void switch_booke_debug_regs(struct thread_struct *new_thread) |
375 | { | 375 | { |
376 | if ((current->thread.dbcr0 & DBCR0_IDM) | 376 | if ((current->thread.debug.dbcr0 & DBCR0_IDM) |
377 | || (new_thread->dbcr0 & DBCR0_IDM)) | 377 | || (new_thread->debug.dbcr0 & DBCR0_IDM)) |
378 | prime_debug_regs(new_thread); | 378 | prime_debug_regs(new_thread); |
379 | } | 379 | } |
380 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ | 380 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ |
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c index 9a0d24c390a3..ddaf1780879c 100644 --- a/arch/powerpc/kernel/ptrace.c +++ b/arch/powerpc/kernel/ptrace.c | |||
@@ -854,8 +854,8 @@ void user_enable_single_step(struct task_struct *task) | |||
854 | 854 | ||
855 | if (regs != NULL) { | 855 | if (regs != NULL) { |
856 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS | 856 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
857 | task->thread.dbcr0 &= ~DBCR0_BT; | 857 | task->thread.debug.dbcr0 &= ~DBCR0_BT; |
858 | task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; | 858 | task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; |
859 | regs->msr |= MSR_DE; | 859 | regs->msr |= MSR_DE; |
860 | #else | 860 | #else |
861 | regs->msr &= ~MSR_BE; | 861 | regs->msr &= ~MSR_BE; |
@@ -871,8 +871,8 @@ void user_enable_block_step(struct task_struct *task) | |||
871 | 871 | ||
872 | if (regs != NULL) { | 872 | if (regs != NULL) { |
873 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS | 873 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
874 | task->thread.dbcr0 &= ~DBCR0_IC; | 874 | task->thread.debug.dbcr0 &= ~DBCR0_IC; |
875 | task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT; | 875 | task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT; |
876 | regs->msr |= MSR_DE; | 876 | regs->msr |= MSR_DE; |
877 | #else | 877 | #else |
878 | regs->msr &= ~MSR_SE; | 878 | regs->msr &= ~MSR_SE; |
@@ -894,16 +894,16 @@ void user_disable_single_step(struct task_struct *task) | |||
894 | * And, after doing so, if all debug flags are off, turn | 894 | * And, after doing so, if all debug flags are off, turn |
895 | * off DBCR0(IDM) and MSR(DE) .... Torez | 895 | * off DBCR0(IDM) and MSR(DE) .... Torez |
896 | */ | 896 | */ |
897 | task->thread.dbcr0 &= ~DBCR0_IC; | 897 | task->thread.debug.dbcr0 &= ~DBCR0_IC; |
898 | /* | 898 | /* |
899 | * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set. | 899 | * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set. |
900 | */ | 900 | */ |
901 | if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0, | 901 | if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, |
902 | task->thread.dbcr1)) { | 902 | task->thread.debug.dbcr1)) { |
903 | /* | 903 | /* |
904 | * All debug events were off..... | 904 | * All debug events were off..... |
905 | */ | 905 | */ |
906 | task->thread.dbcr0 &= ~DBCR0_IDM; | 906 | task->thread.debug.dbcr0 &= ~DBCR0_IDM; |
907 | regs->msr &= ~MSR_DE; | 907 | regs->msr &= ~MSR_DE; |
908 | } | 908 | } |
909 | #else | 909 | #else |
@@ -1022,14 +1022,14 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, | |||
1022 | */ | 1022 | */ |
1023 | 1023 | ||
1024 | /* DAC's hold the whole address without any mode flags */ | 1024 | /* DAC's hold the whole address without any mode flags */ |
1025 | task->thread.dac1 = data & ~0x3UL; | 1025 | task->thread.debug.dac1 = data & ~0x3UL; |
1026 | 1026 | ||
1027 | if (task->thread.dac1 == 0) { | 1027 | if (task->thread.debug.dac1 == 0) { |
1028 | dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W); | 1028 | dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
1029 | if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0, | 1029 | if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, |
1030 | task->thread.dbcr1)) { | 1030 | task->thread.debug.dbcr1)) { |
1031 | task->thread.regs->msr &= ~MSR_DE; | 1031 | task->thread.regs->msr &= ~MSR_DE; |
1032 | task->thread.dbcr0 &= ~DBCR0_IDM; | 1032 | task->thread.debug.dbcr0 &= ~DBCR0_IDM; |
1033 | } | 1033 | } |
1034 | return 0; | 1034 | return 0; |
1035 | } | 1035 | } |
@@ -1041,7 +1041,7 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, | |||
1041 | 1041 | ||
1042 | /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0 | 1042 | /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0 |
1043 | register */ | 1043 | register */ |
1044 | task->thread.dbcr0 |= DBCR0_IDM; | 1044 | task->thread.debug.dbcr0 |= DBCR0_IDM; |
1045 | 1045 | ||
1046 | /* Check for write and read flags and set DBCR0 | 1046 | /* Check for write and read flags and set DBCR0 |
1047 | accordingly */ | 1047 | accordingly */ |
@@ -1071,10 +1071,10 @@ static long set_instruction_bp(struct task_struct *child, | |||
1071 | struct ppc_hw_breakpoint *bp_info) | 1071 | struct ppc_hw_breakpoint *bp_info) |
1072 | { | 1072 | { |
1073 | int slot; | 1073 | int slot; |
1074 | int slot1_in_use = ((child->thread.dbcr0 & DBCR0_IAC1) != 0); | 1074 | int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0); |
1075 | int slot2_in_use = ((child->thread.dbcr0 & DBCR0_IAC2) != 0); | 1075 | int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0); |
1076 | int slot3_in_use = ((child->thread.dbcr0 & DBCR0_IAC3) != 0); | 1076 | int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0); |
1077 | int slot4_in_use = ((child->thread.dbcr0 & DBCR0_IAC4) != 0); | 1077 | int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0); |
1078 | 1078 | ||
1079 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) | 1079 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) |
1080 | slot2_in_use = 1; | 1080 | slot2_in_use = 1; |
@@ -1093,9 +1093,9 @@ static long set_instruction_bp(struct task_struct *child, | |||
1093 | /* We need a pair of IAC regsisters */ | 1093 | /* We need a pair of IAC regsisters */ |
1094 | if ((!slot1_in_use) && (!slot2_in_use)) { | 1094 | if ((!slot1_in_use) && (!slot2_in_use)) { |
1095 | slot = 1; | 1095 | slot = 1; |
1096 | child->thread.iac1 = bp_info->addr; | 1096 | child->thread.debug.iac1 = bp_info->addr; |
1097 | child->thread.iac2 = bp_info->addr2; | 1097 | child->thread.debug.iac2 = bp_info->addr2; |
1098 | child->thread.dbcr0 |= DBCR0_IAC1; | 1098 | child->thread.debug.dbcr0 |= DBCR0_IAC1; |
1099 | if (bp_info->addr_mode == | 1099 | if (bp_info->addr_mode == |
1100 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | 1100 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) |
1101 | dbcr_iac_range(child) |= DBCR_IAC12X; | 1101 | dbcr_iac_range(child) |= DBCR_IAC12X; |
@@ -1104,9 +1104,9 @@ static long set_instruction_bp(struct task_struct *child, | |||
1104 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | 1104 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
1105 | } else if ((!slot3_in_use) && (!slot4_in_use)) { | 1105 | } else if ((!slot3_in_use) && (!slot4_in_use)) { |
1106 | slot = 3; | 1106 | slot = 3; |
1107 | child->thread.iac3 = bp_info->addr; | 1107 | child->thread.debug.iac3 = bp_info->addr; |
1108 | child->thread.iac4 = bp_info->addr2; | 1108 | child->thread.debug.iac4 = bp_info->addr2; |
1109 | child->thread.dbcr0 |= DBCR0_IAC3; | 1109 | child->thread.debug.dbcr0 |= DBCR0_IAC3; |
1110 | if (bp_info->addr_mode == | 1110 | if (bp_info->addr_mode == |
1111 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | 1111 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) |
1112 | dbcr_iac_range(child) |= DBCR_IAC34X; | 1112 | dbcr_iac_range(child) |= DBCR_IAC34X; |
@@ -1126,30 +1126,30 @@ static long set_instruction_bp(struct task_struct *child, | |||
1126 | */ | 1126 | */ |
1127 | if (slot2_in_use || (slot3_in_use == slot4_in_use)) { | 1127 | if (slot2_in_use || (slot3_in_use == slot4_in_use)) { |
1128 | slot = 1; | 1128 | slot = 1; |
1129 | child->thread.iac1 = bp_info->addr; | 1129 | child->thread.debug.iac1 = bp_info->addr; |
1130 | child->thread.dbcr0 |= DBCR0_IAC1; | 1130 | child->thread.debug.dbcr0 |= DBCR0_IAC1; |
1131 | goto out; | 1131 | goto out; |
1132 | } | 1132 | } |
1133 | } | 1133 | } |
1134 | if (!slot2_in_use) { | 1134 | if (!slot2_in_use) { |
1135 | slot = 2; | 1135 | slot = 2; |
1136 | child->thread.iac2 = bp_info->addr; | 1136 | child->thread.debug.iac2 = bp_info->addr; |
1137 | child->thread.dbcr0 |= DBCR0_IAC2; | 1137 | child->thread.debug.dbcr0 |= DBCR0_IAC2; |
1138 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | 1138 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
1139 | } else if (!slot3_in_use) { | 1139 | } else if (!slot3_in_use) { |
1140 | slot = 3; | 1140 | slot = 3; |
1141 | child->thread.iac3 = bp_info->addr; | 1141 | child->thread.debug.iac3 = bp_info->addr; |
1142 | child->thread.dbcr0 |= DBCR0_IAC3; | 1142 | child->thread.debug.dbcr0 |= DBCR0_IAC3; |
1143 | } else if (!slot4_in_use) { | 1143 | } else if (!slot4_in_use) { |
1144 | slot = 4; | 1144 | slot = 4; |
1145 | child->thread.iac4 = bp_info->addr; | 1145 | child->thread.debug.iac4 = bp_info->addr; |
1146 | child->thread.dbcr0 |= DBCR0_IAC4; | 1146 | child->thread.debug.dbcr0 |= DBCR0_IAC4; |
1147 | #endif | 1147 | #endif |
1148 | } else | 1148 | } else |
1149 | return -ENOSPC; | 1149 | return -ENOSPC; |
1150 | } | 1150 | } |
1151 | out: | 1151 | out: |
1152 | child->thread.dbcr0 |= DBCR0_IDM; | 1152 | child->thread.debug.dbcr0 |= DBCR0_IDM; |
1153 | child->thread.regs->msr |= MSR_DE; | 1153 | child->thread.regs->msr |= MSR_DE; |
1154 | 1154 | ||
1155 | return slot; | 1155 | return slot; |
@@ -1159,49 +1159,49 @@ static int del_instruction_bp(struct task_struct *child, int slot) | |||
1159 | { | 1159 | { |
1160 | switch (slot) { | 1160 | switch (slot) { |
1161 | case 1: | 1161 | case 1: |
1162 | if ((child->thread.dbcr0 & DBCR0_IAC1) == 0) | 1162 | if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0) |
1163 | return -ENOENT; | 1163 | return -ENOENT; |
1164 | 1164 | ||
1165 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) { | 1165 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) { |
1166 | /* address range - clear slots 1 & 2 */ | 1166 | /* address range - clear slots 1 & 2 */ |
1167 | child->thread.iac2 = 0; | 1167 | child->thread.debug.iac2 = 0; |
1168 | dbcr_iac_range(child) &= ~DBCR_IAC12MODE; | 1168 | dbcr_iac_range(child) &= ~DBCR_IAC12MODE; |
1169 | } | 1169 | } |
1170 | child->thread.iac1 = 0; | 1170 | child->thread.debug.iac1 = 0; |
1171 | child->thread.dbcr0 &= ~DBCR0_IAC1; | 1171 | child->thread.debug.dbcr0 &= ~DBCR0_IAC1; |
1172 | break; | 1172 | break; |
1173 | case 2: | 1173 | case 2: |
1174 | if ((child->thread.dbcr0 & DBCR0_IAC2) == 0) | 1174 | if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0) |
1175 | return -ENOENT; | 1175 | return -ENOENT; |
1176 | 1176 | ||
1177 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) | 1177 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) |
1178 | /* used in a range */ | 1178 | /* used in a range */ |
1179 | return -EINVAL; | 1179 | return -EINVAL; |
1180 | child->thread.iac2 = 0; | 1180 | child->thread.debug.iac2 = 0; |
1181 | child->thread.dbcr0 &= ~DBCR0_IAC2; | 1181 | child->thread.debug.dbcr0 &= ~DBCR0_IAC2; |
1182 | break; | 1182 | break; |
1183 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | 1183 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
1184 | case 3: | 1184 | case 3: |
1185 | if ((child->thread.dbcr0 & DBCR0_IAC3) == 0) | 1185 | if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0) |
1186 | return -ENOENT; | 1186 | return -ENOENT; |
1187 | 1187 | ||
1188 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) { | 1188 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) { |
1189 | /* address range - clear slots 3 & 4 */ | 1189 | /* address range - clear slots 3 & 4 */ |
1190 | child->thread.iac4 = 0; | 1190 | child->thread.debug.iac4 = 0; |
1191 | dbcr_iac_range(child) &= ~DBCR_IAC34MODE; | 1191 | dbcr_iac_range(child) &= ~DBCR_IAC34MODE; |
1192 | } | 1192 | } |
1193 | child->thread.iac3 = 0; | 1193 | child->thread.debug.iac3 = 0; |
1194 | child->thread.dbcr0 &= ~DBCR0_IAC3; | 1194 | child->thread.debug.dbcr0 &= ~DBCR0_IAC3; |
1195 | break; | 1195 | break; |
1196 | case 4: | 1196 | case 4: |
1197 | if ((child->thread.dbcr0 & DBCR0_IAC4) == 0) | 1197 | if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0) |
1198 | return -ENOENT; | 1198 | return -ENOENT; |
1199 | 1199 | ||
1200 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) | 1200 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) |
1201 | /* Used in a range */ | 1201 | /* Used in a range */ |
1202 | return -EINVAL; | 1202 | return -EINVAL; |
1203 | child->thread.iac4 = 0; | 1203 | child->thread.debug.iac4 = 0; |
1204 | child->thread.dbcr0 &= ~DBCR0_IAC4; | 1204 | child->thread.debug.dbcr0 &= ~DBCR0_IAC4; |
1205 | break; | 1205 | break; |
1206 | #endif | 1206 | #endif |
1207 | default: | 1207 | default: |
@@ -1231,18 +1231,18 @@ static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info) | |||
1231 | dbcr_dac(child) |= DBCR_DAC1R; | 1231 | dbcr_dac(child) |= DBCR_DAC1R; |
1232 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | 1232 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
1233 | dbcr_dac(child) |= DBCR_DAC1W; | 1233 | dbcr_dac(child) |= DBCR_DAC1W; |
1234 | child->thread.dac1 = (unsigned long)bp_info->addr; | 1234 | child->thread.debug.dac1 = (unsigned long)bp_info->addr; |
1235 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | 1235 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
1236 | if (byte_enable) { | 1236 | if (byte_enable) { |
1237 | child->thread.dvc1 = | 1237 | child->thread.debug.dvc1 = |
1238 | (unsigned long)bp_info->condition_value; | 1238 | (unsigned long)bp_info->condition_value; |
1239 | child->thread.dbcr2 |= | 1239 | child->thread.debug.dbcr2 |= |
1240 | ((byte_enable << DBCR2_DVC1BE_SHIFT) | | 1240 | ((byte_enable << DBCR2_DVC1BE_SHIFT) | |
1241 | (condition_mode << DBCR2_DVC1M_SHIFT)); | 1241 | (condition_mode << DBCR2_DVC1M_SHIFT)); |
1242 | } | 1242 | } |
1243 | #endif | 1243 | #endif |
1244 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | 1244 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE |
1245 | } else if (child->thread.dbcr2 & DBCR2_DAC12MODE) { | 1245 | } else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) { |
1246 | /* Both dac1 and dac2 are part of a range */ | 1246 | /* Both dac1 and dac2 are part of a range */ |
1247 | return -ENOSPC; | 1247 | return -ENOSPC; |
1248 | #endif | 1248 | #endif |
@@ -1252,19 +1252,19 @@ static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info) | |||
1252 | dbcr_dac(child) |= DBCR_DAC2R; | 1252 | dbcr_dac(child) |= DBCR_DAC2R; |
1253 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | 1253 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
1254 | dbcr_dac(child) |= DBCR_DAC2W; | 1254 | dbcr_dac(child) |= DBCR_DAC2W; |
1255 | child->thread.dac2 = (unsigned long)bp_info->addr; | 1255 | child->thread.debug.dac2 = (unsigned long)bp_info->addr; |
1256 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | 1256 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
1257 | if (byte_enable) { | 1257 | if (byte_enable) { |
1258 | child->thread.dvc2 = | 1258 | child->thread.debug.dvc2 = |
1259 | (unsigned long)bp_info->condition_value; | 1259 | (unsigned long)bp_info->condition_value; |
1260 | child->thread.dbcr2 |= | 1260 | child->thread.debug.dbcr2 |= |
1261 | ((byte_enable << DBCR2_DVC2BE_SHIFT) | | 1261 | ((byte_enable << DBCR2_DVC2BE_SHIFT) | |
1262 | (condition_mode << DBCR2_DVC2M_SHIFT)); | 1262 | (condition_mode << DBCR2_DVC2M_SHIFT)); |
1263 | } | 1263 | } |
1264 | #endif | 1264 | #endif |
1265 | } else | 1265 | } else |
1266 | return -ENOSPC; | 1266 | return -ENOSPC; |
1267 | child->thread.dbcr0 |= DBCR0_IDM; | 1267 | child->thread.debug.dbcr0 |= DBCR0_IDM; |
1268 | child->thread.regs->msr |= MSR_DE; | 1268 | child->thread.regs->msr |= MSR_DE; |
1269 | 1269 | ||
1270 | return slot + 4; | 1270 | return slot + 4; |
@@ -1276,32 +1276,32 @@ static int del_dac(struct task_struct *child, int slot) | |||
1276 | if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) | 1276 | if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) |
1277 | return -ENOENT; | 1277 | return -ENOENT; |
1278 | 1278 | ||
1279 | child->thread.dac1 = 0; | 1279 | child->thread.debug.dac1 = 0; |
1280 | dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W); | 1280 | dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
1281 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | 1281 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE |
1282 | if (child->thread.dbcr2 & DBCR2_DAC12MODE) { | 1282 | if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) { |
1283 | child->thread.dac2 = 0; | 1283 | child->thread.debug.dac2 = 0; |
1284 | child->thread.dbcr2 &= ~DBCR2_DAC12MODE; | 1284 | child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; |
1285 | } | 1285 | } |
1286 | child->thread.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE); | 1286 | child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE); |
1287 | #endif | 1287 | #endif |
1288 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | 1288 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
1289 | child->thread.dvc1 = 0; | 1289 | child->thread.debug.dvc1 = 0; |
1290 | #endif | 1290 | #endif |
1291 | } else if (slot == 2) { | 1291 | } else if (slot == 2) { |
1292 | if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) | 1292 | if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) |
1293 | return -ENOENT; | 1293 | return -ENOENT; |
1294 | 1294 | ||
1295 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | 1295 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE |
1296 | if (child->thread.dbcr2 & DBCR2_DAC12MODE) | 1296 | if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) |
1297 | /* Part of a range */ | 1297 | /* Part of a range */ |
1298 | return -EINVAL; | 1298 | return -EINVAL; |
1299 | child->thread.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE); | 1299 | child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE); |
1300 | #endif | 1300 | #endif |
1301 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | 1301 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
1302 | child->thread.dvc2 = 0; | 1302 | child->thread.debug.dvc2 = 0; |
1303 | #endif | 1303 | #endif |
1304 | child->thread.dac2 = 0; | 1304 | child->thread.debug.dac2 = 0; |
1305 | dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W); | 1305 | dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W); |
1306 | } else | 1306 | } else |
1307 | return -EINVAL; | 1307 | return -EINVAL; |
@@ -1343,22 +1343,22 @@ static int set_dac_range(struct task_struct *child, | |||
1343 | return -EIO; | 1343 | return -EIO; |
1344 | } | 1344 | } |
1345 | 1345 | ||
1346 | if (child->thread.dbcr0 & | 1346 | if (child->thread.debug.dbcr0 & |
1347 | (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)) | 1347 | (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)) |
1348 | return -ENOSPC; | 1348 | return -ENOSPC; |
1349 | 1349 | ||
1350 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | 1350 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) |
1351 | child->thread.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM); | 1351 | child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM); |
1352 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | 1352 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
1353 | child->thread.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM); | 1353 | child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM); |
1354 | child->thread.dac1 = bp_info->addr; | 1354 | child->thread.debug.dac1 = bp_info->addr; |
1355 | child->thread.dac2 = bp_info->addr2; | 1355 | child->thread.debug.dac2 = bp_info->addr2; |
1356 | if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) | 1356 | if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) |
1357 | child->thread.dbcr2 |= DBCR2_DAC12M; | 1357 | child->thread.debug.dbcr2 |= DBCR2_DAC12M; |
1358 | else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | 1358 | else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) |
1359 | child->thread.dbcr2 |= DBCR2_DAC12MX; | 1359 | child->thread.debug.dbcr2 |= DBCR2_DAC12MX; |
1360 | else /* PPC_BREAKPOINT_MODE_MASK */ | 1360 | else /* PPC_BREAKPOINT_MODE_MASK */ |
1361 | child->thread.dbcr2 |= DBCR2_DAC12MM; | 1361 | child->thread.debug.dbcr2 |= DBCR2_DAC12MM; |
1362 | child->thread.regs->msr |= MSR_DE; | 1362 | child->thread.regs->msr |= MSR_DE; |
1363 | 1363 | ||
1364 | return 5; | 1364 | return 5; |
@@ -1489,9 +1489,9 @@ static long ppc_del_hwdebug(struct task_struct *child, long data) | |||
1489 | rc = del_dac(child, (int)data - 4); | 1489 | rc = del_dac(child, (int)data - 4); |
1490 | 1490 | ||
1491 | if (!rc) { | 1491 | if (!rc) { |
1492 | if (!DBCR_ACTIVE_EVENTS(child->thread.dbcr0, | 1492 | if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0, |
1493 | child->thread.dbcr1)) { | 1493 | child->thread.debug.dbcr1)) { |
1494 | child->thread.dbcr0 &= ~DBCR0_IDM; | 1494 | child->thread.debug.dbcr0 &= ~DBCR0_IDM; |
1495 | child->thread.regs->msr &= ~MSR_DE; | 1495 | child->thread.regs->msr &= ~MSR_DE; |
1496 | } | 1496 | } |
1497 | } | 1497 | } |
@@ -1669,7 +1669,7 @@ long arch_ptrace(struct task_struct *child, long request, | |||
1669 | if (addr > 0) | 1669 | if (addr > 0) |
1670 | break; | 1670 | break; |
1671 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS | 1671 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
1672 | ret = put_user(child->thread.dac1, datalp); | 1672 | ret = put_user(child->thread.debug.dac1, datalp); |
1673 | #else | 1673 | #else |
1674 | dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) | | 1674 | dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) | |
1675 | (child->thread.hw_brk.type & HW_BRK_TYPE_DABR)); | 1675 | (child->thread.hw_brk.type & HW_BRK_TYPE_DABR)); |
diff --git a/arch/powerpc/kernel/ptrace32.c b/arch/powerpc/kernel/ptrace32.c index f51599e941c7..18c7c65ea46d 100644 --- a/arch/powerpc/kernel/ptrace32.c +++ b/arch/powerpc/kernel/ptrace32.c | |||
@@ -269,7 +269,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, | |||
269 | if (addr > 0) | 269 | if (addr > 0) |
270 | break; | 270 | break; |
271 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS | 271 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
272 | ret = put_user(child->thread.dac1, (u32 __user *)data); | 272 | ret = put_user(child->thread.debug.dac1, (u32 __user *)data); |
273 | #else | 273 | #else |
274 | dabr_fake = ( | 274 | dabr_fake = ( |
275 | (child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) | | 275 | (child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) | |
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c index bebdf1a1a540..3f220d93c72f 100644 --- a/arch/powerpc/kernel/signal_32.c +++ b/arch/powerpc/kernel/signal_32.c | |||
@@ -1309,7 +1309,7 @@ int sys_debug_setcontext(struct ucontext __user *ctx, | |||
1309 | unsigned char tmp; | 1309 | unsigned char tmp; |
1310 | unsigned long new_msr = regs->msr; | 1310 | unsigned long new_msr = regs->msr; |
1311 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS | 1311 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
1312 | unsigned long new_dbcr0 = current->thread.dbcr0; | 1312 | unsigned long new_dbcr0 = current->thread.debug.dbcr0; |
1313 | #endif | 1313 | #endif |
1314 | 1314 | ||
1315 | for (i=0; i<ndbg; i++) { | 1315 | for (i=0; i<ndbg; i++) { |
@@ -1324,7 +1324,7 @@ int sys_debug_setcontext(struct ucontext __user *ctx, | |||
1324 | } else { | 1324 | } else { |
1325 | new_dbcr0 &= ~DBCR0_IC; | 1325 | new_dbcr0 &= ~DBCR0_IC; |
1326 | if (!DBCR_ACTIVE_EVENTS(new_dbcr0, | 1326 | if (!DBCR_ACTIVE_EVENTS(new_dbcr0, |
1327 | current->thread.dbcr1)) { | 1327 | current->thread.debug.dbcr1)) { |
1328 | new_msr &= ~MSR_DE; | 1328 | new_msr &= ~MSR_DE; |
1329 | new_dbcr0 &= ~DBCR0_IDM; | 1329 | new_dbcr0 &= ~DBCR0_IDM; |
1330 | } | 1330 | } |
@@ -1359,7 +1359,7 @@ int sys_debug_setcontext(struct ucontext __user *ctx, | |||
1359 | the user is really doing something wrong. */ | 1359 | the user is really doing something wrong. */ |
1360 | regs->msr = new_msr; | 1360 | regs->msr = new_msr; |
1361 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS | 1361 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
1362 | current->thread.dbcr0 = new_dbcr0; | 1362 | current->thread.debug.dbcr0 = new_dbcr0; |
1363 | #endif | 1363 | #endif |
1364 | 1364 | ||
1365 | if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx)) | 1365 | if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx)) |
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index f783c932faeb..4f5df4e7df12 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c | |||
@@ -351,8 +351,8 @@ static inline int check_io_access(struct pt_regs *regs) | |||
351 | #define REASON_TRAP ESR_PTR | 351 | #define REASON_TRAP ESR_PTR |
352 | 352 | ||
353 | /* single-step stuff */ | 353 | /* single-step stuff */ |
354 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) | 354 | #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) |
355 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) | 355 | #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) |
356 | 356 | ||
357 | #else | 357 | #else |
358 | /* On non-4xx, the reason for the machine check or program | 358 | /* On non-4xx, the reason for the machine check or program |
@@ -1486,7 +1486,7 @@ static void handle_debug(struct pt_regs *regs, unsigned long debug_status) | |||
1486 | if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { | 1486 | if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { |
1487 | dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); | 1487 | dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
1488 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | 1488 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE |
1489 | current->thread.dbcr2 &= ~DBCR2_DAC12MODE; | 1489 | current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; |
1490 | #endif | 1490 | #endif |
1491 | do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, | 1491 | do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, |
1492 | 5); | 1492 | 5); |
@@ -1497,24 +1497,24 @@ static void handle_debug(struct pt_regs *regs, unsigned long debug_status) | |||
1497 | 6); | 1497 | 6); |
1498 | changed |= 0x01; | 1498 | changed |= 0x01; |
1499 | } else if (debug_status & DBSR_IAC1) { | 1499 | } else if (debug_status & DBSR_IAC1) { |
1500 | current->thread.dbcr0 &= ~DBCR0_IAC1; | 1500 | current->thread.debug.dbcr0 &= ~DBCR0_IAC1; |
1501 | dbcr_iac_range(current) &= ~DBCR_IAC12MODE; | 1501 | dbcr_iac_range(current) &= ~DBCR_IAC12MODE; |
1502 | do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, | 1502 | do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, |
1503 | 1); | 1503 | 1); |
1504 | changed |= 0x01; | 1504 | changed |= 0x01; |
1505 | } else if (debug_status & DBSR_IAC2) { | 1505 | } else if (debug_status & DBSR_IAC2) { |
1506 | current->thread.dbcr0 &= ~DBCR0_IAC2; | 1506 | current->thread.debug.dbcr0 &= ~DBCR0_IAC2; |
1507 | do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, | 1507 | do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, |
1508 | 2); | 1508 | 2); |
1509 | changed |= 0x01; | 1509 | changed |= 0x01; |
1510 | } else if (debug_status & DBSR_IAC3) { | 1510 | } else if (debug_status & DBSR_IAC3) { |
1511 | current->thread.dbcr0 &= ~DBCR0_IAC3; | 1511 | current->thread.debug.dbcr0 &= ~DBCR0_IAC3; |
1512 | dbcr_iac_range(current) &= ~DBCR_IAC34MODE; | 1512 | dbcr_iac_range(current) &= ~DBCR_IAC34MODE; |
1513 | do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, | 1513 | do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, |
1514 | 3); | 1514 | 3); |
1515 | changed |= 0x01; | 1515 | changed |= 0x01; |
1516 | } else if (debug_status & DBSR_IAC4) { | 1516 | } else if (debug_status & DBSR_IAC4) { |
1517 | current->thread.dbcr0 &= ~DBCR0_IAC4; | 1517 | current->thread.debug.dbcr0 &= ~DBCR0_IAC4; |
1518 | do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, | 1518 | do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, |
1519 | 4); | 1519 | 4); |
1520 | changed |= 0x01; | 1520 | changed |= 0x01; |
@@ -1524,19 +1524,20 @@ static void handle_debug(struct pt_regs *regs, unsigned long debug_status) | |||
1524 | * Check all other debug flags and see if that bit needs to be turned | 1524 | * Check all other debug flags and see if that bit needs to be turned |
1525 | * back on or not. | 1525 | * back on or not. |
1526 | */ | 1526 | */ |
1527 | if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1)) | 1527 | if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, |
1528 | current->thread.debug.dbcr1)) | ||
1528 | regs->msr |= MSR_DE; | 1529 | regs->msr |= MSR_DE; |
1529 | else | 1530 | else |
1530 | /* Make sure the IDM flag is off */ | 1531 | /* Make sure the IDM flag is off */ |
1531 | current->thread.dbcr0 &= ~DBCR0_IDM; | 1532 | current->thread.debug.dbcr0 &= ~DBCR0_IDM; |
1532 | 1533 | ||
1533 | if (changed & 0x01) | 1534 | if (changed & 0x01) |
1534 | mtspr(SPRN_DBCR0, current->thread.dbcr0); | 1535 | mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); |
1535 | } | 1536 | } |
1536 | 1537 | ||
1537 | void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) | 1538 | void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) |
1538 | { | 1539 | { |
1539 | current->thread.dbsr = debug_status; | 1540 | current->thread.debug.dbsr = debug_status; |
1540 | 1541 | ||
1541 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while | 1542 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while |
1542 | * on server, it stops on the target of the branch. In order to simulate | 1543 | * on server, it stops on the target of the branch. In order to simulate |
@@ -1553,8 +1554,8 @@ void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) | |||
1553 | 1554 | ||
1554 | /* Do the single step trick only when coming from userspace */ | 1555 | /* Do the single step trick only when coming from userspace */ |
1555 | if (user_mode(regs)) { | 1556 | if (user_mode(regs)) { |
1556 | current->thread.dbcr0 &= ~DBCR0_BT; | 1557 | current->thread.debug.dbcr0 &= ~DBCR0_BT; |
1557 | current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; | 1558 | current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; |
1558 | regs->msr |= MSR_DE; | 1559 | regs->msr |= MSR_DE; |
1559 | return; | 1560 | return; |
1560 | } | 1561 | } |
@@ -1582,13 +1583,13 @@ void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) | |||
1582 | return; | 1583 | return; |
1583 | 1584 | ||
1584 | if (user_mode(regs)) { | 1585 | if (user_mode(regs)) { |
1585 | current->thread.dbcr0 &= ~DBCR0_IC; | 1586 | current->thread.debug.dbcr0 &= ~DBCR0_IC; |
1586 | if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, | 1587 | if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, |
1587 | current->thread.dbcr1)) | 1588 | current->thread.debug.dbcr1)) |
1588 | regs->msr |= MSR_DE; | 1589 | regs->msr |= MSR_DE; |
1589 | else | 1590 | else |
1590 | /* Make sure the IDM bit is off */ | 1591 | /* Make sure the IDM bit is off */ |
1591 | current->thread.dbcr0 &= ~DBCR0_IDM; | 1592 | current->thread.debug.dbcr0 &= ~DBCR0_IDM; |
1592 | } | 1593 | } |
1593 | 1594 | ||
1594 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | 1595 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); |