14 files changed, 346 insertions, 74 deletions

diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
index 0a5bea9e3585..987a165ede26 100644
--- a/drivers/cpufreq/cpufreq.c
+++ b/drivers/cpufreq/cpufreq.c
@@ -1199,6 +1199,26 @@ unsigned int cpufreq_quick_get(unsigned int cpu)
 }
 EXPORT_SYMBOL(cpufreq_quick_get);
 
+/**
+ * cpufreq_quick_get_max - get the max reported CPU frequency for this CPU
+ * @cpu: CPU number
+ *
+ * Just return the max possible frequency for a given CPU.
+ */
+unsigned int cpufreq_quick_get_max(unsigned int cpu)
+{
+        struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
+        unsigned int ret_freq = 0;
+
+        if (policy) {
+                ret_freq = policy->max;
+                cpufreq_cpu_put(policy);
+        }
+
+        return ret_freq;
+}
+EXPORT_SYMBOL(cpufreq_quick_get_max);
+
 
 static unsigned int __cpufreq_get(unsigned int cpu)
 {
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4d46441cbe2d..8a5a032ec696 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1123,6 +1123,44 @@ static int i915_emon_status(struct seq_file *m, void *unused)
         return 0;
 }
 
+static int i915_ring_freq_table(struct seq_file *m, void *unused)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        int ret;
+        int gpu_freq, ia_freq;
+
+        if (!IS_GEN6(dev)) {
+                seq_printf(m, "unsupported on this chipset\n");
+                return 0;
+        }
+
+        ret = mutex_lock_interruptible(&dev->struct_mutex);
+        if (ret)
+                return ret;
+
+        seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
+
+        for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay;
+             gpu_freq++) {
+                I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
+                I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
+                           GEN6_PCODE_READ_MIN_FREQ_TABLE);
+                if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
+                              GEN6_PCODE_READY) == 0, 10)) {
+                        DRM_ERROR("pcode read of freq table timed out\n");
+                        continue;
+                }
+                ia_freq = I915_READ(GEN6_PCODE_DATA);
+                seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
+        }
+
+        mutex_unlock(&dev->struct_mutex);
+
+        return 0;
+}
+
 static int i915_gfxec(struct seq_file *m, void *unused)
 {
         struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -1426,6 +1464,7 @@ static struct drm_info_list i915_debugfs_list[] = {
         {"i915_inttoext_table", i915_inttoext_table, 0},
         {"i915_drpc_info", i915_drpc_info, 0},
         {"i915_emon_status", i915_emon_status, 0},
+        {"i915_ring_freq_table", i915_ring_freq_table, 0},
         {"i915_gfxec", i915_gfxec, 0},
         {"i915_fbc_status", i915_fbc_status, 0},
         {"i915_sr_status", i915_sr_status, 0},
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 609358faaa90..b54f7d9b173a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -70,6 +70,9 @@ module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 static bool i915_try_reset = true;
 module_param_named(reset, i915_try_reset, bool, 0600);
 
+bool i915_enable_hangcheck = true;
+module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
+
 static struct drm_driver driver;
 extern int intel_agp_enabled;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index eddabf68e97a..e0f9ca3e5ff8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -994,6 +994,7 @@ extern unsigned int i915_panel_use_ssc;
 extern int i915_vbt_sdvo_panel_type;
 extern unsigned int i915_enable_rc6;
 extern unsigned int i915_enable_fbc;
+extern bool i915_enable_hangcheck;
 
 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
 extern int i915_resume(struct drm_device *dev);
@@ -1193,7 +1194,7 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
                                             uint32_t read_domains,
                                             uint32_t write_domain);
-int __must_check i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj);
+int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
 int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
 void i915_gem_do_init(struct drm_device *dev,
@@ -1212,7 +1213,8 @@ int __must_check
 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
                                   bool write);
 int __must_check
-i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
+i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
+                                     u32 alignment,
                                      struct intel_ring_buffer *pipelined);
 int i915_gem_attach_phys_object(struct drm_device *dev,
                                 struct drm_i915_gem_object *obj,
@@ -1226,9 +1228,14 @@ void i915_gem_release(struct drm_device *dev, struct drm_file *file);
 uint32_t
 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj);
 
+int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
+                                    enum i915_cache_level cache_level);
+
 /* i915_gem_gtt.c */
 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
+void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
+                                enum i915_cache_level cache_level);
 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
 
 /* i915_gem_evict.c */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5c0d1247f453..e9d1d5c3a696 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1771,8 +1771,11 @@ i915_add_request(struct intel_ring_buffer *ring,
         ring->outstanding_lazy_request = false;
 
         if (!dev_priv->mm.suspended) {
-                mod_timer(&dev_priv->hangcheck_timer,
-                          jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
+                if (i915_enable_hangcheck) {
+                        mod_timer(&dev_priv->hangcheck_timer,
+                                  jiffies +
+                                  msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
+                }
                 if (was_empty)
                         queue_delayed_work(dev_priv->wq,
                                            &dev_priv->mm.retire_work, HZ);
@@ -2143,6 +2146,30 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
         return 0;
 }
 
+static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
+{
+        u32 old_write_domain, old_read_domains;
+
+        /* Act a barrier for all accesses through the GTT */
+        mb();
+
+        /* Force a pagefault for domain tracking on next user access */
+        i915_gem_release_mmap(obj);
+
+        if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
+                return;
+
+        old_read_domains = obj->base.read_domains;
+        old_write_domain = obj->base.write_domain;
+
+        obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
+        obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
+
+        trace_i915_gem_object_change_domain(obj,
+                                            old_read_domains,
+                                            old_write_domain);
+}
+
 /**
  * Unbinds an object from the GTT aperture.
  */
@@ -2159,23 +2186,28 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj)
                 return -EINVAL;
         }
 
-        /* blow away mappings if mapped through GTT */
-        i915_gem_release_mmap(obj);
-
-        /* Move the object to the CPU domain to ensure that
-         * any possible CPU writes while it's not in the GTT
-         * are flushed when we go to remap it. This will
-         * also ensure that all pending GPU writes are finished
-         * before we unbind.
-         */
-        ret = i915_gem_object_set_to_cpu_domain(obj, 1);
+        ret = i915_gem_object_finish_gpu(obj);
         if (ret == -ERESTARTSYS)
                 return ret;
         /* Continue on if we fail due to EIO, the GPU is hung so we
          * should be safe and we need to cleanup or else we might
          * cause memory corruption through use-after-free.
          */
+
+        i915_gem_object_finish_gtt(obj);
+
+        /* Move the object to the CPU domain to ensure that
+         * any possible CPU writes while it's not in the GTT
+         * are flushed when we go to remap it.
+         */
+        if (ret == 0)
+                ret = i915_gem_object_set_to_cpu_domain(obj, 1);
+        if (ret == -ERESTARTSYS)
+                return ret;
         if (ret) {
+                /* In the event of a disaster, abandon all caches and
+                 * hope for the best.
+                 */
                 i915_gem_clflush_object(obj);
                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
         }
@@ -2997,51 +3029,139 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
         return 0;
 }
 
+int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
+                                    enum i915_cache_level cache_level)
+{
+        int ret;
+
+        if (obj->cache_level == cache_level)
+                return 0;
+
+        if (obj->pin_count) {
+                DRM_DEBUG("can not change the cache level of pinned objects\n");
+                return -EBUSY;
+        }
+
+        if (obj->gtt_space) {
+                ret = i915_gem_object_finish_gpu(obj);
+                if (ret)
+                        return ret;
+
+                i915_gem_object_finish_gtt(obj);
+
+                /* Before SandyBridge, you could not use tiling or fence
+                 * registers with snooped memory, so relinquish any fences
+                 * currently pointing to our region in the aperture.
+                 */
+                if (INTEL_INFO(obj->base.dev)->gen < 6) {
+                        ret = i915_gem_object_put_fence(obj);
+                        if (ret)
+                                return ret;
+                }
+
+                i915_gem_gtt_rebind_object(obj, cache_level);
+        }
+
+        if (cache_level == I915_CACHE_NONE) {
+                u32 old_read_domains, old_write_domain;
+
+                /* If we're coming from LLC cached, then we haven't
+                 * actually been tracking whether the data is in the
+                 * CPU cache or not, since we only allow one bit set
+                 * in obj->write_domain and have been skipping the clflushes.
+                 * Just set it to the CPU cache for now.
+                 */
+                WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
+                WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
+
+                old_read_domains = obj->base.read_domains;
+                old_write_domain = obj->base.write_domain;
+
+                obj->base.read_domains = I915_GEM_DOMAIN_CPU;
+                obj->base.write_domain = I915_GEM_DOMAIN_CPU;
+
+                trace_i915_gem_object_change_domain(obj,
+                                                    old_read_domains,
+                                                    old_write_domain);
+        }
+
+        obj->cache_level = cache_level;
+        return 0;
+}
+
 /*
- * Prepare buffer for display plane. Use uninterruptible for possible flush
- * wait, as in modesetting process we're not supposed to be interrupted.
+ * Prepare buffer for display plane (scanout, cursors, etc).
+ * Can be called from an uninterruptible phase (modesetting) and allows
+ * any flushes to be pipelined (for pageflips).
+ *
+ * For the display plane, we want to be in the GTT but out of any write
+ * domains. So in many ways this looks like set_to_gtt_domain() apart from the
+ * ability to pipeline the waits, pinning and any additional subtleties
+ * that may differentiate the display plane from ordinary buffers.
  */
 int
-i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
+i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
+                                     u32 alignment,
                                      struct intel_ring_buffer *pipelined)
 {
-        uint32_t old_read_domains;
+        u32 old_read_domains, old_write_domain;
         int ret;
 
-        /* Not valid to be called on unbound objects. */
-        if (obj->gtt_space == NULL)
-                return -EINVAL;
-
         ret = i915_gem_object_flush_gpu_write_domain(obj);
         if (ret)
                 return ret;
 
-
-        /* Currently, we are always called from an non-interruptible context. */
         if (pipelined != obj->ring) {
                 ret = i915_gem_object_wait_rendering(obj);
                 if (ret)
                         return ret;
         }
 
+        /* The display engine is not coherent with the LLC cache on gen6.  As
+         * a result, we make sure that the pinning that is about to occur is
+         * done with uncached PTEs. This is lowest common denominator for all
+         * chipsets.
+         *
+         * However for gen6+, we could do better by using the GFDT bit instead
+         * of uncaching, which would allow us to flush all the LLC-cached data
+         * with that bit in the PTE to main memory with just one PIPE_CONTROL.
+         */
+        ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
+        if (ret)
+                return ret;
+
+        /* As the user may map the buffer once pinned in the display plane
+         * (e.g. libkms for the bootup splash), we have to ensure that we
+         * always use map_and_fenceable for all scanout buffers.
+         */
+        ret = i915_gem_object_pin(obj, alignment, true);
+        if (ret)
+                return ret;
+
         i915_gem_object_flush_cpu_write_domain(obj);
 
+        old_write_domain = obj->base.write_domain;
         old_read_domains = obj->base.read_domains;
+
+        /* It should now be out of any other write domains, and we can update
+         * the domain values for our changes.
+         */
+        BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
 
         trace_i915_gem_object_change_domain(obj,
                                             old_read_domains,
-                                            obj->base.write_domain);
+                                            old_write_domain);
 
         return 0;
 }
 
 int
-i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj)
+i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
 {
         int ret;
 
-        if (!obj->active)
+        if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
                 return 0;
 
         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
@@ -3050,6 +3170,9 @@ i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj)
                         return ret;
         }
 
+        /* Ensure that we invalidate the GPU's caches and TLBs. */
+        obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
+
         return i915_gem_object_wait_rendering(obj);
 }
 
@@ -3576,7 +3699,23 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
 
-        obj->cache_level = I915_CACHE_NONE;
+        if (IS_GEN6(dev)) {
+                /* On Gen6, we can have the GPU use the LLC (the CPU
+                 * cache) for about a 10% performance improvement
+                 * compared to uncached.  Graphics requests other than
+                 * display scanout are coherent with the CPU in
+                 * accessing this cache.  This means in this mode we
+                 * don't need to clflush on the CPU side, and on the
+                 * GPU side we only need to flush internal caches to
+                 * get data visible to the CPU.
+                 *
+                 * However, we maintain the display planes as UC, and so
+                 * need to rebind when first used as such.
+                 */
+                obj->cache_level = I915_CACHE_LLC;
+        } else
+                obj->cache_level = I915_CACHE_NONE;
+
         obj->base.driver_private = NULL;
         obj->fence_reg = I915_FENCE_REG_NONE;
         INIT_LIST_HEAD(&obj->mm_list);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e46b645773cf..7a709cd8d543 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -59,24 +59,8 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
                               (dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);
 
         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
-                unsigned int agp_type =
-                        cache_level_to_agp_type(dev, obj->cache_level);
-
                 i915_gem_clflush_object(obj);
-
-                if (dev_priv->mm.gtt->needs_dmar) {
-                        BUG_ON(!obj->sg_list);
-
-                        intel_gtt_insert_sg_entries(obj->sg_list,
-                                                    obj->num_sg,
-                                                    obj->gtt_space->start >> PAGE_SHIFT,
-                                                    agp_type);
-                } else
-                        intel_gtt_insert_pages(obj->gtt_space->start
-                                                   >> PAGE_SHIFT,
-                                               obj->base.size >> PAGE_SHIFT,
-                                               obj->pages,
-                                               agp_type);
+                i915_gem_gtt_rebind_object(obj, obj->cache_level);
         }
 
         intel_gtt_chipset_flush();
@@ -110,6 +94,27 @@ int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj)
         return 0;
 }
 
+void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
+                                enum i915_cache_level cache_level)
+{
+        struct drm_device *dev = obj->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        unsigned int agp_type = cache_level_to_agp_type(dev, cache_level);
+
+        if (dev_priv->mm.gtt->needs_dmar) {
+                BUG_ON(!obj->sg_list);
+
+                intel_gtt_insert_sg_entries(obj->sg_list,
+                                            obj->num_sg,
+                                            obj->gtt_space->start >> PAGE_SHIFT,
+                                            agp_type);
+        } else
+                intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
+                                       obj->base.size >> PAGE_SHIFT,
+                                       obj->pages,
+                                       agp_type);
+}
+
 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
 {
         intel_gtt_clear_range(obj->gtt_space->start >> PAGE_SHIFT,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ae2b49969b99..0b0de5239ad5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -361,10 +361,12 @@ static void notify_ring(struct drm_device *dev,
 
         ring->irq_seqno = seqno;
         wake_up_all(&ring->irq_queue);
-
-        dev_priv->hangcheck_count = 0;
-        mod_timer(&dev_priv->hangcheck_timer,
-                  jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
+        if (i915_enable_hangcheck) {
+                dev_priv->hangcheck_count = 0;
+                mod_timer(&dev_priv->hangcheck_timer,
+                          jiffies +
+                          msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
+        }
 }
 
 static void gen6_pm_rps_work(struct work_struct *work)
@@ -1664,6 +1666,9 @@ void i915_hangcheck_elapsed(unsigned long data)
         uint32_t acthd, instdone, instdone1;
         bool err = false;
 
+        if (!i915_enable_hangcheck)
+                return;
+
         /* If all work is done then ACTHD clearly hasn't advanced. */
         if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
             i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d5def756c9e..4a446b116e6a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3434,7 +3434,9 @@
 #define GEN6_PCODE_MAILBOX                      0x138124
 #define   GEN6_PCODE_READY                      (1<<31)
 #define   GEN6_READ_OC_PARAMS                   0xc
-#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE       0x9
+#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE       0x8
+#define   GEN6_PCODE_READ_MIN_FREQ_TABLE        0x9
 #define GEN6_PCODE_DATA                         0x138128
+#define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT        8
 
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index e8152d23d5b6..6fbd997f5a6c 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -875,8 +875,10 @@ int i915_restore_state(struct drm_device *dev)
                 intel_init_emon(dev);
         }
 
-        if (IS_GEN6(dev))
+        if (IS_GEN6(dev)) {
                 gen6_enable_rps(dev_priv);
+                gen6_update_ring_freq(dev_priv);
+        }
 
         /* Cache mode state */
         I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 21b6f93fe919..804ac4d6cb48 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -24,6 +24,7 @@
  *      Eric Anholt <eric@anholt.net>
  */
 
+#include <linux/cpufreq.h>
 #include <linux/module.h>
 #include <linux/input.h>
 #include <linux/i2c.h>
@@ -1812,14 +1813,10 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
         }
 
         dev_priv->mm.interruptible = false;
-        ret = i915_gem_object_pin(obj, alignment, true);
+        ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
         if (ret)
                 goto err_interruptible;
 
-        ret = i915_gem_object_set_to_display_plane(obj, pipelined);
-        if (ret)
-                goto err_unpin;
-
         /* Install a fence for tiled scan-out. Pre-i965 always needs a
          * fence, whereas 965+ only requires a fence if using
          * framebuffer compression.  For simplicity, we always install
@@ -1971,7 +1968,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                  * This should only fail upon a hung GPU, in which case we
                  * can safely continue.
                  */
-                ret = i915_gem_object_flush_gpu(obj);
+                ret = i915_gem_object_finish_gpu(obj);
                 (void) ret;
         }
 
@@ -5434,21 +5431,15 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
                         goto fail_locked;
                 }
 
-                ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
-                if (ret) {
-                        DRM_ERROR("failed to pin cursor bo\n");
-                        goto fail_locked;
-                }
-
-                ret = i915_gem_object_set_to_gtt_domain(obj, 0);
+                ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
                 if (ret) {
                         DRM_ERROR("failed to move cursor bo into the GTT\n");
-                        goto fail_unpin;
+                        goto fail_locked;
                 }
 
                 ret = i915_gem_object_put_fence(obj);
                 if (ret) {
-                        DRM_ERROR("failed to move cursor bo into the GTT\n");
+                        DRM_ERROR("failed to release fence for cursor");
                         goto fail_unpin;
                 }
 
@@ -7283,6 +7274,59 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
         mutex_unlock(&dev_priv->dev->struct_mutex);
 }
 
+void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
+{
+        int min_freq = 15;
+        int gpu_freq, ia_freq, max_ia_freq;
+        int scaling_factor = 180;
+
+        max_ia_freq = cpufreq_quick_get_max(0);
+        /*
+         * Default to measured freq if none found, PCU will ensure we don't go
+         * over
+         */
+        if (!max_ia_freq)
+                max_ia_freq = tsc_khz;
+
+        /* Convert from kHz to MHz */
+        max_ia_freq /= 1000;
+
+        mutex_lock(&dev_priv->dev->struct_mutex);
+
+        /*
+         * For each potential GPU frequency, load a ring frequency we'd like
+         * to use for memory access.  We do this by specifying the IA frequency
+         * the PCU should use as a reference to determine the ring frequency.
+         */
+        for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
+             gpu_freq--) {
+                int diff = dev_priv->max_delay - gpu_freq;
+
+                /*
+                 * For GPU frequencies less than 750MHz, just use the lowest
+                 * ring freq.
+                 */
+                if (gpu_freq < min_freq)
+                        ia_freq = 800;
+                else
+                        ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
+                ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
+
+                I915_WRITE(GEN6_PCODE_DATA,
+                           (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
+                           gpu_freq);
+                I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
+                           GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
+                if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
+                              GEN6_PCODE_READY) == 0, 10)) {
+                        DRM_ERROR("pcode write of freq table timed out\n");
+                        continue;
+                }
+        }
+
+        mutex_unlock(&dev_priv->dev->struct_mutex);
+}
+
 static void ironlake_init_clock_gating(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7926,8 +7970,10 @@ void intel_modeset_init(struct drm_device *dev)
                 intel_init_emon(dev);
         }
 
-        if (IS_GEN6(dev))
+        if (IS_GEN6(dev)) {
                 gen6_enable_rps(dev_priv);
+                gen6_update_ring_freq(dev_priv);
+        }
 
         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9ffa61eb4d7e..8ac3bd8b6faa 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -317,6 +317,7 @@ extern void intel_enable_clock_gating(struct drm_device *dev);
 extern void ironlake_enable_drps(struct drm_device *dev);
 extern void ironlake_disable_drps(struct drm_device *dev);
 extern void gen6_enable_rps(struct drm_i915_private *dev_priv);
+extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
 extern void gen6_disable_rps(struct drm_device *dev);
 extern void intel_init_emon(struct drm_device *dev);
 
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 56a8e2aea19c..cffd3edd9bb4 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -773,14 +773,10 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay,
         if (ret != 0)
                 return ret;
 
-        ret = i915_gem_object_pin(new_bo, PAGE_SIZE, true);
+        ret = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
         if (ret != 0)
                 return ret;
 
-        ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
-        if (ret != 0)
-                goto out_unpin;
-
         ret = i915_gem_object_put_fence(new_bo);
         if (ret)
                 goto out_unpin;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 95c4b1429935..e9615685a39c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -236,7 +236,8 @@ init_pipe_control(struct intel_ring_buffer *ring)
                 ret = -ENOMEM;
                 goto err;
         }
-        obj->cache_level = I915_CACHE_LLC;
+
+        i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 
         ret = i915_gem_object_pin(obj, 4096, true);
         if (ret)
@@ -776,7 +777,8 @@ static int init_status_page(struct intel_ring_buffer *ring)
                 ret = -ENOMEM;
                 goto err;
         }
-        obj->cache_level = I915_CACHE_LLC;
+
+        i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 
         ret = i915_gem_object_pin(obj, 4096, true);
         if (ret != 0) {
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index 11be48e0d168..6216115c7789 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -324,11 +324,16 @@ static inline unsigned int cpufreq_get(unsigned int cpu)
 /* query the last known CPU freq (in kHz). If zero, cpufreq couldn't detect it */
 #ifdef CONFIG_CPU_FREQ
 unsigned int cpufreq_quick_get(unsigned int cpu);
+unsigned int cpufreq_quick_get_max(unsigned int cpu);
 #else
 static inline unsigned int cpufreq_quick_get(unsigned int cpu)
 {
         return 0;
 }
+static inline unsigned int cpufreq_quick_get_max(unsigned int cpu)
+{
+        return 0;
+}
 #endif