aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/mach-shmobile/board-ag5evm.c16
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c2
-rw-r--r--arch/arm/mach-shmobile/board-kota2.c7
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c8
-rw-r--r--arch/arm/mach-shmobile/cpuidle.c52
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h4
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh73a0.h8
-rw-r--r--arch/arm/mach-shmobile/pfc-sh7367.c122
-rw-r--r--arch/arm/mach-shmobile/pfc-sh7372.c262
-rw-r--r--arch/arm/mach-shmobile/pfc-sh7377.c159
-rw-r--r--arch/arm/mach-shmobile/pfc-sh73a0.c193
-rw-r--r--arch/arm/mach-shmobile/pm-sh7372.c14
-rw-r--r--include/linux/sh_pfc.h76
13 files changed, 400 insertions, 523 deletions
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 83624e26b884..b862e9f81e3e 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -515,14 +515,14 @@ static void __init ag5evm_init(void)
515 /* enable MMCIF */ 515 /* enable MMCIF */
516 gpio_request(GPIO_FN_MMCCLK0, NULL); 516 gpio_request(GPIO_FN_MMCCLK0, NULL);
517 gpio_request(GPIO_FN_MMCCMD0_PU, NULL); 517 gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
518 gpio_request(GPIO_FN_MMCD0_0, NULL); 518 gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
519 gpio_request(GPIO_FN_MMCD0_1, NULL); 519 gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
520 gpio_request(GPIO_FN_MMCD0_2, NULL); 520 gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
521 gpio_request(GPIO_FN_MMCD0_3, NULL); 521 gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
522 gpio_request(GPIO_FN_MMCD0_4, NULL); 522 gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
523 gpio_request(GPIO_FN_MMCD0_5, NULL); 523 gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
524 gpio_request(GPIO_FN_MMCD0_6, NULL); 524 gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
525 gpio_request(GPIO_FN_MMCD0_7, NULL); 525 gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
526 gpio_request(GPIO_PORT208, NULL); /* Reset */ 526 gpio_request(GPIO_PORT208, NULL); /* Reset */
527 gpio_direction_output(GPIO_PORT208, 1); 527 gpio_direction_output(GPIO_PORT208, 1);
528 528
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index a3aa0f6df964..4c865ece9ac4 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -201,7 +201,7 @@ static struct physmap_flash_data nor_flash_data = {
201static struct resource nor_flash_resources[] = { 201static struct resource nor_flash_resources[] = {
202 [0] = { 202 [0] = {
203 .start = 0x20000000, /* CS0 shadow instead of regular CS0 */ 203 .start = 0x20000000, /* CS0 shadow instead of regular CS0 */
204 .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */ 204 .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */
205 .flags = IORESOURCE_MEM, 205 .flags = IORESOURCE_MEM,
206 } 206 }
207}; 207};
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index adc73122bf20..bd9a78424d6b 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -48,6 +48,7 @@
48#include <asm/hardware/cache-l2x0.h> 48#include <asm/hardware/cache-l2x0.h>
49#include <asm/traps.h> 49#include <asm/traps.h>
50 50
51/* SMSC 9220 */
51static struct resource smsc9220_resources[] = { 52static struct resource smsc9220_resources[] = {
52 [0] = { 53 [0] = {
53 .start = 0x14000000, /* CS5A */ 54 .start = 0x14000000, /* CS5A */
@@ -77,6 +78,7 @@ static struct platform_device eth_device = {
77 .num_resources = ARRAY_SIZE(smsc9220_resources), 78 .num_resources = ARRAY_SIZE(smsc9220_resources),
78}; 79};
79 80
81/* KEYSC */
80static struct sh_keysc_info keysc_platdata = { 82static struct sh_keysc_info keysc_platdata = {
81 .mode = SH_KEYSC_MODE_6, 83 .mode = SH_KEYSC_MODE_6,
82 .scan_timing = 3, 84 .scan_timing = 3,
@@ -120,6 +122,7 @@ static struct platform_device keysc_device = {
120 }, 122 },
121}; 123};
122 124
125/* GPIO KEY */
123#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 } 126#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
124 127
125static struct gpio_keys_button gpio_buttons[] = { 128static struct gpio_keys_button gpio_buttons[] = {
@@ -150,6 +153,7 @@ static struct platform_device gpio_keys_device = {
150 }, 153 },
151}; 154};
152 155
156/* GPIO LED */
153#define GPIO_LED(n, g) { .name = n, .gpio = g } 157#define GPIO_LED(n, g) { .name = n, .gpio = g }
154 158
155static struct gpio_led gpio_leds[] = { 159static struct gpio_led gpio_leds[] = {
@@ -175,6 +179,7 @@ static struct platform_device gpio_leds_device = {
175 }, 179 },
176}; 180};
177 181
182/* MMCIF */
178static struct resource mmcif_resources[] = { 183static struct resource mmcif_resources[] = {
179 [0] = { 184 [0] = {
180 .name = "MMCIF", 185 .name = "MMCIF",
@@ -207,6 +212,7 @@ static struct platform_device mmcif_device = {
207 .resource = mmcif_resources, 212 .resource = mmcif_resources,
208}; 213};
209 214
215/* SDHI0 */
210static struct sh_mobile_sdhi_info sdhi0_info = { 216static struct sh_mobile_sdhi_info sdhi0_info = {
211 .tmio_caps = MMC_CAP_SD_HIGHSPEED, 217 .tmio_caps = MMC_CAP_SD_HIGHSPEED,
212 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT, 218 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
@@ -243,6 +249,7 @@ static struct platform_device sdhi0_device = {
243 }, 249 },
244}; 250};
245 251
252/* SDHI1 */
246static struct sh_mobile_sdhi_info sdhi1_info = { 253static struct sh_mobile_sdhi_info sdhi1_info = {
247 .tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ, 254 .tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ,
248 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT, 255 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 66975921e646..995a9c3aec8f 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -476,7 +476,7 @@ static struct clk_ops fsidiv_clk_ops = {
476 .disable = fsidiv_disable, 476 .disable = fsidiv_disable,
477}; 477};
478 478
479static struct clk_mapping sh7372_fsidiva_clk_mapping = { 479static struct clk_mapping fsidiva_clk_mapping = {
480 .phys = FSIDIVA, 480 .phys = FSIDIVA,
481 .len = 8, 481 .len = 8,
482}; 482};
@@ -484,10 +484,10 @@ static struct clk_mapping sh7372_fsidiva_clk_mapping = {
484struct clk sh7372_fsidiva_clk = { 484struct clk sh7372_fsidiva_clk = {
485 .ops = &fsidiv_clk_ops, 485 .ops = &fsidiv_clk_ops,
486 .parent = &div6_reparent_clks[DIV6_FSIA], /* late install */ 486 .parent = &div6_reparent_clks[DIV6_FSIA], /* late install */
487 .mapping = &sh7372_fsidiva_clk_mapping, 487 .mapping = &fsidiva_clk_mapping,
488}; 488};
489 489
490static struct clk_mapping sh7372_fsidivb_clk_mapping = { 490static struct clk_mapping fsidivb_clk_mapping = {
491 .phys = FSIDIVB, 491 .phys = FSIDIVB,
492 .len = 8, 492 .len = 8,
493}; 493};
@@ -495,7 +495,7 @@ static struct clk_mapping sh7372_fsidivb_clk_mapping = {
495struct clk sh7372_fsidivb_clk = { 495struct clk sh7372_fsidivb_clk = {
496 .ops = &fsidiv_clk_ops, 496 .ops = &fsidiv_clk_ops,
497 .parent = &div6_reparent_clks[DIV6_FSIB], /* late install */ 497 .parent = &div6_reparent_clks[DIV6_FSIB], /* late install */
498 .mapping = &sh7372_fsidivb_clk_mapping, 498 .mapping = &fsidivb_clk_mapping,
499}; 499};
500 500
501static struct clk *late_main_clks[] = { 501static struct clk *late_main_clks[] = {
diff --git a/arch/arm/mach-shmobile/cpuidle.c b/arch/arm/mach-shmobile/cpuidle.c
index 2e44f11f592e..1b2334277e85 100644
--- a/arch/arm/mach-shmobile/cpuidle.c
+++ b/arch/arm/mach-shmobile/cpuidle.c
@@ -26,65 +26,59 @@ void (*shmobile_cpuidle_modes[CPUIDLE_STATE_MAX])(void) = {
26}; 26};
27 27
28static int shmobile_cpuidle_enter(struct cpuidle_device *dev, 28static int shmobile_cpuidle_enter(struct cpuidle_device *dev,
29 struct cpuidle_state *state) 29 struct cpuidle_driver *drv,
30 int index)
30{ 31{
31 ktime_t before, after; 32 ktime_t before, after;
32 int requested_state = state - &dev->states[0];
33 33
34 dev->last_state = &dev->states[requested_state];
35 before = ktime_get(); 34 before = ktime_get();
36 35
37 local_irq_disable(); 36 local_irq_disable();
38 local_fiq_disable(); 37 local_fiq_disable();
39 38
40 shmobile_cpuidle_modes[requested_state](); 39 shmobile_cpuidle_modes[index]();
41 40
42 local_irq_enable(); 41 local_irq_enable();
43 local_fiq_enable(); 42 local_fiq_enable();
44 43
45 after = ktime_get(); 44 after = ktime_get();
46 return ktime_to_ns(ktime_sub(after, before)) >> 10; 45 dev->last_residency = ktime_to_ns(ktime_sub(after, before)) >> 10;
46
47 return index;
47} 48}
48 49
49static struct cpuidle_device shmobile_cpuidle_dev; 50static struct cpuidle_device shmobile_cpuidle_dev;
50static struct cpuidle_driver shmobile_cpuidle_driver = { 51static struct cpuidle_driver shmobile_cpuidle_driver = {
51 .name = "shmobile_cpuidle", 52 .name = "shmobile_cpuidle",
52 .owner = THIS_MODULE, 53 .owner = THIS_MODULE,
54 .states[0] = {
55 .name = "C1",
56 .desc = "WFI",
57 .exit_latency = 1,
58 .target_residency = 1 * 2,
59 .flags = CPUIDLE_FLAG_TIME_VALID,
60 },
61 .safe_state_index = 0, /* C1 */
62 .state_count = 1,
53}; 63};
54 64
55void (*shmobile_cpuidle_setup)(struct cpuidle_device *dev); 65void (*shmobile_cpuidle_setup)(struct cpuidle_driver *drv);
56 66
57static int shmobile_cpuidle_init(void) 67static int shmobile_cpuidle_init(void)
58{ 68{
59 struct cpuidle_device *dev = &shmobile_cpuidle_dev; 69 struct cpuidle_device *dev = &shmobile_cpuidle_dev;
60 struct cpuidle_state *state; 70 struct cpuidle_driver *drv = &shmobile_cpuidle_driver;
61 int i; 71 int i;
62 72
63 cpuidle_register_driver(&shmobile_cpuidle_driver); 73 for (i = 0; i < CPUIDLE_STATE_MAX; i++)
64 74 drv->states[i].enter = shmobile_cpuidle_enter;
65 for (i = 0; i < CPUIDLE_STATE_MAX; i++) {
66 dev->states[i].name[0] = '\0';
67 dev->states[i].desc[0] = '\0';
68 dev->states[i].enter = shmobile_cpuidle_enter;
69 }
70
71 i = CPUIDLE_DRIVER_STATE_START;
72
73 state = &dev->states[i++];
74 snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
75 strncpy(state->desc, "WFI", CPUIDLE_DESC_LEN);
76 state->exit_latency = 1;
77 state->target_residency = 1 * 2;
78 state->power_usage = 3;
79 state->flags = 0;
80 state->flags |= CPUIDLE_FLAG_TIME_VALID;
81
82 dev->safe_state = state;
83 dev->state_count = i;
84 75
85 if (shmobile_cpuidle_setup) 76 if (shmobile_cpuidle_setup)
86 shmobile_cpuidle_setup(dev); 77 shmobile_cpuidle_setup(drv);
78
79 cpuidle_register_driver(drv);
87 80
81 dev->state_count = drv->state_count;
88 cpuidle_register_device(dev); 82 cpuidle_register_device(dev);
89 83
90 return 0; 84 return 0;
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index c0cdbf997c91..834bd6cd508f 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -9,9 +9,9 @@ extern int clk_init(void);
9extern void shmobile_handle_irq_intc(struct pt_regs *); 9extern void shmobile_handle_irq_intc(struct pt_regs *);
10extern void shmobile_handle_irq_gic(struct pt_regs *); 10extern void shmobile_handle_irq_gic(struct pt_regs *);
11extern struct platform_suspend_ops shmobile_suspend_ops; 11extern struct platform_suspend_ops shmobile_suspend_ops;
12struct cpuidle_device; 12struct cpuidle_driver;
13extern void (*shmobile_cpuidle_modes[])(void); 13extern void (*shmobile_cpuidle_modes[])(void);
14extern void (*shmobile_cpuidle_setup)(struct cpuidle_device *dev); 14extern void (*shmobile_cpuidle_setup)(struct cpuidle_driver *drv);
15 15
16extern void sh7367_init_irq(void); 16extern void sh7367_init_irq(void);
17extern void sh7367_add_early_devices(void); 17extern void sh7367_add_early_devices(void);
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 18ae6a990bc2..881d515a9686 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -470,6 +470,14 @@ enum {
470 GPIO_FN_SDHICMD2_PU, 470 GPIO_FN_SDHICMD2_PU,
471 GPIO_FN_MMCCMD0_PU, 471 GPIO_FN_MMCCMD0_PU,
472 GPIO_FN_MMCCMD1_PU, 472 GPIO_FN_MMCCMD1_PU,
473 GPIO_FN_MMCD0_0_PU,
474 GPIO_FN_MMCD0_1_PU,
475 GPIO_FN_MMCD0_2_PU,
476 GPIO_FN_MMCD0_3_PU,
477 GPIO_FN_MMCD0_4_PU,
478 GPIO_FN_MMCD0_5_PU,
479 GPIO_FN_MMCD0_6_PU,
480 GPIO_FN_MMCD0_7_PU,
473 GPIO_FN_FSIACK_PU, 481 GPIO_FN_FSIACK_PU,
474 GPIO_FN_FSIAILR_PU, 482 GPIO_FN_FSIAILR_PU,
475 GPIO_FN_FSIAIBT_PU, 483 GPIO_FN_FSIAIBT_PU,
diff --git a/arch/arm/mach-shmobile/pfc-sh7367.c b/arch/arm/mach-shmobile/pfc-sh7367.c
index 128555e76e43..e6e524654e67 100644
--- a/arch/arm/mach-shmobile/pfc-sh7367.c
+++ b/arch/arm/mach-shmobile/pfc-sh7367.c
@@ -21,68 +21,49 @@
21#include <linux/gpio.h> 21#include <linux/gpio.h>
22#include <mach/sh7367.h> 22#include <mach/sh7367.h>
23 23
24#define _1(fn, pfx, sfx) fn(pfx, sfx) 24#define CPU_ALL_PORT(fn, pfx, sfx) \
25 25 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
26#define _10(fn, pfx, sfx) \ 26 PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
27 _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \ 27 PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
28 _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \ 28 PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
29 _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \ 29 PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
30 _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \ 30 PORT_10(fn, pfx##26, sfx), PORT_1(fn, pfx##270, sfx), \
31 _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx) 31 PORT_1(fn, pfx##271, sfx), PORT_1(fn, pfx##272, sfx)
32
33#define _90(fn, pfx, sfx) \
34 _10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \
35 _10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \
36 _10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \
37 _10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx), \
38 _10(fn, pfx##9, sfx)
39
40#define _273(fn, pfx, sfx) \
41 _10(fn, pfx, sfx), _90(fn, pfx, sfx), \
42 _10(fn, pfx##10, sfx), _90(fn, pfx##1, sfx), \
43 _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \
44 _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \
45 _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \
46 _10(fn, pfx##26, sfx), _1(fn, pfx##270, sfx), \
47 _1(fn, pfx##271, sfx), _1(fn, pfx##272, sfx)
48
49#define _PORT(pfx, sfx) pfx##_##sfx
50#define PORT_273(str) _273(_PORT, PORT, str)
51 32
52enum { 33enum {
53 PINMUX_RESERVED = 0, 34 PINMUX_RESERVED = 0,
54 35
55 PINMUX_DATA_BEGIN, 36 PINMUX_DATA_BEGIN,
56 PORT_273(DATA), /* PORT0_DATA -> PORT272_DATA */ 37 PORT_ALL(DATA), /* PORT0_DATA -> PORT272_DATA */
57 PINMUX_DATA_END, 38 PINMUX_DATA_END,
58 39
59 PINMUX_INPUT_BEGIN, 40 PINMUX_INPUT_BEGIN,
60 PORT_273(IN), /* PORT0_IN -> PORT272_IN */ 41 PORT_ALL(IN), /* PORT0_IN -> PORT272_IN */
61 PINMUX_INPUT_END, 42 PINMUX_INPUT_END,
62 43
63 PINMUX_INPUT_PULLUP_BEGIN, 44 PINMUX_INPUT_PULLUP_BEGIN,
64 PORT_273(IN_PU), /* PORT0_IN_PU -> PORT272_IN_PU */ 45 PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT272_IN_PU */
65 PINMUX_INPUT_PULLUP_END, 46 PINMUX_INPUT_PULLUP_END,
66 47
67 PINMUX_INPUT_PULLDOWN_BEGIN, 48 PINMUX_INPUT_PULLDOWN_BEGIN,
68 PORT_273(IN_PD), /* PORT0_IN_PD -> PORT272_IN_PD */ 49 PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT272_IN_PD */
69 PINMUX_INPUT_PULLDOWN_END, 50 PINMUX_INPUT_PULLDOWN_END,
70 51
71 PINMUX_OUTPUT_BEGIN, 52 PINMUX_OUTPUT_BEGIN,
72 PORT_273(OUT), /* PORT0_OUT -> PORT272_OUT */ 53 PORT_ALL(OUT), /* PORT0_OUT -> PORT272_OUT */
73 PINMUX_OUTPUT_END, 54 PINMUX_OUTPUT_END,
74 55
75 PINMUX_FUNCTION_BEGIN, 56 PINMUX_FUNCTION_BEGIN,
76 PORT_273(FN_IN), /* PORT0_FN_IN -> PORT272_FN_IN */ 57 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT272_FN_IN */
77 PORT_273(FN_OUT), /* PORT0_FN_OUT -> PORT272_FN_OUT */ 58 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT272_FN_OUT */
78 PORT_273(FN0), /* PORT0_FN0 -> PORT272_FN0 */ 59 PORT_ALL(FN0), /* PORT0_FN0 -> PORT272_FN0 */
79 PORT_273(FN1), /* PORT0_FN1 -> PORT272_FN1 */ 60 PORT_ALL(FN1), /* PORT0_FN1 -> PORT272_FN1 */
80 PORT_273(FN2), /* PORT0_FN2 -> PORT272_FN2 */ 61 PORT_ALL(FN2), /* PORT0_FN2 -> PORT272_FN2 */
81 PORT_273(FN3), /* PORT0_FN3 -> PORT272_FN3 */ 62 PORT_ALL(FN3), /* PORT0_FN3 -> PORT272_FN3 */
82 PORT_273(FN4), /* PORT0_FN4 -> PORT272_FN4 */ 63 PORT_ALL(FN4), /* PORT0_FN4 -> PORT272_FN4 */
83 PORT_273(FN5), /* PORT0_FN5 -> PORT272_FN5 */ 64 PORT_ALL(FN5), /* PORT0_FN5 -> PORT272_FN5 */
84 PORT_273(FN6), /* PORT0_FN6 -> PORT272_FN6 */ 65 PORT_ALL(FN6), /* PORT0_FN6 -> PORT272_FN6 */
85 PORT_273(FN7), /* PORT0_FN7 -> PORT272_FN7 */ 66 PORT_ALL(FN7), /* PORT0_FN7 -> PORT272_FN7 */
86 67
87 MSELBCR_MSEL2_1, MSELBCR_MSEL2_0, 68 MSELBCR_MSEL2_1, MSELBCR_MSEL2_0,
88 PINMUX_FUNCTION_END, 69 PINMUX_FUNCTION_END,
@@ -327,41 +308,6 @@ enum {
327 PINMUX_MARK_END, 308 PINMUX_MARK_END,
328}; 309};
329 310
330#define PORT_DATA_I(nr) \
331 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
332
333#define PORT_DATA_I_PD(nr) \
334 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
335 PORT##nr##_IN, PORT##nr##_IN_PD)
336
337#define PORT_DATA_I_PU(nr) \
338 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
339 PORT##nr##_IN, PORT##nr##_IN_PU)
340
341#define PORT_DATA_I_PU_PD(nr) \
342 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
343 PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
344
345#define PORT_DATA_O(nr) \
346 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
347
348#define PORT_DATA_IO(nr) \
349 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
350 PORT##nr##_IN)
351
352#define PORT_DATA_IO_PD(nr) \
353 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
354 PORT##nr##_IN, PORT##nr##_IN_PD)
355
356#define PORT_DATA_IO_PU(nr) \
357 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
358 PORT##nr##_IN, PORT##nr##_IN_PU)
359
360#define PORT_DATA_IO_PU_PD(nr) \
361 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
362 PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
363
364
365static pinmux_enum_t pinmux_data[] = { 311static pinmux_enum_t pinmux_data[] = {
366 312
367 /* specify valid pin states for each pin in GPIO mode */ 313 /* specify valid pin states for each pin in GPIO mode */
@@ -1098,13 +1044,9 @@ static pinmux_enum_t pinmux_data[] = {
1098 PINMUX_DATA(DIVLOCK_MARK, PORT272_FN1), 1044 PINMUX_DATA(DIVLOCK_MARK, PORT272_FN1),
1099}; 1045};
1100 1046
1101#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
1102#define GPIO_PORT_273() _273(_GPIO_PORT, , unused)
1103#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
1104
1105static struct pinmux_gpio pinmux_gpios[] = { 1047static struct pinmux_gpio pinmux_gpios[] = {
1106 /* 49-1 -> 49-6 (GPIO) */ 1048 /* 49-1 -> 49-6 (GPIO) */
1107 GPIO_PORT_273(), 1049 GPIO_PORT_ALL(),
1108 1050
1109 /* Special Pull-up / Pull-down Functions */ 1051 /* Special Pull-up / Pull-down Functions */
1110 GPIO_FN(PORT48_KEYIN0_PU), GPIO_FN(PORT49_KEYIN1_PU), 1052 GPIO_FN(PORT48_KEYIN0_PU), GPIO_FN(PORT49_KEYIN1_PU),
@@ -1345,22 +1287,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1345 GPIO_FN(DIVLOCK), 1287 GPIO_FN(DIVLOCK),
1346}; 1288};
1347 1289
1348/* helper for top 4 bits in PORTnCR */
1349#define PCRH(in, in_pd, in_pu, out) \
1350 0, (out), (in), 0, \
1351 0, 0, 0, 0, \
1352 0, 0, (in_pd), 0, \
1353 0, 0, (in_pu), 0
1354
1355#define PORTCR(nr, reg) \
1356 { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
1357 PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
1358 PORT##nr##_IN_PU, PORT##nr##_OUT), \
1359 PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
1360 PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
1361 PORT##nr##_FN6, PORT##nr##_FN7 } \
1362 }
1363
1364static struct pinmux_cfg_reg pinmux_config_regs[] = { 1290static struct pinmux_cfg_reg pinmux_config_regs[] = {
1365 PORTCR(0, 0xe6050000), /* PORT0CR */ 1291 PORTCR(0, 0xe6050000), /* PORT0CR */
1366 PORTCR(1, 0xe6050001), /* PORT1CR */ 1292 PORTCR(1, 0xe6050001), /* PORT1CR */
diff --git a/arch/arm/mach-shmobile/pfc-sh7372.c b/arch/arm/mach-shmobile/pfc-sh7372.c
index 9c265dae138a..1bd6585a6acf 100644
--- a/arch/arm/mach-shmobile/pfc-sh7372.c
+++ b/arch/arm/mach-shmobile/pfc-sh7372.c
@@ -25,27 +25,13 @@
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <mach/sh7372.h> 26#include <mach/sh7372.h>
27 27
28#define _1(fn, pfx, sfx) fn(pfx, sfx) 28#define CPU_ALL_PORT(fn, pfx, sfx) \
29 29 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
30#define _10(fn, pfx, sfx) \ 30 PORT_10(fn, pfx##10, sfx), PORT_10(fn, pfx##11, sfx), \
31 _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \ 31 PORT_10(fn, pfx##12, sfx), PORT_10(fn, pfx##13, sfx), \
32 _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \ 32 PORT_10(fn, pfx##14, sfx), PORT_10(fn, pfx##15, sfx), \
33 _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \ 33 PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \
34 _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \ 34 PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx)
35 _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
36
37#define _80(fn, pfx, sfx) \
38 _10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \
39 _10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \
40 _10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \
41 _10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx)
42
43#define _190(fn, pfx, sfx) \
44 _10(fn, pfx, sfx), _80(fn, pfx, sfx), _10(fn, pfx##9, sfx), \
45 _10(fn, pfx##10, sfx), _80(fn, pfx##1, sfx), _1(fn, pfx##190, sfx)
46
47#define _PORT(pfx, sfx) pfx##_##sfx
48#define PORT_ALL(str) _190(_PORT, PORT, str)
49 35
50enum { 36enum {
51 PINMUX_RESERVED = 0, 37 PINMUX_RESERVED = 0,
@@ -381,108 +367,124 @@ enum {
381 PINMUX_MARK_END, 367 PINMUX_MARK_END,
382}; 368};
383 369
384/* PORT_DATA_I_PD(nr) */
385#define _I___D(nr) \
386 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
387 PORT##nr##_IN, PORT##nr##_IN_PD)
388
389/* PORT_DATA_I_PU(nr) */
390#define _I__U_(nr) \
391 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
392 PORT##nr##_IN, PORT##nr##_IN_PU)
393
394/* PORT_DATA_I_PU_PD(nr) */
395#define _I__UD(nr) \
396 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
397 PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
398
399/* PORT_DATA_O(nr) */
400#define __O___(nr) \
401 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
402
403/* PORT_DATA_IO(nr) */
404#define _IO___(nr) \
405 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
406 PORT##nr##_IN)
407
408/* PORT_DATA_IO_PD(nr) */
409#define _IO__D(nr) \
410 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
411 PORT##nr##_IN, PORT##nr##_IN_PD)
412
413/* PORT_DATA_IO_PU(nr) */
414#define _IO_U_(nr) \
415 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
416 PORT##nr##_IN, PORT##nr##_IN_PU)
417
418/* PORT_DATA_IO_PU_PD(nr) */
419#define _IO_UD(nr) \
420 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
421 PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
422
423
424static pinmux_enum_t pinmux_data[] = { 370static pinmux_enum_t pinmux_data[] = {
425 371
426 /* specify valid pin states for each pin in GPIO mode */ 372 /* specify valid pin states for each pin in GPIO mode */
427 373 PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
428 _IO__D(0), _IO__D(1), __O___(2), _I___D(3), _I___D(4), 374 PORT_DATA_O(2), PORT_DATA_I_PD(3),
429 _I___D(5), _IO_UD(6), _I___D(7), _IO__D(8), __O___(9), 375 PORT_DATA_I_PD(4), PORT_DATA_I_PD(5),
430 376 PORT_DATA_IO_PU_PD(6), PORT_DATA_I_PD(7),
431 __O___(10), __O___(11), _IO_UD(12), _IO__D(13), _IO__D(14), 377 PORT_DATA_IO_PD(8), PORT_DATA_O(9),
432 __O___(15), _IO__D(16), _IO__D(17), _I___D(18), _IO___(19), 378
433 379 PORT_DATA_O(10), PORT_DATA_O(11),
434 _IO___(20), _IO___(21), _IO___(22), _IO___(23), _IO___(24), 380 PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PD(13),
435 _IO___(25), _IO___(26), _IO___(27), _IO___(28), _IO___(29), 381 PORT_DATA_IO_PD(14), PORT_DATA_O(15),
436 382 PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
437 _IO___(30), _IO___(31), _IO___(32), _IO___(33), _IO___(34), 383 PORT_DATA_I_PD(18), PORT_DATA_IO(19),
438 _IO___(35), _IO___(36), _IO___(37), _IO___(38), _IO___(39), 384
439 385 PORT_DATA_IO(20), PORT_DATA_IO(21),
440 _IO___(40), _IO___(41), _IO___(42), _IO___(43), _IO___(44), 386 PORT_DATA_IO(22), PORT_DATA_IO(23),
441 _IO___(45), _IO_U_(46), _IO_U_(47), _IO_U_(48), _IO_U_(49), 387 PORT_DATA_IO(24), PORT_DATA_IO(25),
442 388 PORT_DATA_IO(26), PORT_DATA_IO(27),
443 _IO_U_(50), _IO_U_(51), _IO_U_(52), _IO_U_(53), _IO_U_(54), 389 PORT_DATA_IO(28), PORT_DATA_IO(29),
444 _IO_U_(55), _IO_U_(56), _IO_U_(57), _IO_U_(58), _IO_U_(59), 390
445 391 PORT_DATA_IO(30), PORT_DATA_IO(31),
446 _IO_U_(60), _IO_U_(61), _IO___(62), __O___(63), __O___(64), 392 PORT_DATA_IO(32), PORT_DATA_IO(33),
447 _IO_U_(65), __O___(66), _IO_U_(67), __O___(68), _IO___(69), /*66?*/ 393 PORT_DATA_IO(34), PORT_DATA_IO(35),
448 394 PORT_DATA_IO(36), PORT_DATA_IO(37),
449 _IO___(70), _IO___(71), __O___(72), _I__U_(73), _I__UD(74), 395 PORT_DATA_IO(38), PORT_DATA_IO(39),
450 _IO_UD(75), _IO_UD(76), _IO_UD(77), _IO_UD(78), _IO_UD(79), 396
451 397 PORT_DATA_IO(40), PORT_DATA_IO(41),
452 _IO_UD(80), _IO_UD(81), _IO_UD(82), _IO_UD(83), _IO_UD(84), 398 PORT_DATA_IO(42), PORT_DATA_IO(43),
453 _IO_UD(85), _IO_UD(86), _IO_UD(87), _IO_UD(88), _IO_UD(89), 399 PORT_DATA_IO(44), PORT_DATA_IO(45),
454 400 PORT_DATA_IO_PU(46), PORT_DATA_IO_PU(47),
455 _IO_UD(90), _IO_UD(91), _IO_UD(92), _IO_UD(93), _IO_UD(94), 401 PORT_DATA_IO_PU(48), PORT_DATA_IO_PU(49),
456 _IO_UD(95), _IO_U_(96), _IO_UD(97), _IO_UD(98), __O___(99), /*99?*/ 402
457 403 PORT_DATA_IO_PU(50), PORT_DATA_IO_PU(51),
458 _IO__D(100), _IO__D(101), _IO__D(102), _IO__D(103), _IO__D(104), 404 PORT_DATA_IO_PU(52), PORT_DATA_IO_PU(53),
459 _IO__D(105), _IO_U_(106), _IO_U_(107), _IO_U_(108), _IO_U_(109), 405 PORT_DATA_IO_PU(54), PORT_DATA_IO_PU(55),
460 406 PORT_DATA_IO_PU(56), PORT_DATA_IO_PU(57),
461 _IO_U_(110), _IO_U_(111), _IO__D(112), _IO__D(113), _IO_U_(114), 407 PORT_DATA_IO_PU(58), PORT_DATA_IO_PU(59),
462 _IO_U_(115), _IO_U_(116), _IO_U_(117), _IO_U_(118), _IO_U_(119), 408
463 409 PORT_DATA_IO_PU(60), PORT_DATA_IO_PU(61),
464 _IO_U_(120), _IO__D(121), _IO__D(122), _IO__D(123), _IO__D(124), 410 PORT_DATA_IO(62), PORT_DATA_O(63),
465 _IO__D(125), _IO__D(126), _IO__D(127), _IO__D(128), _IO_UD(129), 411 PORT_DATA_O(64), PORT_DATA_IO_PU(65),
466 412 PORT_DATA_O(66), PORT_DATA_IO_PU(67), /*66?*/
467 _IO_UD(130), _IO_UD(131), _IO_UD(132), _IO_UD(133), _IO_UD(134), 413 PORT_DATA_O(68), PORT_DATA_IO(69),
468 _IO_UD(135), _IO__D(136), _IO__D(137), _IO__D(138), _IO__D(139), 414
469 415 PORT_DATA_IO(70), PORT_DATA_IO(71),
470 _IO__D(140), _IO__D(141), _IO__D(142), _IO_UD(143), _IO__D(144), 416 PORT_DATA_O(72), PORT_DATA_I_PU(73),
471 _IO__D(145), _IO__D(146), _IO__D(147), _IO__D(148), _IO__D(149), 417 PORT_DATA_I_PU_PD(74), PORT_DATA_IO_PU_PD(75),
472 418 PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
473 _IO__D(150), _IO__D(151), _IO_UD(152), _I___D(153), _IO_UD(154), 419 PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
474 _I___D(155), _IO__D(156), _IO__D(157), _I___D(158), _IO__D(159), 420
475 421 PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
476 __O___(160), _IO__D(161), _IO__D(162), _IO__D(163), _I___D(164), 422 PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83),
477 _IO__D(165), _I___D(166), _I___D(167), _I___D(168), _I___D(169), 423 PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85),
478 424 PORT_DATA_IO_PU_PD(86), PORT_DATA_IO_PU_PD(87),
479 _I___D(170), __O___(171), _IO_UD(172), _IO_UD(173), _IO_UD(174), 425 PORT_DATA_IO_PU_PD(88), PORT_DATA_IO_PU_PD(89),
480 _IO_UD(175), _IO_UD(176), _IO_UD(177), _IO_UD(178), __O___(179), 426
481 427 PORT_DATA_IO_PU_PD(90), PORT_DATA_IO_PU_PD(91),
482 _IO_UD(180), _IO_UD(181), _IO_UD(182), _IO_UD(183), _IO_UD(184), 428 PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
483 __O___(185), _IO_UD(186), _IO_UD(187), _IO_UD(188), _IO_UD(189), 429 PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
484 430 PORT_DATA_IO_PU(96), PORT_DATA_IO_PU_PD(97),
485 _IO_UD(190), 431 PORT_DATA_IO_PU_PD(98), PORT_DATA_O(99), /*99?*/
432
433 PORT_DATA_IO_PD(100), PORT_DATA_IO_PD(101),
434 PORT_DATA_IO_PD(102), PORT_DATA_IO_PD(103),
435 PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105),
436 PORT_DATA_IO_PU(106), PORT_DATA_IO_PU(107),
437 PORT_DATA_IO_PU(108), PORT_DATA_IO_PU(109),
438
439 PORT_DATA_IO_PU(110), PORT_DATA_IO_PU(111),
440 PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113),
441 PORT_DATA_IO_PU(114), PORT_DATA_IO_PU(115),
442 PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117),
443 PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119),
444
445 PORT_DATA_IO_PU(120), PORT_DATA_IO_PD(121),
446 PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
447 PORT_DATA_IO_PD(124), PORT_DATA_IO_PD(125),
448 PORT_DATA_IO_PD(126), PORT_DATA_IO_PD(127),
449 PORT_DATA_IO_PD(128), PORT_DATA_IO_PU_PD(129),
450
451 PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131),
452 PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133),
453 PORT_DATA_IO_PU_PD(134), PORT_DATA_IO_PU_PD(135),
454 PORT_DATA_IO_PD(136), PORT_DATA_IO_PD(137),
455 PORT_DATA_IO_PD(138), PORT_DATA_IO_PD(139),
456
457 PORT_DATA_IO_PD(140), PORT_DATA_IO_PD(141),
458 PORT_DATA_IO_PD(142), PORT_DATA_IO_PU_PD(143),
459 PORT_DATA_IO_PD(144), PORT_DATA_IO_PD(145),
460 PORT_DATA_IO_PD(146), PORT_DATA_IO_PD(147),
461 PORT_DATA_IO_PD(148), PORT_DATA_IO_PD(149),
462
463 PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151),
464 PORT_DATA_IO_PU_PD(152), PORT_DATA_I_PD(153),
465 PORT_DATA_IO_PU_PD(154), PORT_DATA_I_PD(155),
466 PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157),
467 PORT_DATA_I_PD(158), PORT_DATA_IO_PD(159),
468
469 PORT_DATA_O(160), PORT_DATA_IO_PD(161),
470 PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
471 PORT_DATA_I_PD(164), PORT_DATA_IO_PD(165),
472 PORT_DATA_I_PD(166), PORT_DATA_I_PD(167),
473 PORT_DATA_I_PD(168), PORT_DATA_I_PD(169),
474
475 PORT_DATA_I_PD(170), PORT_DATA_O(171),
476 PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173),
477 PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175),
478 PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177),
479 PORT_DATA_IO_PU_PD(178), PORT_DATA_O(179),
480
481 PORT_DATA_IO_PU_PD(180), PORT_DATA_IO_PU_PD(181),
482 PORT_DATA_IO_PU_PD(182), PORT_DATA_IO_PU_PD(183),
483 PORT_DATA_IO_PU_PD(184), PORT_DATA_O(185),
484 PORT_DATA_IO_PU_PD(186), PORT_DATA_IO_PU_PD(187),
485 PORT_DATA_IO_PU_PD(188), PORT_DATA_IO_PU_PD(189),
486
487 PORT_DATA_IO_PU_PD(190),
486 488
487 /* IRQ */ 489 /* IRQ */
488 PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0), 490 PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0),
@@ -926,10 +928,6 @@ static pinmux_enum_t pinmux_data[] = {
926 PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1), 928 PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1),
927}; 929};
928 930
929#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
930#define GPIO_PORT_ALL() _190(_GPIO_PORT, , unused)
931#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
932
933static struct pinmux_gpio pinmux_gpios[] = { 931static struct pinmux_gpio pinmux_gpios[] = {
934 932
935 /* PORT */ 933 /* PORT */
@@ -1201,22 +1199,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1201 GPIO_FN(SDENC_DV_CLKI), 1199 GPIO_FN(SDENC_DV_CLKI),
1202}; 1200};
1203 1201
1204/* helper for top 4 bits in PORTnCR */
1205#define PCRH(in, in_pd, in_pu, out) \
1206 0, (out), (in), 0, \
1207 0, 0, 0, 0, \
1208 0, 0, (in_pd), 0, \
1209 0, 0, (in_pu), 0
1210
1211#define PORTCR(nr, reg) \
1212 { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
1213 PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
1214 PORT##nr##_IN_PU, PORT##nr##_OUT), \
1215 PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
1216 PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
1217 PORT##nr##_FN6, PORT##nr##_FN7 } \
1218 }
1219
1220static struct pinmux_cfg_reg pinmux_config_regs[] = { 1202static struct pinmux_cfg_reg pinmux_config_regs[] = {
1221 PORTCR(0, 0xE6051000), /* PORT0CR */ 1203 PORTCR(0, 0xE6051000), /* PORT0CR */
1222 PORTCR(1, 0xE6051001), /* PORT1CR */ 1204 PORTCR(1, 0xE6051001), /* PORT1CR */
diff --git a/arch/arm/mach-shmobile/pfc-sh7377.c b/arch/arm/mach-shmobile/pfc-sh7377.c
index 613e6842ad05..2f10511946ad 100644
--- a/arch/arm/mach-shmobile/pfc-sh7377.c
+++ b/arch/arm/mach-shmobile/pfc-sh7377.c
@@ -22,84 +22,65 @@
22#include <linux/gpio.h> 22#include <linux/gpio.h>
23#include <mach/sh7377.h> 23#include <mach/sh7377.h>
24 24
25#define _1(fn, pfx, sfx) fn(pfx, sfx) 25#define CPU_ALL_PORT(fn, pfx, sfx) \
26 26 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
27#define _10(fn, pfx, sfx) \ 27 PORT_10(fn, pfx##10, sfx), \
28 _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \ 28 PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
29 _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \ 29 PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
30 _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \ 30 PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
31 _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \ 31 PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
32 _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx) 32 PORT_1(fn, pfx##118, sfx), \
33 33 PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
34#define _90(fn, pfx, sfx) \ 34 PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
35 _10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \ 35 PORT_10(fn, pfx##15, sfx), \
36 _10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \ 36 PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
37 _10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \ 37 PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
38 _10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx), \ 38 PORT_1(fn, pfx##164, sfx), \
39 _10(fn, pfx##9, sfx) 39 PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
40 40 PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
41#define _265(fn, pfx, sfx) \ 41 PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
42 _10(fn, pfx, sfx), _90(fn, pfx, sfx), \ 42 PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
43 _10(fn, pfx##10, sfx), \ 43 PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
44 _1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx), \ 44 PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
45 _1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx), \ 45 PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
46 _1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx), \ 46 PORT_1(fn, pfx##260, sfx), PORT_1(fn, pfx##261, sfx), \
47 _1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx), \ 47 PORT_1(fn, pfx##262, sfx), PORT_1(fn, pfx##263, sfx), \
48 _1(fn, pfx##118, sfx), \ 48 PORT_1(fn, pfx##264, sfx)
49 _1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx), \
50 _10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx), \
51 _10(fn, pfx##15, sfx), \
52 _1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx), \
53 _1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx), \
54 _1(fn, pfx##164, sfx), \
55 _1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx), \
56 _1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx), \
57 _1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx), \
58 _1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx), \
59 _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \
60 _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \
61 _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \
62 _1(fn, pfx##260, sfx), _1(fn, pfx##261, sfx), \
63 _1(fn, pfx##262, sfx), _1(fn, pfx##263, sfx), \
64 _1(fn, pfx##264, sfx)
65
66#define _PORT(pfx, sfx) pfx##_##sfx
67#define PORT_265(str) _265(_PORT, PORT, str)
68 49
69enum { 50enum {
70 PINMUX_RESERVED = 0, 51 PINMUX_RESERVED = 0,
71 52
72 PINMUX_DATA_BEGIN, 53 PINMUX_DATA_BEGIN,
73 PORT_265(DATA), /* PORT0_DATA -> PORT264_DATA */ 54 PORT_ALL(DATA), /* PORT0_DATA -> PORT264_DATA */
74 PINMUX_DATA_END, 55 PINMUX_DATA_END,
75 56
76 PINMUX_INPUT_BEGIN, 57 PINMUX_INPUT_BEGIN,
77 PORT_265(IN), /* PORT0_IN -> PORT264_IN */ 58 PORT_ALL(IN), /* PORT0_IN -> PORT264_IN */
78 PINMUX_INPUT_END, 59 PINMUX_INPUT_END,
79 60
80 PINMUX_INPUT_PULLUP_BEGIN, 61 PINMUX_INPUT_PULLUP_BEGIN,
81 PORT_265(IN_PU), /* PORT0_IN_PU -> PORT264_IN_PU */ 62 PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT264_IN_PU */
82 PINMUX_INPUT_PULLUP_END, 63 PINMUX_INPUT_PULLUP_END,
83 64
84 PINMUX_INPUT_PULLDOWN_BEGIN, 65 PINMUX_INPUT_PULLDOWN_BEGIN,
85 PORT_265(IN_PD), /* PORT0_IN_PD -> PORT264_IN_PD */ 66 PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT264_IN_PD */
86 PINMUX_INPUT_PULLDOWN_END, 67 PINMUX_INPUT_PULLDOWN_END,
87 68
88 PINMUX_OUTPUT_BEGIN, 69 PINMUX_OUTPUT_BEGIN,
89 PORT_265(OUT), /* PORT0_OUT -> PORT264_OUT */ 70 PORT_ALL(OUT), /* PORT0_OUT -> PORT264_OUT */
90 PINMUX_OUTPUT_END, 71 PINMUX_OUTPUT_END,
91 72
92 PINMUX_FUNCTION_BEGIN, 73 PINMUX_FUNCTION_BEGIN,
93 PORT_265(FN_IN), /* PORT0_FN_IN -> PORT264_FN_IN */ 74 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT264_FN_IN */
94 PORT_265(FN_OUT), /* PORT0_FN_OUT -> PORT264_FN_OUT */ 75 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT264_FN_OUT */
95 PORT_265(FN0), /* PORT0_FN0 -> PORT264_FN0 */ 76 PORT_ALL(FN0), /* PORT0_FN0 -> PORT264_FN0 */
96 PORT_265(FN1), /* PORT0_FN1 -> PORT264_FN1 */ 77 PORT_ALL(FN1), /* PORT0_FN1 -> PORT264_FN1 */
97 PORT_265(FN2), /* PORT0_FN2 -> PORT264_FN2 */ 78 PORT_ALL(FN2), /* PORT0_FN2 -> PORT264_FN2 */
98 PORT_265(FN3), /* PORT0_FN3 -> PORT264_FN3 */ 79 PORT_ALL(FN3), /* PORT0_FN3 -> PORT264_FN3 */
99 PORT_265(FN4), /* PORT0_FN4 -> PORT264_FN4 */ 80 PORT_ALL(FN4), /* PORT0_FN4 -> PORT264_FN4 */
100 PORT_265(FN5), /* PORT0_FN5 -> PORT264_FN5 */ 81 PORT_ALL(FN5), /* PORT0_FN5 -> PORT264_FN5 */
101 PORT_265(FN6), /* PORT0_FN6 -> PORT264_FN6 */ 82 PORT_ALL(FN6), /* PORT0_FN6 -> PORT264_FN6 */
102 PORT_265(FN7), /* PORT0_FN7 -> PORT264_FN7 */ 83 PORT_ALL(FN7), /* PORT0_FN7 -> PORT264_FN7 */
103 84
104 MSELBCR_MSEL17_1, MSELBCR_MSEL17_0, 85 MSELBCR_MSEL17_1, MSELBCR_MSEL17_0,
105 MSELBCR_MSEL16_1, MSELBCR_MSEL16_0, 86 MSELBCR_MSEL16_1, MSELBCR_MSEL16_0,
@@ -360,45 +341,6 @@ enum {
360 PINMUX_MARK_END, 341 PINMUX_MARK_END,
361}; 342};
362 343
363#define PORT_DATA_I(nr) \
364 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
365
366#define PORT_DATA_I_PD(nr) \
367 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
368 PORT##nr##_IN, PORT##nr##_IN_PD)
369
370#define PORT_DATA_I_PU(nr) \
371 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
372 PORT##nr##_IN, PORT##nr##_IN_PU)
373
374#define PORT_DATA_I_PU_PD(nr) \
375 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
376 PORT##nr##_IN, PORT##nr##_IN_PD, \
377 PORT##nr##_IN_PU)
378
379#define PORT_DATA_O(nr) \
380 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
381 PORT##nr##_OUT)
382
383#define PORT_DATA_IO(nr) \
384 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
385 PORT##nr##_OUT, PORT##nr##_IN)
386
387#define PORT_DATA_IO_PD(nr) \
388 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
389 PORT##nr##_OUT, PORT##nr##_IN, \
390 PORT##nr##_IN_PD)
391
392#define PORT_DATA_IO_PU(nr) \
393 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
394 PORT##nr##_OUT, PORT##nr##_IN, \
395 PORT##nr##_IN_PU)
396
397#define PORT_DATA_IO_PU_PD(nr) \
398 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
399 PORT##nr##_OUT, PORT##nr##_IN, \
400 PORT##nr##_IN_PD, PORT##nr##_IN_PU)
401
402static pinmux_enum_t pinmux_data[] = { 344static pinmux_enum_t pinmux_data[] = {
403 /* specify valid pin states for each pin in GPIO mode */ 345 /* specify valid pin states for each pin in GPIO mode */
404 /* 55-1 (GPIO) */ 346 /* 55-1 (GPIO) */
@@ -1078,13 +1020,9 @@ static pinmux_enum_t pinmux_data[] = {
1078 PINMUX_DATA(RESETOUTS_MARK, PORT264_FN1), 1020 PINMUX_DATA(RESETOUTS_MARK, PORT264_FN1),
1079}; 1021};
1080 1022
1081#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
1082#define GPIO_PORT_265() _265(_GPIO_PORT, , unused)
1083#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
1084
1085static struct pinmux_gpio pinmux_gpios[] = { 1023static struct pinmux_gpio pinmux_gpios[] = {
1086 /* 55-1 -> 55-5 (GPIO) */ 1024 /* 55-1 -> 55-5 (GPIO) */
1087 GPIO_PORT_265(), 1025 GPIO_PORT_ALL(),
1088 1026
1089 /* Special Pull-up / Pull-down Functions */ 1027 /* Special Pull-up / Pull-down Functions */
1090 GPIO_FN(PORT66_KEYIN0_PU), GPIO_FN(PORT67_KEYIN1_PU), 1028 GPIO_FN(PORT66_KEYIN0_PU), GPIO_FN(PORT67_KEYIN1_PU),
@@ -1362,23 +1300,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1362 GPIO_FN(RESETOUTS), 1300 GPIO_FN(RESETOUTS),
1363}; 1301};
1364 1302
1365/* helper for top 4 bits in PORTnCR */
1366#define PCRH(in, in_pd, in_pu, out) \
1367 0, (out), (in), 0, \
1368 0, 0, 0, 0, \
1369 0, 0, (in_pd), 0, \
1370 0, 0, (in_pu), 0
1371
1372#define PORTCR(nr, reg) \
1373 { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
1374 PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
1375 PORT##nr##_IN_PU, PORT##nr##_OUT), \
1376 PORT##nr##_FN0, PORT##nr##_FN1, \
1377 PORT##nr##_FN2, PORT##nr##_FN3, \
1378 PORT##nr##_FN4, PORT##nr##_FN5, \
1379 PORT##nr##_FN6, PORT##nr##_FN7 } \
1380 }
1381
1382static struct pinmux_cfg_reg pinmux_config_regs[] = { 1303static struct pinmux_cfg_reg pinmux_config_regs[] = {
1383 PORTCR(0, 0xe6050000), /* PORT0CR */ 1304 PORTCR(0, 0xe6050000), /* PORT0CR */
1384 PORTCR(1, 0xe6050001), /* PORT1CR */ 1305 PORTCR(1, 0xe6050001), /* PORT1CR */
diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c
index 5abe02fbd6b9..e05634ce2e0d 100644
--- a/arch/arm/mach-shmobile/pfc-sh73a0.c
+++ b/arch/arm/mach-shmobile/pfc-sh73a0.c
@@ -24,83 +24,71 @@
24#include <mach/sh73a0.h> 24#include <mach/sh73a0.h>
25#include <mach/irqs.h> 25#include <mach/irqs.h>
26 26
27#define _1(fn, pfx, sfx) fn(pfx, sfx) 27#define CPU_ALL_PORT(fn, pfx, sfx) \
28 28 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
29#define _10(fn, pfx, sfx) \ 29 PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx), \
30 _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \ 30 PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx), \
31 _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \ 31 PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx), \
32 _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \ 32 PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx), \
33 _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \ 33 PORT_10(fn, pfx##10, sfx), \
34 _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx) 34 PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
35 35 PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
36#define _310(fn, pfx, sfx) \ 36 PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
37 _10(fn, pfx, sfx), _10(fn, pfx##1, sfx), \ 37 PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
38 _10(fn, pfx##2, sfx), _10(fn, pfx##3, sfx), \ 38 PORT_1(fn, pfx##118, sfx), \
39 _10(fn, pfx##4, sfx), _10(fn, pfx##5, sfx), \ 39 PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
40 _10(fn, pfx##6, sfx), _10(fn, pfx##7, sfx), \ 40 PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
41 _10(fn, pfx##8, sfx), _10(fn, pfx##9, sfx), \ 41 PORT_10(fn, pfx##15, sfx), \
42 _10(fn, pfx##10, sfx), \ 42 PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
43 _1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx), \ 43 PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
44 _1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx), \ 44 PORT_1(fn, pfx##164, sfx), \
45 _1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx), \ 45 PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
46 _1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx), \ 46 PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
47 _1(fn, pfx##118, sfx), \ 47 PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
48 _1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx), \ 48 PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
49 _10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx), \ 49 PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
50 _10(fn, pfx##15, sfx), \ 50 PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
51 _1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx), \ 51 PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
52 _1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx), \ 52 PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \
53 _1(fn, pfx##164, sfx), \ 53 PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
54 _1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx), \ 54 PORT_1(fn, pfx##282, sfx), \
55 _1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx), \ 55 PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
56 _1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx), \ 56 PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx)
57 _1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx), \
58 _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \
59 _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \
60 _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \
61 _10(fn, pfx##26, sfx), _10(fn, pfx##27, sfx), \
62 _1(fn, pfx##280, sfx), _1(fn, pfx##281, sfx), \
63 _1(fn, pfx##282, sfx), \
64 _1(fn, pfx##288, sfx), _1(fn, pfx##289, sfx), \
65 _10(fn, pfx##29, sfx), _10(fn, pfx##30, sfx)
66
67#define _PORT(pfx, sfx) pfx##_##sfx
68#define PORT_310(str) _310(_PORT, PORT, str)
69 57
70enum { 58enum {
71 PINMUX_RESERVED = 0, 59 PINMUX_RESERVED = 0,
72 60
73 PINMUX_DATA_BEGIN, 61 PINMUX_DATA_BEGIN,
74 PORT_310(DATA), /* PORT0_DATA -> PORT309_DATA */ 62 PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */
75 PINMUX_DATA_END, 63 PINMUX_DATA_END,
76 64
77 PINMUX_INPUT_BEGIN, 65 PINMUX_INPUT_BEGIN,
78 PORT_310(IN), /* PORT0_IN -> PORT309_IN */ 66 PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
79 PINMUX_INPUT_END, 67 PINMUX_INPUT_END,
80 68
81 PINMUX_INPUT_PULLUP_BEGIN, 69 PINMUX_INPUT_PULLUP_BEGIN,
82 PORT_310(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */ 70 PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */
83 PINMUX_INPUT_PULLUP_END, 71 PINMUX_INPUT_PULLUP_END,
84 72
85 PINMUX_INPUT_PULLDOWN_BEGIN, 73 PINMUX_INPUT_PULLDOWN_BEGIN,
86 PORT_310(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */ 74 PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */
87 PINMUX_INPUT_PULLDOWN_END, 75 PINMUX_INPUT_PULLDOWN_END,
88 76
89 PINMUX_OUTPUT_BEGIN, 77 PINMUX_OUTPUT_BEGIN,
90 PORT_310(OUT), /* PORT0_OUT -> PORT309_OUT */ 78 PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
91 PINMUX_OUTPUT_END, 79 PINMUX_OUTPUT_END,
92 80
93 PINMUX_FUNCTION_BEGIN, 81 PINMUX_FUNCTION_BEGIN,
94 PORT_310(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */ 82 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */
95 PORT_310(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */ 83 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */
96 PORT_310(FN0), /* PORT0_FN0 -> PORT309_FN0 */ 84 PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */
97 PORT_310(FN1), /* PORT0_FN1 -> PORT309_FN1 */ 85 PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */
98 PORT_310(FN2), /* PORT0_FN2 -> PORT309_FN2 */ 86 PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */
99 PORT_310(FN3), /* PORT0_FN3 -> PORT309_FN3 */ 87 PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */
100 PORT_310(FN4), /* PORT0_FN4 -> PORT309_FN4 */ 88 PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */
101 PORT_310(FN5), /* PORT0_FN5 -> PORT309_FN5 */ 89 PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */
102 PORT_310(FN6), /* PORT0_FN6 -> PORT309_FN6 */ 90 PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */
103 PORT_310(FN7), /* PORT0_FN7 -> PORT309_FN7 */ 91 PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */
104 92
105 MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1, 93 MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
106 MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1, 94 MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
@@ -508,6 +496,14 @@ enum {
508 SDHICMD2_PU_MARK, 496 SDHICMD2_PU_MARK,
509 MMCCMD0_PU_MARK, 497 MMCCMD0_PU_MARK,
510 MMCCMD1_PU_MARK, 498 MMCCMD1_PU_MARK,
499 MMCD0_0_PU_MARK,
500 MMCD0_1_PU_MARK,
501 MMCD0_2_PU_MARK,
502 MMCD0_3_PU_MARK,
503 MMCD0_4_PU_MARK,
504 MMCD0_5_PU_MARK,
505 MMCD0_6_PU_MARK,
506 MMCD0_7_PU_MARK,
511 FSIBISLD_PU_MARK, 507 FSIBISLD_PU_MARK,
512 FSIACK_PU_MARK, 508 FSIACK_PU_MARK,
513 FSIAILR_PU_MARK, 509 FSIAILR_PU_MARK,
@@ -517,45 +513,6 @@ enum {
517 PINMUX_MARK_END, 513 PINMUX_MARK_END,
518}; 514};
519 515
520#define PORT_DATA_I(nr) \
521 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
522
523#define PORT_DATA_I_PD(nr) \
524 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
525 PORT##nr##_IN, PORT##nr##_IN_PD)
526
527#define PORT_DATA_I_PU(nr) \
528 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
529 PORT##nr##_IN, PORT##nr##_IN_PU)
530
531#define PORT_DATA_I_PU_PD(nr) \
532 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
533 PORT##nr##_IN, PORT##nr##_IN_PD, \
534 PORT##nr##_IN_PU)
535
536#define PORT_DATA_O(nr) \
537 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
538 PORT##nr##_OUT)
539
540#define PORT_DATA_IO(nr) \
541 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
542 PORT##nr##_OUT, PORT##nr##_IN)
543
544#define PORT_DATA_IO_PD(nr) \
545 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
546 PORT##nr##_OUT, PORT##nr##_IN, \
547 PORT##nr##_IN_PD)
548
549#define PORT_DATA_IO_PU(nr) \
550 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
551 PORT##nr##_OUT, PORT##nr##_IN, \
552 PORT##nr##_IN_PU)
553
554#define PORT_DATA_IO_PU_PD(nr) \
555 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
556 PORT##nr##_OUT, PORT##nr##_IN, \
557 PORT##nr##_IN_PD, PORT##nr##_IN_PU)
558
559static pinmux_enum_t pinmux_data[] = { 516static pinmux_enum_t pinmux_data[] = {
560 /* specify valid pin states for each pin in GPIO mode */ 517 /* specify valid pin states for each pin in GPIO mode */
561 518
@@ -1561,6 +1518,24 @@ static pinmux_enum_t pinmux_data[] = {
1561 MSEL4CR_MSEL15_0), 1518 MSEL4CR_MSEL15_0),
1562 PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU, 1519 PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU,
1563 MSEL4CR_MSEL15_1), 1520 MSEL4CR_MSEL15_1),
1521
1522 PINMUX_DATA(MMCD0_0_PU_MARK,
1523 PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0),
1524 PINMUX_DATA(MMCD0_1_PU_MARK,
1525 PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0),
1526 PINMUX_DATA(MMCD0_2_PU_MARK,
1527 PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0),
1528 PINMUX_DATA(MMCD0_3_PU_MARK,
1529 PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0),
1530 PINMUX_DATA(MMCD0_4_PU_MARK,
1531 PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0),
1532 PINMUX_DATA(MMCD0_5_PU_MARK,
1533 PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0),
1534 PINMUX_DATA(MMCD0_6_PU_MARK,
1535 PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0),
1536 PINMUX_DATA(MMCD0_7_PU_MARK,
1537 PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0),
1538
1564 PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU), 1539 PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU),
1565 PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU), 1540 PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
1566 PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU), 1541 PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
@@ -1568,12 +1543,8 @@ static pinmux_enum_t pinmux_data[] = {
1568 PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU), 1543 PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
1569}; 1544};
1570 1545
1571#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
1572#define GPIO_PORT_310() _310(_GPIO_PORT, , unused)
1573#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
1574
1575static struct pinmux_gpio pinmux_gpios[] = { 1546static struct pinmux_gpio pinmux_gpios[] = {
1576 GPIO_PORT_310(), 1547 GPIO_PORT_ALL(),
1577 1548
1578 /* Table 25-1 (Functions 0-7) */ 1549 /* Table 25-1 (Functions 0-7) */
1579 GPIO_FN(VBUS_0), 1550 GPIO_FN(VBUS_0),
@@ -2236,24 +2207,20 @@ static struct pinmux_gpio pinmux_gpios[] = {
2236 GPIO_FN(SDHICMD2_PU), 2207 GPIO_FN(SDHICMD2_PU),
2237 GPIO_FN(MMCCMD0_PU), 2208 GPIO_FN(MMCCMD0_PU),
2238 GPIO_FN(MMCCMD1_PU), 2209 GPIO_FN(MMCCMD1_PU),
2210 GPIO_FN(MMCD0_0_PU),
2211 GPIO_FN(MMCD0_1_PU),
2212 GPIO_FN(MMCD0_2_PU),
2213 GPIO_FN(MMCD0_3_PU),
2214 GPIO_FN(MMCD0_4_PU),
2215 GPIO_FN(MMCD0_5_PU),
2216 GPIO_FN(MMCD0_6_PU),
2217 GPIO_FN(MMCD0_7_PU),
2239 GPIO_FN(FSIACK_PU), 2218 GPIO_FN(FSIACK_PU),
2240 GPIO_FN(FSIAILR_PU), 2219 GPIO_FN(FSIAILR_PU),
2241 GPIO_FN(FSIAIBT_PU), 2220 GPIO_FN(FSIAIBT_PU),
2242 GPIO_FN(FSIAISLD_PU), 2221 GPIO_FN(FSIAISLD_PU),
2243}; 2222};
2244 2223
2245#define PORTCR(nr, reg) \
2246 { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
2247 0, \
2248 /*0001*/ PORT##nr##_OUT , \
2249 /*0010*/ PORT##nr##_IN , 0, 0, 0, 0, 0, 0, 0, \
2250 /*1010*/ PORT##nr##_IN_PD, 0, 0, 0, \
2251 /*1110*/ PORT##nr##_IN_PU, 0, \
2252 PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
2253 PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
2254 PORT##nr##_FN6, PORT##nr##_FN7, 0, 0, 0, 0, 0, 0, 0, 0 } \
2255 }
2256
2257static struct pinmux_cfg_reg pinmux_config_regs[] = { 2224static struct pinmux_cfg_reg pinmux_config_regs[] = {
2258 PORTCR(0, 0xe6050000), /* PORT0CR */ 2225 PORTCR(0, 0xe6050000), /* PORT0CR */
2259 PORTCR(1, 0xe6050001), /* PORT1CR */ 2226 PORTCR(1, 0xe6050001), /* PORT1CR */
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index 79612737c5b2..0a5b22942fd3 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -402,22 +402,18 @@ static void sh7372_setup_a3sm(unsigned long msk, unsigned long msk2)
402 402
403#ifdef CONFIG_CPU_IDLE 403#ifdef CONFIG_CPU_IDLE
404 404
405static void sh7372_cpuidle_setup(struct cpuidle_device *dev) 405static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
406{ 406{
407 struct cpuidle_state *state; 407 struct cpuidle_state *state = &drv->states[drv->state_count];
408 int i = dev->state_count;
409 408
410 state = &dev->states[i];
411 snprintf(state->name, CPUIDLE_NAME_LEN, "C2"); 409 snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
412 strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN); 410 strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
413 state->exit_latency = 10; 411 state->exit_latency = 10;
414 state->target_residency = 20 + 10; 412 state->target_residency = 20 + 10;
415 state->power_usage = 1; /* perhaps not */ 413 state->flags = CPUIDLE_FLAG_TIME_VALID;
416 state->flags = 0; 414 shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby;
417 state->flags |= CPUIDLE_FLAG_TIME_VALID;
418 shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
419 415
420 dev->state_count = i + 1; 416 drv->state_count++;
421} 417}
422 418
423static void sh7372_cpuidle_init(void) 419static void sh7372_cpuidle_init(void)
diff --git a/include/linux/sh_pfc.h b/include/linux/sh_pfc.h
index bc8c9208f7e2..8446789216e5 100644
--- a/include/linux/sh_pfc.h
+++ b/include/linux/sh_pfc.h
@@ -104,4 +104,80 @@ struct pinmux_info {
104int register_pinmux(struct pinmux_info *pip); 104int register_pinmux(struct pinmux_info *pip);
105int unregister_pinmux(struct pinmux_info *pip); 105int unregister_pinmux(struct pinmux_info *pip);
106 106
107/* helper macro for port */
108#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
109
110#define PORT_10(fn, pfx, sfx) \
111 PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
112 PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
113 PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
114 PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
115 PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
116
117#define PORT_90(fn, pfx, sfx) \
118 PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \
119 PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \
120 PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \
121 PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \
122 PORT_10(fn, pfx##9, sfx)
123
124#define _PORT_ALL(pfx, sfx) pfx##_##sfx
125#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
126#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
127#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused)
128#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
129
130/* helper macro for pinmux_enum_t */
131#define PORT_DATA_I(nr) \
132 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
133
134#define PORT_DATA_I_PD(nr) \
135 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
136 PORT##nr##_IN, PORT##nr##_IN_PD)
137
138#define PORT_DATA_I_PU(nr) \
139 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
140 PORT##nr##_IN, PORT##nr##_IN_PU)
141
142#define PORT_DATA_I_PU_PD(nr) \
143 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
144 PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
145
146#define PORT_DATA_O(nr) \
147 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
148
149#define PORT_DATA_IO(nr) \
150 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
151 PORT##nr##_IN)
152
153#define PORT_DATA_IO_PD(nr) \
154 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
155 PORT##nr##_IN, PORT##nr##_IN_PD)
156
157#define PORT_DATA_IO_PU(nr) \
158 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
159 PORT##nr##_IN, PORT##nr##_IN_PU)
160
161#define PORT_DATA_IO_PU_PD(nr) \
162 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
163 PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
164
165/* helper macro for top 4 bits in PORTnCR */
166#define _PCRH(in, in_pd, in_pu, out) \
167 0, (out), (in), 0, \
168 0, 0, 0, 0, \
169 0, 0, (in_pd), 0, \
170 0, 0, (in_pu), 0
171
172#define PORTCR(nr, reg) \
173 { \
174 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
175 _PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
176 PORT##nr##_IN_PU, PORT##nr##_OUT), \
177 PORT##nr##_FN0, PORT##nr##_FN1, \
178 PORT##nr##_FN2, PORT##nr##_FN3, \
179 PORT##nr##_FN4, PORT##nr##_FN5, \
180 PORT##nr##_FN6, PORT##nr##_FN7 } \
181 }
182
107#endif /* __SH_PFC_H */ 183#endif /* __SH_PFC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-03 08:02:51 -0500