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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-dove/Makefile2
-rw-r--r--arch/arm/mach-dove/addr-map.c125
-rw-r--r--arch/arm/mach-dove/board-dt.c2
-rw-r--r--arch/arm/mach-dove/common.c39
-rw-r--r--arch/arm/mach-dove/common.h2
-rw-r--r--arch/arm/mach-dove/include/mach/dove.h5
-rw-r--r--arch/arm/plat-orion/Makefile1
8 files changed, 47 insertions, 130 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 21c6dd5dceb2..6ee09663e929 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -562,6 +562,7 @@ config ARCH_DOVE
562 select PINCTRL_DOVE 562 select PINCTRL_DOVE
563 select PLAT_ORION_LEGACY 563 select PLAT_ORION_LEGACY
564 select USB_ARCH_HAS_EHCI 564 select USB_ARCH_HAS_EHCI
565 select MVEBU_MBUS
565 help 566 help
566 Support for the Marvell Dove SoC 88AP510 567 Support for the Marvell Dove SoC 88AP510
567 568
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index 3f0a858fb597..4d9d2ffc4535 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,4 +1,4 @@
1obj-y += common.o addr-map.o irq.o 1obj-y += common.o irq.o
2obj-$(CONFIG_DOVE_LEGACY) += mpp.o 2obj-$(CONFIG_DOVE_LEGACY) += mpp.o
3obj-$(CONFIG_PCI) += pcie.o 3obj-$(CONFIG_PCI) += pcie.o
4obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o 4obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o
diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
deleted file mode 100644
index 2a06c0163418..000000000000
--- a/arch/arm/mach-dove/addr-map.c
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * arch/arm/mach-dove/addr-map.c
3 *
4 * Address map functions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h>
15#include <asm/mach/arch.h>
16#include <asm/setup.h>
17#include <mach/dove.h>
18#include <plat/addr-map.h>
19#include "common.h"
20
21/*
22 * Generic Address Decode Windows bit settings
23 */
24#define TARGET_DDR 0x0
25#define TARGET_BOOTROM 0x1
26#define TARGET_CESA 0x3
27#define TARGET_PCIE0 0x4
28#define TARGET_PCIE1 0x8
29#define TARGET_SCRATCHPAD 0xd
30
31#define ATTR_CESA 0x01
32#define ATTR_BOOTROM 0xfd
33#define ATTR_DEV_SPI0_ROM 0xfe
34#define ATTR_DEV_SPI1_ROM 0xfb
35#define ATTR_PCIE_IO 0xe0
36#define ATTR_PCIE_MEM 0xe8
37#define ATTR_SCRATCHPAD 0x0
38
39static inline void __iomem *ddr_map_sc(int i)
40{
41 return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
42}
43
44/*
45 * Description of the windows needed by the platform code
46 */
47static struct __initdata orion_addr_map_cfg addr_map_cfg = {
48 .num_wins = 8,
49 .remappable_wins = 4,
50 .bridge_virt_base = BRIDGE_VIRT_BASE,
51};
52
53static const struct __initdata orion_addr_map_info addr_map_info[] = {
54 /*
55 * Windows for PCIe IO+MEM space.
56 */
57 { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
58 TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE
59 },
60 { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
61 TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE
62 },
63 { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
64 TARGET_PCIE0, ATTR_PCIE_MEM, -1
65 },
66 { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
67 TARGET_PCIE1, ATTR_PCIE_MEM, -1
68 },
69 /*
70 * Window for CESA engine.
71 */
72 { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
73 TARGET_CESA, ATTR_CESA, -1
74 },
75 /*
76 * Window to the BootROM for Standby and Sleep Resume
77 */
78 { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
79 TARGET_BOOTROM, ATTR_BOOTROM, -1
80 },
81 /*
82 * Window to the PMU Scratch Pad space
83 */
84 { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
85 TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1
86 },
87 /* End marker */
88 { -1, 0, 0, 0, 0, 0 }
89};
90
91void __init dove_setup_cpu_mbus(void)
92{
93 int i;
94 int cs;
95
96 /*
97 * Disable, clear and configure windows.
98 */
99 orion_config_wins(&addr_map_cfg, addr_map_info);
100
101 /*
102 * Setup MBUS dram target info.
103 */
104 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
105
106 for (i = 0, cs = 0; i < 2; i++) {
107 u32 map = readl(ddr_map_sc(i));
108
109 /*
110 * Chip select enabled?
111 */
112 if (map & 1) {
113 struct mbus_dram_window *w;
114
115 w = &orion_mbus_dram_info.cs[cs++];
116 w->cs_index = i;
117 w->mbus_attr = 0; /* CS address decoding done inside */
118 /* the DDR controller, no need to */
119 /* provide attributes */
120 w->base = map & 0xff800000;
121 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
122 }
123 }
124 orion_mbus_dram_info.num_cs = cs;
125}
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index fbde1dd67113..0b142803b2e1 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -64,7 +64,7 @@ static void __init dove_dt_init(void)
64#ifdef CONFIG_CACHE_TAUROS2 64#ifdef CONFIG_CACHE_TAUROS2
65 tauros2_init(0); 65 tauros2_init(0);
66#endif 66#endif
67 dove_setup_cpu_mbus(); 67 dove_setup_cpu_wins();
68 68
69 /* Setup root of clk tree */ 69 /* Setup root of clk tree */
70 dove_of_clk_init(); 70 dove_of_clk_init();
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index c6b3b2bb50e7..e2b5da031f96 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -224,6 +224,9 @@ void __init dove_i2c_init(void)
224void __init dove_init_early(void) 224void __init dove_init_early(void)
225{ 225{
226 orion_time_set_base(TIMER_VIRT_BASE); 226 orion_time_set_base(TIMER_VIRT_BASE);
227 mvebu_mbus_init("marvell,dove-mbus",
228 BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
229 DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
227} 230}
228 231
229static int __init dove_find_tclk(void) 232static int __init dove_find_tclk(void)
@@ -326,6 +329,40 @@ void __init dove_sdio1_init(void)
326 platform_device_register(&dove_sdio1); 329 platform_device_register(&dove_sdio1);
327} 330}
328 331
332void __init dove_setup_cpu_wins(void)
333{
334 /*
335 * The PCIe windows will no longer be statically allocated
336 * here once Dove is migrated to the pci-mvebu driver.
337 */
338 mvebu_mbus_add_window_remap_flags("pcie0.0",
339 DOVE_PCIE0_IO_PHYS_BASE,
340 DOVE_PCIE0_IO_SIZE,
341 DOVE_PCIE0_IO_BUS_BASE,
342 MVEBU_MBUS_PCI_IO);
343 mvebu_mbus_add_window_remap_flags("pcie1.0",
344 DOVE_PCIE1_IO_PHYS_BASE,
345 DOVE_PCIE1_IO_SIZE,
346 DOVE_PCIE1_IO_BUS_BASE,
347 MVEBU_MBUS_PCI_IO);
348 mvebu_mbus_add_window_remap_flags("pcie0.0",
349 DOVE_PCIE0_MEM_PHYS_BASE,
350 DOVE_PCIE0_MEM_SIZE,
351 MVEBU_MBUS_NO_REMAP,
352 MVEBU_MBUS_PCI_MEM);
353 mvebu_mbus_add_window_remap_flags("pcie1.0",
354 DOVE_PCIE1_MEM_PHYS_BASE,
355 DOVE_PCIE1_MEM_SIZE,
356 MVEBU_MBUS_NO_REMAP,
357 MVEBU_MBUS_PCI_MEM);
358 mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE,
359 DOVE_CESA_SIZE);
360 mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE,
361 DOVE_BOOTROM_SIZE);
362 mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE,
363 DOVE_SCRATCHPAD_SIZE);
364}
365
329void __init dove_init(void) 366void __init dove_init(void)
330{ 367{
331 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", 368 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
@@ -334,7 +371,7 @@ void __init dove_init(void)
334#ifdef CONFIG_CACHE_TAUROS2 371#ifdef CONFIG_CACHE_TAUROS2
335 tauros2_init(0); 372 tauros2_init(0);
336#endif 373#endif
337 dove_setup_cpu_mbus(); 374 dove_setup_cpu_wins();
338 375
339 /* Setup root of clk tree */ 376 /* Setup root of clk tree */
340 dove_clk_init(); 377 dove_clk_init();
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index ee59fba4c6d1..e86347928b67 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -23,7 +23,7 @@ void dove_map_io(void);
23void dove_init(void); 23void dove_init(void);
24void dove_init_early(void); 24void dove_init_early(void);
25void dove_init_irq(void); 25void dove_init_irq(void);
26void dove_setup_cpu_mbus(void); 26void dove_setup_cpu_wins(void);
27void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data); 27void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
28void dove_sata_init(struct mv_sata_platform_data *sata_data); 28void dove_sata_init(struct mv_sata_platform_data *sata_data);
29#ifdef CONFIG_PCI 29#ifdef CONFIG_PCI
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index 661725e3115a..0c4b35f4ee5b 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -77,6 +77,8 @@
77/* North-South Bridge */ 77/* North-South Bridge */
78#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000) 78#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000)
79#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000) 79#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000)
80#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE)
81#define BRIDGE_WINS_SZ (0x80)
80 82
81/* Cryptographic Engine */ 83/* Cryptographic Engine */
82#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000) 84#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000)
@@ -168,6 +170,9 @@
168#define DOVE_SSP_CLOCK_ENABLE (1 << 1) 170#define DOVE_SSP_CLOCK_ENABLE (1 << 1)
169#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) 171#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)
170/* Memory Controller */ 172/* Memory Controller */
173#define DOVE_MC_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x00000)
174#define DOVE_MC_WINS_BASE (DOVE_MC_PHYS_BASE + 0x100)
175#define DOVE_MC_WINS_SZ (0x8)
171#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000) 176#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000)
172 177
173/* LCD Controller */ 178/* LCD Controller */
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index 58db16d32607..9fd843e1785b 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -3,7 +3,6 @@
3# 3#
4ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include 4ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
5 5
6obj-$(CONFIG_ARCH_DOVE) += addr-map.o
7obj-$(CONFIG_ARCH_ORION5X) += addr-map.o 6obj-$(CONFIG_ARCH_ORION5X) += addr-map.o
8obj-$(CONFIG_ARCH_MV78XX0) += addr-map.o 7obj-$(CONFIG_ARCH_MV78XX0) += addr-map.o
9 8
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-08 08:14:06 -0500