13 files changed, 115 insertions, 40 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5b714695b01b..dedf02b6f322 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1684,8 +1684,9 @@ config SCHED_HRTICK
         def_bool HIGH_RES_TIMERS
 
 config THUMB2_KERNEL
-        bool "Compile the kernel in Thumb-2 mode"
+        bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
         depends on CPU_V7 && !CPU_V6 && !CPU_V6K
+        default y if CPU_THUMBONLY
         select AEABI
         select ARM_ASM_UNIFIED
         select ARM_UNWIND
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index 5ef4d8015a60..1f3262e99d81 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -42,6 +42,8 @@
 #define vectors_high()  (0)
 #endif
 
+#ifdef CONFIG_CPU_CP15
+
 extern unsigned long cr_no_alignment;   /* defined in entry-armv.S */
 extern unsigned long cr_alignment;      /* defined in entry-armv.S */
 
@@ -82,6 +84,18 @@ static inline void set_copro_access(unsigned int val)
         isb();
 }
 
-#endif
+#else /* ifdef CONFIG_CPU_CP15 */
+
+/*
+ * cr_alignment and cr_no_alignment are tightly coupled to cp15 (at least in the
+ * minds of the developers). Yielding 0 for machines without a cp15 (and making
+ * it read-only) is fine for most cases and saves quite some #ifdeffery.
+ */
+#define cr_no_alignment UL(0)
+#define cr_alignment    UL(0)
+
+#endif /* ifdef CONFIG_CPU_CP15 / else */
+
+#endif /* ifndef __ASSEMBLY__ */
 
 #endif
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index ad41ec2471e8..7652712d1d14 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -38,6 +38,24 @@
 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
         ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
 
+#define ARM_CPU_IMP_ARM                 0x41
+#define ARM_CPU_IMP_INTEL               0x69
+
+#define ARM_CPU_PART_ARM1136            0xB360
+#define ARM_CPU_PART_ARM1156            0xB560
+#define ARM_CPU_PART_ARM1176            0xB760
+#define ARM_CPU_PART_ARM11MPCORE        0xB020
+#define ARM_CPU_PART_CORTEX_A8          0xC080
+#define ARM_CPU_PART_CORTEX_A9          0xC090
+#define ARM_CPU_PART_CORTEX_A5          0xC050
+#define ARM_CPU_PART_CORTEX_A15         0xC0F0
+#define ARM_CPU_PART_CORTEX_A7          0xC070
+
+#define ARM_CPU_XSCALE_ARCH_MASK        0xe000
+#define ARM_CPU_XSCALE_ARCH_V1          0x2000
+#define ARM_CPU_XSCALE_ARCH_V2          0x4000
+#define ARM_CPU_XSCALE_ARCH_V3          0x6000
+
 extern unsigned int processor_id;
 
 #ifdef CONFIG_CPU_CP15
@@ -50,6 +68,7 @@ extern unsigned int processor_id;
                     : "cc");                                            \
                 __val;                                                  \
         })
+
 #define read_cpuid_ext(ext_reg)                                         \
         ({                                                              \
                 unsigned int __val;                                     \
@@ -59,29 +78,24 @@ extern unsigned int processor_id;
                     : "cc");                                            \
                 __val;                                                  \
         })
-#else
-#define read_cpuid(reg) (processor_id)
-#define read_cpuid_ext(reg) 0
-#endif
 
-#define ARM_CPU_IMP_ARM                 0x41
-#define ARM_CPU_IMP_INTEL               0x69
+#else /* ifdef CONFIG_CPU_CP15 */
 
-#define ARM_CPU_PART_ARM1136            0xB360
-#define ARM_CPU_PART_ARM1156            0xB560
-#define ARM_CPU_PART_ARM1176            0xB760
-#define ARM_CPU_PART_ARM11MPCORE        0xB020
-#define ARM_CPU_PART_CORTEX_A8          0xC080
-#define ARM_CPU_PART_CORTEX_A9          0xC090
-#define ARM_CPU_PART_CORTEX_A5          0xC050
-#define ARM_CPU_PART_CORTEX_A15         0xC0F0
-#define ARM_CPU_PART_CORTEX_A7          0xC070
+/*
+ * read_cpuid and read_cpuid_ext should only ever be called on machines that
+ * have cp15 so warn on other usages.
+ */
+#define read_cpuid(reg)                                                 \
+        ({                                                              \
+                WARN_ON_ONCE(1);                                        \
+                0;                                                      \
+        })
 
-#define ARM_CPU_XSCALE_ARCH_MASK        0xe000
-#define ARM_CPU_XSCALE_ARCH_V1          0x2000
-#define ARM_CPU_XSCALE_ARCH_V2          0x4000
-#define ARM_CPU_XSCALE_ARCH_V3          0x6000
+#define read_cpuid_ext(reg) read_cpuid(reg)
+
+#endif /* ifdef CONFIG_CPU_CP15 / else */
 
+#ifdef CONFIG_CPU_CP15
 /*
  * The CPU ID never changes at run time, so we might as well tell the
  * compiler that it's constant.  Use this function to read the CPU ID
@@ -92,6 +106,15 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
         return read_cpuid(CPUID_ID);
 }
 
+#else /* ifdef CONFIG_CPU_CP15 */
+
+static inline unsigned int __attribute_const__ read_cpuid_id(void)
+{
+        return processor_id;
+}
+
+#endif /* ifdef CONFIG_CPU_CP15 / else */
+
 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 {
         return (read_cpuid_id() & 0xFF000000) >> 24;
diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h
index 8cacbcda76da..b6e9f2c108b5 100644
--- a/arch/arm/include/asm/glue-df.h
+++ b/arch/arm/include/asm/glue-df.h
@@ -18,12 +18,12 @@
  *      ================
  *
  *      We have the following to choose from:
- *        arm6          - ARM6 style
  *        arm7          - ARM7 style
  *        v4_early      - ARMv4 without Thumb early abort handler
  *        v4t_late      - ARMv4 with Thumb late abort handler
  *        v4t_early     - ARMv4 with Thumb early abort handler
- *        v5tej_early   - ARMv5 with Thumb and Java early abort handler
+ *        v5t_early     - ARMv5 with Thumb early abort handler
+ *        v5tj_early    - ARMv5 with Thumb and Java early abort handler
  *        xscale        - ARMv5 with Thumb with Xscale extensions
  *        v6_early      - ARMv6 generic early abort handler
  *        v7_early      - ARMv7 generic early abort handler
@@ -39,19 +39,19 @@
 # endif
 #endif
 
-#ifdef CONFIG_CPU_ABRT_LV4T
+#ifdef CONFIG_CPU_ABRT_EV4
 # ifdef CPU_DABORT_HANDLER
 #  define MULTI_DABORT 1
 # else
-#  define CPU_DABORT_HANDLER v4t_late_abort
+#  define CPU_DABORT_HANDLER v4_early_abort
 # endif
 #endif
 
-#ifdef CONFIG_CPU_ABRT_EV4
+#ifdef CONFIG_CPU_ABRT_LV4T
 # ifdef CPU_DABORT_HANDLER
 #  define MULTI_DABORT 1
 # else
-#  define CPU_DABORT_HANDLER v4_early_abort
+#  define CPU_DABORT_HANDLER v4t_late_abort
 # endif
 #endif
 
@@ -63,19 +63,19 @@
 # endif
 #endif
 
-#ifdef CONFIG_CPU_ABRT_EV5TJ
+#ifdef CONFIG_CPU_ABRT_EV5T
 # ifdef CPU_DABORT_HANDLER
 #  define MULTI_DABORT 1
 # else
-#  define CPU_DABORT_HANDLER v5tj_early_abort
+#  define CPU_DABORT_HANDLER v5t_early_abort
 # endif
 #endif
 
-#ifdef CONFIG_CPU_ABRT_EV5T
+#ifdef CONFIG_CPU_ABRT_EV5TJ
 # ifdef CPU_DABORT_HANDLER
 #  define MULTI_DABORT 1
 # else
-#  define CPU_DABORT_HANDLER v5t_early_abort
+#  define CPU_DABORT_HANDLER v5tj_early_abort
 # endif
 #endif
 
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 854bd22380d3..5b391a689b47 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -98,8 +98,9 @@ __mmap_switched:
         str     r9, [r4]                        @ Save processor ID
         str     r1, [r5]                        @ Save machine type
         str     r2, [r6]                        @ Save atags pointer
-        bic     r4, r0, #CR_A                   @ Clear 'A' bit
-        stmia   r7, {r0, r4}                    @ Save control register values
+        cmp     r7, #0
+        bicne   r4, r0, #CR_A                   @ Clear 'A' bit
+        stmneia r7, {r0, r4}                    @ Save control register values
         b       start_kernel
 ENDPROC(__mmap_switched)
 
@@ -113,7 +114,11 @@ __mmap_switched_data:
         .long   processor_id                    @ r4
         .long   __machine_arch_type             @ r5
         .long   __atags_pointer                 @ r6
+#ifdef CONFIG_CPU_CP15
         .long   cr_alignment                    @ r7
+#else
+        .long   0                               @ r7
+#endif
         .long   init_thread_union + THREAD_START_SP @ sp
         .size   __mmap_switched_data, . - __mmap_switched_data
 
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 2c228a07e58c..6a2e09c952c7 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -32,15 +32,21 @@
  * numbers for r1.
  *
  */
-        .arm
 
         __HEAD
+
+#ifdef CONFIG_CPU_THUMBONLY
+        .thumb
+ENTRY(stext)
+#else
+        .arm
 ENTRY(stext)
 
  THUMB( adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
  THUMB( bx      r9              )       @ If this is a Thumb-2 kernel,
  THUMB( .thumb                  )       @ switch to Thumb now.
  THUMB(1:                       )
+#endif
 
         setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
                                                 @ and irqs disabled
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 3f6cbb2e3eda..1cc9e1796415 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -291,10 +291,10 @@ static int cpu_has_aliasing_icache(unsigned int arch)
 
 static void __init cacheid_init(void)
 {
-        unsigned int cachetype = read_cpuid_cachetype();
         unsigned int arch = cpu_architecture();
 
         if (arch >= CPU_ARCH_ARMv6) {
+                unsigned int cachetype = read_cpuid_cachetype();
                 if ((cachetype & (7 << 29)) == 4 << 29) {
                         /* ARMv7 register format */
                         arch = CPU_ARCH_ARMv7;
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 45eac87ed66a..5bc1a63284e3 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -41,7 +41,7 @@ void scu_enable(void __iomem *scu_base)
 
 #ifdef CONFIG_ARM_ERRATA_764369
         /* Cortex-A9 only */
-        if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
+        if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc090) {
                 scu_ctrl = __raw_readl(scu_base + 0x30);
                 if (!(scu_ctrl & 1))
                         __raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 8a68f1ec66b9..577298ed5a44 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -300,7 +300,7 @@ void __init omap3xxx_check_revision(void)
          * If the processor type is Cortex-A8 and the revision is 0x0
          * it means its Cortex r0p0 which is 3430 ES1.0.
          */
-        cpuid = read_cpuid(CPUID_ID);
+        cpuid = read_cpuid_id();
         if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
                 omap_revision = OMAP3430_REV_ES1_0;
                 cpu_rev = "1.0";
@@ -460,7 +460,7 @@ void __init omap4xxx_check_revision(void)
          * Use ARM register to detect the correct ES version
          */
         if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
-                idcode = read_cpuid(CPUID_ID);
+                idcode = read_cpuid_id();
                 rev = (idcode & 0xf) - 1;
         }
 
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index d9727218dd0a..7f5626d8fd3e 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -209,7 +209,7 @@ static void __init omap4_smp_init_cpus(void)
         unsigned int i = 0, ncores = 1, cpu_id;
 
         /* Use ARM cpuid check here, as SoC detection will not work so early */
-        cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
+        cpu_id = read_cpuid_id() & CPU_MASK;
         if (cpu_id == CPU_CORTEX_A9) {
                 /*
                  * Currently we can't call ioremap here because
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 025d17328730..cb812a13e299 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -397,6 +397,13 @@ config CPU_V7
         select CPU_PABRT_V7
         select CPU_TLB_V7 if MMU
 
+config CPU_THUMBONLY
+        bool
+        # There are no CPUs available with MMU that don't implement an ARM ISA:
+        depends on !MMU
+        help
+          Select this if your CPU doesn't support the 32 bit ARM instructions.
+
 # Figure out what processor architecture version we should be using.
 # This defines the compiler instruction set which depends on the machine type.
 config CPU_32v3
@@ -608,7 +615,7 @@ config ARCH_DMA_ADDR_T_64BIT
         bool
 
 config ARM_THUMB
-        bool "Support Thumb user binaries"
+        bool "Support Thumb user binaries" if !CPU_THUMBONLY
         depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
         default y
         help
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index db26e2e543f4..6f4585b89078 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -961,12 +961,14 @@ static int __init alignment_init(void)
                 return -ENOMEM;
 #endif
 
+#ifdef CONFIG_CPU_CP15
         if (cpu_is_v6_unaligned()) {
                 cr_alignment &= ~CR_A;
                 cr_no_alignment &= ~CR_A;
                 set_cr(cr_alignment);
                 ai_usermode = safe_usermode(ai_usermode, false);
         }
+#endif
 
         hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
                         "alignment exception");
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e95a996ab78f..c6d45c87540e 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -112,6 +112,7 @@ static struct cachepolicy cache_policies[] __initdata = {
         }
 };
 
+#ifdef CONFIG_CPU_CP15
 /*
  * These are useful for identifying cache coherency
  * problems by allowing the cache or the cache and
@@ -210,6 +211,22 @@ void adjust_cr(unsigned long mask, unsigned long set)
 }
 #endif
 
+#else /* ifdef CONFIG_CPU_CP15 */
+
+static int __init early_cachepolicy(char *p)
+{
+        pr_warning("cachepolicy kernel parameter not supported without cp15\n");
+}
+early_param("cachepolicy", early_cachepolicy);
+
+static int __init noalign_setup(char *__unused)
+{
+        pr_warning("noalign kernel parameter not supported without cp15\n");
+}
+__setup("noalign", noalign_setup);
+
+#endif /* ifdef CONFIG_CPU_CP15 / else */
+
 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE