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-rw-r--r--arch/arm64/include/asm/sysreg.h60
-rw-r--r--arch/arm64/kernel/head.S6
-rw-r--r--drivers/irqchip/irq-gic-v3.c16
-rw-r--r--include/linux/irqchip/arm-gic-v3.h42
4 files changed, 93 insertions, 31 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
new file mode 100644
index 000000000000..5c89df0acbcb
--- /dev/null
+++ b/arch/arm64/include/asm/sysreg.h
@@ -0,0 +1,60 @@
1/*
2 * Macros for accessing system registers with older binutils.
3 *
4 * Copyright (C) 2014 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef __ASM_SYSREG_H
21#define __ASM_SYSREG_H
22
23#define sys_reg(op0, op1, crn, crm, op2) \
24 ((((op0)-2)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
25
26#ifdef __ASSEMBLY__
27
28 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
29 .equ __reg_num_x\num, \num
30 .endr
31 .equ __reg_num_xzr, 31
32
33 .macro mrs_s, rt, sreg
34 .inst 0xd5300000|(\sreg)|(__reg_num_\rt)
35 .endm
36
37 .macro msr_s, sreg, rt
38 .inst 0xd5100000|(\sreg)|(__reg_num_\rt)
39 .endm
40
41#else
42
43asm(
44" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
45" .equ __reg_num_x\\num, \\num\n"
46" .endr\n"
47" .equ __reg_num_xzr, 31\n"
48"\n"
49" .macro mrs_s, rt, sreg\n"
50" .inst 0xd5300000|(\\sreg)|(__reg_num_\\rt)\n"
51" .endm\n"
52"\n"
53" .macro msr_s, sreg, rt\n"
54" .inst 0xd5100000|(\\sreg)|(__reg_num_\\rt)\n"
55" .endm\n"
56);
57
58#endif
59
60#endif /* __ASM_SYSREG_H */
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index c99e3a879ebc..144f10567f82 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -297,12 +297,12 @@ CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
297 cmp x0, #1 297 cmp x0, #1
298 b.ne 3f 298 b.ne 3f
299 299
300 mrs x0, ICC_SRE_EL2 300 mrs_s x0, ICC_SRE_EL2
301 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 301 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
302 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 302 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
303 msr ICC_SRE_EL2, x0 303 msr_s ICC_SRE_EL2, x0
304 isb // Make sure SRE is now set 304 isb // Make sure SRE is now set
305 msr ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults 305 msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
306 306
3073: 3073:
308#endif 308#endif
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 81519bae0453..57eaa5a0b1e3 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -108,39 +108,39 @@ static u64 gic_read_iar(void)
108{ 108{
109 u64 irqstat; 109 u64 irqstat;
110 110
111 asm volatile("mrs %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); 111 asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
112 return irqstat; 112 return irqstat;
113} 113}
114 114
115static void gic_write_pmr(u64 val) 115static void gic_write_pmr(u64 val)
116{ 116{
117 asm volatile("msr " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val)); 117 asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
118} 118}
119 119
120static void gic_write_ctlr(u64 val) 120static void gic_write_ctlr(u64 val)
121{ 121{
122 asm volatile("msr " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val)); 122 asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
123 isb(); 123 isb();
124} 124}
125 125
126static void gic_write_grpen1(u64 val) 126static void gic_write_grpen1(u64 val)
127{ 127{
128 asm volatile("msr " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val)); 128 asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
129 isb(); 129 isb();
130} 130}
131 131
132static void gic_write_sgi1r(u64 val) 132static void gic_write_sgi1r(u64 val)
133{ 133{
134 asm volatile("msr " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); 134 asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
135} 135}
136 136
137static void gic_enable_sre(void) 137static void gic_enable_sre(void)
138{ 138{
139 u64 val; 139 u64 val;
140 140
141 asm volatile("mrs %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); 141 asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
142 val |= ICC_SRE_EL1_SRE; 142 val |= ICC_SRE_EL1_SRE;
143 asm volatile("msr " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val)); 143 asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
144 isb(); 144 isb();
145 145
146 /* 146 /*
@@ -150,7 +150,7 @@ static void gic_enable_sre(void)
150 * 150 *
151 * Kindly inform the luser. 151 * Kindly inform the luser.
152 */ 152 */
153 asm volatile("mrs %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); 153 asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
154 if (!(val & ICC_SRE_EL1_SRE)) 154 if (!(val & ICC_SRE_EL1_SRE))
155 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 155 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
156} 156}
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 30cb7556d43f..03a4ea37ba86 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -18,6 +18,8 @@
18#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H 18#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
19#define __LINUX_IRQCHIP_ARM_GIC_V3_H 19#define __LINUX_IRQCHIP_ARM_GIC_V3_H
20 20
21#include <asm/sysreg.h>
22
21/* 23/*
22 * Distributor registers. We assume we're running non-secure, with ARE 24 * Distributor registers. We assume we're running non-secure, with ARE
23 * being set. Secure-only and non-ARE registers are not described. 25 * being set. Secure-only and non-ARE registers are not described.
@@ -125,17 +127,17 @@
125#define ICH_VMCR_PMR_SHIFT 24 127#define ICH_VMCR_PMR_SHIFT 24
126#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) 128#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
127 129
128#define ICC_EOIR1_EL1 S3_0_C12_C12_1 130#define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
129#define ICC_IAR1_EL1 S3_0_C12_C12_0 131#define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
130#define ICC_SGI1R_EL1 S3_0_C12_C11_5 132#define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
131#define ICC_PMR_EL1 S3_0_C4_C6_0 133#define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
132#define ICC_CTLR_EL1 S3_0_C12_C12_4 134#define ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
133#define ICC_SRE_EL1 S3_0_C12_C12_5 135#define ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
134#define ICC_GRPEN1_EL1 S3_0_C12_C12_7 136#define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
135 137
136#define ICC_IAR1_EL1_SPURIOUS 0x3ff 138#define ICC_IAR1_EL1_SPURIOUS 0x3ff
137 139
138#define ICC_SRE_EL2 S3_4_C12_C9_5 140#define ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
139 141
140#define ICC_SRE_EL2_SRE (1 << 0) 142#define ICC_SRE_EL2_SRE (1 << 0)
141#define ICC_SRE_EL2_ENABLE (1 << 3) 143#define ICC_SRE_EL2_ENABLE (1 << 3)
@@ -143,16 +145,16 @@
143/* 145/*
144 * System register definitions 146 * System register definitions
145 */ 147 */
146#define ICH_VSEIR_EL2 S3_4_C12_C9_4 148#define ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
147#define ICH_HCR_EL2 S3_4_C12_C11_0 149#define ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
148#define ICH_VTR_EL2 S3_4_C12_C11_1 150#define ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
149#define ICH_MISR_EL2 S3_4_C12_C11_2 151#define ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
150#define ICH_EISR_EL2 S3_4_C12_C11_3 152#define ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
151#define ICH_ELSR_EL2 S3_4_C12_C11_5 153#define ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
152#define ICH_VMCR_EL2 S3_4_C12_C11_7 154#define ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
153 155
154#define __LR0_EL2(x) S3_4_C12_C12_ ## x 156#define __LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
155#define __LR8_EL2(x) S3_4_C12_C13_ ## x 157#define __LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
156 158
157#define ICH_LR0_EL2 __LR0_EL2(0) 159#define ICH_LR0_EL2 __LR0_EL2(0)
158#define ICH_LR1_EL2 __LR0_EL2(1) 160#define ICH_LR1_EL2 __LR0_EL2(1)
@@ -171,13 +173,13 @@
171#define ICH_LR14_EL2 __LR8_EL2(6) 173#define ICH_LR14_EL2 __LR8_EL2(6)
172#define ICH_LR15_EL2 __LR8_EL2(7) 174#define ICH_LR15_EL2 __LR8_EL2(7)
173 175
174#define __AP0Rx_EL2(x) S3_4_C12_C8_ ## x 176#define __AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
175#define ICH_AP0R0_EL2 __AP0Rx_EL2(0) 177#define ICH_AP0R0_EL2 __AP0Rx_EL2(0)
176#define ICH_AP0R1_EL2 __AP0Rx_EL2(1) 178#define ICH_AP0R1_EL2 __AP0Rx_EL2(1)
177#define ICH_AP0R2_EL2 __AP0Rx_EL2(2) 179#define ICH_AP0R2_EL2 __AP0Rx_EL2(2)
178#define ICH_AP0R3_EL2 __AP0Rx_EL2(3) 180#define ICH_AP0R3_EL2 __AP0Rx_EL2(3)
179 181
180#define __AP1Rx_EL2(x) S3_4_C12_C9_ ## x 182#define __AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
181#define ICH_AP1R0_EL2 __AP1Rx_EL2(0) 183#define ICH_AP1R0_EL2 __AP1Rx_EL2(0)
182#define ICH_AP1R1_EL2 __AP1Rx_EL2(1) 184#define ICH_AP1R1_EL2 __AP1Rx_EL2(1)
183#define ICH_AP1R2_EL2 __AP1Rx_EL2(2) 185#define ICH_AP1R2_EL2 __AP1Rx_EL2(2)
@@ -189,7 +191,7 @@
189 191
190static inline void gic_write_eoir(u64 irq) 192static inline void gic_write_eoir(u64 irq)
191{ 193{
192 asm volatile("msr " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq)); 194 asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq));
193 isb(); 195 isb();
194} 196}
195 197
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