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-rw-r--r--Documentation/devicetree/bindings/dma/ste-dma40.txt62
-rw-r--r--arch/arm/mach-ux500/board-mop500-audio.c56
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c40
-rw-r--r--arch/arm/mach-ux500/board-mop500.c63
-rw-r--r--arch/arm/mach-ux500/board-mop500.h1
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c52
-rw-r--r--arch/arm/mach-ux500/devices-db8500.c123
-rw-r--r--arch/arm/mach-ux500/ste-dma40-db8500.h193
-rw-r--r--arch/arm/mach-ux500/usb.c18
-rw-r--r--drivers/crypto/ux500/cryp/cryp.h7
-rw-r--r--drivers/crypto/ux500/cryp/cryp_core.c31
-rw-r--r--drivers/crypto/ux500/hash/hash_alg.h5
-rw-r--r--drivers/crypto/ux500/hash/hash_core.c24
-rw-r--r--drivers/dma/ste_dma40.c366
-rw-r--r--drivers/dma/ste_dma40_ll.c106
-rw-r--r--drivers/dma/ste_dma40_ll.h3
-rw-r--r--include/linux/platform_data/dma-ste-dma40.h20
17 files changed, 504 insertions, 666 deletions
diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
new file mode 100644
index 000000000000..2679a873522d
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -0,0 +1,62 @@
1* DMA40 DMA Controller
2
3Required properties:
4- compatible: "stericsson,dma40"
5- reg: Address range of the DMAC registers
6- reg-names: Names of the above areas to use during resource look-up
7- interrupt: Should contain the DMAC interrupt number
8- #dma-cells: must be <3>
9
10Optional properties:
11- dma-channels: Number of channels supported by hardware - if not present
12 the driver will attempt to obtain the information from H/W
13
14Example:
15
16 dma: dma-controller@801C0000 {
17 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
18 reg = <0x801C0000 0x1000 0x40010000 0x800>;
19 reg-names = "base", "lcpa";
20 interrupt-parent = <&intc>;
21 interrupts = <0 25 0x4>;
22
23 #dma-cells = <2>;
24 dma-channels = <8>;
25 };
26
27Clients
28Required properties:
29- dmas: Comma separated list of dma channel requests
30- dma-names: Names of the aforementioned requested channels
31
32Each dmas request consists of 4 cells:
33 1. A phandle pointing to the DMA controller
34 2. Device Type
35 3. The DMA request line number (only when 'use fixed channel' is set)
36 4. A 32bit mask specifying; mode, direction and endianess [NB: This list will grow]
37 0x00000001: Mode:
38 Logical channel when unset
39 Physical channel when set
40 0x00000002: Direction:
41 Memory to Device when unset
42 Device to Memory when set
43 0x00000004: Endianess:
44 Little endian when unset
45 Big endian when set
46 0x00000008: Use fixed channel:
47 Use automatic channel selection when unset
48 Use DMA request line number when set
49
50Example:
51
52 uart@80120000 {
53 compatible = "arm,pl011", "arm,primecell";
54 reg = <0x80120000 0x1000>;
55 interrupts = <0 11 0x4>;
56
57 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
58 <&dma 13 0 0x0>; /* Logical - MemToDev */
59 dma-names = "rx", "rx";
60
61 status = "disabled";
62 };
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index aba9e5692958..ec872622340f 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -22,27 +22,13 @@
22static struct stedma40_chan_cfg msp0_dma_rx = { 22static struct stedma40_chan_cfg msp0_dma_rx = {
23 .high_priority = true, 23 .high_priority = true,
24 .dir = STEDMA40_PERIPH_TO_MEM, 24 .dir = STEDMA40_PERIPH_TO_MEM,
25 25 .dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
26 .src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
27 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
28
29 .src_info.psize = STEDMA40_PSIZE_LOG_4,
30 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
31
32 /* data_width is set during configuration */
33}; 26};
34 27
35static struct stedma40_chan_cfg msp0_dma_tx = { 28static struct stedma40_chan_cfg msp0_dma_tx = {
36 .high_priority = true, 29 .high_priority = true,
37 .dir = STEDMA40_MEM_TO_PERIPH, 30 .dir = STEDMA40_MEM_TO_PERIPH,
38 31 .dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
39 .src_dev_type = STEDMA40_DEV_DST_MEMORY,
40 .dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
41
42 .src_info.psize = STEDMA40_PSIZE_LOG_4,
43 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
44
45 /* data_width is set during configuration */
46}; 32};
47 33
48struct msp_i2s_platform_data msp0_platform_data = { 34struct msp_i2s_platform_data msp0_platform_data = {
@@ -54,27 +40,13 @@ struct msp_i2s_platform_data msp0_platform_data = {
54static struct stedma40_chan_cfg msp1_dma_rx = { 40static struct stedma40_chan_cfg msp1_dma_rx = {
55 .high_priority = true, 41 .high_priority = true,
56 .dir = STEDMA40_PERIPH_TO_MEM, 42 .dir = STEDMA40_PERIPH_TO_MEM,
57 43 .dev_type = DB8500_DMA_DEV30_MSP3,
58 .src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
59 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
60
61 .src_info.psize = STEDMA40_PSIZE_LOG_4,
62 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
63
64 /* data_width is set during configuration */
65}; 44};
66 45
67static struct stedma40_chan_cfg msp1_dma_tx = { 46static struct stedma40_chan_cfg msp1_dma_tx = {
68 .high_priority = true, 47 .high_priority = true,
69 .dir = STEDMA40_MEM_TO_PERIPH, 48 .dir = STEDMA40_MEM_TO_PERIPH,
70 49 .dev_type = DB8500_DMA_DEV30_MSP1,
71 .src_dev_type = STEDMA40_DEV_DST_MEMORY,
72 .dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
73
74 .src_info.psize = STEDMA40_PSIZE_LOG_4,
75 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
76
77 /* data_width is set during configuration */
78}; 50};
79 51
80struct msp_i2s_platform_data msp1_platform_data = { 52struct msp_i2s_platform_data msp1_platform_data = {
@@ -86,31 +58,15 @@ struct msp_i2s_platform_data msp1_platform_data = {
86static struct stedma40_chan_cfg msp2_dma_rx = { 58static struct stedma40_chan_cfg msp2_dma_rx = {
87 .high_priority = true, 59 .high_priority = true,
88 .dir = STEDMA40_PERIPH_TO_MEM, 60 .dir = STEDMA40_PERIPH_TO_MEM,
89 61 .dev_type = DB8500_DMA_DEV14_MSP2,
90 .src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
91 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
92
93 /* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
94 .src_info.psize = STEDMA40_PSIZE_LOG_1,
95 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
96
97 /* data_width is set during configuration */
98}; 62};
99 63
100static struct stedma40_chan_cfg msp2_dma_tx = { 64static struct stedma40_chan_cfg msp2_dma_tx = {
101 .high_priority = true, 65 .high_priority = true,
102 .dir = STEDMA40_MEM_TO_PERIPH, 66 .dir = STEDMA40_MEM_TO_PERIPH,
103 67 .dev_type = DB8500_DMA_DEV14_MSP2,
104 .src_dev_type = STEDMA40_DEV_DST_MEMORY,
105 .dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
106
107 .src_info.psize = STEDMA40_PSIZE_LOG_4,
108 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
109
110 .use_fixed_channel = true, 68 .use_fixed_channel = true,
111 .phy_channel = 1, 69 .phy_channel = 1,
112
113 /* data_width is set during configuration */
114}; 70};
115 71
116static struct platform_device *db8500_add_msp_i2s(struct device *parent, 72static struct platform_device *db8500_add_msp_i2s(struct device *parent,
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 0ef38775a0c1..29be714b8a73 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -35,19 +35,13 @@
35struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = { 35struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
36 .mode = STEDMA40_MODE_LOGICAL, 36 .mode = STEDMA40_MODE_LOGICAL,
37 .dir = STEDMA40_PERIPH_TO_MEM, 37 .dir = STEDMA40_PERIPH_TO_MEM,
38 .src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX, 38 .dev_type = DB8500_DMA_DEV29_SD_MM0,
39 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
40 .src_info.data_width = STEDMA40_WORD_WIDTH,
41 .dst_info.data_width = STEDMA40_WORD_WIDTH,
42}; 39};
43 40
44static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = { 41static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
45 .mode = STEDMA40_MODE_LOGICAL, 42 .mode = STEDMA40_MODE_LOGICAL,
46 .dir = STEDMA40_MEM_TO_PERIPH, 43 .dir = STEDMA40_MEM_TO_PERIPH,
47 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 44 .dev_type = DB8500_DMA_DEV29_SD_MM0,
48 .dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,
49 .src_info.data_width = STEDMA40_WORD_WIDTH,
50 .dst_info.data_width = STEDMA40_WORD_WIDTH,
51}; 45};
52#endif 46#endif
53 47
@@ -88,19 +82,13 @@ void mop500_sdi_tc35892_init(struct device *parent)
88static struct stedma40_chan_cfg sdi1_dma_cfg_rx = { 82static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
89 .mode = STEDMA40_MODE_LOGICAL, 83 .mode = STEDMA40_MODE_LOGICAL,
90 .dir = STEDMA40_PERIPH_TO_MEM, 84 .dir = STEDMA40_PERIPH_TO_MEM,
91 .src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX, 85 .dev_type = DB8500_DMA_DEV32_SD_MM1,
92 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
93 .src_info.data_width = STEDMA40_WORD_WIDTH,
94 .dst_info.data_width = STEDMA40_WORD_WIDTH,
95}; 86};
96 87
97static struct stedma40_chan_cfg sdi1_dma_cfg_tx = { 88static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
98 .mode = STEDMA40_MODE_LOGICAL, 89 .mode = STEDMA40_MODE_LOGICAL,
99 .dir = STEDMA40_MEM_TO_PERIPH, 90 .dir = STEDMA40_MEM_TO_PERIPH,
100 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 91 .dev_type = DB8500_DMA_DEV32_SD_MM1,
101 .dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX,
102 .src_info.data_width = STEDMA40_WORD_WIDTH,
103 .dst_info.data_width = STEDMA40_WORD_WIDTH,
104}; 92};
105#endif 93#endif
106 94
@@ -125,19 +113,13 @@ struct mmci_platform_data mop500_sdi1_data = {
125struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = { 113struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
126 .mode = STEDMA40_MODE_LOGICAL, 114 .mode = STEDMA40_MODE_LOGICAL,
127 .dir = STEDMA40_PERIPH_TO_MEM, 115 .dir = STEDMA40_PERIPH_TO_MEM,
128 .src_dev_type = DB8500_DMA_DEV28_SD_MM2_RX, 116 .dev_type = DB8500_DMA_DEV28_SD_MM2,
129 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
130 .src_info.data_width = STEDMA40_WORD_WIDTH,
131 .dst_info.data_width = STEDMA40_WORD_WIDTH,
132}; 117};
133 118
134static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = { 119static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
135 .mode = STEDMA40_MODE_LOGICAL, 120 .mode = STEDMA40_MODE_LOGICAL,
136 .dir = STEDMA40_MEM_TO_PERIPH, 121 .dir = STEDMA40_MEM_TO_PERIPH,
137 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 122 .dev_type = DB8500_DMA_DEV28_SD_MM2,
138 .dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,
139 .src_info.data_width = STEDMA40_WORD_WIDTH,
140 .dst_info.data_width = STEDMA40_WORD_WIDTH,
141}; 123};
142#endif 124#endif
143 125
@@ -163,19 +145,13 @@ struct mmci_platform_data mop500_sdi2_data = {
163struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = { 145struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
164 .mode = STEDMA40_MODE_LOGICAL, 146 .mode = STEDMA40_MODE_LOGICAL,
165 .dir = STEDMA40_PERIPH_TO_MEM, 147 .dir = STEDMA40_PERIPH_TO_MEM,
166 .src_dev_type = DB8500_DMA_DEV42_SD_MM4_RX, 148 .dev_type = DB8500_DMA_DEV42_SD_MM4,
167 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
168 .src_info.data_width = STEDMA40_WORD_WIDTH,
169 .dst_info.data_width = STEDMA40_WORD_WIDTH,
170}; 149};
171 150
172static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = { 151static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
173 .mode = STEDMA40_MODE_LOGICAL, 152 .mode = STEDMA40_MODE_LOGICAL,
174 .dir = STEDMA40_MEM_TO_PERIPH, 153 .dir = STEDMA40_MEM_TO_PERIPH,
175 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 154 .dev_type = DB8500_DMA_DEV42_SD_MM4,
176 .dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,
177 .src_info.data_width = STEDMA40_WORD_WIDTH,
178 .dst_info.data_width = STEDMA40_WORD_WIDTH,
179}; 155};
180#endif 156#endif
181 157
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 78389de94dde..f59d52806afe 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -425,35 +425,20 @@ void mop500_snowball_ethernet_clock_enable(void)
425static struct cryp_platform_data u8500_cryp1_platform_data = { 425static struct cryp_platform_data u8500_cryp1_platform_data = {
426 .mem_to_engine = { 426 .mem_to_engine = {
427 .dir = STEDMA40_MEM_TO_PERIPH, 427 .dir = STEDMA40_MEM_TO_PERIPH,
428 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 428 .dev_type = DB8500_DMA_DEV48_CAC1,
429 .dst_dev_type = DB8500_DMA_DEV48_CAC1_TX,
430 .src_info.data_width = STEDMA40_WORD_WIDTH,
431 .dst_info.data_width = STEDMA40_WORD_WIDTH,
432 .mode = STEDMA40_MODE_LOGICAL, 429 .mode = STEDMA40_MODE_LOGICAL,
433 .src_info.psize = STEDMA40_PSIZE_LOG_4,
434 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
435 }, 430 },
436 .engine_to_mem = { 431 .engine_to_mem = {
437 .dir = STEDMA40_PERIPH_TO_MEM, 432 .dir = STEDMA40_PERIPH_TO_MEM,
438 .src_dev_type = DB8500_DMA_DEV48_CAC1_RX, 433 .dev_type = DB8500_DMA_DEV48_CAC1,
439 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
440 .src_info.data_width = STEDMA40_WORD_WIDTH,
441 .dst_info.data_width = STEDMA40_WORD_WIDTH,
442 .mode = STEDMA40_MODE_LOGICAL, 434 .mode = STEDMA40_MODE_LOGICAL,
443 .src_info.psize = STEDMA40_PSIZE_LOG_4,
444 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
445 } 435 }
446}; 436};
447 437
448static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = { 438static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
449 .dir = STEDMA40_MEM_TO_PERIPH, 439 .dir = STEDMA40_MEM_TO_PERIPH,
450 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 440 .dev_type = DB8500_DMA_DEV50_HAC1_TX,
451 .dst_dev_type = DB8500_DMA_DEV50_HAC1_TX,
452 .src_info.data_width = STEDMA40_WORD_WIDTH,
453 .dst_info.data_width = STEDMA40_WORD_WIDTH,
454 .mode = STEDMA40_MODE_LOGICAL, 441 .mode = STEDMA40_MODE_LOGICAL,
455 .src_info.psize = STEDMA40_PSIZE_LOG_16,
456 .dst_info.psize = STEDMA40_PSIZE_LOG_16,
457}; 442};
458 443
459static struct hash_platform_data u8500_hash1_platform_data = { 444static struct hash_platform_data u8500_hash1_platform_data = {
@@ -471,19 +456,13 @@ static struct platform_device *mop500_platform_devs[] __initdata = {
471static struct stedma40_chan_cfg ssp0_dma_cfg_rx = { 456static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
472 .mode = STEDMA40_MODE_LOGICAL, 457 .mode = STEDMA40_MODE_LOGICAL,
473 .dir = STEDMA40_PERIPH_TO_MEM, 458 .dir = STEDMA40_PERIPH_TO_MEM,
474 .src_dev_type = DB8500_DMA_DEV8_SSP0_RX, 459 .dev_type = DB8500_DMA_DEV8_SSP0,
475 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
476 .src_info.data_width = STEDMA40_BYTE_WIDTH,
477 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
478}; 460};
479 461
480static struct stedma40_chan_cfg ssp0_dma_cfg_tx = { 462static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
481 .mode = STEDMA40_MODE_LOGICAL, 463 .mode = STEDMA40_MODE_LOGICAL,
482 .dir = STEDMA40_MEM_TO_PERIPH, 464 .dir = STEDMA40_MEM_TO_PERIPH,
483 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 465 .dev_type = DB8500_DMA_DEV8_SSP0,
484 .dst_dev_type = DB8500_DMA_DEV8_SSP0_TX,
485 .src_info.data_width = STEDMA40_BYTE_WIDTH,
486 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
487}; 466};
488#endif 467#endif
489 468
@@ -512,55 +491,37 @@ static void __init mop500_spi_init(struct device *parent)
512static struct stedma40_chan_cfg uart0_dma_cfg_rx = { 491static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
513 .mode = STEDMA40_MODE_LOGICAL, 492 .mode = STEDMA40_MODE_LOGICAL,
514 .dir = STEDMA40_PERIPH_TO_MEM, 493 .dir = STEDMA40_PERIPH_TO_MEM,
515 .src_dev_type = DB8500_DMA_DEV13_UART0_RX, 494 .dev_type = DB8500_DMA_DEV13_UART0,
516 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
517 .src_info.data_width = STEDMA40_BYTE_WIDTH,
518 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
519}; 495};
520 496
521static struct stedma40_chan_cfg uart0_dma_cfg_tx = { 497static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
522 .mode = STEDMA40_MODE_LOGICAL, 498 .mode = STEDMA40_MODE_LOGICAL,
523 .dir = STEDMA40_MEM_TO_PERIPH, 499 .dir = STEDMA40_MEM_TO_PERIPH,
524 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 500 .dev_type = DB8500_DMA_DEV13_UART0,
525 .dst_dev_type = DB8500_DMA_DEV13_UART0_TX,
526 .src_info.data_width = STEDMA40_BYTE_WIDTH,
527 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
528}; 501};
529 502
530static struct stedma40_chan_cfg uart1_dma_cfg_rx = { 503static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
531 .mode = STEDMA40_MODE_LOGICAL, 504 .mode = STEDMA40_MODE_LOGICAL,
532 .dir = STEDMA40_PERIPH_TO_MEM, 505 .dir = STEDMA40_PERIPH_TO_MEM,
533 .src_dev_type = DB8500_DMA_DEV12_UART1_RX, 506 .dev_type = DB8500_DMA_DEV12_UART1,
534 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
535 .src_info.data_width = STEDMA40_BYTE_WIDTH,
536 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
537}; 507};
538 508
539static struct stedma40_chan_cfg uart1_dma_cfg_tx = { 509static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
540 .mode = STEDMA40_MODE_LOGICAL, 510 .mode = STEDMA40_MODE_LOGICAL,
541 .dir = STEDMA40_MEM_TO_PERIPH, 511 .dir = STEDMA40_MEM_TO_PERIPH,
542 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 512 .dev_type = DB8500_DMA_DEV12_UART1,
543 .dst_dev_type = DB8500_DMA_DEV12_UART1_TX,
544 .src_info.data_width = STEDMA40_BYTE_WIDTH,
545 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
546}; 513};
547 514
548static struct stedma40_chan_cfg uart2_dma_cfg_rx = { 515static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
549 .mode = STEDMA40_MODE_LOGICAL, 516 .mode = STEDMA40_MODE_LOGICAL,
550 .dir = STEDMA40_PERIPH_TO_MEM, 517 .dir = STEDMA40_PERIPH_TO_MEM,
551 .src_dev_type = DB8500_DMA_DEV11_UART2_RX, 518 .dev_type = DB8500_DMA_DEV11_UART2,
552 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
553 .src_info.data_width = STEDMA40_BYTE_WIDTH,
554 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
555}; 519};
556 520
557static struct stedma40_chan_cfg uart2_dma_cfg_tx = { 521static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
558 .mode = STEDMA40_MODE_LOGICAL, 522 .mode = STEDMA40_MODE_LOGICAL,
559 .dir = STEDMA40_MEM_TO_PERIPH, 523 .dir = STEDMA40_MEM_TO_PERIPH,
560 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 524 .dev_type = DB8500_DMA_DEV11_UART2,
561 .dst_dev_type = DB8500_DMA_DEV11_UART2_TX,
562 .src_info.data_width = STEDMA40_BYTE_WIDTH,
563 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
564}; 525};
565#endif 526#endif
566 527
@@ -676,6 +637,8 @@ static void __init snowball_init_machine(void)
676 637
677 mop500_snowball_ethernet_clock_enable(); 638 mop500_snowball_ethernet_clock_enable();
678 639
640 u8500_cryp1_hash1_init(parent);
641
679 /* This board has full regulator constraints */ 642 /* This board has full regulator constraints */
680 regulator_has_full_constraints(); 643 regulator_has_full_constraints();
681} 644}
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 49514b825034..6f0bfcb08907 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -93,6 +93,7 @@ extern struct amba_pl011_data uart0_plat;
93extern struct amba_pl011_data uart1_plat; 93extern struct amba_pl011_data uart1_plat;
94extern struct amba_pl011_data uart2_plat; 94extern struct amba_pl011_data uart2_plat;
95extern struct pl022_ssp_controller ssp0_plat; 95extern struct pl022_ssp_controller ssp0_plat;
96extern struct stedma40_platform_data dma40_plat_data;
96 97
97extern void mop500_sdi_init(struct device *parent); 98extern void mop500_sdi_init(struct device *parent);
98extern void snowball_sdi_init(struct device *parent); 99extern void snowball_sdi_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 46cca52890bc..243b91b66ae0 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -162,26 +162,15 @@ static void __init db8500_add_gpios(struct device *parent)
162 dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE); 162 dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
163} 163}
164 164
165static int usb_db8500_rx_dma_cfg[] = { 165static int usb_db8500_dma_cfg[] = {
166 DB8500_DMA_DEV38_USB_OTG_IEP_1_9, 166 DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9,
167 DB8500_DMA_DEV37_USB_OTG_IEP_2_10, 167 DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10,
168 DB8500_DMA_DEV36_USB_OTG_IEP_3_11, 168 DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11,
169 DB8500_DMA_DEV19_USB_OTG_IEP_4_12, 169 DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12,
170 DB8500_DMA_DEV18_USB_OTG_IEP_5_13, 170 DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13,
171 DB8500_DMA_DEV17_USB_OTG_IEP_6_14, 171 DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14,
172 DB8500_DMA_DEV16_USB_OTG_IEP_7_15, 172 DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15,
173 DB8500_DMA_DEV39_USB_OTG_IEP_8 173 DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8
174};
175
176static int usb_db8500_tx_dma_cfg[] = {
177 DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
178 DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
179 DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
180 DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
181 DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
182 DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
183 DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
184 DB8500_DMA_DEV39_USB_OTG_OEP_8
185}; 174};
186 175
187static const char *db8500_read_soc_id(void) 176static const char *db8500_read_soc_id(void)
@@ -215,7 +204,7 @@ struct device * __init u8500_init_devices(void)
215 204
216 db8500_add_rtc(parent); 205 db8500_add_rtc(parent);
217 db8500_add_gpios(parent); 206 db8500_add_gpios(parent);
218 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 207 db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg);
219 208
220 for (i = 0; i < ARRAY_SIZE(platform_devs); i++) 209 for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
221 platform_devs[i]->dev.parent = parent; 210 platform_devs[i]->dev.parent = parent;
@@ -232,17 +221,7 @@ static struct device * __init u8500_of_init_devices(void)
232{ 221{
233 struct device *parent = db8500_soc_device_init(); 222 struct device *parent = db8500_soc_device_init();
234 223
235 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 224 db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg);
236
237 u8500_dma40_device.dev.parent = parent;
238
239 /*
240 * Devices to be DT:ed:
241 * u8500_dma40_device = todo
242 * db8500_pmu_device = done
243 * db8500_prcmu_device = done
244 */
245 platform_device_register(&u8500_dma40_device);
246 225
247 return parent; 226 return parent;
248} 227}
@@ -251,9 +230,9 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
251 /* Requires call-back bindings. */ 230 /* Requires call-back bindings. */
252 OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), 231 OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
253 /* Requires DMA bindings. */ 232 /* Requires DMA bindings. */
254 OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), 233 OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
255 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat), 234 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
256 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), 235 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
257 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), 236 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
258 OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), 237 OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data),
259 OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data), 238 OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data),
@@ -289,6 +268,9 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
289 "ux500-msp-i2s.2", &msp2_platform_data), 268 "ux500-msp-i2s.2", &msp2_platform_data),
290 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000, 269 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
291 "ux500-msp-i2s.3", &msp3_platform_data), 270 "ux500-msp-i2s.3", &msp3_platform_data),
271 /* Requires clock name bindings and channel address lookup table. */
272 OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000,
273 "dma40.0", &dma40_plat_data),
292 {}, 274 {},
293}; 275};
294 276
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 1cf94ce0feec..e21ffd8c1412 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -42,128 +42,7 @@ static struct resource dma40_resources[] = {
42 } 42 }
43}; 43};
44 44
45/* Default configuration for physcial memcpy */ 45struct stedma40_platform_data dma40_plat_data = {
46struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
47 .mode = STEDMA40_MODE_PHYSICAL,
48 .dir = STEDMA40_MEM_TO_MEM,
49
50 .src_info.data_width = STEDMA40_BYTE_WIDTH,
51 .src_info.psize = STEDMA40_PSIZE_PHY_1,
52 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
53
54 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
55 .dst_info.psize = STEDMA40_PSIZE_PHY_1,
56 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
57};
58/* Default configuration for logical memcpy */
59struct stedma40_chan_cfg dma40_memcpy_conf_log = {
60 .dir = STEDMA40_MEM_TO_MEM,
61
62 .src_info.data_width = STEDMA40_BYTE_WIDTH,
63 .src_info.psize = STEDMA40_PSIZE_LOG_1,
64 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
65
66 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
67 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
68 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
69};
70
71/*
72 * Mapping between destination event lines and physical device address.
73 * The event line is tied to a device and therefore the address is constant.
74 * When the address comes from a primecell it will be configured in runtime
75 * and we set the address to -1 as a placeholder.
76 */
77static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
78 /* MUSB - these will be runtime-reconfigured */
79 [DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,
80 [DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,
81 [DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,
82 [DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,
83 [DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,
84 [DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,
85 [DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,
86 [DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,
87 /* PrimeCells - run-time configured */
88 [DB8500_DMA_DEV0_SPI0_TX] = -1,
89 [DB8500_DMA_DEV1_SD_MMC0_TX] = -1,
90 [DB8500_DMA_DEV2_SD_MMC1_TX] = -1,
91 [DB8500_DMA_DEV3_SD_MMC2_TX] = -1,
92 [DB8500_DMA_DEV8_SSP0_TX] = -1,
93 [DB8500_DMA_DEV9_SSP1_TX] = -1,
94 [DB8500_DMA_DEV11_UART2_TX] = -1,
95 [DB8500_DMA_DEV12_UART1_TX] = -1,
96 [DB8500_DMA_DEV13_UART0_TX] = -1,
97 [DB8500_DMA_DEV28_SD_MM2_TX] = -1,
98 [DB8500_DMA_DEV29_SD_MM0_TX] = -1,
99 [DB8500_DMA_DEV32_SD_MM1_TX] = -1,
100 [DB8500_DMA_DEV33_SPI2_TX] = -1,
101 [DB8500_DMA_DEV35_SPI1_TX] = -1,
102 [DB8500_DMA_DEV40_SPI3_TX] = -1,
103 [DB8500_DMA_DEV41_SD_MM3_TX] = -1,
104 [DB8500_DMA_DEV42_SD_MM4_TX] = -1,
105 [DB8500_DMA_DEV43_SD_MM5_TX] = -1,
106 [DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
107 [DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
108 [DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
109 [DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
110 [DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
111};
112
113/* Mapping between source event lines and physical device address */
114static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
115 /* MUSB - these will be runtime-reconfigured */
116 [DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,
117 [DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,
118 [DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,
119 [DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,
120 [DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,
121 [DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,
122 [DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,
123 [DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,
124 /* PrimeCells */
125 [DB8500_DMA_DEV0_SPI0_RX] = -1,
126 [DB8500_DMA_DEV1_SD_MMC0_RX] = -1,
127 [DB8500_DMA_DEV2_SD_MMC1_RX] = -1,
128 [DB8500_DMA_DEV3_SD_MMC2_RX] = -1,
129 [DB8500_DMA_DEV8_SSP0_RX] = -1,
130 [DB8500_DMA_DEV9_SSP1_RX] = -1,
131 [DB8500_DMA_DEV11_UART2_RX] = -1,
132 [DB8500_DMA_DEV12_UART1_RX] = -1,
133 [DB8500_DMA_DEV13_UART0_RX] = -1,
134 [DB8500_DMA_DEV28_SD_MM2_RX] = -1,
135 [DB8500_DMA_DEV29_SD_MM0_RX] = -1,
136 [DB8500_DMA_DEV32_SD_MM1_RX] = -1,
137 [DB8500_DMA_DEV33_SPI2_RX] = -1,
138 [DB8500_DMA_DEV35_SPI1_RX] = -1,
139 [DB8500_DMA_DEV40_SPI3_RX] = -1,
140 [DB8500_DMA_DEV41_SD_MM3_RX] = -1,
141 [DB8500_DMA_DEV42_SD_MM4_RX] = -1,
142 [DB8500_DMA_DEV43_SD_MM5_RX] = -1,
143 [DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
144 [DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
145 [DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
146 [DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
147};
148
149/* Reserved event lines for memcpy only */
150static int dma40_memcpy_event[] = {
151 DB8500_DMA_MEMCPY_TX_0,
152 DB8500_DMA_MEMCPY_TX_1,
153 DB8500_DMA_MEMCPY_TX_2,
154 DB8500_DMA_MEMCPY_TX_3,
155 DB8500_DMA_MEMCPY_TX_4,
156 DB8500_DMA_MEMCPY_TX_5,
157};
158
159static struct stedma40_platform_data dma40_plat_data = {
160 .dev_len = DB8500_DMA_NR_DEV,
161 .dev_rx = dma40_rx_map,
162 .dev_tx = dma40_tx_map,
163 .memcpy = dma40_memcpy_event,
164 .memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
165 .memcpy_conf_phy = &dma40_memcpy_conf_phy,
166 .memcpy_conf_log = &dma40_memcpy_conf_log,
167 .disabled_channels = {-1}, 46 .disabled_channels = {-1},
168}; 47};
169 48
diff --git a/arch/arm/mach-ux500/ste-dma40-db8500.h b/arch/arm/mach-ux500/ste-dma40-db8500.h
index a616419bea76..0296ae5b0fd9 100644
--- a/arch/arm/mach-ux500/ste-dma40-db8500.h
+++ b/arch/arm/mach-ux500/ste-dma40-db8500.h
@@ -12,133 +12,74 @@
12 12
13#define DB8500_DMA_NR_DEV 64 13#define DB8500_DMA_NR_DEV 64
14 14
15enum dma_src_dev_type { 15/*
16 DB8500_DMA_DEV0_SPI0_RX = 0, 16 * Unless otherwise specified, all channels numbers are used for
17 DB8500_DMA_DEV1_SD_MMC0_RX = 1, 17 * TX & RX, and can be used for either source or destination
18 DB8500_DMA_DEV2_SD_MMC1_RX = 2, 18 * channels.
19 DB8500_DMA_DEV3_SD_MMC2_RX = 3, 19 */
20 DB8500_DMA_DEV4_I2C1_RX = 4, 20enum dma_dev_type {
21 DB8500_DMA_DEV5_I2C3_RX = 5, 21 DB8500_DMA_DEV0_SPI0 = 0,
22 DB8500_DMA_DEV6_I2C2_RX = 6, 22 DB8500_DMA_DEV1_SD_MMC0 = 1,
23 DB8500_DMA_DEV7_I2C4_RX = 7, /* Only on V1 and later */ 23 DB8500_DMA_DEV2_SD_MMC1 = 2,
24 DB8500_DMA_DEV8_SSP0_RX = 8, 24 DB8500_DMA_DEV3_SD_MMC2 = 3,
25 DB8500_DMA_DEV9_SSP1_RX = 9, 25 DB8500_DMA_DEV4_I2C1 = 4,
26 DB8500_DMA_DEV10_MCDE_RX = 10, 26 DB8500_DMA_DEV5_I2C3 = 5,
27 DB8500_DMA_DEV11_UART2_RX = 11, 27 DB8500_DMA_DEV6_I2C2 = 6,
28 DB8500_DMA_DEV12_UART1_RX = 12, 28 DB8500_DMA_DEV7_I2C4 = 7, /* Only on V1 and later */
29 DB8500_DMA_DEV13_UART0_RX = 13, 29 DB8500_DMA_DEV8_SSP0 = 8,
30 DB8500_DMA_DEV14_MSP2_RX = 14, 30 DB8500_DMA_DEV9_SSP1 = 9,
31 DB8500_DMA_DEV15_I2C0_RX = 15, 31 DB8500_DMA_DEV10_MCDE_RX = 10, /* RX only */
32 DB8500_DMA_DEV16_USB_OTG_IEP_7_15 = 16, 32 DB8500_DMA_DEV11_UART2 = 11,
33 DB8500_DMA_DEV17_USB_OTG_IEP_6_14 = 17, 33 DB8500_DMA_DEV12_UART1 = 12,
34 DB8500_DMA_DEV18_USB_OTG_IEP_5_13 = 18, 34 DB8500_DMA_DEV13_UART0 = 13,
35 DB8500_DMA_DEV19_USB_OTG_IEP_4_12 = 19, 35 DB8500_DMA_DEV14_MSP2 = 14,
36 DB8500_DMA_DEV20_SLIM0_CH0_RX_HSI_RX_CH0 = 20, 36 DB8500_DMA_DEV15_I2C0 = 15,
37 DB8500_DMA_DEV21_SLIM0_CH1_RX_HSI_RX_CH1 = 21, 37 DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15 = 16,
38 DB8500_DMA_DEV22_SLIM0_CH2_RX_HSI_RX_CH2 = 22, 38 DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14 = 17,
39 DB8500_DMA_DEV23_SLIM0_CH3_RX_HSI_RX_CH3 = 23, 39 DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13 = 18,
40 DB8500_DMA_DEV24_SRC_SXA0_RX_TX = 24, 40 DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12 = 19,
41 DB8500_DMA_DEV25_SRC_SXA1_RX_TX = 25, 41 DB8500_DMA_DEV20_SLIM0_CH0_HSI_CH0 = 20,
42 DB8500_DMA_DEV26_SRC_SXA2_RX_TX = 26, 42 DB8500_DMA_DEV21_SLIM0_CH1_HSI_CH1 = 21,
43 DB8500_DMA_DEV27_SRC_SXA3_RX_TX = 27, 43 DB8500_DMA_DEV22_SLIM0_CH2_HSI_CH2 = 22,
44 DB8500_DMA_DEV28_SD_MM2_RX = 28, 44 DB8500_DMA_DEV23_SLIM0_CH3_HSI_CH3 = 23,
45 DB8500_DMA_DEV29_SD_MM0_RX = 29, 45 DB8500_DMA_DEV24_SXA0 = 24,
46 DB8500_DMA_DEV30_MSP1_RX = 30, 46 DB8500_DMA_DEV25_SXA1 = 25,
47 DB8500_DMA_DEV26_SXA2 = 26,
48 DB8500_DMA_DEV27_SXA3 = 27,
49 DB8500_DMA_DEV28_SD_MM2 = 28,
50 DB8500_DMA_DEV29_SD_MM0 = 29,
51 DB8500_DMA_DEV30_MSP1 = 30,
47 /* On DB8500v2, MSP3 RX replaces MSP1 RX */ 52 /* On DB8500v2, MSP3 RX replaces MSP1 RX */
48 DB8500_DMA_DEV30_MSP3_RX = 30, 53 DB8500_DMA_DEV30_MSP3 = 30,
49 DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX = 31, 54 DB8500_DMA_DEV31_MSP0_SLIM0_CH0 = 31,
50 DB8500_DMA_DEV32_SD_MM1_RX = 32, 55 DB8500_DMA_DEV32_SD_MM1 = 32,
51 DB8500_DMA_DEV33_SPI2_RX = 33, 56 DB8500_DMA_DEV33_SPI2 = 33,
52 DB8500_DMA_DEV34_I2C3_RX2 = 34, 57 DB8500_DMA_DEV34_I2C3_RX2_TX2 = 34,
53 DB8500_DMA_DEV35_SPI1_RX = 35, 58 DB8500_DMA_DEV35_SPI1 = 35,
54 DB8500_DMA_DEV36_USB_OTG_IEP_3_11 = 36, 59 DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11 = 36,
55 DB8500_DMA_DEV37_USB_OTG_IEP_2_10 = 37, 60 DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10 = 37,
56 DB8500_DMA_DEV38_USB_OTG_IEP_1_9 = 38, 61 DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9 = 38,
57 DB8500_DMA_DEV39_USB_OTG_IEP_8 = 39, 62 DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8 = 39,
58 DB8500_DMA_DEV40_SPI3_RX = 40, 63 DB8500_DMA_DEV40_SPI3 = 40,
59 DB8500_DMA_DEV41_SD_MM3_RX = 41, 64 DB8500_DMA_DEV41_SD_MM3 = 41,
60 DB8500_DMA_DEV42_SD_MM4_RX = 42, 65 DB8500_DMA_DEV42_SD_MM4 = 42,
61 DB8500_DMA_DEV43_SD_MM5_RX = 43, 66 DB8500_DMA_DEV43_SD_MM5 = 43,
62 DB8500_DMA_DEV44_SRC_SXA4_RX_TX = 44, 67 DB8500_DMA_DEV44_SXA4 = 44,
63 DB8500_DMA_DEV45_SRC_SXA5_RX_TX = 45, 68 DB8500_DMA_DEV45_SXA5 = 45,
64 DB8500_DMA_DEV46_SLIM0_CH8_RX_SRC_SXA6_RX_TX = 46, 69 DB8500_DMA_DEV46_SLIM0_CH8_SRC_SXA6 = 46,
65 DB8500_DMA_DEV47_SLIM0_CH9_RX_SRC_SXA7_RX_TX = 47, 70 DB8500_DMA_DEV47_SLIM0_CH9_SRC_SXA7 = 47,
66 DB8500_DMA_DEV48_CAC1_RX = 48, 71 DB8500_DMA_DEV48_CAC1 = 48,
67 /* 49, 50 and 51 are not used */ 72 DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49, /* TX only */
68 DB8500_DMA_DEV52_SLIM0_CH4_RX_HSI_RX_CH4 = 52, 73 DB8500_DMA_DEV50_HAC1_TX = 50, /* TX only */
69 DB8500_DMA_DEV53_SLIM0_CH5_RX_HSI_RX_CH5 = 53, 74 DB8500_DMA_MEMCPY_TX_0 = 51, /* TX only */
70 DB8500_DMA_DEV54_SLIM0_CH6_RX_HSI_RX_CH6 = 54, 75 DB8500_DMA_DEV52_SLIM0_CH4_HSI_CH4 = 52,
71 DB8500_DMA_DEV55_SLIM0_CH7_RX_HSI_RX_CH7 = 55, 76 DB8500_DMA_DEV53_SLIM0_CH5_HSI_CH5 = 53,
72 /* 56, 57, 58, 59 and 60 are not used */ 77 DB8500_DMA_DEV54_SLIM0_CH6_HSI_CH6 = 54,
73 DB8500_DMA_DEV61_CAC0_RX = 61, 78 DB8500_DMA_DEV55_SLIM0_CH7_HSI_CH7 = 55,
74 /* 62 and 63 are not used */ 79 /* 56 -> 60 are channels reserved for memcpy only */
75}; 80 DB8500_DMA_DEV61_CAC0 = 61,
76 81 DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62, /* TX only */
77enum dma_dest_dev_type { 82 DB8500_DMA_DEV63_HAC0_TX = 63, /* TX only */
78 DB8500_DMA_DEV0_SPI0_TX = 0,
79 DB8500_DMA_DEV1_SD_MMC0_TX = 1,
80 DB8500_DMA_DEV2_SD_MMC1_TX = 2,
81 DB8500_DMA_DEV3_SD_MMC2_TX = 3,
82 DB8500_DMA_DEV4_I2C1_TX = 4,
83 DB8500_DMA_DEV5_I2C3_TX = 5,
84 DB8500_DMA_DEV6_I2C2_TX = 6,
85 DB8500_DMA_DEV7_I2C4_TX = 7, /* Only on V1 and later */
86 DB8500_DMA_DEV8_SSP0_TX = 8,
87 DB8500_DMA_DEV9_SSP1_TX = 9,
88 /* 10 is not used*/
89 DB8500_DMA_DEV11_UART2_TX = 11,
90 DB8500_DMA_DEV12_UART1_TX = 12,
91 DB8500_DMA_DEV13_UART0_TX = 13,
92 DB8500_DMA_DEV14_MSP2_TX = 14,
93 DB8500_DMA_DEV15_I2C0_TX = 15,
94 DB8500_DMA_DEV16_USB_OTG_OEP_7_15 = 16,
95 DB8500_DMA_DEV17_USB_OTG_OEP_6_14 = 17,
96 DB8500_DMA_DEV18_USB_OTG_OEP_5_13 = 18,
97 DB8500_DMA_DEV19_USB_OTG_OEP_4_12 = 19,
98 DB8500_DMA_DEV20_SLIM0_CH0_TX_HSI_TX_CH0 = 20,
99 DB8500_DMA_DEV21_SLIM0_CH1_TX_HSI_TX_CH1 = 21,
100 DB8500_DMA_DEV22_SLIM0_CH2_TX_HSI_TX_CH2 = 22,
101 DB8500_DMA_DEV23_SLIM0_CH3_TX_HSI_TX_CH3 = 23,
102 DB8500_DMA_DEV24_DST_SXA0_RX_TX = 24,
103 DB8500_DMA_DEV25_DST_SXA1_RX_TX = 25,
104 DB8500_DMA_DEV26_DST_SXA2_RX_TX = 26,
105 DB8500_DMA_DEV27_DST_SXA3_RX_TX = 27,
106 DB8500_DMA_DEV28_SD_MM2_TX = 28,
107 DB8500_DMA_DEV29_SD_MM0_TX = 29,
108 DB8500_DMA_DEV30_MSP1_TX = 30,
109 DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX = 31,
110 DB8500_DMA_DEV32_SD_MM1_TX = 32,
111 DB8500_DMA_DEV33_SPI2_TX = 33,
112 DB8500_DMA_DEV34_I2C3_TX2 = 34,
113 DB8500_DMA_DEV35_SPI1_TX = 35,
114 DB8500_DMA_DEV36_USB_OTG_OEP_3_11 = 36,
115 DB8500_DMA_DEV37_USB_OTG_OEP_2_10 = 37,
116 DB8500_DMA_DEV38_USB_OTG_OEP_1_9 = 38,
117 DB8500_DMA_DEV39_USB_OTG_OEP_8 = 39,
118 DB8500_DMA_DEV40_SPI3_TX = 40,
119 DB8500_DMA_DEV41_SD_MM3_TX = 41,
120 DB8500_DMA_DEV42_SD_MM4_TX = 42,
121 DB8500_DMA_DEV43_SD_MM5_TX = 43,
122 DB8500_DMA_DEV44_DST_SXA4_RX_TX = 44,
123 DB8500_DMA_DEV45_DST_SXA5_RX_TX = 45,
124 DB8500_DMA_DEV46_SLIM0_CH8_TX_DST_SXA6_RX_TX = 46,
125 DB8500_DMA_DEV47_SLIM0_CH9_TX_DST_SXA7_RX_TX = 47,
126 DB8500_DMA_DEV48_CAC1_TX = 48,
127 DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49,
128 DB8500_DMA_DEV50_HAC1_TX = 50,
129 DB8500_DMA_MEMCPY_TX_0 = 51,
130 DB8500_DMA_DEV52_SLIM1_CH4_TX_HSI_TX_CH4 = 52,
131 DB8500_DMA_DEV53_SLIM1_CH5_TX_HSI_TX_CH5 = 53,
132 DB8500_DMA_DEV54_SLIM1_CH6_TX_HSI_TX_CH6 = 54,
133 DB8500_DMA_DEV55_SLIM1_CH7_TX_HSI_TX_CH7 = 55,
134 DB8500_DMA_MEMCPY_TX_1 = 56,
135 DB8500_DMA_MEMCPY_TX_2 = 57,
136 DB8500_DMA_MEMCPY_TX_3 = 58,
137 DB8500_DMA_MEMCPY_TX_4 = 59,
138 DB8500_DMA_MEMCPY_TX_5 = 60,
139 DB8500_DMA_DEV61_CAC0_TX = 61,
140 DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62,
141 DB8500_DMA_DEV63_HAC0_TX = 63,
142}; 83};
143 84
144#endif 85#endif
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 2dfc72f7cd8a..72754e369417 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -15,21 +15,11 @@
15#define MUSB_DMA40_RX_CH { \ 15#define MUSB_DMA40_RX_CH { \
16 .mode = STEDMA40_MODE_LOGICAL, \ 16 .mode = STEDMA40_MODE_LOGICAL, \
17 .dir = STEDMA40_PERIPH_TO_MEM, \ 17 .dir = STEDMA40_PERIPH_TO_MEM, \
18 .dst_dev_type = STEDMA40_DEV_DST_MEMORY, \
19 .src_info.data_width = STEDMA40_WORD_WIDTH, \
20 .dst_info.data_width = STEDMA40_WORD_WIDTH, \
21 .src_info.psize = STEDMA40_PSIZE_LOG_16, \
22 .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
23 } 18 }
24 19
25#define MUSB_DMA40_TX_CH { \ 20#define MUSB_DMA40_TX_CH { \
26 .mode = STEDMA40_MODE_LOGICAL, \ 21 .mode = STEDMA40_MODE_LOGICAL, \
27 .dir = STEDMA40_MEM_TO_PERIPH, \ 22 .dir = STEDMA40_MEM_TO_PERIPH, \
28 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, \
29 .src_info.data_width = STEDMA40_WORD_WIDTH, \
30 .dst_info.data_width = STEDMA40_WORD_WIDTH, \
31 .src_info.psize = STEDMA40_PSIZE_LOG_16, \
32 .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
33 } 23 }
34 24
35static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS] 25static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
@@ -125,20 +115,20 @@ struct platform_device ux500_musb_device = {
125 .resource = usb_resources, 115 .resource = usb_resources,
126}; 116};
127 117
128static inline void ux500_usb_dma_update_rx_ch_config(int *src_dev_type) 118static inline void ux500_usb_dma_update_rx_ch_config(int *dev_type)
129{ 119{
130 u32 idx; 120 u32 idx;
131 121
132 for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_CHANNELS; idx++) 122 for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_CHANNELS; idx++)
133 musb_dma_rx_ch[idx].src_dev_type = src_dev_type[idx]; 123 musb_dma_rx_ch[idx].dev_type = dev_type[idx];
134} 124}
135 125
136static inline void ux500_usb_dma_update_tx_ch_config(int *dst_dev_type) 126static inline void ux500_usb_dma_update_tx_ch_config(int *dev_type)
137{ 127{
138 u32 idx; 128 u32 idx;
139 129
140 for (idx = 0; idx < UX500_MUSB_DMA_NUM_TX_CHANNELS; idx++) 130 for (idx = 0; idx < UX500_MUSB_DMA_NUM_TX_CHANNELS; idx++)
141 musb_dma_tx_ch[idx].dst_dev_type = dst_dev_type[idx]; 131 musb_dma_tx_ch[idx].dev_type = dev_type[idx];
142} 132}
143 133
144void ux500_add_usb(struct device *parent, resource_size_t base, int irq, 134void ux500_add_usb(struct device *parent, resource_size_t base, int irq,
diff --git a/drivers/crypto/ux500/cryp/cryp.h b/drivers/crypto/ux500/cryp/cryp.h
index 14cfd05b777a..d1d6606fe56c 100644
--- a/drivers/crypto/ux500/cryp/cryp.h
+++ b/drivers/crypto/ux500/cryp/cryp.h
@@ -114,6 +114,9 @@ enum cryp_status_id {
114}; 114};
115 115
116/* Cryp DMA interface */ 116/* Cryp DMA interface */
117#define CRYP_DMA_TX_FIFO 0x08
118#define CRYP_DMA_RX_FIFO 0x10
119
117enum cryp_dma_req_type { 120enum cryp_dma_req_type {
118 CRYP_DMA_DISABLE_BOTH, 121 CRYP_DMA_DISABLE_BOTH,
119 CRYP_DMA_ENABLE_IN_DATA, 122 CRYP_DMA_ENABLE_IN_DATA,
@@ -217,7 +220,8 @@ struct cryp_dma {
217 220
218/** 221/**
219 * struct cryp_device_data - structure for a cryp device. 222 * struct cryp_device_data - structure for a cryp device.
220 * @base: Pointer to the hardware base address. 223 * @base: Pointer to virtual base address of the cryp device.
224 * @phybase: Pointer to physical memory location of the cryp device.
221 * @dev: Pointer to the devices dev structure. 225 * @dev: Pointer to the devices dev structure.
222 * @clk: Pointer to the device's clock control. 226 * @clk: Pointer to the device's clock control.
223 * @pwr_regulator: Pointer to the device's power control. 227 * @pwr_regulator: Pointer to the device's power control.
@@ -232,6 +236,7 @@ struct cryp_dma {
232 */ 236 */
233struct cryp_device_data { 237struct cryp_device_data {
234 struct cryp_register __iomem *base; 238 struct cryp_register __iomem *base;
239 phys_addr_t phybase;
235 struct device *dev; 240 struct device *dev;
236 struct clk *clk; 241 struct clk *clk;
237 struct regulator *pwr_regulator; 242 struct regulator *pwr_regulator;
diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index 32f480622b97..4f8b11af29a6 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -475,6 +475,19 @@ static int cryp_get_device_data(struct cryp_ctx *ctx,
475static void cryp_dma_setup_channel(struct cryp_device_data *device_data, 475static void cryp_dma_setup_channel(struct cryp_device_data *device_data,
476 struct device *dev) 476 struct device *dev)
477{ 477{
478 struct dma_slave_config mem2cryp = {
479 .direction = DMA_MEM_TO_DEV,
480 .dst_addr = device_data->phybase + CRYP_DMA_TX_FIFO,
481 .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
482 .dst_maxburst = 4,
483 };
484 struct dma_slave_config cryp2mem = {
485 .direction = DMA_DEV_TO_MEM,
486 .src_addr = device_data->phybase + CRYP_DMA_RX_FIFO,
487 .src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
488 .src_maxburst = 4,
489 };
490
478 dma_cap_zero(device_data->dma.mask); 491 dma_cap_zero(device_data->dma.mask);
479 dma_cap_set(DMA_SLAVE, device_data->dma.mask); 492 dma_cap_set(DMA_SLAVE, device_data->dma.mask);
480 493
@@ -490,6 +503,9 @@ static void cryp_dma_setup_channel(struct cryp_device_data *device_data,
490 stedma40_filter, 503 stedma40_filter,
491 device_data->dma.cfg_cryp2mem); 504 device_data->dma.cfg_cryp2mem);
492 505
506 dmaengine_slave_config(device_data->dma.chan_mem2cryp, &mem2cryp);
507 dmaengine_slave_config(device_data->dma.chan_cryp2mem, &cryp2mem);
508
493 init_completion(&device_data->dma.cryp_dma_complete); 509 init_completion(&device_data->dma.cryp_dma_complete);
494} 510}
495 511
@@ -1431,6 +1447,7 @@ static int ux500_cryp_probe(struct platform_device *pdev)
1431 goto out_kfree; 1447 goto out_kfree;
1432 } 1448 }
1433 1449
1450 device_data->phybase = res->start;
1434 device_data->base = ioremap(res->start, resource_size(res)); 1451 device_data->base = ioremap(res->start, resource_size(res));
1435 if (!device_data->base) { 1452 if (!device_data->base) {
1436 dev_err(dev, "[%s]: ioremap failed!", __func__); 1453 dev_err(dev, "[%s]: ioremap failed!", __func__);
@@ -1458,11 +1475,17 @@ static int ux500_cryp_probe(struct platform_device *pdev)
1458 goto out_regulator; 1475 goto out_regulator;
1459 } 1476 }
1460 1477
1478 ret = clk_prepare(device_data->clk);
1479 if (ret) {
1480 dev_err(dev, "[%s]: clk_prepare() failed!", __func__);
1481 goto out_clk;
1482 }
1483
1461 /* Enable device power (and clock) */ 1484 /* Enable device power (and clock) */
1462 ret = cryp_enable_power(device_data->dev, device_data, false); 1485 ret = cryp_enable_power(device_data->dev, device_data, false);
1463 if (ret) { 1486 if (ret) {
1464 dev_err(dev, "[%s]: cryp_enable_power() failed!", __func__); 1487 dev_err(dev, "[%s]: cryp_enable_power() failed!", __func__);
1465 goto out_clk; 1488 goto out_clk_unprepare;
1466 } 1489 }
1467 1490
1468 cryp_error = cryp_check(device_data); 1491 cryp_error = cryp_check(device_data);
@@ -1518,11 +1541,16 @@ static int ux500_cryp_probe(struct platform_device *pdev)
1518 goto out_power; 1541 goto out_power;
1519 } 1542 }
1520 1543
1544 dev_info(dev, "successfully registered\n");
1545
1521 return 0; 1546 return 0;
1522 1547
1523out_power: 1548out_power:
1524 cryp_disable_power(device_data->dev, device_data, false); 1549 cryp_disable_power(device_data->dev, device_data, false);
1525 1550
1551out_clk_unprepare:
1552 clk_unprepare(device_data->clk);
1553
1526out_clk: 1554out_clk:
1527 clk_put(device_data->clk); 1555 clk_put(device_data->clk);
1528 1556
@@ -1593,6 +1621,7 @@ static int ux500_cryp_remove(struct platform_device *pdev)
1593 dev_err(&pdev->dev, "[%s]: cryp_disable_power() failed", 1621 dev_err(&pdev->dev, "[%s]: cryp_disable_power() failed",
1594 __func__); 1622 __func__);
1595 1623
1624 clk_unprepare(device_data->clk);
1596 clk_put(device_data->clk); 1625 clk_put(device_data->clk);
1597 regulator_put(device_data->pwr_regulator); 1626 regulator_put(device_data->pwr_regulator);
1598 1627
diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h
index cd9351cb24df..be6eb54da40f 100644
--- a/drivers/crypto/ux500/hash/hash_alg.h
+++ b/drivers/crypto/ux500/hash/hash_alg.h
@@ -11,6 +11,7 @@
11#include <linux/bitops.h> 11#include <linux/bitops.h>
12 12
13#define HASH_BLOCK_SIZE 64 13#define HASH_BLOCK_SIZE 64
14#define HASH_DMA_FIFO 4
14#define HASH_DMA_ALIGN_SIZE 4 15#define HASH_DMA_ALIGN_SIZE 4
15#define HASH_DMA_PERFORMANCE_MIN_SIZE 1024 16#define HASH_DMA_PERFORMANCE_MIN_SIZE 1024
16#define HASH_BYTES_PER_WORD 4 17#define HASH_BYTES_PER_WORD 4
@@ -347,7 +348,8 @@ struct hash_req_ctx {
347 348
348/** 349/**
349 * struct hash_device_data - structure for a hash device. 350 * struct hash_device_data - structure for a hash device.
350 * @base: Pointer to the hardware base address. 351 * @base: Pointer to virtual base address of the hash device.
352 * @phybase: Pointer to physical memory location of the hash device.
351 * @list_node: For inclusion in klist. 353 * @list_node: For inclusion in klist.
352 * @dev: Pointer to the device dev structure. 354 * @dev: Pointer to the device dev structure.
353 * @ctx_lock: Spinlock for current_ctx. 355 * @ctx_lock: Spinlock for current_ctx.
@@ -361,6 +363,7 @@ struct hash_req_ctx {
361 */ 363 */
362struct hash_device_data { 364struct hash_device_data {
363 struct hash_register __iomem *base; 365 struct hash_register __iomem *base;
366 phys_addr_t phybase;
364 struct klist_node list_node; 367 struct klist_node list_node;
365 struct device *dev; 368 struct device *dev;
366 struct spinlock ctx_lock; 369 struct spinlock ctx_lock;
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index cf5508967539..9ca6fbb5e30d 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -122,6 +122,13 @@ static void hash_dma_setup_channel(struct hash_device_data *device_data,
122 struct device *dev) 122 struct device *dev)
123{ 123{
124 struct hash_platform_data *platform_data = dev->platform_data; 124 struct hash_platform_data *platform_data = dev->platform_data;
125 struct dma_slave_config conf = {
126 .direction = DMA_MEM_TO_DEV,
127 .dst_addr = device_data->phybase + HASH_DMA_FIFO,
128 .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
129 .dst_maxburst = 16,
130 };
131
125 dma_cap_zero(device_data->dma.mask); 132 dma_cap_zero(device_data->dma.mask);
126 dma_cap_set(DMA_SLAVE, device_data->dma.mask); 133 dma_cap_set(DMA_SLAVE, device_data->dma.mask);
127 134
@@ -131,6 +138,8 @@ static void hash_dma_setup_channel(struct hash_device_data *device_data,
131 platform_data->dma_filter, 138 platform_data->dma_filter,
132 device_data->dma.cfg_mem2hash); 139 device_data->dma.cfg_mem2hash);
133 140
141 dmaengine_slave_config(device_data->dma.chan_mem2hash, &conf);
142
134 init_completion(&device_data->dma.complete); 143 init_completion(&device_data->dma.complete);
135} 144}
136 145
@@ -1699,6 +1708,7 @@ static int ux500_hash_probe(struct platform_device *pdev)
1699 goto out_kfree; 1708 goto out_kfree;
1700 } 1709 }
1701 1710
1711 device_data->phybase = res->start;
1702 device_data->base = ioremap(res->start, resource_size(res)); 1712 device_data->base = ioremap(res->start, resource_size(res));
1703 if (!device_data->base) { 1713 if (!device_data->base) {
1704 dev_err(dev, "[%s] ioremap() failed!", 1714 dev_err(dev, "[%s] ioremap() failed!",
@@ -1726,11 +1736,17 @@ static int ux500_hash_probe(struct platform_device *pdev)
1726 goto out_regulator; 1736 goto out_regulator;
1727 } 1737 }
1728 1738
1739 ret = clk_prepare(device_data->clk);
1740 if (ret) {
1741 dev_err(dev, "[%s] clk_prepare() failed!", __func__);
1742 goto out_clk;
1743 }
1744
1729 /* Enable device power (and clock) */ 1745 /* Enable device power (and clock) */
1730 ret = hash_enable_power(device_data, false); 1746 ret = hash_enable_power(device_data, false);
1731 if (ret) { 1747 if (ret) {
1732 dev_err(dev, "[%s]: hash_enable_power() failed!", __func__); 1748 dev_err(dev, "[%s]: hash_enable_power() failed!", __func__);
1733 goto out_clk; 1749 goto out_clk_unprepare;
1734 } 1750 }
1735 1751
1736 ret = hash_check_hw(device_data); 1752 ret = hash_check_hw(device_data);
@@ -1756,12 +1772,15 @@ static int ux500_hash_probe(struct platform_device *pdev)
1756 goto out_power; 1772 goto out_power;
1757 } 1773 }
1758 1774
1759 dev_info(dev, "[%s] successfully probed\n", __func__); 1775 dev_info(dev, "successfully registered\n");
1760 return 0; 1776 return 0;
1761 1777
1762out_power: 1778out_power:
1763 hash_disable_power(device_data, false); 1779 hash_disable_power(device_data, false);
1764 1780
1781out_clk_unprepare:
1782 clk_unprepare(device_data->clk);
1783
1765out_clk: 1784out_clk:
1766 clk_put(device_data->clk); 1785 clk_put(device_data->clk);
1767 1786
@@ -1826,6 +1845,7 @@ static int ux500_hash_remove(struct platform_device *pdev)
1826 dev_err(dev, "[%s]: hash_disable_power() failed", 1845 dev_err(dev, "[%s]: hash_disable_power() failed",
1827 __func__); 1846 __func__);
1828 1847
1848 clk_unprepare(device_data->clk);
1829 clk_put(device_data->clk); 1849 clk_put(device_data->clk);
1830 regulator_put(device_data->regulator); 1850 regulator_put(device_data->regulator);
1831 1851
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 1734feec47b1..6ed775736853 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -17,6 +17,8 @@
17#include <linux/pm.h> 17#include <linux/pm.h>
18#include <linux/pm_runtime.h> 18#include <linux/pm_runtime.h>
19#include <linux/err.h> 19#include <linux/err.h>
20#include <linux/of.h>
21#include <linux/of_dma.h>
20#include <linux/amba/bus.h> 22#include <linux/amba/bus.h>
21#include <linux/regulator/consumer.h> 23#include <linux/regulator/consumer.h>
22#include <linux/platform_data/dma-ste-dma40.h> 24#include <linux/platform_data/dma-ste-dma40.h>
@@ -45,6 +47,9 @@
45#define D40_LCLA_LINK_PER_EVENT_GRP 128 47#define D40_LCLA_LINK_PER_EVENT_GRP 128
46#define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP 48#define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
47 49
50/* Max number of logical channels per physical channel */
51#define D40_MAX_LOG_CHAN_PER_PHY 32
52
48/* Attempts before giving up to trying to get pages that are aligned */ 53/* Attempts before giving up to trying to get pages that are aligned */
49#define MAX_LCLA_ALLOC_ATTEMPTS 256 54#define MAX_LCLA_ALLOC_ATTEMPTS 256
50 55
@@ -53,7 +58,50 @@
53#define D40_ALLOC_PHY (1 << 30) 58#define D40_ALLOC_PHY (1 << 30)
54#define D40_ALLOC_LOG_FREE 0 59#define D40_ALLOC_LOG_FREE 0
55 60
56#define MAX(a, b) (((a) < (b)) ? (b) : (a)) 61/* Reserved event lines for memcpy only. */
62#define DB8500_DMA_MEMCPY_EV_0 51
63#define DB8500_DMA_MEMCPY_EV_1 56
64#define DB8500_DMA_MEMCPY_EV_2 57
65#define DB8500_DMA_MEMCPY_EV_3 58
66#define DB8500_DMA_MEMCPY_EV_4 59
67#define DB8500_DMA_MEMCPY_EV_5 60
68
69static int dma40_memcpy_channels[] = {
70 DB8500_DMA_MEMCPY_EV_0,
71 DB8500_DMA_MEMCPY_EV_1,
72 DB8500_DMA_MEMCPY_EV_2,
73 DB8500_DMA_MEMCPY_EV_3,
74 DB8500_DMA_MEMCPY_EV_4,
75 DB8500_DMA_MEMCPY_EV_5,
76};
77
78/* Default configuration for physcial memcpy */
79struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
80 .mode = STEDMA40_MODE_PHYSICAL,
81 .dir = STEDMA40_MEM_TO_MEM,
82
83 .src_info.data_width = STEDMA40_BYTE_WIDTH,
84 .src_info.psize = STEDMA40_PSIZE_PHY_1,
85 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
86
87 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
88 .dst_info.psize = STEDMA40_PSIZE_PHY_1,
89 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
90};
91
92/* Default configuration for logical memcpy */
93struct stedma40_chan_cfg dma40_memcpy_conf_log = {
94 .mode = STEDMA40_MODE_LOGICAL,
95 .dir = STEDMA40_MEM_TO_MEM,
96
97 .src_info.data_width = STEDMA40_BYTE_WIDTH,
98 .src_info.psize = STEDMA40_PSIZE_LOG_1,
99 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
100
101 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
102 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
103 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
104};
57 105
58/** 106/**
59 * enum 40_command - The different commands and/or statuses. 107 * enum 40_command - The different commands and/or statuses.
@@ -171,6 +219,9 @@ static u32 d40_backup_regs_chan[] = {
171 D40_CHAN_REG_SDLNK, 219 D40_CHAN_REG_SDLNK,
172}; 220};
173 221
222#define BACKUP_REGS_SZ_MAX ((BACKUP_REGS_SZ_V4A > BACKUP_REGS_SZ_V4B) ? \
223 BACKUP_REGS_SZ_V4A : BACKUP_REGS_SZ_V4B)
224
174/** 225/**
175 * struct d40_interrupt_lookup - lookup table for interrupt handler 226 * struct d40_interrupt_lookup - lookup table for interrupt handler
176 * 227 *
@@ -534,7 +585,7 @@ struct d40_base {
534 resource_size_t lcpa_size; 585 resource_size_t lcpa_size;
535 struct kmem_cache *desc_slab; 586 struct kmem_cache *desc_slab;
536 u32 reg_val_backup[BACKUP_REGS_SZ]; 587 u32 reg_val_backup[BACKUP_REGS_SZ];
537 u32 reg_val_backup_v4[MAX(BACKUP_REGS_SZ_V4A, BACKUP_REGS_SZ_V4B)]; 588 u32 reg_val_backup_v4[BACKUP_REGS_SZ_MAX];
538 u32 *reg_val_backup_chan; 589 u32 *reg_val_backup_chan;
539 u16 gcc_pwr_off_mask; 590 u16 gcc_pwr_off_mask;
540 bool initialized; 591 bool initialized;
@@ -1257,21 +1308,17 @@ static void __d40_config_set_event(struct d40_chan *d40c,
1257static void d40_config_set_event(struct d40_chan *d40c, 1308static void d40_config_set_event(struct d40_chan *d40c,
1258 enum d40_events event_type) 1309 enum d40_events event_type)
1259{ 1310{
1311 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
1312
1260 /* Enable event line connected to device (or memcpy) */ 1313 /* Enable event line connected to device (or memcpy) */
1261 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || 1314 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
1262 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) { 1315 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1263 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1264
1265 __d40_config_set_event(d40c, event_type, event, 1316 __d40_config_set_event(d40c, event_type, event,
1266 D40_CHAN_REG_SSLNK); 1317 D40_CHAN_REG_SSLNK);
1267 }
1268
1269 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
1270 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1271 1318
1319 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM)
1272 __d40_config_set_event(d40c, event_type, event, 1320 __d40_config_set_event(d40c, event_type, event,
1273 D40_CHAN_REG_SDLNK); 1321 D40_CHAN_REG_SDLNK);
1274 }
1275} 1322}
1276 1323
1277static u32 d40_chan_has_events(struct d40_chan *d40c) 1324static u32 d40_chan_has_events(struct d40_chan *d40c)
@@ -1713,8 +1760,6 @@ static int d40_validate_conf(struct d40_chan *d40c,
1713 struct stedma40_chan_cfg *conf) 1760 struct stedma40_chan_cfg *conf)
1714{ 1761{
1715 int res = 0; 1762 int res = 0;
1716 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1717 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
1718 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL; 1763 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
1719 1764
1720 if (!conf->dir) { 1765 if (!conf->dir) {
@@ -1722,44 +1767,10 @@ static int d40_validate_conf(struct d40_chan *d40c,
1722 res = -EINVAL; 1767 res = -EINVAL;
1723 } 1768 }
1724 1769
1725 if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY && 1770 if ((is_log && conf->dev_type > d40c->base->num_log_chans) ||
1726 d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 && 1771 (!is_log && conf->dev_type > d40c->base->num_phy_chans) ||
1727 d40c->runtime_addr == 0) { 1772 (conf->dev_type < 0)) {
1728 1773 chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type);
1729 chan_err(d40c, "Invalid TX channel address (%d)\n",
1730 conf->dst_dev_type);
1731 res = -EINVAL;
1732 }
1733
1734 if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1735 d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1736 d40c->runtime_addr == 0) {
1737 chan_err(d40c, "Invalid RX channel address (%d)\n",
1738 conf->src_dev_type);
1739 res = -EINVAL;
1740 }
1741
1742 if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
1743 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
1744 chan_err(d40c, "Invalid dst\n");
1745 res = -EINVAL;
1746 }
1747
1748 if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
1749 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
1750 chan_err(d40c, "Invalid src\n");
1751 res = -EINVAL;
1752 }
1753
1754 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1755 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
1756 chan_err(d40c, "No event line\n");
1757 res = -EINVAL;
1758 }
1759
1760 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1761 (src_event_group != dst_event_group)) {
1762 chan_err(d40c, "Invalid event group\n");
1763 res = -EINVAL; 1774 res = -EINVAL;
1764 } 1775 }
1765 1776
@@ -1880,7 +1891,7 @@ out:
1880 1891
1881static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) 1892static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
1882{ 1893{
1883 int dev_type; 1894 int dev_type = d40c->dma_cfg.dev_type;
1884 int event_group; 1895 int event_group;
1885 int event_line; 1896 int event_line;
1886 struct d40_phy_res *phys; 1897 struct d40_phy_res *phys;
@@ -1895,13 +1906,11 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
1895 num_phy_chans = d40c->base->num_phy_chans; 1906 num_phy_chans = d40c->base->num_phy_chans;
1896 1907
1897 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { 1908 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1898 dev_type = d40c->dma_cfg.src_dev_type;
1899 log_num = 2 * dev_type; 1909 log_num = 2 * dev_type;
1900 is_src = true; 1910 is_src = true;
1901 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || 1911 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1902 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { 1912 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1903 /* dst event lines are used for logical memcpy */ 1913 /* dst event lines are used for logical memcpy */
1904 dev_type = d40c->dma_cfg.dst_dev_type;
1905 log_num = 2 * dev_type + 1; 1914 log_num = 2 * dev_type + 1;
1906 is_src = false; 1915 is_src = false;
1907 } else 1916 } else
@@ -2012,14 +2021,23 @@ static int d40_config_memcpy(struct d40_chan *d40c)
2012 dma_cap_mask_t cap = d40c->chan.device->cap_mask; 2021 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
2013 2022
2014 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) { 2023 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
2015 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log; 2024 d40c->dma_cfg = dma40_memcpy_conf_log;
2016 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY; 2025 d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
2017 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data-> 2026
2018 memcpy[d40c->chan.chan_id]; 2027 d40_log_cfg(&d40c->dma_cfg,
2028 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2019 2029
2020 } else if (dma_has_cap(DMA_MEMCPY, cap) && 2030 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
2021 dma_has_cap(DMA_SLAVE, cap)) { 2031 dma_has_cap(DMA_SLAVE, cap)) {
2022 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy; 2032 d40c->dma_cfg = dma40_memcpy_conf_phy;
2033
2034 /* Generate interrrupt at end of transfer or relink. */
2035 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
2036
2037 /* Generate interrupt on error. */
2038 d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
2039 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
2040
2023 } else { 2041 } else {
2024 chan_err(d40c, "No memcpy\n"); 2042 chan_err(d40c, "No memcpy\n");
2025 return -EINVAL; 2043 return -EINVAL;
@@ -2032,7 +2050,7 @@ static int d40_free_dma(struct d40_chan *d40c)
2032{ 2050{
2033 2051
2034 int res = 0; 2052 int res = 0;
2035 u32 event; 2053 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
2036 struct d40_phy_res *phy = d40c->phy_chan; 2054 struct d40_phy_res *phy = d40c->phy_chan;
2037 bool is_src; 2055 bool is_src;
2038 2056
@@ -2051,13 +2069,11 @@ static int d40_free_dma(struct d40_chan *d40c)
2051 } 2069 }
2052 2070
2053 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || 2071 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
2054 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { 2072 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM)
2055 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
2056 is_src = false; 2073 is_src = false;
2057 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { 2074 else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
2058 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
2059 is_src = true; 2075 is_src = true;
2060 } else { 2076 else {
2061 chan_err(d40c, "Unknown direction\n"); 2077 chan_err(d40c, "Unknown direction\n");
2062 return -EINVAL; 2078 return -EINVAL;
2063 } 2079 }
@@ -2098,7 +2114,7 @@ static bool d40_is_paused(struct d40_chan *d40c)
2098 unsigned long flags; 2114 unsigned long flags;
2099 void __iomem *active_reg; 2115 void __iomem *active_reg;
2100 u32 status; 2116 u32 status;
2101 u32 event; 2117 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
2102 2118
2103 spin_lock_irqsave(&d40c->lock, flags); 2119 spin_lock_irqsave(&d40c->lock, flags);
2104 2120
@@ -2119,10 +2135,8 @@ static bool d40_is_paused(struct d40_chan *d40c)
2119 2135
2120 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || 2136 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
2121 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { 2137 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
2122 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
2123 status = readl(chanbase + D40_CHAN_REG_SDLNK); 2138 status = readl(chanbase + D40_CHAN_REG_SDLNK);
2124 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { 2139 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
2125 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
2126 status = readl(chanbase + D40_CHAN_REG_SSLNK); 2140 status = readl(chanbase + D40_CHAN_REG_SSLNK);
2127 } else { 2141 } else {
2128 chan_err(d40c, "Unknown direction\n"); 2142 chan_err(d40c, "Unknown direction\n");
@@ -2253,24 +2267,6 @@ err:
2253 return NULL; 2267 return NULL;
2254} 2268}
2255 2269
2256static dma_addr_t
2257d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
2258{
2259 struct stedma40_platform_data *plat = chan->base->plat_data;
2260 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2261 dma_addr_t addr = 0;
2262
2263 if (chan->runtime_addr)
2264 return chan->runtime_addr;
2265
2266 if (direction == DMA_DEV_TO_MEM)
2267 addr = plat->dev_rx[cfg->src_dev_type];
2268 else if (direction == DMA_MEM_TO_DEV)
2269 addr = plat->dev_tx[cfg->dst_dev_type];
2270
2271 return addr;
2272}
2273
2274static struct dma_async_tx_descriptor * 2270static struct dma_async_tx_descriptor *
2275d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src, 2271d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
2276 struct scatterlist *sg_dst, unsigned int sg_len, 2272 struct scatterlist *sg_dst, unsigned int sg_len,
@@ -2297,14 +2293,10 @@ d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
2297 if (sg_next(&sg_src[sg_len - 1]) == sg_src) 2293 if (sg_next(&sg_src[sg_len - 1]) == sg_src)
2298 desc->cyclic = true; 2294 desc->cyclic = true;
2299 2295
2300 if (direction != DMA_TRANS_NONE) { 2296 if (direction == DMA_DEV_TO_MEM)
2301 dma_addr_t dev_addr = d40_get_dev_addr(chan, direction); 2297 src_dev_addr = chan->runtime_addr;
2302 2298 else if (direction == DMA_MEM_TO_DEV)
2303 if (direction == DMA_DEV_TO_MEM) 2299 dst_dev_addr = chan->runtime_addr;
2304 src_dev_addr = dev_addr;
2305 else if (direction == DMA_MEM_TO_DEV)
2306 dst_dev_addr = dev_addr;
2307 }
2308 2300
2309 if (chan_is_logical(chan)) 2301 if (chan_is_logical(chan))
2310 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst, 2302 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
@@ -2397,11 +2389,55 @@ static void d40_set_prio_realtime(struct d40_chan *d40c)
2397 2389
2398 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || 2390 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
2399 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) 2391 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
2400 __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true); 2392 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
2401 2393
2402 if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) || 2394 if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) ||
2403 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) 2395 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
2404 __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false); 2396 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
2397}
2398
2399#define D40_DT_FLAGS_MODE(flags) ((flags >> 0) & 0x1)
2400#define D40_DT_FLAGS_DIR(flags) ((flags >> 1) & 0x1)
2401#define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
2402#define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
2403
2404static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
2405 struct of_dma *ofdma)
2406{
2407 struct stedma40_chan_cfg cfg;
2408 dma_cap_mask_t cap;
2409 u32 flags;
2410
2411 memset(&cfg, 0, sizeof(struct stedma40_chan_cfg));
2412
2413 dma_cap_zero(cap);
2414 dma_cap_set(DMA_SLAVE, cap);
2415
2416 cfg.dev_type = dma_spec->args[0];
2417 flags = dma_spec->args[2];
2418
2419 switch (D40_DT_FLAGS_MODE(flags)) {
2420 case 0: cfg.mode = STEDMA40_MODE_LOGICAL; break;
2421 case 1: cfg.mode = STEDMA40_MODE_PHYSICAL; break;
2422 }
2423
2424 switch (D40_DT_FLAGS_DIR(flags)) {
2425 case 0:
2426 cfg.dir = STEDMA40_MEM_TO_PERIPH;
2427 cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2428 break;
2429 case 1:
2430 cfg.dir = STEDMA40_PERIPH_TO_MEM;
2431 cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2432 break;
2433 }
2434
2435 if (D40_DT_FLAGS_FIXED_CHAN(flags)) {
2436 cfg.phy_channel = dma_spec->args[1];
2437 cfg.use_fixed_channel = true;
2438 }
2439
2440 return dma_request_channel(cap, stedma40_filter, &cfg);
2405} 2441}
2406 2442
2407/* DMA ENGINE functions */ 2443/* DMA ENGINE functions */
@@ -2433,23 +2469,21 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
2433 } 2469 }
2434 2470
2435 pm_runtime_get_sync(d40c->base->dev); 2471 pm_runtime_get_sync(d40c->base->dev);
2436 /* Fill in basic CFG register values */
2437 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
2438 &d40c->dst_def_cfg, chan_is_logical(d40c));
2439 2472
2440 d40_set_prio_realtime(d40c); 2473 d40_set_prio_realtime(d40c);
2441 2474
2442 if (chan_is_logical(d40c)) { 2475 if (chan_is_logical(d40c)) {
2443 d40_log_cfg(&d40c->dma_cfg,
2444 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2445
2446 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) 2476 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
2447 d40c->lcpa = d40c->base->lcpa_base + 2477 d40c->lcpa = d40c->base->lcpa_base +
2448 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE; 2478 d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
2449 else 2479 else
2450 d40c->lcpa = d40c->base->lcpa_base + 2480 d40c->lcpa = d40c->base->lcpa_base +
2451 d40c->dma_cfg.dst_dev_type * 2481 d40c->dma_cfg.dev_type *
2452 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA; 2482 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
2483
2484 /* Unmask the Global Interrupt Mask. */
2485 d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
2486 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
2453 } 2487 }
2454 2488
2455 dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n", 2489 dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
@@ -2710,15 +2744,8 @@ static int d40_set_runtime_config(struct dma_chan *chan,
2710 dst_maxburst = config->dst_maxburst; 2744 dst_maxburst = config->dst_maxburst;
2711 2745
2712 if (config->direction == DMA_DEV_TO_MEM) { 2746 if (config->direction == DMA_DEV_TO_MEM) {
2713 dma_addr_t dev_addr_rx =
2714 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2715
2716 config_addr = config->src_addr; 2747 config_addr = config->src_addr;
2717 if (dev_addr_rx) 2748
2718 dev_dbg(d40c->base->dev,
2719 "channel has a pre-wired RX address %08x "
2720 "overriding with %08x\n",
2721 dev_addr_rx, config_addr);
2722 if (cfg->dir != STEDMA40_PERIPH_TO_MEM) 2749 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2723 dev_dbg(d40c->base->dev, 2750 dev_dbg(d40c->base->dev,
2724 "channel was not configured for peripheral " 2751 "channel was not configured for peripheral "
@@ -2733,15 +2760,8 @@ static int d40_set_runtime_config(struct dma_chan *chan,
2733 dst_maxburst = src_maxburst; 2760 dst_maxburst = src_maxburst;
2734 2761
2735 } else if (config->direction == DMA_MEM_TO_DEV) { 2762 } else if (config->direction == DMA_MEM_TO_DEV) {
2736 dma_addr_t dev_addr_tx =
2737 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2738
2739 config_addr = config->dst_addr; 2763 config_addr = config->dst_addr;
2740 if (dev_addr_tx) 2764
2741 dev_dbg(d40c->base->dev,
2742 "channel has a pre-wired TX address %08x "
2743 "overriding with %08x\n",
2744 dev_addr_tx, config_addr);
2745 if (cfg->dir != STEDMA40_MEM_TO_PERIPH) 2765 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2746 dev_dbg(d40c->base->dev, 2766 dev_dbg(d40c->base->dev,
2747 "channel was not configured for memory " 2767 "channel was not configured for memory "
@@ -2761,6 +2781,11 @@ static int d40_set_runtime_config(struct dma_chan *chan,
2761 return -EINVAL; 2781 return -EINVAL;
2762 } 2782 }
2763 2783
2784 if (config_addr <= 0) {
2785 dev_err(d40c->base->dev, "no address supplied\n");
2786 return -EINVAL;
2787 }
2788
2764 if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) { 2789 if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
2765 dev_err(d40c->base->dev, 2790 dev_err(d40c->base->dev,
2766 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n", 2791 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
@@ -2795,8 +2820,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
2795 if (chan_is_logical(d40c)) 2820 if (chan_is_logical(d40c))
2796 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); 2821 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2797 else 2822 else
2798 d40_phy_cfg(cfg, &d40c->src_def_cfg, 2823 d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);
2799 &d40c->dst_def_cfg, false);
2800 2824
2801 /* These settings will take precedence later */ 2825 /* These settings will take precedence later */
2802 d40c->runtime_addr = config_addr; 2826 d40c->runtime_addr = config_addr;
@@ -2927,7 +2951,7 @@ static int __init d40_dmaengine_init(struct d40_base *base,
2927 } 2951 }
2928 2952
2929 d40_chan_init(base, &base->dma_memcpy, base->log_chans, 2953 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2930 base->num_log_chans, base->plat_data->memcpy_len); 2954 base->num_log_chans, ARRAY_SIZE(dma40_memcpy_channels));
2931 2955
2932 dma_cap_zero(base->dma_memcpy.cap_mask); 2956 dma_cap_zero(base->dma_memcpy.cap_mask);
2933 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); 2957 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
@@ -3121,7 +3145,7 @@ static int __init d40_phy_res_init(struct d40_base *base)
3121 3145
3122static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) 3146static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
3123{ 3147{
3124 struct stedma40_platform_data *plat_data; 3148 struct stedma40_platform_data *plat_data = pdev->dev.platform_data;
3125 struct clk *clk = NULL; 3149 struct clk *clk = NULL;
3126 void __iomem *virtbase = NULL; 3150 void __iomem *virtbase = NULL;
3127 struct resource *res = NULL; 3151 struct resource *res = NULL;
@@ -3187,8 +3211,10 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
3187 * DB8540v1 has revision 4 3211 * DB8540v1 has revision 4
3188 */ 3212 */
3189 rev = AMBA_REV_BITS(pid); 3213 rev = AMBA_REV_BITS(pid);
3190 3214 if (rev < 2) {
3191 plat_data = pdev->dev.platform_data; 3215 d40_err(&pdev->dev, "hardware revision: %d is not supported", rev);
3216 goto failure;
3217 }
3192 3218
3193 /* The number of physical channels on this HW */ 3219 /* The number of physical channels on this HW */
3194 if (plat_data->num_of_phy_chans) 3220 if (plat_data->num_of_phy_chans)
@@ -3196,26 +3222,14 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
3196 else 3222 else
3197 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4; 3223 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
3198 3224
3199 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x with %d physical channels\n", 3225 num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
3200 rev, res->start, num_phy_chans);
3201
3202 if (rev < 2) {
3203 d40_err(&pdev->dev, "hardware revision: %d is not supported",
3204 rev);
3205 goto failure;
3206 }
3207 3226
3208 /* Count the number of logical channels in use */ 3227 dev_info(&pdev->dev,
3209 for (i = 0; i < plat_data->dev_len; i++) 3228 "hardware rev: %d @ 0x%x with %d physical and %d logical channels\n",
3210 if (plat_data->dev_rx[i] != 0) 3229 rev, res->start, num_phy_chans, num_log_chans);
3211 num_log_chans++;
3212
3213 for (i = 0; i < plat_data->dev_len; i++)
3214 if (plat_data->dev_tx[i] != 0)
3215 num_log_chans++;
3216 3230
3217 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) + 3231 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
3218 (num_phy_chans + num_log_chans + plat_data->memcpy_len) * 3232 (num_phy_chans + num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) *
3219 sizeof(struct d40_chan), GFP_KERNEL); 3233 sizeof(struct d40_chan), GFP_KERNEL);
3220 3234
3221 if (base == NULL) { 3235 if (base == NULL) {
@@ -3276,17 +3290,11 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
3276 if (!base->lookup_phy_chans) 3290 if (!base->lookup_phy_chans)
3277 goto failure; 3291 goto failure;
3278 3292
3279 if (num_log_chans + plat_data->memcpy_len) { 3293 base->lookup_log_chans = kzalloc(num_log_chans *
3280 /* 3294 sizeof(struct d40_chan *),
3281 * The max number of logical channels are event lines for all 3295 GFP_KERNEL);
3282 * src devices and dst devices 3296 if (!base->lookup_log_chans)
3283 */ 3297 goto failure;
3284 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
3285 sizeof(struct d40_chan *),
3286 GFP_KERNEL);
3287 if (!base->lookup_log_chans)
3288 goto failure;
3289 }
3290 3298
3291 base->reg_val_backup_chan = kmalloc(base->num_phy_chans * 3299 base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
3292 sizeof(d40_backup_regs_chan), 3300 sizeof(d40_backup_regs_chan),
@@ -3470,17 +3478,52 @@ failure:
3470 return ret; 3478 return ret;
3471} 3479}
3472 3480
3481static int __init d40_of_probe(struct platform_device *pdev,
3482 struct device_node *np)
3483{
3484 struct stedma40_platform_data *pdata;
3485
3486 /*
3487 * FIXME: Fill in this routine as more support is added.
3488 * First platform enabled (u8500) doens't need any extra
3489 * properties to run, so this is fairly sparce currently.
3490 */
3491
3492 pdata = devm_kzalloc(&pdev->dev,
3493 sizeof(struct stedma40_platform_data),
3494 GFP_KERNEL);
3495 if (!pdata)
3496 return -ENOMEM;
3497
3498 pdev->dev.platform_data = pdata;
3499
3500 return 0;
3501}
3502
3473static int __init d40_probe(struct platform_device *pdev) 3503static int __init d40_probe(struct platform_device *pdev)
3474{ 3504{
3505 struct stedma40_platform_data *plat_data = pdev->dev.platform_data;
3506 struct device_node *np = pdev->dev.of_node;
3475 int err; 3507 int err;
3476 int ret = -ENOENT; 3508 int ret = -ENOENT;
3477 struct d40_base *base; 3509 struct d40_base *base = NULL;
3478 struct resource *res = NULL; 3510 struct resource *res = NULL;
3479 int num_reserved_chans; 3511 int num_reserved_chans;
3480 u32 val; 3512 u32 val;
3481 3513
3482 base = d40_hw_detect_init(pdev); 3514 if (!plat_data) {
3515 if (np) {
3516 if(d40_of_probe(pdev, np)) {
3517 ret = -ENOMEM;
3518 goto failure;
3519 }
3520 } else {
3521 d40_err(&pdev->dev, "No pdata or Device Tree provided\n");
3522 goto failure;
3523 }
3524 }
3483 3525
3526 base = d40_hw_detect_init(pdev);
3484 if (!base) 3527 if (!base)
3485 goto failure; 3528 goto failure;
3486 3529
@@ -3601,6 +3644,13 @@ static int __init d40_probe(struct platform_device *pdev)
3601 3644
3602 d40_hw_init(base); 3645 d40_hw_init(base);
3603 3646
3647 if (np) {
3648 err = of_dma_controller_register(np, d40_xlate, NULL);
3649 if (err && err != -ENODEV)
3650 dev_err(&pdev->dev,
3651 "could not register of_dma_controller\n");
3652 }
3653
3604 dev_info(base->dev, "initialized\n"); 3654 dev_info(base->dev, "initialized\n");
3605 return 0; 3655 return 0;
3606 3656
@@ -3654,11 +3704,17 @@ failure:
3654 return ret; 3704 return ret;
3655} 3705}
3656 3706
3707static const struct of_device_id d40_match[] = {
3708 { .compatible = "stericsson,dma40", },
3709 {}
3710};
3711
3657static struct platform_driver d40_driver = { 3712static struct platform_driver d40_driver = {
3658 .driver = { 3713 .driver = {
3659 .owner = THIS_MODULE, 3714 .owner = THIS_MODULE,
3660 .name = D40_NAME, 3715 .name = D40_NAME,
3661 .pm = DMA40_PM_OPS, 3716 .pm = DMA40_PM_OPS,
3717 .of_match_table = d40_match,
3662 }, 3718 },
3663}; 3719};
3664 3720
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index 7180e0d41722..ab5a2a706f7a 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -50,68 +50,58 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
50 50
51} 51}
52 52
53/* Sets up SRC and DST CFG register for both logical and physical channels */ 53void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
54void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
55 u32 *src_cfg, u32 *dst_cfg, bool is_log)
56{ 54{
57 u32 src = 0; 55 u32 src = 0;
58 u32 dst = 0; 56 u32 dst = 0;
59 57
60 if (!is_log) { 58 if ((cfg->dir == STEDMA40_PERIPH_TO_MEM) ||
61 /* Physical channel */ 59 (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
62 if ((cfg->dir == STEDMA40_PERIPH_TO_MEM) || 60 /* Set master port to 1 */
63 (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) { 61 src |= 1 << D40_SREG_CFG_MST_POS;
64 /* Set master port to 1 */ 62 src |= D40_TYPE_TO_EVENT(cfg->dev_type);
65 src |= 1 << D40_SREG_CFG_MST_POS; 63
66 src |= D40_TYPE_TO_EVENT(cfg->src_dev_type); 64 if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
67 65 src |= 1 << D40_SREG_CFG_PHY_TM_POS;
68 if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL) 66 else
69 src |= 1 << D40_SREG_CFG_PHY_TM_POS; 67 src |= 3 << D40_SREG_CFG_PHY_TM_POS;
70 else 68 }
71 src |= 3 << D40_SREG_CFG_PHY_TM_POS; 69 if ((cfg->dir == STEDMA40_MEM_TO_PERIPH) ||
72 } 70 (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
73 if ((cfg->dir == STEDMA40_MEM_TO_PERIPH) || 71 /* Set master port to 1 */
74 (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) { 72 dst |= 1 << D40_SREG_CFG_MST_POS;
75 /* Set master port to 1 */ 73 dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
76 dst |= 1 << D40_SREG_CFG_MST_POS; 74
77 dst |= D40_TYPE_TO_EVENT(cfg->dst_dev_type); 75 if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
78 76 dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
79 if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL) 77 else
80 dst |= 1 << D40_SREG_CFG_PHY_TM_POS; 78 dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
81 else 79 }
82 dst |= 3 << D40_SREG_CFG_PHY_TM_POS; 80 /* Interrupt on end of transfer for destination */
83 } 81 dst |= 1 << D40_SREG_CFG_TIM_POS;
84 /* Interrupt on end of transfer for destination */ 82
85 dst |= 1 << D40_SREG_CFG_TIM_POS; 83 /* Generate interrupt on error */
86 84 src |= 1 << D40_SREG_CFG_EIM_POS;
87 /* Generate interrupt on error */ 85 dst |= 1 << D40_SREG_CFG_EIM_POS;
88 src |= 1 << D40_SREG_CFG_EIM_POS; 86
89 dst |= 1 << D40_SREG_CFG_EIM_POS; 87 /* PSIZE */
90 88 if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
91 /* PSIZE */ 89 src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
92 if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) { 90 src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
93 src |= 1 << D40_SREG_CFG_PHY_PEN_POS; 91 }
94 src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS; 92 if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
95 } 93 dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
96 if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) { 94 dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
97 dst |= 1 << D40_SREG_CFG_PHY_PEN_POS; 95 }
98 dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS; 96
99 } 97 /* Element size */
100 98 src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
101 /* Element size */ 99 dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
102 src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS; 100
103 dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS; 101 /* Set the priority bit to high for the physical channel */
104 102 if (cfg->high_priority) {
105 /* Set the priority bit to high for the physical channel */ 103 src |= 1 << D40_SREG_CFG_PRI_POS;
106 if (cfg->high_priority) { 104 dst |= 1 << D40_SREG_CFG_PRI_POS;
107 src |= 1 << D40_SREG_CFG_PRI_POS;
108 dst |= 1 << D40_SREG_CFG_PRI_POS;
109 }
110
111 } else {
112 /* Logical channel */
113 dst |= 1 << D40_SREG_CFG_LOG_GIM_POS;
114 src |= 1 << D40_SREG_CFG_LOG_GIM_POS;
115 } 105 }
116 106
117 if (cfg->src_info.big_endian) 107 if (cfg->src_info.big_endian)
diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h
index fdde8ef77542..1b47312bc574 100644
--- a/drivers/dma/ste_dma40_ll.h
+++ b/drivers/dma/ste_dma40_ll.h
@@ -432,8 +432,7 @@ enum d40_lli_flags {
432 432
433void d40_phy_cfg(struct stedma40_chan_cfg *cfg, 433void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
434 u32 *src_cfg, 434 u32 *src_cfg,
435 u32 *dst_cfg, 435 u32 *dst_cfg);
436 bool is_log);
437 436
438void d40_log_cfg(struct stedma40_chan_cfg *cfg, 437void d40_log_cfg(struct stedma40_chan_cfg *cfg,
439 u32 *lcsp1, 438 u32 *lcsp1,
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index 4b781014b0a0..288dc2420ee6 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -86,7 +86,7 @@ enum stedma40_xfer_dir {
86 86
87 87
88/** 88/**
89 * struct stedma40_chan_cfg - dst/src channel configuration 89 * struct stedma40_half_channel_info - dst/src channel configuration
90 * 90 *
91 * @big_endian: true if the src/dst should be read as big endian 91 * @big_endian: true if the src/dst should be read as big endian
92 * @data_width: Data width of the src/dst hardware 92 * @data_width: Data width of the src/dst hardware
@@ -109,8 +109,7 @@ struct stedma40_half_channel_info {
109 * version 3+, i.e DB8500v2+ 109 * version 3+, i.e DB8500v2+
110 * @mode: channel mode: physical, logical, or operation 110 * @mode: channel mode: physical, logical, or operation
111 * @mode_opt: options for the chosen channel mode 111 * @mode_opt: options for the chosen channel mode
112 * @src_dev_type: Src device type 112 * @dev_type: src/dst device type (driver uses dir to figure out which)
113 * @dst_dev_type: Dst device type
114 * @src_info: Parameters for dst half channel 113 * @src_info: Parameters for dst half channel
115 * @dst_info: Parameters for dst half channel 114 * @dst_info: Parameters for dst half channel
116 * @use_fixed_channel: if true, use physical channel specified by phy_channel 115 * @use_fixed_channel: if true, use physical channel specified by phy_channel
@@ -126,8 +125,7 @@ struct stedma40_chan_cfg {
126 bool realtime; 125 bool realtime;
127 enum stedma40_mode mode; 126 enum stedma40_mode mode;
128 enum stedma40_mode_opt mode_opt; 127 enum stedma40_mode_opt mode_opt;
129 int src_dev_type; 128 int dev_type;
130 int dst_dev_type;
131 struct stedma40_half_channel_info src_info; 129 struct stedma40_half_channel_info src_info;
132 struct stedma40_half_channel_info dst_info; 130 struct stedma40_half_channel_info dst_info;
133 131
@@ -138,13 +136,8 @@ struct stedma40_chan_cfg {
138/** 136/**
139 * struct stedma40_platform_data - Configuration struct for the dma device. 137 * struct stedma40_platform_data - Configuration struct for the dma device.
140 * 138 *
141 * @dev_len: length of dev_tx and dev_rx
142 * @dev_tx: mapping between destination event line and io address 139 * @dev_tx: mapping between destination event line and io address
143 * @dev_rx: mapping between source event line and io address 140 * @dev_rx: mapping between source event line and io address
144 * @memcpy: list of memcpy event lines
145 * @memcpy_len: length of memcpy
146 * @memcpy_conf_phy: default configuration of physical channel memcpy
147 * @memcpy_conf_log: default configuration of logical channel memcpy
148 * @disabled_channels: A vector, ending with -1, that marks physical channels 141 * @disabled_channels: A vector, ending with -1, that marks physical channels
149 * that are for different reasons not available for the driver. 142 * that are for different reasons not available for the driver.
150 * @soft_lli_chans: A vector, that marks physical channels will use LLI by SW 143 * @soft_lli_chans: A vector, that marks physical channels will use LLI by SW
@@ -159,13 +152,6 @@ struct stedma40_chan_cfg {
159 * for 'multiple of 4' channels, like 8. 152 * for 'multiple of 4' channels, like 8.
160 */ 153 */
161struct stedma40_platform_data { 154struct stedma40_platform_data {
162 u32 dev_len;
163 const dma_addr_t *dev_tx;
164 const dma_addr_t *dev_rx;
165 int *memcpy;
166 u32 memcpy_len;
167 struct stedma40_chan_cfg *memcpy_conf_phy;
168 struct stedma40_chan_cfg *memcpy_conf_log;
169 int disabled_channels[STEDMA40_MAX_PHYS]; 155 int disabled_channels[STEDMA40_MAX_PHYS];
170 int *soft_lli_chans; 156 int *soft_lli_chans;
171 int num_of_soft_lli_chans; 157 int num_of_soft_lli_chans;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 01:29:01 -0500